HS-82C12RH Radiation Hardened 8-Bit Input/Output Port March 1996 Features Functional Diagram • Devices QML Qualified in Accordance with MIL-PRF-38535 • Detailed Electrical and Screening Requirements are Contained in SMD# 5962-95818 and Intersil’ QM Plan - Radiation Hardened CMOS Process - Total Dose 1 x 105 RAD (Si) - Transient Upset > 1 x 108 RAD (Si)/s - Latch-Up Immune EPI-CMOS > 1 x 1012 RAD (Si)/s • • • • • • • • • • • DS1 CONTROL AND DEVICE SELECT LOGIC DS2 STB CLR SERVICE REQUEST F.F. 2 INT 3 MD Low Power Dissipation High Noise Immunity Single Power Supply +5V Low Input Load Current 8-Bit Data Register and Buffer Asynchronous Register Clear Service Request Flip-Flop for Interrupt Generation Three-State Outputs Bus-Compatible with HS-80C85RH CPU Electrically Equivalent to Sandia SA3026 Military Temperature Range -55oC to +125oC DI0-7 DATA LATCH AND BUFFER (8) DO0-7 Pin Description PIN DESCRIPTION DI0-DI7 Data In DO0-DO7 Data Out DS1, DS2 Device Select Description MD Mode The Intersil HS-82C12RH is a radiation hardened 8-bit input/ output port designed for use with the HS-80C85RH radiation hardened microprocessor. It is manufactured using a selfaligned, junction-isolated EPI-CMOS process and features three-state output buffers and device selection and control logic. A service request flip-flop is included for the generation and control of interrupts to the microprocessor. The device can be used in implement many of the peripheral and input/output functions of a microcomputer system. The HS-82C12RH is pinout- and function- compatible with industry-standard 8212 devices. STB Strobe INT Interrupt CLR Clear Ordering Information TEMPERATURE RANGE SCREENING LEVEL PACKAGE 5962R9581801QJC -55oC to +125oC MIL-PRF-38535 Level Q 24 Lead SBDIP 5962R9581801QXC -55oC to +125oC MIL-PRF-38535 Level Q 24 Lead Ceramic Flatpack 5962R9581801VJC -55oC to +125oC MIL-PRF-38535 Level V 24 Lead SBDIP 5962R9581801VXC -55oC to +125oC MIL-PRF-38535 Level V 24 Lead Ceramic Flatpack HS1-82C12RH/Sample +25oC Sample 24 Lead SBDIP HS9-82C12RH/Sample +25oC Sample 24 Lead Ceramic Flatpack DB NA PART NUMBER CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 1 Spec Number File Number 518063 3041.2 HS-82C12RH Pinouts 24 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T24 TOP VIEW DS1 1 24 VDD MD 2 23 INT DI0 3 22 DI7 DO0 4 21 DO7 DI1 5 20 DI6 DO1 6 19 DO6 DI2 7 18 DI5 DO2 8 17 DO5 DI3 9 16 DI4 DO3 10 15 DO4 STB 11 14 CLR GND 12 13 DS2 24 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F24 TOP VIEW DS1 1 MD 2 DI0 3 DO0 4 DI1 DO1 DI2 5 DO2 8 DI3 DO3 9 STB GND 11 24 23 22 21 20 19 18 17 16 15 14 13 6 7 10 12 VDD INT DI7 DO7 DI6 DO6 DI5 DO5 DI4 DO4 CLR DS2 Spec Number 2 518063 Specifications HS-82C12RH Absolute Maximum Ratings Reliability Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.3V to VDD+0.3V Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance θJA θJC SBDIP Package . . . . . . . . . . . . . . . . . . . . 55oC/W 14oC/W Ceramic Flatpack Package . . . . . . . . . . . 74oC/W 13oC/W Maximum Package Power Dissipation at +125oC Ambient SBDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.91W Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W If device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: SBDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18.2mW/C Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . .13.5mW/C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to +1.0V Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VDD -1V to VDD TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER SYMBOL GROUP A SUBGROUPS CONDITIONS TEMPERATURE MIN MAX UNITS High Input Leakage Current IIH VDD = 5.25V, VIN = 0V, Pin under test = 5.25V 1, 2, 3 -55oC, +25oC, +125oC - 1 µA Low Input Leakage Current IIL VDD = 5.25V, VIN = 5.25V, Pin under test = 0V 1, 2, 3 -55oC, +25oC, +125oC -1 - µA Low Output Voltage VOL VDD = 5.25V, IOL = 2mA 1, 2, 3 -55oC, +25oC, +125oC - 0.5 V High Output Voltage VOH VDD = 4.75V, IOH = -2mA 1, 2, 3 -55oC, +25oC, +125oC 4.25 - V Static Current SIDD VDD = 5.25V, VIN = GND 1, 2, 3 -55oC, +25oC, +125oC - 100 µA 7, 8A, 8B -55oC, +25oC, +125oC - - - Functional Tests FT VDD = 4.75V and 5.25V, VIH = VDD-1.0V, VIL = 1.0V NOTE: All devices are guaranteed at worst case limits and over radiation. TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS SYMBOL GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS Data to Output Delay TPD 9, 10, 11 -55oC, +25oC, +125oC - 105 ns Write Enable to Output Delay TWE 9, 10, 11 -55oC, +25oC, +125oC - 200 ns Reset to Output Delay TR 9, 10, 11 -55oC, +25oC, +125oC - 145 ns Set to Output Delay TS 9, 10, 11 -55oC, +25oC, +125oC - 100 ns Clear to Output Delay TC 9, 10, 11 -55oC, +25oC, +125oC - 135 ns Output Enable Time TE 9, 10, 11 -55oC, +25oC, +125oC - 125 ns Output Disable Time TD 9, 10, 11 -55oC, +25oC, +125oC - 85 ns PARAMETER NOTE: 1. Output Timings are measured with the following conditions: CL = 100pF, VIH = 3.75V, and VIL = 1.0V Spec Number 3 518063 Specifications HS-82C12RH TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Input Capacitance Output Capacitance SYMBOL GROUP A SUBGROUPS CONDITIONS TEMPERATURE MIN MAX UNITS CIN VDD = Open, f = 1MHz, All measurements referenced to device ground TA = +25oC - 8 pF COUT VDD = Open, f = 1MHz, All measurements referenced to device ground TA = +25oC - 8 pF Pulse Width TPW VDD = 4.75, VIH = 3.75, VIL = 1.0 9, 10, 11 -55oC, +25oC, +125oC - 50 ns Data Set Up Time TSET VDD = 4.75, VIH = 3.75, VIL = 1.0 9, 10, 11 -55oC, +25oC, +125oC - 30 ns TH VDD = 4.75, VIH = 3.75, VIL = 1.0 9, 10, 11 -55oC, +25oC, +125oC - 40 ns Data Hold Time NOTE: The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design release and upon design changes which would affect these characteristics. TABLE 4. POST 100K RAD ELECTRICAL PERFORMANCE CHARACTERISTICS NOTE: The Post Irradiation test conditions and limits are the same as those listed in Table 1 and Table 2. Spec Number 4 518063 HS-82C12RH Timing Waveforms (DS, • DS2) tE 0.5VDD tD VOH OUTPUT VOL 0.5VDD FIGURE 1. READ TIMING DATA tPW MD OR (DS, • DS2) tH tWE OUTPUT FIGURE 2. WRITE TIMING DATA tSET tH STB OR (DS, • DS2) tPD OUTPUT FIGURE 3. DATA SETUP, HOLD, PROPAGATION DELAY TIMING tPW STB tPW (DS, • DS2) tR tS INT FIGURE 4. INTERRUPT TIMING tPW CLR tC DO FIGURE 5. CLEAR TIMING Spec Number 5 518063 HS-82C12RH Functional Description Data Latch Mode The data latch is comprised of eight “D” type flip-flops. The output of each flip-flop will follow the corresponding data input (DI0 - DI7) when the clock (C) is high. The clock input is level sensitive and the data becomes latched when the clock returns low. the mode input (MD) is used to control the state of the output buffer and to determine the source of the data latch clock (C). When MD is high, the output buffers are enabled and the source of the data latch clock (C) is the device select logic (DS1 • DS2). An asynchronous reset (CLR) is used to clear the latched data. Since the clock (C) overrides the reset (CLR), the data must be in the latched state in order to clear the flip-flops. If the data is not latched (i.e. clock is high) when CLR goes low, then the Q outputs of the data latch will continue to follow the data input, overriding the reset signal. When MD is low, the state of the output buffer is controlled by the device select logic (DS1 • DS2) and the source of the data latch clock is the strobe (STB) input. Strobe The strobe input (STB) is used as the data latch clock (C) when the mode input (MD) is low. The service request flipflop is synchronously set on the negative going edge of STB. Output Buffer Three-state buffers are used to provide output drive for the data latch. A high level on the “output buffer enable” control line enables the buffer outputs. When “output buffer enable” is low the buffer outputs are forced to the high-impedance state. Service Request Flip-Flop The service request flip-flop is to generate interrupts to microcomputer systems. It is negative edge triggered and asynchronously cleared (reset). The output of the service request flip-flop is AND-gated with the device select logic (DS1 • DS2). The output of the AND gate is the active low interrupt (INT) signal. Device Select Logic The inputs DS1 and DS2 are used for device selection. When DS1 is low and DS2 is high, the device is selected. The output buffers are enabled and the service request flipflop is asynchronously cleared when the device is selected. Spec Number 6 518063 HS-82C12RH Logic Diagram INT DEVICE DS1 23 DATA OUT ENABLE SELECT 13 LATCH RESET DI0 DS2 3 S STB DO0 D E D Q C Q 11 Q Q TSB Q Q TSB Q Q TSB Q Q TSB Q Q TSB Q Q TSB Q Q TSB Q Q TSB 4 R SERVICE REQUEST FLIP-FLOP DI1 DO1 D E 5 CLR 6 R 14 DI2 DO2 D E 7 8 R LATCH CLOCK DI3 DO3 D E MD 9 2 10 R DI4 DO4 D E 16 15 R DI5 DO5 D E 18 17 R DI6 DO6 D E 20 19 R DI7 DO7 D E 22 21 R TRUTH TABLE 1. DATA OUT STB MD DS1 • DS2 0 0 0 1 0 0 TRUTH TABLE 2. INT CLR DS1 • DS2 STB Q* INT High Z State 0 RESET 0 0 0 1 0 High Z State 1 0 0 0 1 1 0 Data Latch 1 0 1 0 1 1 0 Data Latch 1 1 RESET 0 0 0 0 0 1 Data Latch 1 0 0 0 1 1 0 1 Data In 0 1 1 Data In 1 1 1 Data In DATA OUT EQUALS * Internal Service Request Flip-Flop Spec Number 7 518063 HS-82C12RH Metallization Topology DIE DIMENSIONS: 90 x 76 x 14 ± 1mils METALLIZATION: Type: AlSi Thickness: 11kÅ ± 2kÅ GLASSIVATION: Type: SiO2 Thickness: 8kÅ ± 1kÅ Metallization Mask Layout (23) INT (24) VDD (1) DS1 (2) MD (3) DI0 HS-82C12RH (22) DI7 DO0 (4) (21) DO7 DI1 (5) (20) DI6 DO1 (6) (19) DO6 DI2 (7) (18) DI5 DO2 (8) (17) DO5 DI3 (9) (16) DI4 CLR (14) DS2 (13) GND (12) STB (11) DO3 (10) (15) DO4 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Spec Number 8 518063