Design and Implementation of a fixed-frequency Adapter with Very Low Power Consumption Agenda • New ENERGY STAR® requirements • Needed features to meet the new specification • New controller family NCP1237/38/87/88 • Design step 1: Power stage • Design step 2: Set the compensations • Design step 3: No Load Input Power • Design step 4: Magnetics • Design step 5: EMI • Preliminary demo board example • Conclusion 2 EPA 2.0 (External Power Supplies) (was > 0.84 in previous version 1.1) (< 0.5 W in 1.1) (< 0.75 W in 1.1) 3 EPS 5.0 (ENERGY STAR® Program Requirements for Computers) • • Defines ETEC for different types of products as a Typical Energy Consumption For the desktop and notebook product categories TEC will be determined by the following formula: ETEC = (8760/1000) * (Poff * Toff + Psleep * Tsleep + Pidle * Tidle) • where all Px are power values in watts, all Tx are Time values in % of year, and the TEC ETEC is in units of kWh and represents annual energy consumption based on mode weightings • The light load efficiency and no load consumption is more important ETEC requirement desktops and notebooks Desktops and Integrated Computers (kWh) TEC (kWh) • 4 Category A: ≤ 148.0 Category B: ≤ 175.0 Category C: ≤ 209.0 Category D: ≤ 234.0 Notebook Computers (kWh) Category A: ≤ 40.0 Category B: ≤ 53.0 Category C: ≤ 88.5 Effective from July 1, 2009 (except: game consoles from July 1, 2010) Agenda • New ENERGY STAR® requirements • Needed features to meet the new specification • New controller family NCP1237/38/87/88 • Design step 1: Power stage • Design step 2: Set the compensations • Design step 3: No Load Input Power • Design step 4: Magnetics • Design step 5: EMI • Preliminary demo board example • Conclusion 5 Improving Efficiency • Sources of loss: – Switching losses: Ploss ( switching ) = 1 2 ⋅ C DRAIN ⋅VDRAIN ( turn −off ) ⋅ FSW 2 – Losses caused by leakage inductance: Ploss(leak) = • 1 2 ⋅ Lleak ⋅ I peak ⋅ FSW 2 Ways to improve efficiency: – Lower the switching frequency FSW Î frequency foldback at light loads – Lower the Drain voltage at turn-off Î valley switching 6 Reducing No-load Input Power • Static losses in the start-up circuit: – Start-up resistor permanently drawing current from the bulk capacitor • Ways to lower the start-up circuit losses – With external start-up resistor Î Extremely low start-up current – Integrated start-up current source Î Extremely low leakage when off – Connect the start-up circuit to the half-wave rectified ac input HV rail Start-up resistors NCP1351 1 8 2 7 3 6 4 5 Vcc 7 Reducing No-load Input Power RstartupHW = Rstartup π Selected from bulk connection Vpeak 350 250 I1 150 50.0 RstartupHW -50.0 Mains input 10.0M Cbulk 30.0M 50.0M time in secs 70.0M 90.0M Vcc CVcc PRstartupHW = 8 PRstartup π 4 auxiliary winding Brings a 21% reduction in power Agenda • New ENERGY STAR® requirements • Needed features to meet the new specification • New controller family NCP1237/38/87/88 • Design step 1: Power stage • Design step 2: Set the compensations • Design step 3: No Load Input Power • Design step 4: Magnetics • Design step 5: EMI • Preliminary demo board example • Conclusion 9 NCP1237/38/87/88 Avail. in Q1 2010 Value Proposition The NCP1237/38/87/88 series represents the next generation of fixed frequency PWM controllers. It targets applications where cost-effectiveness, reliability, design flexibility and low standby power are compulsory. Unique Features Benefits High-voltage current source Fewer components and with built-in Brown-out and mains OVP Freq. reduction in light load conditions and skip mode Adjustable Over Power Protection rugged design Extremely low no-load standby power Simple option to alter the max. peak current set point at high line Application Data DSS NCP1237A NCP1237B NCP1238A NCP1238B NCP1287A NCP1287B NCP1288A NCP1288B Others Features Latch-off input for severe fault conditions, allowing direct connection of NTC Timer-based protection: auto-recovery or latched Dual OCP option available Built-in ramp compensation Frequency jittering for a softened EMI signature Vcc operation up to 30 V Market & Applications 10 AC-DC adapters for notebooks, LCD monitor, game console, printers CE applications (DVD, STB) Yes Yes Yes Yes HV only HV only HV only HV only Dual OCP Yes Yes No No Yes Yes No No Latch Auto Recovery Yes Yes Yes Yes Yes Yes Yes Yes Various options available depending upon end applications needs Ordering & Package Information NCP1237/38xDR2G - NCP1287/88xDR2G SOIC-7 2500p per reel Pb O, DW NCP1237/38/87/88 – Built-in Startup FET A flyback auxiliary winding supplies biasing voltage in normal condition to save power High startup current to reduce charging time Low initial startup current to prevent damage if Vcc pin is shorted to ground. No startup resistor! 11 Saves PCB area & saves power NCP1237/38/87/88 – Dynamic Self Supply (Optional) Vcc How it works... Vccon 11.3V avg Vccoff (HV) pin8 4 + 2 ON/OFF 3 - (Vcc) pin6 10.5V/12V C ON Current source OFF 10.00M 30.00M 50.00M 70.00M 90.00M Power ON Æ Current Source turns ON Æ Vcc is rising; no output pulses Vcc reaches Vcc(on) Æ Current Source turns OFF Æ Vcc is falling; output is pulsing Vcc falls to Vcc(off) Æ Current Source turns ON Æ Vcc is rising; Dynamic Self-Supply 12 output is pulsing No need of auxiliary winding! NCP1237/38/87/88 – Dual Startup Current Level Startup current is low initially to prevent damage when VCC pin is grounded. Startup current is off when VCC reaches VCC(on) Startup current is activated when VCC drops to VCC(off). Hence, the voltage never drops below VCC(off) after startup. 13 NCP1237/38/87/88 – Brown-out and Mains OVP Detection independent of Ripple on HV pin 14 Can be connected to the half-wave rectified ac line NCP1237/38/87/88 – Brown-out and Mains OVP VHV VHV(start) VHV(stop) Starts only at VCC(on) time HV timer starts HV timer restarts One Shot 40ms min. time DRV Brown-out time Timer-based detection 15 Passes full line cycle drop-out NCP1237/38/87/88 – Over Power Protection Need to compensate for the effect of the propagation delay Over Power Protection 16 The compensation current creates an offset on the Current Sense signal Maximum output power clamped NCP1237/38/87/88 – Dual OCP Threshold VOUT Fault timer starts VOUT Over load Skip Max output power 0.7 V at CS pin Fault timer starts Output still in regulation Transient peak power Output load Accommodates large output power transients Skip Over load Max DC power Max peak power 0.5 V at CS pin 0.7 V at CS pin Output load Suitable for printers These protections use the Up/Down counters, like classical analog integration. 17 NCP1237/38/87/88 – 4 ms Soft Start voltage / current without soft-start with soft-start time VCC Max. current setpoint envelope time 4 ms “digital” soft-start operation 4 ms Soft Start 18 Stressless start-up phase NCP1237/38/87/88 – Frequency Foldback 19 Switching frequency lowered at light load Increased efficiency Switching frequency clamped at 25 kHz No audible noise NCP1237/38/87/88 – Recover from Standby Soft-Skip mode is left as soon as the voltage on the feedback pin reaches the TLD threshold Transient Load Detect Function (TLD) 20 Improved Load Transient response time NCP1237/38/87/88 – Latch-off Protection VLATCH Latch! OK Latch! time An NTC thermistor can be directly connected to the IC Less external components needed 21 NCP1237/38/87/88 – Slope Compensation • • • There is a built in slope compensation with no external setting The internal slope compensation is activated if the duty cycle is higher than 40% The amount of slope compensation is 5mV/% observed at CS pin Internal PWM setpoint VILIMIT VILIMT – 0.2 V 0% 22 40% 80% 100% Duty Cycle Application Schematic 23 Agenda • New ENERGY STAR® requirements • Needed features to meet the new specification • New controller family NCP1237/38/87/88 • Design step 1: Power stage • Design step 2: Set the compensations • Design step 3: No Load Input Power • Design step 4: Magnetics • Design step 5: EMI • Preliminary demo board example • Conclusion 24 Power stage: Schematic of Flyback Converter N= 25 N sec N prim Power Stage Design: Bulk Capacitor • Output power Pout Pout = Vout ⋅ I out • Estimation of input power Pin Pin = Pout η Estimate the η based on the EPA standard 26 • Average input current Iin,avg I in ,avg = Pin Vbulk ,min • Bulk capacitor value Cbulk C bulk = I in ,avg ⋅ t dis ΔVbulk Use tdis=8.5ms Power Stage Design: Drain Voltage Vds(t) Vr Vr Vbulk Vds_pk tleak Vclamp Vleak Vds_max trec toff Tsw 27 ton t Power Stage Design: Transformer Ratio Transformer ratio – consideration of the VDSS of used Q1 N= kC ⋅ (Vout + V f ,diode ) 0.85 ⋅ VDS ,max − 20V − Vbulk ,max Vclamp kC = Vr The 20V means margin for clamping diode turning-on overshoot. Reflected voltage Vr at primary from secondary Vr = Vout + V f ,diode N= N N sec N prim Maximum duty cycle DCmax In CCM operation: DC max 28 Vr = Vr + Vbulk ,min In DCM operation doesn’t depend on N: DC max = Vout Vbulk ,min ⋅ 2 ⋅ L prim ⋅ Fsw Rload ,min Power Stage Design: Current Ripple Ipeak I in ,avg Ivalley I L ,avg = ΔI The average shared transformer current reflected to primary winding IL,avg DC max Choose the relative ripple δIr: it affects the operation in the CCM or DCM • • For universal AC input design use the δIr in range 0.5 to 1.0 For European AC input use the δIr in range 0.8 to 1.6 δI r = 29 ΔI ΔI = δI r ⋅ I L ,avg I L ,avg ΔI = I peak − I valley ⎛ δI ⎞ I peak = I L ,avg ⋅ ⎜1 + r ⎟ 2 ⎠ ⎝ ⎛ δI ⎞ I valley = I L ,avg ⋅ ⎜1 − r ⎟ 2 ⎠ ⎝ Power Stage Design: Primary Inductance Transformer primary winding inductance Lprim L prim = Vbulk ,min ⋅ DC max Fsw ⋅ ΔI Maximum RMS value of the current flowing through primary winding Iprim,RMS I primRMS ⎛ ΔI 2 ⎞ 2 ⎟⎟ = DC max ⋅ ⎜⎜ I peak − I peak ⋅ ΔI + 3 ⎠ ⎝ Maximum RMS value of the current flowing through secondary winding Isec,RMS I sec, peak = I sec RMS 30 I peak N ΔI sec = ΔI N 2 ⎛ ΔI sec ⎞ 2 ⎟ = (1 − DC max ) ⋅ ⎜⎜ I sec, peak − I sec, peak ⋅ ΔI sec + 3 ⎟⎠ ⎝ Power Stage Design: Q1 Selection Conduction loss at Q1 should be approx. 1% of the Pout R DSon ≤ Pout 100 ⋅ I prim , RMS 2 Then the right device is chosen by parameters VDSmax, Ipeak, ton, toff Current sensing resistor Rsense selection Rsense = VILIM 1.1 ⋅ I peak Psense = I primRMS ⋅ Rsense 2 The 1.1 factor means 10% margin for Lprim and other parameters spread, to be able to deliver maximum power. 31 Power Stage Design: Secondary Rectification D1 selection: Reflected voltage across D1 PIV = Vbulk ,max ⋅ N + Vout The next important parameters for D1 selection are Isec,peak, Iout and the fast and soft recovery Cout selection: Minimum Cout value C out ≥ I out ⋅ DC max Vout ,ripple ⋅ Fsw The maximum allowed ESR of Cout ESR ≤ Vout ,ripple Dominant part I sec, peak I Cout ,rms = I sec,rms − I out 2 2 it is recommended to use more parallel Cout for lowering the output voltage ripple. 32 Power Stage Design: Clamping Network TVS – losses in the suppressor: Pclamp Vclamp 1 2 = Eclamp ⋅ Fsw = ⋅ Lleak ⋅ I peak ⋅ Fsw ⋅ 2 Vclamp − Vr RCD clamp – 1st iteration: Rclamp = C clamp > 33 better at no load conditions 2 ⋅ Vleak ⋅ Vclamp Lleak ⋅ I peak ⋅ Fsw 2 Vclamp Vripple ⋅ Rclamp ⋅ Fsw better EMI response Pclamp = Vclamp 2 Rclamp These values need to be optimized for the no load consumption and losses in slow clamping diode D2 TVS vs RCD Clamp Comparison Drain voltage ringing with TVS as clamp Drain voltage ringing with RCD as clamp Different Rdamp used in clamp Ch1 – Drain, Ch3 – Clamp node 34 Synchronous Rectification • 35 New SR controller NCP4303 coming in 2010 Agenda • New ENERGY STAR® requirements • Needed features to meet the new specification • New controller family NCP1237/38/87/88 • Design step 1: Power stage • Design step 2: Set the compensations • Design step 3: No Load Input Power • Design step 4: Magnetics • Design step 5: EMI • Preliminary demo board example • Conclusion 36 Over Power Compensation The overpower compensation affects the primary peak current, by the following formula: I PEAK = ⎛t VCS int R ⎞ R + Vbulk ⋅ ⎜⎜ PROP − g OPP ⋅ OPP ⎟⎟ + Voff ⋅ g OPP ⋅ OPP Rsense Rsense ⎠ Rsense ⎝ LP Then the overpower compensation resistor can be calculated: ROPP = t PROP ⋅ Rsense LP ⋅ g OPP The over power compensating resistor affects only the Ipeak value, but in CCM the output power is given by the following formula, where Ivalley plays a role: Pout 37 ( 2 2 1 = ⋅ η ⋅ L prim ⋅ Fsw ⋅ I peak − I valley 2 ) 2nd Level Over Power Protection The overpower compensation affects the 2nd level over power protection by the addition of bulk voltage feed forward. I TRAN = VCStran R − (Vbulk − Voff )⋅ g OPP ⋅ OPP Rsense Rsense The overpower compensation can be used for reducing the transformer size to ½ and keeping the peak power capability. 38 Spread Sheet Design of OPC OPC design spread sheet was created and the user can choose the right ROPP and it’s effect to Ipeak, Itran, Pout and Ptran: Inputs: Output voltage Primary turns Secondary turns Ramp Comp at CS Maximum int set point Sensing resistor Propagation delay Primary inductance Vin to Iopp ratio Over power comp resistor Switching frequency 2nd level overcurrent prot Vout [V] N1 [-] N2 [-] RaCo [mV/%] Vilimit [V] Rsense [Ohm] tprop [ns] Lp [uH] gopp [uS] Ropp [Ohm] Fsw [kHz] Vcstran [V] 19 100 25 5 0.7 0.235 100 560 0.5 680 65 0.5 Will be available soon, while NCP1237/38/87/88 will be released 39 Spread Sheet Design of OPC Ipeak & Itran vs line input voltage Pmax & Ptran vs line input voltage 140.0 3.0 120.0 Pmax [W], Ptran [W], PoutCC [W] 3.5 Ipeak [A], Itran [A] 2.5 2.0 1.5 1.0 0.5 100.0 80.0 60.0 40.0 20.0 0.0 0.0 0 50 100 150 200 250 300 350 400 0 50 100 150 Vin [V] Ipeak 200 250 300 350 Vbulk [V] Itran Ptran Pmax Keeping constant Ipeak in CCM mode tends to Ivalley decreasing with increasing the Vin. That’s why the maximum output deliverable power Pout increases with increasing Vin. Choose the right compensation. 40 400 Loop Compensation Download the work sheet at: http://www.onsemi.com/pub/Collateral/FLYBACK DWS.XLS.ZIP 41 Agenda • New ENERGY STAR® requirements • Needed features to meet the new specification • New controller family NCP1237/38/87/88 • Design step 1: Power stage • Design step 2: Set the compensations • Design step 3: No Load Input Power • Design step 4: Magnetics • Design step 5: EMI • Preliminary demo board example • Conclusion 42 No Load Input Power Reducing Approach • • • • • 43 Decrease the transformer leakage inductance Use the controller IC with the frequency foldback and skip mode features Do not allow the DSS operation (Vcc cap increase) In case of low Vcc and high aux winding leakage increase the aux number of turns to disable the DSS Decrease the value of the Vcc damping resistor (may affect the EMI) No Load Input Power Reducing Approach • • • • • • • 44 Lower the M1 switching losses Optimize the clamping circuitry Reduce the losses in the secondary rectifier and its snubber Decrease the TL431 biasing Decrease the cross current through the feedback resistor divider Set a stable operation for all loading currents Do not use the output voltage indication LED Agenda • New ENERGY STAR® requirements • Needed features to meet the new specification • New controller family NCP1237/38/87/88 • Design step 1: Power stage • Design step 2: Set the compensations • Design step 3: No Load Input Power • Design step 4: Magnetics • Design step 5: EMI • Preliminary demo board example • Conclusion 45 Area Product AP • There is defined the area product AP [m4] • Product of effective window area Wa [m2] and iron cross section area Ac [m2] AP = Wa ⋅ Ac • Allows fast, effective and optimal magnetic design • Should be published in core datasheet 46 Window Utilization Factor Ku Ku is a measure of the amount of copper that appears in the window area of transformer. This window utilization factor is affected by: 1) 2) 3) 4) Wire insulation Wire lay (fill factor) Bobbin area Insulation required for multilayer windings or between windings Typical values lay in range 0.35 to 0.48 47 The Load Coefficient Kload • Flux density in magnetic should be designed at Ipeak with some margin (5%) to avoid saturation • Do you really need 100% Iout for 100% time?? If not, decrease core size!! K load = I out , RMS I out , RMS ,max Example: • Maximum DC output current is 3.5 A, but it’s only needed for transients • The long term RMS value is only 1.75 A (at least 10 min.) • Loading coefficient is only 0.5 (not 1) → core size is smaller → losses in core and in copper are smaller 48 Flyback Transformer Core Sizing The core size can be calculated by the AP factor in case of these inputs: 1. Converter parameters: Lprim, Ipeak, Kload, δIr, DCmax 2. Core maximum flux density Bmax considered with the hysteresis and eddy current losses at switching frequency Fsw 3. Winding parameters (utilization factors for primary and secondary windings Kuprim, Kusec), (current densities in primary and secondary windings Jprim, Jsec AP = L prim ⋅ I peak Bmax 2 ⋅ K load ⎛ DC max 1 − DC max ⎜ ⋅ + ⎜ J prim ⋅ Ku prim J sec ⋅ Ku sec ⎝ 2 ⎞ δ I r + 12 ⎟⋅ ⎟ 3 ⋅ (δI + 2 )2 r ⎠ Now the appropriate core can be selected from the vendor products list by the AP factor . 49 Windings Design • Number of turns of primary winding NT prim = L prim ⋅ I peak B max ⋅ A c • Number of turns of secondary winding NTsec = N ⋅ NT prim • Number of turns of auxiliary winding NTaux = 50 VCC + V f ,Vcc Vout + V f ,diode ⋅ NTsec Air Gap Length lg lg = N ⋅ μ 0 ⋅ I peak Bmax − MPL μr in case of l g << MPL MPL – core magnetic path length μ0 - permeability of vacuum μr - permeability of core In case an EE, RM or pot core is used, divide the calculated lg by factor 2, because your core has 2 air gaps in magnetic path lg Ac MPL 51 Agenda • New ENERGY STAR® requirements • Needed features to meet the new specification • New controller family NCP1237/38/87/88 • Design step 1: Power stage • Design step 2: Set the compensations • Design step 3: No Load Input Power • Design step 4: Magnetics • Design step 5: EMI • Preliminary demo board example • Conclusion 52 How to improve EMI of my design? Diode snubber AC line filter DC output filter Clamping loop DRV damping Power switch loop 53 • All switching loops with RF currents should have small area • Divide input AC filter at two chokes to decrease the parasitic capacitance coupling • CY – closes the current loop for the RF currents injected via transformer Diode Snubber Design • Snubber resistance value should be close to the characteristic impedance of ringing circuitry Rsnubber = • Lleak , SEC Cd Cd – reverse direction diode capacitance RC time constant of the snubber should be small compared to the switching period but long compared to the voltage rise time C snubber ≈ 3 ÷ 4 ⋅ C d 54 Lleak,SEC –the transformer leakage inductance observed from secondary side PCB Layout Tips DRV loop Output loop Diode snubber 55 Power switch loop Clamping loop Capacitor pads arrangement for better filtering RF currents Agenda • New ENERGY STAR® requirements • Needed features to meet the new specification • New controller family NCP1237/38/87/88 • Design step 1: Power stage • Design step 2: Set the compensations • Design step 3: No Load Input Power • Design step 4: Magnetics • Design step 5: EMI • Preliminary demonstration board example • Conclusion 56 Preliminary Demonstration Board A typical 65 W notebook adapter (19 V output) (optimized for EPS 2.0) 57 Schematic of Preliminary Demonstration Board A typical 65 W notebook adapter (19 V output) (optimized for EPS 2.0) 58 Demonstration Board Efficiency (Measured with DC Cord) The DC cord length is 1.05m and copper cross sec. is 0.75mm2 VIN % of POUTnom 100 % (65 W) 75 % (49 W) 50 % (32 W) 25 % (16 W) 115 Vac/60Hz 230 Vac/60Hz 87.10 % 87.37 % 87.52 % 87.63 % 87.54 % 87.88 % 87.79 % 85.96 % Average at 115Vac is 87.32% and at 230 Vac is 87.21 % 59 Demonstration Board Standby Power Light load and no load input power with the NCP1237 VIN POUT 10 % 115 Vac/60 Hz 230 Vac/50 Hz 86.55 % 83.74 % 85.40 % 78.72 % 77.49 % 73.77 % 51.1 mW 73.5 mW (6.5 W) 5% (3.3 W) 1% (0.65 W) No load 60 Demonstration Board Efficiency 90 88 86 Efficiency [%] 84 82 80 78 – 115 Vac - NCP1237 – 230 Vac - NCP1237 76 74 72 70 0 10 20 30 40 Pout [W] 61 50 60 70 Demonstration Board Conducted EMI 80% of full load (2.72 A) at 230 V/50 Hz NCP1237B 65 kHz 62 NCP1237B 100 kHz Frequency Jittering Ref1 – DRV frequency 63 NCP1237B 100 kHz Frequency Foldback Ch1 – DRV, Ch2 – FB, Ref1 – DRV frequency 64 Load Transient Response from 20% to 100% Ch1 – Drain, Ch2 – FB, Ch3 – Vout (AC coupling), Ch4 - Iout 65 Load Transient Response from 100% to 20% Ch1 – Drain, Ch2 – FB, Ch3 – Vout (AC coupling), Ch4 - Iout 66 Agenda • New ENERGY STAR® requirements • Needed features to meet the new specification • New controller family NCP1237/38/87/88 • Design step 1: Power stage • Design step 2: Set the compensations • Design step 3: No Load Input Power • Design step 4: Magnetics • Design step 5: EMI • Preliminary demo board example • Conclusion 67 Conclusion • Meeting the most recent requirements from ENERGY STAR® or IEC is possible with the classical Flyback converter • The new controller NCP1237/37/87/88 with frequency foldback and skip-mode at light load makes it possible • Average efficiencies above 87% are possible • No-load input power below 300 mW is possible • No-load input power below 100 mW is achievable, although the controller alone cannot ensure this. The whole power supply must be designed to reduce power waste. 68 For More Information 69 • View the extensive portfolio of power management products from ON Semiconductor at www.onsemi.com • View reference designs, design notes, and other material supporting the design of highly efficient power supplies at www.onsemi.com/powersupplies