HCTS245T Data Sheet July 1999 Radiation Hardened Octal Bus Transceiver, Three-State, Non-Inverting Intersil’s Satellite Applications FlowTM (SAF) devices are fully tested and guaranteed to 100kRAD total dose. These QML Class T devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability. The Intersil HCTS245T is a Radiation Hardened NonInverting Octal Bidirectional Bus Transceiver, Three-State, intended for two-way asynchronous communication between data busses. The HCTS245T allows data transmission from the A bus to the B bus or from the B bus to the A bus. The logic level at the direction input (DIR) determines the data direction. The output enable input (OE) puts the I/O port in the high-impedance state when high. Specifications Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed below must be used when ordering. • QML Class T, Per MIL-PRF-38535 • Radiation Performance - Gamma Dose (γ) 1 x 105 RAD(Si) - Latch-Up Free Under Any Conditions - SEP Effective LET No Upsets: >100 MEV-cm2/mg - Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ) • 3 Micron Radiation Hardened CMOS SOS • Fanout (Over Temperature Range) - Bus Driver Outputs - 15 LSTTL Loads • Significant Power Reduction Compared to LSTTL ICs • DC Operating Voltage Range: 4.5V to 5.5V • LSTTL Input Compatibility - VIL = 0.8V Max - VIH = VCC/2 Min • Input Current Levels Ii ≤ 5mA at VOL, VOH Pinouts HCTS245DTR (SBDIP), CDIP2-T20 TOP VIEW Intersil’s Quality Management Plan (QM Plan), listing all Class T screening operations, is also available on our website. www.intersil.com/quality/manuals.asp Ordering Information PART NUMBER TEMP. RANGE (oC) 5962R9574501TRC HCTS245DTR -55 to 125 5962R9574501TXC HCTS245KTR -55 to 125 NOTE: Minimum order quantity for -T is 150 units through distribution, or 450 units direct. DIR 1 A0 2 19 OE A1 3 18 B0 A2 4 17 B1 A3 5 16 B2 A4 6 15 B3 A5 7 14 B4 A6 8 13 B5 A7 9 12 B6 GND 10 11 B7 20 VCC HCTS245KTR (FLATPACK), CDFP4-F20 TOP VIEW DIR 1 20 VCC A0 2 19 OE A1 3 18 B0 A2 4 17 B1 A3 5 16 B2 A4 6 15 B3 A5 7 14 B4 A6 8 13 B5 A7 9 12 B6 10 11 B7 GND 1 4619.1 Features Detailed Electrical Specifications for the HCTS245T are contained in SMD 5962-95745. A “hot-link” is provided from our website for downloading. www.intersil.com/spacedefense/newsafclasst.asp ORDERING NUMBER File Number CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 Satellite Applications Flow™ (SAF) is a trademark of Intersil Corporation. HCTS245T Functional Diagram ONE OF 8 TRANSCEIVERS P A DATA 9 N P B DATA (2, 3, 4, 5, 6, 7, 8) N 11 (18, 17, 16, 15, 14, 13, 12) TO OTHER 7 CIRCUITS DIR 1 OUTPUT ENABLE 19 TRUTH TABLE CONTROL INPUTS OE DIR OPERATION L L B Data to A Bus L H A Data to B Bus H X Isolation H = High Voltage Level, L = Low Voltage Level, X = Immaterial To prevent excess currents in the High-Z (Isolation) modes, all I/O terminals should be terminated with 10kΩ to 1MΩ resistors. 2 HCTS245T Die Characteristics DIE DIMENSIONS: PASSIVATION: (3149µm x 2794µm x 533µm ±51µm) Type: Silox (SiO2) 124 x 110 x 21mils ±2mil Thickness: 13kÅ ±2.6kÅ METALLIZATION: WORST CASE CURRENT DENSITY: < 2.0e5 A/cm2 Type: Al Si Thickness: 11.0kÅ ±1kÅ TRANSISTOR COUNT: SUBSTRATE POTENTIAL: 274 Unbiased Silicon on Sapphire PROCESS: BACKSIDE FINISH: CMOS SOS Sapphire Metallization Mask Layout (19) OE NC NC (20) VCC (1) DIR NC NC HCTS245T A0 (2) (18) B0 A1 (3) (17) B1 A2 (4) (16) B2 A3 (5) (15) B3 B6 (12) B7 (11) (13) B5 GND (10) A5 (7) A7 (9) (14) B4 A6 (8) A4 (6) NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location. The mask series for the HCTS245 is TA14417A. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 3