HCTS109T Data Sheet July 1999 File Number Radiation Hardened Dual JK Flip Flop Features Intersil’s Satellite Applications FlowTM (SAF) devices are fully tested and guaranteed to 100kRAD total dose. These QML Class T devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability. • QML Class T, Per MIL-PRF-38535 The Intersil HCTS109T is a Radiation Hardened Dual JK Flip Flop with set and reset. The flip flop changes state with the positive transition of the clock (CP1 or CP2). 4624.1 • Radiation Performance - Gamma Dose (γ) 1 x 105 RAD(Si) - Latch-Up Free Under Any Conditions - SEP Effective LET No Upsets: >100 MEV-cm2/mg - Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ) • 3 Micron Radiation Hardened SOS CMOS • Significant Power Reduction Compared to LSTTL ICs Specifications Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed below must be used when ordering. Detailed Electrical Specifications for the HCTS109T are contained in SMD 5962-95769. A “hot-link” is provided from our website for downloading. www.intersil.com/spacedefense/newsafclasst.asp • DC Operating Voltage Range: 4.5V to 5.5V • LSTTL Input Logic Compatibility - VIL = 0.8V Max - VIH = VCC/2 Min • Input Current Levels Ii ≤ 5mA at VOL, VOH Pinouts HCTS109T (SBDIP), CDIP2-T16 TOP VIEW Intersil’s Quality Management Plan (QM Plan), listing all Class T screening operations, is also available on our website. www.intersil.com/quality/manuals.asp Ordering Information ORDERING NUMBER PART NUMBER TEMP. RANGE (oC) 5962R9576901TEC HCTS109DTR -55 to 125 5962R9576901TXC HCTS109KTR -55 to 125 NOTE: Minimum order quantity for -T is 150 units through distribution, or 450 units direct. 1 RI 1 16 VCC J1 2 15 R2 K1 3 14 J2 CP1 4 13 K2 S1 5 12 CP2 Q1 6 11 S2 Q1 7 10 Q2 GND 8 9 Q2 HCTS109T (FLATPACK), CDFP4-F16 TOP VIEW R1 1 16 VCC J1 2 15 R2 K1 3 14 J2 CP1 4 13 K2 S1 5 12 CP2 Q1 6 11 S2 Q1 7 10 Q2 GND 8 9 Q2 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 Satellite Applications Flow™ (SAF) is a trademark of Intersil Corporation. HCTS109T Functional Diagram 5 (11) S 2 (14) J J 3 (13) K K S Q 6 (10) Q F/F CL CL R 7 (9) Q Q 4 (12) CP 1 (15) R 16 VCC 8 GND TRUTH TABLE INPUTS OUTPUTS S R CP J K Q Q L H X X X H L H L X X X L H L L X X X H† H† H H L L L H H H H L Toggle H H L H No Change H H H H H H X X L H L No Change † Unpredictable and unstable condition if both S and R go high simultaneously. 2 HCTS109T Die Characteristics DIE DIMENSIONS: PASSIVATION: 2261µm x 2235µm x 533µm ±51µm) Type: Silox (SiO2) 89 x 88 x 21mils ±2mil Thickness: 13kÅ ±2.6kÅ METALLIZATION: WORST CASE CURRENT DENSITY: < 2.0e5 A/cm2 Type: Al Si Thickness: 11kÅ 1kÅ TRANSISTOR COUNT: SUBSTRATE POTENTIAL: 268 Unbiased Silicon on Sapphire PROCESS: BACKSIDE FINISH: CMOS SOS Sapphire Metallization Mask Layout HCTS109T J1 (2) R1 (1) VCC (16) K1 (3) (15) R2 CP1 (4) (14) J2 S1 (5) (13) K2 Q1 (6) (12) CP2 (11) S2 Q1 (7) (8) GND (9) Q2 (10) Q2 NOTE: The die diagram is a generic plot form a similar HCS device. It is intended to indicate approximate die size and bond pad location. The mask series for the HCTS109 is TA14440A. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 3