HV506 Preliminary 275V 40-Channel Row Driver with SCR Outputs Ordering Information Package Options Device HV506 80-Lead Ceramic Gullwing 64-Lead 3-Sided Plastic Gullwing HV506DG HV506PG Features HV506X General Description ❏ Processed with HVDI technology The HV506 is a low-voltage serial to high-voltage parallel converter with push-pull outputs. It is especially suitable for use as a symmetric row driver in AC thin-film electroluminescent (ACTFEL) displays. ❏ Symmetric row drive ❏ Output voltage up to 275V ❏ Source/Sink current 300mA (min.) ❏ Shift Register Speed 3MHz ❏ Pin-programmable shift direction (DIR) ❏ Hi-Rel processing available Absolute Maximum Ratings Logic supply voltage, LVDD1 -0.5V to +15V 1 -0.5V to +15V Substrate bias voltage, Vsub See Note 3 Output supply voltage, VDD Output voltage, HVOUT ±300V Logic input levels Continuous total power Die -0.5V to VDD +0.5V dissipation2 Operating temperature range Storage temperature range Lead temperature 1.6mm (1/16 inch) from case for 10 seconds Ceramic Plastic 1900mW 1200mW Plastic -40°C to +85°C Ceramic -55°C to +125°C When the data reset pin (DRIO) is at logic high, it will reset all the outputs of the internal shift register to zero. At the same time, the output of the shift register will start shifting a logic high from the least significant bit to the most significant bit. The DRIO can be triggered at any time. The DIR pin controls the direction of data through the device. When DIR is at logic high, DRIOA is the input and DRIOB is the output. When DIR is grounded, DRIOB is the input and the DRIOA is the output. See the Output Sequence Operation Table for output sequence. The POL and OE pins perform the polarity select and output enable function respectively. Data is clocked through the shift register loaded on the low to high transition of the clock. A logic high in the shift register will cause the other corresponding output to swing to VDD if POL is high, or to VSS if POL is low. All other outputs will be in the High-Z state. If OE is at logic high all outputs will be in the High-Z state. An output in the High-Z state may block up to 275V above VSS or 275V below VDD. The DP/DN pins are for the positive/negative discharge of the high voltage output HVOUT. Data output buffers are provided for cascading devices. LVDD requires low current for the HV506 logic section. VDD requires high current for the output section . Typically these two pins are at the same potential. The same current and potential conditions apply to the LVSS, logic, and VSS, output pins. Vsub must always be equal or greater than the most positive supply. -65°C to +150°C 260°C Notes: 1. All voltages are referenced to VSS. 2. For operation above 25°C ambient derate linearly to maximum operating temperture at 20mW/°C for plasitc and at 19mW/°C for ceramic. 3. Vsub must be the most positive with respect to VSS. 12/13/01 Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to 1 workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website. Electrical Characteristics (over recommended operating conditions of VDD = 12V, LVDD = 12V, and TA = 25°C unless noted) DC Characteristics Symbol Parameter Min Max Units Conditions IDD VDD supply current 10 mA fCLK = 3MHz IDDQ Quiescent VDD supply current 100 µA All VIN = VSS or VDD VOH High-level output VDD-10 V IO= -300mA 10.8 V IO= -100µA VSS+10 V IO= 300mA 1.2 V IO= 100µA HVOUT Data out VOL Low-level output HVOUT Data out IIH High-level logic input current 1 µA VIH = VDD IIL Low-level logic input current -1 µA VIL = VSS Output OFF leakage current (High-Z) 10 µA HVOUT - VSS = 275V, Vsub = HVOUT 10 µA VDD - HVOUT = 275V, Vsub = VDD Max Units IOFF Notes: 1. Only one output can be turned on at a time. SCR Characteristics Symbol Parameter VOH High-level output VOL Low-level output Min VDD-10 IO= -300mA VSS+10 V IO= 300mA IL Latching Current 15 mA VL Latching Voltage 100 V IH Holding Current 10 mA VH Holding Voltage 10 V IOFF Output OFF leakage current (High-Z) 2 Conditions V 10 µA HVOUT - VSS = 275V, Vsub = HVOUT 10 µA VDD - HVOUT = 275V, Vsub = VDD HV506 AC Characteristics Symbol Parameter fCLK Clock frequency tW (H/L) Pulse width - clock high or low 150 ns tSUD Data set-up time before clock rises 50 ns tHD Data hold time after clock rises 50 ns tSUC HVOUT delay from clock rises (Hi-Z to H or L) tSUE HVOUT delay from Output Enable rises tHC HVOUT delay from clock rises (H or L to Hi-Z) tHE Min Max Units 3 MHz Conditions 1 µs CL = 10nF 600 ns CL = 10nF 2 µs CL = 10nF HVOUT delay from Output Enable rises 600 ns CL = 10nF tDHL * Delay time clock to data output falls 250 ns CL = 15pF tDLH * Delay time clock to data output rises 250 ns CL = 15pF tOFF(SCR) Turn off time of output SCR 4 µs Time after IOUT ≤ 2mA, CL = 10nF tOFF(D) Turn off time of output diode 2 µs Time after IOUT ≤ 2mA, CL = 10nF tPOW POL pulse width 3 µs tOEW Output Enable pulse width 3 µs SR Slew rate of HVOUT 200 V/µs * The delay is measured from the trailing edge of the clock but the data is triggered by the rising edge of the clock. There is an internal delay for the data output which is equal to tWH. Therefore the delay is measured from the trailing edge of the clock. 3 HV506 Recommended Operating Conditions Symbol Parameter Min Max Units LVDD Logic supply voltage 10.8 13.2 V VDD Output supply voltage 10.8 13.2 V VIH High-level input voltage 0.8LVDD LVDD V VIL Low-level input voltage 0 0.2LVDD V fCLK Clock frequency 3 MHz ±300 mA IO High voltage output current TA Operating free-air temperature IOD Plastic -40 +85 °C Ceramic -55 +125 °C ±500 mA Allowable pulse current through diodes Notes: The substrate pin Vsub (pin 39) must be biased for proper output breakdown voltage. Vsub ≥ VDD or HVOUT whichever is higher. LVDD/VDD are measured with respect to LVSS/VSS. Input and Output Equivalent Circuits LVDD LVDD VDD HVOUT Data Out Input DN DP LVSS LVSS VSS Logic Data Output Logic Inputs SCR Characteristics I IH IL VH VL V 4 High Voltage Outputs HV506 Switching Waveforms 1/fCLK t WL t WH VIH 50% CLK t SUD Data Reset Input (DRIOA/DRIOB) 50% 50% 50% 50% VIL t HD VIH Data Valid 50% VIL t DLH t DHL VOH Data Reset Output (DRIOA/DRIOB) 50% 50% t SUC t HC 90% HVOUT (POL = H) VOL VOH 10% High Impedance High Impedance 90% HVOUT (POL = L) 10% t SUC POL VOL t HC t POW 50% VIH 50% VIL t OEW VIH OE 50% 50% t SUE t HE VIL VOH 90% HVOUT 10% High Impedance High Impedance 90% HVOUT 10% t HE t SUE 5 VOL HV506 Functional Block Diagram VDD OE POL LVDD Output HVOUT1 Output HVOUT2 Output HVOUT40 DRIOA CLK S/R DIR DRIOB LVSS VSS Function Table Inputs I/O Relations CLK DIR O/P HIGH X X O/P OFF X O/P LOW O/P OFF S/R Data POL OE HV Outputs H H L H X L X L HIGH-Z X X H L L L X X X X H All O/P HIGH-Z Note: H = logic high level, L = logic low level, X = irrelevant Output Sequence Operation Table DIR L H Data Reset In Data Reset Out DRIOB DRIOA1 40 → 1 DRIOA 2 1 → 40 DRIOB Direction3 HVOUT # Sequence Notes: 1. DRIOA is DRIOBdelayed by 40 clock pulses. 2. DRIOB is DRIOA delayed by 40 clock pulses. 3. Reference to chip layout drawing. 6 DP DN HV506 Typical Output Circuit Connections +HV LVDD VDD HV506 Source SCR D3 12V + – HVOUT D1 D4 Sink SCR LVSS D2 DN DP VSS GND -HV Note: The voltage potential between LVDD/VDD and LVSS/VSS must not exceed recommended operating conditions of 10.8V - 13.2V (12V typical) Substrate Bias Operation higher. Refer to Typical Output Circuit Connections for wiring. A typical Vsub signal is shown below. In order to achieve the desired output breakdown voltage, the substrate must be biased to the most positive potential of any circuit node. For this condition, Vsub ≥ VDD or HVOUT whichever is + HV Vcolumns Vsub VSS 0V -HV Note: In general, when driving the outputs positive, VSUB = +HV. And when driving outputs negative, VSUB equals most positive voltage; e.g. GND or >0V. 7 HV506 HV Switching Waveforms and Operation then discharged through a discharge diode when D2 is switched to GND. The application of a positive pulse to a row operates in a similar manner using the selected source SCR and D1. To drive a TFEL row with a negative pulse: The desired sink SCR is enabled and VSS is connected to -HV via a current limited switch. After holding the output at the -HV level, the switch is opened in order to set the sink SCR current to zero. The row is + HV - (VDD - VSS) 0V VSS Drive Current Disabled - HV Drive Current Disabled High Impedance Output n Sink* SCR D2* tOFF (D2) tOFF (Source SCR) tOFF (Sink SCR) tOFF (D1) Output n+1 High Impedance * Source* SCR D1* Notes internal device handling current flow. Refer to Typical Output Circuit Connections for schematic. 8 High Impedance HV506 Pin Configurations HV506 Option A: Pin Function 1 HVOUT1 2 HVOUT 2 3 HVOUT 3 4 HVOUT 4 5 HVOUT 5 6 HVOUT 6 7 HVOUT 7 8 HVOUT 8 9 HVOUT 9 10 HVOUT 10 11 HVOUT 11 12 HVOUT 12 13 HVOUT 13 14 HVOUT 14 15 HVOUT 15 16 HVOUT 16 17 HVOUT 17 18 HVOUT 18 19 HVOUT 19 20 HVOUT 20 21 N/C 22 DP 23 DN 24 N/C 25 N/C 26 LVSS 27 VDD 28 DIR 29 VSS 30 CLOCK 31 DRIOA 32 DRIOB Pin 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Package Outline Function OE POL LVDD VSS VDD LVSS Vsub N/C N/C DN DP N/C HVOUT 21 HVOUT 22 HVOUT 23 HVOUT 24 HVOUT 25 HVOUT 26 HVOUT 27 HVOUT 28 HVOUT 29 HVOUT 30 HVOUT 31 HVOUT 32 HVOUT 33 HVOUT 34 HVOUT 35 HVOUT 36 HVOUT 37 HVOUT 38 HVOUT 39 HVOUT 40 1 64 Index 24 41 40 25 top view 3-sided Plastic 64-pin Gullwing Package Note: Pins 65–80 are NC. 12/13/010 ©2001 Supertex Inc. All rights reserved. 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