TC1797 Data Sheet

32-Bit
TC1797
32-Bit Single-Chip Microcontroller
Data Sheet
V1.3 2014-08
Microcontrollers
Edition 2014-08
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2014 Infineon Technologies AG
All Rights Reserved.
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32-Bit
TC1797
32-Bit Single-Chip Microcontroller
Data Sheet
V1.3 2014-08
Microcontrollers
TC1797
TC1797 Data Sheet
Revision History: V1.3, 2014-08
Previous Version: V1.2, 2009-09
Page
Subjects (major changes since last revision)
6
add SAK-TC1797-512F180EF and SAK-TC1797-384F150EF.
185
add figure for new package P/PG-BGA-416-27.
all
add package P/PG-BGA-416-27 for new variants SAK-TC1797512F180EF and SAK-TC1797-384F150EF.
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Data Sheet
V1.3, 2014-08
TC1797
Table of Contents
Table of Contents
1
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
2.1
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.2
2.2.1
2.2.2
2.2.3
2.2.3.1
2.2.3.2
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.4.1
2.3.4.2
2.3.4.3
2.3.4.4
2.3.4.5
2.3.5
2.3.6
2.3.6.1
2.3.6.2
2.3.6.3
2.3.6.4
2.3.6.5
2.3.7
2.4
2.5
2.5.1
2.5.2
2.5.3
2.5.4
2.5.4.1
2.5.4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
About this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Related Documentations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Text Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Reserved, Undefined, and Unimplemented Terminology . . . . . . . . . . . . 9
Register Access Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Abbreviations and Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
System Architecture of the TC1797 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
TC1797 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
System Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CPU Cores of the TC1797 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
High-performance 32-bit CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
High-performance 32-bit Peripheral Control Processor . . . . . . . . . . . 17
On-Chip System Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Flexible Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Direct Memory Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
System Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
System Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Clock Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Features of the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
External Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Die Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
General Purpose I/O Ports and Peripheral I/O Lines . . . . . . . . . . . . . . . 23
Program Memory Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Overlay RAM and Data Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Emulation Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Tuning Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Program and Data Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Data Access Overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
On-Chip Peripheral Units of the TC1797 . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Asynchronous/Synchronous Serial Interfaces . . . . . . . . . . . . . . . . . . . . 33
High-Speed Synchronous Serial Interfaces . . . . . . . . . . . . . . . . . . . . . . 35
Micro Second Channel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
FlexRay™ Protocol Controller (Mod_Name) . . . . . . . . . . . . . . . . . . . . . 39
Mod_Name Kernel Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Data Sheet
1
V1.3, 2014-08
TC1797
Table of Contents
2.5.5
2.5.6
2.5.7
2.5.7.1
2.5.7.2
2.5.8
2.5.8.1
2.5.8.2
2.5.9
2.6
2.6.1
2.6.2
2.6.3
2.6.4
2.6.5
2.6.6
MultiCAN Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Micro Link Serial Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Purpose Timer Array (GPTA) . . . . . . . . . . . . . . . . . . . . . . . . . .
Functionality of GPTA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functionality of LTCA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog-to-Digital Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FADC Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Debug Support (OCDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Real Time Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Calibration Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tool Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Self-Test Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FAR Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3.1
3.1.2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
TC1797 Pin Definition and Functions: P/PG-BGA-416-10 / P/PG-BGA-416-27
60
TC1797 P/PG-BGA-416-27P/PG-BGA-416-10 / Package Variant Pin
Configuration 62
Pull-Up/Pull-Down Reset Behavior of the Pins . . . . . . . . . . . . . . . . . . 123
4
Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.3
5.3.1
5.3.2
5.3.3
5.3.4
Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pad Driver and Pad Classes Summary . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog to Digital Converters (ADC0/ADC1/ADC2) . . . . . . . . . . . . . . .
Fast Analog to Digital Converter (FADC) . . . . . . . . . . . . . . . . . . . . . . .
Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Rise/Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power, Pad and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1
Data Sheet
2
42
45
47
48
50
51
51
53
56
56
57
57
57
58
58
58
127
127
127
128
129
130
134
134
138
143
146
146
148
150
150
151
152
154
V1.3, 2014-08
TC1797
Table of Contents
5.3.5
Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.6
E-Ray Phase Locked Loop (E-Ray PLL) . . . . . . . . . . . . . . . . . . . . . . .
5.3.7
BFCLKO Output Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.8
JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.9
DAP Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.10
EBU Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.10.1
EBU Asynchronous Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.10.2
EBU Burst Mode Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.10.3
EBU Arbitration Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.11
Peripheral Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.11.1
Micro Link Interface (MLI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.11.2
Micro Second Channel (MSC) Interface Timing . . . . . . . . . . . . . . .
5.3.11.3
SSC Master/Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.11.4
E-Ray Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4
Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.1
Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.2
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.3
Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.4
Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Sheet
3
156
159
160
161
163
165
165
172
174
175
175
178
179
181
183
183
184
186
187
V1.3, 2014-08
TC1797
Summary of Features
1
•
•
•
•
•
•
•
•
Summary of Features
High-performance 32-bit super-scalar TriCore V1.3.1 CPU with 4-stage pipeline
– Superior real-time performance
– Strong bit handling
– Fully integrated DSP capabilities
– Single precision Floating Point Unit (FPU)
– 180 or 1501) MHz operation at full temperature range
32-bit Peripheral Control Processor with single cycle instruction (PCP2)
– 16 Kbyte Parameter Memory (PRAM)
– 32 Kbyte Code Memory (CMEM)
– 180 or1501) MHz operation at full temperature range
Multiple on-chip memories
– 4 or 31) Mbyte Program Flash Memory (PFLASH) with ECC
– 64 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation
– 128 Kbyte Data Memory (LDRAM)
– 40 Kbyte Code Scratchpad Memory (SPRAM)
– Instruction Cache: up to 16 Kbyte (ICACHE, configurable)
– Data Cache: up to 4 Kbyte (DCACHE, configurable)
– 8 Kbyte Overlay Memory (OVRAM)
– 16 Kbyte BootROM (BROM)
16-Channel DMA Controller
32-bit External Bus Interface Unit (EBU) with
– 32-bit demultiplexed / 16-bit multiplexed external bus interface (3.3V, 2.5V)
– Support for Burst Flash memory devices
– Scalable external bus timing up to 75 MHz
Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels
serviced by CPU or PCP2
High performing on-chip bus structure
– 64-bit Local Memory Buses between CPU, EBU, Flash and Data Memory
– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
– One bus bridges (LFI Bridge)
Versatile On-chip Peripheral Units
– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,
parity, framing and overrun error detection
– Two High-Speed Synchronous Serial Channels (SSC) with programmable data
length and shift direction
– Two serial Micro Second Bus interface (MSC) for serial port expansion to external
power devices
1) Derivative dependent.
Data Sheet
4
V1.3, 2014-08
TC1797
Summary of Features
•
•
•
•
•
•
•
•
•
•
•
•
– Two High-Speed Micro Link interface (MLI) for serial inter-processor
communication
– One MultiCAN Module with 4 CAN nodes and 128 free assignable message
objects for high efficiency data handling via FIFO buffering and gateway data
transfer
– One FlexRayTM module with 2 channels (E-Ray).
– Two General Purpose Timer Array Modules (GPTA) with additional Local Timer
Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer
functionality to realize autonomous and complex Input/Output management
44 analog input lines for ADC
– 3 independent kernels (ADC0, ADC1, ADC2)
– Analog supply voltage range from 3.3 V to 5 V (single supply)
– Performance for 12 bit resolution (@fADCI = 10 MHz)
4 different FADC input channels
– channels with impedance control and overlaid with ADC1 inputs
– Extreme fast conversion, 21 cycles of fFADC clock (262.5 ns @ fFADC = 80 MHz)
– 10-bit A/D conversion (higher resolution can be achieved by averaging of
consecutive conversions in digital data reduction filter)
221 digital general purpose I/O lines1) (GPIO), 4 input lines
Digital I/O ports with 3.3 V capability
On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Bus)
Dedicated Emulation Device chip available (TC1797ED)
– multi-core debugging, real time tracing, and calibration
– four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface
Power Management System
Clock Generation Unit with PLL
Core supply voltage of 1.5 V
I/O voltage of 3.3 V
Full automotive temperature range: -40° to +125°C
Package variants: P/PG-BGA-416-10 and P/PG-BGA-416-27
1) TC1797 package variant P/PG-BGA-416-10 / P/PG-BGA-416-27: 86 GPIO´s
Data Sheet
5
V1.3, 2014-08
TC1797
Summary of Features
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies:
•
•
The derivative itself, i.e. its function set, the temperature range, and the supply
voltage
The package and the type of delivery.
For the available ordering codes for the TC1797 please refer to the “Product Catalog
Microcontrollers”, which summarizes all available microcontroller variants.
This document describes the derivatives of the device.The Table 1 enumerates these
derivatives and summarizes the differences.
Table 1
TC1797 Derivative Synopsis
Derivative
Ambient
Temperature
Range
SAK-TC1797-512F180E
TA =
4 MBytes 180MHz
-40oC to +125oC
P/PG-BGA-416-10
SAK-TC1797-384F150E
TA =
3 MBytes 150MHz
-40oC to +125oC
P/PG-BGA-416-10
SAK-TC1797-512F180EF TA =
4 MBytes 180MHz
-40oC to +125oC
P/PG-BGA-416-27
SAK-TC1797-384F150EF TA =
3 MBytes 150MHz
-40oC to +125oC
P/PG-BGA-416-27
Data Sheet
Program CPU
Package
Flash
frequency
6
V1.3, 2014-08
TC1797
Introduction
2
Introduction
This Data Sheet describes the Infineon TC1797, a 32-bit microcontroller DSP, based on
the Infineon TriCore Architecture.
2.1
About this Document
This document is designed to be read primarily by design engineers and software
engineers who need a detailed description of the interactions of the TC1797 functional
units, registers, instructions, and exceptions.
This TC1797 Data Sheet describes the features of the TC1797 with respect to the
TriCore Architecture. Where the TC1797 directly implements TriCore architectural
functions, this manual simply refers to those functions as features of the TC1797. In all
cases where this manual describes a TC1797 feature without referring to the TriCore
Architecture, this means that the TC1797 is a direct implementation of the TriCore
Architecture.
Where the TC1797 implements a subset of TriCore architectural features, this manual
describes the TC1797 implementation, and then describes how it differs from the TriCore
Architecture. Such differences between the TC1797 and the TriCore Architecture are
documented in the section covering each such subject.
2.1.1
Related Documentations
A complete description of the TriCore architecture is found in the document entitled
“TriCore Architecture Manual”. The architecture of the TC1797 is described separately
this way because of the configurable nature of the TriCore specification: Different
versions of the architecture may contain a different mix of systems components. The
TriCore architecture, however, remains constant across all derivative designs in order to
preserve compatibility.
This Data Sheets together with the “TriCore Architecture Manual” are required to
understand the complete TC1797 micro controller functionality.
2.1.2
Text Conventions
This document uses the following text conventions for named components of the
TC1797:
•
•
•
Functional units of the TC1797 are given in plain UPPER CASE. For example: “The
SSC supports full-duplex and half-duplex synchronous communication”.
Pins using negative logic are indicated by an overline. For example: “The external
reset pin, ESR0, has a dual function.”.
Bit fields and bits in registers are in general referenced as
“Module_Register name.Bit field” or “Module_Register name.Bit”. For example: “The
Current CPU Priority Number bit field CPU_ICR.CCPN is cleared”. Most of the
Data Sheet
7
V1.3, 2014-08
TC1797
Introduction
•
•
•
•
•
register names contain a module name prefix, separated by an underscore character
“_” from the actual register name (for example, “ASC0_CON”, where “ASC0” is the
module name prefix, and “CON” is the kernel register name). In chapters describing
the kernels of the peripheral modules, the registers are mainly referenced with their
kernel register names. The peripheral module implementation sections mainly refer
to the actual register names with module prefixes.
Variables used to describe sets of processing units or registers appear in mixed
upper and lower cases. For example, register name “MSGCFGn” refers to multiple
“MSGCFG” registers with variable n. The bounds of the variables are always given
where the register expression is first used (for example, “n = 0-31”), and are repeated
as needed in the rest of the text.
The default radix is decimal. Hexadecimal constants are suffixed with a subscript
letter “H”, as in 100H. Binary constants are suffixed with a subscript letter “B”, as in:
111B.
When the extent of register fields, groups register bits, or groups of pins are
collectively named in the body of the document, they are represented as
“NAME[A:B]”, which defines a range for the named group from B to A. Individual bits,
signals, or pins are given as “NAME[C]” where the range of the variable C is given in
the text. For example: CFG[2:0] and SRPN[0].
Units are abbreviated as follows:
– MHz = Megahertz
– μs = Microseconds
– kBaud, kbit = 1000 characters/bits per second
– MBaud, Mbit = 1,000,000 characters/bits per second
– Kbyte, KB = 1024 bytes of memory
– Mbyte, MB= 1048576 bytes of memory
In general, the k prefix scales a unit by 1000 whereas the K prefix scales a unit by
1024. Hence, the Kbyte unit scales the expression preceding it by 1024. The
kBaud unit scales the expression preceding it by 1000. The M prefix scales by
1,000,000 or 1048576, and μ scales by .000001. For example, 1 Kbyte is
1024 bytes, 1 Mbyte is 1024 × 1024 bytes, 1 kBaud/kbit are 1000 characters/bits
per second, 1 MBaud/Mbit are 1000000 characters/bits per second, and 1 MHz is
1,000,000 Hz.
Data format quantities are defined as follows:
– Byte = 8-bit quantity
– Half-word = 16-bit quantity
– Word = 32-bit quantity
– Double-word = 64-bit quantity
Data Sheet
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2.1.3
Reserved, Undefined, and Unimplemented Terminology
In tables where register bit fields are defined, the following conventions are used to
indicate undefined and unimplemented function. Furthermore, types of bits and bit fields
are defined using the abbreviations as shown in Table 2.
Table 2
Bit Function Terminology
Function of Bits
Description
Unimplemented,
Reserved
Register bit fields named 0 indicate unimplemented functions
with the following behavior.
• Reading these bit fields returns 0.
• These bit fields should be written with 0 if the bit field is
defined as r or rh.
• These bit fields have to be written with 0 if the bit field is
defined as rw.
These bit fields are reserved. The detailed description of these
bit fields can be found in the register descriptions.
rw
The bit or bit field can be read and written.
rwh
As rw, but bit or bit field can be also set or reset by hardware.
r
The bit or bit field can only be read (read-only).
w
The bit or bit field can only be written (write-only). A read to this
register will always give a default value back.
rh
This bit or bit field can be modified by hardware (read-hardware,
typical example: status flags). A read of this bit or bit field give
the actual status of this bit or bit field back. Writing to this bit or
bit field has no effect to the setting of this bit or bit field.
s
Bits with this attribute are “sticky” in one direction. If their reset
value is once overwritten by software, they can be switched
again into their reset state only by a reset operation. Software
cannot switch this type of bit into its reset state by writing the
register. This attribute can be combined to “rws” or “rwhs”.
f
Bits with this attribute are readable only when they are accessed
by an instruction fetch. Normal data read operations will return
other values.
2.1.4
Register Access Modes
Read and write access to registers and memory locations are sometimes restricted. In
memory and register access tables, the terms as defined in Table 3 are used.
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Table 3
Access Terms
Symbol
Description
U
Access Mode: Access permitted in User Mode 0 or 1.
SV
Access permitted in Supervisor Mode.
R
Read-only register.
Reset Value: Value or bit is not changed by a reset operation.
32
Only 32-bit word accesses are permitted to this register/address range.
E
Endinit-protected register/address.
PW
Password-protected register/address.
NC
No change, indicated register is not changed.
BE
Indicates that an access to this address range generates a Bus Error.
nBE
Indicates that no Bus Error is generated when accessing this address
range, even though it is either an access to an undefined address or the
access does not follow the given rules.
nE
Indicates that no Error is generated when accessing this address or
address range, even though the access is to an undefined address or
address range. True for CPU accesses (MTCR/MFCR) to undefined
addresses in the CSFR range.
2.1.5
Abbreviations and Acronyms
The following acronyms and terms are used in this document:
ADC
Analog-to-Digital Converter
AGPR
Address General Purpose Register
ALU
Arithmetic and Logic Unit
ASC
Asynchronous/Synchronous Serial Controller
BCU
Bus Control Unit
BROM
Boot ROM & Test ROM
CAN
Controller Area Network
CMEM
PCP Code Memory
CISC
Complex Instruction Set Computing
CPS
CPU Slave Interface
CPU
Central Processing Unit
Data Sheet
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CSA
Context Save Area
CSFR
Core Special Function Register
DAP
Device Access Port
DAS
Device Access Server
DCACHE
Data Cache
DFLASH
Data Flash Memory
DGPR
Data General Purpose Register
DMA
Direct Memory Access
DMI
Data Memory Interface
EBU
External Bus Interface
EMI
Electro-Magnetic Interference
FADC
Fast Analog-to-Digital Converter
FAM
Flash Array Module
FCS
Flash Command State Machine
FIM
Flash Interface and Control Module
FPI
Flexible Peripheral Interconnect (Bus)
FPU
Floating Point Unit
GPIO
General Purpose Input/Output
GPR
General Purpose Register
GPTA
General Purpose Timer Array
ICACHE
Instruction Cache
I/O
Input / Output
JTAG
Joint Test Action Group = IEEE1149.1
LBCU
Local Memory Bus Control Unit
LDRAM
Local Data RAM
LFI
Local Memory-to-FPI Bus Interface
LMB
Local Memory Bus
LTC
Local Timer Cell
MLI
Micro Link Interface
MMU
Memory Management Unit
MSB
Most Significant Bit
MSC
Micro Second Channel
Data Sheet
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NC
Not Connected
NMI
Non-Maskable Interrupt
OCDS
On-Chip Debug Support
OVRAM
Overlay Memory
PCP
Peripheral Control Processor
PMU
Program Memory Unit
PLL
Phase Locked Loop
PCODE
PCP Code Memory
PFLASH
Program Flash Memory
PMI
Program Memory Interface
PMU
Program Memory Unit
PRAM
PCP Parameter RAM
RAM
Random Access Memory
RISC
Reduced Instruction Set Computing
SBCU
System Peripheral Bus Control Unit
SCU
System Control Unit
SFR
Special Function Register
SPB
System Peripheral Bus
SPRAM
Scratch-Pad RAM
SRAM
Static Data Memory
SRN
Service Request Node
SSC
Synchronous Serial Controller
STM
System Timer
WDT
Watchdog Timer
Data Sheet
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2.2
System Architecture of the TC1797
The TC1797 combines three powerful technologies within one silicon die, achieving new
levels of power, speed, and economy for embedded applications:
•
•
•
Reduced Instruction Set Computing (RISC) processor architecture
Digital Signal Processing (DSP) operations and addressing modes
On-chip memories and peripherals
DSP operations and addressing modes provide the computational power necessary to
efficiently analyze complex real-world signals. The RISC load/store architecture
provides high computational bandwidth with low system cost. On-chip memory and
peripherals are designed to support even the most demanding high-bandwidth real-time
embedded control-systems tasks.
Additional high-level features of the TC1797 include:
•
•
•
•
•
•
•
•
•
Efficient memory organization: instruction and data scratch memories, caches
Serial communication interfaces – flexible synchronous and asynchronous modes
Peripheral Control Processor – standalone data operations and interrupt servicing
DMA Controller – DMA operations and interrupt servicing
General-purpose timers
High-performance on-chip buses
On-chip debugging and emulation facilities
Flexible interconnections to external components
Flexible power-management
The TC1797 is a high-performance microcontroller with TriCore CPU, program and data
memories, buses, bus arbitration, an interrupt controller, a peripheral control processor
and a DMA controller and several on-chip peripherals. The TC1797 is designed to meet
the needs of the most demanding embedded control systems applications where the
competing issues of price/performance, real-time responsiveness, computational power,
data bandwidth, and power consumption are key design elements.
The TC1797 offers several versatile on-chip peripheral units such as serial controllers,
timer units, and Analog-to-Digital converters. Within the TC1797, all these peripheral
units are connected to the TriCore CPU/system via the Flexible Peripheral Interconnect
(FPI) Bus and the Local Memory Bus (LMB). Several I/O lines on the TC1797 ports are
reserved for these peripheral units to communicate with the external world.
Data Sheet
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2.2.1
TC1797 Block Diagram
Figure 1 shows the block diagram of the TC1797.
FPU
PMI
TriCore
CPU
24
32 KB
KB SPRAM
SPRAM
16 KB ICACHE
(Configurable)
8 KB ICACHE
Abbreviations:
ICACHE:
Instruction Cache
DCACHE Data Cache
SPRAM:
Scratch-Pad RAM
LDRAM:
Local Data RAM
OVRAM:
Overlay RAM
BROM:
Boot ROM
PFlash:
Program Flash
DFlash:
Data Flash
PRAM:
Parameter RAM in PCP
PCODE:
Code RAM in PCP
DMI
124 KB LDRAM
LDRAM
4 KB DCACHE
(Configurable)
DCACHE
CPS
Local Memory Bus (LMB)
EBU
PMU0
PMU1
2 MB PFlash
64 KB DFlash
8 KB OVRAM
16 KB BROM
1 MB PFlash
BCU
1.5V, 3.3V
Ext. Supply
1)
DMA
Bridge
16 channels
SMIF
M
OCDS L1 Debug
Interface/JTAG
1 MB PFlash
M/S
1) The upper MB of the
PMU1 is available only
in the 4MByte derivative
MLI0
System Peripheral Bus
(SPB)
MLI1
16 KB PRAM
PCP2
Core
STM
32 KB CMEM
SBCU
PLL
E-RAY
PLL
MemCheck
5V (3.3V supported as well)
Ext. ADC Supply
SCU
Ports
fE-Ray
fCPU
GPTA0
ADC0
16
ADC1
16
ADC2
16
SSC0
Analog Input Assignment
(hardwired/configurable)
(2 Channels)
System Peripheral Bus
ASC1
Interrupts
FPI-Bus Interface
ASC0
E-Ray
Interrupt
System
FADC
GPTA1
SSC1
LTCA2
Ext.
Request
Unit
Multi
CAN
(4 Nodes,
128 MO)
MSC
0
MSC
1
(LVDS)
(LVDS)
3.3V
Ext. FADC Supply
BlockDiagram
TC1797
Figure 1
Data Sheet
TC1797 Block Diagram
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2.2.2
System Features
The TC1797 has the following features:
Package
•
•
P/PG-BGA-416-10 package, 1mm pitch
P/PG-BGA-416-27 package, 1mm pitch
Clock Frequencies for the 180 MHz derivative
•
•
•
Maximum CPU clock frequency: 180 MHz1)
Maximum PCP clock frequency: 180 MHz2)
Maximum system clock frequency: 90 MHz3)
Clock Frequencies for the 150 MHz derivative
•
•
•
Maximum CPU clock frequency: 150 MHz1)
Maximum PCP clock frequency: 150 MHz2)
Maximum system clock frequency: 90 MHz3)
1) For CPU frequencies > 90 MHz, 2:1 mode has to be enabled. CPU 2:1 mode means: fFPI = 0.5 * fCPU
2) For PCP frequencies > 90 MHz, 2:1 mode has to be enabled. PCP 2:1 mode means: fFPI = 0.5 * fPCP
3) CPU 1:1 Mode means: fFPI = fCPU . PCP 1:1 mode means: fFPI = fPCP
Data Sheet
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2.2.3
CPU Cores of the TC1797
The TC1797 includes a high Performance CPU and a Peripheral Control Processor.
2.2.3.1
High-performance 32-bit CPU
This chapter gives an overview about the TriCore 1 architecture.
TriCore (TC1.3.1) Architectural Highlights
•
•
•
•
•
•
•
•
•
•
•
•
•
Unified RISC MCU/DSP
32-bit architecture with 4 Gbytes unified data, program, and input/output address
space
Fast automatic context-switching
Multiply-accumulate unit
Floating point unit
Saturating integer arithmetic
High-performance on-chip peripheral bus (FPI Bus)
Register based design with multiple variable register banks
Bit handling
Packed data operations
Zero overhead loop
Precise exceptions
Flexible power management
High-efficiency TriCore Instruction Set
•
•
•
•
•
16/32-bit instructions for reduced code size
Data types include: Boolean, array of bits, character, signed and unsigned integer,
integer with saturation, signed fraction, double-word integers, and IEEE-754 singleprecision floating point
Data formats include: Bit, 8-bit byte, 16-bit half-word, 32-bit word, and 64-bit doubleword data formats
Powerful instruction set
Flexible and efficient addressing mode for high code density
Integrated CPU related On-Chip Memories
•
•
Instruction memory: 40 KB total. After reset, configured into:1)
– 40 Kbyte Scratch-Pad RAM (SPRAM)
– 0 Kbyte Instruction Cache (ICACHE)
Data memory: 128 KB total. After reset, configured into:1)
– 128 Kbyte Local Data RAM (LDRAM)
1) Software configurable. Available options are described in the CPU chapter.
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•
– 0 Kbyte Data Cache (DACHE)
On-chip SRAMs with parity error detection
2.2.3.2
High-performance 32-bit Peripheral Control Processor
The PCP is a flexible Peripheral Control Processor optimized for interrupt handling and
thus unloading the CPU.
Features
•
•
•
•
•
•
•
•
•
•
•
Data move between any two memory or I/O locations
Data move until predefined limit supported
Read-Modify-Write capabilities
Full computation capabilities including basic MUL/DIV
Read/move data and accumulate it to previously read data
Read two data values and perform arithmetic or logical operation and store result
Bit-handling capabilities (testing, setting, clearing)
Flow control instructions (conditional/unconditional jumps, breakpoint)
Dedicated Interrupt System
PCP SRAMs with parity error detection
PCP/FPI clock mode 1:1 and 2:1 available
Integrated PCP related On-Chip Memories
•
•
32 Kbyte Code Memory (CMEM)
16 Kbyte Parameter Memory (PRAM)
Data Sheet
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2.3
On-Chip System Units
The TC1797 microcontroller offers several versatile on-chip system peripheral units
such as DMA controller, embedded Flash module, interrupt system and ports.
2.3.1
Flexible Interrupt System
The TC1797 includes a programmable interrupt system with the following features:
Features
•
•
•
•
Fast interrupt response
Independent interrupt systems for CPU and PCP
Each SRN can be mapped to the CPU or PCP interrupt system
Flexible interrupt-prioritizing scheme with 255 interrupt priority levels per interrupt
system
2.3.2
Direct Memory Access Controller
The TC1797 includes a fast and flexible DMA controller with 16 independant DMA
channels (two DMA Move Engines).
Features
•
•
•
•
•
•
•
8 independent DMA channels
– 8 DMA channels in the DMA Sub-Block
– Up to 16 selectable request inputs per DMA channel
– 2-level programmable priority of DMA channels within the DMA Sub-Block
– Software and hardware DMA request
– Hardware requests by selected on-chip peripherals and external inputs
3-level programmable priority of the DMA Sub-Block at the on chip bus interfaces
Buffer capability for move actions on the buses (at least 1 move per bus is buffered)
Individually programmable operation modes for each DMA channel
– Single Mode: stops and disables DMA channel after a predefined number of DMA
transfers
– Continuous Mode: DMA channel remains enabled after a predefined number of
DMA transfers; DMA transaction can be repeated
– Programmable address modification
– Two shadow register modes (with / w/o automatic re-set and direct write access).
Full 32-bit addressing capability of each DMA channel
– 4 Gbyte address range
– Data block move supports > 32 Kbyte moves per DMA transaction
– Circular buffer addressing mode with flexible circular buffer sizes
Programmable data width of DMA transfer/transaction: 8-bit, 16-bit, or 32-bit
Register set for each DMA channel
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•
•
•
– Source and destination address register
– Channel control and status register
– Transfer count register
Flexible interrupt generation (the service request node logic for the MLI channel is
also implemented in the DMA module)
DMA module is working on SPB frequency, LMB interface on LMB frequency.
Dependant on the target/destination address, Read/write requests from the Move
Engine are directed to the SPB, LMB, MLI or to the the Cerberus.
Data Sheet
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2.3.3
System Timer
The TC1797’s STM is designed for global system timing applications requiring both high
precision and long range.
Features
•
•
•
•
•
•
•
•
Free-running 56-bit counter
All 56 bits can be read synchronously
Different 32-bit portions of the 56-bit counter can be read synchronously
Flexible interrupt generation based on compare match with partial STM content
Driven by maximum 90 MHz (= fSYS, default after reset = fSYS/2)
Counting starts automatically after a reset operation
STM registers are reset by an application reset if bit ARSTDIS.STMDIS is cleared. If
bit ARSTDIS.STMDIS is set, the STM is not reset.
STM can be halted in debug/suspend mode
Special STM register semantics provide synchronous views of the entire 56-bit counter,
or 32-bit subsets at different levels of resolution.
The maximum clock period is 256 × fSTM. At fSTM = 90 MHz, for example, the STM counts
25.39 years before overflowing. Thus, it is capable of continuously timing the entire
expected product life time of a system without overflowing.
In case of a power-on reset, a watchdog reset, or a software reset, the STM is reset. After
one of these reset conditions, the STM is enabled and immediately starts counting up. It
is not possible to affect the content of the timer during normal operation of the TC1797.
The STM can be optionally disabled for power-saving purposes, or suspended for
debugging purposes via its clock control register. In suspend mode of the TC1797
(initiated by writing an appropriate value to STM_CLC register), the STM clock is
stopped but all registers are still readable.
Due to the 56-bit width of the STM, it is not possible to read its entire content with one
instruction. It needs to be read with two load instructions. Since the timer would continue
to count between the two load operations, there is a chance that the two values read are
not consistent (due to possible overflow from the low part of the timer to the high part
between the two read operations). To enable a synchronous and consistent reading of
the STM content, a capture register (STM_CAP) is implemented. It latches the content
of the high part of the STM each time when one of the registers STM_TIM0 to STM_TIM5
is read. Thus, STM_CAP holds the upper value of the timer at exactly the same time
when the lower part is read. The second read operation would then read the content of
the STM_CAP to get the complete timer value.
The content of the 56-bit System Timer can be compared against the content of two
compare values stored in the STM_CMP0 and STM_CMP1 registers. Interrupts can be
generated on a compare match of the STM with the STM_CMP0 or STM_CMP1
registers.
Data Sheet
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Figure 2 provides an overview on the STM module. It shows the options for reading
parts of STM content.
STM Module
31
23
STM_CMP0
to DMA etc.
15
7
Compare Register 0
31
Interrupt
Control
Clock
Control
23
STM_CMP1
STM
IRQ0
55
STM
IRQ1
0
47
15
7
0
Compare Register1
39
31
23
15
7
0
56-bit System Timer
Enable /
Disable
00 H
STM_CAP
fSTM
00 H
STM_TIM6
STM_TIM5
Address
Decoder
STM_TIM4
STM_TIM3
PORST
STM_TIM2
STM_TIM1
STM_TIM0
MCB06185_mod
Figure 2
Data Sheet
General Block Diagram of the STM Module Registers
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2.3.4
System Control Unit
The following SCU introduction gives an overview about the TC1797 System Control
Unit (SCU) For Information about the SCU see chapter 3.
2.3.4.1
Clock Generation Unit
The Clock Generation Unit (CGU) allows a very flexible clock generation for the TC1797.
During user program execution the frequency can be programmed for an optimal ratio
between performance and power consumption.
2.3.4.2
Features of the Watchdog Timer
The main features of the WDT are summarized here.
•
•
•
•
•
•
•
•
•
16-bit Watchdog counter
Selectable input frequency: fFPI/256 or fFPI/16384
16-bit user-definable reload value for normal Watchdog operation, fixed reload value
for Time-Out and Prewarning Modes
Incorporation of the ENDINIT bit and monitoring of its modifications
Sophisticated Password Access mechanism with fixed and user-definable password
fields
Access Error Detection: Invalid password (during first access) or invalid guard bits
(during second access) trigger the Watchdog reset generation
Overflow Error Detection: An overflow of the counter triggers the Watchdog reset
generation
Watchdog function can be disabled; access protection and ENDINIT monitor function
remain enabled
Double Reset Detection
2.3.4.3
Reset Operation
The following reset request triggers are available:
•
•
•
•
•
•
1 External power-on hardware reset request trigger; PORST, (cold reset)
2 External System Request reset triggers; ESR0 and ESR1,(warm reset)
Watchdog Timer (WDT) reset request trigger, (warm reset)
Software reset (SW), (warm reset)
Debug (OCDS) reset request trigger, (warm reset)
Resets via the JTAG interface
There are two basic types of reset request triggers:
•
Trigger sources that do not depend on a clock, such as the PORST. This trigger force
the device into an asynchronous reset assertion independently of any clock. The
activation of an asynchronous reset is asynchronous to the system clock, whereas
its de-assertion is synchronized.
Data Sheet
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•
Trigger sources that need a clock in order to be asserted, such as the input signals
ESR0, ESR1, the WDT trigger, the parity trigger, or the SW trigger.
2.3.4.4
External Interface
The SCU provides interface pads for system purpose. Various functions are covered by
these pins. Due to the different tasks some of the pads can not be shared with other
functions but most of them can be shared with other functions. The following functions
are covered by the SCU controlled pads:
•
•
•
•
•
Reset request triggers
Reset indication
Trap request triggers
Interrupt request triggers
Non SCU module triggers
The first three points are covered by the ESR pads and the last two points by the ERU
pads.
2.3.4.5
Die Temperature Measurement
The Die Temperature Sensor (DTS) generates a measurement result that indicates
directly the current temperature. The result of the measurement can be read via an DTS
register.
2.3.5
General Purpose I/O Ports and Peripheral I/O Lines
The TC1797 includes a flexible Ports structure with the following features:
Features
•
•
•
•
•
•
•
Digital General-Purpose Input/Output (GPIO) port lines
Input/output functionality individually programmable for each port line
Programmable input characteristics (pull-up, pull-down, no pull device)
Programmable output driver strength for EMI minimization (weak, medium, strong)
Programmable output characteristics (push-pull, open drain)
Programmable alternate output functions
Output lines of each port can be updated port-wise or set/reset/toggled bit-wise
2.3.6
Program Memory Unit (PMU)
The devices of the AudoF family contain at least one Program Memory Unit. This is
named “PMU0”. Some devices contain additional PMUs which are named “PMU1”, …
In the TC1797, the PMU0 contains the following submodules:
•
•
The Flash command and fetch control interface for Program Flash and Data Flash.
The Overlay RAM interface with Online Data Acquisition (OLDA) support.
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•
•
•
The Boot ROM interface.
The Emulation Memory interface.
The Local Memory Bus LMB slave interface.
Following memories are controlled by and belong to the PMU0:
•
•
•
•
2 Mbyte of Program Flash memory (PFlash)
64 Kbyte of Data Flash memory (DFlash, represents 16 Kbyte EEPROM)
16 Kbyte of Boot ROM (BROM)
8 Kbyte Overlay RAM (OVRAM)
In the TC1797 an additional PMU is included with only a subset of PMU0’s submodules:
•
•
The Flash command and fetch control interface but only for Program Flash.
The Local Memory Bus LMB slave interface.
The following memories are controlled and belong to the PMU1:
•
2 Mbyte of Program Flash memory (PFlash).
Because of its independence from PMU0 this second PMU enables additional
functionality: Read while Write (RWW), Write while Write (WWW) or concurrent data and
instruction accesses, if those are operating on different PMUs.
Data Sheet
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The following figure shows the block diagram of the PMU0:
To/From
Local Memory Bus
64
LMB Interface
Slave
PMU0
Overlay RAM
Interface
PMU
Control
64
64
64
ROM Control
64
OVRAM
64
Flash Interface Module
64
BROM
DFLASH
Emulation
Memory
Interface
PFLASH
Emulation Memory
Figure 3
PMU0_BasicBlockDiag_generic
PMU0 Basic Block Diagram
As described before the PMU1 is reduced to the PFLASH and its controlling
submodules.
2.3.6.1
Boot ROM
The internal 16 Kbyte Boot ROM (BROM) is divided into two parts, used for:
•
•
firmware (Boot ROM), and
factory test routines (Test ROM).
The different sections of the firmware in Boot ROM provide startup and boot operations
after reset. The TestROM is reserved for special routines, which are used for testing,
stressing and qualification of the component.
Data Sheet
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2.3.6.2
Overlay RAM and Data Acquisition
The overlay memory OVRAM is provided in the PMU especially for redirection of data
accesses to program memory to the OVRAM by using the data overlay function. The
data overlay functionality itself is controlled in the DMI module.
For online data acquisition (OLDA) of application or calibration data a virtual 32 KB
memory range is provided which can be accessed without error reporting. Accesses to
this OLDA range can also be redirected to an overlay memory.
2.3.6.3
Emulation Memory Interface
In TC1797 Emulation Device, an Emulation Memory (EMEM) is provided, which can fully
be used for calibration via program memory or OLDA overlay. The Emulation Memory
interface shown in Figure 4 is a 64-bit wide memory interface that controls the CPUaccesses to the Emulation Memory in the TC1797 Emulation Device. In the TC1797
production device, the EMEM interface is always disabled.
2.3.6.4
Tuning Protection
Tuning protection is required by the user to absolutely protect control data (e.g. for
engine control), serial number and user software, stored in the Flash, from being
manipulated, and to safely detect changed or disturbed data. For the internal Flash,
these protection requirements are excellently fulfilled in the TC1797 with
•
•
•
Flash read and write protection with user-specific protection levels, and with
dedicated HW and firmware, supporting the internal Flash read protection, and with
the Alternate Boot Mode.
Special tuning protection support is provided for external Flash, which must also be
protected.
2.3.6.5
Program and Data Flash
The embedded Flash modules of PMU0 includes 2 Mbyte of Flash memory for code or
constant data (called Program Flash) and additionally 64 Kbyte of Flash memory used
for emulation of EEPROM data (called Data Flash). The Program Flash is realized as
one independent Flash bank, whereas the Data Flash is built of two Flash banks,
allowing the following combinations of concurrent Flash operations:
•
•
•
Read code or data from Program Flash, while one bank of Data Flash is busy with a
program or erase operation.
Read data from one bank of Data Flash, while the other bank of Data Flash is busy
with a program or erase operation.
Program one bank of Data Flash while erasing the other bank of Data Flash, read
from Program Flash.
Data Sheet
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V1.3, 2014-08
TC1797
Introduction
In TC1797 the PMU1 contains 2 Mbyte of Program Flash realized as one Flash bank. It
does not contain any Data Flash.
Since in TC1797 the two PMUs can work in parallel, further combinations of concurrent
operations are supported if those are operating on Flash modules in different PMUs, e.g.
•
•
•
Read data from Flash1 while accessing code from Flash0.
Read code or data from one Flash while the other Flash is busy with program or erase
operation.
Both Flash modules are concurrently busy with program or erase operation.
Both, the Program Flash and the Data Flash, provide error correction of single-bit errors
within a 64-bit read double-word, resulting in an extremely low failure rate. Read
accesses to Program Flash are executed in 256-bit width, to Data Flash in 64-bit width
(both plus ECC). Single-cycle burst transfers of up to 4 double-words and sequential
prefetching with control of prefetch hit are supported for Program Flash.
The minimum programming width is the page, including 256 bytes in Program Flash and
128 bytes in Data Flash. Concurrent programming and erasing in Data Flash is
performed using an automatic erase suspend and resume function.
A basic block diagram of the Flash Module is shown in the following figure.
Control
FSI
Control
Flash Command
State Machine FCS
Redundancy
Control
Voltage Control
SFRs
FSRAM
Microcode
Address
Addr Bus
64
64
Write Bus
Page
Write
Buffers
256 byte
and
128 byte
WR_DATA
Program
Flash
8
ECC Block
PF-Read
Buffer
ECC Code
8
64
Read Bus
64
256+32 bit
and
DF-Read
Buffer
Bank 0
Data
Flash
Bank 1
Bank 0
Bank 1
64+8 bit
RD_DATA
Flash Interface&Control Module
FIM
PMU
Flash Array Module
FAM
Flash FSI & Array
Flash_BasicBlockDiagram_generic.vsd
Figure 4
Basic Block Diagram of Flash Module
All Flash operations are controlled simply by transferring command sequences to the
Flash which are based on JEDEC standard. This user interface of the embedded Flash
is very comfortable, because all operations are controlled with high level commands,
such as “Erase Sector”. State transitions, such as termination of command execution, or
errors are reported to the user by maskable interrupts. Command sequences are
Data Sheet
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V1.3, 2014-08
TC1797
Introduction
normally written to Flash by the CPU, but may also be issued by the DMA controller (or
OCDS).
The Flash also features an advanced read/write protection architecture, including a read
protection for the whole Flash array (optionally without Data Flash) and separate write
protection for all sectors (only Program Flash). Write protected sectors can be made reprogrammable (enabled with passwords), or they can be locked for ever (ROM function).
Each sector can be assigned to up to three different users for write protection. The
different users are organized hierarchically.
Program Flash Features and Functions
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2 Mbyte on-chip Program Flash in PMU0.
2 Mbyte on-chip Program Flash in PMU1.
Any use for instruction code or constant data.
Double Flash module system approach:
– Concurrent read access of code and data.
– Read while write (RWW).
– Concurrent program/erase in both modules.
256 bit read interface (burst transfer operation).
Dynamic correction of single-bit errors during read access.
Transfer rate in burst mode: One 64-bit double-word per clock cycle.
Sector architecture:
– Eight 16 Kbyte, one 128 Kbyte and seven 256 Kbyte sectors.
– Each sector separately erasable.
– Each sector lockable for protection against erase and program (write protection).
One additional configuration sector (not accessible to the user).
Optional read protection for whole Flash, with sophisticated read access supervision.
Combined with whole Flash write protection — thus supporting protection against
Trojan horse programs.
Sector specific write protection with support of re-programmability or locked forever.
Comfortable password checking for temporary disable of write or read protection.
User controlled configuration blocks (UCB) in configuration sector for keywords and
for sector-specific lock bits (one block for every user; up to three users).
Pad supply voltage (VDDP) also used for program and erase (no VPP pin).
Efficient 256 byte page program operation.
All Flash operations controlled by CPU per command sequences (unlock sequences)
for protection against unintended operation.
End-of-busy as well as error reporting with interrupt and bus error trap.
Write state machine for automatic program and erase, including verification of
operation quality.
Support of margin check.
Delivery in erased state (read all zeros).
Global and sector status information.
Data Sheet
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V1.3, 2014-08
TC1797
Introduction
•
•
•
•
•
Overlay support with SRAM for calibration applications.
Configurable wait state selection for different CPU frequencies.
Endurance = 1000; minimum 1000 program/erase cycles per physical sector;
reduced endurance of 100 per 16 KB sector.
Operating lifetime (incl. Retention): 20 years with endurance=1000.
For further operating conditions see data sheet section “Flash Memory Parameters”.
Data Flash Features and Functions
Note: Only available in PMU0.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
64 Kbyte on-chip Flash, configured in two independent Flash banks of equal size.
64 bit read interface.
Erase/program one bank while data read access from the other bank.
Programming one bank while erasing the other bank using an automatic
suspend/resume function.
Dynamic correction of single-bit errors during read access.
Sector architecture:
– Two sectors of equal size.
– Each sector separately erasable.
128 byte pages to be written in one step.
Operational control per command sequences (unlock sequences, same as those of
Program Flash) for protection against unintended operation.
End-of-busy as well as error reporting with interrupt and bus error trap.
Write state machine for automatic program and erase.
Margin check for detection of problematic Flash bits.
Endurance = 30000 (can be device dependent); i.e. 30000 program/erase cycles per
sector are allowed, with a retention of min. 5 years.
Dedicated DFlash status information.
Other characteristics: Same as Program Flash.
Data Sheet
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V1.3, 2014-08
TC1797
Introduction
2.3.7
Data Access Overlay
The data overlay functionality provides the capability to redirect data accesses by the
TriCore to program memory (internal Program Flash or external memory) to the Overlay
SRAM in the PMU, or to the Emulation Memory in Emulation Device ED, or to the
external memory. This functionality makes it possible, for example, to modify the
application’s test and calibration parameters (which are typically stored in the program
memory) during run time of a program. Note that read and write data accesses from/to
program memory are redirected.
Attention: As the address translation is implemented in the DMI, it is only effective
for data accesses by the TriCore. Instruction fetches by the TriCore or
accesses by any other master (including the debug interface) are not
affected!
Note: The external memory can be used as overlay memory only in Emulation Devices
“ED” with an EBU. Generally this feature is not supported in Production Devices
“PD”. However, this function is fully described here in this spec.
Summary of Features and Functions
•
•
•
•
•
•
•
•
•
•
16 overlay ranges (“blocks”) configurable for Program Flash and external memory
Support of 8 Kbyte embedded Overlay SRAM (OVRAM) in PMU
Support of up to 512 Kbyte overlay/calibration memory in Emulation Device (EMEM)
Support of up to 2 MB overlay memory in external memory (EBU space)
Support of Online Data Acquisition into range of up to 32 KB and of its overlay
Support of different overlay memory selections for every enabled overlay block
Sizes of overlay blocks selectable from 16 byte to 2 Kbyte for redirection to OVRAM
Sizes of overlay blocks selectable from 1 Kbyte to 128 Kbyte for redirection to EMEM
or to external memory
All configured overlay ranges can be enabled with only one register write access
Programmable flush (invalidate) control for data cache in DMI
2.4
Development Support
Overview about the TC1797 development environment:
Complete Development Support
A variety of software and hardware development tools for the 32-bit microcontroller
TC1797 are available from experienced international tool suppliers. The development
environment for the Infineon 32-bit microcontroller includes the following tools:
•
•
Embedded Development Environment for TriCore Products
The TC1797 On-chip Debug Support (OCDS) provides a JTAG port for
communication between external hardware and the system
Data Sheet
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V1.3, 2014-08
TC1797
Introduction
•
•
•
Flexible Peripheral Interconnect Buses (FPI Bus) for on-chip interconnections and its
FPI Bus control unit (SBCU)
The System Timer (STM) with high-precision, long-range timing capabilities
The TC1797 includes a power management system, a watchdog timer as well as
reset logic
Data Sheet
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TC1797
Introduction
2.5
On-Chip Peripheral Units of the TC1797
The TC1797 microcontroller offers several versatile on-chip peripheral units such as
serial controllers, timer units, and Analog-to-Digital converters. Several I/O lines on the
TC1797 ports are reserved for these peripheral units to communicate with the external
world.
On-Chip Peripheral Units
•
•
•
•
•
•
•
•
•
•
Two Asynchronous/Synchronous Serial Channels (ASC) with baud-rate generator,
parity, framing and overrun error detection
Two Synchronous Serial Channels (SSC) with programmable data length and shift
direction
Two Micro Second Bus Interfaces (MSC) for serial communication
One CAN Module with four CAN nodes (MultiCAN) for high-efficiency data handling
via FIFO buffering and gateway data transfer
Two Micro Link Serial Bus Interfaces (MLI) for serial multiprocessor communication
Two General Purpose Timer Arrays (GPTA) with a powerful set of digital signal
filtering and timer functionality to accomplish autonomous and complex Input/Output
management. One additional Local Timer Cell Array (LCTA).
Three Analog-to-Digital Converter Units (ADC) with 8-bit, 10-bit, or 12-bit resolution.
One fast Analog-to-Digital Converter Unit (FADC)
One FlexRayTM module with 2 channels (E-Ray).
One External Bus Interface (EBU)
Data Sheet
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V1.3, 2014-08
TC1797
Introduction
2.5.1
Asynchronous/Synchronous Serial Interfaces
The TC1797 includes two Asynchronous/Synchronous Serial Interfaces, ASC0 and
ASC1. Both ASC modules have the same functionality.
Figure 5 shows a global view of the Asynchronous/Synchronous Serial Interface (ASC).
Clock
Control
fASC
RXD
Address
Decoder
Interrupt
Control
ASC
Module
(Kernel)
TXD
RXD
Port
Control
TXD
EIR
TBIR
TIR
RIR
To DMA
MCB05762_mod
Figure 5
General Block Diagram of the ASC Interface
The ASC provides serial communication between the
microcontrollers, microprocessors, or external peripherals.
TC1797
and
other
The ASC supports full-duplex asynchronous communication and half-duplex
synchronous communication. In Synchronous Mode, data is transmitted or received
synchronous to a shift clock that is generated by the ASC internally. In Asynchronous
Mode, 8-bit or 9-bit data transfer, parity generation, and the number of stop bits can be
selected. Parity, framing, and overrun error detection are provided to increase the
reliability of data transfers. Transmission and reception of data is double-buffered. For
multiprocessor communication, a mechanism is included to distinguish address bytes
from data bytes. Testing is supported by a loop-back option. A 13-bit baud rate generator
provides the ASC with a separate serial clock signal, which can be accurately adjusted
by a prescaler implemented as fractional divider.
Data Sheet
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V1.3, 2014-08
TC1797
Introduction
Features
•
•
•
•
•
Full-duplex asynchronous operating modes
– 8-bit or 9-bit data frames, LSB first
– Parity-bit generation/checking
– One or two stop bits
– Baud rate from 5.625 Mbit/s to 1.34 bit/s (@ 90 MHz module clock)
– Multiprocessor mode for automatic address/data byte detection
– Loop-back capability
Half-duplex 8-bit synchronous operating mode
– Baud rate from 11.25 Mbit/s to 915.5 bit/s (@ 90 MHz module clock)
Double-buffered transmitter/receiver
Interrupt generation
– On a transmit buffer empty condition
– On a transmit last bit of a frame condition
– On a receive buffer full condition
– On an error condition (frame, parity, overrun error)
Implementation features
– Connections to DMA Controller
– Connections of receiver input to GPTA (LTC) for baud rate detection and LIN break
signal measuring
Data Sheet
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TC1797
Introduction
2.5.2
High-Speed Synchronous Serial Interfaces
The TC1797 includes two High-Speed Synchronous Serial Interfaces, SSC0 and SSC1.
Both SSC modules have the same functionality.
Figure 6 shows a global view of the Synchronous Serial interface (SSC).
fSSC
Clock
Control
fCLC
Address
Decoder
RIR
Interrupt
Control
Master
TIR
EIR
DMA Requests
SSC
Module
(Kernel)
MRSTA
MRSTB
MTSR
Slave
MTSRA
MTSRB
MRST
Slave
SCLKA
SCLKB
SCLK
Master
Slave
Master
MTSR
MRST
Port
Control
SLSI[7:1]
SLSO[7:0]
SLSOANDO[7:0]
SLSOANDI[7:0]
SCLK
SLSI[7:1]
SLSO[7:0]
SLSOANDO[7:0]
Enable
M/S Select
MCB06058_mod
Figure 6
General Block Diagram of the SSC Interface
The SSC supports full-duplex and half-duplex serial synchronous communication up to
45 Mbit/s (@ 90 MHz module clock, Master Mode). The serial clock signal can be
generated by the SSC itself (Master Mode) or can be received from an external master
(Slave Mode). Data width, shift direction, clock polarity and phase are programmable.
This allows communication with SPI-compatible devices. Transmission and reception of
data are double-buffered. A shift clock generator provides the SSC with a separate serial
clock signal. One slave select input is available for slave mode operation. Eight
programmable slave select outputs (chip selects) are supported in Master Mode.
Data Sheet
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V1.3, 2014-08
TC1797
Introduction
Features
•
•
•
•
•
•
•
Master and Slave Mode operation
– Full-duplex or half-duplex operation
– Automatic pad control possible
Flexible data format
– Programmable number of data bits: 2 to 16 bits
– Programmable shift direction: LSB or MSB shift first
– Programmable clock polarity: Idle low or idle high state for the shift clock
– Programmable clock/data phase: Data shift with leading or trailing edge of the shift
clock
Baud rate generation
– Master Mode:
– Slave Mode:
Interrupt generation
– On a transmitter empty condition
– On a receiver full condition
– On an error condition (receive, phase, baud rate, transmit error)
Flexible SSC pin configuration
Seven slave select inputs SLSI[7:1] in Slave Mode
Eight programmable slave select outputs SLSO[7:0] in Master Mode
– Automatic SLSO generation with programmable timing
– Programmable active level and enable control
– Combinable with SLSO output signals from other SSC modules
Data Sheet
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V1.3, 2014-08
TC1797
Introduction
2.5.3
Micro Second Channel Interface
The TC1797 includes two Micro Second Channel interfaces, MSC0 and MSC1. Both
MSC modules have the same functionality.
Each Micro Second Channel (MSC) interface provides serial communication links
typically used to connect power switches or other peripheral devices. The serial
communication link includes a fast synchronous downstream channel and a slow
asynchronous upstream channel. Figure 7 shows a global view of the interface signals
of an MSC interface.
fMSC
Clock
Control
fCLC
FCLP
FCLN
Interrupt SR[3:0]
Control
4
MSC
Module
(Kernel)
SOP
Downstream
Channel
Address
Decoder
SON
EN0
EN1
EN2
To DMA
ALTINH[15:0]
Upstream
Channel
ALTINL[15:0]
EN3
16
16
8
SDI[7:0]
EMGSTOPMSC
MCB06059
Figure 7
General Block Diagram of the MSC Interface
The downstream and upstream channels of the MSC module communicate with the
external world via nine I/O lines. Eight output lines are required for the serial
communication of the downstream channel (clock, data, and enable signals). One out of
eight input lines SDI[7:0] is used as serial data input signal for the upstream channel. The
source of the serial data to be transmitted by the downstream channel can be MSC
register contents or data that is provided on the ALTINL/ALTINH input lines. These input
lines are typically connected with other on-chip peripheral units (for example with a timer
unit such as the GPTA). An emergency stop input signal makes it possible to set bits of
the serial data stream to dedicated values in an emergency case.
Clock control, address decoding, and interrupt service request control are managed
outside the MSC module kernel. Service request outputs are able to trigger an interrupt
or a DMA request.
Data Sheet
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V1.3, 2014-08
TC1797
Introduction
Features
•
•
•
•
Fast synchronous serial interface to connect power switches in particular, or other
peripheral devices via serial buses
High-speed synchronous serial transmission on downstream channel
– Serial output clock frequency: fFCL = fMSC/2 (fMSCmax = 90 MHz)
– Fractional clock divider for precise frequency control of serial clock fMSC
– Command, data, and passive frame types
– Start of serial frame: Software-controlled, timer-controlled, or free-running
– Programmable upstream data frame length (16 or 12 bits)
– Transmission with or without SEL bit
– Flexible chip select generation indicates status during serial frame transmission
– Emergency stop without CPU intervention
Low-speed asynchronous serial reception on upstream channel
– Baud rate: fMSC divided by 4, 8, 16, 32, 64, 128, or 256 (fMSCmax = 90 MHz)
– Standard asynchronous serial frames
– Parity error checker
– 8-to-1 input multiplexer for SDI lines
– Built-in spike filter on SDI lines
Selectable pin types of downstream channel interface:
four LVDS differential output drivers or four digital GPIO pins
Data Sheet
38
V1.3, 2014-08
TC1797
Introduction
2.5.4
FlexRay™ Protocol Controller (Mod_Name)
The Mod_Name IP-module performs communication according to the FlexRay™ 1)
protocol specification v2.1. With maximum specified clock the bitrate can be
programmed to values up to 10 Mbit/s. Additional bus driver (BD) hardware is required
for connection to the physical layer.
2.5.4.1
Mod_Name Kernel Description
Figure 2.5.4.1 shows a global view of the Mod_Name interface.
fSYS
fPL L _ER AY
fC L C_ ER AY
Clock
Control
fSC L K
Channel A
Address
Decoder
RXDA
TXDA
TXENA
Port
Control
ERAY
Module
(Kernel)
Channel B
RXDB
TXDB
TXENB
STPW
Interrupt
Control
MT
Stop
Watch
Trigger
Select
External
Request
Unit
f
MT
External
Clock
Output
eray_overview.vsd
Figure 8
General Block Diagram of the Mod_Name Interface
1) Infineon®, Infineon Technologies®, are trademarks of Infineon Technologies AG. FlexRay™ is a trademark of
FlexRay Consortium.
Data Sheet
39
V1.3, 2014-08
TC1797
Introduction
The Mod_Name module communicates with the external world via three I/O lines each
channel. The RXDAx and RXDBx lines are the receive data input signals, TXDA and
TXDB lines are the transmit output signals, TXENA and TXENB the transmit enable
signals.
Clock control, address decoding, and service request control are managed outside the
Mod_Name module kernel.
2.5.4.2
Overview
For communication on a FlexRay™ network, individual Message Buffers with up to 254
data byte are configurable. The message storage consists of a single-ported Message
RAM that holds up to 128 Message Buffers. All functions concerning the handling of
messages are implemented in the Message Handler. Those functions are the
acceptance filtering, the transfer of messages between the two FlexRay™ Channel
Protocol Controllers and the Message RAM, maintaining the transmission schedule as
well as providing message status information.
The register set of the Mod_Name IP-module can be accessed directly by an external
Host via the module’s Host interface. These registers are used to
control/configure/monitor the FlexRay™ Channel Protocol Controllers, Message
Handler, Global Time Unit, System Universal Control, Frame and Symbol Processing,
Network Management, Service Request Control, and to access the Message RAM via
Input / Output Buffer.
The Mod_Name IP-module supports the following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
Conformance with FlexRay™ protocol specification v2.1
Data rates of up to 10 Mbit/s on each channel
Up to 128 Message Buffers configurable
8 Kbyte of Message RAM for storage of e.g. 128 Message Buffers with max. 48 byte
data field or up to 30 Message Buffers with 254 byte Data Sections
Configuration of Message Buffers with different payload lengths possible
One configurable receive FIFO
Each Message Buffer can be configured as receive buffer, as transmit buffer or as
part of the receive FIFO
Host access to Message Buffers via Input and Output Buffer.
Input Buffer: Holds message to be transferred to the Message RAM
Output Buffer: Holds message read from the Message RAM
Filtering for slot counter, cycle counter, and channel
Maskable module service requests
Network Management supported
Four service request lines
Automatic delayed read access to Output Command Request Register (OBCR) if a
data transfer from Message RAM to Output Shadow Buffer (initiated by a previous
write access to the OBCR) is ongoing.
Data Sheet
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V1.3, 2014-08
TC1797
Introduction
•
•
•
Automatic delayed read access to Input Command Request Register (IBCR) if a data
transfer from Input Shadow Buffer to Message RAM to (initiated by a previous write
access to the IBCR) is ongoing.
Four Input Buffer for building up transmission Frames in parallel.
Flag indicating which Input Buffer is currently accessible by the host.
Data Sheet
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V1.3, 2014-08
TC1797
Introduction
2.5.5
MultiCAN Controller
The MultiCAN module provides four independent CAN nodes, representing four serial
communication interfaces. The number of available message objects is 128.
MultiCAN Module Kernel
fCAN
Clock
Control
Address
Decoder
f CLC
Message
Object
Buffer
128
Objects
Interrupt
Control
Linked
List
Control
CAN
Node 3
TXDC3
CAN
Node 2
TXDC2
CAN
Node 1
TXDC1
CAN
Node 0
TXDC0
RXDC3
RXDC2
Port
Control
RXDC1
RXDC0
CAN Control
MCA06060_N4
Figure 9
Overview of the MultiCAN Module
The MultiCAN module contains four independently operating CAN nodes with Full-CAN
functionality that are able to exchange Data and Remote Frames via a gateway function.
Transmission and reception of CAN frames is handled in accordance to CAN
specification V2.0 B (active). Each CAN node can receive and transmit standard frames
with 11-bit identifiers as well as extended frames with 29-bit identifiers.
All four CAN nodes share a common set of message objects. Each message object can
be individually allocated to one of the CAN nodes. Besides serving as a storage
container for incoming and outgoing frames, message objects can be combined to build
gateways between the CAN nodes or to set up a FIFO buffer.
The message objects are organized in double-chained linked lists, where each CAN
node has its own list of message objects. A CAN node stores frames only into message
objects that are allocated to the message object list of the CAN node, and it transmits
only messages belonging to this message object list. A powerful, command-driven list
controller performs all message object list operations.
The bit timings for the CAN nodes are derived from the module timer clock (fCAN) and are
programmable up to a data rate of 1 Mbit/s. External bus transceivers are connected to
a CAN node via a pair of receive and transmit pins.
Data Sheet
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V1.3, 2014-08
TC1797
Introduction
Features
•
•
•
•
•
•
•
•
•
•
•
Compliant with ISO 11898
CAN functionality according to CAN specification V2.0 B active
Dedicated control registers for each CAN node
Data transfer rates up to 1 Mbit/s
Flexible and powerful message transfer control and error handling capabilities
Advanced CAN bus bit timing analysis and baud rate detection for each CAN node
via a frame counter
Full-CAN functionality: A set of 128 message objects can be individually
– Allocated (assigned) to any CAN node
– Configured as transmit or receive object
– Setup to handle frames with 11-bit or 29-bit identifier
– Identified by a timestamp via a frame counter
– Configured to remote monitoring mode
Advanced Acceptance Filtering
– Each message object provides an individual acceptance mask to filter incoming
frames.
– A message object can be configured to accept standard or extended frames or to
accept both standard and extended frames.
– Message objects can be grouped into four priority classes for transmission and
reception.
– The selection of the message to be transmitted first can be based on frame
identifier, IDE bit and RTR bit according to CAN arbitration rules, or on its order in
the list.
Advanced message object functionality
– Message objects can be combined to build FIFO message buffers of arbitrary size,
limited only by the total number of message objects.
– Message objects can be linked to form a gateway that automatically transfers
frames between 2 different CAN buses. A single gateway can link any two CAN
nodes. An arbitrary number of gateways can be defined.
Advanced data management
– The message objects are organized in double-chained lists.
– List reorganizations can be performed at any time, even during full operation of the
CAN nodes.
– A powerful, command-driven list controller manages the organization of the list
structure and ensures consistency of the list.
– Message FIFOs are based on the list structure and can easily be scaled in size
during CAN operation.
– Static allocation commands offer compatibility with MultiCAN applications that are
not list-based.
Advanced interrupt handling
Data Sheet
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V1.3, 2014-08
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Introduction
– Up to 16 interrupt output lines are available. Interrupt requests can be routed
individually to one of the 16 interrupt output lines.
– Message post-processing notifications can be combined flexibly into a dedicated
register field of 256 notification bits.
Data Sheet
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V1.3, 2014-08
TC1797
Introduction
2.5.6
Micro Link Serial Bus Interface
This TC1797 contains two Micro Link Serial Bus Interfaces, MLI0 and MLI1.
The Micro Link Interface (MLI) is a fast synchronous serial interface to exchange data
between microcontrollers or other devices, such as stand-alone peripheral components.
Figure 10 shows how two microcontrollers are typically connected together via their MLI
interfaces.
Controller 1
Controller 2
CPU
CPU
Peripheral
A
Peripheral
B
Peripheral
C
Peripheral
D
Memory
MLI
MLI
Memory
System Bus
System Bus
MCA06061
Figure 10
Typical Micro Link Interface Connection
Features
•
•
•
•
•
•
•
•
•
•
Synchronous serial communication between an MLI transmitter and an MLI receiver
Different system clock speeds supported in MLI transmitter and MLI receiver due to
full handshake protocol (4 lines between a transmitter and a receiver)
Fully transparent read/write access supported (= remote programming)
Complete address range of target device available
Specific frame protocol to transfer commands, addresses and data
Error detection by parity bit
32-bit, 16-bit, or 8-bit data transfers supported
Programmable baud rate: fMLI/2 (max. fMLI = fSYS)
Address range protection scheme to block unauthorized accesses
Multiple receiving devices supported
Data Sheet
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V1.3, 2014-08
TC1797
Introduction
Figure 11 shows a general block diagram of the MLI module.
TREADY[D:A] 4
TVALID[D:A]
fSYS
Fract.
Divider
MLI
Transmitter
I/O
Control
4
TDATA
TCLK
TR[3:0]
fMLI
Port
Control
MLI Module
BRKOUT
RCLK[D:A]
4
RREADY[D:A] 4
SR[7:0]
Move
Engine
MLI
Receiver
I/O
Control
RVALID[D:A]
4
RDATA[D:A]
4
MCB06062_mod
Figure 11
General Block Diagram of the MLI Modules
The MLI transmitter and MLI receiver communicate with other MLI receivers and MLI
transmitters via a four-line serial connection each. Several I/O lines of these connections
are available outside the MLI module kernel as a four-line output or input vector with
index numbering A, B, C and D. The MLI module internal I/O control blocks define which
signal of a vector is actually taken into account and also allow polarity inversions (to
adapt to different physical interconnection means)
Data Sheet
46
V1.3, 2014-08
TC1797
Introduction
2.5.7
General Purpose Timer Array (GPTA)
The TC1797 contains the General Purpose Timer Array (GPTA0), plus the additional
Local Timer Cell Array (LTCA2). Figure 12 shows a global view of the GPTA modules.
The GPTA provides a set of timer, compare, and capture functionalities that can be
flexibly combined to form signal measurement and signal generation units. They are
optimized for tasks typical of engine, gearbox, and electrical motor control applications,
but can also be used to generate simple and complex signal waveforms required for
other industrial applications.
GPTA0
Clock Generation Cells
FPC0
FPC1
DCM0
PDL0
FPC2
DCM1
FPC3
DCM2
FPC4
DIGITAL
PLL
PDL1
DCM3
FPC5
fGPTA Clock Distribution Cells
GT0
GT1
Cl ock Bus
Clock
Conn .
Signal
Generation Cells
LTCA2
GTC00
GTC01
GTC02
GTC03
LTC00
LTC01
LTC02
LTC03
LTC00
LTC01
LTC02
LTC03
Global
Timer
Cell Array
Local
Timer
Cell Array
Local
Timer
Cell Array
GTC30
GTC31
LTC62
LTC63
LTC62
LTC63
I/O Line Sharing Block
I/O Line
Sharing Block
Interrupt Sharing Block
Interrupt
Sharing Block
MCB05910_TC1767
Figure 12
Data Sheet
General Block Diagram of the GPTA Modules in the TC1797
47
V1.3, 2014-08
TC1797
Introduction
2.5.7.1
Functionality of GPTA0
The General Purpose Timer Array (GPTA0) provides a set of hardware modules
required for high-speed digital signal processing:
•
•
•
•
•
•
•
•
Filter and Prescaler Cells (FPC) support input noise filtering and prescaler operation.
Phase Discrimination Logic units (PDL) decode the direction information output by a
rotation tracking system.
Duty Cycle Measurement Cells (DCM) provide pulse-width measurement
capabilities.
A Digital Phase Locked Loop unit (PLL) generates a programmable number of GPTA
module clock ticks during an input signal’s period.
Global Timer units (GT) driven by various clock sources are implemented to operate
as a time base for the associated Global Timer Cells.
Global Timer Cells (GTC) can be programmed to capture the contents of a Global
Timer on an external or internal event. A GTC may also be used to control an external
port pin depending on the result of an internal compare operation. GTCs can be
logically concatenated to provide a common external port pin with a complex signal
waveform.
Local Timer Cells (LTC) operating in Timer, Capture, or Compare Mode may also be
logically tied together to drive a common external port pin with a complex signal
waveform. LTCs – enabled in Timer Mode or Capture Mode – can be clocked or
triggered by various external or internal events.
On-chip Trigger and Gating Signals (OTGS) can be configured to provide trigger or
gating signals to integrated peripherals.
Input lines can be shared by an LTC and a GTC to trigger their programmed operation
simultaneously.
The following list summarizes the specific features of the GPTA units.
Clock Generation Unit
•
•
Filter and Prescaler Cell (FPC)
– Six independent units
– Three basic operating modes:
Prescaler, Delayed Debounce Filter, Immediate Debounce Filter
– Selectable input sources:
Port lines, GPTA module clock, FPC output of preceding FPC cell
– Selectable input clocks:
GPTA module clock, prescaled GPTA module clock, DCM clock, compensated or
uncompensated PLL clock.
– fGPTA/2 maximum input signal frequency in Filter Modes
Phase Discriminator Logic (PDL)
– Two independent units
– Two operating modes (2- and 3- sensor signals)
Data Sheet
48
V1.3, 2014-08
TC1797
Introduction
•
•
•
– fGPTA/4 maximum input signal frequency in 2-sensor Mode, fGPTA/6 maximum input
signal frequency in 3-sensor Mode
Duty Cycle Measurement (DCM)
– Four independent units
– 0 - 100% margin and time-out handling
– fGPTA maximum resolution
– fGPTA/2 maximum input signal frequency
Digital Phase Locked Loop (PLL)
– One unit
– Arbitrary multiplication factor between 1 and 65535
– fGPTA maximum resolution
– fGPTA/2 maximum input signal frequency
Clock Distribution Unit (CDU)
– One unit
– Provides nine clock output signals:
fGPTA, divided fGPTA clocks, FPC1/FPC4 outputs, DCM clock, LTC prescaler clock
Signal Generation Unit
•
•
•
Global Timers (GT)
– Two independent units
– Two operating modes (Free-Running Timer and Reload Timer)
– 24-bit data width
– fGPTA maximum resolution
– fGPTA/2 maximum input signal frequency
Global Timer Cell (GTC)
– 32 units related to the Global Timers
– Two operating modes (Capture, Compare and Capture after Compare)
– 24-bit data width
– fGPTA maximum resolution
– fGPTA/2 maximum input signal frequency
Local Timer Cell (LTC)
– 64 independent units
– Three basic operating modes (Timer, Capture and Compare) for 63 units
– Special compare modes for one unit
– 16-bit data width
– fGPTA maximum resolution
– fGPTA/2 maximum input signal frequency
Interrupt Sharing Unit
•
286 interrupt sources, generating up to 92 service requests
Data Sheet
49
V1.3, 2014-08
TC1797
Introduction
On-chip Trigger Unit
•
16 on-chip trigger signals
I/O Sharing Unit
•
Interconnecting inputs and outputs from internal clocks, FPC, GTC, LTC, ports, and
MSC interface
2.5.7.2
Functionality of LTCA2
The Local Timer Cell Array (LTCA2) provides a set of hardware modules required for
high-speed digital signal processing:
•
Local Timer Cells (LTC) operating in Timer, Capture, or Compare Mode may also be
logically tied together to drive a common external port pin with a complex signal
waveform. LTCs – enabled in Timer Mode or Capture Mode – can be clocked or
triggered by various external or internal events.
The following list summarizes the specific features of the LTCA unit.
The Local Timer Arrays (LTCA2) provides a set of hardware modules required for highspeed digital signal processing:
Signal Generation Unit
•
Local Timer Cell (LTC)
– 32 independent units
– Three basic operating modes (Timer, Capture and Compare) for 63 units
– Special compare modes for one unit
– 16-bit data width
– fGPTA maximum resolution
– fGPTA/2 maximum input signal frequency
I/O Sharing Unit
•
Interconnecting inputs and outputs from internal clocks, LTC, ports, and MSC
interface
Data Sheet
50
V1.3, 2014-08
TC1797
Introduction
2.5.8
Analog-to-Digital Converters
The TC1797 includes three Analog to Digital Converter modules (ADC0, ADC1, ADC2)
and one Fast Analog to Digital Converter (FADC).
2.5.8.1
ADC Block Diagram
The analog to digital converter module (ADC) allows the conversion of analog input
values into discrete digital values based on the successive approximation method.
This module contains 3 independent kernels (ADC0, ADC1, ADC2) that can operate
autonomously or can be synchronized to each other. An ADC kernel is a unit used to
convert an analog input signal (done by an analog part) and provides means for
triggering conversions, data handling and storage (done by a digital part).
analog part kernel 0
...
analog
inputs
AD
converter
data (result)
handling
conversion
control
request
control
analog part kernel 1
...
analog
inputs
digital part kernel 1
AD
converter
data (result)
handling
conversion
control
request
control
analog part kernel 2
...
analog
inputs
digital part kernel 0
bus
interface
digital part kernel 2
AD
converter
data (result)
handling
conversion
control
request
control
ADC_3_kernels
Figure 13
ADC Module with three ADC Kernels
Features of the analog part of each ADC kernel:
Data Sheet
51
V1.3, 2014-08
TC1797
Introduction
•
•
•
•
•
•
•
•
•
Input voltage range from 0V to analog supply voltage
Analog supply voltage range from 3.3 V to 5 V (single supply)
(5V nominal supply voltage, performance degradation accepted for lower voltages)
Input multiplexer width of 16 possible analog input channels (not all of them are
necessarily available on pins)
Performance for 12 bit resolution (@fADCI = 10 MHz):
- conversion time about 2µs, TUE1) of ±4 LSB12 @ operating voltage 5 V
- conversion time about 2µs, TUE of ±4 LSB12 @ operating voltage 3.3 V
VAREF and 1 alternative reference input at channel 0
Programmable sample time (in periods of fADCI)
Wide range of accepted analog clock frequencies fADCI
Multiplexer test mode (channel 7 input can be connected to ground via a resistor for
test purposes during run time by specific control bit)
Power saving mechanisms
Features of the digital part of each ADC kernel:
•
•
•
•
•
•
•
•
•
•
•
•
Independent result registers (16 independent registers)
5 conversion request sources (e.g. for external events, auto-scan, programmable
sequence, etc.)
Synchronization of the ADC kernels for concurrent conversion starts
Control an external analog multiplexer, respecting the additional set up time
Programmable sampling times for different channels
Possibility to cancel running conversions on demand with automatic restart
Flexible interrupt generation (possibility of DMA support)
Limit checking to reduce interrupt load
Programmable data reduction filter by adding conversion results
Support of conversion data FIFO
Support of suspend and power down modes
Individually programmable reference selection for each channel (with exception of
dedicated channels always referring to VAREF)
1) This value reflects the ADC module capability in an adapted electrical environment, e.g. characterized by
“clean” routing of analog and digital signals and separation of analog and digital PCB areas, low noise on
analog power supply (< 30mV), low switching activity of digital pins near to the ADC, etc.
Data Sheet
52
V1.3, 2014-08
TC1797
Introduction
2.5.8.2
FADC Short Description
General Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Extreme fast conversion, 21 cycles of fFADC clock (262.5 ns @ fFADC = 80 MHz)
10-bit A/D conversion (higher resolution can be achieved by averaging of
consecutive conversions in digital data reduction filter)
Successive approximation conversion method
Two differential input channels with impedance control available on dedicated pins
Two differential input channels with impedance control overlaid with ADC1 inputs
Each differential input channel can also be used as single-ended input
Offset calibration support for each channel
Programmable gain of 1, 2, 4, or 8 for each channel
Free-running (Channel Timers) or triggered conversion modes
Trigger and gating control for external signals
Built-in Channel Timers for internal triggering
Channel timer request periods independently selectable for each channel
Selectable, programmable digital anti-aliasing and data reduction filter block with four
independent filter units
VFAREF VDDAF VDDMF VDDIF
VFAGND VSSAF VSSMF
Interrupt
Control
fFADC
Data
Reduction
Unit
fCLC
SRx
A/D
Control
A/D
Converter
Stage
SRx
DMA
TS[H:A]
GS[H:A]
Channel
Trigger
Control
Input Structure
Clock
Control
FAIN0P
FAIN0N
FAIN1P
FAIN1N
FAIN2P
FAIN2N
FAIN3P
FAIN3N
input
channel 0
input
channel 1
input
channel 2
input
channel 3
Channel
Timers
MCB06065_m4
Figure 14
Data Sheet
Block Diagram of the FADC Module with 4 Input Channels
53
V1.3, 2014-08
TC1797
Introduction
As shown in Figure 14, the main FADC functional blocks are:
•
•
•
•
•
•
An Input Structure containing the differential inputs and impedance control.
An A/D Converter Stage responsible for the analog-to-digital conversion including an
input multiplexer to select between the channel amplifiers
A Data Reduction Unit containing programmable anti-aliasing and data reduction
filters
A Channel Trigger Control block determining the trigger and gating conditions for the
FADC channels
A Channel Timer for each channel to independently trigger the conversions
An A/D Control block responsible for the overall FADC functionality
FADC Power Supply and References
The FADC module is supplied by the following power supply and reference voltage lines:
•
•
•
•
VDDMF / VSSMF: FADC Analog Channel Amplifier Power Supply (3.3 V)
VDDIF / VSSMF: FADC Analog Input Stage Power Supply (3.3 - 5 V),
the VDDIF supply does not appear as supply pin, because it is internally connected to
the VDDM supply of the ADC that is sharing the FADC input pins.
VDDAF / VSSAF: FADC Analog Part Power Supply (1.5 V),
to be fed in externally
VFAREF / VFAGND: FADC Reference Voltage (3.3 V max.) and FADC Reference Ground
Input Structure
The input structure of the FADC in the TC1797 contains:
•
•
•
A differential analog input stage for each input channel to select the input impedance
(differential or single-ended measurement) and to decouple the FADC input signal
from the pins.
Input channels 2 and 3 are overlaid with ADC1 input signals (AN28, AN29, AN30,
AN31), whereas input channels 0 and 1 are available on dedicated input pins (AN32,
AN33, AN34, AN35).
A channel amplifier for each input channel with a settling time (about 5µs) when
changing the characteristics of an input stage (changing between unused,
differential, single-ended N, or single-ended P mode).
Data Sheet
54
V1.3, 2014-08
TC1797
Introduction
Analog Input
Stages
FAIN0P
Rp
FAIN0N
Rn
Channel Amplifier
Stages
VDDMF
VSSMF
FAIN2P
Rp
FAIN2N
Rn
VDDMF
Converter Stage
A/D conversion
Control control
gain
CHNR
VSSMF
FAIN1P
Rp
FAIN1N
Rn
VDDMF
A/D
VDDAF VSSAF
VSSMF
FAIN3P
Rp
FAIN3N
Rn
VDDMF
VSSMF
VDDIF
Figure 15
Data Sheet
MCA06432_m4n
VSSMF
FADC Input Structure in TC1797
55
V1.3, 2014-08
TC1797
Introduction
2.5.9
External Bus Interface
The External Bus Unit (EBU) of the TC1797 controls the accesses from peripheral units
to external memories.
Features:
•
•
•
•
•
64-bit internal LMB interface
32-bit demultiplexed / 16-bit multiplexed external bus interface (3.3V, 2.5V)
– Support for Intel-style and Motorola-style interface signals
– Support for Burst Flash memory devices
– Flexibly programmable access parameters
– Programmable chip select lines
– Little-endian support
Examples for memories that has to be supported
– Burst Flash:
– Spansion: S29CD016, S29CD032
– Spansion: S29CL032J1RFAM010 @3,3V
– ST: M58BW016, M58BW032
– ST: M58BW032GB B45ZA3T @3,3V
– Flash (for 16 bit muxed mode):
– http://www.spansion.com/products/Am29LV160B.html
– SRAM (for 16 bit muxed mode):
– http://www.idt.com/products/files/10372/71V016saautomotive.pdf
– http://213.174.55.51/zmd.biz/pdf/ UL62H1616A.pdf
– IDT 71V416YS15BEI
Scalable external bus frequency
– Derived from LMB frequency (fCPU) divided by 1, 2, 3, or 4
– Maximum 75 MHz1)
Data buffering supported
– Code prefetch buffer
– Read/write buffer
2.6
On-Chip Debug Support (OCDS)
The TC1797 contains resources for different kinds of “debugging”, covering needs from
software development to real-time-tuning. These resources are either embedded in
specific modules (e.g. breakpoint logic of the TriCore) or part of a central peripheral
(known as CERBERUS).
1) Maximum frequency of today available automotive Burst Flash devices.
Data Sheet
56
V1.3, 2014-08
TC1797
Introduction
2.6.1
On-Chip Debug Support
The classic software debug approach (start/stop, single-stepping) is supported by
several features labelled “OCDS Level 1”:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Run/stop and single-step execution independently for TriCore and PCP.
Means to request all kinds of reset without usage of sideband pins.
Halt-after-Reset for repeatable debug sessions.
Different Boot modes to use application software not yet programmed to the Flash.
A total of four hardware breakpoints for the TriCore based on instruction address,
data address or combination of both.
Unlimited number of software breakpoints (DEBUG instruction) for TriCore and PCP.
Debug event generated by access to a specific address via the system bus.
Tool access to all SFRs and internal memories independent of the Cores.
Two central Break Switches to collect debug events from all modules (TriCore, PCP,
DMA, BCU, break input pins) and distribute them selectively to breakable modules
(TriCore, PCP, break output pins).
Central Suspend Switch to suspend parts of the system (TriCore, PCP, Peripherals)
instead if breaking them as reaction to a debug event.
Dedicated interrupt resources to handle debug events inside TriCore (breakpoint
trap, software interrupt) and Cerberus (can trigger PCP), e.g. for implementing
Monitor programs.
Access to all OCDS Level 1 resources also for TriCore and PCP themselves for
debug tools integrated into the application code.
Triggered Transfer of data in response to a debug event; if target is programmed to
be a device interface simple variable tracing can be done.
In depth performance analysis and profiling support given by the Emulation Device
through MCDS Event Counters driven by a variety of trigger signals (e.g. cache hit,
wait state, interrupt accepted).
2.6.2
Real Time Trace
For detailed tracing of the system’s behavior a pin-compatible Emulation Device will be
available.1)
2.6.3
Calibration Support
Two main use cases are catered for by resources in addition the OCDS Level 1
infrastructure: Overlay of non-volatile on-chip memory and non-intrusive signaling:
•
•
8 KB SRAM for Overlay.
Can be split into up to 16 blocks which can overlay independent regions of on-chip
Data Flash.
1) The OCDS L2 interface of AudoNG is not available.
Data Sheet
57
V1.3, 2014-08
TC1797
Introduction
•
•
•
•
•
•
•
Changing the configuration is triggered by a single SFR access to maintain
consistency.
Overlay configuration switch does not require the TriCore to be stopped or
suspended.
Invalidation of the Data Cache (maintaining write-back data) can be done
concurrently with the same SFR.
256 KB additional Overlay RAM on Emulation Device.
The 256 KB Trace memory of the Emulation Device can optionally be used for
Overlay also.
A dedicated trigger SFR with 32 independent status bits is provided to centrally post
requests from application code to the host computer.
The host is notified automatically when the trigger SFR is updated by the TriCore or
PCP. No polling via a system bus is required.
2.6.4
Tool Interfaces
Three options exist for the communication channel between Tools (e.g. Debugger,
Calibration Tool) and TC1797:
•
•
•
•
•
•
•
•
Two wire DAP (Device Access Port) protocol for long connections or noisy
environments.
Four (or five) wire JTAG (IEEE 1149.1) for standardized manufacturing tests.
CAN (plus software linked into the application code) for low bandwidth deeply
embedded purposes.
DAP and JTAG are clocked by the tool.
Bit clock up to 40 MHz for JTAG, up to 80 MHz for DAP.
Hot attach (i.e. physical disconnect/reconnect of the host connection without reset of
the TC1797) for all interfaces.
Infineon standard DAS (Device Access Server) implementation for seamless,
transparent tool access over any supported interface.
Lock mechanism to prevent unauthorized tool access to critical application code.
2.6.5
Self-Test Support
Some manufacturing tests can be invoked by the application (e.g. after power-on) if
needed:
•
•
Hardware-accelerated checksum calculation (e.g. for Flash content).
RAM tests optimized for the implemented architecture.
2.6.6
FAR Support
To efficiently locate and identify faults after integration of a TC1797 into a system special
functions are available:
•
Boundary Scan (IEEE 1149.1) via JTAG and DAP.
Data Sheet
58
V1.3, 2014-08
TC1797
Introduction
•
SSCM (Single Scan Chain Mode1)) for structural scan testing of the chip itself.
1) This function requires access to some device pins (e.g. TESTMODE) in addition to those needed for OCDS.
Data Sheet
59
V1.3, 2014-08
TC1797
Pinning
3
Pinning
3.1
TC1797 Pin Definition and Functions: P/PG-BGA-416-10 / P/PGBGA-416-27
Figure 16 is showing the TC1797 Logic Symbol for the package variants: P/PG-BGA416-10 / P/PG-BGA-416-27.
Alternate Functions:
PORST
16
TESTMODE
General Control
ESR0
16
ESR1
16
TRST
16
TCK / DAP0
16
OCDS /
JTAG Control
TDI / BRKIN/
BRKOUT
16
TDO /BRKOUT/
DAP2 / BRKIN
12
TMS / DAP1
8
XTAL1
8
XTAL2
15
VDDOSC
Oscillator
V DDOSC3
6
V SS OS C /
VS S
TC1797
VDDP F
16
Digital Circuitry
Power Supply
9
16
11
16
3
16
VDDP
13
VDD
V DDFL3
4
VDDSB RA M
VSS
VS SA F
FADC Analog
Power Supply
79
VSS MF
V FA GND
VFA RE F
3
3
VDDMF
VDDA F
N.C.
E-RAY / GPTA / HWCFG
Port 1
GPTA / MLI0 / ERU / SSC1
Port 2
GPTA / SSC0 / SSC1
Port 3
GPTA
Port 4
Port 5
Port 6
Port 7
ASC0 / ASC1 / MSC0 /
MSC1 / LVDS / MLI0
ASC0 / ASC1 / SSC1 / CAN /
E-RAY
ERU / ADC-Mux
Port 8
MLI1 / GPTA
Port 9
MSC0 / MSC1 / GPTA
Port 10
Port 11
EBU
8
VDDP F3C3
VDDE BU
Port 0
9
Port 12
EBU
Port 13
GPTA / EBU
Port 14
GPTA / EBU
Port 15
EBU
Port 16
EBU
AN[43:0]
ADC
Analog Inputs
VA RE Fx
VA GNDx
VDDM
VS SM
ADC0 /ADC1
Analog Power Supply
TC1797 _LogSym_416
Figure 16
Data Sheet
TC1797 Logic Symbol for the package variants P/PG-BGA-41610 / P/PG-BGA-416-27
60
V1.3, 2014-08
TC1797
Pinning
3.1.1
TC1797 P/PG-BGA-416-27P/PG-BGA-416-10 / Package Variant
Pin Configuration
Figure 18 shows the TC1797 pin configuration for the P/PG-BGA-416-10 / P/PG-BGA416-27 package variant.
7
8
A
N.C.
1
P2.9 P2.13 P2.15 P0.14 P0.5
P0.2
P0.1
B
P2.6
P2.7 P2.10 P2.14 P0.9
P0.4
P0.3 P3.15 P3.6
C
P2.5
P2.8 P2.11 P2.12 P0.12 P0.10 P0.8
D
P2.4
P2.3
P2.2 P0.15 P0.13 P0.11 VDDP
E
P6.12 P6.11 P6.6
P6.9
F
P6.14 P6.10 P6.4
P6.8
TRST TMS
G
P6.15 P6.13 P6.7
P6.5
VDDPF VDDPF3 XTAL XTAL
2
1
G
H
P8.1
P8.0 VDDFL3
VDD
VDDEBU VDDEBU VDDEBU VDDEBU
H
J
P8.4
P8.3
P8.2
VSS
P11.3 P12.6 P12.7 P11.0
J
K
P8.7
P8.5
P8.6
VDDP
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P11.7 P11.4 P11.1 P11.2
K
L
P1.15 P1.14 P1.13 P1.11
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P11.
P11.5 P11.6
11
L
M
P1.10 P1.9
P1.8
P1.5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDEBU P11. P11.9 P11.8
10
M
N
P1.3
P1.7
P1.6
P1.4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P11.
13
P11.
14
P11.
12
N
P
P1.2
P1.1
P1.0 P1.12
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
P12.1 P12.2 P12.0
P
R
VDD
P7.1
P7.0
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P12.3 P12.5 P12.4
R
SBRAM
2
3
4
5
6
P0.6
9
10
11
12
13
14
P3.1
P5.1
P5.2
P5.7 P5.12 P5.15 VDDFL3 P9.0
P9.3
P3.3
P3.0
P5.0
P5.3
P5.6 P5.13 P5.14 VDDFL3 P9.1
P9.2 P9.10
P0.7
P3.7 P3.10 P3.9
P3.4
P3.2
P5.5
P5.4
P5.9 P5.10 P5.11 P9.6
VSS
VDD
P3.8 P3.12 P3.13 P3.11 VDDP
VSS
VDD
P0.0 P3.14 P3.5
15
16
17
P5.8
18
P9.4
19
P9.5
20
25
26
P9.9 ESR1 ESR0 N.C.
21
22
23
24
VDDP
VSS
A
PO TEST V
DDP
RST MODE
VSS
VDD
B
P9.8 P9.11 N.C.
VDDP
VSS
VDD
P9.13
C
P9.7 P9.12 VDDP
VSS
VDD
TDO P9.14
D
VDD
TCK
TDI
VDD
E
OSC3
VSS
VSS
VDD
OSC
OSC
P11.
15
F
T
P7.6
P7.5
P7.4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDEBU P13.1 P13.3 P13.0
T
U
AN23 P7.7
P7.3
P7.2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P13.6 P13.9 P13.5 P13.2
U
V
AN22 AN21 AN19 AN16
VDD
P13.
P13.8 P13.4
13
V
W
AN20 AN17 AN13 VDDM
VSS
P14.0
P13.
P13.7
12
W
Y
AN18 AN14 AN10 VSSM
VDDEBU P14.2 P13.
14
P13.
10
Y
AA
AN15 AN11
AN5
AN2
P14.3 P14.6 P14.1
P13.
11
AA
AB
AN12
AN9
AN3
AN7
AC
AN8
AN4
AN32 AN38 AN42 VAGND1 AN26 AN24 VDDAF
VSS
VDD
P4.4
AD
AN6
AN1
AN34 AN40 AN35 VAREF1 AN27 AN25 VAREF2 P4.0
P4.2
P4.5 P4.11 P4.15 P10.2 VDDP P15.5 P16.1 P15.3 P15.2 P15.1 P16.2 N.C.
AE
AN0
AN33 AN36 AN41 VAREF0 AN28 AN30 VFAGND VDDMF P4.1
P4.3
P4.7 P4.13 P10.4 P10.0 VDDP P15.4 P15.7 P16.3
AF
N.C.
AN37 AN39 AN43 VAGND0 AN29 AN31 VFAREF VSSMF P4.6
P4.9 P4.10 P4.14 P10.3 P10.1 VDDP P16.0 P15.6
1
2
3
4
5
6
7
8
9
10
11
12
P4.8 P4.12 P10.5 VDDP
13
14
15
16
VSS VDDEBU VSS
17
18
VDD
N.C. VDDEBU
VDD
P14.5 P14.4
P13.
15
AB
VSS
P14.
P14.9 P14.7
12
AC
P14.
15
P14.
P14.8
11
AD
P15.
P15.0 N.C.
11
N.C.
P14.
14
P14.
13
P14.
10
AE
P15.
P15.
P15.8 P15.9
12
10
P15.
13
P15.
14
P15.
15
N.C.
AF
23
24
25
26
19
20
21
22
mca05584_97.vsd
Figure 17
Data Sheet
TC1797 Pinning for P/PG-BGA-416-10 / P/PG-BGA-416-27 Package
61
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package)
Symbol
Ctrl.
Type Function
P0.0
I/O0
HWCFG0
I
A1/
PU
OUT56
O1
OUT56 Line of GPTA0
OUT56
O2
OUT56 Line of GPTA1
OUT80
O3
OUT80 Line of LTCA2
P0.1
I/O0
HWCFG1
I
OUT57
O1
OUT57 Line of GPTA0
OUT57
O2
OUT57 Line of GPTA1
OUT81
O3
OUT81 Line of LTCA2
P0.2
I/O0
HWCFG2
I
OUT58
O1
OUT58 Line of GPTA0
OUT58
O2
OUT58 Line of GPTA1
OUT82
O3
OUT82 Line of LTCA2
P0.3
I/O0
HWCFG3
I
OUT59
O1
OUT59 Line of GPTA0
OUT59
O2
OUT59 Line of GPTA1
OUT83
O3
OUT83 Line of LTCA2
Port 0
A9
A8
A7
B8
Data Sheet
A1/
PU
A1/
PU
A1/
PU
Port 0 General Purpose I/O Line 0
Hardware Configuration Input 0
Port 0 General Purpose I/O Line 1
Hardware Configuration Input 1
Port 0 General Purpose I/O Line 2
Hardware Configuration Input 2
Port 0 General Purpose I/O Line 3
Hardware Configuration Input 3
62
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
B7
P0.4
I/O0
HWCFG4
I
A1/
PU
OUT60
O1
OUT60 Line of GPTA0
OUT60
O2
OUT60 Line of GPTA1
OUT84
O3
OUT84 Line of LTCA2
P0.5
I/O0
HWCFG5
I
OUT61
O1
OUT61 Line of GPTA0
OUT61
O2
OUT61 Line of GPTA1
OUT85
O3
OUT85 Line of LTCA2
P0.6
I/O0
HWCFG6
I
OUT62
O1
OUT62 Line of GPTA0
OUT62
O2
OUT62 Line of GPTA1
OUT86
O3
OUT86 Line of LTCA2
P0.7
I/O0
HWCFG7
I
OUT63
O1
OUT63 Line of GPTA0
OUT63
O2
OUT63 Line of GPTA1
OUT87
O3
OUT87 Line of LTCA2
P0.8
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A6
B6
C8
C7
Data Sheet
A1/
PU
A1/
PU
A1/
PU
A1/
PU
Port 0 General Purpose I/O Line 4
Hardware Configuration Input 4
Port 0 General Purpose I/O Line 5
Hardware Configuration Input 5
Port 0 General Purpose I/O Line 6
Hardware Configuration Input 6
Port 0 General Purpose I/O Line 7
Hardware Configuration Input 7
Port 0 General Purpose I/O Line 8
-
63
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
B5
P0.9
I/O0
RXDA0
I
A1/
PU
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
P0.10
I/O0
TXENA
O1
Reserved
O2
-
Reserved
O3
-
P0.11
I/O0
TXENB
O1
Reserved
O2
-
Reserved
O3
-
P0.12
I/O0
TXDB
O1
Reserved
O2
-
Reserved
O3
-
P0.13
I/O0
RXDB0
I
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
C6
D6
C5
D5
Data Sheet
A2/
PU
A2/
PU
A2/
PU
A1/
PU
Port 0 General Purpose I/O Line 9
E-Ray Channel A Receive Data Input 0
Port 0 General Purpose I/O Line 10
E-Ray Channel A Transmit Data Output
enable
Port 0 General Purpose I/O Line 11
E-Ray Channel B Transmit Data Output
enable
Port 0 General Purpose I/O Line 12
E-Ray Channel B Transmit Data Output
Port 0 General Purpose I/O Line 13
E-Ray Channel B Receive Data Input 0
64
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
A5
P0.14
I/O0
TXDA
O1
A2/
PU
Reserved
O2
-
Reserved
O3
-
P0.15
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
P1.0
I/O0
REQ0
I
EXTCLK1
O1
External Clock Output 1
Reserved
O2
-
Reserved
O3
-
P1.1
I/O0
REQ1
I
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
P1.2
I/O0
REQ2
I
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
D4
A1/
PU
Port 0 General Purpose I/O Line 14
E-Ray Channel A Transmit Data Output
Port 0 General Purpose I/O Line 15
-
Port 1
P3
P2
P1
Data Sheet
A2/
PU
A1/
PU
A1/
PU
Port 1 General Purpose I/O Line 0
External trigger Input 0
Port 1 General Purpose I/O Line 1
External trigger Input 1
Port 1 General Purpose I/O Line 2
External trigger Input 2
65
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
N1
P1.3
I/O0
REQ3
I
A1/
PU
TREADY0B
I
MLI0 Transmit Channel ready Input B
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
P1.4
I/O0
TCLK0
O1
Reserved
O2
-
Reserved
O3
-
P1.5
I/O0
TREADY0A
I
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
P1.6
I/O0
TVALID0A
O1
SLSO10
O2
Slave Select Output Line 10
Reserved
O3
-
P1.7
I/O0
TData0
O1
Reserved
O2
-
Reserved
O3
-
N4
M4
N3
N2
Data Sheet
A2/
PU
A1/
PU
A2/
PU
A2/
PU
Port 1 General Purpose I/O Line 3
External trigger Input 3
Port 1 General Purpose I/O Line 4
MLI0 Transmit Channel Clock Output
Port 1 General Purpose I/O Line 35
MLI0 Transmit Channel ready Input A
Port 1 General Purpose I/O Line 6
MLI0 Transmit Channel valid Output A
Port 1 General Purpose I/O Line 7
MLI0 Transmit Channel Data Output
66
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
M3
P1.8
I/O0
RCLK0A
I
A1/
PU
OUT64
O1
OUT64 Line of GPTA0
OUT64
O2
OUT64 Line of GPTA1
OUT88
O3
OUT88 Line of LTCA2
P1.9
I/O0
RREADY0A
O1
SLSO11
O2
Slave Select Output Line 11
OUT65
O3
OUT65 Line of GPTA0
P1.10
I/O0
RVALID0A
I
OUT66
O1
OUT66 Line of GPTA0
OUT66
O2
OUT66 Line of GPTA1
OUT90
O3
OUT90 Line of LTCA2
P1.11
I/O0
RData0A
I
OUT67
O1
OUT67 Line of GPTA0
OUT67
O2
OUT67 Line of GPTA1
OUT91
O3
OUT91 Line of LTCA2
P1.12
I/O0
EXTCLK0
O1
OUT68
O2
OUT68 Line of GPTA0
OUT68
O3
OUT68 Line of GPTA1
M2
M1
L4
P4
Data Sheet
A2/
PU
A1/
PU
A1/
PU
A2/
PU
Port 1 General Purpose I/O Line 8
MLI0 Receive Channel Clock Input A
Port 1 General Purpose I/O Line 9
MLI0 Receive Channel ready Output A
Port 1 General Purpose I/O Line 10
MLI0 Receive Channel valid Input A
Port 1 General Purpose I/O Line 11
MLI0 Receive Channel Data Input A
Port 1 General Purpose I/O Line 12
External Clock Output 0
67
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
L3
P1.13
I/O0
RCLK0B
I
A1/
PU
OUT69
O1
OUT69 Line of GPTA0
OUT69
O2
OUT69 Line of GPTA1
OUT93
O3
OUT93 Line of LTCA2
P1.14
I/O0
RVALID0B
I
OUT70
O1
OUT70 Line of GPTA0
OUT70
O2
OUT70 Line of GPTA1
OUT94
O3
OUT94 Line of LTCA2
P1.15
I/O0
RData0B
I
OUT70
O1
OUT71 Line of GPTA0
OUT70
O2
OUT71 Line of GPTA1
OUT95
O3
OUT95 Line of LTCA2
P2.2
I/O0
SLSO02
O1
SLSO12
O2
Slave Select Output Line 12
SLSO02
AND
SLSO12
O3
Slave Select Output Line 2 AND Slave Select
Output Line 12
L2
L1
A1/
PU
A1/
PU
Port 1 General Purpose I/O Line 13
MLI0 Receive Channel Clock Input B
Port 1 General Purpose I/O Line 14
MLI0 Receive Channel valid Input B
Port 1 General Purpose I/O Line 15
MLI0 Receive Channel Data Input B
Port 2
D3
Data Sheet
A2/
PU
Port 2 General Purpose I/O Line 2
Slave Select Output Line 2
68
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
D2
P2.3
I/O0
SLSO03
O1
A2/
PU
SLSO13
O2
Slave Select Output Line 13
SLSO03
AND
SLSO13
O3
Slave Select Output Line 3 AND Slave Select
Output Line 13
P2.4
I/O0
SLSO04
O1
SLSO14
O2
Slave Select Output Line 14
SLSO04
AND
SLSO14
O3
Slave Select Output Line 4 AND Slave Select
Output Line 14
P2.5
I/O0
SLSO05
O1
SLSO15
O2
Slave Select Output Line 15
SLSO05
AND
SLSO15
O3
Slave Select Output Line 5 AND Slave Select
Output Line 15
P2.6
I/O0
SLSO06
O1
SLSO16
O2
Slave Select Output Line 16
SLSO06
AND
SLSO16
O3
Slave Select Output Line 6 AND Slave Select
Output Line 16
D1
C1
B1
Data Sheet
A2/
PU
A2/
PU
A2/
PU
Port 2 General Purpose I/O Line 3
Slave Select Output Line 3
Port 2 General Purpose I/O Line 4
Slave Select Output Line 4
Port 2 General Purpose I/O Line 5
Slave Select Output Line 5
Port 2 General Purpose I/O Line 6
Slave Select Output Line 6
69
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
B2
P2.7
I/O0
SLSO07
O1
A2/
PU
SLSO17
O2
Slave Select Output Line 17
SLSO07
AND
SLSO17
O3
Slave Select Output Line 7AND Slave Select
Output Line 17
P2.8
I/O0
IN0
I
IN0
I
IN0 Line of GPTA1
IN0
I
IN0 Line of LTCA2
OUT0
O1
OUT0 Line of GPTA0
OUT0
O2
OUT0 Line of GPTA1
OUT0
O3
OUT0 Line of LTCA2
P2.9
I/O0
IN1
I
IN1
I
IN1 Line of GPTA1
IN1
I
IN1 Line of LTCA2
OUT1
O1
OUT1 Line of GPTA0
OUT1
O2
OUT1 Line of GPTA1
OUT1
O3
OUT1 Line of LTCA2
C2
A2
Data Sheet
A1/
PU
A1/
PU
Port 2 General Purpose I/O Line 7
Slave Select Output Line 7
Port 2 General Purpose I/O Line 8
IN0 Line of GPTA0
Port 2 General Purpose I/O Line 9
IN1 Line of GPTA0
70
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
B3
P2.10
I/O0
IN2
I
A1/
PU
IN2
I
IN2 Line of GPTA1
IN2
I
IN2 Line of LTCA2
OUT2
O1
OUT2 Line of GPTA0
OUT2
O2
OUT2 Line of GPTA1
OUT2
O3
OUT2 Line of LTCA2
P2.11
I/O0
IN3
I
IN3
I
IN3 Line of GPTA1
IN3
I
IN3 Line of LTCA2
OUT3
O1
OUT3 Line of GPTA0
OUT3
O2
OUT3 Line of GPTA1
OUT3
O3
OUT3 Line of LTCA2
P2.12
I/O0
IN4
I
IN4
I
IN4 Line of GPTA1
IN4
I
IN4 Line of LTCA2
OUT4
O1
OUT4 Line of GPTA0
OUT4
O2
OUT4 Line of GPTA1
OUT4
O3
OUT4 Line of LTCA2
C3
C4
Data Sheet
A1/
PU
A1/
PU
Port 2 General Purpose I/O Line 10
IN2 Line of GPTA0
Port 2 General Purpose I/O Line 11
IN3 Line of GPTA0
Port 2 General Purpose I/O Line 12
IN4 Line of GPTA0
71
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
A3
P2.13
I/O0
IN5
I
A1/
PU
IN5
I
IN5 Line of GPTA1
IN5
I
IN5 Line of LTCA2
OUT5
O1
OUT5 Line of GPTA0
OUT5
O2
OUT5 Line of GPTA1
OUT5
O3
OUT5 Line of LTCA2
P2.14
I/O0
IN6
I
IN6
I
IN6 Line of GPTA1
IN6
I
IN6 Line of LTCA2
OUT6
O1
OUT6 Line of GPTA0
OUT6
O2
OUT6 Line of GPTA1
OUT6
O3
OUT6 Line of LTCA2
P2.15
I/O0
IN7
I
IN7
I
IN7 Line of GPTA1
IN7
I
IN7 Line of LTCA2
OUT7
O1
OUT7 Line of GPTA0
OUT7
O2
OUT7 Line of GPTA1
OUT7
O3
OUT7 Line of LTCA2
B4
A4
A1/
PU
A1/
PU
Port 2 General Purpose I/O Line 13
IN5 Line of GPTA0
Port 2 General Purpose I/O Line 14
IN6 Line of GPTA0
Port 2 General Purpose I/O Line 15
IN7 Line of GPTA0
Port 3
Data Sheet
72
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
B12
P3.0
I/O0
IN8
I
A1/
PU
IN8
I
IN8 Line of GPTA1
IN8
I
IN8 Line of LTCA2
OUT8
O1
OUT8 Line of GPTA0
OUT8
O2
OUT8 Line of GPTA1
OUT8
O3
OUT8 Line of LTCA2
P3.1
I/O0
IN9
I
IN9
I
IN9 Line of GPTA1
IN9
I
IN9 Line of LTCA2
OUT9
O1
OUT9 Line of GPTA0
OUT9
O2
OUT9 Line of GPTA1
OUT9
O3
OUT9 Line of LTCA2
P3.2
I/O0
IN10
I
IN10
I
IN10 Line of GPTA1
IN10
I
IN10 Line of LTCA2
OUT10
O1
OUT10 Line of GPTA0
OUT10
O2
OUT10 Line of GPTA1
OUT10
O3
OUT10 Line of LTCA2
A12
C13
Data Sheet
A1/
PU
A1/
PU
Port 3 General Purpose I/O Line 0
IN8 Line of GPTA0
Port 3 General Purpose I/O Line 1
IN9 Line of GPTA0
Port 3 General Purpose I/O Line 2
IN10 Line of GPTA0
73
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
B11
P3.3
I/O0
IN11
I
A1/
PU
IN11
I
IN11 Line of GPTA1
IN11
I
IN11 Line of LTCA2
OUT11
O1
OUT11 Line of GPTA0
OUT11
O2
OUT11 Line of GPTA1
OUT11
O3
OUT11 Line of LTCA2
P3.4
I/O0
IN12
I
IN12
I
IN12 Line of GPTA1
IN12
I
IN12 Line of LTCA2
OUT12
O1
OUT12 Line of GPTA0
OUT12
O2
OUT12 Line of GPTA1
OUT12
O3
OUT12 Line of LTCA2
P3.5
I/O0
IN13
I
IN13
I
IN13 Line of GPTA1
IN13
I
IN13 Line of LTCA2
OUT13
O1
OUT13 Line of GPTA0
OUT13
O2
OUT13 Line of GPTA1
OUT13
O3
OUT13 Line of LTCA2
C12
A11
Data Sheet
A1/
PU
A1/
PU
Port 3 General Purpose I/O Line 3
IN11 Line of GPTA0
Port 3 General Purpose I/O Line 4
IN12 Line of GPTA0
Port 3 General Purpose I/O Line 5
IN13 Line of GPTA0
74
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
B10
P3.6
I/O0
IN14
I
A1/
PU
IN14
I
IN14 Line of GPTA1
IN14
I
IN14 Line of LTCA2
OUT14
O1
OUT14 Line of GPTA0
OUT14
O2
OUT14 Line of GPTA1
OUT14
O3
OUT14 Line of LTCA2
P3.7
I/O0
IN15
I
IN15
I
IN15 Line of GPTA1
IN15
I
IN15 Line of LTCA2
OUT15
O1
OUT15 Line of GPTA0
OUT15
O2
OUT15 Line of GPTA1
OUT15
O3
OUT15 Line of LTCA2
P3.8
I/O0
IN16
I
IN16
I
IN16 Line of GPTA1
IN16
I
IN16 Line of LTCA2
OUT16
O1
OUT16 Line of GPTA0
OUT16
O2
OUT16 Line of GPTA1
OUT16
O3
OUT16 Line of LTCA2
C9
D10
Data Sheet
A1/
PU
A1/
PU
Port 3 General Purpose I/O Line 6
IN14 Line of GPTA0
Port 3 General Purpose I/O Line 7
IN15 Line of GPTA0
Port 3 General Purpose I/O Line 8
IN16 Line of GPTA0
75
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
C11
P3.9
I/O0
IN17
I
A1/
PU
IN17
I
IN17 Line of GPTA1
IN17
I
IN17 Line of LTCA2
OUT17
O1
OUT17 Line of GPTA0
OUT17
O2
OUT17 Line of GPTA1
OUT17
O3
OUT17 Line of LTCA2
P3.10
I/O0
IN18
I
IN18
I
IN18 Line of GPTA1
IN18
I
IN18 Line of LTCA2
OUT18
O1
OUT18 Line of GPTA0
OUT18
O2
OUT18 Line of GPTA1
OUT18
O3
OUT18 Line of LTCA2
P3.11
I/O0
IN19
I
IN19
I
IN19 Line of GPTA1
IN19
I
IN19 Line of LTCA2
OUT19
O1
OUT19 Line of GPTA0
OUT19
O2
OUT19 Line of GPTA1
OUT19
O3
OUT19 Line of LTCA2
C10
D13
Data Sheet
A1/
PU
A1/
PU
Port 3 General Purpose I/O Line 9
IN17 Line of GPTA0
Port 3 General Purpose I/O Line 10
IN18 Line of GPTA0
Port 3 General Purpose I/O Line 11
IN19 Line of GPTA0
76
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
D11
P3.12
I/O0
IN20
I
A1/
PU
IN20
I
IN20 Line of GPTA1
IN20
I
IN20 Line of LTCA2
OUT20
O1
OUT20 Line of GPTA0
OUT20
O2
OUT20 Line of GPTA1
OUT20
O3
OUT20 Line of LTCA2
P3.13
I/O0
IN21
I
IN21
I
IN21 Line of GPTA1
IN21
I
IN21 Line of LTCA2
OUT21
O1
OUT21 Line of GPTA0
OUT21
O2
OUT21 Line of GPTA1
OUT21
O3
OUT21 Line of LTCA2
P3.14
I/O0
IN22
I
IN22
I
IN22 Line of GPTA1
IN22
I
IN22 Line of LTCA2
OUT22
O1
OUT22 Line of GPTA0
OUT22
O2
OUT22 Line of GPTA1
OUT22
O3
OUT22 Line of LTCA2
D12
A10
Data Sheet
A1/
PU
A1/
PU
Port 3 General Purpose I/O Line 12
IN20 Line of GPTA0
Port 3 General Purpose I/O Line 13
IN21 Line of GPTA0
Port 3 General Purpose I/O Line 14
IN22 Line of GPTA0
77
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
B9
P3.15
I/O0
IN23
I
A1/
PU
IN23
I
IN23 Line of GPTA1
IN23
I
IN23 Line of LTCA2
OUT23
O1
OUT23 Line of GPTA0
OUT23
O2
OUT23 Line of GPTA1
OUT23
O3
OUT23 Line of LTCA2
P4.0
I/O0
IN24
I
IN24
I
IN24 Line of GPTA1
IN24
I
IN24 Line of LTCA2
OUT24
O1
OUT24 Line of GPTA0
OUT24
O2
OUT24 Line of GPTA1
OUT24
O3
OUT24 Line of LTCA2
P4.1
I/O0
IN25
I
IN25
I
IN25 Line of GPTA1
IN25
I
IN25 Line of LTCA2
OUT25
O1
OUT25 Line of GPTA0
OUT25
O2
OUT25 Line of GPTA1
OUT25
O3
OUT25 Line of LTCA2
Port 3 General Purpose I/O Line 15
IN23 Line of GPTA0
Port 4
AD10
AE10
Data Sheet
A2/
PU
A2/
PU
Port 4 General Purpose I/O Line 0
IN24 Line of GPTA0
Port 4 General Purpose I/O Line 1
IN25 Line of GPTA0
78
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
AD11
P4.2
I/O0
IN26
I
A2/
PU
IN26
I
IN26 Line of GPTA1
IN26
I
IN26 Line of LTCA2
OUT26
O1
OUT26 Line of GPTA0
OUT26
O2
OUT26 Line of GPTA1
OUT26
O3
OUT26 Line of LTCA2
P4.3
I/O0
IN27
I
IN27
I
IN27 Line of GPTA1
IN27
I
IN27 Line of LTCA2
OUT27
O1
OUT27 Line of GPTA0
OUT27
O2
OUT27 Line of GPTA1
OUT27
O3
OUT27 Line of LTCA2
P4.4
I/O0
IN28
I
IN28
I
IN28 Line of GPTA1
IN28
I
IN28 Line of LTCA2
OUT28
O1
OUT28 Line of GPTA0
OUT28
O2
OUT28 Line of GPTA1
OUT28
O3
OUT28 Line of LTCA2
AE11
AC12
Data Sheet
A2/
PU
A2/
PU
Port 4 General Purpose I/O Line 2
IN26 Line of GPTA0
Port 4 General Purpose I/O Line 3
IN27 Line of GPTA0
Port 4 General Purpose I/O Line 4
IN28 Line of GPTA0
79
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
AD12
P4.5
I/O0
IN29
I
A2/
PU
IN29
I
IN29 Line of GPTA1
IN29
I
IN29 Line of LTCA2
OUT29
O1
OUT29 Line of GPTA0
OUT29
O2
OUT29 Line of GPTA1
OUT29
O3
OUT29 Line of LTCA2
P4.6
I/O0
IN30
I
IN30
I
IN30 Line of GPTA1
IN30
I
IN30 Line of LTCA2
OUT30
O1
OUT30 Line of GPTA0
OUT30
O2
OUT30 Line of GPTA1
OUT30
O3
OUT30 Line of LTCA2
P4.7
I/O0
IN31
I
IN31
I
IN31 Line of GPTA1
IN31
I
IN31Line of LTCA2
OUT31
O1
OUT31 Line of GPTA0
OUT31
O2
OUT31 Line of GPTA1
OUT31
O3
OUT31 Line of LTCA2
AF10
AE12
Data Sheet
A2/
PU
A2/
PU
Port 4 General Purpose I/O Line 5
IN29 Line of GPTA0
Port 4 General Purpose I/O Line 6
IN30 Line of GPTA0
Port 4 General Purpose I/O Line 7
IN31 Line of GPTA0
80
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
AC13
P4.8
I/O0
IN32
I
A1/
PU
IN32
I
IN32 Line of GPTA1
OUT32
O1
OUT32 Line of GPTA0
OUT32
O2
OUT32 Line of GPTA1
OUT0
O3
OUT0 Line of LTCA2
P4.9
I/O0
IN33
I
IN33
I
IN33 Line of GPTA1
OUT33
O1
OUT33 Line of GPTA0
OUT33
O2
OUT33 Line of GPTA1
OUT1
O3
OUT1 Line of LTCA2
P4.10
I/O0
IN34
I
IN34
I
IN34 Line of GPTA1
OUT34
O1
OUT34 Line of GPTA0
OUT34
O2
OUT34 Line of GPTA1
OUT2
O3
OUT2 Line of LTCA2
P4.11
I/O0
IN35
I
IN35
I
IN35 Line of GPTA1
OUT35
O1
OUT35 Line of GPTA0
OUT35
O2
OUT35 Line of GPTA1
OUT3
O3
OUT3 Line of LTCA2
AF11
AF12
AD13
Data Sheet
A1/
PU
A1/
PU
A1/
PU
Port 4 General Purpose I/O Line 8
IN32 Line of GPTA0
Port 4 General Purpose I/O Line 9
IN33 Line of GPTA0
Port 4 General Purpose I/O Line 10
IN34 Line of GPTA0
Port 4 General Purpose I/O Line 11
IN35 Line of GPTA0
81
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
AC14
P4.12
I/O0
IN36
I
A1/
PU
IN36
I
IN36 Line of GPTA1
OUT36
O1
OUT36 Line of GPTA0
OUT36
O2
OUT36 Line of GPTA1
OUT4
O3
OUT4 Line of LTCA2
P4.13
I/O0
IN37
I
IN37
I
IN37 Line of GPTA1
OUT37
O1
OUT37 Line of GPTA0
OUT37
O2
OUT37 Line of GPTA1
OUT5
O3
OUT5 Line of LTCA2
P4.14
I/O0
IN38
I
IN38
I
IN38 Line of GPTA1
OUT38
O1
OUT38 Line of GPTA0
OUT38
O2
OUT38 Line of GPTA1
OUT6
O3
OUT6 Line of LTCA2
P4.15
I/O0
IN39
I
IN39
I
IN39 Line of GPTA1
OUT39
O1
OUT39 Line of GPTA0
OUT39
O2
OUT39 Line of GPTA1
OUT7
O3
OUT7 Line of LTCA2
AE13
AF13
AD14
A1/
PU
A1/
PU
A1/
PU
Port 4 General Purpose I/O Line 12
IN36 Line of GPTA0
Port 4 General Purpose I/O Line 13
IN37 Line of GPTA0
Port 4 General Purpose I/O Line 14
IN38 Line of GPTA0
Port 4 General Purpose I/O Line 15
IN39 Line of GPTA0
Port 5
Data Sheet
82
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
B13
P5.0
I/O0
RXD0A
I
A2/
PU
RXD0A
O1
ASC0 Receiver Input/Output A
OUT72
O2
OUT72 Line of GPTA0
OUT72
O3
OUT72 Line of GPTA1
P5.1
I/O0
TXD0
O1
OUT73
O2
OUT73 Line of GPTA0
OUT73
O3
OUT73 Line of GPTA1
P5.2
I/O0
RXD1A
I
RXD1A
O1
ASC1 Receiver Input/Output A
OUT74
O2
OUT74 Line of GPTA0
OUT74
O3
OUT74 Line of GPTA1
P5.3
I/O0
TXD1
O1
OUT75
O2
OUT75 Line of GPTA0
OUT75
O3
OUT75 Line of GPTA1
P5.4
I/O0
EN00
O1
RREADY0B
O2
MLI0 Receive Channel ready Output B
OUT76
O3
OUT76 Line of GPTA0
A13
A14
B14
C15
Data Sheet
A2/
PU
A2/
PU
A2/
PU
A2/
PU
Port 5 General Purpose I/O Line 0
ASC0 Receiver Input/Output A
Port 5 General Purpose I/O Line 1
ASC0 Transmitter Output A
Port 5 General Purpose I/O Line 2
ASC1 Receiver Input/Output A
Port 5 General Purpose I/O Line 3
ASC1 Transmitter Output A
Port 5 General Purpose I/O Line 4
MSC0 Device Select Output 0
83
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
C14
P5.5
I/O0
SDI0
I
A2/
PU
OUT77
O1
OUT77 Line of GPTA0
OUT77
O2
OUT77 Line of GPTA1
OUT101
O3
OUT101 Line of LTCA2
P5.6
I/O0
EN10
O1
TVALID0B
O2
MLI0 Transmit Channel valid Output B
OUT78
O3
OUT78 Line of GPTA0
P5.7
I/O0
SDI1
I
OUT79
O1
OUT79 Line of GPTA0
OUT79
O2
OUT79 Line of GPTA1
OUT103
O3
OUT103 Line of LTCA2
P5.8
I/O0
SON0
O1
OUT80
O2
OUT80 Line of GPTA0
OUT80
O3
OUT 80 Line of GPTA1
P5.9
I/O0
SOP0A
O1
OUT81
O2
OUT81 Line of GPTA0
OUT81
O3
OUT81 Line of GPTA1
B15
A15
D17
C16
Data Sheet
A2/
PU
A2/
PU
F/
PU
F/
PU
Port 5 General Purpose I/O Line 5
MSC0 serial Data Input
Port 5 General Purpose I/O Line 6
MSC1 Device Select Output 0
Port 5 General Purpose I/O Line 7
MSC1 serial Data Input
Port 5 General Purpose I/O Line 8
MSC0 Differential Driver serial Data Output
Negative
Port 5 General Purpose I/O Line 9
MSC0 Differential Driver serial Data Output
Positive A
84
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
C17
P5.10
I/O0
FCLN0
O1
F/
PU
OUT82
O2
OUT82 Line of GPTA0
OUT82
O3
OUT82 Line of GPTA1
P5.11
I/O0
FCLP0A
O1
OUT83
O2
OUT83 Line of GPTA0
OUT83
O3
OUT83 Line of GPTA1
P5.12
I/O0
SON1
O1
OUT84
O2
OUT84 Line of GPTA0
OUT84
O3
OUT84 Line of GPTA1
P5.13
I/O0
SOP1A
O1
OUT85
O2
OUT85 Line of GPTA0
OUT85
O3
OUT85 Line of GPTA1
P5.14
I/O0
FCLN1
O1
OUT86
O2
OUT86 Line of GPTA0
OUT86
O3
OUT86 Line of GPTA1
C18
A16
B16
B17
Data Sheet
F/
PU
F/
PU
F/
PU
F/
PU
Port 5 General Purpose I/O Line 10
MSC0 Differential Driver Clock Output
Negative
Port 5 General Purpose I/O Line 11
MSC0 Differential Driver Clock Output
Positive A
Port 5 General Purpose I/O Line 12
MSC1 Differential Driver serial Data
OutputNegative
Port 5 General Purpose I/O Line 13
MSC1 Differential Driver serial Data Output
Positive A
Port 5 General Purpose I/O Line 14
MSC1 Differential Driver Clock Output
Negative
85
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
A17
P5.15
I/O0
FCLNP1A
O1
F/
PU
OUT87
O2
OUT87 Line of GPTA0
OUT87
O3
OUT87 Line of GPTA1
P6.4
I/O0
MTSR1
I
MTSR1
O1
SSC1 Master Transmit Output (Master
Mode)
Reserved
O2
-
Reserved
O3
-
P6.5
I/O0
MRST1
I
MRST1
O1
SSC1 Slave Transmit Output (Slave Mode)
Reserved
O2
-
Reserved
O3
-
P6.6
I/O0
SCLK1
I
SCLK1
O1
SSC1 Clock Input/Output
Reserved
O2
-
Reserved
O3
-
Port 5 General Purpose I/O Line 15
MSC1 Differential Driver Clock Output
Positive A
Port 6
F3
G4
E3
Data Sheet
A2/
PU
A2/
PU
A2/
PU
Port 6 General Purpose I/O Line 4
SSC1 Slave Receive Input (Slave Mode)
Port 6 General Purpose I/O Line 5
SSC1 Master Receive Input (Master Mode)
Port 6 General Purpose I/O Line 6
SSC1 Clock Input/Output
86
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
G3
P6.7
I/O0
SLSI11
I
A2/
PU
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
P6.8
I/O0
RXDCAN0
I
RXD0B
I
ASC0 Receiver Input/Output B
Reserved
O1
-
RXD0B
O2
ASC0 Receiver Input/Output B
Reserved
O3
-
P6.9
I/O0
TXDCAN0
O1
TXD0
O2
ASC0 Transmitter Output B
Reserved
O3
-
P6.10
I/O0
RXDCAN1
I
RXD1B
I
ASC1 Receiver Input/Output B
Reserved
O1
-
RXD1B
O2
ASC1 Receiver Input/Output B
TXENA
O3
E-Ray Channel A Transmit Data Output
enable
F4
E4
F2
Data Sheet
A2/
PU
A2/
PU
A2/
PU
Port 6 General Purpose I/O Line 7
SSC1 Slave Select Input
Port 6 General Purpose I/O Line 8
CAN Node 0 Receiver Input 0
CAN Node 3 Receiver Input 1
Port 6 General Purpose I/O Line 9
CAN Node 0 Transmitter Output
Port 6 General Purpose I/O Line 10
CAN Node 1 Receiver Input 0
CAN Node 0 Receiver Input 1
87
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
E2
P6.11
I/O0
TXDCAN1
O1
A2/
PU
TXD1
O2
ASC1 Transmitter Output B
TXENB
O3
E-Ray Channel B Transmit Data Output
enable
P6.12
I/O0
RXDCAN2
I
RXDA1
I
E-Ray Channel A Receive Data Input 1
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
P6.13
I/O0
TXDCAN2
O1
TXDA
O2
E-Ray Channel A Transmit Data Output
Reserved
O3
-
P6.14
I/O0
RXDCAN3
I
RXDB1
I
E-Ray Channel B Receive Data Input 1
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
P6.15
I/O0
TXDCAN3
O1
TXDB
O2
E-Ray Channel B Transmit Data Output
Reserved
O3
-
E1
G2
F1
G1
Data Sheet
A1/
PU
A2/
PU
A1/
PU
A2/
PU
Port 6 General Purpose I/O Line 11
CAN Node 1 Transmitter Output
Port 6 General Purpose I/O Line 12
CAN Node 2 Receiver Input 0
CAN Node 1 Receiver Input 1
Port 6 General Purpose I/O Line 13
CAN Node 2 Transmitter Output
Port 6 General Purpose I/O Line 14
CAN Node 3 Receiver Input 0
CAN Node 2 Receiver Input 1
Port 6 General Purpose I/O Line 15
CAN Node 3 Transmitter Output
88
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol
Ctrl.
Type Function
P7.0
I/O0
REQ4
I
A1/
PU
AD2EMUX2
O1
ADC2 external multiplexer Control Output 2
Reserved
O2
-
Reserved
O3
-
P7.1
I/O0
REQ5
I
AD0EMUX2
O1
ADC0 external multiplexer Control Output 2
Reserved
O2
-
Reserved
O3
-
P7.2
I/O0
AD0EMUX0
O1
Reserved
O2
-
Reserved
O3
-
P7.3
I/O0
AD0EMUX1
O1
Reserved
O2
-
Reserved
O3
-
P7.4
I/O0
REQ6
I
AD2EMUX0
O1
ADC2 external multiplexer Control Output 0
Reserved
O2
-
Reserved
O3
-
Port 7
R3
R2
U4
U3
T3
Data Sheet
A1/
PU
A1/
PU
A1/
PU
A1/
PU
Port 7 General Purpose I/O Line 0
External trigger Input 4
Port 7 General Purpose I/O Line 1
External trigger Input 5
Port 7 General Purpose I/O Line 2
ADC0 external multiplexer Control Output 0
Port 7 General Purpose I/O Line 3
ADC0 external multiplexer Control Output 1
Port 7 General Purpose I/O Line 4
External trigger Input 6
89
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
T2
P7.5
I/O0
REQ7
I
A1/
PU
AD2EMUX1
O1
ADC2 external multiplexer Control Output 1
Reserved
O2
-
Reserved
O3
-
P7.6
I/O0
AD1EMUX0
O1
Reserved
O2
-
Reserved
O3
-
P7.7
I/O0
AD1EMUX1
O1
Reserved
O2
-
Reserved
O3
-
P8.0
I/O0
IN40
I
IN40
I
I/O Line of GPTA1
OUT40
O1
I/O Line of GPTA0
OUT40
O2
I/O Line of GPTA1
TCLK1
O3
MLI1 Transmit Channel Clock Output
T1
U2
A1/
PU
A1/
PU
Port 7 General Purpose I/O Line 5
External trigger Input 7
Port 7 General Purpose I/O Line 6
ADC1 external multiplexer Control Output 0
Port 7 General Purpose I/O Line 7
ADC1 external multiplexer Control Output 1
Port 8
H2
Data Sheet
A2/
PU
Port 8 General Purpose I/O Line 0
I/O Line of GPTA0
90
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
H1
P8.1
I/O0
IN41
I
A1/
PU
IN41
I
I/O Line of GPTA1
TREADY1A
I
MLI1 Transmit Channel ready Input A
OUT41
O1
I/O Line of GPTA0
OUT41
O2
I/O Line of GPTA1
Reserved
O3
-
P8.2
I/O0
IN42
I
IN42
I
I/O Line of GPTA1
OUT42
O1
I/O Line of GPTA0
OUT42
O2
I/O Line of GPTA1
TVALID1A
O3
MLI1 Transmit Channel valid Output A
P8.3
I/O0
IN43
I
IN43
I
I/O Line of GPTA1
OUT43
O1
I/O Line of GPTA0
OUT43
O2
I/O Line of GPTA1
TData1
O3
MLI1 Transmit Channel Data Output A
P8.4
I/O0
IN44
I
IN44
I
I/O Line of GPTA1
RCLK1A
I
MLI1 Receive Channel Clock Input A
OUT44
O1
I/O Line of GPTA0
OUT44
O2
I/O Line of GPTA1
Reserved
O3
-
J3
J2
J1
Data Sheet
A2/
PU
A2/
PU
A1/
PU
Port 8 General Purpose I/O Line 1
I/O Line of GPTA0
Port 8 General Purpose I/O Line 2
I/O Line of GPTA0
Port 8 General Purpose I/O Line 3
I/O Line of GPTA0
Port 8 General Purpose I/O Line 4
I/O Line of GPTA0
91
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
K2
P8.5
I/O0
IN45
I
A2/
PU
IN45
I
I/O Line of GPTA1
OUT45
O1
I/O Line of GPTA0
OUT45
O2
I/O Line of GPTA1
RREADY1A
O3
MLI1 Receive Channel ready Output A
P8.6
I/O0
IN46
I
IN46
I
I/O Line of GPTA1
RVALID1A
I
MLI1 Receive Channel valid Input A
OUT46
O1
I/O Line of GPTA0
OUT46
O2
I/O Line of GPTA1
Reserved
O3
-
P8.7
I/O0
IN47
I
IN47
I
I/O Line of GPTA1
RData1A
I
MLI1 Receive Channel Data Input A
OUT47
O1
I/O Line of GPTA0
OUT47
O2
I/O Line of GPTA1
Reserved
O3
-
K3
K1
A1/
PU
A1/
PU
Port 8 General Purpose I/O Line 5
I/O Line of GPTA0
Port 8 General Purpose I/O Line 6
I/O Line of GPTA0
Port 8 General Purpose I/O Line 7
I/O Line of GPTA0
Port 9
Data Sheet
92
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
A19
P9.0
I/O0
IN48
I
A2/
PU
IN48
I
I/O Line of GPTA1
OUT48
O1
I/O Line of GPTA0
OUT48
O2
I/O Line of GPTA1
EN12
O3
MSC1 Device Select Output 2
P9.1
I/O0
IN49
I
IN49
I
I/O Line of GPTA1
OUT49
O1
I/O Line of GPTA0
OUT49
O2
I/O Line of GPTA1
EN11
O3
MSC1 Device Select Output 1
P9.2
I/O0
IN50
I
IN50
I
I/O Line of GPTA1
OUT50
O1
I/O Line of GPTA0
OUT50
O2
I/O Line of GPTA1
SOP1B
O3
MSC1 serial Data Output
P9.3
I/O0
IN51
I
IN51
I
I/O Line of GPTA1
OUT51
O1
I/O Line of GPTA0
OUT51
O2
I/O Line of GPTA1
FCLP1B
O3
MSC1 Clock Output
B19
B20
A20
Data Sheet
A2/
PU
A2/
PU
A2/
PU
Port 9 General Purpose I/O Line 0
I/O Line of GPTA0
Port 9 General Purpose I/O Line 1
I/O Line of GPTA0
Port 9 General Purpose I/O Line 2
I/O Line of GPTA0
Port 9 General Purpose I/O Line 3
I/O Line of GPTA0
93
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
D18
P9.4
I/O0
IN52
I
A2/
PU
IN52
I
I/O Line of GPTA1
OUT52
O1
I/O Line of GPTA0
OUT52
O2
I/O Line of GPTA1
EN03
O3
MSC0 Device Select Output 3
P9.5
I/O0
IN53
I
IN53
I
I/O Line of GPTA1
OUT53
O1
I/O Line of GPTA0
OUT53
O2
I/O Line of GPTA1
EN02
O3
MSC0 Device Select Output 2
P9.6
I/O0
IN54
I
IN54
I
I/O Line of GPTA1
OUT54
O1
I/O Line of GPTA0
OUT54
O2
I/O Line of GPTA1
EN01
O3
MSC0 Device Select Output 1
P9.7
I/O0
IN55
I
IN55
I
I/O Line of GPTA1
OUT55
O1
I/O Line of GPTA0
OUT55
O2
I/O Line of GPTA1
SOP0B
O3
MSC0 serial Data Output
’D19
C19
D20
Data Sheet
A2/
PU
A2/
PU
A2/
PU
Port 9 General Purpose I/O Line 4
I/O Line of GPTA0
Port 9 General Purpose I/O Line 5
I/O Line of GPTA0
Port 9 General Purpose I/O Line 6
I/O Line of GPTA0
Port 9 General Purpose I/O Line 7
I/O Line of GPTA0
94
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
C20
P9.8
I/O0
FCLP0B
O1
A2/
PU
FCLP0B
O2
MSC0 Clock Output
FCLP0B
O3
MSC0 Clock Output
P9.9
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
P9.10
I/O0
EMGSTOP
I
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
P9.11
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
P9.12
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A21
B21
C21
D21
Data Sheet
A1/
PU
A1/
PU
A1/
PU
A1/
PU
Port 9 General Purpose I/O Line 8
MSC0 Clock Output
Port 9 General Purpose I/O Line 9
-
Port 9 General Purpose I/O Line 10
Emergency Stop
Port 9 General Purpose I/O Line 11
-
Port 9 General Purpose I/O Line 12
-
95
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
C26
P9.13
I/O0
BRKIN
I
A2/
PU
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
BRKOUT
O
OCDS Break Output
P9.14
I/O0
BRKIN
I
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
BRKOUT
O
OCDS Break Output
P10.0
I/O0
MRST0
I
MRST0
O1
SSC0 Slave Transmit Output (Slave Mode)
Reserved
O2
-
Reserved
O3
-
P10.1
I/O0
MTSR0
I
MTSR0
O1
SSC0 Master Transmit Output (Master
Mode)
Reserved
O2
-
Reserved
O3
-
D26
A2/
PU
Port 9 General Purpose I/O Line 13
OCDS Break Input
Port 9 General Purpose I/O Line 14
OCDS Break Input
Port 10
AE15
AF15
Data Sheet
A2/
PU
A2/
PU
Port 10 General Purpose I/O Line 0
SSC0 Master Receive Input (Master Mode)
Port 10 General Purpose I/O Line 1
SSC0 Slave Receive Input (Slave Mode)
96
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
AD15
P10.2
I/O0
SLSI01
I
A1/
PU
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
P10.3
I/O0
SCLK0
I
SCLK0
O1
SSC0 Clock Input/Output
Reserved
O2
-
Reserved
O3
-
P10.4
I/O0
SLSO00
O1
Reserved
O2
-
Reserved
O3
-
P10.5
I/O0
SLSO01
O1
Reserved
O2
-
Reserved
O3
-
P11.0
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A0
O
EBU Address Bus Line 0
AF14
AE14
AC15
A2/
PU
A2/
PU
A2/
PU
Port 10 General Purpose I/O Line 2
SSC0 Slave Select Input
Port 10 General Purpose I/O Line 3
SSC0 Clock Input/Output
Port 10 General Purpose I/O Line 4
SSC0 Slave Select Output Line 0
Port 10 General Purpose I/O Line 5
SSC0 Slave Select Output Line 1
Port 11
J26
Data Sheet
B1/
PU
Port 11 General Purpose I/O Line 0
-
97
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
K25
P11.1
I/O0
Reserved
O1
B1/
PU
Reserved
O2
-
Reserved
O3
-
A1
O
EBU Address Bus Line 1
P11.2
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A2
O
EBU Address Bus Line 2
P11.3
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A3
O
EBU Address Bus Line 3
P11.4
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A4
O
EBU Address Bus Line 4
P11.5
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A5
O
EBU Address Bus Line 5
K26
J23
K24
L25
Data Sheet
B1/
PU
B1/
PU
B1/
PU
B1/
PU
Port 11 General Purpose I/O Line 1
-
Port 11 General Purpose I/O Line 2
-
Port 11 General Purpose I/O Line 3
-
Port 11 General Purpose I/O Line 4
-
Port 11 General Purpose I/O Line 5
-
98
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
L26
P11.6
I/O0
Reserved
O1
B1/
PU
Reserved
O2
-
Reserved
O3
-
A6
O
EBU Address Bus Line 6
P11.7
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A7
O
EBU Address Bus Line 7
P11.8
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A8
O
EBU Address Bus Line 8
P11.9
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A9
O
EBU Address Bus Line 9
P11.10
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A10
O
EBU Address Bus Line 10
K23
M26
M25
M24
Data Sheet
B1/
PU
B1/
PU
B1/
PU
B1/
PU
Port 11 General Purpose I/O Line 6
-
Port 11 General Purpose I/O Line 7
-
Port 11 General Purpose I/O Line 8
-
Port 11 General Purpose I/O Line 9
-
Port 11 General Purpose I/O Line 10
-
99
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
L24
P11.11
I/O0
Reserved
O1
B1/
PU
Reserved
O2
-
Reserved
O3
-
A11
O
EBU Address Bus Line 11
P11.12
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A12
O
EBU Address Bus Line 12
P11.13
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A13
O
EBU Address Bus Line 13
P11.14
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A14
O
EBU Address Bus Line 14
P11.15
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A15
O
EBU Address Bus Line 15
N26
N23
N24
N25
B1/
PU
B1/
PU
B1/
PU
B1/
PU
Port 11 General Purpose I/O Line 11
-
Port 11 General Purpose I/O Line 12
-
Port 11 General Purpose I/O Line 13
-
Port 11 General Purpose I/O Line 14
-
Port 11 General Purpose I/O Line 15
-
Port 12
Data Sheet
100
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
P26
P12.0
I/O0
Reserved
O1
B1/
PU
Reserved
O2
-
Reserved
O3
-
A16
O
EBU Address Bus Line 16
P12.1
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A17
O
EBU Address Bus Line 17
P12.2
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A18
O
EBU Address Bus Line 18
P12.3
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A19
O
EBU Address Bus Line 19
P12.4
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A20
O
EBU Address Bus Line 20
P24
P25
R24
R26
Data Sheet
B1/
PU
B1/
PU
B1/
PU
B1/
PU
Port 12 General Purpose I/O Line 0
-
Port 12 General Purpose I/O Line 1
-
Port 12 General Purpose I/O Line 2
-
Port 12 General Purpose I/O Line 3
-
Port 12 General Purpose I/O Line 4
-
101
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
R25
P12.5
I/O0
Reserved
O1
B1/
PU
Reserved
O2
-
Reserved
O3
-
A21
O
EBU Address Bus Line 21
P12.6
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A22
O
EBU Address Bus Line 22
P12.7
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A23
O
EBU Address Bus Line 23
P13.0
I/O0
AD0
I
OUT88
O1
OUT88 Line of GPTA0
OUT88
O2
OUT88 Line of GPTA1
OUT80
O3
OUT80 Line of LTCA2
AD0
O
EBU Address/Data Bus Line 0
J24
J25
B1/
PU
B1/
PU
Port 12 General Purpose I/O Line 5
-
Port 12 General Purpose I/O Line 6
-
Port 12 General Purpose I/O Line 7
-
Port 13
T26
Data Sheet
B1/
PU
Port 13 General Purpose I/O Line 0
EBU Address/Data Bus Line 0
102
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
T24
P13.1
I/O0
AD1
I
B1/
PU
OUT89
O1
OUT89 Line of GPTA0
OUT89
O2
OUT89 Line of GPTA1
OUT81
O3
OUT81 Line of LTCA2
AD1
O
EBU Address/Data Bus Line 1
P13.2
I/O0
AD2
I
OUT90
O1
OUT90 Line of GPTA0
OUT90
O2
OUT90 Line of GPTA1
OUT82
O3
OUT82 Line of LTCA2
AD2
O
EBU Address/Data Bus Line 2
P13.3
I/O0
AD3
I
OUT91
O1
OUT91 Line of GPTA0
OUT91
O2
OUT91 Line of GPTA1
OUT83
O3
OUT83 Line of LTCA2
AD3
O
EBU Address/Data Bus Line 3
P13.4
I/O0
AD4
I
OUT92
O1
OUT92 Line of GPTA0
OUT92
O2
OUT92 Line of GPTA1
OUT84
O3
OUT84 Line of LTCA2
AD4
O
EBU Address/Data Bus Line 4
U26
T25
V26
Data Sheet
B1/
PU
B1/
PU
B1/
PU
Port 13 General Purpose I/O Line 1
EBU Address/Data Bus Line 1
Port 13 General Purpose I/O Line 2
EBU Address/Data Bus Line 2
Port 13 General Purpose I/O Line 3
EBU Address/Data Bus Line 3
Port 13 General Purpose I/O Line 4
EBU Address/Data Bus Line 4
103
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
U25
P13.5
I/O0
AD5
I
B1/
PU
OUT93
O1
OUT93 Line of GPTA0
OUT93
O2
OUT93 Line of GPTA1
OUT85
O3
OUT85 Line of LTCA2
AD5
O
EBU Address/Data Bus Line 5
P13.6
I/O0
AD6
I
OUT94
O1
OUT94 Line of GPTA0
OUT94
O2
OUT94 Line of GPTA1
OUT86
O3
OUT86 Line of LTCA2
AD6
O
EBU Address/Data Bus Line 6
P13.7
I/O0
AD7
I
OUT95
O1
OUT95 Line of GPTA0
OUT95
O2
OUT95 Line of GPTA1
OUT87
O3
OUT87 Line of LTCA2
AD7
O
EBU Address/Data Bus Line 7
P13.8
I/O0
AD8
I
OUT96
O1
OUT96 Line of GPTA0
OUT96
O2
OUT96 Line of GPTA1
OUT88
O3
OUT88 Line of LTCA2
AD8
O
EBU Address/Data Bus Line 8
U23
W26
V25
Data Sheet
B1/
PU
B1/
PU
B1/
PU
Port 13 General Purpose I/O Line 5
EBU Address/Data Bus Line 5
Port 13 General Purpose I/O Line 6
EBU Address/Data Bus Line 6
Port 13 General Purpose I/O Line 7
EBU Address/Data Bus Line 7
Port 13 General Purpose I/O Line 8
EBU Address/Data Bus Line 8
104
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
U24
P13.9
I/O0
AD9
I
B1/
PU
OUT97
O1
OUT97 Line of GPTA0
OUT97
O2
OUT97 Line of GPTA1
OUT89
O3
OUT89 Line of LTCA2
AD9
O
EBU Address/Data Bus Line 9
P13.10
I/O0
AD10
I
OUT98
O1
OUT98 Line of GPTA0
OUT98
O2
OUT98 Line of GPTA1
OUT90
O3
OUT90 Line of LTCA2
AD10
O
EBU Address/Data Bus Line 10
P13.11
I/O0
AD11
I
OUT99
O1
OUT99 Line of GPTA0
OUT99
O2
OUT99 Line of GPTA1
OUT91
O3
OUT91 Line of LTCA2
AD11
O
EBU Address/Data Bus Line 11
P13.12
I/O0
AD12
I
OUT100
O1
OUT100 Line of GPTA0
OUT100
O2
OUT100 Line of GPTA1
OUT92
O3
OUT92 Line of LTCA2
AD12
O
EBU Address/Data Bus Line 12
Y26
AA26
W25
Data Sheet
B1/
PU
B1/
PU
B1/
PU
Port 13 General Purpose I/O Line 9
EBU Address/Data Bus Line 9
Port 13 General Purpose I/O Line 10
EBU Address/Data Bus Line 10
Port 13 General Purpose I/O Line 11
EBU Address/Data Bus Line 11
Port 13 General Purpose I/O Line 12
EBU Address/Data Bus Line 12
105
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
V24
P13.13
I/O0
AD13
I
B1/
PU
OUT101
O1
OUT101 Line of GPTA0
OUT101
O2
OUT101 Line of GPTA1
OUT93
O3
OUT93 Line of LTCA2
AD13
O
EBU Address/Data Bus Line 13
P13.14
I/O0
AD14
I
OUT102
O1
OUT102 Line of GPTA0
OUT102
O2
OUT102 Line of GPTA1
OUT94
O3
OUT94 Line of LTCA2
AD14
O
EBU Address/Data Bus Line 14
P13.15
I/O0
AD15
I
OUT103
O1
OUT103 Line of GPTA0
OUT103
O2
OUT103 Line of GPTA1
OUT95
O3
OUT95 Line of LTCA2
AD15
O
EBU Address/Data Bus Line 15
P14.0
I/O0
AD16
I
OUT96
O1
OUT96 Line of GPTA0
OUT96
O2
OUT96 Line of GPTA1
OUT96
O3
OUT96 Line of LTCA2
AD16
O
EBU Address/Data Bus Line 16
Y25
AB26
B1/
PU
B1/
PU
Port 13 General Purpose I/O Line 13
EBU Address/Data Bus Line 13
Port 13 General Purpose I/O Line 14
EBU Address/Data Bus Line 14
Port 13 General Purpose I/O Line 15
EBU Address/Data Bus Line 15
Port 14
W24
Data Sheet
B1/
PU
Port 14 General Purpose I/O Line 0
EBU Address/Data Bus Line 16
106
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
AA25
P14.1
I/O0
AD17
I
B1/
PU
OUT97
O1
OUT97 Line of GPTA0
OUT97
O2
OUT97 Line of GPTA1
OUT97
O3
OUT97 Line of LTCA2
AD17
O
EBU Address/Data Bus Line 17
P14.2
I/O0
AD18
I
OUT98
O1
OUT98 Line of GPTA0
OUT98
O2
OUT98 Line of GPTA1
OUT98
O3
OUT98 Line of LTCA2
AD18
O
EBU Address/Data Bus Line 18
P14.3
I/O0
AD19
I
OUT99
O1
OUT99 Line of GPTA0
OUT99
O2
OUT99 Line of GPTA1
OUT99
O3
OUT99 Line of LTCA2
AD19
O
EBU Address/Data Bus Line 19
P14.4
I/O0
AD20
I
OUT100
O1
OUT100 Line of GPTA0
OUT100
O2
OUT100 Line of GPTA1
OUT100
O3
OUT100 Line of LTCA2
AD20
O
EBU Address/Data Bus Line 20
Y24
AA23
AB25
Data Sheet
B1/
PU
B1/
PU
B1/
PU
Port 14 General Purpose I/O Line 1
EBU Address/Data Bus Line 17
Port 14 General Purpose I/O Line 2
EBU Address/Data Bus Line 18
Port 14 General Purpose I/O Line 3
EBU Address/Data Bus Line 19
Port 14 General Purpose I/O Line 4
EBU Address/Data Bus Line 20
107
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
AB24
P14.5
I/O0
AD21
I
B1/
PU
OUT101
O1
OUT101 Line of GPTA0
OUT101
O2
OUT101 Line of GPTA1
OUT101
O3
OUT101 Line of LTCA2
AD21
O
EBU Address/Data Bus Line 21
P14.6
I/O0
AD22
I
OUT102
O1
OUT102 Line of GPTA0
OUT102
O2
OUT102 Line of GPTA1
OUT102
O3
OUT102 Line of LTCA2
AD22
O
EBU Address/Data Bus Line 22
P14.7
I/O0
AD23
I
OUT103
O1
OUT103 Line of GPTA0
OUT103
O2
OUT103 Line of GPTA1
OUT103
O3
OUT103 Line of LTCA2
AD23
O
EBU Address/Data Bus Line 23
P14.8
I/O0
AD24
I
OUT104
O1
OUT104 Line of GPTA0
OUT104
O2
OUT104 Line of GPTA1
OUT104
O3
OUT104 Line of LTCA2
AD24
O
EBU Address/Data Bus Line 24
AA24
AC26
AD26
Data Sheet
B1/
PU
B1/
PU
B1/
PU
Port 14 General Purpose I/O Line 5
EBU Address/Data Bus Line 21
Port 14 General Purpose I/O Line 6
EBU Address/Data Bus Line 22
Port 14 General Purpose I/O Line 7
EBU Address/Data Bus Line 23
Port 14 General Purpose I/O Line 8
EBU Address/Data Bus Line 24
108
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
AC25
P14.9
I/O0
AD25
I
B1/
PU
OUT105
O1
OUT105 Line of GPTA0
OUT105
O2
OUT105 Line of GPTA1
OUT105
O3
OUT105 Line of LTCA2
AD25
O
EBU Address/Data Bus Line 25
P14.10
I/O0
AD26
I
OUT106
O1
OUT106 Line of GPTA0
OUT106
O2
OUT106 Line of GPTA1
OUT106
O3
OUT106 Line of LTCA2
AD26
O
EBU Address/Data Bus Line 26
P14.11
I/O0
AD27
I
OUT107
O1
OUT107 Line of GPTA0
OUT107
O2
OUT107 Line of GPTA1
OUT107
O3
OUT107 Line of LTCA2
AD27
O
EBU Address/Data Bus Line 27
P14.12
I/O0
AD28
I
OUT108
O1
OUT108 Line of GPTA0
OUT108
O2
OUT108 Line of GPTA1
OUT108
O3
OUT108 Line of LTCA2
AD28
O
EBU Address/Data Bus Line 28
AE26
AD25
AC24
Data Sheet
B1/
PU
B1/
PU
B1/
PU
Port 14 General Purpose I/O Line 9
EBU Address/Data Bus Line 25
Port 14 General Purpose I/O Line 10
EBU Address/Data Bus Line 26
Port 14 General Purpose I/O Line 11
EBU Address/Data Bus Line 27
Port 14 General Purpose I/O Line 12
EBU Address/Data Bus Line 28
109
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
AE25
P14.13
I/O0
AD29
I
B1/
PU
OUT109
O1
OUT109 Line of GPTA0
OUT109
O2
OUT109 Line of GPTA1
OUT109
O3
OUT109 Line of LTCA2
AD29
O
EBU Address/Data Bus Line 29
P14.14
I/O0
AD30
I
OUT110
O1
OUT110 Line of GPTA0
OUT110
O2
OUT110 Line of GPTA1
OUT110
O3
OUT110 Line of LTCA2
AD30
O
EBU Address/Data Bus Line 30
P14.15
I/O0
AD31
I
OUT111
O1
OUT111 Line of GPTA0
OUT111
O2
OUT111 Line of GPTA1
OUT111
O3
OUT111 Line of LTCA2
AD31
O
EBU Address/Data Bus Line 31
P15.0
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
CS0
O
Chip Select Output Line 0
AE24
AD24
B1/
PU
B1/
PU
Port 14 General Purpose I/O Line 13
EBU Address/Data Bus Line 29
Port 14 General Purpose I/O Line 14
EBU Address/Data Bus Line 30
Port 14 General Purpose I/O Line 15
EBU Address/Data Bus Line 31
Port 15
AE21
Data Sheet
B1/
PU
Port 15 General Purpose I/O Line 0
-
110
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
AD21
P15.1
I/O0
Reserved
O1
B1/
PU
Reserved
O2
-
Reserved
O3
-
CS1
O
Chip Select Output Line 1
P15.2
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
CS2
O
Chip Select Output Line 2
P15.3
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
CS3
O
Chip Select Output Line 3
P15.4
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
BC0
O
Byte Control Line 0
P15.5
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
BC1
O
Byte Control Line 1
AD20
AD19
AE17
AD17
Data Sheet
B1/
PU
B1/
PU
B1/
PU
B1/
PU
Port 15 General Purpose I/O Line 1
-
Port 15 General Purpose I/O Line 2
-
Port 15 General Purpose I/O Line 3
-
Port 15 General Purpose I/O Line 4
-
Port 15 General Purpose I/O Line 5
-
111
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
AF18
P15.6
I/O0
Reserved
O1
B1/
PU
Reserved
O2
-
Reserved
O3
-
BC2
O
Byte Control Line 2
P15.7
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
BC3
O
Byte Control Line 3
P15.8
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
RD
O
Read Control Line
P15.9
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
RD/WR
O
Write Control Line
P15.10
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
ADV
O
Address Valid Output
AE18
AF20
AF21
AF22
Data Sheet
B1/
PU
B1/
PU
B1/
PU
B1/
PU
Port 15 General Purpose I/O Line 6
-
Port 15 General Purpose I/O Line 7
-
Port 15 General Purpose I/O Line 8
-
Port 15 General Purpose I/O Line 9
-
Port 15 General Purpose I/O Line 10
-
112
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
AE20
P15.11
I/O0
WAIT
I
B1/
PU
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
P15.12
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
MR/W
O
Motorola-style Read/Write Control Signal
P15.13
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
BAA
O
Burst Address Advance Output
P15.14
I/O0
BFCLKI
I
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
P15.15
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
BFCLKO
O
Burst Mode Flash Clock Output (NonDifferential)
AF19
AF23
AF24
AF25
Data Sheet
B1/
PU
B1/
PU
B1/
PU
B2/
PU
Port 15 General Purpose I/O Line 11
Wait Input for inserting Wait-States
Port 15 General Purpose I/O Line 12
-
Port 15 General Purpose I/O Line 13
-
Port 15 General Purpose I/O Line 14
Burst FLASH Clock Input (Clock Feedback).
Port 15 General Purpose I/O Line 15
-
113
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol
Ctrl.
Type Function
P16.0
I/O0
HOLD
I
B1/
PU
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
P16.1
I/O0
HLDA
I
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
HLDA
O
Hold Acknowledge Output
P16.2
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
BREQ
O
Bus Request Output
P16.3
I/O0
Reserved
O1
Reserved
O2
-
Reserved
O3
-
CSCOMB
O
Combined Chip Select Output
Port 16
AF17
AD18
AD22
AE19
B1/
PU
B1/
PU
B1/
PU
Port 16 General Purpose I/O Line 0
Hold Request Input
Port 16 General Purpose I/O Line 1
Hold Acknowledge Output
Port 16 General Purpose I/O Line 2
-
Port 16 General Purpose I/O Line 3
-
Analog Input Port
AE1
AN0
I
D
Analog Input 0
AD2
AN1
I
D
Analog Input 1
AA4
AN2
I
D
Analog Input 2
Data Sheet
114
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
AB3
AN3
I
D
Analog Input 3
AC2
AN4
I
D
Analog Input 4
AA3
AN5
I
D
Analog Input 5
AD1
AN6
I
D
Analog Input 6
AB4
AN7
I
D
Analog Input 7
AC1
AN8
I
D
Analog Input 8
AB2
AN9
I
D
Analog Input 9
Y3
AN10
I
D
Analog Input 10
AA2
AN11
I
D
Analog Input 11
AB1
AN12
I
D
Analog Input 12
W3
AN13
I
D
Analog Input 13
Y2
AN14
I
D
Analog Input 14
AA1
AN15
I
D
Analog Input 15
V4
AN16
I
D
Analog Input 16
W2
AN17
I
D
Analog Input 17
Y1
AN18
I
D
Analog Input 18
V3
AN19
I
D
Analog Input 19
W1
AN20
I
D
Analog Input 20
V2
AN21
I
D
Analog Input 21
V1
AN22
I
D
Analog Input 22
U1
AN23
I
D
Analog Input 23
AC8
AN24
I
D
Analog Input 24
AD8
AN25
I
D
Analog Input 25
AC7
AN26
I
D
Analog Input 26
AD7
AN27
I
D
Analog Input 27
AE6
AN28
I
D
Analog Input 28
Data Sheet
115
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
AF6
AN29
I
D
Analog Input 29
AE7
AN30
I
D
Analog Input 30
AF7
AN31
I
D
Analog Input 31
AC3
AN32
I
D
Analog Input 32
AE2
AN33
I
D
Analog Input 33
AD3
AN34
I
D
Analog Input 34
AD5
AN35
I
D
Analog Input 35
AE3
AN36
I
D
Analog Input 36
AF2
AN37
I
D
Analog Input 37
AC4
AN38
I
D
Analog Input 38
AF3
AN39
I
D
Analog Input 39
AD4
AN40
I
D
Analog Input 40
AE4
AN41
I
D
Analog Input 41
AC5
AN42
I
D
Analog Input 42
AF4
AN43
I
D
Analog Input 43
System I/O
B22
PORST
I
Input
only/
PD
Power-on Reset Input
(input pad with input spike-filter)
A23
ESR0
I/O
A2
External System Request Reset Input 0
Default configuration during and after reset is
open-drain Driver, corresponding to A2 strong
Driver, sharp edge. The Driver drives low during
power-on reset.
A22
ESR1
I/O
A2/
PD
External System Request Reset Input 1
E24
TCK
I
JTAG Module Clock Input
DAP0
I
Input
only/
PD
Data Sheet
Device Access Port Line 0
116
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
E25
TDI
I
BRKIN
I
A2/
PU
BRKOUT
O
B23
TESTMODE
I
Input
only/
PU
Test Mode Select Input
F24
TMS
I
JTAG Module State Machine Control Input
DAP1
I/O
A2/
PD
F23
TRST
I
Input
only/
PD
JTAG Module Reset/Enable Input
G26
XTAL1
I
Main Oscillator/PLL/Clock Generator Input
G25
XTAL2
O
Main Oscillator/PLL/Clock Generator Output
D25
TDO
O
BRKIN
I
BRKOUT
O
OCDS Break Output (Alternate Output)
DAP2
O
Device Access Port Line 2
N.C.
-
-
Not connected. These pins are reserved for
future extension and shall not be connected
externally.
A1,
AF1,
AF26,
A24,
C22,
AC21,
AD23,
AE22,
AE23
JTAG Module Serial Data Input
OCDS Break Input (Alternate Output)
OCDS Break Output (Alternate Input)
A2/
PU
Device Access Port Line 1
JTAG Module Serial Data Output
OCDS Break Input (Alternate Input)
Power Supply
W4
VDDM
-
-
ADC Analog Part Power Supply (3.3V - 5V)
Y4
VSSM
-
-
ADC Analog Part Ground
AE5
VAREF0
-
-
ADC0 Reference Voltage
Data Sheet
117
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
AF5
VAGND0
-
-
ADC0 Reference Ground
VAGND2
-
-
ADC2 Reference Ground
AD6
VAREF1
-
-
ADC1 Reference Voltage
AC6
VAGND1
-
-
ADC1 Reference Ground
AD9
VAREF2
-
-
ADC2 Reference Voltage
AF8
VFAREF
-
-
FADC Reference Voltage
AE8
VFAGND
-
-
FADC Reference Ground
AE9
VDDMF
-
-
FADC Analog Part Power Supply (3.3V)1)
AC9
VDDAF
-
-
FADC Analog Part Logic Power Supply
(1.5V)
AF9
VSSMF
-
-
FADC Analog Part Ground
VSSAF
-
-
FADC Analog Part Logic Ground
A18,
B18,
H3
VDDFL3
-
-
Flash Power Supply (3.3V)
F25
VSSOSC
-
-
Main Oscillator Ground
VSS
-
-
Digital Ground
F26
VDDOSC
-
-
Main Oscillator Power Supply (1.5V)
E26
VDDOSC3
-
-
Main Oscillator Power Supply (3.3V)
G23
VDDPF
-
-
E-Ray PLL Power Supply (1.5V)
G24
VDDPF3
-
-
E-Ray PLL Power Supply (3.3V)
Data Sheet
118
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
AC11,
AC20,
AB23,
V23,
P23,
E23,
D24,
C25,
B26,
D16,
D9,
H4,
R4
VDD
-
-
Digital Core Power Supply (1.5V)
-
-
Port Power Supply (3.3V)
AC16, VDDP
AD16,
AE16,
AF16,
D22,
C23,
B24,
A25,
D14,
D7, K4
H23,
H24,
H25,
H26,
M23,
T23,
Y23,
AC18,
AC22
VDDEBU
-
-
EBU Port Power Supply (2.5V - 3.3V)
R1
VDDE(SB)
-
-
Emulation Stand-by SRAM Power Supply
(1.5V) (Emulation device only)
Note: This pin is N.C. in a productive device.
Data Sheet
119
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
AC10,
AC17,
AC19,
AC23,
W23,
R23,
L23,
D23,
C24,
B25,
A26,
D15,
D8,
J4, T4
VSS
-
-
Digital Ground (outer balls)
K10,
K11,
K12,
K13,
K14,
K15,
K16,
K17
VSS
-
-
Digital Ground (center balls)
L10,
L11,
L12,
L13,
L14,
L15,
L16,
L17
VSS
-
-
Digital Ground (center balls cont’d)
M10,
M11,
M12,
M13,
M14,
M15,
M16,
M17
VSS
-
-
Digital Ground (center balls cont’d)
Data Sheet
120
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
N10,
N11,
N12,
N13,
N14,
N15,
N16,
N17
VSS
-
-
Digital Ground (center balls cont’d)
P10,
P11,
P12,
P13,
P14,
P15,
P16,
P17
VSS
-
-
Digital Ground (center balls cont’d)
R10,
R11,
R12,
R13,
R14,
R15,
R16,
R17
VSS
-
-
Digital Ground (center balls cont’d)
T10,
T11,
T12,
T13,
T14,
T15,
T16,
T17
VSS
-
-
Digital Ground (center balls cont’d)
Data Sheet
121
V1.3, 2014-08
TC1797
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Pin
Symbol
Ctrl.
Type Function
U10,
U11,
U12,
U13,
U14,
U15,
U16,
U17
VSS
-
-
Digital Ground (center balls cont’d)
1) This pin is also connected to the analog power supply for comparator of the ADC module.
Legend for Table 4
Column “Ctrl.”:
I = Input (for GPIO port Lines with IOCR bit field Selection PCx = 0XXXB)
O = Output
O0 = Output with IOCR bit field selection PCx = 1X00B
O1 = Output with IOCR bit field selection PCx = 1X01B (ALT1)
O2 = Output with IOCR bit field selection PCx = 1X10B (ALT2)
O3 = Output with IOCR bit field selection PCx = 1X11B (ALT3)
Column “Type”:
A1 = Pad class A1 (LVTTL)
A2 = Pad class A2 (LVTTL)
F = Pad class F (LVDS/CMOS)
D = Pad class D (ADC)
PU = with pull-up device connected during reset (PORST = 0)
PD = with pull-down device connected during reset (PORST = 0)
TR = tri-state during reset (PORST = 0)
3.1.2
Table 5
Pull-Up/Pull-Down Reset Behavior of the Pins
List of Pull-Up/Pull-Down Reset Behavior of the Pins
Pins
PORST = 0
all GPIOs, TDI, TESTMODE
Pull-up
PORST, TRST, TCK, TMS
Pull-down
Data Sheet
122
PORST = 1
V1.3, 2014-08
TC1797
Pinning
Table 5
List of Pull-Up/Pull-Down Reset Behavior of the Pins
Pins
PORST = 0
PORST = 1
ESR0
The open-drain driver is
used to drive low.1)
Pull-up2)
ESR1
Pull-down2)
TDO
Pull-up
High-impedance
1) Valid additionally after deactivation of PORST until the internal reset phase has finished. See the SCU chapter
for details.
2) See the SCU_IOCR register description.
Data Sheet
123
V1.3, 2014-08
TC1797
Pinning
Data Sheet
124
V1.3, 2014-08
TC1797
Identification Registers
4
Identification Registers
The Identification Registers uniquely identify a module or the whole device.
Table 4-1
TC1797 Identification Registers 1)
Short Name
Value
Address
Stepping
ADC0_ID
0059 C000H
F010 1008H
–
ADC1_ID
0059 C000H
F010 1408H
–
ADC2_ID
0059 C000H
F010 1808H
–
ASC0_ID
0000 4402H
F000 0A08H
–
ASC1_ID
0000 4402H
F000 0B08H
–
CAN_ID
002B C051H
F000 4008H
–
CBS_JDPID
0000 6350H
F000 0408H
–
CBS_JTAGID
1015 A083H
F000 0464H
–
CPS_ID
0015 C007H
F7E0 FF08H
–
CPU_ID
000A C006H
F7E1 FE18H
–
DMA_ID
001A C004H
F000 3C08H
–
DMI_ID
0008 C005H
F87F FC08H
–
EBU_ID
0014 C009H
F800 0008H
–
ERAY_ID
0044 C003H
F001 0008H
–
FADC_ID
0027 C003H
F010 0408H
–
FLASH0_ID
0053 C001H
F800 2008H
–
FLASH1_ID
0055 C001H
F800 4008H
–
FPU_ID
0054 C003H
F7E1 A020H
–
GPTA0_ID
0029 C005H
F000 1808H
–
GPTA1_ID
0029 C005H
F000 2008H
–
LBCU_ID
000F C005H
F87F FE08H
–
LFI_ID
000C C006H
F87F FF08H
–
LTCA2_ID
002A C005H
F000 2808H
–
MCHK_ID
001B C001H
F010 C208H
–
MLI0_ID
0025 C007H
F010 C008H
–
MLI1_ID
0025 C007H
F010 C108H
–
MSC0_ID
0028 C003H
F000 0808H
–
Data Sheet
Mod_Name
125
V1.3, 2014-08
TC1797
Identification Registers
Table 4-1
TC1797 Identification Registers (cont’d)1)
Short Name
Value
Address
Stepping
MSC1_ID
0028 C003H
F000 0908H
–
PCP_ID
0020 C006H
F004 3F08H
–
PMI_ID
000B C005H
F87F FD08H
–
PMU0_ID
0050 C001H
F800 0508H
–
PMU1_ID
0051 C001H
F800 6008H
–
SBCU_ID
0000 6A0CH
F000 0108H
–
SCU_CHIPID
0000 9001H
F000 0640H
–
SCU_ID
0052 C001H
F000 0508H
–
SCU_MANID
0000 1820H
F000 0644H
–
SCU_RTID
0000 0003H
F000 0648H
AC only
SSC0_ID
0000 4511H
F010 0108H
–
SSC1_ID
0000 4511H
F010 0208H
–
STM_ID
0000 C006H
F000 0208H
–
1) Valid for all design steps except if explicitely defined.
Data Sheet
Mod_Name
126
V1.3, 2014-08
TC1797
Electrical Parameters
5
Electrical Parameters
5.1
General Parameters
5.1.1
Parameter Interpretation
The parameters listed in this section partly represent the characteristics of the TC1797
and partly its requirements on the system. To aid interpreting the parameters easily
when evaluating them for a design, they are marked with an two-letter abbreviation in
column “Symbol”:
•
•
CC
Such parameters indicate Controller Characteristics which are a distinctive feature of
the TC1797 and must be regarded for a system design.
SR
Such parameters indicate System Requirements which must provided by the
microcontroller system in which the TC1797 designed in.
Data Sheet
127
V1.3, 2014-08
TC1797
Electrical Parameters
5.1.2
Pad Driver and Pad Classes Summary
This section gives an overview on the different pad driver classes and its basic
characteristics. More details (mainly DC parameters) are defined in the Section 5.2.1.
Table 6
Pad Driver and Pad Classes Overview
Leakage1) Termination
Class Power Type
Supply
Sub Class
Speed Load
Grade
A
LVTTL
I/O,
LVTTL
outputs
A1
(e.g. GPIO)
6 MHz
100 pF 500 nA
A2
(e.g. serial
I/Os)
40
MHz
50 pF
6 μA
Series
termination
recommended
LVTTL
I/O
B1
(e.g. Ext.
Bus
Interface)
40
MHz
50 pF
6 μA
No
B2
(e.g. Bus
Clock)
75
MHz
35 pF
B
3.3 V
2.375 3.6 V2)
No
Series
termination
recommended
(for f > 25 MHz)
F
3.3 V
LVDS/
CMOS
–
50
MHz
–
–
Parallel
termination3),
100 Ω ± 10%
DE
5V
ADC
–
–
–
–
see Table 11
1) Values are for TJmax = 150 °C.
2) AC characteristics for EBU pins are valid for 2.5 V ± 5% and 3.3 V ± 5%.
3) In applications where the LVDS pins are not used (disabled), these pins must be either left unconnected, or
properly terminated with the differential parallel termination of 100 Ω ± 10%.
Data Sheet
128
V1.3, 2014-08
TC1797
Electrical Parameters
5.1.3
Absolute Maximum Ratings
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
During absolute maximum rating overload conditions (VIN > related VDD or VIN < VSS) the
voltage on the related VDD pins with respect to ground (VSS) must not exceed the values
defined by the absolute maximum ratings.
Table 7
Absolute Maximum Rating Parameters
Parameter
Symbol
Values
Min. Typ. Max.
Unit Note /
Test Con
dition
Ambient temperature
-40
–
125
°C
Under bias
Storage temperature
-65
–
150
°C
–
-40
–
150
°C
Under bias
–
–
2.25
V
–
–
–
3.75
V
–
–
–
5.5
V
–
VDDP + 0.5
or max. 3.7
V
Whatever
is lower
VDDEBU + 0.5 V
or max. 3.7
Whatever
is lower
-0.5 –
VDDM + 0.5
V
–
Voltage on any shared Class VAINF
-0.5 –
D analog input pin with
VFAREF
respect to VSSAF, if the FADC
SR
is switched through to the pin.
VDDM + 0.5
V
–
180
150
MHz Derivative
dependent
TA
SR
TST
SR
Junction temperature
TJ
SR
Voltage at 1.5 V power supply VDD
SR
pins with respect to VSS1)
Voltage at 3.3 V power supply VDDEBU
pins with respect to VSS2)
VDDP SR
Voltage at 5 V power supply VDDM SR
pins with respect to VSS
Voltage on any Class A input VIN
SR
-0.5 –
pin and dedicated input pins
with respect to VSS
Voltage on any Class B input VIN
pin with respect to VSS
Voltage on any Class D
analog input pin with respect
to VAGND
CPU Frequency
Data Sheet
SR -0.5 –
VAIN
VAREFx
SR
fCPU
SR –
129
–
V1.3, 2014-08
TC1797
Electrical Parameters
Table 7
Absolute Maximum Rating Parameters
Parameter
Symbol
Values
Unit Note /
Test Con
dition
Min. Typ. Max.
PCP Frequency
fPCP
E-Ray Sample Frequency
fSAMPLE
SR –
–
180
150
MHz Derivative
dependent
–
–
80
MHz
SR
1) Applicable for VDD, VDDOSC, VDDPF, and VDDAF.
2) Applicable for VDDP, VDDEBU, VDDFL3, VDPF3, and VDDMF.
5.1.4
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation of the TC1797. All parameters specified in the following table refer to these
operating conditions, unless otherwise noticed.
The following operating conditions must not be exceeded in order to ensure correct
operation of the TC1797. All parameters specified in the following table refer to these
operating conditions, unless otherwise noted.
Table 8
Operating Condition Parameters
Parameter
Symbol
Values
Digital supply voltage1)
VDD
SR 1.42
VDDOSC SR
3.13
VDDP SR
VDDOSC3 SR
VDDEBU SR 3.13
Min.
Typ. Max.
–
1.582)
V
–
–
3.473)
V
For Class A pins
(3.3 V ± 5%)
–
3.473)
2.625
V
For Class B
(EBU) pins
–
3.473)
V
–
–
3)
V
FADC
2.375
VDDFL3 SR
Analog supply voltages VDDMF SR
VDDAF SR
VDDM
SR
Digital ground voltage
Ambient temperature
under bias
Data Sheet
VSS
TA
3.13
3.13
Unit Note /
Test Condition
3.47
2)
1.42
–
1.58
V
FADC
4.75
–
5.25
V
For Class DE
pins, ADC
SR 0
–
–
V
–
SR -40
–
+125
°C
–
130
V1.3, 2014-08
TC1797
Electrical Parameters
Table 8
Operating Condition Parameters
Parameter
Symbol
Min.
Values
Typ. Max.
Unit Note /
Test Condition
–
–
–
–
See separate
specification
Page 138,
Page 143
-1
–
3
mA
4)
Sum of overload current Σ|IOV|
at class D pins
–
–
10
mA
per single ADC
Overload coupling
KOVAP
factor for analog inputs5)
–
–
5×105
0 < IOV < 3 mA
KOVAN
–
–
5×104
-1 mA< IOV < 0
Analog supply voltages –
Overload current at
class D pins
IOV
CPU & LMB Bus
Frequency
fCPU
SR
–
–
180
150
MHz Derivative
dependent
PCP Frequency
fPCP
SR
–
–
180
150
MHz Derivative
dependent6)
FPI Bus Frequency
fSYS SR –
ISC
SR -5
Σ|ISC_PG|
–
–
90
MHz
6)
–
+5
mA
7)
–
20
mA
See note
–
1
mA
All power supply
voltages VDDx = 0
–
–
100
mA
See note4)
–
–
–
pF
Depending on pin
class. See DC
characteristics
Short circuit current
Absolute sum of short
circuit currents of a pin
group (see Table 9)
SR
Inactive device pin
current
IID
Absolute sum of short
circuit currents of the
device
Σ|ISC_D|
External load
capacitance
CL
SR -1
SR
SR
1) Digital supply voltages applied to the TC1797 must be static regulated voltages which allow a typical voltage
swing of ±5%.
2) Voltage overshoot up to 1.7 V is permissible at Power-Up and PORST low, provided the pulse duration is less
than 100 μs and the cumulated summary of the pulses does not exceed 1 h.
3) Voltage overshoot to 4 V is permissible at Power-Up and PORST low, provided the pulse duration is less than
100 μs and the cumulated summary of the pulses does not exceed 1 h
Data Sheet
131
V1.3, 2014-08
TC1797
Electrical Parameters
4) See additional document “TC1767 Pin Reliability in Overload“ for definition of overload current on digital pins.
5) The overload coupling factor (kA) defines the worst case relation of an overload condition (IOV) at one pin to
the resulting leakage current (IleakTOT) into an adjacent pin: IleakTOT = ±kA × |IOV| + IOZ1.
Thus under overload conditions an additional error leakage voltage (VAEL) will be induced onto an adjacent
analog input pin due to the resistance of the analog input source (RAIN). That means VAEL = RAIN ×
|IleakTOT|.
The definition of adjacent pins is related to their order on the silicon.
The Injected leakage current always flows in the opposite direction from the causing overload current.
Therefore, the total leakage current must be calculated as an algebraic sum of the both component leakage
currents (the own leakage current IOZ1 and the optional injected leakage current).
6) The PLL jitter characteristics add to this value according to the application settings. See the PLL jitter
parameters.
7) Applicable for digital outputs.
Table 9
Pin Groups for Overload / Short-Circuit Current Sum Parameter
Group
Pins
1
P4.[7:0]
2
P4.[15:8]
3
P10.[5:0]
4
P15.[0, 1, 7:4, 11, 12]
5
P15.[3:0, 8, 13], P16.3
6
P15.9, P16.2, P15.10, P15.[15:14]
7
P14.[15:10]
8
P14.[9:8]
9
P14.[7:2]
10
P14.[1:0], P13.[15:14]
11
P13.[13:12]
12
P13.[11:6]
13
P13.[5:2]
14
P13.[1:0], P12[5:4]
15
P12.[3:0]
16
P11.[15:12]
17
P11.[11:8]
18
P11.[7:4]
19
P11.[3:0]
20
P12.[7:6]
Data Sheet
132
V1.3, 2014-08
TC1797
Electrical Parameters
Table 9
Pin Groups for Overload / Short-Circuit Current Sum Parameter
Group
Pins
21
P9.[14:13, 10:9]
22
P9.[12:11, 8:7, 2]
23
P9.[6:5, 3, 1]
24
P9.[0, 4], P5.[10, 11]
25
P5.[15:14, 9:8]
26
P5.[13:12, 6, 4]
27
P5.[7:5, 3, 0]
28
P3.[7:0]
29
P3.[15:8]
30
P0.[7:0]
31
P0.[15:8]
32
P2.[15:9]
33
P2.[8:4]
34
P2.[3:2], P6[9:8]
35
P6[11, 6:4]
36
P6.[15:12, 10, 7]
37
P8.[7:0]
38
P1.[15:13, 11:8, 5]
39
P1.[12, 7, 6, 4, 3]
40
P1.[1:0], P7.0
41
P7.[5:1]
42
P7.[7:6]
Data Sheet
133
V1.3, 2014-08
TC1797
Electrical Parameters
5.2
DC Parameters
5.2.1
Input/Output Pins
Table 10
Input/Output DC-Characteristics (Operating Conditions apply)
Parameter
Symbol
Values
Unit Note / Test Condition
Min.
Typ. Max.
10
–
100
μA
VIN < VIHAmin;
class A1/A2/F/Input pads.
5
–
85
μA
VIN < VIHBmin;
class B1/B2 pads.
10
–
150
μA
VIN >VILAmax;
class A1/A2/F/Input pads.
VIN > VILBmax;
class B1/B2 pads
–
–
10
pF
f = 1 MHz
TA = 25 °C
General Parameters
Pull-up current1)
|IPUH|
CC
Pull-down
current1)
|IPDL|
Pin capacitance1)
(Digital I/O)
CIO
CC
CC
Input only Pads (VDDP = 3.13 to 3.47 V = 3.3 V ± 5%)
Input low voltage
–
0.36 ×
V
–
0.62 ×
SR VDDP
–
VDDP
VDDP+
V
Whatever is lower
CC 0.58
–
–
–
–
–
VDDP+
0.3 or
max.
3.6
V
Whatever is lower
0.1 ×
CC VDDP
–
–
V
4)
–
–
±3000
±6000
nA
((VDDP/2)-1) < VIN <
((VDDP/2)+1)
Otherwise2)
VILI
-0.3
SR
Input high voltage VIHI
Ratio VIL/VIH
Input high voltage VIHJ
0.64 ×
TRST, TCK
SR VDDP
Input hysteresis
HYSI
Input leakage
current
IOZI
Data Sheet
0.3 or
max.
3.6
CC
134
V1.3, 2014-08
TC1797
Electrical Parameters
Table 10
Input/Output DC-Characteristics (cont’d)(Operating Conditions apply)
Parameter
Symbol
Values
Min.
Spike filter always tSF1
–
blocked pulse
CC
duration
Spike filter passthrough pulse
duration
tSF2
100
Unit Note / Test Condition
Typ. Max.
–
10
ns
–
–
ns
CC
Class A Pads (VDDP = 3.13 to 3.47 V = 3.3V ± 5%)
Output low voltage VOLA
3)
Output high
voltage2) 3)
–
–
0.4
V
IOL = 2 mA for medium
and strong driver mode,
IOL = 500 μA for weak
driver mode
2.4
–
–
V
IOH = -2 mA for medium
CC
VOHA
CC
and strong driver mode,
IOH = -500 μA for weak
driver mode
VDDP - –
–
V
0.4
IOH = -1.4 mA for medium
and strong driver mode,
IOH = -400 μA for weak
driver mode
–
0.36 ×
V
–
Input high voltage VIHA1
0.62 ×
Class A1 pins
SR VDDP
–
VDDP
VDDP+
V
Whatever is lower
Ratio VIL/VIH
Class A1 pins
–
–
–
–
Input high voltage VIHA2
0.60 ×
Class A2 pins
SR VDDP
–
VDDP+
0.3 or
max.
3.6
V
Whatever is lower
Ratio VIL/VIH
Class A2 pins
–
–
–
–
–
–
V
4)
Input low voltage
Class A1/2 pins
Input hysteresis
Data Sheet
VILA
-0.3
SR
CC 0.58
CC 0.6
HYSA
0.1 ×
CC VDDP
0.3 or
max.
3.6
135
V1.3, 2014-08
TC1797
Electrical Parameters
Table 10
Input/Output DC-Characteristics (cont’d)(Operating Conditions apply)
Parameter
Symbol
Input leakage
current Class A2
pins
IOZA2
Input leakage
current
Class A1 pins
IOZA1
Values
Min.
Typ. Max.
–
–
±3000
Unit Note / Test Condition
nA
((VDDP/2)-1) < VIN <
((VDDP/2)+1)
Otherwise2)
±500
nA
0 V <VIN < VDDP
0.4
V
–
V
IOL = 2 mA
IOL = 2 mA
0.34 ×
V
–
VDDEBU
VDDEBU
V
Whatever is lower
CC
±6000
–
–
CC
Class B Pads (VDDEBU = 2.375 to 3.47 V)
Output low voltage VOLB CC –
Output high
voltage
VOHB
Input low voltage
VILB
–
VDDEBU –
CC - 0.4
-0.3
–
SR
Input high voltage VIHB
Ratio VIL/VIH
0.64 × –
SR VDDEBU
CC 0.53
+ 0.3 or
max.
3.6
–
–
–
–
Input hysteresis
–
HYSB
0.1 ×
CC VDDEBU
–
V
4)
Input leakage
current
Class B pins
IOZB
±3000
±6000
nA
((VDDEBU/2)-0.6) < VIN
<
((VDDEBU/2)+0.6)5)
Otherwise2)
–
–
CC
Class F Pads, LVDS Mode (VDDP = 3.13 to 3.47 V = 3.3V ± 5%)
Output low voltage VOL CC 875
Output high
voltage
VOH CC
Output differential VOD CC 150
voltage
Output offset
voltage
VOS CC 1075
Output impedance R0
Data Sheet
CC 40
–
–
mV
Parallel termination
100 Ω ± 1%
–
1525
mV
Parallel termination
100 Ω ± 1%
–
400
mV
Parallel termination
100 Ω ± 1%
–
1325
mV
Parallel termination
100 Ω ± 1%
–
140
Ω
–
136
V1.3, 2014-08
TC1797
Electrical Parameters
Table 10
Input/Output DC-Characteristics (cont’d)(Operating Conditions apply)
Parameter
Symbol
Values
Min.
Unit Note / Test Condition
Typ. Max.
Class F Pads, CMOS Mode (VDDP = 3.13 to 3.47 V = 3.3V ± 5%)
–
0.36 ×
V
–
Input high voltage VIHF
0.60 ×
Class F pins
SR VDDP
–
VDDP
VDDP+
V
Whatever is lower
Input hysteresis
Class F pins
HYSF
0.05 ×
CC VDDP
–
–
V
Input leakage
current Class F
pins
IOZF
–
±3000
nA
((VDDP/2)-1) < VIN
<
((VDDP/2)+1)
Otherwise2)
Input low voltage
Class F pins
VILF
-0.3
SR
–
±6000
Output low voltage VOLF
6)
Output high
voltage2) 6)
0.3 or
max.
3.6
–
–
0.4
V
IOL = 2 mA
2.4
CC V
DDP 0.4
–
–
V
–
–
V
IOH = -2 mA
IOH = -1.4 mA
–
–
–
–
–
CC
VOHF
Class D Pads
See ADC Characteristics
1) Not subject to production test, verified by design / characterization.
2) Only one of these parameters is tested, the other is verified by design characterization
3) Maximum resistance of the driver RDSON, defined for P_MOS / N_MOS transistor separately:
25 / 20 Ω for strong driver mode, IOH / L < 2 mA,
200 / 150 Ω for medium driver mode, IOH / L < 400 uA,
600 / 400 Ω for weak driver mode, IOH / L < 100 uA,
verified by design / characterization.
4) Function verified by design, value verified by design characterization.
Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce.
It cannot be guaranteed that it suppresses switching due to external system noise.
5) VDDEBU = 2.5 V ± 5%. For VDDEBU = 3.3 ± 5% see class A2 pads.
6) The following constraint applies to an LVDS pair used in CMOS mode: only one pin of a pair should be used
as output, the other should be used as input, or both pins should be used as inputs. Using both pins as outputs
is not recommended because of the higher crosstalk between them.
Data Sheet
137
V1.3, 2014-08
TC1797
Electrical Parameters
5.2.2
Analog to Digital Converters (ADC0/ADC1/ADC2)
All ADC parameters are optimized for and valid in the range of VDDM = 5V ± 5%.
Table 11
ADC Characteristics (Operating Conditions apply)
Parameter
Symbol
Values
Min.
Analog supply
voltage
Analog ground
voltage
Unit
Typ. Max.
Note /
Test Condition
5
5.25 1)
V
–
3.13
3.3
3.47
V
–
VDD
SR 1.42
1.5
1.582)
V
Power supply for
ADC digital part,
internal supply
VSSM
SR -0.1
–
0.1
V
–
V
–
VAREF - V
–
VDDM
Analog reference VAREFx
voltage16)
SR 4.75
SR
VAGNDx+1 VDDM VDDM+
V
0.05
1)3)4)
Analog reference VAGNDx SR VSSMx ground16)
0.05V
1V
SR VAGNDx
–
VAREFx
V
–
Analog reference VAREFxVDDM/2
voltage range5)16) VAGNDx SR
–
VDDM + V
0.05
–
fADC SR 1
fADCI
CC 0.5
–
90
MHz –
–
10
MHz –
tS
CC 2
–
257
TAD
CI
–
Total unadjusted TUE6) CC –
error5)
–
±4
LSB
12-bit conversion,
without noise7)8)
–
–
±2
LSB
10-bit conversion8)
–
–
±1
LSB
8-bit conversion8)
–
±1.5
±3.0
LSB
12-bit conversion
without noise8)10)
–
±1.5
±3.0
LSB
12-bit convesion
without noise8)10)
Analog input
voltage range
Converter Clock
Internal ADC
clocks
Sample time
DNL error9) 5)
VAIN
0
EADNL
CC
INL error9)5)
EAINL
CC
Data Sheet
138
V1.3, 2014-08
TC1797
Electrical Parameters
Table 11
ADC Characteristics (cont’d) (Operating Conditions apply)
Parameter
Gain error9)5)
Symbol
EAGAIN
Values
Unit
Note /
Test Condition
±3.5
LSB
12-bit conversion
without noise8)10)
±1.0
±4.0
LSB
12-bit converson
without noise8)10)
-300
–
100
nA
(0% VDDM) < VIN <
(3% VDDM)
-100
–
200
nA
(3% VDDM) < VIN <
(97% VDDM)
-100
–
300
nA
(97% VDDM) < VIN <
(100% VDDM)
Min.
Typ. Max.
–
±0.5
–
CC
Offset error9)5)
EAOFF
CC
Input leakage
IOZ1 CC
current at analog
inputs of ADC0/1
11) 12) 13)
Input leakage
current at
IOZ2
CC –
–
±1.5
μA
0 V < VAREF <
VDDM, no conversion
running
IAREF
CC –
35
75
μA
rms
0 V < VAREF <
VAREF0/1/2,
per module
Input current at
VAREF0/1/216),
VDDM14)
per module
Total
capacitance of
the voltage
reference
inputs15)16)
CAREFTOT
Switched
capacitance at
the positive
reference
voltage input16)
CAREFSW
Resistance of
the reference
voltage input
path15)
RAREF
Total
capacitance of
the analog
inputs15)
CAINTOT
Data Sheet
–
20
40
pF
8)
–
15
30
pF
8)17)
–
500
1000
Ω
500 Ohm increased
for AN[1:0] used as
reference input8)
–
25
30
pF
1)8)
CC
CC
CC
CC
139
V1.3, 2014-08
TC1797
Electrical Parameters
Table 11
ADC Characteristics (cont’d) (Operating Conditions apply)
Parameter
Switched
capacitance at
the analog
voltage inputs
Symbol
CAINSW
Unit
Note /
Test Condition
20
pF
8)18)
700
1500
Ω
8)
550
90019)
Ω
Test feature
available only for
AIN78) 20)
15
rms
30
peak
mA
Test feature
available only for
AIN78)
Typ. Max.
–
7
CC
ON resistance of RAIN
the transmission
gates in the
analog voltage
path
ON resistance
for the ADC test
(pull-down for
AIN7)
Values
Min.
CC –
RAIN7T CC 180
Current through IAIN7T
resistance for the
ADC test (pulldown for AIN7)
CC –
1) Voltage overshoot to tbd. V are permissible, provided the pulse duration is less than 100 μs and the cumulated
summary of the pulses does not exceed 1 h.
2) Voltage overshoot to 1.7 V are permissible, provided the pulse duration is less than 100 μs and the cumulated
summary of the pulses does not exceed 1 h.
3) A running conversion may become inexact in case of violating the normal operating conditions (voltage
overshoot).
VAREF
increases
or
the
VDDM
decreases,
so
that
the
reference
voltage
VAREF = (VDDM + 0.05 V to VDDM + 0.07V), then the accuracy of the ADC decreases by 4LSB12.
5) If a reduced reference voltage in a range of VDDM/2 to VDDM is used, then the ADC converter errors increase.
4) If
If the reference voltage is reduced with the factor k (k<1), then TUE, DNL, INL Gain and Offset errors increase
with the factor 1/k.
If a reduced reference voltage in a range of 1 V to VDDM/2 is used, then there are additional decrease in the
ADC speed and accuracy.
6) TUE is tested at VAREF = 5.0 V, VAGND = 0 V and VDDM = 5.0 V
7) ADC module capability.
8) Not subject to production test, verified by design / characterization.
9) The sum of DNL/INL/Gain/Offset errors does not exceed the related TUE total unadjusted error.
10) For 10-bit conversions the DNL/INL/Gain/Offset error values must be multiplied with factor 0.25.
For 8-bit conversions the DNL/INL/Gain/Offset error values must be multiplied with 0.0625.
11) The leakage current definition is a continuous function, as shown in Figure 21. The numerical values defined
determine the characteristic points of the given continuous linear approximation - they do not define step
function.
Data Sheet
140
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TC1797
Electrical Parameters
12) Only one of these parameters is tested, the other is verified by design characterization.
13) The leakage current decreases typically 30% for junction temperature decrease of 10oC.
14) IAREF_MAX is valid for the minimum specified conversion time. The current flowing during an ADC conversion
with a duration of up to tC = 25 µs can be calculated with the formula IAREF_MAX = QCONV / tC. Every conversion
needs a total charge of QCONV = 150 pC from VAREF.
All ADC conversions with a duration longer than tC = 25µs consume an IAREF_MAX = 6µA.
15) For the definition of the parameters see also Figure 20.
16) Applies to AINx, when used as auxiliary reference inputs.
17) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage
at once. Instead of this smaller capacitances are successively switched to the reference voltage.
18) The sampling capacity of the conversion C-Network is pre-charged to VAREF / 2 before the sampling moment.
Because of the parasitic elements the voltage measured at AINx deviates from VAREF/2, and is typically 1.35 V.
19) RAIN7T = 1400 Ohm maximum and 830 Ohm typical in the VDDM = 3.3 V ± 5% range.
20) The DC current at the pin is limited to 3 mA for the operational lifetime.
clock
generation
ADC kernel
f ADC
interrupts,
etc.
divider for
fADCI
divider for
fADCD
digital clock
analog clock
f ADCI
registers
analog part
fADCD
arbiter
ADC_clocking
Figure 19
ADC0/ADC1 Clock Circuit
Table 12
Conversion Time (Operating Conditions apply)
Parameter
Symbol Value
tC
Conversion
time with
post-calibration
Conversion
time without
post-calibration
Data Sheet
Unit Note
CC 2 × TADC + (4 + STC + n) × TADCI μs
2 × TADC + (2 + STC + n) × TADCI
141
n = 8, 10, 12 for
n - bit conversion
TADC = 1 / fADC
TADCI = 1 / fADCI
V1.3, 2014-08
TC1797
Electrical Parameters
REXT
VAIN =
Analog Input Circuitry
RAIN, On
ANx
CEXT
CAINSW
CAINTOT - CAINSW
VAGNDx
RAIN7T
Reference Voltage Input Circuitry
RAREF, On
VAREFx
VAREF
CAREFTOT - CAREFSW
CAREFSW
VAGNDx
Analog_InpRefDiag
Figure 20
ADC0/ADC1 Input Circuits
Io z 1
300nA
200nA
100nA
-1 0 0 n A
V IN [V D D M % ]
3%
97% 100%
-3 0 0 n A
A D C L e a k a g e 1 0 .v s d
Figure 21
Data Sheet
ADC0/ADC1Analog Inputs Leakage
142
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TC1797
Electrical Parameters
5.2.3
Fast Analog to Digital Converter (FADC)
All parameters apply to FADC used in differential mode, which is the default and the
intended mode of operation, and which takes advantage of many error cancelation
effects inherent to differential measurements in general.
Table 13
FADC Characteristics (Operating Conditions apply)
Parameter
Symbol
Values
Min.
DNL error
INL error
Gradient error
9)
Unit
Note /
Test Condition
Typ. Max.
–
±1
LSB
9)
–
±4
LSB
9)
–
±5
%
Without calibration
gain 1, 2, 4
–
–
±6
%
Without calibration
gain 8
–
–
±203)
mV
With calibration1)
CC –
–
±903)
mV
Without calibration
–
–
±60
mV
–
–
3.474)
V
–
–
1.585)
V
–
–
0.1
V
–
–
3.474)6)
V
Nominal 3.3 V
EFDNL CC –
EFINL CC –
EFGRAD
–
CC
Offset error9)1)
Reference error of
internal VFAREF/2
Analog supply
voltages
Analog ground
voltage
EFOFF2)
EFREF
CC
VDDMF SR 3.13
VDDAF SR 1.42
VSSAF
-0.1
SR
Analog reference
voltage
VFAREF
Analog reference
ground
VFAGND
3.13
SR
VSSAF + V
0.05 V
–
VDDMF
V
–
–
15
mA
–
–
12
mA
7)
–
120
μA
rms
Independent of
conversion
–
Input leakage current IFOZ2
CC
at VFAREF 8)
–
±500
nA
0 V < VIN < VDDMF
–
Input leakage current IFOZ3
CC
at VFAGND8)
–
±8
μA
0 V < VIN < VDDMF
Analog input voltage VAINF
range
Analog supply
currents
Input current at
VFAREF
Data Sheet
VSSAF - –
SR 0.05 V
VFAGND –
SR
IDDMF SR –
IDDAF SR –
–
IFAREF
CC
143
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TC1797
Electrical Parameters
Table 13
FADC Characteristics (Operating Conditions apply) (cont’d)
Parameter
Symbol
Values
Min.
Conversion time
tC
Converter Clock
fFADC SR –
RFAIN
100
Input resistance of
the analog voltage
path (Rn, Rp)
CC –
Unit
Typ. Max.
Note /
Test Condition
–
21
CLK
For 10-bit conv.
of fADC
–
90
MHz
–
–
200
kΩ
9)
2
–
–
MHz
–
CC –
–
5
μs
–
CC
Channel Amplifier
Cutoff Frequency9)
fCOFF
Settling Time of a
Channel Amplifier
after changing ENN
or ENP9)
tSET
CC
1) Calibration should be performed at each power-up. In case of continuous operation, calibration should be
performed minimum once per week, or on regular basis in order to compensate for temperature changes.
2) The offset error voltage drifts over the whole temperature range maximum ±6 LSB.
3) Applies when the gain of the channel equals one. For the other gain settings, the offset error increases; it must
be multiplied with the applied gain.
4) Voltage overshoots up to 4 V are permissible, provided the pulse duration is less than 100 μs and the
cumulated summary of the pulses does not exceed 1 h.
5) Voltage overshoots up to 1.7 V are permissible, provided the pulse duration is less than 100 μs and the
cumulated sum of the pulses does not exceed 1 h.
6) A running conversion may become inexact in case of violating the normal operating conditions (voltage
overshoots).
7) Current peaks of up to 40 mA with a duration of max. 2 ns may occur
8) This value applies in power-down mode.
9) Not subject to production test, verified by design / characterization.
The calibration procedure should run after each power-up, when all power supply
voltages and the reference voltage have stabilized. The offset calibration must run first,
followed by the gain calibration.
Data Sheet
144
V1.3, 2014-08
TC1797
Electrical Parameters
FADC Analog Input Stage
RN
FAINxN
=
VFAGND
-
VFAREF /2
+
+
RP
FAINxP
-
FADC Reference Voltage
Input Circuitry
VFAREF
IFAREF
VFAREF
VFAGND
FADC_InpRefDiag
Figure 22
Data Sheet
FADC Input Circuits
145
V1.3, 2014-08
TC1797
Electrical Parameters
5.2.4
Table 14
Oscillator Pins
Oscillator Pins Characteristics (Operating Conditions apply)
Parameter
Symbol
Values
Min.
Frequency Range
Typ. Max.
fOSC CC 4
–
40
MHz Direct Input Mode
selected
8
–
25
MHz External Crystal
Mode selected
0.3 ×
V
–
VDDOSC3
VDDOSC3 V
–
Input low voltage at
XTAL11)
VILX SR -0.2
Input high voltage at
XTAL11)
VIHX SR 0.7 ×
–
VDDOSC3
IIX1 CC –
–
Input current at
XTAL1
Unit Note /
Test Condition
–
+ 0.2
±25
μA
0 V < VIN < VDDOSC3
1) If the XTAL1 pin is driven by a crystal, reaching a minimum amplitude (peak-to-peak) of 0.3 × VDDOSC3 is
necessary.
Note: It is strongly recommended to measure the oscillation allowance (negative
resistance) in the final target system (layout) to determine the optimal parameters
for the oscillator operation. Please refer to the limits specified by the crystal
supplier.
5.2.5
Table 15
Temperature Sensor
Temperature Sensor Characteristics (Operating Conditions apply)
Parameter
Symbol
Unit Note /
Test Condition
Min. Typ. Max.
Temperature sensor range
TSR
-40
Temperature sensor
measurement time
tTSMT SR
–
Start-up time after reset
tTSST SR
TTSA CC
–
Sensor accuracy
SR
Values
–
150
°C
Junction
temperature
–
100
μs
–
–
10
μs
–
–
±6
°C
Calibrated
1)
1) Not subject to production test, verified by design / characterization.
Data Sheet
146
V1.3, 2014-08
TC1797
Electrical Parameters
The following formula calculates the temperature measured by the DTS in [oC] from the
RESULT bitfield of the DTSSTAT register.
(1)
DTSSTAT RESULT – 619
Tj = -----------------------------------------------------------------2, 28
Data Sheet
147
V1.3, 2014-08
TC1797
Electrical Parameters
5.2.6
Power Supply Current
The default test conditions (differences explicitly specified) are:
VDD=1.58 V, VDD=3.47 V, fCPU=180 MHz, Tj=150oC
Table 16
Power Supply Currents (Operating Conditions apply)
Parameter
Symbol
Core active mode
supply current1)2) 3)
IDD
Values
Unit Note /
Test Condition
Min. Typ. Max.
fCPU=180 MHz
fCPU/fSYS = 2:1
VDD = 1.53 V,
TJ = 150oC
CC –
–
600
mA
–
–
430
mA
E-Ray PLL 1.5 V supply IDDPF
CC –
–
4
mA
–
E-Ray PLL 3.3 V supply IDDPF3
CC –
–
5
mA
– 5)
FADC 3.3 V analog
supply current
IDDMF
CC –
–
15
mA
–
FADC 1.5 V analog
supply current
IDDAF
CC –
–
12
mA
– 5)
Flash memory 3.3 V
supply current
IDDFL3R CC –
–
125
mA
continuously reading
the Flash memory 6)
IDDFL3E CC –
–
120
mA
Flash memory
erase-verify 7)
IDDOSC
IDDOSC3
ILVDS
IDDP
IDDP_FP
CC –
–
3
mA
– 5)
CC –
–
10
mA
– 5)
–
–
30
mA
in total for four pairs
CC –
–
30
mA
– 5) 8)
CC –
–
54
mA
IDDP including Data
Realistic core active
mode supply current 4) 5)
Oscillator 1.5 V supply
Oscillator 3.3 V supply
LVDS 3.3 V supply
Pad currents, sum of
VDDP 3.3 V supplies
Flash programming
current 8) 9)
ADC 5 V power supply
Maximum Average
Power Dissipation1)
IDDM
PD
CC –
–
6
mA
ADC0/1/2
SR –
–
1800 mW worst case
TA = 125oC,
PD × RΘJA < 25oC
1) Infineon Power Loop: CPU and PCP running, all peripherals active. The power consumption of each custom
application will most probably be lower than this value, but must be evaluated separately.
2) The IDD maximum value is 530 mA at fCPU = 150 MHz, constant TJ = 150oC, for the Infineon Max Power Loop.
The dependency in this range is, at constant junction temperature, linear.
fCPU/fSYS = 2:1 mode.
Data Sheet
148
V1.3, 2014-08
TC1797
Electrical Parameters
3) Not using the E-Ray module, E-Ray PLL in an application lowers the current consumption for typically 9mA.
4) The IDD maximum value is 390 mA at fCPU = 150 MHz, constant TJ = 150oC, for the Realistic Pattern.
The dependency in this range is, at constant junction temperature, linear.
fCPU/fSYS = 2:1 mode.
5) Not tested in production separately, verified by design / characterization.
6) This value assumes worst case of reading flash line with all cells erased. In case of 50% cells written with “1”
and 50% cells written with “0”, the maximum current drops down to 95 mA.
7) Relevant for the power supply dimensioning, not for thermal considerations.
In case of erase of Data Flash, internal flash array loading effects may generate transient current spikes of up
to 15 mA for maximum 5 ms.
8) No GPIO and EBU activity, LVDS off
9) This value is relevant for the power supply dimensioning. The currents caused by the GPIO and EBU activity
depend on the particular application and should be added separately. If two Flash modules are programmed
in parallel, the current increase is 2 × 24 mA.
Data Sheet
149
V1.3, 2014-08
TC1797
Electrical Parameters
5.3
AC Parameters
All AC parameters are defined with the temperature compensation disabled. That
means, keeping the pads constantly at maximum strength.
5.3.1
Testing Waveforms
VDDP
VDDEBU
90%
90%
10%
10%
VSS
tR
tF
rise_fall
Figure 23
Rise/Fall Time Parameters
VDDP
VDDEBU
VDDE / 2
Test Points
VDDE / 2
VSS
mct04881_a.vsd
Figure 24
Testing Waveform, Output Delay
VLoad+ 0.1 V
VLoad- 0.1 V
Timing
Reference
Points
VOH - 0.1 V
VOL - 0.1 V
MCT04880_new
Figure 25
Data Sheet
Testing Waveform, Output High Impedance
150
V1.3, 2014-08
TC1797
Electrical Parameters
5.3.2
Output Rise/Fall Times
Table 17
Output Rise/Fall Times (Operating Conditions apply)
Parameter
Symbol
Values
Unit Note / Test Condition
Min. Typ. Max.
Class A1 Pads
Rise/fall times1) tRA1, tFA1 –
–
50
ns
140
18000
150
550
65000
Regular (medium) driver, 50 pF
Regular (medium) driver, 150 pF
Regular (medium) driver, 20 nF
Weak driver, 20 pF
Weak driver, 150 pF
Weak driver, 20 000 pF
–
3.7
ns
7.5
7
18
50
140
18000
150
550
65000
Strong driver, sharp edge, 50 pF
Strong driver, sharp edge, 100pF
Strong driver, med. edge, 50 pF
Strong driver, soft edge, 50 pF
Medium driver, 50 pF
Medium driver, 150 pF
Medium driver, 20 000 pF
Weak driver, 20 pF
Weak driver, 150 pF
Weak driver, 20 000 pF
–
–
3.0
3.7
7.5
ns
35 pF
50 pF
100 pF
–
–
3.7
4.6
9.0
ns
35 pF
50 pF
100 pF
tRF1, tRF1 –
tRF2, tRF2 –
–
2
ns
LVDS Mode
–
60
ns
CMOS Mode, 50 pF
Class A2 Pads
Rise/fall times
1)
tRA2, tFA2 –
Class B Pads 3.3V ± 5%
Rise/fall times
1)2)
tRB, tFB
Class B Pads 2.5V ± 5%
Rise/fall times
1)3)
tRB, tFB
Class F Pads
Rise/fall times
Rise/fall times
1) Not all parameters are subject to production test, but verified by design/characterization and test correlation.
2) Parameter test correlation for VDDEBU = 2.5 V ± 5%
3) Parameter test correlation for VDDEBU = 2.5 V ± 5%
Data Sheet
151
V1.3, 2014-08
TC1797
Electrical Parameters
5.3.3
Power Sequencing
V
+-5%
5V
VAREF
+-5%
3.3V
+-5%
1.5V
-12%
0.5V
-12%
0.5V
0.5V
t
VDDP
PORST
power
down
power
fail
t
Power-Up 8.vsd
Figure 26
5 V / 3.3 V / 1.5 V Power-Up/Down Sequence
The following list of rules applies to the power-up/down sequence:
•
•
•
All ground pins VSS must be externally connected to one single star point in the
system. Regarding the DC current component, all ground pins are internally directly
connected.
At any moment,
each power supply must be higher than any lower_power_supply - 0.5 V, or:
VDD5 > VDD3.3 - 0.5 V; VDD5 > VDD1.5 - 0.5 V;VDD3.3 > VDD1.5 - 0.5 V, see
Figure 26.
During power-up and power-down, the voltage difference between the power supply
pins of the same voltage (3.3 V, 1.5 V, and 5 V) with different names (for example
VDDP, VDDFL3 ...), that are internally connected via diodes, must be lower than
100 mV. On the other hand, all power supply pins with the same name (for example
Data Sheet
152
V1.3, 2014-08
TC1797
Electrical Parameters
•
•
•
•
•
•
all VDDP ), are internally directly connected. It is recommended that the power pins
of the same voltage are driven by a single power supply.
The PORST signal may be deactivated after all VDD5, VDD3.3, VDD1.5, and VAREF
power-supplies and the oscillator have reached stable operation, within the normal
operating conditions.
At normal power down the PORST signal should be activated within the normal
operating range, and then the power supplies may be switched off. Care must be
taken that all Flash write or delete sequences have been completed.
At power fail the PORST signal must be activated at latest when any 3.3 V or 1.5 V
power supply voltage falls 12% below the nominal level. The same limit of 3.3 V-12%
applies to the 5 V power supply too. If, under these conditions, the PORST is
activated during a Flash write, only the memory row that was the target of the write
at the moment of the power loss will contain unreliable content. In order to ensure
clean power-down behavior, the PORST signal should be activated as close as
possible to the normal operating voltage range.
In case of a power-loss at any power-supply, all power supplies must be powereddown, conforming at the same time to the rules number 2 and 4.
Although not necessary, it is additionally recommended that all power supplies are
powered-up/down together in a controlled way, as tight to each other as possible.
Aditionally, regarding the ADC reference voltage VAREF:
– VAREF must power-up at the same time or later than VDDM, and
– VAREF must power-down eather earlier or at latest to satisfy the condition
VAREF < VDDM + 0.5 V. This is required in order to prevent discharge of VAREF
filter capacitance through the ESD diodes through the VDDM power supply. In
case of discharging the reference capacitance through the ESD diodes, the
current must be lower than 5 mA.
Data Sheet
153
V1.3, 2014-08
TC1797
Electrical Parameters
5.3.4
Table 18
Power, Pad and Reset Timing
Power, Pad and Reset Timing Parameters
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit Note /
Test Con
dition
Min. VDDP voltage to ensure
defined pad states1)
VDDPPA CC 0.6
–
–
V
–
Oscillator start-up time2)
tOSCS
CC –
–
10
ms
–
SR 10
–
–
ms
–
Minimum PORST active time tPOA
after power supplies are stable
at operating levels
ESR0 pulse width
tHD
CC Program –
mable3)5)
–
fSYS
–
PORST rise time
tPOR
tPOS
SR –
–
50
ms
–
SR 0
–
–
ns
–
Hold time from PORST rising
edge
tPOH
SR 100
–
–
ns
TESTMODE
TRST
Setup time to ESR0 rising
edge
tHDS
SR 0
–
–
ns
–
Hold time from ESR0 rising
edge
tHDH
SR 16 ×
1/fSYS5)
–
–
ns
HWCFG
Ports inactive after PORST
reset active6)7)
tPIP
CC –
–
150
ns
–
Ports inactive after ESR0 reset tPI
active (and for all logic)
CC –
–
8 × 1/ ns
fSYS
–
Power on Reset Boot Time8)
CC –
–
2.5
ms
–
CC 125
–
575
μs
–
Setup time to PORST rising
edge4)
Application Reset Boot Time
at fCPU=180MHz9)10)
tBP
tB
1) This parameter is valid under assumption that PORST signal is constantly at low level during the powerup/power-down of the VDDP.
2) tOSCS is defined from the moment when VDDOSC3 = 3.13 V until the oscillations reach an amplitude at XTAL1 of
0,3 × VDDOSC3. This parameter is verified by device characterization. The external oscillator circuitry must be
optimized by the customer and checked for negative resistance as recommended and specified by crystal
suppliers.
3) Any ESR0 activation is internally prolonged to SCU_RSTCNTCON.RELSA FPI bus clock (fFPI) cycles.
Data Sheet
154
V1.3, 2014-08
TC1797
Electrical Parameters
4) Applicable for input pins TESTMODE and TRST.
5) fFPI = fCPU/2
6) Not subject to production test, verified by design / characterization.
7) This parameter includes the delay of the analog spike filter in the PORST pad.
8) The duration of the boot-time is defined between the rising edge of the PORST and the moment when the first
user instruction has entered the CPU and its processing starts.
9) The duration of the boot time is defined between the rising edge of the internal application reset and the clock
cycle when the first user instruction has entered the CPU pipeline and its processing starts.
10) The given time includes the time of the internal reset extension for a configured value of
SCU_RSTCNTCON.RELSA = 0x05BE.
VD D P -12%
V D D PPA
V D D PPA
VDDP
VDD
VD D -12%
tPOA
tPOA
PORST
tPOH
TRST
TESTMODE
tPOH
t hd
t hd
ESR0
tHDH
tHDH
tHDH
HWCFG
t PIP
tPI
t PIP
tPI
Pads
tPI
tPI
t PIP
tPI
Pad-state undefined
Tri-state or pull device active
reset_beh2
As programmed
Figure 27
Data Sheet
Power, Pad and Reset Timing
155
V1.3, 2014-08
TC1797
Electrical Parameters
5.3.5
Phase Locked Loop (PLL)
Note: All PLL characteristics defined on this and the next page are not subject to
production test, but verified by design characterization.
Table 19
PLL Parameters (Operating Conditions apply)
Parameter
Symbol
|Dm|
VCO frequency range
fVCO
VCO input frequency range fREF
fPLLBASE
PLL base frequency1)
PLL lock-in time
tL
Accumulated jitter
Min.
Values
Typ.
Max.
Unit Note /
Test Con
dition
–
–
7
ns
–
400
–
800
MHz –
8
–
16
MHz –
50
200
320
MHz –
–
–
200
μs
–
1) The CPU base frequency with which the application software starts after PORST is calculated by dividing the
limit values by 16 (this is the K2 factor after reset).
Phase Locked Loop Operation
When PLL operation is enabled and configured, the PLL clock fVCO (and with it the LMBBus clock fLMB) is constantly adjusted to the selected frequency. The PLL is constantly
adjusting its output frequency to correspond to the input frequency (from crystal or clock
source), resulting in an accumulated jitter that is limited. This means that the relative
deviation for periods of more than one clock cycle is lower than for a single clock cycle.
This is especially important for bus cycles using waitstates and for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
Two formulas are defined for the (absolute) approximate maximum value of jitter Dm in
[ns] dependent on the K2 - factor, the LMB clock frequency fLMB in [MHz], and the
number m of consecutive fLMB clock periods.
for
( K2 ≤ 100 )
( m ≤ ( f LMB [ MHz ] ) ⁄ 2 )
and
( 1 – 0, 01 × K2 ) × ( m – 1 )
D m [ ns ] = ⎛⎝ --------------------------------------------- + 5⎞⎠ × ⎛⎝ ---------------------------------------------------------------- + 0, 01 × K2⎞⎠
0, 5 × f LMB [ MHz ] – 1
K2 × f LMB [ MHz ]
740
else
Data Sheet
740
D m [ ns ] = --------------------------------------------- + 5
K2 × f LMB [ MHz ]
156
(2)
(3)
V1.3, 2014-08
TC1797
Electrical Parameters
With rising number m of clock cycles the maximum jitter increases linearly up to a value
of m that is defined by the K2-factor of the PLL. Beyond this value of m the maximum
accumulated jitter remains at a constant value. Further, a lower LMB-Bus clock
frequency fLMB results in a higher absolute maximum jitter value.
Figure 28 gives the jitter curves for several K2 / fLMB combinations.
±10.0
Dm ns
fLMB = 50 MHz (K2 = 8)
fLMB = 100 MHz (K2 = 4)
±8.0
±7.0
±6.0
fLMB = 180 MHz (K2 = 4)
±4.0
fLMB = 150 MHz (K2 = 4)
fLMB = 100 MHz (K2 = 8)
±2.0
fLMB = 50 MHz (K2 = 16)
±1.0
±0.0
0
20
40
60
Dm = Max. jitter
m = Number of consecutive fLMB periods
K2 = K2-divider of PLL
Figure 28
80
100
120
oo
m
TC1797_PLL_JITT_M
Approximated Maximum Accumulated PLL Jitter for Typical LMBBus Clock Frequencies fLMB
Note: The specified PLL jitter values are valid if the capacitive load per output pin does
not exceed CL = 20 pF with the maximum driver and sharp edge, except the E-Ray
output pins, which can be loaded with CL = 25 pF. In case of applications with
many pins with high loads, driver strengths and toggle rates the specified jitter
values could be exceeded.
Note: The maximum peak-to-peak noise on the pad supply voltage, measured between
VDDOSC3 at pin E26 and VSSOSC at pin F25, is limited to a peak-to-peak voltage of
VPP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise
frequencies above 300 KHz.
The maximum peak-to peak noise on the pad supply votage, measured between
VDDOSC at pin F26 and VSSOSC at pin F25, is limited to a peak-to-peak voltage of
VPP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise
Data Sheet
157
V1.3, 2014-08
TC1797
Electrical Parameters
frequencies above 300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage
as near as possible to the supply pins and using PCB supply and ground planes.
Data Sheet
158
V1.3, 2014-08
TC1797
Electrical Parameters
5.3.6
E-Ray Phase Locked Loop (E-Ray PLL)
Note: All PLL characteristics defined on this and the next page are not subject to
production test, but verified by design characterization.
Table 20
PLL Parameters of the System PLL(Operating Conditions apply)
Parameter
Symbol
Min.
Typ.
Max.
Unit Note /
Test Con
dition
DP_ERAY_I
Accumulated jitter at
E_Ray module clock input1)
–
–
0.5
ns
–
Accumulated jitter at
SYSCLK pin2)
DP_ERAY_E
–
–
0.8
ns
–
VCO frequency range
fVCO_ERAY
400
–
500
MHz –
20
–
40
MHz –
–
320
MHz –
–
200
μs
VCO input frequency range fREF_ERAY
PLL base frequency3)
PLL lock-in time
Values
fPLLBASE_ERAY 140
tL_ERAY
–
–
1) Short term jitter and long term jitter for all numbers P of sample clocks (P ≥ 1), with fOSC = 20MHz, K = 6, and
fSAMPLE = 80 MHz.
2) Short term jitter and long term jitter for all numbers P of sample clocks (P ≥ 1), with fOSC = 20MHz, K = 6, and
fSAMPLE = 80 MHz.
3) The CPU base frequency which is selected after reset is calculated by dividing the limit values by 16 (this is
the K factor after reset).
Note: The specified PLL jitter values are valid if the capacitive load per output pin does
not exceed CL = 20 pF with the maximum driver and sharp edge, except the E-Ray
output pins, which can be loaded with CL = 25 pF. In case of applications with
many pins with high loads, driver strengths and toggle rates the specified jitter
values could be exceeded.
Note: The maximum peak-to-peak noise on the pad supply voltage, measured between
VDDPF3 at pin G24 and VSSOSC at pin F25, is limited to a peak-to-peak voltage of
VPP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise
frequencies above 300 KHz.
The maximum peak-to peak noise on the pad supply voltage, measured between
VDDPF at pin G23 and VSSOSC at pin F25, is limited to a peak-to-peak voltage of
VPP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise
frequencies above 300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage
as near as possible to the supply pins and using PCB supply and ground planes.
Data Sheet
159
V1.3, 2014-08
TC1797
Electrical Parameters
5.3.7
BFCLKO Output Clock Timing
VSS = 0 V;VDD = 1.5 V ± 5%; VDDEBU = 2.5 V ± 5% and 3.3 V ± 5%,;
TA = -40 °C to +125 °C; CL = 35 pF
BFCLK0 Output Clock Timing Parameters1)
Table 21
Parameter
Symbol
Values
Max.
Unit Note /
Test Con
dition
13.332) –
–
ns
–
3
–
–
ns
–
3
–
–
ns
–
–
–
3
ns
–
Min.
BFCLKO clock period
BFCLKO high time
BFCLKO low time
BFCLKO rise time
BFCLKO fall time
BFCLKO duty cycle t5/(t5 + t6)3)
tBFCLKO CC
t5
CC
t6
CC
t7
CC
t8
CC
DC
Typ.
–
–
3
ns
–
45
50
55
%
–
1) Not subject to production test, verified by design/characterization.
2) The PLL jitter characteristics add to this value according to the application settings. See the PLL jitter
parameters.
3) The PLL jitter is not included in this parameter. If the BFCLKO frequency is equal to fCPU, the K divider has to
be regarded.
tBFCLKO
BFCLKO
0.5 VDDP05
t5
t6
t8
t7
0.9 VDD
0.1 VDD
MCT04883_mod
Figure 29
Data Sheet
BFCLKO Output Clock Timing
160
V1.3, 2014-08
TC1797
Electrical Parameters
5.3.8
JTAG Interface Timing
The following parameters are applicable for communication through the JTAG debug
interface. The JTAG module is fully compliant with IEEE1149.1-2000.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Table 22
JTAG Interface Timing Parameters
(Operating Conditions apply)
Parameter
Min.
Typ.
Max.
Unit Note /
Test Condition
t1 SR
t2 SR
t3 SR
t4 SR
t5 SR
t6 SR
25
–
–
ns
–
12
–
–
ns
–
10
–
–
ns
–
–
–
4
ns
–
–
–
4
ns
–
6
–
–
ns
–
t7 SR
6
–
–
ns
–
TDO valid after TCK falling t8 CC
edge1) (propagation delay) t CC
8
–
–
13
ns
CL = 50 pF
–
–
3
ns
CL = 20 pF
TDO hold after TCK falling t18 CC
edge1)
2
–
–
ns
TCK clock period
TCK high time
TCK low time
TCK clock rise time
TCK clock fall time
TDI/TMS setup
to TCK rising edge
TDI/TMS hold
after TCK rising edge
Symbol
Values
TDO high imped. to valid
from TCK falling edge1)2)
t9 CC
–
–
14
ns
CL = 50 pF
TDO valid to high imped.
from TCK falling edge1)
t10 CC
–
–
13.5
ns
CL = 50 pF
1) The falling edge on TCK is used to generate the TDO timing.
2) The setup time for TDO is given implicitly by the TCK cycle time.
Data Sheet
161
V1.3, 2014-08
TC1797
Electrical Parameters
t1
0.9 VD D P
0.5 VD D P
t5
t2
0.1 VD D P
t4
t3
MC_ JTAG_ TCK
Figure 30
Test Clock Timing (TCK)
TCK
t6
t7
t6
t7
TMS
TDI
t9
t8
t1 0
TDO
t18
MC_JTAG
Figure 31
Data Sheet
JTAG Timing
162
V1.3, 2014-08
TC1797
Electrical Parameters
5.3.9
DAP Interface Timing
The following parameters are applicable for communication through the DAP debug
interface.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Table 23
DAP Interface Timing Parameters
(Operating Conditions apply)
Parameter
Symbol
Min.
Typ.
Max.
Unit Note /
Test Condition
t11 SR
t12 SR
t13 SR
t14 SR
t15 SR
t16 SR
12.5
–
–
ns
–
4
–
–
ns
–
4
–
–
ns
–
–
–
2
ns
–
–
–
2
ns
–
6
–
–
ns
–
DAP1 hold
after DAP0 rising edge
t17 SR
6
–
–
ns
–
DAP1 valid
per DAP0 clock period1)
t19 SR
8
–
–
ns
80 MHz,
CL = 20 pF
t19 SR
10
–
–
ns
40 MHz,
CL = 50 pF
DAP0 clock period
DAP0 high time
DAP0 low time
DAP0 clock rise time
DAP0 clock fall time
DAP1 setup
to DAP0 rising edge
Values
1) The Host has to find a suitable sampling point by analyzing the sync telegram response.
t11
0.9 VD D P
0.5 VD D P
t1 5
t1 2
t14
0.1 VD D P
t1 3
MC_DAP0
Figure 32
Data Sheet
Test Clock Timing (DAP0)
163
V1.3, 2014-08
TC1797
Electrical Parameters
DAP0
t1 6
t1 7
DAP1
MC_ DAP1_RX
Figure 33
DAP Timing Host to Device
t1 1
DAP1
t1 9
MC_ DAP1_TX
Figure 34
Data Sheet
DAP Timing Device to Host
164
V1.3, 2014-08
TC1797
Electrical Parameters
5.3.10
EBU Timings
VSS = 0 V;VDD = 1.5 V ± 5%; VDDEBU = 2.5 V ± 5% and 3.3 V ± 5%, Class B pins;
TA = -40 °C to +125 °C; CL = 35 pF for address/data; CL = 40pF for the control lines.
5.3.10.1 EBU Asynchronous Timings
For each timing, the accumulated PLL jitter of the programed duration in number of clock
periods must be added separately. Operating conditions apply and CL = 35 pF.
Table 24
Common timing parameters for all asynchronous timings1)
Parameter
Symbol
Limit Values Unit Edge
Setting
max
min
Pulse width deviation from the ideal
programmed width due to the A2 pad
asymmetry, strong driver mode,
rise delay - fall delay. CL = 35 pF.
ta
CC -1
-2
AD(31:0) output delay to ADV rising edge, t13
AD(31:0) output delay multiplexed
t14
read / write
1.5
ns
sharp
1
medium
CC -5.5
2
–
CC -5.5
2
–
1) Not subject to production test, verified by design/characterization.
Data Sheet
165
V1.3, 2014-08
TC1797
Electrical Parameters
Read Timings
Table 25
Asynchronous read timings, multiplexed and demultiplexed1)
Parameter
Symbol
Limit Values
min
A(23:0) output delay
A(23:0) output delay
CS rising edge
to RD rising edge,
t0
deviation from the ideal t
1
programmed value.
t2
t3
t4
t5
t6
t7
t8
t9
ADV rising edge
BC rising edge
WAIT input setup
WAIT input hold
Data input setup
Data input hold
MR / W output delay
Unit
max
CC -2.5
2.5
CC -2.5
2.5
CC -2
2.5
CC -1.5
4.5
CC -2.5
2.5
SR 12
–
SR 0
–
SR 12
–
SR 0
–
CC -2.5
1.5
ns
1) Not subject to production test, verified by design/characterization.
Data Sheet
166
V1.3, 2014-08
TC1797
Electrical Parameters
Multiplexed Read Timing
EBU
STATE
Address
Phase
Address Hold
Phase (opt.)
Command
Delay Phase
Command
Phase
Recovery
Phase (opt.)
New Addr.
Phase
Control Bitfield:
ADDRC
AHOLDC
CMDDELAY
RDWAIT
RDRECOVC
ADDRC
1...15
0...15
0...7
1...31
Duration Limits in
EBU_CLK Cycles
0...15
1...15
Next
Addr.
Valid Address
A[23:0]
pv + t0
pv + ta
pv +
t1
t2
CS[3:0]
CSCOMB
pv + ta
pv +
t3
ADV
pv +
ta
RD
pv +
ta
pv +
ta
t4
BC[3:0]
pv +
t5
t6
WAIT
pv +
AD[31:0]
MR/W
t13
pv +
t14
t7
Address Out
Data In
pv +
t9
pv = programmed value,
TEBU_CLK * sum (correponding bitfield values)
Figure 35
Data Sheet
t8
new_MuxRD_Async_10.vsd
Multiplexed Read Access
167
V1.3, 2014-08
TC1797
Electrical Parameters
Demultiplexed Read Timing
EBU
STATE
Control Bitfield:
Duration Limits in
EBU_CLK Cycles
Address
Phase
Address Hold
Phase (opt.)
Command
Phase
Recovery
Phase (opt.)
New Addr.
Phase
ADDRC
AHOLDC
RDWAIT
RDRECOVC
ADDRC
1...15
0...15
1...31
0...15
Next
Addr.
Valid Address
A[23:0]
pv +
pv + t1
t0
pv +
CS[3:0]
CSCOMB
pv +
1...15
t2
ta
pv + t3
ta
ADV
pv +
ta
RD
pv +
ta
pv + ta
t4
BC[3:0]
pv +
t5
t6
WAIT
t7
AD[31:0]
Data In
MR/W
pv +
pv = programmed value,
TEBU_CLK * sum (correponding bitfield values)
Figure 36
Data Sheet
t8
t9
new_DemuxRD_Async_10.vsd
Demultiplexed Read Access
168
V1.3, 2014-08
TC1797
Electrical Parameters
Write Timings
Table 26
Asynchronous write timings, multiplexed and demultiplexed1)
Parameter
Symbol Limit Values
A(23:0) output delay to RD/WR rising edge,
A(23:0) output delay deviation from the ideal
programmed value.
CS rising edge
t30
t31
t32
t33
t34
t35
t36
t37
t38
t39
min
ADV rising edge
BC rising edge
WAIT input setup
WAIT input hold
Data output delay
Data output delay
MR / W output delay
Unit
max
CC -2.5
2.5
CC -2.5
2.5
CC -2
2
CC -2
4.5
CC -2.5
2
SR 12
–
SR 0
–
CC -5.5
2
CC -5.5
2
CC -2.5
1.5
ns
1) Not subject to production test, verified by design/characterization.
Data Sheet
169
V1.3, 2014-08
TC1797
Electrical Parameters
Multiplexed Write Timing
EBU
STATE
Address
Phase
Address Hold
Phase (opt.)
Command
Phase
Data
Hold Phase
Recovery
Phase (opt.)
Control Bitfield:
ADDRC
AHOLDC
RDWAIT
DATAC
RDRECOVC
1...31
0...15
Duration Limits in
EBU_CLK Cycles
1...15
0...15
A[23:0]
0...15
pv + t30
pv +
ADDRC
1...15
Next
Addr.
Valid Address
CS[3:0]
CSCOMB
New Addr.
Phase
pv + t31
ta
pv + t32
pv + t33
pv + ta
ADV
pv +
ta
RD/WR
pv +
ta
pv +
ta
t34
BC[3:0]
t35
WAIT
t36
pv +
AD[31:0]
MR/W
t14
t13
t37
Data Out
Address Out
pv + t39
pv = programmed value,
TEBU_CLK * sum (correponding bitfield values)
Figure 37
Data Sheet
pv + t38
new_MuxWR_Async_10.vsd
Multiplexed Write Access
170
V1.3, 2014-08
TC1797
Electrical Parameters
Demultiplexed Write Timing
EBU
STATE
Address
Phase
Control Bitfield:
ADDRC
Duration Limits in
EBU_CLK Cycles
1...15
Address Hold
Phase (opt.)
AHOLDC
0...15
A[23:0]
Command
Phase
Data
Hold Phase
RDWAIT
DATAC
1...31
0...15
Recovery
Phase (opt.)
RDRECOVC
0...15
pv + t30
pv +
ADDRC
1...15
Next
Addr.
Valid Address
CS[3:0]
CSCOMB
New Addr.
Phase
pv + t31
ta
pv + t32
pv + t33
pv + ta
ADV
pv +
ta
RD/WR
pv +
ta
pv +
ta
t34
BC[3:0]
t35
WAIT
t36
t37
AD[31:0]
MR/W
Data Out
pv + t39
pv = programmed value,
TEBU_CLK * sum (correponding bitfield values)
Figure 38
Data Sheet
pv + t38
new_DemuxWR_Async_10.vsd
Demultiplexed Write Access
171
V1.3, 2014-08
TC1797
Electrical Parameters
5.3.10.2 EBU Burst Mode Access Timing
VSS = 0 V;VDD = 1.5 V ± 5%; VDDEBU = 2.5 V ± 5% and 3.3 V ± 5%, Class B pins;
TA = -40 °C to +125 °C; CL = 35 pF;
Table 27
EBU Burst Mode Read / Write Access Timing Parameters1)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note /
Test Con
dition
t10
CC
-2
–
2
ns
–
RD and RD/WR active/inactive t12
after BFCLKO active edge3)
CC
-2
–
2
ns
–
Output delay from BFCLKO
active edge2)
CSx output delay from
BFCLKO active edge3)
t21
CC -2.5
–
1.5
ns
–
ADV active/inactive after
BFCLKO active edge4)
t22
CC -2
–
2
ns
–
BAA active/inactive after
BFCLKO active edge4)
t22a
CC -2.5
–
1.5
ns
–
Data setup to BFCLKI rising
edge5)
t23
SR 3
–
–
ns
–
Data hold from BFCLKI rising
edge5)
t24
SR 0
–
–
ns
–
WAIT setup (low or high) to
BFCLKI rising edge5)
t25
SR 3
–
–
ns
–
WAIT hold (low or high) from
BFCLKI rising edge5)
t26
SR 0
–
–
ns
–
1) Not subject to production test, verified by design/characterization.
2) This is a default parameter which are applicable to all timings which are not explicitly covered by the other
parameters.
3) An active edge can be rising or falling edge, depending on the settings of bits BFCON.EBSE / ECSE and clock
divider ratio.
Negative minimum values for these parameters mean that the last data read during a burst may be corrupted.
However, with clock feedback enabled, this value is oversampling not required for the LMB transaction and
will be discarded.
4) This parameter is valid for BUSCONx.EBSE = 1 and BUSAPx.EXTCLK = 00B.
For BUSCONx.EBSE = 1 and other values of BUSAPx.EXTCLK, ADV and BAA will be delayed by 1 / 2 of the
LMB bus clock period TCPU = 1 / fCPU.
For BUSCONx. EBSE = 0 and BUSAPx.EXTCLK = 11B, add 2 LMB clock periods.
For BUSCONx. EBSE = 0 and other values of BUSAPx.EXTCLK add 1 LMB clock period.
Data Sheet
172
V1.3, 2014-08
TC1797
Electrical Parameters
5) If the clock feedback is not enabled, the input signals are latched using the internal clock in the same way as
at asynchronous access. So t5, t6, t7 and t8 from the asynchronous timings apply.
Address
Phase(s)
BFCLKI
BFCLKO
Command
Phase(s)
Burst
Phase(s)
Burst
Phase(s)
Recovery
Phase(s)
Next Addr.
Phase(s)
1)
t10
t10
A[23:0]
Next
Addr.
Burst Start Address
t22
t22
t22
ADV
t21
t21
t21
CS[3:0]
CSCOMB
t12
t12
RD
RD/WR
t22a
t22a
BAA
t24
t23
D[31:0]
(32-Bit)
D[15:0]
(16-Bit)
t25
t24
t23
Data (Addr+0)
Data (Addr+4)
Data (Addr+0)
Data (Addr+2)
t26
WAIT
1)
Figure 39
Data Sheet
Output delays are always referenced to BCLKO. The reference clock for input
characteristics depends on bit EBU_BFCON.FDBKEN.
EBU_BFCON.FDBKEN = 0: BFCLKO is the input reference clock.
EBU_BFCON.FDBKEN = 1: BFCLKI is the input reference clock (EBU clock
feedback enabled).
BurstRDWR_4.vsd
EBU Burst Mode Read / Write Access Timing
173
V1.3, 2014-08
TC1797
Electrical Parameters
5.3.10.3 EBU Arbitration Signal Timing
VSS = 0 V;VDD = 1.5 V ± 5%; VDDEBU = 2.5 V ± 5% and 3.3 V ± 5%, Class B pins;
TA = -40°C to +125 °C; CL = 35 pF;
Table 28
EBU Arbitration Signal Timing Parameters1)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit Note /
Test Con
dition
Output delay from BFCLKO
rising edge
t27
CC –
–
3
ns
–
Data setup to BFCLKO
falling edge
t28
SR 11
–
–
ns
–
Data hold from BFCLKO
falling edge
t29
SR 2
–
–
ns
–
1) Not subject to production test, verified by design/characterization.
BFCLKO
t27
t27
HLDA Output
t27
t27
BREQ Output
BFCLKO
t28
t28
t29
t29
HOLD Input
HLDA Input
Figure 40
Data Sheet
EBUArb_1
EBU Arbitration Signal Timing
174
V1.3, 2014-08
TC1797
Electrical Parameters
5.3.11
Peripheral Timings
Note: Peripheral timing parameters are not subject to production test. They are verified
by design/characterization.
5.3.11.1 Micro Link Interface (MLI) Timing
MLI Transmitter Timing
t13
t14
t10
t12
TCLKx
t11
t15
t15
TDATAx
TVALIDx
t16
t17
TREADYx
MLI Receiver Timing
t23
t24
t20
t22
RCLKx
t21
t25
t26
RDATAx
RVALIDx
t27
t27
RREADYx
MLI_Tmg_2.vsd
Figure 41
Data Sheet
MLI Interface Timing
175
V1.3, 2014-08
TC1797
Electrical Parameters
Note: The generation of RREADYx is in the input clock domain of the receiver. The
reception of TREADYx is asynchronous to TCLKx.
Table 29
MLI Timings (Operating Conditions apply), CL = 50 pF
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit Note /
Test Co
ndition
–
–
ns
MLI Transmitter Timing
TCLK clock period
TCLK high time
TCLK low time
TCLK rise time
TCLK fall time
TDATA/TVALID output
delay time
t10
t11
t12
t13
t14
t15
CC 2 × TMLI
1)
0.45 × t10 0.5 × t10 0.55 × t10 ns
2)3)
CC 0.45 × t10 0.5 × t10 0.55 × t10 ns
2)3)
CC
–
4)
CC –
–
4)
ns
–
CC -3
–
4.4
ns
–
CC –
ns
–
TREADY setup time to
TCLK rising edge
t16
SR 18
–
–
ns
–
TREADY hold time from
TCLK rising edge
t17
SR 0
–
–
ns
–
SR 1 × TMLI
–
–
ns
1)
SR –
0.5 × t20 –
ns
5)6)
RCLK low time
t20
t21
t22
SR –
0.5 × t2
0
–
ns
5)6)
RCLK rise time
t23
MLI Receiver Timing
RCLK clock period
RCLK high time
S
–
–
4
ns
7)
S
–
–
4
ns
7)
S
4.2
–
–
ns
–
RDATA/RVALID hold time t26
from RCLK rising edge
R
S
2.2
–
–
ns
–
RREADY output delay time t27
C
C
0
–
16
ns
–
R
RCLK fall time
t24
R
RDATA/RVALID setup
time to RCLK falling edge
t25
R
1) TMLImin. = TSYS = 1/fSYS. When fSYS = 90 MHz, t10 = 22.22 ns and t20 = 11.11 ns.
2) The following formula is valid: t11 + t12 = t10
Data Sheet
176
V1.3, 2014-08
TC1797
Electrical Parameters
3) The min./max. TCLK low/high times t11/t12 include the PLL jitter of fSYS. Fractional divider settings must be
regarded additionally to t11 / t12.
4) For high-speed MLI interface, strong driver sharp or medium edge selection (class A2 pad) is recommended
for TCLK.
5) The following formula is valid: t21 + t22 = t20
6) The min. and max. value of is parameter can be adjusted by considering the other receiver timing parameters.
7) The RCLK max. input rise/fall times are best case parameters for fSYS = 90 MHz. For reduction of EMI, slower
input signal rise/fall times can be used for longer RCLK clock periods.
Data Sheet
177
V1.3, 2014-08
TC1797
Electrical Parameters
5.3.11.2 Micro Second Channel (MSC) Interface Timing
Table 30
MSC Interface Timing (Operating Conditions apply), CL = 50 pF
Parameter
Symbol
Values
Min.
FCLP clock period1)2)
SOP/ENx outputs delay
from FCLP rising edge
SDI bit time
SDI rise time
SDI fall time
Typ.
Unit
Note /
Test Con
dition
Max.
t40
t45
CC 2 × TMSC3) –
–
ns
–
CC -10
10
ns
–
t46
t48
t49
CC 8 × TMSC
–
ns
–
SR
100
ns
–
SR
100
ns
–
1) FCLP signal rise/fall times are the same as the A2 Pads rise/fall times.
2) FCLP signal high and low can be minimum 1 × TMSC.
3) TMSCmin = TSYS = 1 / fSYS. When fSYS = 90 MHz, t40 = 22,2ns
t40
0.9 VDDP
0.1 VDDP
FCLP
t45
t45
SOP
EN
t48
t49
0.9 VDDP
0.1 VDDP
SDI
t46
t46
MSC_Tmg_1.vsd
Figure 42
MSC Interface Timing
Note: The data at SOP should be sampled with the falling edge of FCLP in the target
device.
Data Sheet
178
V1.3, 2014-08
TC1797
Electrical Parameters
5.3.11.3 SSC Master/Slave Mode Timing
Table 31
SSC Master/Slave Mode Timing
(Operating Conditions apply), CL = 50 pF
Parameter
Symbol
Values
Min.
Typ. Max.
Unit Note /
Test Con
dition
–
–
ns
1)2)3)
–
8
ns
–
Master Mode Timing
SCLK clock period
MTSR/SLSOx delay from
SCLK rising edge
t50
t51
CC 2 × TSSC
CC
0
MRST setup to SCLK
falling edge
t52
SR 13
–
–
ns
3)
MRST hold from SCLK
falling edge
t53
SR 0
–
–
ns
3)
t54
SR 4 × TSSC
t55/t54 SR 45
t56
SR TSSC + 5
–
–
ns
1)3)
–
55
%
–
–
–
ns
3)4)
MTSR hold from SCLK
latching edge
t57
SR TSSC + 5
–
–
ns
3)4)
SLSI setup to first SCLK
shift edge
t58
SR TSSC + 5
–
–
ns
3)
SLSI hold from last SCLK
latching edge
t59
SR 7
–
–
ns
–
MRST delay from SCLK
shift edge
t60
CC 0
–
15
ns
–
SLSI to valid data on MRST t61
CC –
–
12
ns
–
Slave Mode Timing
SCLK clock period
SCLK duty cycle
MTSR setup to SCLK
latching edge
1) SCLK signal rise/fall times are the same as the A2 Pads rise/fall times.
2) SCLK signal high and low times can be minimum 1 × TSSC.
3) TSSCmin = TSYS = 1/fSYS. When fSYS = 90 MHz, t50 = 22.2 ns.
4) Fractional divider switched off, SSC internal baud rate generation used.
Data Sheet
179
V1.3, 2014-08
TC1797
Electrical Parameters
t50
SCLK1)2)
t51
t51
MTSR1)
t52
t53
Data
valid
1)
MRST
t51
2)
SLSOx
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
2) The transition at SLSOx is based on the following setup: SSOTC.TRAIL = 0
and the first SCLK high pulse is in the first one of a transmission.
SSC_TmgMM
Figure 43
SSC Master Mode Timing
t54
First latching
SCLK edge
First shift
SCLK edge
SCLK1)
t55
t56
Last latching
SCLK edge
t55
t56
t57
Data
valid
1)
MTSR
t60
t57
Data
valid
t60
1)
MRST
t61
SLSI
t59
t58
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
SSC_TmgSM
Figure 44
Data Sheet
SSC Slave Mode Timing
180
V1.3, 2014-08
TC1797
Electrical Parameters
5.3.11.4 E-Ray Interface Timing
The timings in this section are valid for the strong / sharp and strong / medium settings
of the output drivers, and for both A1 or A2 input pads. The timing parameters are not
subject to production test, but verified by design / characterization.
Table 32
E-Ray Interface Timing (Operating Conditions apply), CL = 25 pF
Parameter
Symbol
Limit Values
Min.
Typ. Max.
Unit Notes
Conditions
TxDA / TxDB Signal Timing at end of frame
t60
Time span from last
BSS to FES without the
influence of quartz
tolerances d10Bit_Tx 1)
TxD data valid, from
fsample flip-flop txd_reg
⇒ TxDA, TxDB,
(dTxAsym) 2) 3)
CC 997.75 –
1002.25 ns
foscdd = 20MHz;
foscdd = 40MHz;
CL = 25 pF
(TxDA, TXDB)
|t61 - t62| CC –
–
1.5
ns
Asymmetrical
delay of rising
and falling edge
(TxDA, TxDB)
–
1046.1
ns
foscdd = 20MHz;
foscdd = 40MHz;
CL = 25 pF
RxDA / RxDB Signal Timing at end of frame
Time span between last t63
BSS and FES that is
properly decoded,
without influence of
quartz tolerances
d10Bit_Rx 1) 4) 5)
RxD capture by fsample,
RxDA / RxDB ⇒
sampling flip-flop,
(dRxAsym) 5)
SR 966
(TxDA, TXDB)
|t64 - t65| CC –
–
3.0
ns
Asymmetrical
delay of rising
and falling edge
(RxDA, RxDB)
1) PLL jitter included.
2) Refers to delays caused by the asymmetries of the output drivers of the digital logic and the GPIO pad drivers.
Quartz tolerance and PLL jitter are not included.
3) E-Ray TxD output drivers have an asymmetry of rising and falling edges of |tF - tR| ≤ 1 ns.
4) Limits of 966.5 ns and 1046 ns correspond to (30%, 70%) × VDDP FlexRay standard input thresholds.
Due to different input thresholds of the TC1797, a correcton of -0.5 ns and +0.1 ns has been applied.
5) Valid for output slopes of the Bus Driver of dRxSlope ≤ 5 ns, 20% × VDDP to 80% × VDDP, according to the
FlexRay Electrical Physical Layer Specification V2.1 B. For A1 pads, the rise and fall times of the incoming
signal have to satisfy the following inequality: -1.6 ns ≤ tF - tR ≤ 1.3 ns .
Data Sheet
181
V1.3, 2014-08
TC1797
Electrical Parameters
Last CRC Byte
BSS
FES
Frame End Sequence
Byte Start
Sequence
0.7 VDDP
0.3 VDDP
TXD
t60
tsample
TXD
0.9 VDDP
0.1 VDDP
t61
BSS
t62
Last CRC Byte
Byte Start
Sequence
FES
Frame End Sequence
0.62 VDDP
0.36 VDDP
RXD
t63
tsample
0.62 VDDP
RXD
0.36 VDDP
t64
t65
E-RAY_TIMING_A1
Figure 45
Data Sheet
E-Ray Timing
182
V1.3, 2014-08
TC1797
Electrical Parameters
5.4
Package and Reliability
5.4.1
Package Parameters
Table 33
Thermal Characteristics of the Package
Device
Package
RΘJCT1)
RΘJCB1)
Unit
TC1797
P/PG-BGA-416-10 /
P/PG-BGA-416-27
4
6
K/W
Note
1) The top and bottom thermal resistances between the case and the ambient (RTCAT, RTCAB) are to be combined
with the thermal resistances between the junction and the case given above (RTJCT, RTJCB), in order to
calculate the total thermal resistance between the junction and the ambient (RTJA). The thermal resistances
between the case and the ambient (RTCAT, RTCAB) depend on the external system (PCB, case) characteristics,
and are under user responsibility.
The junction temperature can be calculated using the following equation: TJ = TA + RTJA × PD, where the RTJA
is the total thermal resistance between the junction and the ambient. This total junction ambient resistance
RTJA can be obtained from the upper four partial thermal resistances.
Thermal resistances as measured by the ‘cold plate method’ (MIL SPEC-883 Method 1012.1).
Data Sheet
183
V1.3, 2014-08
TC1797
Electrical Parameters
5.4.2
Package Outline
25 x 1 = 25
A26
1
25 x 1 = 25
A1
AF1
(0.56)
0.5 ±0.1
(1.17)
2.5 MAX.
1
ø0.63 +0.07
-0.13
416x
ø0.25 M A B C
ø0.1 M C
0.15
C
27 ±0.2
24 ±0.5
20 ±0.2
A
Index Marking
20 ±0.2
24 ±0.5
27 ±0.2
Index Marking
(sharp edge)
B
PG-BGA-416-4, -10, -13, -14-PO V02
Figure 46
Data Sheet
Package Outlines P/PG-BGA-416-10, Plastic (Green) Ball Grid Array
184
V1.3, 2014-08
TC1797
Electrical Parameters
Figure 47
Package Outlines P/PG-BGA-416-27, Plastic (Green) Ball Grid Array
You can find all of our packages, sorts of packing and others in Infineon Internet Page.
Data Sheet
185
V1.3, 2014-08
TC1797
Electrical Parameters
5.4.3
Flash Memory Parameters
The data retention time of the TC1797’s Flash memory (i.e. the time after which stored
data can still be retrieved) depends on the number of times the Flash memory has been
erased and programmed.
Table 34
Flash Parameters
Parameter
Symbol
Unit
Note /
Test Condition
–
years
Max. 1000
erase/program
cycles
–
–
years
Max. 100
erase/program
cycles
–
–
cycles Max. data
retention time
5 years
120000 –
–
cycles Max. data
retention time
5 years
–
–
5
ms
–
Program Flash Erase
tERP
–
Time per 256-KB Sector
CC
–
5
s
fCPU = 180 MHz
–
–
2.5
s
fCPU = 180 MHz
–
–
4000/fCPU μs
+ 180
Program Flash
Retention Time,
Physical Sector1)2)
tRET
Program Flash
Retention Time
Logical Sector1)2)
tRETL
Data Flash
Endurance
(64 KB)
NE
Data Flash Endurance,
EEPROM Emulation
(4 × 16 KB)
NE8
Programming Time
per Page3)
tPR
Values
Min.
Typ. Max.
20
–
20
30 000
CC
CC
CC
CC
CC
Data Flash Erase Time
for 2 × 32-KB Sectors
tERD
Wake-up time
tWU
CC
CC
–
1) Storage and inactive time included.
2) At average weighted junction temperature Tj = 100oC, or
the retention time at average weighted temperature of Tj = 110oC is minimum 10 years, or
the retention time at average weighted temperature of Tj = 150oC is minimum 0.7 years.
3) In case the Program Verify feature detects weak bits, these bits will be programmed once more. The
reprogramming takes additional 5 ms.
Data Sheet
186
V1.3, 2014-08
TC1797
Electrical Parameters
5.4.4
Table 35
Quality Declarations
Quality Parameters
Parameter
Symbol
Values
Unit
Note / Test Condition
Min. Typ. Max.
–
–
24000 hours –2) 3)
ESD susceptibility VHBM
according to
Human Body
Model (HBM)
–
–
2000
V
Conforming to
JESD22-A114-B
ESD susceptibility VHBM1
of the LVDS pins
–
–
500
V
–
ESD susceptibility VCDM
according to
Charged Device
Model (CDM)
–
–
500
V
Conforming to
JESD22-C101-C
Moisture
Sensitivity Level
–
–
3
–
Conforming to Jedec
J-STD-020C for 240°C
Operation
Lifetime1)
tOP
MSL
1) This lifetime refers only to the time when the device is powered on.
2) For worst-case temperature profile equivalent to:
2000 hours at Tj = 150oC
16000 hours at Tj = 125oC
6000 hours at Tj = 110oC
3) This 30000 hours worst-case temperature profile is also covered:
300 hours at Tj = 150oC
1000 hours at Tj = 140oC
1700 hours at Tj = 130oC
24000 hours at Tj = 120oC
3000 hours at Tj = 110oC
Data Sheet
187
V1.3, 2014-08
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Published by Infineon Technologies AG