TC1793 Data Sheet

32-Bit
Microcontroller
TC1793
32-Bit Single-Chip Microcontroller
Data Sheet
V 1.2 2014-05
Microcontrollers
Edition 2014-05
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2014 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
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Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
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approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
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be endangered.
32-Bit
Microcontroller
TC1793
32-Bit Single-Chip Microcontroller
Data Sheet
V 1.2 2014-05
Microcontrollers
TC1793
Table of Contents
1
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
2
2.1
System Overview of the TC1793 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
3
3.1
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
TC1793 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
4
Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-88
5
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.6.1
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
5.3.10
5.3.11
5.3.12
5.3.12.1
5.3.12.2
5.3.12.3
Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-90
General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-90
Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-90
Pad Driver and Pad Classes Summary . . . . . . . . . . . . . . . . . . . . . . . 5-91
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-92
Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-94
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-96
Extended Range Operating Conditions . . . . . . . . . . . . . . . . . . . . 5-100
DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-103
Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-103
Analog to Digital Converters (ADCx) . . . . . . . . . . . . . . . . . . . . . . . . 5-121
Fast Analog to Digital Converter (FADC) . . . . . . . . . . . . . . . . . . . . . 5-126
Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-130
Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-131
Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-132
Calculating the 1.3 V Current Consumption . . . . . . . . . . . . . . . . 5-135
AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-137
Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-137
Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-138
Power, Pad and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-140
Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-142
ERAY Phase Locked Loop (ERAY_PLL) . . . . . . . . . . . . . . . . . . . . . 5-145
JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-146
DAP Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-148
Micro Link Interface (MLI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 5-149
Micro Second Channel (MSC) Interface Timing . . . . . . . . . . . . . . . 5-152
SSC Master/Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-154
ERAY Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-157
EBU Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-159
BFCLKO Output Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-159
EBU Asynchronous Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-159
EBU Burst Mode Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . 5-168
Data Sheet
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TC1793
5.3.12.4
EBU Arbitration Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4
Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5
Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.1
Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.2
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.3
Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
Data Sheet
5-171
5-172
5-174
5-174
5-175
5-175
History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
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Summary of Features
1
Summary of Features
The SAK-TC1793F-512F270EF has the following features:
•
•
•
•
•
•
•
•
High-performance 32-bit super-scalar TriCore V1.6 CPU with 6-stage pipeline
– Superior real-time performance
– Strong bit handling
– Fully integrated DSP capabilities
– Multiply-accumulate unit able to sustain 2 MAC operations per cycle
– Fully pipelined Floating point unit (FPU)
– 270 MHz operation at full temperature range
32-bit Peripheral Control Processor with single cycle instruction (PCP2)
– 16 Kbyte Parameter Memory (PRAM)
– 32 Kbyte Code Memory (CMEM)
– 200 MHz operation at full temperature range
Multiple on-chip memories
– 4 Mbyte Program Flash Memory (PFLASH) with ECC
– 192 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation
– 2 x 8 Kbyte Key Flash
– 128 Kbyte Data Scratch-Pad RAM (DSPR)
– 16 Kbyte Instruction Cache (ICACHE)
– 32 Kbyte Instruction Scratch-Pad RAM (PSPR)
– 16 Kbyte Data Cache (DACHE)
– 128 Kbyte Memory (SRAM)
– 16 Kbyte BootROM (BROM)
16-Channel DMA Controller
8-Channel Safe DMA (SDMA) Controller
Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels
serviced by CPU or PCP2
High performing on-chip bus structure
– 64-bit Cross Bar Interconnect between CPU, Flash and Data Memory
– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
– One bus bridge (SFI Bridge)
Versatile On-chip Peripheral Units
– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,
parity, framing and overrun error detection
– Four High-Speed Synchronous Serial Channels (SSC) with programmable data
length and shift direction
– Four SSC Guardian (SSCG) modules, one for each SSC
– Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external
power devices
– Two High-Speed Micro Link interfaces (MLI) for serial inter-processor
communication
Data Sheet
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TC1793
Summary of Features
•
•
•
•
•
•
•
•
•
•
– One External Bus Interface (EBU) supporting different memories: asynchronous
memories e.g. SRAM, peripheral devices; synchronous devices e.g. burst NOR
flash, PSRAM; and DDR NOR flash e.g. LPDDR-NVM (Jedec 42.2), ONFI 2.0
(limited frequency at 1.8 V I/O supply)
– One MultiCAN Module with 4 CAN nodes and 128 free assignable message
objects for high efficiency data handling via FIFO buffering and gateway data
transfer (one CAN node supports TTCAN functionality)
– One FlexRayTM module with 2 channels (E-Ray).
– Two General Purpose Timer Array Modules (GPTA) with additional Local Timer
Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer
functionality to realize autonomous and complex Input/Output management
– Two Capture / Compare 6 modules
– Two General Purpose 12 Timer Units (GPT120 and GPT121)
44 analog input lines for ADC
– 4 independent kernels (ADC0, ADC1, and ADC2)
– Analog supply voltage range from 3.3 V to 5 V (single supply)
4 different FADC input channels
– channels with impedance control and overlaid with ADC1 inputs
– Extreme fast conversion, 21 cycles of fFADC clock
– 10-bit A/D conversion (higher resolution can be achieved by averaging of
consecutive conversions in digital data reduction filter)
8 digital input lines for SENT
– communication according to the SENT specification J2716 FEB2008
221 digital general purpose I/O lines (GPIO)
Digital I/O ports with 3.3 V capability
On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Buses)
Dedicated Emulation Device chip available (TC1793ED)
– multi-core debugging, real time tracing, and calibration
– four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface
Power Management System
Clock Generation Unit with PLL and PLL_ERAY
Flexible CRC Engine (FCE)
– IEEE 802.3 CRC32 ethernet polynomial: 0x82608EDB (CRC kernel 0)
– CRC32C Castagnoli: 0xD419CC15 (CRC kernel 1)
The SAK-TC1793F-512F200EB / SAK-TC1793F-512F200EF
features:
•
has
the
following
High-performance 32-bit super-scalar TriCore V1.6 CPU with 6-stage pipeline
– Superior real-time performance
– Strong bit handling
– Fully integrated DSP capabilities
– Multiply-accumulate unit able to sustain 2 MAC operations per cycle
– Fully pipelined Floating point unit (FPU)
Data Sheet
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TC1793
Summary of Features
•
•
•
•
•
•
•
– 200 MHz operation at full temperature range
32-bit Peripheral Control Processor with single cycle instruction (PCP2)
– 16 Kbyte Parameter Memory (PRAM)
– 32 Kbyte Code Memory (CMEM)
– 200 MHz operation at full temperature range
Multiple on-chip memories
– 4 Mbyte Program Flash Memory (PFLASH) with ECC
– 192 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation
– 2 x 8 Kbyte Key Flash
– 128 Kbyte Data Scratch-Pad RAM (DSPR)
– 16 Kbyte Instruction Cache (ICACHE)
– 32 Kbyte Instruction Scratch-Pad RAM (PSPR)
– 16 Kbyte Data Cache (DACHE)
– 128 Kbyte Memory (SRAM)
– 16 Kbyte BootROM (BROM)
16-Channel DMA Controller
8-Channel Safe DMA (SDMA) Controller
Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels
serviced by CPU or PCP2
High performing on-chip bus structure
– 64-bit Cross Bar Interconnect between CPU, Flash and Data Memory
– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
– One bus bridge (SFI Bridge)
Versatile On-chip Peripheral Units
– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,
parity, framing and overrun error detection
– Four High-Speed Synchronous Serial Channels (SSC) with programmable data
length and shift direction
– Four SSC Guardian (SSCG) modules, one for each SSC
– Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external
power devices
– Two High-Speed Micro Link interfaces (MLI) for serial inter-processor
communication
– One External Bus Interface (EBU) supporting different memories: asynchronous
memories e.g. SRAM, peripheral devices; synchronous devices e.g. burst NOR
flash, PSRAM; and DDR NOR flash e.g. LPDDR-NVM (Jedec 42.2), ONFI 2.0
(limited frequency at 1.8 V I/O supply)
– One MultiCAN Module with 4 CAN nodes and 128 free assignable message
objects for high efficiency data handling via FIFO buffering and gateway data
transfer (one CAN node supports TTCAN functionality)
– One FlexRayTM module with 2 channels (E-Ray).
Data Sheet
3
V 1.2, 2014-05
TC1793
Summary of Features
•
•
•
•
•
•
•
•
•
•
– Two General Purpose Timer Array Modules (GPTA) with additional Local Timer
Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer
functionality to realize autonomous and complex Input/Output management
– Two Capture / Compare 6 modules
– Two General Purpose 12 Timer Units (GPT120 and GPT121)
44 analog input lines for ADC
– 4 independent kernels (ADC0, ADC1, and ADC2)
– Analog supply voltage range from 3.3 V to 5 V (single supply)
4 different FADC input channels
– channels with impedance control and overlaid with ADC1 inputs
– Extreme fast conversion, 21 cycles of fFADC clock
– 10-bit A/D conversion (higher resolution can be achieved by averaging of
consecutive conversions in digital data reduction filter)
8 digital input lines for SENT
– communication according to the SENT specification J2716 FEB2008
221 digital general purpose I/O lines (GPIO)
Digital I/O ports with 3.3 V capability
On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Buses)
Dedicated Emulation Device chip available (TC1793ED)
– multi-core debugging, real time tracing, and calibration
– four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface
Power Management System
Clock Generation Unit with PLL and PLL_ERAY
Flexible CRC Engine (FCE)
– IEEE 802.3 CRC32 ethernet polynomial: 0x82608EDB (CRC kernel 0)
– CRC32C Castagnoli: 0xD419CC15 (CRC kernel 1)
The SAK-TC1793N-512F270EF has the following features:
•
•
•
High-performance 32-bit super-scalar TriCore V1.6 CPU with 6-stage pipeline
– Superior real-time performance
– Strong bit handling
– Fully integrated DSP capabilities
– Multiply-accumulate unit able to sustain 2 MAC operations per cycle
– Fully pipelined Floating point unit (FPU)
– 270 MHz operation at full temperature range
32-bit Peripheral Control Processor with single cycle instruction (PCP2)
– 16 Kbyte Parameter Memory (PRAM)
– 32 Kbyte Code Memory (CMEM)
– 200 MHz operation at full temperature range
Multiple on-chip memories
– 4 Mbyte Program Flash Memory (PFLASH) with ECC
– 192 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation
– 2 x 8 Kbyte Key Flash
Data Sheet
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V 1.2, 2014-05
TC1793
Summary of Features
•
•
•
•
•
•
•
– 128 Kbyte Data Scratch-Pad RAM (DSPR)
– 16 Kbyte Instruction Cache (ICACHE)
– 32 Kbyte Instruction Scratch-Pad RAM (PSPR)
– 16 Kbyte Data Cache (DACHE)
– 128 Kbyte Memory (SRAM)
– 16 Kbyte BootROM (BROM)
16-Channel DMA Controller
8-Channel Safe DMA (SDMA) Controller
Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels
serviced by CPU or PCP2
High performing on-chip bus structure
– 64-bit Cross Bar Interconnect between CPU, Flash and Data Memory
– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
– One bus bridge (SFI Bridge)
Versatile On-chip Peripheral Units
– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,
parity, framing and overrun error detection
– Four High-Speed Synchronous Serial Channels (SSC) with programmable data
length and shift direction
– Four SSC Guardian (SSCG) modules, one for each SSC
– Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external
power devices
– Two High-Speed Micro Link interfaces (MLI) for serial inter-processor
communication
– One External Bus Interface (EBU) supporting different memories: asynchronous
memories e.g. SRAM, peripheral devices; synchronous devices e.g. burst NOR
flash, PSRAM; and DDR NOR flash e.g. LPDDR-NVM (Jedec 42.2), ONFI 2.0
(limited frequency at 1.8 V I/O supply)
– One MultiCAN Module with 4 CAN nodes and 128 free assignable message
objects for high efficiency data handling via FIFO buffering and gateway data
transfer (one CAN node supports TTCAN functionality)
– Two General Purpose Timer Array Modules (GPTA) with additional Local Timer
Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer
functionality to realize autonomous and complex Input/Output management
– Two Capture / Compare 6 modules
– Two General Purpose 12 Timer Units (GPT120 and GPT121)
44 analog input lines for ADC
– 4 independent kernels (ADC0, ADC1, and ADC2)
– Analog supply voltage range from 3.3 V to 5 V (single supply)
4 different FADC input channels
– channels with impedance control and overlaid with ADC1 inputs
– Extreme fast conversion, 21 cycles of fFADC clock
Data Sheet
5
V 1.2, 2014-05
TC1793
Summary of Features
•
•
•
•
•
•
•
•
– 10-bit A/D conversion (higher resolution can be achieved by averaging of
consecutive conversions in digital data reduction filter)
8 digital input lines for SENT
– communication according to the SENT specification J2716 FEB2008
221 digital general purpose I/O lines (GPIO)
Digital I/O ports with 3.3 V capability
On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Buses)
Dedicated Emulation Device chip available (TC1793ED)
– multi-core debugging, real time tracing, and calibration
– four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface
Power Management System
Clock Generation Unit with PLL and PLL_ERAY
Flexible CRC Engine (FCE)
– IEEE 802.3 CRC32 ethernet polynomial: 0x82608EDB (CRC kernel 0)
– CRC32C Castagnoli: 0xD419CC15 (CRC kernel 1)
The SAK-TC1793S-512F270EF has the following features:
•
•
•
•
•
•
•
High-performance 32-bit super-scalar TriCore V1.6 CPU with 6-stage pipeline
– Superior real-time performance
– Strong bit handling
– Fully integrated DSP capabilities
– Multiply-accumulate unit able to sustain 2 MAC operations per cycle
– Fully pipelined Floating point unit (FPU)
– 270 MHz operation at full temperature range
32-bit Peripheral Control Processor with single cycle instruction (PCP2)
– 16 Kbyte Parameter Memory (PRAM)
– 32 Kbyte Code Memory (CMEM)
– 200 MHz operation at full temperature range
Multiple on-chip memories
– 4 Mbyte Program Flash Memory (PFLASH) with ECC
– 192 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation
– 2 x 8 Kbyte Key Flash
– 128 Kbyte Data Scratch-Pad RAM (DSPR)
– 16 Kbyte Instruction Cache (ICACHE)
– 32 Kbyte Instruction Scratch-Pad RAM (PSPR)
– 16 Kbyte Data Cache (DACHE)
– 128 Kbyte Memory (SRAM)
– 16 Kbyte BootROM (BROM)
16-Channel DMA Controller
8-Channel Safe DMA (SDMA) Controller
Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels
serviced by CPU or PCP2
High performing on-chip bus structure
Data Sheet
6
V 1.2, 2014-05
TC1793
Summary of Features
•
•
•
•
•
•
•
•
•
– 64-bit Cross Bar Interconnect between CPU, Flash and Data Memory
– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
– One bus bridge (SFI Bridge)
Versatile On-chip Peripheral Units
– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,
parity, framing and overrun error detection
– Four High-Speed Synchronous Serial Channels (SSC) with programmable data
length and shift direction
– Four SSC Guardian (SSCG) modules, one for each SSC
– Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external
power devices
– Two High-Speed Micro Link interfaces (MLI) for serial inter-processor
communication
– One External Bus Interface (EBU) supporting different memories: asynchronous
memories e.g. SRAM, peripheral devices; synchronous devices e.g. burst NOR
flash, PSRAM; and DDR NOR flash e.g. LPDDR-NVM (Jedec 42.2), ONFI 2.0
(limited frequency at 1.8 V I/O supply)
– One MultiCAN Module with 4 CAN nodes and 128 free assignable message
objects for high efficiency data handling via FIFO buffering and gateway data
transfer (one CAN node supports TTCAN functionality)
– One FlexRayTM module with 2 channels (E-Ray).
– Two General Purpose Timer Array Modules (GPTA) with additional Local Timer
Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer
functionality to realize autonomous and complex Input/Output management
– Two Capture / Compare 6 modules
– Two General Purpose 12 Timer Units (GPT120 and GPT121)
44 analog input lines for ADC
– 4 independent kernels (ADC0, ADC1, and ADC2)
– Analog supply voltage range from 3.3 V to 5 V (single supply)
4 different FADC input channels
– channels with impedance control and overlaid with ADC1 inputs
– Extreme fast conversion, 21 cycles of fFADC clock
– 10-bit A/D conversion (higher resolution can be achieved by averaging of
consecutive conversions in digital data reduction filter)
8 digital input lines for SENT
– communication according to the SENT specification J2716 FEB2008
221 digital general purpose I/O lines (GPIO)
Digital I/O ports with 3.3 V capability
On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Buses)
Dedicated Emulation Device chip available (TC1793ED)
– multi-core debugging, real time tracing, and calibration
– four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface
Power Management System
Data Sheet
7
V 1.2, 2014-05
TC1793
Summary of Features
•
•
•
Clock Generation Unit with PLL and PLL_ERAY
Flexible CRC Engine (FCE)
– IEEE 802.3 CRC32 ethernet polynomial: 0x82608EDB (CRC kernel 0)
– CRC32C Castagnoli: 0xD419CC15 (CRC kernel 1)
Secure Hardware Extension (SHE)
– For further information please contact your Infineon representative
Data Sheet
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TC1793
Summary of Features
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies:
•
•
The derivative itself, i.e. its function set, the temperature range, and the supply
voltage
The package and the type of delivery.
For the available ordering codes for the TC1793 please refer to the “Product Catalog
Microcontrollers”, which summarizes all available microcontroller variants.
This document describes the derivatives of the device.The Table 1 enumerates these
derivatives and summarizes the differences.
Table 1
TC1793 Derivative Synopsis
Derivative
Ambient Temperature Range
SAK-TC1793F-512F270EF
TA = -40oC to +125oC
SAK-TC1793F-512F200EF
TA = -40oC to +125oC
SAK-TC1793F-512F200EB
TA = -40oC to +125oC
SAK-TC1793N-512F270EF
TA = -40oC to +125oC
SAK-TC1793S-512F270EF
TA = -40oC to +125oC
Data Sheet
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System Overview of the TC1793
2
System Overview of the TC1793
The TC1793 combines three powerful technologies within one silicon die, achieving new
levels of power, speed, and economy for embedded applications:
•
•
•
Reduced Instruction Set Computing (RISC) processor architecture
Digital Signal Processing (DSP) operations and addressing modes
On-chip memories and peripherals
DSP operations and addressing modes provide the computational power necessary to
efficiently analyze complex real-world signals. The RISC load/store architecture
provides high computational bandwidth with low system cost. On-chip memory and
peripherals are designed to support even the most demanding high-bandwidth real-time
embedded control-systems tasks.
Additional high-level features of the TC1793 include:
•
•
•
•
•
•
•
•
•
Efficient memory organization: instruction and data scratch memories, caches
Serial communication interfaces – flexible synchronous and asynchronous modes
Peripheral Control Processor – standalone data operations and interrupt servicing
DMA Controller – DMA operations and interrupt servicing
General-purpose timers
High-performance on-chip buses
On-chip debugging and emulation facilities
Flexible interconnections to external components
Flexible power-management
The TC1793 is a high-performance microcontroller with TriCore CPU, program and data
memories, buses, bus arbitration, an interrupt controller, a peripheral control processor
and a DMA controller and several on-chip peripherals. The TC1793 is designed to meet
the needs of the most demanding embedded control systems applications where the
competing issues of price/performance, real-time responsiveness, computational power,
data bandwidth, and power consumption are key design elements.
The TC1793 offers several versatile on-chip peripheral units such as serial controllers,
timer units, and Analog-to-Digital converters. Within the TC1793, all these peripheral
units are connected to the TriCore CPU/system via the Flexible Peripheral Interconnect
(FPI) Bus and the Cross Bar Interconnect (SRI). Several I/O lines on the TC1793 ports
are reserved for these peripheral units to communicate with the external world.
Data Sheet
10
V 1.2, 2014-05
TC1793
System Overview of the TC1793Block Diagram
2.1
Block Diagram
Figure 1 shows the block diagram of the SAK-TC1793F-512F270EF / SAK-TC1793F512F200EF / SAK-TC1793F-512F200EB.
FPU
PMI
DMI
LMU
TriCore
CPU
32 KB PSPR
16 KB ICACHE
128LDRAM
KB DSPR
16 KB DCACHE
DCACHE
128 KB
SRAM
M/S
S
M/S
EBU
Cross Bar Interconnect (SRI)
S
XBAR
S
S
PMU0
PMU1
M
M/S
2 MB PFlash
192 KB DFlash
16 KB BROM
KeyFlash
16 channels
(MemCheck)
(SFI)
2 MB PFlash
M/S
Interrupt
System
SSCG
PCP2
M /S
4
Core
4
Interrupts
ASC
SSC
E-Ray
2
SBCU
BMU
Ports
5V (3.3V supported as well)
Ext. ADC Supply
External
Request Unit
CCU6
(2xCCU6)
SENT
(8 channels )
FCE
2
GPT120
GPTA 0
GPTA1
LTCA2
SDMA
8 channels
32 KB CMEM
(2 Channels)
(4 Nodes, 128 MO)
MLI
STM
SSC Guardian
MultiCAN
Interface/JTAG
2
M/S
16 KB PRAM
2
OCDS L1 Debug
DMA
Bridge
Abbreviations:
ICACHE: Instruction Cache
DCACHE Data Cache
PSPR:
Program Scratch-Pad RAM
DSPR:
Data Scratch-Padl Data RAM
BROM:
Boot ROM
PFlash:
Program Flash
DFlash:
Data Flash
PRAM:
Parameter RAM in PCP
CMEM:
Code RAM in PCP
XBAR:
SRI Cross Bar (XBar_SRI)
:
On Chip Bus Slave Interface
S
On Chip Bus Master Interface
M :
2
ADC0
ADC1
(5V max)
44
ADC2
SCU
MSC
FM-PLL
(LVDS)
PLL E-RAY
(3.3V max)
FADC
8
System Peripheral Bus (SPB)
3.3V
Ext. FADC Supply
TC1793
Figure 1
Data Sheet
Block Diagram
11
V 1.2, 2014-05
TC1793
System Overview of the TC1793Block Diagram
Figure 2 shows the block diagram of the SAK-TC1793N-512F270EF.
FPU
PMI
DMI
LMU
TriCore
CPU
32 KB PSPR
16 KB ICACHE
128LDRAM
KB DSPR
16 KB DCACHE
DCACHE
128 KB
SRAM
M/S
S
M/S
EBU
Cross Bar Interconnect (SRI)
S
XBAR
S
S
PMU0
PMU1
M
M/S
2 MB PFlash
192 KB DFlash
16 KB BROM
KeyFlash
16 channels
(MemCheck)
(SFI)
2 MB PFlash
M/S
Interrupt
System
4
SSCG
M /S
PCP2
Core
4
Interrupts
ASC
SSC
Interface/JTAG
2
MLI
M/S
16 KB PRAM
2
OCDS L1 Debug
DMA
Bridge
Abbreviations:
ICACHE: Instruction Cache
DCACHE Data Cache
PSPR:
Program Scratch-Pad RAM
DSPR:
Data Scratch-Padl Data RAM
BROM:
Boot ROM
PFlash:
Program Flash
DFlash:
Data Flash
PRAM:
Parameter RAM in PCP
CMEM:
Code RAM in PCP
XBAR:
SRI Cross Bar (XBar_SRI)
On Chip Bus Slave Interface
S :
On Chip Bus Master Interface
M :
SDMA
8 channels
STM
SSC Guardian
SBCU
BMU
Ports
5V (3.3V supported as well)
Ext. ADC Supply
32 KB CMEM
MultiCAN
(4 Nodes, 128 MO)
2
(2xCCU6)
SENT
(8 channels )
External
Request Unit
CCU6
FCE
2
GPT120
GPTA0
GPTA1
LTCA2
2
ADC0
ADC1
(5V max)
44
ADC2
SCU
MSC
FM-PLL
(LVDS)
PLL E-RAY
(3.3V max)
FADC
8
System Peripheral Bus (SPB)
3.3V
Ext. FADC Supply
TC1793
Figure 2
Data Sheet
Block Diagram
12
V 1.2, 2014-05
TC1793
System Overview of the TC1793Block Diagram
Figure 3 shows the block diagram of the SAK-TC1793S-512F270EF.
FPU
PMI
DMI
LMU
TriCore
CPU
32 KB PSPR
16 KB ICACHE
128LDRAM
KB DSPR
16 KB DCACHE
DCACHE
128 KB
SRAM
M/S
S
M/S
EBU
Cross Bar Interconnect (SRI)
S
XBAR
S
S
PMU0
PMU1
M
M/S
2 MB PFlash
192 KB DFlash
16 KB BROM
KeyFlash
16 channels
(MemCheck)
(SFI)
2 MB PFlash
M/S
4
SSCG
M /S
PCP2
Core
4
Interrupts
ASC
SSC
SSC Guardian
MultiCAN
2
Interrupt
System
8 channels
STM
SHE
SBCU
BMU
Ports
5V (3.3V supported as well)
Ext. ADC Supply
External
Request Unit
CCU6
(2xCCU6)
SENT
(8 channels )
FCE
2
GPT120
GPTA0
GPTA1
LTCA2
MLI
SDMA
32 KB CMEM
E-Ray
(2 Channels)
(4 Nodes, 128 MO)
Interface/JTAG
2
M/S
16 KB PRAM
2
OCDS L 1 Debug
DMA
Bridge
Abbreviations:
ICACHE: Instruction Cache
DCACHE Data Cache
PSPR:
Program Scratch-Pad RAM
DSPR:
Data Scratch-Padl Data RAM
BROM:
Boot ROM
PFlash:
Program Flash
DFlash:
Data Flash
PRAM:
Parameter RAM in PCP
CMEM:
Code RAM in PCP
XBAR:
SRI Cross Bar (XBar_SRI)
S
:
On Chip Bus Slave Interface
M
:
On Chip Bus Master Interface
2
ADC0
ADC1
(5V max)
44
ADC2
SCU
MSC
FM-PLL
(LVDS)
PLL E-RAY
(3.3V max)
FADC
8
System Peripheral Bus (SPB)
3.3V
Ext. FADC Supply
TC1793
Figure 3
Data Sheet
Block Diagram
13
V 1.2, 2014-05
TC1793
Pinning
3
Pinning
Figure 4 is showing the TC1793 Logic Symbol.
Alternate Functions :
PORST
General Control
16
TESTMODE
ESR0
16
ESR1
14
TRST
16
TCK / DAP0
OCDS /
JTAG Control
16
TDI / BRKIN/
BRKOUT
16
TDO /BRKOUT/
DAP2 / BRKIN
12
TMS / DAP1
8
XTAL1
8
XTAL2
Oscillator
VD D OSC
15
VD D OSC3
6
VSSOSC /
VSS
TC1793
16
VD D PF
8
VD D PF3 C3
Digital Circuitry
Power Supply
VD D EBU
VD D P
VD D
VD D FL3
VSS
VD D SB
9
16
11
16
13
16
3
79
4
16
(ED only, N.C. in PD)
VSSAF
FADC Analog
Power Supply
VSSMF
VFAGN D
VFAR EF
VD D MF
VD D AF
N.C.
3
2
9
Port 1
GPTA / HWCFG / E-RAY1)/
GPT12
GPTA / MLI 0 / ERU / SSC1 /
SSC3 / CCU6 / GPT12
Port 2
GPTA / SSC0 / SSC1
Port 3
GPTA / CCU6 / GPT12
Port 4
GPTA / SSC2 / CCU6 / GPT12
Port 0
Port 5
Port 6
ASC0 / ASC1 / MSC0 / MSC1 /
LVDS / MLI0 / CCU6 / GPT12
ASC0 / ASC1 / SSC1 / CAN /
E-RAY1)/ CCU6 / GPT12
Port 7
ERU / ADC-Mux / SSC3
Port 8
Port 9
MLI 1 / GPTA / SENT /
CCU6 / GPT12
MSC0 / MSC1 / GPTA /
SENT / CCU6 / GPT12
Port 10
SSC0
Port 11
EBU
Port 12
EBU
Port 13
GPTA / EBU
Port 14
GPTA / EBU / CCU6 / GPT12
Port 15
EBU
Port 16
EBU
Port 17
SENT
(Overlay with Analog Inputs )
AN[43:0]
ADC / FADC
Analog Inputs
VAR EFx
VAGN D x
VD D M
VSSM
ADC0 / ADC1 / ADC2
Analog Power Supply
1) Only available for SAK-TC 1793F-512F270EF, SAKTC1793F- 512F270EB, SAK-TC1793F- 512F200EF,
and SAK-TC 1793F- 512F200EB
TC1793_LogSym_416
Figure 4
Data Sheet
TC1793 Logic Symbol
14
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
3.1
TC1793 Pin Configuration
This chapter shows the pin configuration of the TC1793 package PG-BGA- 416.
1
A
N.C.
2
3
4
5
6
P2.9 P2.13 P2.15 P0.14 P0.5
7
8
P0.2
P0.1
B
P2.6
P2.7 P2.10 P2.14 P0.9
C
P2.5
P2.8 P2.11 P2.12 P0.12 P0.10 P0.8
P2.4
P2.2 P0.15 P0.13 P0.11 VDDP
D
E
F
G
H
J
K
L
M
N
P6.12 P6.11 P6.6
11
12
13
14
P3.1
P5.1
P5.2
25
26
P5.7 P5.12 P5.15 VDDFL3 P9.0
15
16
17
18
19
P9.3
20
P9.9 ESR1 ESR0 N.C.
21
22
23
24
VDDP
VSS
A
VSS
VDD
B
P3.3
P3.0
P5.0
P5.3
P5.6 P5.13 P5.14 VDDFL3 P9.1
PO TEST V
P9.2 P9.10
DDP
RST MODE
P0.7
P3.7 P3.10 P3.9
P3.4
P3.2
P5.5
P5.4
P5.9 P5.10 P5.11 P9.6
P9.8 P9.11 N.C.
VDDP
VSS
VDD
P9.13
C
VSS
VDD
P3.8 P3.12 P3.13 P3.11 VDDP
VSS
VDD
P9.7 P9.12 VDDP
VSS
VDD
TDO P9.14
D
VDD
TCK
TDI
P0.3 P3.15 P3.6
P5.8
P9.4
P9.5
P6.9
VDD
E
OSC3
VSS
VDD
OSC
OSC
F
P6.8
P6.15 P6.13 P6.7
P6.5
VDDPF VDDPF3 XTAL XTAL
G
P8.1
P8.0 VDDFL3
VDD
VDDEBU VDDEBU VDDEBU VDDEBU
H
P8.3
P8.2
VSS
P11.3 P12.6 P12.7 P11.0
J
P8.6
VDDP
P11.7 P11.4 P11.1 P11.2
K
P11.
P11.5 P11.6
11
L
VDDEBU P11. P11.9 P11.8
M
P6.14 P6.10 P6.4
P8.4
P8.7
P8.5
2
VSS
P1.15 P1.14 P1.13 P1.11
P1.10 P1.9
P1.3
P1.2
R
VDD
SBRAM
U
P0.4
10
TRST TMS
P
T
P2.3
P0.6
9
P0.0 P3.14 P3.5
P7.6
P1.7
P1.1
P7.1
P7.5
AN23 P7.7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
1
P1.5
VSS
VSS
VSS
P1.4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P11.
13
P11.
14
P11.
12
N
P1.0 P1.12
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
P12.1 P12.2 P12.0
P
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P12.3 P12.5 P12.4
R
VSS
VSS
VSS
VSS
VSS
VSS
VDDEBU P13.1 P13.3 P13.0
T
VSS
VSS
VSS
VSS
VSS
VSS
P13.6 P13.9 P13.5 P13.2
U
P13.
P13.8 P13.4
13
V
P13.
P14.0
P13.7
12
W
P1.8
P1.6
P7.0
VDD
P7.4
VSS
P7.3
VSS
VSS
P7.2
VSS
VSS
VSS
VSS
10
P11.
15
V
AN22 AN21 AN19 AN16
VDD
W
AN20 AN17 AN13 VDDM
VSS
Y
AN18 AN14 AN10 VSSM
VDDEBU P14.2 P13.
AN15 AN11
P13.
P14.3 P14.6 P14.1
11
AA
VDD
P13.
P14.5 P14.4
15
AB
N.C. VDDEBU VSS
P14.
P14.9 P14.7
12
AC
P14.
15
P14.
P14.8
11
AD
AA
AB
AC
AN12
AN9
AN5
AN3
14
AN2
AN7
VSS
AN8
AD
AN6
AN1 AN34 AN40 AN35 VAREF1 AN27 AN25 VAREF2 P4.0
P4.2
P4.5 P4.11 P4.15 P10.2 VDDP P15.5 P16.1 P15.3 P15.2 P15.1 P16.2 N.C.
AE
AN0 AN33 AN36 AN41 VAREF0 AN28 AN30 VFAGND VDDMF P4.1
P4.3
P4.7 P4.13 P10.4 P10.0 VDDP P15.4 P15.7 P16.3
AF
N.C. AN37 AN39 AN43 VAGND0 AN29 AN31 VFAREF VSSMF P4.6
P4.9 P4.10 P4.14 P10.3 P10.1 VDDP P16.0 P15.6
1
2
3
4
5
6
7
8
9
10
VDD
P4.4
11
12
P4.8 P4.12 P10.5 VDDP
VSS VDDEBU VSS
AN4 AN32 AN38 AN42 VAGND1 AN26 AN24 VDDAF
13
14
15
16
17
VDD
P13.
10
Y
P15.
P15.0 N.C.
11
N.C.
P14.
14
P14.
13
P14.
10
AE
P15.
P15.
P15.8 P15.9
12
10
P15.
13
P15.
14
P15.
15
N.C.
AF
23
24
25
26
18
19
20
21
22
mca05584_97.vsd
Figure 5
Data Sheet
TC1793 Pinning for PG-BGA- 416 Package
15
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Table 2
Pin
Pin Definitions and Functions
Symbol
Ctrl.
Type Function
P0.0
I/O
HWCFG0
I
A1+/
PU
OUT56
O1
OUT56 Line of GPTA0
OUT56
O2
OUT56 Line of GPTA1
OUT80
O3
OUT80 Line of LTCA2
P0.1
I/O
HWCFG1
I
OUT57
O1
OUT57 Line of GPTA0
OUT57
O2
OUT57 Line of GPTA1
OUT81
O3
OUT81 Line of LTCA2
P0.2
I/O
HWCFG2
I
OUT58
O1
OUT58 Line of GPTA0
OUT58
O2
OUT58 Line of GPTA1
OUT82
O3
OUT82 Line of LTCA2
P0.3
I/O
HWCFG3
I
OUT59
O1
OUT59 Line of GPTA0
OUT59
O2
OUT59 Line of GPTA1
OUT83
O3
OUT83 Line of LTCA2
Port 0
A9
A8
A7
B8
Data Sheet
A1/
PU
A2/
PU
A1/
PU
Port 0 General Purpose I/O Line 0
Hardware Configuration Input 0
Port 0 General Purpose I/O Line 1
Hardware Configuration Input 1
Port 0 General Purpose I/O Line 2
Hardware Configuration Input 2
Port 0 General Purpose I/O Line 3
Hardware Configuration Input 3
16
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
B7
P0.4
I/O
HWCFG4
I
A1/
PU
OUT60
O1
OUT60 Line of GPTA0
OUT60
O2
OUT60 Line of GPTA1
EVTO0
O3
MCDS Output Event 01)
P0.5
I/O
HWCFG5
I
OUT61
O1
OUT61 Line of GPTA0
OUT61
O2
OUT61 Line of GPTA1
EVTO1
O3
MCDS Output Event 11)
P0.6
I/O
HWCFG6
I
OUT62
O1
OUT62 Line of GPTA0
OUT62
O2
OUT62 Line of GPTA1
EVTO2
O3
MCDS Output Event 21)
P0.7
I/O
HWCFG7
I
OUT63
O1
OUT63 Line of GPTA0
OUT63
O2
OUT63 Line of GPTA1
EVTO3
O3
MCDS Output Event 31)
P0.8
I/O
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A6
B6
C8
C7
Data Sheet
A1/
PU
A2/
PU
A1/
PU
A1/
PU
Port 0 General Purpose I/O Line 4
Hardware Configuration Input 4
Port 0 General Purpose I/O Line 5
Hardware Configuration Input 5
Port 0 General Purpose I/O Line 6
Hardware Configuration Input 6
Port 0 General Purpose I/O Line 7
Hardware Configuration Input 7
Port 0 General Purpose I/O Line 8
-
17
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
B5
P0.9
I/O
RXDA0
I
A1/
PU
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
P0.10
I/O
TXENA
O1
Reserved
O2
-
Reserved
O3
-
P0.11
I/O
T5INB
I
T5INA
I
GPT121
TXENB
O1
E-Ray Channel B transmit Data Output
enable 2)
Reserved
O2
-
Reserved
O3
-
P0.12
I/O
T5EUDA
I
T5EUDB
I
GPT121
TXDB
O1
E-Ray Channel B transmit Data Output 2)
Reserved
O2
-
Reserved
O3
-
C6
D6
C5
Data Sheet
A2/
PU
A2/
PU
A2/
PU
Port 0 General Purpose I/O Line 9
E-Ray Channel A Receive Data Input 0 2)
Port 0 General Purpose I/O Line 10
E-Ray Channel A transmit Data Output
enable 2)
Port 0 General Purpose I/O Line 11
GPT120
Port 0 General Purpose I/O Line 12
GPT120
18
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
D5
P0.13
I/O
RXDB0
I
A1/
PU
T5EUDB
I
GPT120
T5EUDA
I
GPT121
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
P0.14
I/O
T6INA
I
T6INB
I
GPT121
TXDA
O1
E-Ray Channel A transmit Data Output 2)
Reserved
O2
-
Reserved
O3
-
P0.15
I/O
Reserved
O1
Reserved
O2
-
Reserved
O3
-
P1.0
I/O
REQ0
I
EXTCLK1
O1
External Clock Output 1
Reserved
O2
-
Reserved
O3
-
A5
D4
A2/
PU
A1/
PU
Port 0 General Purpose I/O Line 13
E-Ray Channel B Receive Data Input 0 2)
Port 0 General Purpose I/O Line 14
GPT120
Port 0 General Purpose I/O Line 15
-
Port 1
P3
Data Sheet
A2/
PU
Port 1 General Purpose I/O Line 0
External trigger Input 0
19
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
P2
P1.1
I/O
REQ1
I
A1/
PU
CC60INA
I
CCU60
CC60INB
I
CCU61
CC60
O1
CCU60
Reserved
O2
-
Reserved
O3
-
P1.2
I/O
REQ2
I
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
P1.3
I/O
REQ3
I
TREADY0B
I
MLI0 transmit Channel ready Input B
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
P1.4
I/O
TCLK0
O1
Reserved
O2
-
Reserved
O3
-
P1
N1
N4
Data Sheet
A1/
PU
A1/
PU
A2/
PU
Port 1 General Purpose I/O Line 1
External trigger Input 1
Port 1 General Purpose I/O Line 2
External trigger Input 2
Port 1 General Purpose I/O Line 3
External trigger Input 3
Port 1 General Purpose I/O Line 4
MLI0 transmit Channel Clock Output
20
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
M4
P1.5
I/O
TREADY0A
I
A1/
PU
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
P1.6
I/O
TVALID0A
O1
SLSO10
O2
SSC1 Slave Select Output Line 10
COUT60
O3
CCU60
P1.7
I/O
CC61INB
I
CC61INA
I
CCU61
TData0
O1
MLI0 transmit Channel Data Output
CC61
O2
CCU61
T3OUT
O3
GPT120
P1.8
I/O
RCLK0A
I
OUT64
O1
OUT64 Line of GPTA0
OUT64
O2
OUT64 Line of GPTA1
OUT88
O3
OUT88 Line of LTCA2
P1.9
I/O
RREADY0A
O1
SLSO11
O2
SSC1 Slave Select Output Line 11
OUT65
O3
OUT65 Line of GPTA0
N3
N2
M3
M2
Data Sheet
A2/
PU
A2/
PU
A1/
PU
A2/
PU
Port 1 General Purpose I/O Line 35
MLI0 transmit Channel ready Input A
Port 1 General Purpose I/O Line 6
MLI0 transmit Channel valid Output A
Port 1 General Purpose I/O Line 7
CCU60
Port 1 General Purpose I/O Line 8
MLI0 Receive Channel Clock Input A
Port 1 General Purpose I/O Line 9
MLI0 Receive Channel ready Output A
21
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
M1
P1.10
I/O
RVALID0A
I
A1/
PU
OUT66
O1
OUT66 Line of GPTA0
OUT66
O2
OUT66 Line of GPTA1
OUT90
O3
OUT90 Line of LTCA2
P1.11
I/O
RDATA0A
I
SLSI3
I
SSC3 Input
OUT67
O1
OUT67 Line of GPTA0
OUT67
O2
OUT67 Line of GPTA1
OUT91
O3
OUT91 Line of LTCA2
P1.12
I/O
EXTCLK0
O1
OUT68
O2
OUT68 Line of GPTA0
OUT68
O3
OUT68 Line of GPTA1
P1.13
I/O
RCLK0B
I
OUT69
O1
OUT69 Line of GPTA0
OUT69
O2
OUT69 Line of GPTA1
OUT93
O3
OUT93 Line of LTCA2
P1.14
I/O
RVALID0B
I
OUT70
O1
OUT70 Line of GPTA0
OUT70
O2
OUT70 Line of GPTA1
OUT94
O3
OUT94 Line of LTCA2
L4
P4
L3
L2
Data Sheet
A1/
PU
A2/
PU
A1/
PU
A1/
PU
Port 1 General Purpose I/O Line 10
MLI0 Receive Channel valid Input A
Port 1 General Purpose I/O Line 11
MLI0 Receive Channel Data Input A
Port 1 General Purpose I/O Line 12
External Clock Output 0
Port 1 General Purpose I/O Line 13
MLI0 Receive Channel Clock Input B
Port 1 General Purpose I/O Line 14
MLI0 Receive Channel valid Input B
22
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
L1
P1.15
I/O
RDATA0B
I
A1/
PU
OUT71
O1
OUT71 Line of GPTA0
OUT71
O2
OUT71 Line of GPTA1
OUT95
O3
OUT95 Line of LTCA2
P2.2
I/O
SLSO02
O1
SLSO12
O2
SSC1 Slave Select Output Line 12
SLSO02
AND
SLSO12
O3
SSC0 & SSC1 Slave Select Output Line 2
AND Slave Select Output Line 12
P2.3
I/O
SLSO03
O1
SLSO13
O2
SSC1 Slave Select Output Line 13
SLSO03
AND
SLSO13
O3
SSC0 & SSC1 Slave Select Output Line 3
AND Slave Select Output Line 13
P2.4
I/O
SLSO04
O1
SLSO14
O2
SSC1 Slave Select Output Line 14
SLSO04
AND
SLSO14
O3
SSC0 & SSC1 Slave Select Output Line 4
AND Slave Select Output Line 14
Port 1 General Purpose I/O Line 15
MLI0 Receive Channel Data Input B
Port 2
D3
D2
D1
Data Sheet
A1+/
PU
A1+/
PU
A1+/
PU
Port 2 General Purpose I/O Line 2
SSC0 Slave Select Output Line 2
Port 2 General Purpose I/O Line 3
SSC0 Slave Select Output Line 3
Port 2 General Purpose I/O Line 4
SSC0 Slave Select Output Line 4
23
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
C1
P2.5
I/O
SLSO05
O1
A1+/
PU
SLSO15
O2
SSC1 Slave Select Output Line 15
SLSO05
AND
SLSO15
O3
SSC0 & SSC1 Slave Select Output Line 5
AND Slave Select Output Line 15
P2.6
I/O
SLSO06
O1
SLSO16
O2
SSC1 Slave Select Output Line 16
SLSO06
AND
SLSO16
O3
SSC0 & SSC1 Slave Select Output Line 6
AND Slave Select Output Line 16
P2.7
I/O
SLSO07
O1
SLSO17
O2
SSC1 Slave Select Output Line 17
SLSO07
AND
SLSO17
O3
SSC0 & SSC1 Slave Select Output Line
7AND Slave Select Output Line 17
B1
B2
Data Sheet
A1+/
PU
A1+/
PU
Port 2 General Purpose I/O Line 5
SSC0 Slave Select Output Line 5
Port 2 General Purpose I/O Line 6
SSC0 Slave Select Output Line 6
Port 2 General Purpose I/O Line 7
SSC0 Slave Select Output Line 7
24
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
C2
P2.8
I/O
IN0
I
A1/
PU
IN0
I
IN0 Line of GPTA1
IN0
I
IN0 Line of LTCA2
CCPOS0A
I
CCU62
T12HRB
I
CCU63
T3INB
I
GPT120
T3INA
I
GPT121
OUT0
O1
OUT0 Line of GPTA0
OUT0
O2
OUT0 Line of GPTA1
OUT0
O3
OUT0 Line of LTCA2
P2.9
I/O
IN1
I
IN1
I
IN1 Line of GPTA1
IN1
I
IN1 Line of LTCA2
OUT1
O1
OUT1 Line of GPTA0
OUT1
O2
OUT1 Line of GPTA1
OUT1
O3
OUT1 Line of LTCA2
A2
Data Sheet
A1/
PU
Port 2 General Purpose I/O Line 8
IN0 Line of GPTA0
Port 2 General Purpose I/O Line 9
IN1 Line of GPTA0
25
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
B3
P2.10
I/O
IN2
I
A1/
PU
IN2
I
IN2 Line of GPTA1
IN2
I
IN2 Line of LTCA2
T12HRE
I
CCU60
CC61INC
I
CCU60
CTRAPA
I
CCU61
CTRAPB
I
CCU63
CC60INC
I
CCU61
OUT2
O1
OUT2 Line of GPTA0
OUT2
O2
OUT2 Line of GPTA1
OUT2
O3
OUT2 Line of LTCA2
P2.11
I/O
IN3
I
IN3
I
IN3 Line of GPTA1
IN3
I
IN3 Line of LTCA2
OUT3
O1
OUT3 Line of GPTA0
OUT3
O2
OUT3 Line of GPTA1
OUT3
O3
OUT3 Line of LTCA2
C3
Data Sheet
A1/
PU
Port 2 General Purpose I/O Line 10
IN2 Line of GPTA0
Port 2 General Purpose I/O Line 11
IN3 Line of GPTA0
26
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
C4
P2.12
I/O
IN4
I
A1/
PU
IN4
I
IN4 Line of GPTA1
IN4
I
IN4 Line of LTCA2
T12HRB
I
CCU62
CCPOS0A
I
CCU63
T2INB
I
GPT120
T2INA
I
GPT121
OUT4
O1
OUT4 Line of GPTA0
OUT4
O2
OUT4 Line of GPTA1
OUT4
O3
OUT4 Line of LTCA2
P2.13
I/O
IN5
I
IN5
I
IN5 Line of GPTA1
IN5
I
IN5 Line of LTCA2
OUT5
O1
OUT5 Line of GPTA0
OUT5
O2
OUT5 Line of GPTA1
OUT5
O3
OUT5 Line of LTCA2
A3
Data Sheet
A1/
PU
Port 2 General Purpose I/O Line 12
IN4 Line of GPTA0
Port 2 General Purpose I/O Line 13
IN5 Line of GPTA0
27
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
B4
P2.14
I/O
IN6
I
A1/
PU
IN6
I
IN6 Line of GPTA1
IN6
I
IN6 Line of LTCA2
CCPOS0A
I
CCU60
T12HRB
I
CCU61
T3INA
I
GPT120
T3INB
I
GPT121
OUT6
O1
OUT6 Line of GPTA0
OUT6
O2
OUT6 Line of GPTA1
OUT6
O3
OUT6 Line of LTCA2
P2.15
I/O
IN7
I
IN7
I
IN7 Line of GPTA1
IN7
I
IN7 Line of LTCA2
OUT7
O1
OUT7 Line of GPTA0
OUT7
O2
OUT7 Line of GPTA1
OUT7
O3
OUT7 Line of LTCA2
A4
A1/
PU
Port 2 General Purpose I/O Line 14
IN6 Line of GPTA0
Port 2 General Purpose I/O Line 15
IN7 Line of GPTA0
Port 3
Data Sheet
28
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
B12
P3.0
I/O
IN8
I
A1/
PU
IN8
I
IN8 Line of GPTA1
IN8
I
IN8 Line of LTCA2
CTRAPA
I
CCU62
CTRAPB
I
CCU61
CC60INC
I
CCU62
T12HRE
I
CCU63
CC61INC
I
CCU63
T5INA
I
GPT120
T5INB
I
GPT121
OUT8
O1
OUT8 Line of GPTA0
OUT8
O2
OUT8 Line of GPTA1
OUT8
O3
OUT8 Line of LTCA2
P3.1
I/O
IN9
I
IN9
I
IN9 Line of GPTA1
IN9
I
IN9 Line of LTCA2
OUT9
O1
OUT9 Line of GPTA0
OUT9
O2
OUT9 Line of GPTA1
OUT9
O3
OUT9 Line of LTCA2
A12
Data Sheet
A1/
PU
Port 3 General Purpose I/O Line 0
IN8 Line of GPTA0
Port 3 General Purpose I/O Line 1
IN9 Line of GPTA0
29
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
C13
P3.2
I/O
IN10
I
A1/
PU
IN10
I
IN10 Line of GPTA1
IN10
I
IN10 Line of LTCA2
T13HRE
I
CCU63
OUT10
O1
OUT10 Line of GPTA0
OUT10
O2
OUT10 Line of GPTA1
OUT10
O3
OUT10 Line of LTCA2
P3.3
I/O
IN11
I
IN11
I
IN11 Line of GPTA1
IN11
I
IN11 Line of LTCA2
OUT11
O1
OUT11 Line of GPTA0
OUT11
O2
OUT11 Line of GPTA1
OUT11
O3
OUT11 Line of LTCA2
B11
Data Sheet
A1/
PU
Port 3 General Purpose I/O Line 2
IN10 Line of GPTA0
Port 3 General Purpose I/O Line 3
IN11 Line of GPTA0
30
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
C12
P3.4
I/O
IN12
I
A1/
PU
IN12
I
IN12 Line of GPTA1
IN12
I
IN12 Line of LTCA2
T12HRE
I
CCU62
CC61INC
I
CCU62
CTRAPA
I
CCU63
CTRAPB
I
CCU60
CC60INC
I
CCU63
OUT12
O1
OUT12 Line of GPTA0
OUT12
O2
OUT12 Line of GPTA1
OUT12
O3
OUT12 Line of LTCA2
P3.5
I/O
IN13
I
IN13
I
IN13 Line of GPTA1
IN13
I
IN13 Line of LTCA2
OUT13
O1
OUT13 Line of GPTA0
OUT13
O2
OUT13 Line of GPTA1
OUT13
O3
OUT13 Line of LTCA2
A11
Data Sheet
A1/
PU
Port 3 General Purpose I/O Line 4
IN12 Line of GPTA0
Port 3 General Purpose I/O Line 5
IN13 Line of GPTA0
31
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
B10
P3.6
I/O
IN14
I
A1/
PU
IN14
I
IN14 Line of GPTA1
IN14
I
IN14 Line of LTCA2
T13HRE
I
CCU62
T6EUDB
I
GPT120
T6EUDA
I
GPT121
OUT14
O1
OUT14 Line of GPTA0
OUT14
O2
OUT14 Line of GPTA1
OUT14
O3
OUT14 Line of LTCA2
P3.7
I/O
IN15
I
IN15
I
IN15 Line of GPTA1
IN15
I
IN15 Line of LTCA2
OUT15
O1
OUT15 Line of GPTA0
OUT15
O2
OUT15 Line of GPTA1
OUT15
O3
OUT15 Line of LTCA2
P3.8
I/O
IN16
I
IN16
I
IN16 Line of GPTA1
IN16
I
IN16 Line of LTCA2
T13HRE
I
CCU61
OUT16
O1
OUT16 Line of GPTA0
OUT16
O2
OUT16 Line of GPTA1
OUT16
O3
OUT16 Line of LTCA2
C9
D10
Data Sheet
A1/
PU
A1/
PU
Port 3 General Purpose I/O Line 6
IN14 Line of GPTA0
Port 3 General Purpose I/O Line 7
IN15 Line of GPTA0
Port 3 General Purpose I/O Line 8
IN16 Line of GPTA0
32
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
C11
P3.9
I/O
IN17
I
A1/
PU
IN17
I
IN17 Line of GPTA1
IN17
I
IN17 Line of LTCA2
OUT17
O1
OUT17 Line of GPTA0
OUT17
O2
OUT17 Line of GPTA1
OUT17
O3
OUT17 Line of LTCA2
P3.10
I/O
IN18
I
IN18
I
IN18 Line of GPTA1
IN18
I
IN18 Line of LTCA2
CCPOS1A
I
CCU62
T13HRB
I
CCU63
T3EUDB
I
GPT120
T3EUDA
I
GPT121
OUT18
O1
OUT18 Line of GPTA0
OUT18
O2
OUT18 Line of GPTA1
OUT18
O3
OUT18 Line of LTCA2
P3.11
I/O
IN19
I
IN19
I
IN19 Line of GPTA1
IN19
I
IN19 Line of LTCA2
OUT19
O1
OUT19 Line of GPTA0
OUT19
O2
OUT19 Line of GPTA1
OUT19
O3
OUT19 Line of LTCA2
C10
D13
Data Sheet
A1+/
PU
A1/
PU
Port 3 General Purpose I/O Line 9
IN17 Line of GPTA0
Port 3 General Purpose I/O Line 10
IN18 Line of GPTA0
Port 3 General Purpose I/O Line 11
IN19 Line of GPTA0
33
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
D11
P3.12
I/O
IN20
I
A1/
PU
IN20
I
IN20 Line of GPTA1
IN20
I
IN20 Line of LTCA2
CCPOS2A
I
CCU62
T12HRC
I
CCU63
T13HRC
I
CCU63
T4INB
I
GPT120
T4INA
I
GPT121
OUT20
O1
OUT20 Line of GPTA0
OUT20
O2
OUT20 Line of GPTA1
OUT20
O3
OUT20 Line of LTCA2
P3.13
I/O
IN21
I
IN21
I
IN21 Line of GPTA1
IN21
I
IN21 Line of LTCA2
OUT21
O1
OUT21 Line of GPTA0
OUT21
O2
OUT21 Line of GPTA1
OUT21
O3
OUT21 Line of LTCA2
D12
Data Sheet
A1/
PU
Port 3 General Purpose I/O Line 12
IN20 Line of GPTA0
Port 3 General Purpose I/O Line 13
IN21 Line of GPTA0
34
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
A10
P3.14
I/O
IN22
I
A1/
PU
IN22
I
IN22 Line of GPTA1
IN22
I
IN22 Line of LTCA2
T13HRE
I
CCU63
OUT22
O1
OUT22 Line of GPTA0
OUT22
O2
OUT22 Line of GPTA1
OUT22
O3
OUT22 Line of LTCA2
P3.15
I/O
IN23
I
IN23
I
IN23 Line of GPTA1
IN23
I
IN23 Line of LTCA2
OUT23
O1
OUT23 Line of GPTA0
OUT23
O2
OUT23 Line of GPTA1
OUT23
O3
OUT23 Line of LTCA2
P4.0
I/O
IN24
I
IN24
I
IN24 Line of GPTA1
IN24
I
IN24 Line of LTCA2
MRST2A
I
SSC2 Master Receive Input A (Master Mode)
OUT24
O1
OUT24 Line of GPTA0
OUT24
O2
OUT24 Line of GPTA1
MRST2
O3
SSC2 Slave Transmit Output (Slave Mode)
B9
A1/
PU
Port 3 General Purpose I/O Line 14
IN22 Line of GPTA0
Port 3 General Purpose I/O Line 15
IN23 Line of GPTA0
Port 4
AD10
Data Sheet
A1+/
PU
Port 4 General Purpose I/O Line 0
IN24 Line of GPTA0
35
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
AE10
P4.1
I/O
IN25
I
A1+/
PU
IN25
I
IN25 Line of GPTA1
IN25
I
IN25 Line of LTCA2
MTSR2A
I
SSC2 Slave Receive Input A (Slave Mode)
MRSTG2A
I
SSC Guardian 2 Master Receive Input A
(Master Mode)
OUT25
O1
OUT25 Line of GPTA0
OUT25
O2
OUT25 Line of GPTA1
MTSR2
O3
SSC2 Master Transmit Output (Master
Mode)3)
P4.2
I/O
IN26
I
IN26
I
IN26 Line of GPTA1
IN26
I
IN26 Line of LTCA2
SCLK2
I
SSC2 Input
OUT26
O1
OUT26 Line of GPTA0
OUT26
O2
OUT26 Line of GPTA1
SCLK2
O3
SSC2 Output
P4.3
I/O
IN27
I
IN27
I
IN27 Line of GPTA1
IN27
I
IN27 Line of LTCA2
OUT27
O1
OUT27 Line of GPTA0
OUT27
O2
OUT27 Line of GPTA1
SLSO20
O3
SSC2 Output
AD11
AE11
Data Sheet
A1+/
PU
A1+/
PU
Port 4 General Purpose I/O Line 1
IN25 Line of GPTA0
Port 4 General Purpose I/O Line 2
IN26 Line of GPTA0
Port 4 General Purpose I/O Line 3
IN27 Line of GPTA0
36
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
AC12
P4.4
I/O
IN28
I
A1+/
PU
IN28
I
IN28 Line of GPTA1
IN28
I
IN28 Line of LTCA2
OUT28
O1
OUT28 Line of GPTA0
OUT28
O2
OUT28 Line of GPTA1
SLSO21
O3
SSC2 Output
P4.5
I/O
IN29
I
IN29
I
IN29 Line of GPTA1
IN29
I
IN29 Line of LTCA2
OUT29
O1
OUT29 Line of GPTA0
OUT29
O2
OUT29 Line of GPTA1
SLSO22
O3
SSC2 Output
P4.6
I/O
IN30
I
IN30
I
IN30 Line of GPTA1
IN30
I
IN30 Line of LTCA2
OUT30
O1
OUT30 Line of GPTA0
OUT30
O2
OUT30 Line of GPTA1
SLSO23
O3
SSC2 Output
AD12
AF10
Data Sheet
A1+/
PU
A1+/
PU
Port 4 General Purpose I/O Line 4
IN28 Line of GPTA0
Port 4 General Purpose I/O Line 5
IN29 Line of GPTA0
Port 4 General Purpose I/O Line 6
IN30 Line of GPTA0
37
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
AE12
P4.7
I/O
IN31
I
A1+/
PU
IN31
I
IN31 Line of GPTA1
IN31
I
IN31Line of LTCA2
T6INB
I
GPT120
T6INA
I
GPT121
OUT31
O1
OUT31 Line of GPTA0
OUT31
O2
OUT31 Line of GPTA1
SLSO24
O3
SSC2 Output
P4.8
I/O
IN32
I
IN32
I
IN32 Line of GPTA1
CCPOS1A
I
CCU60
T13HRB
I
CCU61
T3EUDA
I
GPT120
T3EUDB
I
GPT121
OUT32
O1
OUT32 Line of GPTA0
OUT32
O2
OUT32 Line of GPTA1
OUT0
O3
OUT0 Line of LTCA2
AC13
Data Sheet
A1/
PU
Port 4 General Purpose I/O Line 7
IN31 Line of GPTA0
Port 4 General Purpose I/O Line 8
IN32 Line of GPTA0
38
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
AB19
P4.9
I/O
IN33
I
A1/
PU
IN33
I
IN33 Line of GPTA1
CCPOS2A
I
CCU60
T12HRC
I
CCU61
T13HRC
I
CCU61
T4INA
I
GPT120
T4INB
I
GPT121
SLSI2
I
SSC2
OUT33
O1
OUT33 Line of GPTA0
OUT33
O2
OUT33 Line of GPTA1
OUT1
O3
OUT1 Line of LTCA2
P4.10
I/O
IN34
I
IN34
I
IN34 Line of GPTA1
T12HRB
I
CCU60
CCPOS0A
I
CCU61
T2INA
I
GPT120
T2INB
I
GPT121
OUT34
O1
OUT34 Line of GPTA0
OUT34
O2
OUT34 Line of GPTA1
OUT2
O3
OUT2 Line of LTCA2
AF12
Data Sheet
A1/
PU
Port 4 General Purpose I/O Line 9
IN33 Line of GPTA0
Port 4 General Purpose I/O Line 10
IN34 Line of GPTA0
39
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
AD13
P4.11
I/O
IN35
I
A1/
PU
IN35
I
IN35 Line of GPTA1
OUT35
O1
OUT35 Line of GPTA0
OUT35
O2
OUT35 Line of GPTA1
OUT3
O3
OUT3 Line of LTCA2
P4.12
I/O
IN36
I
IN36
I
IN36 Line of GPTA1
T13HRB
I
CCU60
CCPOS1A
I
CCU61
T2EUDA
I
GPT120
T2EUDB
I
GPT121
OUT36
O1
OUT36 Line of GPTA0
OUT36
O2
OUT36 Line of GPTA1
OUT4
O3
OUT4 Line of LTCA2
P4.13
I/O
IN37
I
IN37
I
IN37 Line of GPTA1
OUT37
O1
OUT37 Line of GPTA0
OUT37
O2
OUT37 Line of GPTA1
OUT5
O3
OUT5 Line of LTCA2
AC14
AE13
Data Sheet
A1/
PU
A1/
PU
Port 4 General Purpose I/O Line 11
IN35 Line of GPTA0
Port 4 General Purpose I/O Line 12
IN36 Line of GPTA0
Port 4 General Purpose I/O Line 13
IN37 Line of GPTA0
40
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
AF13
P4.14
I/O
IN38
I
A1/
PU
IN38
I
IN38 Line of GPTA1
T12HRC
I
CCU60
T13HRC
I
CCU60
CCPOS2A
I
CCU61
T4EUDA
I
GPT120
T4EUDB
I
GPT121
OUT38
O1
OUT38 Line of GPTA0
OUT38
O2
OUT38 Line of GPTA1
OUT6
O3
OUT6 Line of LTCA2
P4.15
I/O
IN39
I
IN39
I
IN39 Line of GPTA1
OUT39
O1
OUT39 Line of GPTA0
OUT39
O2
OUT39 Line of GPTA1
OUT7
O3
OUT7 Line of LTCA2
P5.0
I/O
RXD0A
I
T6EUDA
I
GPT120
T6EUDB
I
GPT121
RXD0A
O1
ASC0 Receiver Input/Output A
OUT72
O2
OUT72 Line of GPTA0
OUT72
O3
OUT72 Line of GPTA1
AD14
A1/
PU
Port 4 General Purpose I/O Line 14
IN38 Line of GPTA0
Port 4 General Purpose I/O Line 15
IN39 Line of GPTA0
Port 5
B13
Data Sheet
A1+/
PU
Port 5 General Purpose I/O Line 0
ASC0 Receiver Input/Output A
41
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
A13
P5.1
I/O
TXD0
O1
A1+/
PU
OUT73
O2
OUT73 Line of GPTA0
OUT73
O3
OUT73 Line of GPTA1
P5.2
I/O
RXD1A
I
RXD1A
O1
ASC1 Receiver Input/Output A
OUT74
O2
OUT74 Line of GPTA0
OUT74
O3
OUT74 Line of GPTA1
P5.3
I/O
TXD1
O1
OUT75
O2
OUT75 Line of GPTA0
OUT75
O3
OUT75 Line of GPTA1
P5.4
I/O
T13HRB
I
CCPOS1A
I
CCU63
T2EUDB
I
GPT120
T2EUDA
I
GPT121
EN00
O1
MSC0 Device Select Output 0
RREADY0B
O2
MLI0 Receive Channel ready Output B
OUT76
O3
OUT76 Line of GPTA0
A14
B14
C15
Data Sheet
A2/
PU
A1+/
PU
A2/
PU
Port 5 General Purpose I/O Line 1
ASC0 Transmitter Output A
Port 5 General Purpose I/O Line 2
ASC1 Receiver Input/Output A
Port 5 General Purpose I/O Line 3
ASC1 Transmitter Output A
Port 5 General Purpose I/O Line 4
CCU62
42
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
C14
P5.5
I/O
SDI0
I
A1+/
PU
T12HRC
I
CCU62
T13HRC
I
CCU62
CCPOS2A
I
CCU63
T4EUDB
I
GPT120
T4EUDA
I
GPT121
OUT77
O1
OUT77 Line of GPTA0
OUT77
O2
OUT77 Line of GPTA1
OUT101
O3
OUT101 Line of LTCA2
P5.6
I/O
CC60INA
I
CC60INB
I
CCU63
EN10
O1
MSC1 Device Select Output 0
TVALID0B
O2
MLI0 transmit Channel valid Output B
CC60
O3
CCU62
P5.7
I/O
SDI1
I
CC61INA
I
CCU62
CC61INB
I
CCU63
OUT79
O1
OUT79 Line of GPTA0
OUT79
O2
OUT79 Line of GPTA1
CC61
O3
CCU62
B15
A15
Data Sheet
A2/
PU
A1+/
PU
Port 5 General Purpose I/O Line 5
MSC0 Serial Data Input
Port 5 General Purpose I/O Line 6
CCU62
Port 5 General Purpose I/O Line 7
MSC1 Serial Data Input
43
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
D17
P5.8
I/O
CC62INA
I
F/
PU
CC62INB
I
CCU63
SON0
O1
MSC0 Differential Driver Serial Data Output
Negative
OUT80
O2
OUT80 Line of GPTA0
CC62
O3
CCU62
P5.9
I/O
SOP0A
O1
OUT81
O2
OUT81 Line of GPTA0
COUT60
O3
CCU62
P5.10
I/O
FCLN0
O1
OUT82
O2
OUT82 Line of GPTA0
COUT61
O3
CCU62
P5.11
I/O
FCLP0A
O1
OUT83
O2
OUT83 Line of GPTA0
COUT62
O3
CCU62
P5.12
I/O
SON1
O1
OUT84
O2
OUT84 Line of GPTA0
OUT84
O3
OUT84 Line of GPTA1
C16
C17
C18
A16
Data Sheet
F/
PU
F/
PU
F/
PU
F/
PU
Port 5 General Purpose I/O Line 8
CCU62
Port 5 General Purpose I/O Line 9
MSC0 Differential Driver Serial Data Output
Positive A
Port 5 General Purpose I/O Line 10
MSC0 Differential Driver Clock Output
Negative
Port 5 General Purpose I/O Line 11
MSC0 Differential Driver Clock Output
Positive A
Port 5 General Purpose I/O Line 12
MSC1 Differential Driver Serial Data Output
Negative
44
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
B16
P5.13
I/O
SOP1A
O1
F/
PU
OUT85
O2
OUT85 Line of GPTA0
OUT85
O3
OUT85 Line of GPTA1
P5.14
I/O
FCLN1
O1
OUT86
O2
OUT86 Line of GPTA0
OUT86
O3
OUT86 Line of GPTA1
P5.15
I/O
FCLNP1A
O1
OUT87
O2
OUT87 Line of GPTA0
OUT87
O3
OUT87 Line of GPTA1
P6.4
I/O
MTSR1
I
MRSTG1
I
SSC Guardian 1 Master Receive Input
(Master Mode)
MTSR1
O1
SSC1 Master Transmit Output (Master
Mode)3)
Reserved
O2
-
Reserved
O3
-
B17
A17
F/
PU
F/
PU
Port 5 General Purpose I/O Line 13
MSC1 Differential Driver Serial Data Output
Positive A
Port 5 General Purpose I/O Line 14
MSC1 Differential Driver Clock Output
Negative
Port 5 General Purpose I/O Line 15
MSC1 Differential Driver Clock Output
Positive A
Port 6
F3
Data Sheet
A1+/
PU
Port 6 General Purpose I/O Line 4
SSC1 Slave Receive Input (Slave Mode)
45
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
G4
P6.5
I/O
MRST1
I
A1+/
PU
MRST1
O1
SSC1 Slave Transmit Output (Slave Mode)
Reserved
O2
-
Reserved
O3
-
P6.6
I/O
SCLK1
I
SCLK1
O1
SSC1 Clock Input/Output
Reserved
O2
-
Reserved
O3
-
P6.7
I/O
SLSI1
I
T6OFL
O1
GPT120
Reserved
O2
-
Reserved
O3
-
P6.8
I/O
RXDCAN0
I
RXD0B
I
ASC0 Receiver Input/Output B
CAPINB
I
GPT120
CAPINA
I
GPT121
Reserved
O1
-
RXD0B
O2
ASC0 Receiver Input/Output B
Reserved
O3
-
E3
G3
F4
Data Sheet
A1+/
PU
A1+/
PU
A2/
PU
Port 6 General Purpose I/O Line 5
SSC1 Master Receive Input (Master Mode)
Port 6 General Purpose I/O Line 6
SSC1 Clock Input/Output
Port 6 General Purpose I/O Line 7
SSC1 slave Select Input
Port 6 General Purpose I/O Line 8
CAN Node 0 Receiver Input 0
CAN Node 3 Receiver Input 1
46
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
E4
P6.9
I/O
TXDCAN0
O1
A2/
PU
TXD0
O2
ASC0 Transmitter Output B
T60FL
O3
GPT120
P6.10
I/O
RXDCAN1
I
RXD1B
I
ASC1 Receiver Input/Output B
Reserved
O1
-
RXD1B
O2
ASC1 Receiver Input/Output B
TXENA
O3
E-Ray Channel A transmit Data Output
enable 2)
P6.11
I/O
TXDCAN1
O1
TXD1
O2
ASC1 Transmitter Output B
TXENB
O3
E-Ray Channel B transmit Data Output
enable 2)
P6.12
I/O
RXDCAN2
I
RXDA1
I
E-Ray Channel A Receive Data Input 1 2)
Reserved
O1
-
Reserved
O2
-
COUT61
O3
CCU60
F2
E2
E1
Data Sheet
A2/
PU
A2/
PU
A1/
PU
Port 6 General Purpose I/O Line 9
CAN Node 0 Transmitter Output
Port 6 General Purpose I/O Line 10
CAN Node 1 Receiver Input 0
CAN Node 0 Receiver Input 1
Port 6 General Purpose I/O Line 11
CAN Node 1 Transmitter Output
Port 6 General Purpose I/O Line 12
CAN Node 2 Receiver Input 0
CAN Node 1 Receiver Input 1
47
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
G2
P6.13
I/O
TXDCAN2
O1
A2/
PU
TXDA
O2
E-Ray Channel A transmit Data Output 2)
COUT62
O3
CCU60
P6.14
I/O
RXDCAN3
I
RXDB1
I
E-Ray Channel B Receive Data Input 1 2)
Reserved
O1
-
Reserved
O2
-
COUT63
O3
CCU60
P6.15
I/O
CC60INB
I
CC60INA
I
CCU61
TXDCAN3
O1
CAN Node 3 Transmitter Output
TXDB
O2
E-Ray Channel B transmit Data Output 2)
CC60
O3
CCU61
P7.0
I/O
MRST3
I
REQ4
I
External trigger Input 4
AD2EMUX2
O1
ADC2 external multiplexer Control Output 2
MRST3
O2
SSC3 Slave Transmit Output (Maste Mode)
Reserved
O3
-
F1
G1
A1/
PU
A2/
PU
Port 6 General Purpose I/O Line 13
CAN Node 2 Transmitter Output
Port 6 General Purpose I/O Line 14
CAN Node 3 Receiver Input 0
CAN Node 2 Receiver Input 1
Port 6 General Purpose I/O Line 15
CCU60
Port 7
R3
Data Sheet
A1+/
PU
Port 7 General Purpose I/O Line 0
SSC3 Master Receive Input (Slave Mode)
48
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
R2
P7.1
I/O
REQ5
I
A1+/
PU
MTSR3
I
SSC3 Slave Receive Input (Slave Mode)
MRSTG3B
I
SSC Guardian 3 Master Receive Input B
(Master Mode)
AD0EMUX2
O1
ADC0 external multiplexer Control Output 2
MTSR3
O2
SSC3 Master Transmit Output (Master
Mode)3)
Reserved
O3
-
P7.2
I/O
SCLK3
I
AD0EMUX0
O1
ADC0 external multiplexer Control Output 0
SCLK3
O2
SSC3 Output
Reserved
O3
-
P7.3
I/O
AD0EMUX1
O1
SLSO30
O2
SSC3 Output
Reserved
O3
-
P7.4
I/O
REQ6
I
AD2EMUX0
O1
ADC2 external multiplexer Control Output 0
SLSO31
O2
SSC3 Output
Reserved
O3
-
U4
U3
T3
Data Sheet
A1+/
PU
A1+/
PU
A1+/
PU
Port 7 General Purpose I/O Line 1
External trigger Input 5
Port 7 General Purpose I/O Line 2
SSC3 Input
Port 7 General Purpose I/O Line 3
ADC0 external multiplexer Control Output 1
Port 7 General Purpose I/O Line 4
External trigger Input 6
49
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
T2
P7.5
I/O
REQ7
I
A1+/
PU
AD2EMUX1
O1
ADC2 external multiplexer Control Output 1
SLSO32
O2
SSC3 Output
Reserved
O3
-
P7.6
I/O
AD1EMUX0
O1
SLSO33
O2
SSC3 Output
Reserved
O3
-
P7.7
I/O
AD1EMUX1
O1
SLSO34
O2
SSC3 Output
Reserved
O3
-
P8.0
I/O
IN40
I
IN40
I
IN40 Line of GPTA1
SENT0
I
SENT Digital Input
OUT40
O1
OUT40 Line of GPTA0
COUT62
O2
CCU61
TCLK1
O3
MLI1 transmit Channel Clock Output
T1
U2
A1+/
PU
A1+/
PU
Port 7 General Purpose I/O Line 5
External trigger Input 7
Port 7 General Purpose I/O Line 6
ADC1 external multiplexer Control Output 0
Port 7 General Purpose I/O Line 7
ADC1 external multiplexer Control Output 1
Port 8
H2
Data Sheet
A2/
PU
Port 8 General Purpose I/O Line 0
IN40 Line of GPTA0
50
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
H1
P8.1
I/O
IN41
I
A1/
PU
IN41
I
IN41 Line of GPTA1
TREADY1A
I
MLI1 transmit Channel ready Input A
SENT1
I
SENT Digital Input
CC61INA
I
CCU60
CC61INB
I
CCU61
OUT41
O1
OUT41 Line of GPTA0
CC61
O2
CCU60
SENT1
O3
SENT Digital Output
P8.2
I/O
IN42
I
IN42
I
IN42 Line of GPTA1
SENT2
I
SENT Digital Input
CAPINA
I
GPT120
CAPINB
I
GPT121
COUT63
O1
CCU61
OUT42
O2
OUT42 Line of GPTA1
TVALID1A
O3
MLI1 transmit Channel valid Output A
J3
Data Sheet
A2/
PU
Port 8 General Purpose I/O Line 1
IN41 Line of GPTA0
Port 8 General Purpose I/O Line 2
IN42 Line of GPTA0
51
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
J2
P8.3
I/O
IN43
I
A2/
PU
IN43
I
IN43 Line of GPTA1
SENT3
I
SENT Digital Input
CC62INA
I
CCU60
CC62INB
I
CCU61
OUT43
O1
OUT43 Line of GPTA0
CC62
O2
CCU60
TDATA1
O3
MLI1 transmit Channel Data Output A
P8.4
I/O
IN44
I
IN44
I
IN44 Line of GPTA1
RCLK1A
I
MLI1 Receive Channel Clock Input A
SENT4
I
SENT Digital Input
CC62INB
I
CCU60
CC62INA
I
CCU61
OUT44
O1
OUT44 Line of GPTA0
CC62
O2
CCU61
T3OUT
O3
GPT121
J1
Data Sheet
A1/
PU
Port 8 General Purpose I/O Line 3
IN43 Line of GPTA0
Port 8 General Purpose I/O Line 4
IN44 Line of GPTA0
52
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
K2
P8.5
I/O
IN45
I
A2/
PU
IN45
I
IN45 Line of GPTA1
SENT5
I
SENT Digital Input
CTRAPA
I
CCU60
CTRAPB
I
CCU62
CC60INC
I
CCU60
T12HRE
I
CCU61
CC61INC
I
CCU61
OUT45
O1
OUT45 Line of GPTA0
OUT45
O2
OUT45 Line of GPTA1
RREADY1A
O3
MLI1 Receive Channel ready Output A
P8.6
I/O
IN46
I
IN46
I
IN46 Line of GPTA1
RVALID1A
I
MLI1 Receive Channel valid Input A
SENT6
I
SENT Digital Input
OUT46
O1
OUT46 Line of GPTA0
COUT60
O2
CCU61
T6OUT
O3
GPT120
K3
Data Sheet
A1/
PU
Port 8 General Purpose I/O Line 5
IN45 Line of GPTA0
Port 8 General Purpose I/O Line 6
IN46 Line of GPTA0
53
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
K1
P8.7
I/O
IN47
I
A1/
PU
IN47
I
IN47 Line of GPTA1
RDATA1A
I
MLI1 Receive Channel Data Input A
SENT7
I
SENT Digital Input
OUT47
O1
OUT47 Line of GPTA0
COUT61
O2
CCU61
T6OUT
O3
GPT121
P9.0
I/O
IN48
I
IN48
I
IN48 Line of GPTA1
COUT63
O1
CCU62
OUT48
O2
OUt48 Line of GPTA1
EN12
O3
MSC1 Device Select Output 2
P9.1
I/O
IN49
I
IN49
I
IN49 Line of GPTA1
CC60INB
I
CCU62
CC60INA
I
CCU63
CC60
O1
CCU63
OUT49
O2
OUT49 Line of GPTA1
EN11
O3
MSC1 Device Select Output 1
Port 8 General Purpose I/O Line 7
IN47 Line of GPTA0
Port 9
A19
B19
Data Sheet
A2/
PU
A2/
PU
Port 9 General Purpose I/O Line 0
IN48 Line of GPTA0
Port 9 General Purpose I/O Line 1
IN49 Line of GPTA0
54
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
B20
P9.2
I/O
IN50
I
A2/
PU
IN50
I
IN50 Line of GPTA1
CC61INB
I
CCU62
CC61INA
I
CCU63
CC61
O1
CCU63
OUT50
O2
OUT50 Line of GPTA1
SOP1B
O3
MSC1 serial Data Output
P9.3
I/O
IN51
I
IN51
I
IN51 Line of GPTA1
CC62INB
I
CCU62
CC62INA
I
CCU63
CC62
O1
CCU63
OUT51
O2
OUT51 Line of GPTA1
FCLP1B
O3
MSC1 Clock Output
P9.4
I/O
IN52
I
IN52
I
IN52 Line of GPTA1
COUT60
O1
CCU63
OUT52
O2
OUT52 Line of GPTA1
EN03
O3
MSC0 Device Select Output 3
A20
D18
Data Sheet
A2/
PU
A2/
PU
Port 9 General Purpose I/O Line 2
IN50 Line of GPTA0
Port 9 General Purpose I/O Line 3
IN51 Line of GPTA0
Port 9 General Purpose I/O Line 4
IN52 Line of GPTA0
55
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
D19
P9.5
I/O
IN53
I
A2/
PU
IN53
I
IN53 Line of GPTA1
SENT1
I
SENT Digital Input
COUT61
O1
CCU63
OUT53
O2
OUT53 Line of GPTA1
EN02
O3
MSC0 Device Select Output 2
P9.6
I/O
IN54
I
IN54
I
IN54 Line of GPTA1
SENT3
I
SENT Digital Input
OUT54
O1
OUT54 Line of GPTA0
SENT3
O2
SENT Digital Output
EN01
O3
MSC0 Device Select Output 1
P9.7
I/O
IN55
I
IN55
I
IN55 Line of GPTA1
SENT4
I
SENT Digital Input
OUT55
O1
OUT55 Line of GPTA0
SENT4
O2
SENT Digital Output
SOP0B
O3
MSC0 serial Data Output
P9.8
I/O
SENT6
I
COUT62
O1
CCU63
SENT6
O2
SENT Digital Output
FCLP0B
O3
MSC0 Clock Output
C19
D20
C20
Data Sheet
A2/
PU
A2/
PU
A2/
PU
Port 9 General Purpose I/O Line 5
IN53 Line of GPTA0
Port 9 General Purpose I/O Line 6
IN54 Line of GPTA0
Port 9 General Purpose I/O Line 7
IN55 Line of GPTA0
Port 9 General Purpose I/O Line 8
SENT Digital Input
56
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
A21
P9.9
I/O
SENT0
I
A1/
PU
Reserved
O1
-
SENT0
O2
SENT Digital Output
Reserved
O3
-
P9.10
I/O
EMGSTOP
I
SENT7
I
SENT Digital Input
COUT63
O1
CCU63
SENT7
O2
SENT Digital Output
Reserved
O3
-
P9.11
I/O
SENT2
I
Reserved
O1
-
SENT2
O2
SENT Digital Output
Reserved
O3
-
P9.12
I/O
SENT5
I
Reserved
O1
-
SENT5
O2
SENT Digital Output
Reserved
O3
-
B21
C21
D21
Data Sheet
A1/
PU
A1/
PU
A1/
PU
Port 9 General Purpose I/O Line 9
SENT Digital Input
Port 9 General Purpose I/O Line 10
Emergency Stop
Port 9 General Purpose I/O Line 11
SENT Digital Input
Port 9 General Purpose I/O Line 12
SENT Digital Input
57
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
C26
P9.13
I/O
BRKIN
I
A2/
PU
ECTT1
I
TTCAN Input
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
BRKOUT
O
OCDS Break Output
P9.14
I/O
BRKIN
I
ECTT2
I
TTCAN Input
REQ15
I
External trigger Input 15
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
BRKOUT
O
OCDS Break Output
P10.0
I/O
MRST0
I
MRST0
O1
SSC0 Slave Transmit Output (Slave Mode)
Reserved
O2
-
Reserved
O3
-
D26
A2/
PU
Port 9 General Purpose I/O Line 13
OCDS Break Input
Port 9 General Purpose I/O Line 14
OCDS Break Input
Port 10
AE15
Data Sheet
A2/
PU
Port 10 General Purpose I/O Line 0
SSC0 Master Receive Input (Master Mode)
58
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
AF15
P10.1
I/O
MTSR0
I
A2/
PU
MRSTG0
I
SSC Guardian 0 Master Receive Input
(Master Mode)
MTSR0
O1
SSC0 Master Transmit Output (Master
Mode)
Reserved
O2
-
Reserved
O3
-
P10.2
I/O
SLSI0
I
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
P10.3
I/O
SCLK0
I
SCLK0
O1
SSC0 Clock Input/Output
Reserved
O2
-
Reserved
O3
-
P10.4
I/O
SLSO0
O1
Reserved
O2
-
Reserved
O3
-
P10.5
I/O
SLSO1
O1
Reserved
O2
-
Reserved
O3
-
AD15
AF14
AE14
AC15
Data Sheet
A1/
PU
A2/
PU
A1+/
PU
A1+/
PU
Port 10 General Purpose I/O Line 1
SSC0 Slave Receive Input (Slave Mode)
Port 10 General Purpose I/O Line 2
SSC0 Slave Select Input
Port 10 General Purpose I/O Line 3
SSC0 Clock Input/Output
Port 10 General Purpose I/O Line 4
SSC0 Slave Select Output Line 0
Port 10 General Purpose I/O Line 5
SSC0 Slave Select Output Line 1
59
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
P11.0
I/O
Reserved
O1
B/
PU
Reserved
O2
-
Reserved
O3
-
A0
O
EBU Address Bus Line 0
P11.1
I/O
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A1
O
EBU Address Bus Line 1
P11.2
I/O
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A2
O
EBU Address Bus Line 2
P11.3
I/O
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A3
O
EBU Address Bus Line 3
P11.4
I/O
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A4
O
EBU Address Bus Line 4
Port 11
J26
K25
K26
J23
K24
Data Sheet
B/
PU
B/
PU
B/
PU
B/
PU
Port 11 General Purpose I/O Line 0
-
Port 11 General Purpose I/O Line 1
-
Port 11 General Purpose I/O Line 2
-
Port 11 General Purpose I/O Line 3
-
Port 11 General Purpose I/O Line 4
-
60
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
L25
P11.5
I/O
Reserved
O1
B/
PU
Reserved
O2
-
Reserved
O3
-
A5
O
EBU Address Bus Line 5
P11.6
I/O
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A6
O
EBU Address Bus Line 6
P11.7
I/O
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A7
O
EBU Address Bus Line 7
P11.8
I/O
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A8
O
EBU Address Bus Line 8
P11.9
I/O
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A9
O
EBU Address Bus Line 9
L26
K23
M26
M25
Data Sheet
B/
PU
B/
PU
B/
PU
B/
PU
Port 11 General Purpose I/O Line 5
-
Port 11 General Purpose I/O Line 6
-
Port 11 General Purpose I/O Line 7
-
Port 11 General Purpose I/O Line 8
-
Port 11 General Purpose I/O Line 9
-
61
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
M24
P11.10
I/O
Reserved
O1
B/
PU
Reserved
O2
-
Reserved
O3
-
A10
O
EBU Address Bus Line 10
P11.11
I/O
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A11
O
EBU Address Bus Line 11
P11.12
I/O
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A12
O
EBU Address Bus Line 12
P11.13
I/O
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A13
O
EBU Address Bus Line 13
P11.14
I/O
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A14
O
EBU Address Bus Line 14
L24
N26
N23
N24
Data Sheet
B/
PU
B/
PU
B/
PU
B/
PU
Port 11 General Purpose I/O Line 10
-
Port 11 General Purpose I/O Line 11
-
Port 11 General Purpose I/O Line 12
-
Port 11 General Purpose I/O Line 13
-
Port 11 General Purpose I/O Line 14
-
62
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
N25
P11.15
I/O
Reserved
O1
B/
PU
Reserved
O2
-
Reserved
O3
-
A15
O
EBU Address Bus Line 15
P12.0
I/O
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A16
O
EBU Address Bus Line 16
P12.1
I/O
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A17
O
EBU Address Bus Line 17
P12.2
I/O
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A18
O
EBU Address Bus Line 18
P12.3
I/O
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A19
O
EBU Address Bus Line 19
Port 11 General Purpose I/O Line 15
-
Port 12
P26
P24
P25
R24
Data Sheet
B/
PU
B/
PU
B/
PU
B/
PU
Port 12 General Purpose I/O Line 0
-
Port 12 General Purpose I/O Line 1
-
Port 12 General Purpose I/O Line 2
-
Port 12 General Purpose I/O Line 3
-
63
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
R26
P12.4
I/O
Reserved
O1
B/
PU
Reserved
O2
-
Reserved
O3
-
A20
O
EBU Address Bus Line 20
P12.5
I/O
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A21
O
EBU Address Bus Line 21
P12.6
I/O
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A22
O
EBU Address Bus Line 22
P12.7
I/O
Reserved
O1
Reserved
O2
-
Reserved
O3
-
A23
O
EBU Address Bus Line 23
R25
J24
J25
B/
PU
B/
PU
B/
PU
Port 12 General Purpose I/O Line 4
-
Port 12 General Purpose I/O Line 5
-
Port 12 General Purpose I/O Line 6
-
Port 12 General Purpose I/O Line 7
-
Port 13
Data Sheet
64
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
T26
P13.0
I/O
AD0
I
B/
PU
OUT88
O1
OUT88 Line of GPTA0
OUT88
O2
OUT88 Line of GPTA1
OUT80
O3
OUT80 Line of LTCA2
AD0
O
EBU Address/Data Bus Line 0
P13.1
I/O
AD1
I
OUT89
O1
OUT89 Line of GPTA0
OUT89
O2
OUT89 Line of GPTA1
OUT81
O3
OUT81 Line of LTCA2
AD1
O
EBU Address/Data Bus Line 1
P13.2
I/O
AD2
I
OUT90
O1
OUT90 Line of GPTA0
OUT90
O2
OUT90 Line of GPTA1
OUT82
O3
OUT82 Line of LTCA2
AD2
O
EBU Address/Data Bus Line 2
P13.3
I/O
AD3
I
OUT91
O1
OUT91 Line of GPTA0
OUT91
O2
OUT91 Line of GPTA1
OUT83
O3
OUT83 Line of LTCA2
AD3
O
EBU Address/Data Bus Line 3
T24
U26
T25
Data Sheet
B/
PU
B/
PU
B/
PU
Port 13 General Purpose I/O Line 0
EBU Address/Data Bus Line 0
Port 13 General Purpose I/O Line 1
EBU Address/Data Bus Line 1
Port 13 General Purpose I/O Line 2
EBU Address/Data Bus Line 2
Port 13 General Purpose I/O Line 3
EBU Address/Data Bus Line 3
65
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
V26
P13.4
I/O
AD4
I
B/
PU
OUT92
O1
OUT92 Line of GPTA0
OUT92
O2
OUT92 Line of GPTA1
OUT84
O3
OUT84 Line of LTCA2
AD4
O
EBU Address/Data Bus Line 4
P13.5
I/O
AD5
I
OUT93
O1
OUT93 Line of GPTA0
OUT93
O2
OUT93 Line of GPTA1
OUT85
O3
OUT85 Line of LTCA2
AD5
O
EBU Address/Data Bus Line 5
P13.6
I/O
AD6
I
OUT94
O1
OUT94 Line of GPTA0
OUT94
O2
OUT94 Line of GPTA1
OUT86
O3
OUT86 Line of LTCA2
AD6
O
EBU Address/Data Bus Line 6
P13.7
I/O
AD7
I
OUT95
O1
OUT95 Line of GPTA0
OUT95
O2
OUT95 Line of GPTA1
OUT87
O3
OUT87 Line of LTCA2
AD7
O
EBU Address/Data Bus Line 7
U25
U23
W26
Data Sheet
B/
PU
B/
PU
B/
PU
Port 13 General Purpose I/O Line 4
EBU Address/Data Bus Line 4
Port 13 General Purpose I/O Line 5
EBU Address/Data Bus Line 5
Port 13 General Purpose I/O Line 6
EBU Address/Data Bus Line 6
Port 13 General Purpose I/O Line 7
EBU Address/Data Bus Line 7
66
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
V25
P13.8
I/O
AD8
I
B/
PU
OUT96
O1
OUT96 Line of GPTA0
OUT96
O2
OUT96 Line of GPTA1
OUT88
O3
OUT88 Line of LTCA2
AD8
O
EBU Address/Data Bus Line 8
P13.9
I/O
AD9
I
OUT97
O1
OUT97 Line of GPTA0
OUT97
O2
OUT97 Line of GPTA1
OUT89
O3
OUT89 Line of LTCA2
AD9
O
EBU Address/Data Bus Line 9
P13.10
I/O
AD10
I
OUT98
O1
OUT98 Line of GPTA0
OUT98
O2
OUT98 Line of GPTA1
OUT90
O3
OUT90 Line of LTCA2
AD10
O
EBU Address/Data Bus Line 10
P13.11
I/O
AD11
I
OUT99
O1
OUT99 Line of GPTA0
OUT99
O2
OUT99 Line of GPTA1
OUT91
O3
OUT91 Line of LTCA2
AD11
O
EBU Address/Data Bus Line 11
U24
Y26
AA26
Data Sheet
B/
PU
B/
PU
B/
PU
Port 13 General Purpose I/O Line 8
EBU Address/Data Bus Line 8
Port 13 General Purpose I/O Line 9
EBU Address/Data Bus Line 9
Port 13 General Purpose I/O Line 10
EBU Address/Data Bus Line 10
Port 13 General Purpose I/O Line 11
EBU Address/Data Bus Line 11
67
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
W25
P13.12
I/O
AD12
I
B/
PU
OUT100
O1
OUT100 Line of GPTA0
OUT100
O2
OUT100 Line of GPTA1
OUT92
O3
OUT92 Line of LTCA2
AD12
O
EBU Address/Data Bus Line 12
P13.13
I/O
AD13
I
OUT101
O1
OUT101 Line of GPTA0
OUT101
O2
OUT101 Line of GPTA1
OUT93
O3
OUT93 Line of LTCA2
AD13
O
EBU Address/Data Bus Line 13
P13.14
I/O
AD14
I
OUT102
O1
OUT102 Line of GPTA0
OUT102
O2
OUT102 Line of GPTA1
OUT94
O3
OUT94 Line of LTCA2
AD14
O
EBU Address/Data Bus Line 14
P13.15
I/O
AD15
I
OUT103
O1
OUT103 Line of GPTA0
OUT103
O2
OUT103 Line of GPTA1
OUT95
O3
OUT95 Line of LTCA2
AD15
O
EBU Address/Data Bus Line 15
V24
Y25
AB26
B/
PU
B/
PU
B/
PU
Port 13 General Purpose I/O Line 12
EBU Address/Data Bus Line 12
Port 13 General Purpose I/O Line 13
EBU Address/Data Bus Line 13
Port 13 General Purpose I/O Line 14
EBU Address/Data Bus Line 14
Port 13 General Purpose I/O Line 15
EBU Address/Data Bus Line 15
Port 14
Data Sheet
68
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
W24
P14.0
I/O
AD16
I
B/
PU
CC60
O1
CCU60
OUT96
O2
OUT96 Line of GPTA1
OUT96
O3
OUT96 Line of LTCA2
AD16
O
EBU Address/Data Bus Line 16
P14.1
I/O
AD17
I
CC61
O1
CCU60
OUT97
O2
OUT97 Line of GPTA1
OUT97
O3
OUT97 Line of LTCA2
AD17
O
EBU Address/Data Bus Line 17
P14.2
I/O
AD18
I
CC62
O1
CCU60
OUT98
O2
OUT98 Line of GPTA1
OUT98
O3
OUT98 Line of LTCA2
AD18
O
EBU Address/Data Bus Line 18
P14.3
I/O
AD19
I
COUT60
O1
CCU60
OUT99
O2
OUT99 Line of GPTA1
OUT99
O3
OUT99 Line of LTCA2
AD19
O
EBU Address/Data Bus Line 19
AA25
Y24
AA23
Data Sheet
B/
PU
B/
PU
B/
PU
Port 14 General Purpose I/O Line 0
EBU Address/Data Bus Line 16
Port 14 General Purpose I/O Line 1
EBU Address/Data Bus Line 17
Port 14 General Purpose I/O Line 2
EBU Address/Data Bus Line 18
Port 14 General Purpose I/O Line 3
EBU Address/Data Bus Line 19
69
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
AB25
P14.4
I/O
AD20
I
B/
PU
COUT61
O1
CCU60
OUT100
O2
OUT100 Line of GPTA1
OUT100
O3
OUT100 Line of LTCA2
AD20
O
EBU Address/Data Bus Line 20
P14.5
I/O
AD21
I
COUT62
O1
CCU60
OUT101
O2
OUT101 Line of GPTA1
OUT101
O3
OUT101 Line of LTCA2
AD21
O
EBU Address/Data Bus Line 21
P14.6
I/O
AD22
I
COUT63
O1
CCU60
OUT102
O2
OUT102 Line of GPTA1
OUT102
O3
OUT102 Line of LTCA2
AD22
O
EBU Address/Data Bus Line 22
P14.7
I/O
AD23
I
CC60
O1
CCU61
OUT103
O2
OUT103 Line of GPTA1
OUT103
O3
OUT103 Line of LTCA2
AD23
O
EBU Address/Data Bus Line 23
AB24
AA24
AC26
Data Sheet
B/
PU
B/
PU
B/
PU
Port 14 General Purpose I/O Line 4
EBU Address/Data Bus Line 20
Port 14 General Purpose I/O Line 5
EBU Address/Data Bus Line 21
Port 14 General Purpose I/O Line 6
EBU Address/Data Bus Line 22
Port 14 General Purpose I/O Line 7
EBU Address/Data Bus Line 23
70
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
AD26
P14.8
I/O
AD24
I
B/
PU
CC61
O1
CCU61
T3OUT
O2
GPT120
OUT104
O3
OUT104 Line of LTCA2
AD24
O
EBU Address/Data Bus Line 24
P14.9
I/O
AD25
I
CC62
O1
CCU61
T3OUT
O2
GPT121
OUT105
O3
OUT105 Line of LTCA2
AD25
O
EBU Address/Data Bus Line 25
P14.10
I/O
AD26
I
COUT60
O1
CCU61
T6OUT
O1
GPT120
OUT106
O3
OUT106 Line of LTCA2
AD26
O
EBU Address/Data Bus Line 26
P14.11
I/O
AD27
I
COUT61
O1
CCU61
T6OUT
O1
GPT121
OUT107
O3
OUT107 Line of LTCA2
AD27
O
EBU Address/Data Bus Line 27
AC25
AE26
AD25
Data Sheet
B/
PU
B/
PU
B/
PU
Port 14 General Purpose I/O Line 8
EBU Address/Data Bus Line 24
Port 14 General Purpose I/O Line 9
EBU Address/Data Bus Line 25
Port 14 General Purpose I/O Line 10
EBU Address/Data Bus Line 26
Port 14 General Purpose I/O Line 11
EBU Address/Data Bus Line 27
71
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
AC24
P14.12
I/O
AD28
I
B/
PU
COUT62
O1
CCU61
OUT108
O2
OUT108 Line of GPTA1
OUT108
O3
OUT108 Line of LTCA2
AD28
O
EBU Address/Data Bus Line 28
P14.13
I/O
AD29
I
COUT63
O1
CCU61
OUT109
O2
OUT109 Line of GPTA1
OUT109
O3
OUT109 Line of LTCA2
AD29
O
EBU Address/Data Bus Line 29
P14.14
I/O
AD30
I
T3INC
I
GPT120
T3IND
I
GPT121
OUT110
O1
OUT110 Line of GPTA0
OUT110
O2
OUT110 Line of GPTA1
OUT110
O3
OUT110 Line of LTCA2
AD30
O
EBU Address/Data Bus Line 30
AE25
AE24
Data Sheet
B/
PU
B/
PU
Port 14 General Purpose I/O Line 12
EBU Address/Data Bus Line 28
Port 14 General Purpose I/O Line 13
EBU Address/Data Bus Line 29
Port 14 General Purpose I/O Line 14
EBU Address/Data Bus Line 30
72
V 1.2, 2014-05
TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
AD24
P14.15
I/O
AD31
I
B/
PU
T3EUDC
I
GPT120
T3EUDD
I
GPT121
OUT111
O1
OUT111 Line of GPTA0
OUT111
O2
OUT111 Line of GPTA1
OUT111
O3
OUT111 Line of LTCA2
AD31
O
EBU Address/Data Bus Line 31
P15.0
I/O
T4INC
I
T4IND
I
GPT121
CCPOS2B
I
CCU60
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
CS0
O
Chip Select Output Line 0
P15.1
I/O
T4EUDC
I
T4EUDD
I
GPT121
CCPOS2B
I
CCU61
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
CS1
O
Chip Select Output Line 1
Port 14 General Purpose I/O Line 15
EBU Address/Data Bus Line 31
Port 15
AE21
AD21
Data Sheet
B/
PU
B/
PU
Port 15 General Purpose I/O Line 0
GPT120
Port 15 General Purpose I/O Line 1
GPT120
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TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
AD20
P15.2
I/O
Reserved
O1
B/
PU
Reserved
O2
-
Reserved
O3
-
CS2
O
Chip Select Output Line 2
P15.3
I/O
Reserved
O1
Reserved
O2
-
Reserved
O3
-
CS3
O
Chip Select Output Line 3
P15.4
I/O
Reserved
O1
Reserved
O2
-
Reserved
O3
-
BC0
O
Byte Control Line 0
P15.5
I/O
Reserved
O1
Reserved
O2
-
Reserved
O3
-
BC1
O
Byte Control Line 1
P15.6
I/O
Reserved
O1
Reserved
O2
-
Reserved
O3
-
BC2
O
Byte Control Line 2
AD19
AE17
AD17
AF18
Data Sheet
B/
PU
B/
PU
B/
PU
B/
PU
Port 15 General Purpose I/O Line 2
-
Port 15 General Purpose I/O Line 3
-
Port 15 General Purpose I/O Line 4
-
Port 15 General Purpose I/O Line 5
-
Port 15 General Purpose I/O Line 6
-
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TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
AE18
P15.7
I/O
Reserved
O1
B/
PU
Reserved
O2
-
Reserved
O3
-
BC3
O
Byte Control Line 3
P15.8
I/O
Reserved
O1
Reserved
O2
-
Reserved
O3
-
RD
O
Read Control Line
P15.9
I/O
Reserved
O1
Reserved
O2
-
Reserved
O3
-
RD/WR
O
Write Control Line
P15.10
I/O
Reserved
O1
Reserved
O2
-
Reserved
O3
-
ADV
O
Address Valid Output
P15.11
I/O
WAIT
I
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
AF20
AF21
AF22
AE20
Data Sheet
B/
PU
B/
PU
B/
PU
B/
PU
Port 15 General Purpose I/O Line 7
-
Port 15 General Purpose I/O Line 8
-
Port 15 General Purpose I/O Line 9
-
Port 15 General Purpose I/O Line 10
-
Port 15 General Purpose I/O Line 11
Wait Input for inserting Wait-States
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TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
AF19
P15.12
I/O
Reserved
O1
B/
PU
Reserved
O2
-
Reserved
O3
-
MR/W
O
Motorola-style Read/Write Control Signal
P15.13
I/O
Reserved
O1
Reserved
O2
-
Reserved
O3
-
BAA
O
Burst Address Advance Output
P15.14
I/O
BFCLKI
I
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
P15.15
I/O
Reserved
O1
Reserved
O2
-
Reserved
O3
-
BFCLKO
O
Burst Mode Flash Clock Output (NonDifferential)
AF23
AF24
AF25
B/
PU
B/
PU
B/
PU
Port 15 General Purpose I/O Line 12
-
Port 15 General Purpose I/O Line 13
-
Port 15 General Purpose I/O Line 14
Burst FLASH Clock Input (Clock Feedback).
Port 15 General Purpose I/O Line 15
-
Port 16
Data Sheet
76
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TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
AF17
P16.0
I/O
HOLD
I
B/
PU
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
P16.1
I/O
HLDA
I
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
HLDA
O
Hold Acknowledge Output
P16.2
I/O
Reserved
O1
Reserved
O2
-
Reserved
O3
-
BREQ
O
Bus Request Output
P16.3
I/O
Reserved
O1
Reserved
O2
-
Reserved
O3
-
CSCOMB
O
Combined Chip Select Output
P17.0
I
SENT0
I
SENT Digital Input 0
AN8
I
Analog Input : ADC0.CH8 5)
AD18
AD22
AE19
B/
PU
B/
PU
B/
PU
Port 16 General Purpose I/O Line 0
Hold Request Input
Port 16 General Purpose I/O Line 1
Hold Acknowledge Output
Port 16 General Purpose I/O Line 2
-
Port 16 General Purpose I/O Line 3
-
Port 17
AC1
Data Sheet
D/S
Port 17 General Purpose I Line 04)
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TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
AB2
P17.1
I
D/S
SENT1
I
SENT Digital Input 1
AN9
I
Analog Input : ADC0.CH9 5)
P17.2
I
SENT2
I
SENT Digital Input 2
AN10
I
Analog Input : ADC0.CH10 5)
P17.3
I
SENT3
I
SENT Digital Input 3
AN11
I
Analog Input : ADC0.CH11 5)
P17.4
I
SENT4
I
SENT Digital Input 4
AN12
I
Analog Input : ADC0.CH12 5)
P17.5
I
SENT5
I
SENT Digital Input 5
AN13
I
Analog Input : ADC0.CH13 5)
P17.6
I
SENT6
I
SENT Digital Input 6
AN14
I
Analog Input : ADC0.CH14 5)
P17.7
I
SENT7
I
SENT Digital Input 7
AN15
I
Analog Input : ADC0.CH15 5)
P17.8
I
SENT0
I
SENT Digital Input 0
AN36
I
Analog Input : ADC2.CH4 5)
Y3
AA2
AB1
W3
Y2
AA1
AE3
Data Sheet
D/S
D/S
D/S
D/S
D/S
D/S
D/S
Port 17 General Purpose I Line 14)
Port 17 General Purpose I Line 24)
Port 17 General Purpose I Line 34)
Port 17 General Purpose I Line 44)
Port 17 General Purpose I Line 54)
Port 17 General Purpose I Line 64)
Port 17 General Purpose I Line 74)
Port 17 General Purpose I Line 84)
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TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
AF2
P17.9
I
D/S
SENT1
I
SENT Digital Input 1
AN37
I
Analog Input : ADC2.CH5 5)
P17.10
I
SENT2
I
SENT Digital Input 2
AN38
I
Analog Input : ADC2.CH6 5)
P17.11
I
SENT3
I
SENT Digital Input 3
AN39
I
Analog Input : ADC2.CH7 5)
P17.12
I
SENT4
I
SENT Digital Input 4
AN40
I
Analog Input : ADC2.CH8 5)
P17.13
I
SENT5
I
SENT Digital Input 5
AN41
I
Analog Input : ADC2.CH9 5)
P17.14
I
SENT6
I
SENT Digital Input 6
AN42
I
Analog Input : ADC2.CH10 5)
P17.15
I
SENT7
I
SENT Digital Input 7
AN43
I
Analog Input : ADC2.CH11 5)
AC4
AF3
AD4
AE4
AC5
AF4
D/S
D/S
D/S
D/S
D/S
D/S
Port 17 General Purpose I Line 94)
Port 17 General Purpose I Line 104)
Port 17 General Purpose I Line 114)
Port 17 General Purpose I Line 124)
Port 17 General Purpose I Line 134)
Port 17 General Purpose I Line 144)
Port 17 General Purpose I Line 154)
Analog Input Port
AE1
AN0
I
D
Analog Input 0: ADC0.CH0 5)
AD2
AN1
I
D
Analog Input 1: ADC0.CH1 5)
AA4
AN2
I
D
Analog Input 2: ADC0.CH2 5)
AB3
AN3
I
D
Analog Input 3: ADC0.CH3 5)
Data Sheet
79
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TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
AC2
AN4
I
D
Analog Input 4: ADC0.CH4, ADC2.CH12 5)
AA3
AN5
I
D
Analog Input 5: ADC0.CH5, ADC2.CH13 5)
AD1
AN6
I
D
Analog Input 6: ADC0.CH6, ADC2.CH14 5)
AB4
AN7
I
D
Analog Input 7: ADC0.CH7, ADC2.CH15 5)
AC1
AN8
I
D/S
Analog Input 8: ADC0.CH8, SENT0 5)
AB2
AN9
I
D/S
Analog Input 9: ADC0.CH9, SENT1 5)
Y3
AN10
I
D/S
Analog Input 10: ADC0.CH10, SENT2 5)
AA2
AN11
I
D/S
Analog Input 11: ADC0.CH11, SENT3 5)
AB1
AN12
I
D/S
Analog Input 12: ADC0.CH12, SENT4 5)
W3
AN13
I
D/S
Analog Input 13: ADC0.CH13, SENT5 5)
Y2
AN14
I
D/S
Analog Input 14: ADC0.CH14, SENT6 5)
AA1
AN15
I
D/S
Analog Input 15: ADC0.CH15, SENT7 5)
V4
AN16
I
D
Analog Input 16: ADC1.CH0 5)
W2
AN17
I
D
Analog Input 17: ADC1.CH1 5)
Y1
AN18
I
D
Analog Input 18: ADC1.CH2 5)
V3
AN19
I
D
Analog Input 19: ADC1.CH3 5)
W1
AN20
I
D
Analog Input 20: ADC1.CH4 5)
V2
AN21
I
D
Analog Input 21: ADC1.CH5 5)
V1
AN22
I
D
Analog Input 22: ADC1.CH6 5)
U1
AN23
I
D
Analog Input 23: ADC1.CH7 5)
AC8
AN24
I
D
Analog Input 24: ADC1.CH8,
FADC_FADIN0P 6)
AD8
AN25
I
D
Analog Input 25: ADC1.CH9,
FADC_FADIN0N 6)
AC7
AN26
I
D
Analog Input 26: ADC1.CH10,
FADC_FADIN1P 6)
Data Sheet
80
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TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
AD7
AN27
I
D
Analog Input 27: ADC1.CH11,
FADC_FADIN1N 6)
AE6
AN28
I
D
Analog Input 28: ADC1.CH12,
FADC_FADIN2P 6)
AF6
AN29
I
D
Analog Input 29: ADC1.CH13,
FADC_FADIN2N 6)
AE7
AN30
I
D
Analog Input 30: ADC1.CH14,
FADC_FADIN3P 6)
AF7
AN31
I
D
Analog Input 31: ADC1.CH15,
FADC_FADIN3N 6)
AC3
AN32
I
D
Analog Input 32: ADC2.CH0 5)
AE2
AN33
I
D
Analog Input 33: ADC2.CH1 5)
AD3
AN34
I
D
Analog Input 34: ADC2.CH2 5)
AD5
AN35
I
D
Analog Input 35: ADC2.CH3 5)
AE3
AN36
I
D/S
Analog Input 36: ADC2.CH4, SENT0 5)
AF2
AN37
I
D/S
Analog Input 37: ADC2.CH5, SENT1 5)
AC4
AN38
I
D/S
Analog Input 38: ADC2.CH6, SENT2 5)
AF3
AN39
I
D/S
Analog Input 39: ADC2.CH7, SENT3 5)
AD4
AN40
I
D/S
Analog Input 40: ADC2.CH8, SENT4 5)
AE4
AN41
I
D/S
Analog Input 41: ADC2.CH9, SENT5 5)
AC5
AN42
I
D/S
Analog Input 42: ADC2.CH10, SENT6 5)
AF4
AN43
I
D/S
Analog Input 43: ADC2.CH11, SENT7 5)
System I/O
B22
PORST
I
PD
Power-on Reset Input
A23
ESR0
I/O
A2
External System Request Reset Input 0
Default configuration during and after reset is
open-drain driver. The driver drives low during
power-on reset.
Data Sheet
81
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TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
A22
ESR1
I/O
A2/
PD
External System Request Reset Input 1
E24
TCK
I
PD
JTAG Module Clock Input
DAP0
I
TDI
I
BRKIN
I
BRKOUT
O
B23
TESTMODE
I
PU
Test Mode Select Input
F24
TMS
I
JTAG Module State Machine Control Input
DAP1
I/O
A2/
PD
F23
TRST
I
PD
JTAG Module Reset/Enable Input
G26
XTAL1
I
Main Oscillator/PLL/Clock Generator Input
G25
XTAL2
O
Main Oscillator/PLL/Clock Generator Output
D25
TDO
O
BRKIN
I
BRKOUT
O
OCDS Break Output (Alternate Output)
DAP2
O
Device Access Port Line 2
E25
Device Access Port Line 0
A2/
PU
JTAG Module Serial Data Input
OCDS Break Input (Alternate Output)
OCDS Break Output (Alternate Input)
A2/
PU
Device Access Port Line 1
JTAG Module Serial Data Output
OCDS Break Input (Alternate Input)
Power Supply
W4
VDDM
-
-
ADC Analog Part Power Supply (3.3V - 5V)
Y4
VSSM
-
-
ADC Analog Part Ground
AE5
VAREF0
-
-
ADC0 Reference Voltage
AF5
VAGND0
-
-
ADC0 Reference Ground
VAGND2
-
-
ADC2 Reference Ground
AD6
VAREF1
-
-
ADC1 Reference Voltage
AC6
VAGND1
-
-
ADC1 Reference Ground
AD9
VAREF2
-
-
ADC2 Reference Voltage
Data Sheet
82
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TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
AF8
VFAREF
-
-
FADC Reference Voltage
AE8
VFAGND
-
-
FADC Reference Ground
AE9
VDDMF
-
-
FADC Analog Part Power Supply (3.3V)
AC9
VDDAF
-
-
FADC Analog Part Logic Power Supply
(1.3V)
AF9
VSSMF
-
-
FADC Analog Part Ground
VSSAF
-
-
FADC Analog Part Logic Ground
A18,
B18,
H3
VDDFL3
-
-
Flash Power Supply (3.3V)
F25
VSSOSC
-
-
Main Oscillator Ground
VSS
-
-
Digital Ground
F26
VDDOSC
-
-
Main Oscillator Power Supply (1.3V)
E26
VDDOSC3
-
-
Main Oscillator Power Supply (3.3V)
G23
VDDPF
-
-
E-Ray PLL Power Supply (1.3V)
G24
VDDPF3
-
-
E-Ray PLL Power Supply (3.3V)
AC11,
AC20,
AB23,
V23,
P23,
E23,
D24,
C25,
B26,
D16,
D9,
H4,
R4
VDD
-
-
Digital Core Power Supply (1.3V)
Data Sheet
83
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TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
AC16, VDDP
AD16,
AE16,
AF16,
D22,
C23,
B24,
A25,
D14,
D7, K4
-
-
Port Power Supply (3.3V)
H23,
H24,
H25,
H26,
M23,
T23,
Y23,
AC18,
AC22
VDDEBU
-
-
EBU Port Power Supply (1.8V - 2.5V - 3.3V)
R1
VDDSB
-
-
Emulation Stand-by SRAM Power Supply
(1.3V) (Emulation device only)
Note: This pin is N.C. in a productive device.
AC10,
AC17,
AC19,
AC23,
W23,
R23,
L23,
D23,
C24,
B25,
A26,
D15,
D8,
J4, T4
VSS
Data Sheet
-
-
Digital Ground (outer balls)
84
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TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
K10,
K11,
K12,
K13,
K14,
K15,
K16,
K17
VSS
-
-
Digital Ground (center balls)
L10,
L11,
L12,
L13,
L14,
L15,
L16,
L17
VSS
-
-
Digital Ground (center balls cont’d)
M10,
M11,
M12,
M13,
M14,
M15,
M16,
M17
VSS
-
-
Digital Ground (center balls cont’d)
N10,
N11,
N12,
N13,
N14,
N15,
N16,
N17
VSS
-
-
Digital Ground (center balls cont’d)
Data Sheet
85
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TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
P10,
P11,
P12,
P13,
P14,
P15,
P16,
P17
VSS
-
-
Digital Ground (center balls cont’d)
R10,
R11,
R12,
R13,
R14,
R15,
R16,
R17
VSS
-
-
Digital Ground (center balls cont’d)
T10,
T11,
T12,
T13,
T14,
T15,
T16,
T17
VSS
-
-
Digital Ground (center balls cont’d)
U10,
U11,
U12,
U13,
U14,
U15,
U16,
U17
VSS
-
-
Digital Ground (center balls cont’d)
Data Sheet
86
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TC1793
PinningTC1793 Pin Configuration
Pin Definitions and Functions (cont’d)
Table 2
Pin
Symbol
Ctrl.
Type Function
A1,
AF1,
AF26,
A24,
C22,
AC21,
AD23,
AE22,
AE23
N.C.
-
-
Not connected. These pins are reserved for
future extension and shall not be connected
externally.
1) Only applicable in TC1793ED. Reserved in TC1793PD.
2) Only available for SAK-TC1793F-512F270EF, SAK-TC1793F-512F200EF, and SAK-TC1793F-512F200EB.
3) The MTSR output of SSCx is overlayed with the MRSTG input of the related SSCGx
4) Analog Input overlayed with a SENT Digitial Input. The related port logic is used configure the input as either
analog input (default after reset) or digital input. The related port logic supports only the port input features as
the connected pads are input pads only.
5) IOZ1 valid for this pin is the parameter with overlayed = No in the ADC parameter table.
6) IOZ1 valid for this pin is the parameter with overlayed = Yes in the ADC parameter table.
Legend for Table 2
Column “Ctrl.”:
I = Input (for GPIO port lines with IOCR bit field selection PCx = 0XXXB)
O = Output
O0 = Output with IOCR bit field selection PCx = 1X00B
O1 = Output with IOCR bit field selection PCx = 1X01B (ALT1)
O2 = Output with IOCR bit field selection PCx = 1X10B(ALT2)
O3 = Output with IOCR bit field selection PCx = 1X11(ALT3)
Column “Type”:
A1 = Pad class A1 (LVTTL)
A1+ = Pad class A1+ (LVTTL)
A2 = Pad class A2 (LVTTL)
B = Pad class B(LVTTL)
F = Pad class F (LVDS/CMOS)
D = Pad class D (ADC)
S = Pad class S(SENT)
PU = with pull-up device connected during reset (PORST = 0)
PD = with pull-down device connected during reset (PORST = 0)
TR = tri-state during reset (PORST = 0)
Data Sheet
87
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TC1793
Identification Registers
4
Identification Registers
The Identification Registers uniquely identify the whole device.
Table 3
SAK-TC1793F-512F270EF Identification Registers
Short Name
Value
Address
Stepping
CBS_JDPID
0000 6350H
F000 0408H
AB
CBS_JTAGID
1018 E083H
F000 0464H
AB
SCU_CHIPID
8700 9702H
F000 0640H
AB
SCU_MANID
0000 1820H
F000 0644H
AB
SCU_RTID
0000 0000H
F000 0648H
AB
Table 4
SAK-TC1793F-512F200EF Identification Registers
Short Name
Value
Address
Stepping
CBS_JDPID
0000 6350H
F000 0408H
AB
CBS_JTAGID
1018 E083H
F000 0464H
AB
SCU_CHIPID
9700 9702H
F000 0640H
AB
SCU_MANID
0000 1820H
F000 0644H
AB
SCU_RTID
0000 0000H
F000 0648H
AB
Table 5
SAK-TC1793F-512F200EB Identification Registers
Short Name
Value
Address
Stepping
CBS_JDPID
0000 6350H
F000 0408H
AB
CBS_JTAGID
1018 E083H
F000 0464H
AB
SCU_CHIPID
1700 9702H
F000 0640H
AB
SCU_MANID
0000 1820H
F000 0644H
AB
SCU_RTID
0000 0000H
F000 0648H
AB
Table 6
SAK-TC1793N-512F270EF Identification Registers
Short Name
Value
Address
Stepping
CBS_JDPID
0000 6350H
F000 0408H
AB
CBS_JTAGID
1018 E083H
F000 0464H
AB
SCU_CHIPID
8700 B102H
F000 0640H
AB
Data Sheet
88
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TC1793
Identification Registers
Table 6
SAK-TC1793N-512F270EF Identification Registers (cont’d)
Short Name
Value
Address
Stepping
SCU_MANID
0000 1820H
F000 0644H
AB
SCU_RTID
0000 0000H
F000 0648H
AB
Table 7
SAK-TC1793S-512F270EF Identification Registers
Short Name
Value
Address
Stepping
CBS_JDPID
0000 6350H
F000 0408H
AB
CBS_JTAGID
1018 E083H
F000 0464H
AB
SCU_CHIPID
C700 9702H
F000 0640H
AB
SCU_MANID
0000 1820H
F000 0644H
AB
SCU_RTID
0000 0000H
F000 0648H
AB
Data Sheet
89
V 1.2, 2014-05
TC1793
Electrical ParametersGeneral Parameters
5
Electrical Parameters
This specification provides all electrical parameters of the TC1793.
5.1
General Parameters
5.1.1
Parameter Interpretation
The parameters listed in this section partly represent the characteristics of the TC1793
and partly its requirements on the system. To aid interpreting the parameters easily
when evaluating them for a design, they are marked with an two-letter abbreviation in
column “Symbol”:
•
•
CC
Such parameters indicate Controller Characteristics which are a distinctive feature of
the TC1793 and must be regarded for a system design.
SR
Such parameters indicate System Requirements which must provided by the
microcontroller system in which the TC1793 designed in.
Data Sheet
90
V 1.2, 2014-05
TC1793
Electrical ParametersGeneral Parameters
5.1.2
Pad Driver and Pad Classes Summary
This section gives an overview on the different pad driver classes and its basic
characteristics. More details (mainly DC parameters) are defined in the Section 5.2.1.
Table 8
Pad Driver and Pad Classes Overview
Class Power Type
Supply
Sub Class
Speed Load
Grade 1)
Leakage
150oC 1)
Termination
1)
A
B
3.3 V
3.3 V2)
LVTTL
I/O,
LVTTL
outputs
6 MHz
100 pF 500 nA
A1+
(e.g. serial
I/Os)
25
MHz
50 pF
1 μA
Series
termination
recommended
A2
(e.g. serial
I/Os)
40
MHz
50 pF
3 μA
Series
termination
recommended
75
MHz
35 pF
6 μA
75
MHz
35 pF
Series
termination
recommended
–
–
Parallel
termination,
100 Ω ± 10% 3)
A1
(e.g. GPIO)
LVTTL
I/O
2.5 V
2)
F
3.3 V
DE
5V
I
3.3 V
LVDS
–
50
MHz
CMOS
–
6 MHz
50 pF
–
ADC
–
–
–
–
LVTTL
(input
only)
–
–
–
–
No
1) These values show typical application configurations for the pad. Complete and detailed pad parameters are
available in the individual pad parameter table on the following pages.
2) Supplied via VDDEBU.
3) In applications where the LVDS pins are not used (disabled), these pins must be either left unconnected, or
properly terminated with the differential parallel termination of 100 Ω ± 10%.
Data Sheet
91
V 1.2, 2014-05
TC1793
Electrical ParametersGeneral Parameters
5.1.3
Absolute Maximum Ratings
Stresses above the values listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Table 9
Absolute Maximum Rating Parameters
Parameter
Symbol
Values
Min. Typ. Max.
Storage temperature
TST
Voltage at 1.3 V power supply VDD
pins with respect to VSS
Voltage at 3.3 V power supply VDDP
SR
pins with respect to VSS
Voltage at 5 V power supply VDDM
pins with respect to VSS
Voltage on any Class A input VIN
Unit Note /
Test Con
dition
SR -65
–
150
°C
–
SR –
–
2.0
V
–
–
–
4.33
V
–
SR –
–
7.0
V
–
SR -0.7 –
VDDP + 0.7 V
or max. 4.33
Whatever
is lower
-0.6 –
7.0
V
–
Voltage on any shared Class VAINF
-0.6 –
D analog input pin with
VFAREF
respect to VSSAF, if the FADC
SR
is switched through to the pin.
7.0
V
–
Input current on any pin
during overload condition
pin and dedicated input pins
with respect to VSS
Voltage on any Class D
analog input pin with respect
to VAGND
VAIN
VAREFx
SR
IIN
-10
–
+10
mA
Absolute maximum sum of all IIN
input circuit currents for one
port group during overload
condition1)
-25
–
+25
mA
Absolute maximum sum of all ΣIIN
input circuit currents during
overload condition
-200 –
200
mA
Data Sheet
92
V 1.2, 2014-05
TC1793
Electrical ParametersGeneral Parameters
1) The port groups are defined in Table 14.
Data Sheet
93
V 1.2, 2014-05
TC1793
Electrical ParametersGeneral Parameters
5.1.4
Pin Reliability in Overload
When receiving signals from higher voltage devices, low-voltage devices experience
overload currents and voltages that go beyond their own IO power supplies specification.
Table 10 defines overload conditions that will not cause any negative reliability impact if
all the following conditions are met:
•
•
full operation life-time (24000 h) is not exceeded
Operating Conditions are met for
– pad supply levels (VDDP, VDDM, or, VDDEBU)
– temperature
If a pin current is out of the Operating Conditions but within the overload parameters,
then the parameters functionality of this pin as stated in the Operating Conditions can no
longer be guaranteed. Operation is still possible in most cases but with relaxed
parameters.
Note: An overload condition on one or more pins does not require a reset.
Table 10
Overload Parameters
Parameter
Min. Typ. Max.
Unit Note /
Test Con
dition
Input current on any digital pin IIN
during overload condition
except LVDS pins
-5
mA
Input current on LVDS pins
IINLVDS
IING
-3
–
+3
mA
-20
–
+20
mA
IINANA
IINSA
-3
–
+3
mA
-45
–
+45
mA
ΣIINS
-100 –
100
mA
Absolute sum of all input
circuit currents for one port
group during overload
condition1)
Input current on analog pins
Absolute sum of all analog
input currents for analog
inputs during overload
condition
Absolute sum of all input
circuit currents during
overload condition
Symbol
Values
–
+5
1) The port groups are defined in Table 14.
Note: FADC input pins count as analog pin as they are overlayed with an ADC pins.
Data Sheet
94
V 1.2, 2014-05
TC1793
Electrical ParametersGeneral Parameters
Table 11
Pad Type
A1 / A1+ / F
A2
LVDS
D
S
Table 12
Pad Type
A1 / A1+ / F
A2
LVDS
D
S
PN-Junction Characteristics for positive Overload
IIN = 3 mA
UIN = VDDP + 0.6 V
UIN = VDDP + 0.5 V
UIN = VDDP + 0.7 V
UIN = VDDM + 0.6 V
UIN = VDDM + 0.6 V
IIN = 5 mA
UIN = VDDP + 0.7 V
UIN = VDDP + 0.6 V
-
PN-Junction Characteristics for negative Overload
IIN = -3 mA
UIN = VSS - 0.6 V
UIN = VSS - 0.5 V
UIN = VSS - 0.7 V
UIN = VSSM - 0.6 V
UIN = VSSM - 0.6 V
IIN = -5 mA
UIN = VSS - 0.7 V
UIN = VSS - 0.6 V
-
Note: A series resistor at the pin to limit the current to the maximum permitted overload
current is sufficient to handle failure situations like short to battery without having
any negative reliability impact on the operational life-time.
Data Sheet
95
V 1.2, 2014-05
TC1793
Electrical ParametersGeneral Parameters
5.1.5
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation and reliability of the TC1793. All parameters specified in the following tables
refer to these operating conditions, unless otherwise noticed.
Digital supply voltages applied to the TC1793 must be static regulated voltages which
allow a typical voltage swing of ± 5 %.
All parameters specified in the following tables (Table 15 and following) refer to these
operating conditions (Table 13), unless otherwise noticed in the Note / Test Condition
column.
The Extended Range Operating Conditions did not increase area of validity of the
parameters defined in table 10 and later.
Table 13
Operating Conditions Parameters
Parameter
Symbol
Overload coupling factor KOVAN
for analog inputs, negative CC
Values
Unit
Min.
Typ.
Max.
−
−
0.0001
Note /
Test Condition
IOV≤ 0 mA;
IOV≥ -2 mA;
analog
pad= 5.0 V
Overload coupling factor KOVAP
for analog inputs, positive CC
−
−
0.0000
1
IOV≤ 3 mA;
IOV≥ 0 mA;
analog
pad= 5.0 V
CPU Frequency
Data Sheet
fCPU SR −
−
270
MHz SAK-TC1793F512F
270EB; SAKTC1793F-512F
270EF; SAKTC1793N-512F
270EF; SAKTC1793S-512F
270EF
−
−
200
MHz SAK-TC1793F512F 200EF
SAK-TC1793F512F 200EB
96
V 1.2, 2014-05
TC1793
Electrical ParametersGeneral Parameters
Table 13
Operating Conditions Parameters (cont’d)
Parameter
Symbol
Values
Min.
Modulated fCPU
Modulated fFPI
−
270
MHz SAK-TC1793F512F
270EB; SAKTC1793F-512F
270EF; SAKTC1793N-512F
270EF; SAKTC1793S-512F
270EF
−
−
200
MHz SAK-TC1793F512F 200EF
SAK-TC1793F512F 200EB
fFPI SR −
fFPI_modul −
−
100
MHz
−
100MHz MA = modulatio
2*MA1)
n amplitude
−
150
−
150MHz MA = modulatio
2*MA1)
n amplitude
−
200
−
200MHz MA = modulatio
2*MA1)
n amplitude
−
−
270
MHz SAK-TC1793F512F
270EB; SAKTC1793F-512F
270EF; SAKTC1793N-512F
270EF; SAKTC1793S-512F
270EF
−
−
200
MHz SAK-TC1793F512F 200EF
SAK-TC1793F512F 200EB
fCPU_mod −
ated
FSI frequency
Modulated fFSI
Modulated fPCP
SR
SR
fPCP SR −
fPCP_mod −
ulated
SRI Frequency
Data Sheet
SR
fFSI SR −
fFSI_modul −
ated
PCP Frequency
Note /
Test Condition
Max.
ulated
FPI bus frequency
Unit
Typ.
SR
fSRI SR
97
MHz
MHz
V 1.2, 2014-05
TC1793
Electrical ParametersGeneral Parameters
Table 13
Operating Conditions Parameters (cont’d)
Parameter
Symbol
Values
Min.
Unit
Note /
Test Condition
Typ.
Max.
−
270
MHz SAK-TC1793F512F
270EB; SAKTC1793F-512F
270EF; SAKTC1793N-512F
270EF; SAKTC1793S-512F
270EF
−
−
200
MHz SAK-TC1793F512F 200EF
SAK-TC1793F512F 200EB
Inactive device pin current IID SR
-1
−
1
mA
Short circuit current of
digital outputs2)
ISC SR
-5
−
5
mA
Absolute sum of short
circuit currents of the
device
ΣISC_D
CC
−
−
100
mA
Absolute sum of short
circuit currents per pin
group
ΣISC_PG
CC
−
−
20
mA
Ambient Temperature
−
125
°C
Core Supply Voltage
TA SR
-40
TJ SR
-40
VDD SR 1.17
EBU supply voltage
VDDEBU
Modulated fSRI
fSRI_modul −
ated
Junction temperature
SR
SR
Flash supply voltage 3.3V VDDFL3
SR
Data Sheet
−
150
°C
1.3
1.433)
V
3.135
3.3
3.475)
V
2.375
2.5
2.625
V
3.3
5)
V
2.97
98
3.63
All power
supply voltages
VDDx = 0
for duration
limitation see
Section 5.1.5.1
for duration
limitation see
Section 5.1.5.1
V 1.2, 2014-05
TC1793
Electrical ParametersGeneral Parameters
Table 13
Operating Conditions Parameters (cont’d)
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
Note /
Test Condition
ADC analog supply
voltage
VDDM
2.97
5
5.54)
V
Oscillator core supply
voltage
VDDOSC
1.17
1.3
1.433)
V
for duration
limitation see
Section 5.1.5.1
VDDOSC3 2.97
3.3
3.635)
V
for duration
limitation see
Section 5.1.5.1
VDDP SR 2.97
3.3
3.63 5) V
for duration
limitation see
Section 5.1.5.1
Oscillator 3.3V supply
voltage
Digital supply voltage for
IO pads
SR
SR
SR
E-Ray PLL core voltage
supply
VDDPF
1.17
1.3
1.433)
V
SR
for duration
limitation see
Section 5.1.5.1
E-Ray PLL 3.3V supply
VDDPF3
2.97
3.3
3.635)
V
for duration
limitation see
Section 5.1.5.1
VDDPPA
0.65
−
−
V
VSS SR 0
Analog ground voltage for VSSM SR -0.1
VDDM
Analog core supply
VDDAF
1.17
−
−
V
0
0.1
V
1.3
1.433)
V
for duration
limitation see
Section 5.1.5.1
for duration
limitation see
Section 5.1.5.1
SR
VDDP voltage to ensure
defined pad states6)
CC
Digital ground voltage
SR
VDDMF
2.97
3.3
3.635)
V
Analog ground voltage for VSSAF
SR
-0.1
0
0.1
V
FADC / ADC analog
supply voltage
SR
VDDMF
1) MA equals the modulation amplitude in percentage times the configured PLL clock out frequency.
2) Applicable for digital outputs.
3) Voltage overshoot to 1.7V is permissible at Power-Up and PORST low, provided the pulse duration is less
than 100 μs and the cumulated sum of the pulses does not exceed 1 h.
Data Sheet
99
V 1.2, 2014-05
TC1793
Electrical ParametersGeneral Parameters
4) Voltage overshoot to 6.5V is permissible at Power-Up and PORST low, provided the pulse duration is less
than 100 μs and the cumulated sum of the pulses does not exceed 1 h.
5) Voltage overshoot to 4.0V is permissible at Power-Up and PORST low, provided the pulse duration is less
than 100 μs and the cumulated sum of the pulses does not exceed 1 h.
6) This parameter is valid under the assumption the PORST signal is constantly at low level during the powerup/power-down of VDDP.
5.1.5.1
Extended Range Operating Conditions
The following extended operating conditions are defined:
•
•
•
1.3V + 5% < VDD / VDDOSC / VDDPF / VDDAF < 1.3V + 7.5% (overvoltage condition):
– limited to 10000 hours duration cumulative in lifetime, due to the reliability
reduction of the chip caused by the overvoltage stress.
1.3V + 7.5% < VDD / VDDOSC / VDDPF / VDDAF < 1.3V + 10% (overvoltage condition):
– limited to 1000 hours duration cumulative in lifetime, due to the reliability reduction
of the chip caused by the overvoltage stress.
3.3V + 5% < VDDP / VDDOSC3 / VDDPF3 / VDDFL3 / VDDMF / VDDEBU< 3.3V + 10%
(overvoltage condition):
limited to 1000 hours duration cumulative in lifetime, due to the reliability reduction of
the chip caused by the overvoltage stress.
Table 14
Pin Groups for Overload / Short-Circuit Current Sum Parameter
Group
Pins
1
P2.[4:2], P6.[6:9]
2
P6.[5:4], P6.[11:10]
3
P6.[15:12]
4
P8.[5:0]
5
P8.[7:6], P1.[15:13]
6
P1.5, P1.[11:8]
7
P1.[4:2], P1.6, P1.12
8
P1.[1:0], P7.[2:0]
9
P7.[7:3]
10
P4.[6:0]
11
P4.[10:7]
12
P4.[15:11]
13
P10.[5:0]
14
P15.[7:4], P16.[1:0]
15
P15.3, P15.[12:11], P16.[5:3]
Data Sheet
100
V 1.2, 2014-05
TC1793
Electrical ParametersGeneral Parameters
Table 14
Pin Groups for Overload / Short-Circuit Current Sum Parameter
Group
Pins
16
P15.[2:0], P15.[9:8], P16.2, P16.8
17
P15.10, P15.[15:13], P16.[7:6]
18
P14.[15:12]
19
P14.[11:8], P16.12
20
P14.[7:3], P16.11
21
P13.15, P14.[2:0]
22
P13.[14:11]
23
P13.[10:8], P16.10
24
P13.[7:4], P16.9
25
P12.5, P13.[3:0]
26
P12.[4:0]
27
P11.[15:11]
28
P11.[10:6]
29
P11.[5:2]
30
P11.[1:0], P12.[7:6]
31
P9.10, P9.14
32
P9.7, P9.13
33
P9.[4:2], P9.6
34
P9.1, P9.5, P9.[9:8]
35
P9.0, P9.[12:11]
36
P5.[11:8]
37
P5.6, P5.[15:12]
38
P5.0, P5.[5:2], P5.7
39
P3.[5:0], P5.1
40
P3.[12:6]
41
P0.[3:0], P3.[15:13]
42
P0.[11:4]
43
P0.[14:12]
44
P0.15
Data Sheet
101
V 1.2, 2014-05
TC1793
Electrical ParametersGeneral Parameters
Table 14
Pin Groups for Overload / Short-Circuit Current Sum Parameter
Group
Pins
45
P2.[15:11]
46
P2.[10:5]
Data Sheet
102
V 1.2, 2014-05
TC1793
Electrical ParametersDC Parameters
5.2
DC Parameters
5.2.1
Input/Output Pins
Table 15
Standard_Pads Parameters
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note /
Test Condition
TA= 25 °C;
f= 1 MHz
Vi≥ 0.6 x VDDP V
Vi≥ 0.36 x
VDDP V
Vi≤ 0.6 x VDDP V
Vi≤ 0.36 x
VDDP V
Pin capacitance (digital
inputs/outputs)
CIO CC
−
−
10
pF
Pull-down current
|IPDL|
CC
−
−
150
μA
10
−
−
μA
|IPUH|
CC
10
−
−
μA
−
−
100
μA
Spike filter always blocked tSF1 CC
pulse duration
−
−
10
ns
only PORST pin
Spike filter pass-through
pulse duration
100
−
−
ns
only PORST pin
Unit
Note /
Test Condition
Pull-Up current
Table 16
tSF2 CC
Standard_Pads Class_A1
Parameter
Symbol
Min.
Typ.
Max.
Input Hysteresis for A1
pads 1)
HYSA1
0.1 x
−
−
V
CC
VDDP
IOZA1
-500
−
500
nA
VILA1 /
VIHA1
0.6
−
−
Input Leakage Current
Class A1
Ratio Vil/Vih, A1 pads
Values
CC
Vi≥ 0 V;
Vi≤ VDDP V
CC
Data Sheet
103
V 1.2, 2014-05
TC1793
Electrical ParametersDC Parameters
Table 16
Standard_Pads Class_A1 (cont’d)
Parameter
Symbol
On-Resistance of the
RDSONW
class A1 pad, weak driver CC
On-Resistance of the
class A1 pad, medium
driver
CC
Fall time, pad type A1
tFA1 CC
RDSONM
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
−
450
600
Ohm IOH> -0.5 mA;
P_MOS
−
210
340
Ohm IOL< 0.5 mA;
N_MOS
−
−
155
Ohm IOH> -2 mA;
P_MOS
−
−
110
Ohm IOL< 2 mA;
N_MOS
−
−
150
ns
CL= 20 pF; pin
out
driver= weak
−
−
50
ns
CL= 50 pF; pin
out
driver= medium
−
−
140
ns
CL= 150 pF; pin
out
driver= medium
−
−
550
ns
CL= 150 pF; pin
out
driver= weak
−
−
18000
ns
CL= 20000 pF;
pin out
driver= medium
−
−
65000
ns
CL= 20000 pF;
pin out
driver= weak
Data Sheet
104
V 1.2, 2014-05
TC1793
Electrical ParametersDC Parameters
Table 16
Standard_Pads Class_A1 (cont’d)
Parameter
Symbol
Values
Min.
Rise time, pad type A1
Typ.
Max.
tRA1 CC −
−
150
−
−
Unit
Note /
Test Condition
ns
CL= 20 pF; pin
out
driver= weak
50
ns
CL= 50 pF; pin
out
driver= medium
−
−
140
ns
CL= 150 pF; pin
out
driver= medium
−
−
550
ns
CL= 150 pF; pin
out
driver= weak
−
−
18000
ns
CL= 20000 pF;
pin out
driver= medium
−
−
65000
ns
CL= 20000 pF;
pin out
driver= weak
Input high voltage class
A1 pads
VIHA1
SR
0.6 x
min(V V
DDP+
0.3,3.6
)
−
Input low voltage class A1 VILA1 SR -0.3
pads
Data Sheet
−
VDDP
0.36 x
V
VDDP
105
V 1.2, 2014-05
TC1793
Electrical ParametersDC Parameters
Table 16
Standard_Pads Class_A1 (cont’d)
Parameter
Symbol
Values
Min.
Output voltage high class
A1 pads
VOHA1
CC
Typ.
Unit
Note /
Test Condition
V
IOH≥ -1.4 mA;
Max.
VDDP - −
−
−
−
0.4
2.4
pin out
driver= medium
V
IOH≥ -2 mA; pin
out
driver= medium
VDDP - −
−
V
IOH≥ -400 μA;
pin out
driver= weak
2.4
−
−
V
IOH≥ -500 μA;
pin out
driver= weak
−
−
0.4
V
IOL≤ 2 mA; pin
0.4
Output voltage low class
A1 pads
VOLA1
CC
out
driver= medium
−
−
0.4
V
IOL≤ 500 μA;
pin out
driver= weak
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be
guaranteed that it suppresses switching due to external system noise.
Table 17
Standard_Pads Class_A1+
Parameter
Symbol
Input Hysteresis for A1+
pads 1)
HYSA1
+ CC
IOZA1+
VDDP
RDSONW
Input Leakage Current
Class A1+
On-Resistance of the
class A1+ pad, weak
driver
Data Sheet
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
0.1 x
−
−
V
-1000
−
1000
nA
−
450
600
Ohm IOH> -0.5 mA;
P_MOS
−
210
340
Ohm IOL< 0.5 mA;
N_MOS
CC
CC
106
V 1.2, 2014-05
TC1793
Electrical ParametersDC Parameters
Table 17
Standard_Pads Class_A1+ (cont’d)
Parameter
Symbol
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
−
−
155
Ohm IOH> -2 mA;
P_MOS
−
−
110
Ohm IOL< 2 mA;
N_MOS
On-Resistance of the
class A1+ pad, strong
driver
RDSON1+ −
−
100
Ohm IOH> -2 mA;
P_MOS
−
−
80
Ohm IOL< 2 mA;
N_MOS
Fall time, pad type A1+
tFA1+ CC −
−
150
ns
−
−
On-Resistance of the
class A1+ pad, medium
driver
RDSONM
CC
CC
CL= 20 pF; pin
out
driver= weak
28
ns
CL= 50 pF;
edge= slow ;
pin out
driver= strong
−
−
16
ns
CL= 50 pF;
edge= soft ; pin
out
driver= strong
−
−
50
ns
CL= 50 pF; pin
out
driver= medium
−
−
140
ns
CL= 150 pF; pin
out
driver= medium
−
−
550
ns
CL= 150 pF; pin
out
driver= weak
−
−
18000
ns
CL= 20000 pF;
pin out
driver= medium
−
−
65000
ns
CL= 20000 pF;
pin out
driver= weak
Data Sheet
107
V 1.2, 2014-05
TC1793
Electrical ParametersDC Parameters
Table 17
Standard_Pads Class_A1+ (cont’d)
Parameter
Symbol
Values
Min.
Rise time, pad type A1+
Typ.
Max.
tRA1+ CC −
−
150
−
−
Unit
Note /
Test Condition
ns
CL= 20 pF; pin
out
driver= weak
28
ns
CL= 50 pF;
edge= slow ;
pin out
driver= strong
−
−
16
ns
CL= 50 pF;
edge= soft ; pin
out
driver= strong
−
−
50
ns
CL= 50 pF; pin
out
driver= medium
−
−
140
ns
CL= 150 pF; pin
out
driver= medium
−
−
550
ns
CL= 150 pF; pin
out
driver= weak
−
−
18000
ns
CL= 20000 pF;
pin out
driver= medium
−
−
65000
ns
CL= 20000 pF;
pin out
driver= weak
Input high voltage, Class
A1+ pads
Input low voltage Class
A1+ pads
Ratio Vil/Vih, A1+ pads
VIHA1+
SR
VILA1+
0.6 x
−
VDDP
0.3,3.6
)
−
-0.3
SR
VILA1+ /
VIHA1+
min(V V
DDP+
0.36 x
V
VDDP
−
0.6
−
CC
Data Sheet
108
V 1.2, 2014-05
TC1793
Electrical ParametersDC Parameters
Table 17
Standard_Pads Class_A1+ (cont’d)
Parameter
Symbol
Values
Min.
Output voltage high class
A1+ pads
VOHA1+
CC
Typ.
Unit
Note /
Test Condition
V
IOH≥ -1.4 mA;
Max.
VDDP - −
−
VDDP - −
−
−
−
0.4
pin out
driver= medium
V
0.4
2.4
IOH≥ -1.4 mA;
pin out
driver= strong
V
IOH≥ -2 mA; pin
out
driver= medium
−
2.4
−
V
IOH≥ -2 mA; pin
out
driver= strong
VDDP - −
−
V
IOH≥ -400 μA;
pin out
driver= weak
2.4
−
−
V
IOH≥ -500 μA;
pin out
driver= weak
−
−
0.4
V
IOL≤ 2 mA; pin
0.4
Output voltage low class
A1+ pads
VOLA1+
CC
out
driver= medium
−
−
0.4
V
IOL≤ 2 mA; pin
out
driver= strong
−
−
0.4
V
IOL≤ 500 μA;
pin out
driver= weak
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be
guaranteed that it suppresses switching due to external system noise.
Data Sheet
109
V 1.2, 2014-05
TC1793
Electrical ParametersDC Parameters
Table 18
Standard_Pads Class_A2
Parameter
Input Hysteresis for A2
pads 1)
Input Leakage current
Class A2
Symbol
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
HYSA2
0.1 x
−
−
V
CC
VDDP
IOZA2
-6000
−
6000
nA
-3000
−
3000
nA
0.6
−
−
−
450
600
Ohm IOH> -0.5 mA;
P_MOS
−
210
340
Ohm IOL< 0.5 mA;
N_MOS
−
−
155
Ohm IOH> -2 mA;
P_MOS
−
−
110
Ohm IOL< 2 mA;
N_MOS
−
−
28
Ohm IOH> -2 mA;
P_MOS
−
−
22
Ohm IOL< 2 mA;
N_MOS
CC
Vi< VDDP / 2 1 V; Vi> VDDP / 2
+ 1 V; Vi≥ 0 V;
Vi≤ VDDP V
Vi> VDDP / 2 1 V; Vi< VDDP / 2
+1V
Ratio Vil/Vih, A2 pads
VILA2 /
VIHA2
CC
On-Resistance of the
RDSONW
class A2 pad, weak driver CC
On-Resistance of the
class A2 pad, medium
driver
RDSONM
CC
On-Resistance of the
RDSON2
class A2 pad, strong driver CC
Data Sheet
110
V 1.2, 2014-05
TC1793
Electrical ParametersDC Parameters
Table 18
Standard_Pads Class_A2 (cont’d)
Parameter
Fall time, pad type A2
Symbol
tFA2 CC
Values
Min.
Typ.
Max.
−
−
150
Unit
Note /
Test Condition
ns
CL= 20 pF; pin
out
driver= weak
−
−
7
ns
CL= 50 pF;
edge= medium
; pin out
driver= strong
−
−
10
ns
CL= 50 pF;
edge= mediumminus ; pin out
driver= strong
−
−
3.7
ns
CL= 50 pF;
edge= sharp ;
pin out
driver= strong
−
−
5
ns
CL= 50 pF;
edge= sharpminus ; pin out
driver= strong
−
−
16
ns
CL= 50 pF;
edge= soft ; pin
out
driver= strong
−
−
50
ns
CL= 50 pF; pin
out
driver= medium
−
−
7.5
ns
CL= 100 pF;
edge= sharp ;
pin out
driver= strong
−
−
140
ns
CL= 150 pF; pin
out
driver= medium
Data Sheet
111
V 1.2, 2014-05
TC1793
Electrical ParametersDC Parameters
Table 18
Parameter
Standard_Pads Class_A2 (cont’d)
Symbol
Values
Min.
Typ.
Max.
−
−
550
Unit
Note /
Test Condition
ns
CL= 150 pF; pin
out
driver= weak
−
−
18000
ns
CL= 20000 pF;
pin out
driver= medium
−
−
65000
ns
CL= 20000 pF;
pin out
driver= weak
Data Sheet
112
V 1.2, 2014-05
TC1793
Electrical ParametersDC Parameters
Table 18
Standard_Pads Class_A2 (cont’d)
Parameter
Symbol
Values
Min.
Rise time, pad type A2
Typ.
Max.
tRA2 CC −
−
150
−
−
Unit
Note /
Test Condition
ns
CL= 20 pF; pin
out
driver= weak
7.0
ns
CL= 50 pF;
edge= medium
; pin out
driver= strong
−
−
10
ns
CL= 50 pF;
edge= mediumminus ; pin out
driver= strong
−
−
3.7
ns
CL= 50 pF;
edge= sharp ;
pin out
driver= strong
−
−
5
ns
CL= 50 pF;
edge= sharpminus ; pin out
driver= strong
−
−
16
ns
CL= 50 pF;
edge= soft ; pin
out
driver= strong
−
−
50
ns
CL= 50 pF; pin
out
driver= medium
−
−
7.5
ns
CL= 100 pF;
edge= sharp ;
pin out
driver= strong
−
−
140
ns
CL= 150 pF; pin
out
driver= medium
Data Sheet
113
V 1.2, 2014-05
TC1793
Electrical ParametersDC Parameters
Table 18
Standard_Pads Class_A2 (cont’d)
Parameter
Symbol
Values
Min.
Typ.
Max.
−
−
550
Unit
Note /
Test Condition
ns
CL= 150 pF; pin
out
driver= weak
−
−
18000
ns
CL= 20000 pF;
pin out
driver= medium
−
−
65000
ns
CL= 20000 pF;
pin out
driver= weak
Input high voltage, class
A2 pads
VIHA2
SR
0.6 x
VOHA2
CC
min(V V
DDP +
0.3,
3.6)
−
Input low voltage Class A2 VILA2 SR -0.3
pads
Output voltage high class
A2 pads
−
VDDP
0.36 x
V
VDDP
VDDP - −
−
VDDP - −
−
−
−
V
0.4
pin out
driver= medium
V
0.4
2.4
IOH≥ -1.4 mA;
IOH≥ -1.4 mA;
pin out
driver= strong
V
IOH≥ -2 mA; pin
out
driver= medium
−
2.4
−
V
IOH≥ -2 mA; pin
out
driver= strong
VDDP - −
−
V
IOH≥ -400 μA;
pin out
driver= weak
−
−
V
IOH≥ -500 μA;
pin out
driver= weak
0.4
2.4
Data Sheet
114
V 1.2, 2014-05
TC1793
Electrical ParametersDC Parameters
Table 18
Standard_Pads Class_A2 (cont’d)
Parameter
Symbol
Output voltage low class
A2 pads
VOLA2
Values
Min.
Typ.
Max.
−
−
0.4
Unit
Note /
Test Condition
V
IOL≤ 2 mA; pin
CC
out
driver= medium
−
−
0.4
V
IOL≤ 2 mA; pin
out
driver= strong
−
−
0.4
V
IOL≤ 500 μA;
pin out
driver= weak
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be
guaranteed that it suppresses switching due to external system noise.
Table 19
Standard_Pads Class_B
Parameter
Input Hysteresis, B class
pads1)
Symbol
Values
Unit
Note /
Test Condition
−
V
VDDEBU= 2.5 V
−
−
V
VDDEBU= 3.3 V
Min.
Typ.
Max.
HYSB
0.08 x
−
CC
VDDEBU
0.1 x
VDDEBU
Input Leakage Current,
class B pads
IOZB CC -6000
−
6000
nA
else
-3000
−
3000
nA
(VDDEBU/2 0.6 V) < Vi < (V
Ratio between low and
high input threshold
VILB /
0.6
VIHB CC
RDSONW −
−
−
450
600
Ohm IOH> -0.5 mA;
P_MOS
−
210
340
Ohm IOL< 0.5 mA;
N_MOS
−
−
155
Ohm IOH> -2 mA;
P_MOS
−
−
110
Ohm IOL< 2 mA;
N_MOS
DDEBU/2
On-Resistance of the
class B pad, weak driver
On-Resistance of the
class B pad, medium
driver
Data Sheet
CC
RDSONM
CC
115
+ 0.6 V)
V 1.2, 2014-05
TC1793
Electrical ParametersDC Parameters
Table 19
Standard_Pads Class_B (cont’d)
Parameter
On-Resistance of the
class B pad, strong driver
Fall time, class B pads;
edge= sharp ; pin out
driver= strong 2)
Data Sheet
Symbol
RDSON2
Values
Unit
Typ.
Max.
−
−
28
Ohm IOH> -2 mA;
P_MOS
−
−
22
Ohm IOL< 2 mA;
N_MOS
−
−
3.7
ns
−
−
3.0
ns
−
−
4.6
ns
−
−
3.7
ns
−
−
9.0
ns
−
−
7.5
ns
CC
tFB CC
Note /
Test Condition
Min.
116
CL= 35 pF;
VDDEBU> 2.375 ;
VDDEBU≤ 2.625
CL= 35 pF;
VDDEBU> 3.13 ;
VDDEBU≤ 3.47
CL= 50 pF;
VDDEBU> 2.375 ;
VDDEBU≤ 2.625
CL= 50 pF;
VDDEBU> 3.13 ;
VDDEBU≤ 3.47
CL= 100 pF;
VDDEBU> 2.375 ;
VDDEBU≤ 2.625
CL= 100 pF;
VDDEBU> 3.13 ;
VDDEBU≤ 3.47
V 1.2, 2014-05
TC1793
Electrical ParametersDC Parameters
Table 19
Standard_Pads Class_B (cont’d)
Parameter
Rise time, class B pads;
edge= sharp ; pin out
driver= strong 2)
Symbol
tRB CC
Values
Unit
Note /
Test Condition
3.7
ns
−
3.0
ns
−
−
4.6
ns
−
−
3.7
ns
−
−
9.0
ns
−
−
7.5
ns
CL= 35 pF;
VDDEBU> 2.375 ;
VDDEBU≤ 2.625
CL= 35 pF;
VDDEBU> 3.13 ;
VDDEBU≤ 3.47
CL= 50 pF;
VDDEBU> 2.375 ;
VDDEBU≤ 2.625
CL= 50 pF;
VDDEBU 3.13 ;
VDDEBU≤ 3.47
CL= 100 pF;
VDDEBU> 2.375 ;
VDDEBU≤ 2.625
CL= 100 pF;
VDDEBU> 3.13 ;
VDDEBU≤ 3.47
Min.
Typ.
Max.
−
−
−
Input high voltage, class B VIHB CC 0.6 x
−
pads
VDDEBU
−
Input low voltage, Class B VILB CC -0.3
pads
Output voltage high, class VOHB
B pads
CC
max(V V
DDEBU
+ 0.3,
3.6)
0.36 x
V
VDDEBU
VDDEBU −
−
V
- 0.4
IOH -2 mA;
VDDEBU> 2.375
V;
Output voltage low, class
B pads
VOLB CC −
−
0.4
V
VDDEBU≤ 3.47 V
IOL= 2 mA
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be
guaranteed that it suppresses switching due to external system noise.
2) For non strong driver and sharp edge settings see the class A2 definitions.
Data Sheet
117
V 1.2, 2014-05
TC1793
Electrical ParametersDC Parameters
Table 20
Standard_Pads Class_F
Parameter
Input Hysteresis F1)
Input Leakage Current
Class F
Symbol
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
HYSF
0.05 x
−
−
V
CC
VDDP
IOZF CC -6000
−
6000
nA
-3000
−
3000
nA
−
−
−
170
Ohm IOH> -2 mA;
P_MOS
−
−
145
Ohm IOL< 2 mA;
N_MOS
Vi< VDDP / 2 1 V; Vi> VDDP / 2
+ 1 V; Vi≥ 0 V;
Vi≤ VDDP V
Vi> VDDP / 2 1 V; Vi< VDDP / 2
+1V
Ratio Vil/ Vih, F pads
On-Resistance of the
class F pad, medium
driver
0.6
VILF /
VIHF CC
RDSONM −
CC
Fall time, pad type F,
CMOS mode
tFF CC
−
−
60
ns
CL= 50 pF
Rise time, pad type F,
CMOS mode
tRF CC
−
−
60
ns
CL= 50 pF
Input high voltage, pad
class F, CMOS mode
VIHF SR 0.6 x
VDDP
−
min(V V
DDP+
−
Input low voltage, Class F VILF SR
pads, CMOS mode
-0.3
Output high voltage, class VOHF
F pads, CMOS mode
CC
VDDP-
0.36 x
V
VDDP
−
−
V
IOH≥ -1.4 mA
IOH≥ -2 mA
IOL≤ 2 mA
0.4
2.4
Output low voltage, class
F pads, CMOS mode
0.3,
3.6)
VOLF CC −
−
−
V
−
0.4
V
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be
guaranteed that it suppresses switching due to external system noise.
Data Sheet
118
V 1.2, 2014-05
TC1793
Electrical ParametersDC Parameters
Table 21
Standard_Pads Class_I
Parameter
Symbol
Input Hysteresis Class I1)
Input Leakage Current
Ratio between low and
high input threshold
Input high voltage, class I
pins
Input low voltage, Class I
pads
Values
Unit
Min.
Typ.
Max.
HYSI
0.1 x
−
−
V
CC
VDDP
IOZI CC -1000
VILI / VIHI 0.6
−
1000
nA
−
−
VIHI SR
−
min(V V
DDP+
Note /
Test Condition
CC
0.6 x
VDDP
VILI SR
0.3,
3.6)
−
-0.3
0.36 x
V
VDDP
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be
guaranteed that it suppresses switching due to external system noise.
Class S pad parameters are only valid for VDDM = 4.75 V to 5.25 V.
Table 22
Standard_Pads Class_S
Parameter
Symbol
Input Hysteresis for class
S pads1)
HYSS
Input leakage current
Input voltage high
Input voltage low
VILS Delta 2)
Values
Unit
Min.
Typ.
Max.
0.3
−
−
V
-300
−
300
nA
−
−
3.6
V
1.9
−
−
V
-50
−
50
mV
Note /
Test Condition
CC
IOZS CC
VIHS CC
VILS CC
VILSD
CC
Maximum input
low state
threshold
variation over
1ms
(VDDP = consta
nt)
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be
guaranteed that it suppresses switching due to external system noise.
Data Sheet
119
V 1.2, 2014-05
TC1793
Electrical ParametersDC Parameters
2) VILSD is implemented to ensure J2716 specification. It can’t be guaranteed that it suppresses switching due to
external noise.
Table 23
LVDS_Pads Parameters
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
Note /
Test Condition
Output impedance, pad
class F, LVDS mode
RO CC
40
−
140
Ohm
Fall time, pad type LVDS
tFL CC
−
−
2
ns
termination
100 Ω ± 1 %
Rise time, pad type LVDS tRL CC
−
−
2
ns
termination
100 Ω ± 1 %
tSET_LVD −
−
13
μs
termination
100 Ω ± 1 %
−
400
mV
termination
100 Ω ± 1 %
Pad set-up time
S
CC
Output Differential Voltage VOD CC 150
Output voltage high, pad
class F, LVDS mode
VOH CC −
−
1525
mV
termination
100 Ω ± 1 %
Output voltage low, pad
class F, LVDS mode
VOL CC
−
−
mV
termination
100 Ω ± 1 %
Output Offset Voltage
VOS CC 1075
−
1325
mV
termination
100 Ω ± 1 %
Data Sheet
875
120
V 1.2, 2014-05
TC1793
Electrical ParametersDC Parameters
5.2.2
Analog to Digital Converters (ADCx)
ADC parameter are valid for VDD / DDAF = 1.235 V to 1.365 V; VDDM = 4.5 V to 5.5 V.
Table 24
ADC Parameters
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
CAINSW
Switched capacitance at
the analog voltage inputs1) CC
−
9
20
pF
Total capacitance of an
analog input
−
20
30
pF
Switched capacitance at
the positive reference
voltage input2)3)
CAREFSW −
15
30
pF
Total capacitance of the
voltage reference inputs2)
CAREFTO −
20
40
pF
Differential Non-Linearity
Error4)5)6)7)
Gain Error4)5)6)7)
CAINTOT
CC
CC
T CC
EADNL
-3
−
3
LSB
ADC
resolution= 12bit 8) 9)
EAGAIN
-3.5
−
3.5
LSB
ADC
resolution= 12bit 8) 9)
EAINL
-3
−
3
LSB
ADC
resolution= 12bit 8) 9)
EAOFF
-4
−
4
LSB
ADC
resolution= 12bit 8) 9)
CC
CC
Integral NonLinearity4)5)7)7)
Offset Error4)5)6)7)
CC
CC
Converter clock
Internal ADC clock
Charge consumption per
conversion
Note /
Test Condition
fADC SR 4
fADCI CC 1
−
100
MHz fADC= fFPI
−
18
MHz ADC0
1
−
18
MHz ADC1
1
−
2010)
MHz ADC2
100
pC
QCONV
11)
70
85
CC
charge needs to
be provided via
VAREF0
Data Sheet
121
V 1.2, 2014-05
TC1793
Electrical ParametersDC Parameters
Table 24
ADC Parameters (cont’d)
Parameter
Symbol
Values
Min.
Input leakage at analog
inputs12)
IOZ1 CC -100
Typ.
Max.
−
500
Unit
Note /
Test Condition
nA
Vi≤ VDDM V;
Vi≥ 0.97 x
VDDM V;
overlayed= No
-100
−
600
nA
Vi≥ 0.97 x
VDDM V;
Vi≤ VDDM V;
overlayed= Yes
-500
−
100
nA
Vi≤ 0.03 x
VDDM V;
Vi≥ 0 V;
-600
−
100
nA
Vi≤ 0.03 x
VDDM V;
Vi≥ 0 V;
-100
−
200
nA
Vi> 0.03 x
VDDM V;
Vi< 0.97 x
VDDM V;
overlayed= No
overlayed= Yes
overlayed= No
-100
−
300
nA
Vi< 0.97 x
VDDM V;
Vi> 0.03 x
VDDM V;
overlayed= Yes
Input leakage current at
VAREF0 / VAREF2
IOZ2 CC -1
−
1
μA
Input leakage current at
-2
−
2
μA
IOZ3 CC -2
−
2
μA
RAIN CC −
900
1500
Ohm
VAREF1
Input leakage current at
VAGNDx
ON resistance of the
transmission gates in the
analog voltage path
Data Sheet
122
VAREFx≥ 0 V;
VAREFx≤ VDDM V
VAREFx≥ 0 V;
VAREFx≤ VDDM V
VAGNDx≥ 0 V;
VAGNDx≤ VDDM V
V 1.2, 2014-05
TC1793
Electrical ParametersDC Parameters
Table 24
ADC Parameters (cont’d)
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
ON resistance for the ADC RAIN7T
test (pull down for AIN7)
CC
180
550
900
Ohm
Resistance of the
reference voltage input
path
RAREF
CC
−
500
1000
Ohm
Sample time
tS CC
2
tCAL CC −
−
257
TADCI
−
4352
cycle
s
TUE CC -4
−
414)
LSB
Calibration time after bit
ADC_GLOBCFG.SUCAL
is set
Total Unadjusted
Error6)5)13)
Analog reference ground2) VAGND0
SR
Analog input voltage
VAIN SR VAGNDx −
VAGNDx −
Analog reference voltage2) VAREFx
SR
Analog reference voltage
range6)5)2)
VSSM - −
0.05
+1
Note /
Test Condition
ADC
resolution= 12bit
VAREFx V
-1
VAREFx V
VDDM + V
0.0515)
16)
VAREFx - VDDM/2 −
VAGNDx
VDDM + V
0.05
SR
1) The sampling capacity of the conversion C-network is pre-charged to VAREF/2 before the sampling moment.
Because of the parasitic elements the voltage measured at AINx can deviate from VAREF/2.
2) Applies to AINx, when used as auxiliary reference input.
3) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage
at once. Instead smaller capacitances are successively switched to the reference voltage.
4) The sum of DNL/INL/GAIN/OFF errors does not exceed the related TUE total unadjusted error.
5) If a reduced analog reference voltage between 1V and VDDM / 2 is used, then there are additional decrease in
the ADC speed and accuracy.
6) If the analog reference voltage range is below VDDM but still in the defined range of VDDM / 2 and VDDM is used,
then the ADC converter errors increase. If the reference voltage is reduced by the factor k (k<1),
TUE,DNL,INL,Gain, and Offset errors increase also by the factor 1/k.
7) If the analog reference voltage is > VDDM, then the ADC converter errors increase.
8) For 10-bit conversions the error value must be multiplied with a factor 0.25.
9) For 8-bit conversions the error value must be multiplied with a factor 0.0625.
10) For fADCI between 18MHz and 20MHz the TUE and Gain Error can increase beyond the given limits. For
STC < 2 INL, DNL , and Offset errors can also increase.
Data Sheet
123
V 1.2, 2014-05
TC1793
Electrical ParametersDC Parameters
11) For a conversion time of 1 µs a rms value of 85µA result for IAREF0.
12) The leakage current definition is a continuos function, as shown in figure ADCx Analoge Input Leakage. The
numerical values defined determine the characteristic points of the given continuous linear approximation they do not define step function.
13) Measured without noise.
14) For 10-bit conversion the TUE is ±2LSB; for 8-bit conversion the TUE is ±1LSB
15) A running conversion may become inexact in case of violating the normal conditions (voltage overshoot).
16) If the reference voltage VAREF increase or the VDDM decrease, so that VAREF = (VDDM + 0.05V to VDDM + 0.07V),
then the accuracy of the ADC decrease by 4LSB12.
Table 25
Conversion Time (Operating Conditions apply)
Parameter
Symbol Values
Conversion
tC
time with
post-calibration
Unit Note
CC 2 × TADC + (4 + STC + n) × TADCI μs
2 × TADC + (2 + STC + n) × TADCI
Conversion
time without
post-calibration
n = 8, 10, 12 for
n - bit conversion
TADC = 1 / fFPI
TADCI = 1 / fADCI
The power-up calibration of the ADC requires a maximum number of 4352 fADCI cycles.
REXT
VAIN =
Analog Input Circuitry
RAIN, On
ANx
CEXT
CAINTOT - CAINSW
VAGNDx
CAINSW
RAIN7T
Reference Voltage Input Circuitry
RAREF, On
VAREFx
VAREF
CAREFTOT - CAREFSW
CAREFSW
VAGNDx
Analog_InpRefDiag
Figure 6
Data Sheet
ADCx Input Circuits
124
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Electrical ParametersDC Parameters
Ioz1
Single ADC Input
500nA
200nA
100nA
-100nA
VIN[VDDM%]
3%
97% 100%
-500nA
Ioz1
Overlayed ADC/FADC Input
600nA
300nA
100nA
-100nA
VIN[VDDM%]
3%
97% 100%
-600nA
Figure 7
Data Sheet
ADCx Analog Inputs Leakage
125
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Electrical ParametersDC Parameters
5.2.3
Fast Analog to Digital Converter (FADC)
FADC parameter are vaild for VDD / DDAF = 1.235 V to 1.365 V; VDDMF = 2.97 V to 3.6 V.
Table 26
FADC Parameters
Parameter
Input current at VFAREF
Symbol
Values
Unit
Min.
Typ.
Max.
IFAREF
−
−
120
μA
IFOZ2
-500
−
500
nA
IFOZ3
-500
−
500
nA
EFDNL
-1
−
1
LSB
Note /
Test Condition
CC
Input leakage current at
VFAREF1)
CC
Input leakage current at
VFAGND
CC
DNL error
CC
VFAREF≤ VDDMF
V; VFAREF≥ 0 V
VIN mode=
differential;
Gain = 1 or 2
−
-2
2
LSB
VIN mode=
differential;
Gain = 4 or 82)
−
-1
1
LSB
VIN mode=
single ended;
Gain = 1 or 2
−
-2
2
LSB
VIN mode=
single ended;
Gain = 4 or 82)
GRADient error
EFGRAD -5
−
-5
−
5
%
CC
VIN mode=
differential ;
Gain≤ 4
5
%
VIN mode=
single ended ;
Gain≤ 4
−
-6
6
%
VIN mode=
differential ;
Gain= 8
−
-6
6
%
VIN mode=
single ended ;
Gain= 8
Data Sheet
126
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TC1793
Electrical ParametersDC Parameters
Table 26
FADC Parameters (cont’d)
Parameter
INL error
Symbol
EFINL
Values
Unit
Note /
Test Condition
4
LSB
VIN mode=
4
LSB
VIN mode=
Min.
Typ.
Max.
-4
−
-4
−
CC
differential
single ended
Offset error
EFOFF
−
-90
90
mV
CC
VIN mode=
differential ;
Calibration= No
−
-90
90
mV
VIN mode=
single ended ;
Calibration= No
−
-20
20
mV
VIN mode=
differential ;
Calibration= Ye
s 3)4)
−
-20
20
mV
VIN mode=
single ended ;
Calibration= Ye
s 3)4)
EFREF
-60
−
60
mV
Channel amplifier cutoff
frequency
fCOFF
2
−
−
MHz
Converter clock
fFADC
1
−
100
MHz fFADC= fFPI
tC CC
−
−
21
1/
Input resistance of the
analog voltage path (Rn,
Rp)
RFAIN
100
Settling time of a channel
amplifier after changing
ENN or ENP
tSET CC −
Analog input voltage
range
VAINF
Error of commen mode
voltage VFAREF/2
CC
CC
SR
Conversion time
Data Sheet
−
200
kOh
m
−
5
μs
VDDMF
V
CC
SR
For 10-bit
fFADC conversion
VFAGND −
127
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TC1793
Electrical ParametersDC Parameters
Table 26
FADC Parameters (cont’d)
Parameter
Symbol
Values
Min.
Analog reference ground
VFAGND
VSSAF - −
VFAREF
3.0
SR
Analog reference voltage
Typ.
0.05
−
SR
Unit
Max.
VSSAF
V
3.635)
V
Note /
Test Condition
+ 0.05
6)
1) This value applies in power-down mode.
2) No missing codes.
3) Calibration should be preformed at each power-up. In case of a continous operation, it should be performed
minimium once per week.
4) The offser error voltage drifts over the whole temperature range maximum +-3LSB.
5) Voltage overshoot to 4V is permissible, provided the pulse duration is less than 100 μs and the cumulated sum
of the pulses does not exceed 1 h.
6) A running conversion may become inexact in case of violating the nomal operating conditions (voltage
overshoots).
The calibration procedure should run after each power-up, when all power supply
voltages and the reference voltage have stabilized.
Data Sheet
128
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TC1793
Electrical ParametersDC Parameters
FADC Analog Input Stage
FAINxN
-
=
VFAGND
RN
VFAREF /2
+
+
FAINxP
RP
-
FADC Reference Voltage
Input Circuitry
VFAREF
IFAREF
VFAREF
VFAGND
FADC_InpRefDiag
Figure 8
Data Sheet
FADC Input Circuits
129
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TC1793
Electrical ParametersDC Parameters
5.2.4
Table 27
Oscillator Pins
OSC_XTAL Parameters
Parameter
Symbol
Values
Unit
Note /
Test Condition
VIN<VDDOSC3 ;
VIN>0 V
Min.
Typ.
Max.
-25
−
25
μA
Input current at XTAL1
IIX1 CC
Input frequency
fOSC SR 4
−
40
MHz Direct Input
Mode selected
8
−
25
MHz External Crystal
Mode selected
−
−
10
ms
VDDOS
V
Oscillator start-up time1)
tOSCS
CC
Input high voltage at
XTAL12)
VIHX SR 0.7 x
VDDOS
Input low voltage at
XTAL1
VILX SR -0.5
Input Hysteresis for
XTAL1 pad 3)
HYSAX
−
+
0.5
C3
C3
−
0.3 x
V
VDDOS
C3
−
−
200
mV
CC
1) tOSCS is defined from the moment when VDDOSC3 = 3.13V until the oscillations reach an amplitude at XTAL1 of
0.3 * VDDOSC3. The external oscillator circuitry must be optimized by the customer and checked for negative
resistance as recommended and specified by crystral suppliers.
2) If the XTAL1 pin is driven by a crystal, reaching a minimum amplitude (peak-to-peak) of 0.4 * VDDOSC3 is
necessary.
3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be
guaranteed that it suppresses switching due to external system noise.
Note: It is strongly recommended to measure the oscillation allowance (negative
resistance) in the final target system (layout) to determine the optimal parameters
for the oscillator operation. Please refer to the limits specified by the crystal or
ceramic resonator supplier.
Data Sheet
130
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TC1793
Electrical ParametersDC Parameters
5.2.5
Table 28
Temperature Sensor
DTS Parameters
Parameter
Symbol
Values
Min.
Measurement time
Temperature sensor
range
tM CC
TSR SR
Unit
Typ.
Max.
−
−
100
μs
-40
−
150
°C
Sensor Accuracy
(calibrated)
TTSA CC -6
−
6
°C
Start-up time after resets
inactive
tTSST SR −
−
20
μs
Note /
Test Condition
The following formula calculates the temperature measured by the DTS in [oC] from the
RESULT bit field of the DTSSTAT register.
(1)
DTSSTAT RESULT – 596
Tj = ------------------------------------------------------------------2, 03
Data Sheet
131
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TC1793
Electrical ParametersDC Parameters
5.2.6
Power Supply Current
The total power supply current defined below consists of leakage and switching
component.
Application relevant values are typically lower than those given in the following two
tables and depend on the customer's system operating conditions (e.g. thermal
connection or used application configurations).
The operating conditions for the parameters in the following table are:
VDD / VDDOSC / VDDAF / VDDPF = 1.365 V,
VDDM = 5.25 V
VDDP / VDDOSC / VDDMF / VDDFL3 / VDDPF = 3.47 V,
fSRI / CPU=270 / 200 MHz, fPCP=180 / 200 MHz, fSRI=90 / 100 MHz, TJ=150 oC
The realisic power pattern defines the following conditions:
•
•
•
•
•
•
•
TJ=150 oC
fSRI = fCPU = 270 / 200 MHz
fPCP = 180 / 200 MHz
fFPI = 90 / 100MHz
VDD = VDDOSC = VDDAF = VDDPF = 1.326 V
VDDP = VDDOSC3 = VDDFL3 VDDPF3 = VDDMF = 3.366 V
VDDM = 5.1 V
The max power pattern defines the following conditions:
•
•
•
•
•
•
•
TJ=150 oC
fSRI = fCPU = 270 / 200 MHz
fPCP = 180 / 200 MHz
fFPI = 90 / 100MHz
VDD = VDDOSC = VDDAF = VDDPF = 1.43 V
VDDP = VDDOSC3 = VDDFL3 VDDPF3 = VDDMF = 3.63 V
VDDM = 5.5 V
Data Sheet
132
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Electrical ParametersDC Parameters
Table 29
Power Supply Parameters
Parameter
Unit
Note /
Test Condition
8403)
mA
power
pattern= max;
fCPU=270 MHz
−
621
mA
power
pattern= realisti
c;
fCPU=270 MHz
−
−
7354)
mA
power
pattern= max;
fCPU=200 MHz
−
−
555
mA
power
pattern= realisti
c;
fCPU=200 MHz
IDD current at PORST Low IDD_PORS −
T CC
−
−
298
mA
TJ=150 oC
−
249
mA
TJ=140 oC
Core active mode supply
current1)2)
Symbol
IDD CC
Values
Min.
Typ.
Max.
−
−
−
E-Ray PLL core supply
current
IDDPF
−
−
4
mA
Oscillator core supply
current
IDDOSC
−
−
3
mA
Analog core supply
current
IDDAF
−
−
26
mA
Sum of all 1.3 V supply
currents
IDDSUM
−
−
654
mA
power
pattern= realisti
c;
fCPU=270 MHz
−
−
588
mA
power
pattern= realisti
c;
fCPU=200 MHz
IDDPF3
−
−
4
mA
IDDOSC3
−
−
11
mA
E-Ray PLL 3.3V supply
CC
CC
CC
CC
CC
Oscillator power supply
current, 3.3V
Data Sheet
CC
133
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TC1793
Electrical ParametersDC Parameters
Table 29
Power Supply Parameters (cont’d)
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
Note /
Test Condition
FADC analog supply
current, 3.3V
IDDMF
−
−
15
mA
IDDP current at PORST
IDDP_POR −
−
7
mA
−
IDDP_
mA
including flash
read current
mA
including flash
programming
current 6)
mA
including flash
erase verify
current 6)
CC
Low
ST
CC
IDDP CC −
IDDP current no pad
activity, LVDS off 5)
PORST
+ 25
−
−
IDDP_
PORST
+ 55
−
−
IDDP_
PORST
7)
+ 40
5)
−
−
98
mA
flash read
current
−
−
29
mA
flash
programming
current 6)
−
−
98
mA
flash erase
current 6)
ILVDS
−
−
24
mA
in total for all
LVDS pairs
Sum of all 3.3 V supply
currents, no pad activity,
LVDS off
IDD3SUM
−
−
160 8)
mA
including flash
read current
ADC 5V power supply
current
IDDM CC −
−
6
mA
Flash memory current
IDDFL3
CC
Current Consumption of
LVDS Pad Pairs
Data Sheet
CC
CC
134
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TC1793
Electrical ParametersDC Parameters
Table 29
Power Supply Parameters (cont’d)
Parameter
Symbol
Maximum power
dissipation
PD CC
Values
Unit
Note /
Test Condition
1633
mW
power
pattern= max;
fCPU=270 MHz
−
1488
mW
power
pattern= realisti
c;
fCPU=270 MHz
−
−
1523
mW
power
pattern= max;
fCPU=200 MHz
−
−
1403
mW
power
pattern= realisti
c;
fCPU=200 MHz
Min.
Typ.
Max.
−
−
−
1) Infineon Power Loop: CPU and PCP running, all peripherals active. The power consumption of each customer
application will most probably be lower than this value, but must be evaluated seperately.
2) This current includes the E-Ray module power consumption, including the PCP operation component.
3) The IDD decreases typically by 97 mA if the fCPU decreases by 50MHz, at constant TJ
4) The IDD decreases typically by 105 mA if the fCPU decreases by 50MHz, at constant TJ
5)
D-Flash read, write, or erase opoeration in parallel to P-Flash operations name in Test Condition is covered
already in the give current limits.
6) Relevant for the power supply dimensioning, not for thermal considerations.
7) In case of erase of Program Flash PFx, internal flash array loading effects may generate transient current
spikes of up to 15 mA for maximum 5 ms per flash module.
8) For power supply dimensioning of VDDP 30 mA have to added for flash programming case.
Note: In general current consumption for operations with data flash are always lower
than the defined values for program flash read operation.
5.2.6.1
Calculating the 1.3 V Current Consumption
The current consumption of the 1.3 V rail compose out of two parts:
•
•
Static current consumption
Dynamic current consumption
The static current consumption is related to the device temperature TJ and the dynamic
current consumption depends of the configured clocking frequencies and the software
Data Sheet
135
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TC1793
Electrical ParametersDC Parameters
application executed. These two parts needs to be added in order to get the rail current
consumption.
(2)
I
0
mA
= 3, 75 --------- × e 0, 02041 × T J [ C ]
C
(3)
I
0
mA
= 18, 77 --------- × e 0, 01825 × T J [ C ]
C
Function 2 defines the typical static current consumption and Function 3 defines the
maximum static current consumption. Both functions are valid for VDD = 1.326 V.
For the dynamic current consumption
= 3 / 2 * fPCP = 3 * fFPI the function 4 applies:
using
the
real
pattern
and
fSRI
(4)
mA
I D m = 1, 22 ------------- × f CPU [ MHz ]
y
MHz
For the dynamic current consumption using the real pattern and fSRI = fPCP = 2 * fFPI the
function 5 applies:
(5)
mA
I D m = 1, 305 ------------- × f CPU [ MHz ]
y
MHz
and this finally results in
(6)
I DD = I 0 + I DYM
Data Sheet
136
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TC1793
Electrical ParametersAC Parameters
5.3
AC Parameters
All AC parameters are defined with maximum driver strength unless otherwise noted.
5.3.1
Testing Waveforms
VD D P
90%
90%
10%
10%
VSS
tR
tF
rise_fall
Figure 9
Rise/Fall Time Parameters
VD D P
VD D E / 2
Test Points
VD D E / 2
VSS
mct04881_a.vsd
Figure 10
Testing Waveform, Output Delay
VLoad+ 0.1 V
VLoad- 0.1 V
Timing
Reference
Points
VOH - 0.1 V
VOL - 0.1 V
MCT04880_new
Figure 11
Data Sheet
Testing Waveform, Output High Impedance
137
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TC1793
Electrical ParametersAC Parameters
5.3.2
Power Sequencing
V
5.25V
5V
4.75V
VAREF
3.47V
3.3V
3.0V
-12%
1.365V
1.3V
1.235V
0.5V
-12%
0.5V
0.5V
t
VDDP
PORST
power
down
Figure 12
power
fail
t
Power-Up 10.vsd
5 V / 3.3 V / 1.3 V Power-Up/Down Sequence
The following list of rules applies to the power-up/down sequence:
•
•
•
All ground pins VSS must be externally connected to one single star point in the
system. Regarding the DC current component, all ground pins are internally directly
connected.
At any moment in time to avoid increased latch-up risk,
each power supply must be higher then any lower_power_supply - 0.5 V, or:
VDD5 > VDD3.3 - 0.5 V; VDD5 > VDD1.3 - 0.5 V;VDD3.3 > VDD1.3 - 0.5 V, see
Figure 12.
– The latch-up risk is minimized if the I/O currents are limited to:
– 20 mA for one pin group
– AND 100 mA for the completed device I/Os
– AND additionally before power-up / after power-down:
1 mA for one pin in inactive mode (0 V on all power supplies)
During power-up and power-down, the voltage difference between the power supply
pins of the same voltage (3.3 V, 1.3 V, and 5 V) with different names (for example
VDDP, VDDFL3 ...), that are internally connected via diodes, must be lower than
Data Sheet
138
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TC1793
Electrical ParametersAC Parameters
•
•
•
•
•
•
100 mV. On the other hand, all power supply pins with the same name (for example
all VDDP), are internally directly connected. It is recommended that the power pins
of the same voltage are driven by a single power supply.
The PORST signal may be deactivated after all VDD5, VDD3.3, VDD1.3, and VAREF
power-supplies and the oscillator have reached stable operation, within the normal
operating conditions.
At normal power down the PORST signal should be activated within the normal
operating range, and then the power supplies may be switched off. Care must be
taken that all Flash write or delete sequences have been completed.
At power fail the PORST signal must be activated at latest when any 3.3 V or 1.3 V
power supply voltage falls 12% below the nominal level. If, under these conditions,
the PORST is activated during a Flash write, only the memory row that was the target
of the write at the moment of the power loss will contain unreliable content. In order
to ensure clean power-down behavior, the PORST signal should be activated as
close as possible to the normal operating voltage range.
In case of a power-loss at any power-supply, all power supplies must be powereddown, conforming at the same time to the rules number 2 and 4.
Although not necessary, it is additionally recommended that all power supplies are
powered-up/down together in a controlled way, as tight to each other as possible.
Additionally, regarding the ADC reference voltage VAREF:
– VAREF must power-up at the same time or later then VDDM, and
– VAREF must power-down either earlier or at latest to satisfy the condition
VAREF < VDDM + 0.5 V. This is required in order to prevent discharge of VAREF
filter capacitance through the ESD diodes through the VDDM power supply. In
case of discharging the reference capacitance through the ESD diodes, the
current must be lower than 5 mA.
Data Sheet
139
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TC1793
Electrical ParametersAC Parameters
5.3.3
Table 30
Power, Pad and Reset Timing
Reset Timings Parameters
Parameter
Symbol
Values
Min.
Application Reset Boot
Time1)2)
tB CC
Power on Reset Boot
Time3)4)
tBP CC
Typ.
Unit
Note /
Test Condition
fCPU = 270 MHz
fCPU = 200 MHz
Max.
−
−
960
μs
−
−
1140
μs
−
−
2.5
ms
−
−
ns
−
−
ns
HWCFG pins hold time
from ESR0 rising edge
tHDH SR 16 /
fFPI
HWCFG pins setup time to tHDS SR 0
ESR0 rising edge
Ports inactive after ESR0
reset active
tPI CC
−
−
8/fFPI
ns
Ports inactive after
PORST reset active5)
tPIP CC
−
−
150
ns
Minimum PORST active
time after power supplies
are stable at operating
levels
tPOA SR 10
−
−
ms
TESTMODE / TRST hold
time from PORST rising
edge
tPOH SR 100
−
−
ns
PORST rise time
tPOR SR −
tPOS SR 0
−
50
ms
−
−
ns
−
40 6)
μs
TESTMODE / TRST
setup time to PORST
rising edge
Application Reset inactive tPOR_APP −
after PORST deassertion SR
1) The duration of the boot time is defined between the rising edge of the internal application reset and the clock
cycle when the first user instruction has entered the CPU pipeline and its processing starts.
2) The given time includes the time of the internal reset extension for a configured value of
SCU_RSTCNTCON.RELSA = 0x05BE.
3) The duration of the boot time is defined between the rising edge of the PORST and the clock cycle when the
first user instruction has entered the CPU pipeline and its processing starts.
Data Sheet
140
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Electrical ParametersAC Parameters
4) The given time includes the internal reset extension time for the System and Application Reset which is visible
through ESR0.
5) This parameter includes the delay of the analog spike filter in the PORST pad.
6) Application Reset is assumed not to be extended from external, otherwise the time extends by the time the
Application Reset is extended.
VDD P -12%
VD D PPA
V D DPPA
VDDP
VDD
VD D -12%
tPOA
tPOA
PORST
tPOH
TRST
TESTMODE
ESR0
tPOH
t hd
t hd
tHDH
tHDH
tHDH
HWCFG
t PIP
tPI
Pads
tPI
t PIP
tPI
tPI
t PIP
tPI
Pad-state undefined
Tri-state or pull device active
reset_beh2
As programmed
Figure 13
Data Sheet
Power, Pad and Reset Timing
141
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TC1793
Electrical ParametersAC Parameters
5.3.4
Table 31
Phase Locked Loop (PLL)
PLL_SysClk Parameters
Parameter
Symbol
Values
Min.
Accumulated Jitter
Modulation frequency
PLL base frequency
DP CC -7
fMOD SR 50
fPLLBASE 50
Unit
Typ.
Max.
−
7
Note /
Test Condition
ns
−
200
kHz
200
320
MHz
fREF CC 8
fVCO CC 400
−
16
MHz
−
720
MHz with inactive
modulation
400
−
600
MHz with active
modulation
−
2.5
ns
−
9.5
ns
CC
VCO input frequency
VCO frequency range
Modulation jitter
Total long term jitter
JMOD CC −
JTOT CC −
Sum of DP and
JMOD
Modulation Amplitude
PLL lock-in time
System frequency
deviation
MA SR
tL CC
fSYSD
−
0
2.5
%
% of fVCO
14
−
200
μs
N > 32
14
−
400
μs
N ≤ 32
−
−
0.01
%
with active
modulation
CC
Phase Locked Loop Operation
When PLL operation is enabled and configured, the PLL clock fVCO (and with it the SRIBus clock fSRI) is constantly adjusted to the selected frequency. The PLL is constantly
adjusting its output frequency to correspond to the input frequency (from crystal or clock
source), resulting in an accumulated jitter that is limited. This means that the relative
deviation for periods of more than one clock cycle is lower than for a single clock cycle.
This is especially important for bus cycles using wait states and for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
Data Sheet
142
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Electrical ParametersAC Parameters
Two formulas are defined for the (absolute) approximate maximum value of jitter Dm in
[ns] dependent on the K2 - factor, the SRI clock frequency fSRI in [MHz], and the number
m of consecutive fSRI clock periods.
for
( K2 ≤ 100 )
( m ≤ ( f SRI [ MHz ] ) ⁄ 2 )
and
( 1 – 0, 01 × K2 ) × ( m – 1 )
740
D m [ ns ] = ⎛⎝ ------------------------------------------ + 5⎞⎠ × ⎛⎝ ---------------------------------------------------------------- + 0, 01 × K2⎞⎠
0, 5 × f SRI [ MHz ] – 1
K2 × f SRI [ MHz ]
else
740
D m [ ns ] = ------------------------------------------ + 5
K2 × f SRI [ MHz ]
(7)
(8)
With rising number m of clock cycles the maximum jitter increases linearly up to a value
of m that is defined by the K2-factor of the PLL. Beyond this value of m the maximum
accumulated jitter remains at a constant value. Further, a lower SRI-Bus clock frequency
fSRI results in a higher absolute maximum jitter value.
Note: The specified PLL jitter values are valid if the capacitive load per pin does not
exceed CL = 20 pF with the maximum driver and sharp edge.
Note: The maximum peak-to-peak noise on the pad supply voltage, measured between
VDDOSC3 and VSSOSC, is limited to a peak-to-peak voltage of VPP = 100 mV for noise
frequencies below 300 KHz and VPP = 40 mV for noise frequencies above
300 KHz.
The maximum peak-to peak noise on the pad supply voltage, measured between
VDDOSC and VSSOSC, is limited to a peak-to-peak voltage of VPP = 100 mV for noise
frequencies below 300 KHz and VPP = 40 mV for noise frequencies above
300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage
as near as possible to the supply pins and using PCB supply and ground planes.
Oscillator Watchdog (OSC_WDT)
The expected input frequency is selected via the bit field SCU_OSCCON.OSCVAL. The
OSC_WDT checks for too low frequencies and for too high frequencies.
The frequency that is monitored is fOSCREF which is derived for fOSC.
(9)
f O S C R EF
fO S C
= ---------------------------------OSCVAL + 1
The divider value SCU_OSCCON.OSCVAL has to be selected in a way that fOSCREF is
2.5 MHz.
Data Sheet
143
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TC1793
Electrical ParametersAC Parameters
Note: fOSCREF has to be within the range of 2 MHz to 3 MHz and should be as close as
possible to 2.5 MHz.
The monitored frequency is too low if it is below 1.25 MHz and too high if it is above
7.5 MHz. This leads to the following two conditions:
•
•
Too low: fOSC < 1.25 MHz × (SCU_OSCCON.OSCVAL+1)
Too high: fOSC > 7.5 MHz × (SCU_OSCCON.OSCVAL+1)
Note: The accuracy is 30% for these boundaries.
Frequency Modulation
Frequency modulation defines a slow and predictable variation of the clock speed. The
modulation configuration itself is controlled via register SCU_PLLCON2 where the two
bit fields define the modulation properties.
(10)
f OSC MODFREQ × 31, 32
f MOD = -------------- × ---------------------------------------------------P
MODAMP
(11)
MODAMP
MA = ----------------------------
N × 161
Data Sheet
144
V 1.2, 2014-05
TC1793
Electrical ParametersAC Parameters
5.3.5
Table 32
ERAY Phase Locked Loop (ERAY_PLL)
PLL_ERAY Parameters
Parameter
Symbol
Values
Min.
Unit
Typ.
Max.
Accumulated jitter at
SYSCLK pin
DPP CC -0.8
−
0.8
ns
Accumulated_Jitter
DP CC -0.5
fPLLBASE_ 50
−
0.5
ns
250
360
MHz
fREF CC 20
−
40
MHz
fVCO_ERA 450
−
500
MHz
−
200
μs
PLL Base Frequency of
the ERAY PLL
VCO input frequency of
the ERAY PLL
ERAY
Note /
Test Condition
CC
VCO frequency range of
the ERAY PLL
Y
PLL lock-in time
tL CC
CC
5.6
Note: The specified PLL jitter values are valid if the capacitive load per pin does not
exceed CL = 20 pF with the maximum driver and sharp edge.
Note: The maximum peak-to-peak noise on the pad supply voltage, measured between
VDDPF3 and VSSPF, is limited to a peak-to-peak voltage of VPP = 100 mV for noise
frequencies below 300 KHz and VPP = 40 mV for noise frequencies above
300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage
as near as possible to the supply pins and using PCB supply and ground planes.
Data Sheet
145
V 1.2, 2014-05
TC1793
Electrical ParametersAC Parameters
5.3.6
JTAG Interface Timing
The following parameters are applicable for communication through the JTAG debug
interface. The JTAG module is fully compliant with IEEE1149.1-2000.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Table 33
JTAG Interface Timing Parameters
(Operating Conditions apply)
Parameter
Min.
Typ.
Max.
Unit Note /
Test Condition
25
–
–
ns
–
10
–
–
ns
–
10
–
–
ns
–
–
–
4
ns
–
–
–
4
ns
–
6
–
–
ns
–
t7 SR
6
–
–
ns
–
TDO valid after TCK falling t8 CC
edge1) (propagation delay) t CC
8
–
–
13
ns
CL = 50 pF
3
–
–
ns
CL = 20 pF
TDO hold after TCK falling t18 CC
edge1)
2
–
–
ns
TDO high imped. to valid
from TCK falling edge1)2)
t9 CC
–
–
14
ns
CL = 50 pF
TDO valid to high imped.
from TCK falling edge1)
t10 CC
–
–
13.5
ns
CL = 50 pF
TCK clock period
TCK high time
TCK low time
TCK clock rise time
TCK clock fall time
TDI/TMS setup
to TCK rising edge
TDI/TMS hold
after TCK rising edge
Symbol
t1 SR
t2 SR
t3 SR
t4 SR
t5 SR
t6 SR
Values
1) The falling edge on TCK is used to generate the TDO timing.
2) The setup time for TDO is given implicitly by the TCK cycle time.
Data Sheet
146
V 1.2, 2014-05
TC1793
Electrical ParametersAC Parameters
t1
0.9 VD D P
0.5 VD D P
t5
t2
0.1 VD D P
t4
t3
MC_ JTAG_ TCK
Figure 14
Test Clock Timing (TCK)
TCK
t6
t7
t6
t7
TMS
TDI
t9
t8
t1 0
TDO
t18
Figure 15
Data Sheet
MC_JTAG
JTAG Timing
147
V 1.2, 2014-05
TC1793
Electrical ParametersAC Parameters
5.3.7
DAP Interface Timing
The following parameters are applicable for communication through the DAP debug
interface.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Table 34
DAP Parameters
Parameter
Symbol
1)
tTCK SR
t12 SR
t13 SR
t14 SR
t15 SR
t16 SR
DAP0 clock period
DAP0 high time
1)
DAP0 low time
DAP0 clock rise time
DAP0 clock fall time
DAP1 setup to DAP0
rising edge
Values
Unit
Min.
Typ.
Max.
12.5
−
−
ns
4
−
−
ns
4
−
−
ns
−
−
2
ns
−
−
2
ns
6.0
−
−
ns
DAP1 hold after DAP0
rising edge
t17 SR
6.0
−
−
ns
DAP1 valid per DAP0
clock period2)
t19 CC
8
−
−
ns
10
−
−
ns
Note /
Test Condition
CL= 20 pF;
f= 80 MHz
CL= 50 pF;
f= 40 MHz
1) See the DAP chapter for clock rate restrictions in the Active:IDLE protocol state.
2) The Host has to find a suitable sampling point by analyzing the sync telegram response.
t11
0.9 VD D P
0.5 VD D P
t1 5
t1 2
t14
0.1 VD D P
t1 3
MC_DAP0
Figure 16
Data Sheet
Test Clock Timing (DAP0)
148
V 1.2, 2014-05
TC1793
Electrical ParametersAC Parameters
DAP0
t1 6
t1 7
DAP1
MC_ DAP1_RX
Figure 17
DAP Timing Host to Device
t1 1
DAP1
t1 9
MC_ DAP1_TX
Figure 18
5.3.8
Data Sheet
DAP Timing Device to Host
Micro Link Interface (MLI) Timing
149
V 1.2, 2014-05
TC1793
Electrical ParametersAC Parameters
MLI Transmitter Timing
t13
t14
t10
t12
TCLKx
t11
t15
t15
TDATAx
TVALIDx
t16
t17
TREADYx
MLI Receiver Timing
t23
t24
t20
RCLKx
t22
t21
t25
t26
RDATAx
RVALIDx
t27
t27
RREADYx
MLI_Tmg_2.vsd
Figure 19
MLI Interface Timing
Note: The generation of RREADYx is in the input clock domain of the receiver. The
reception of TREADYx is asynchronous to TCLKx.
The MLI parameters are vaild for CL = 50 pF and strong driver medium edge.
Data Sheet
150
V 1.2, 2014-05
TC1793
Electrical ParametersAC Parameters
Table 35
MLI Receiver
Parameter
Symbol
Values
Unit
Min.
Typ.
1 / fFPI
−
−
ns
−
0.5 x
−
ns
−
ns
−
4
ns
−
−
4
ns
4.2
−
−
ns
RDATA/RVALID hold time t26 SR
after RCLK falling edge
2.2
−
−
ns
RREADY output delay
time
0
−
16
ns
RCLK clock period
RCLK high time1)2)
t20 SR
t21 SR
Max.
Note /
Test Condition
t20
RCLK low time1)2)
t22 SR
−
0.5 x
t20
RCLK rise time3)
RCLK fall time
3)
RDATA/RVALID setup
time before RCLK falling
edge
t23 SR
t24 SR
t25 SR
t27 SR
−
1) The following formula is valid: t21 + t22 = t20.
2) Min and Max values for this parameter can be derived from the typ. value by considering the other receiver
timing parameters.
3) The RCLK max. input rise/fall times are best case parameters for fSYS = 90 MHz. For reduction of EMI, slower
input signal rise/fall times can be used for longer RCLK clock periods.
Table 36
MLI Transmitter
Parameter
TCLK clock period
Symbol
t10 CC
Values
Unit
Min.
Typ.
Max.
2x1/
−
−
ns
0.45 x
0.5 x
0.55 x
ns
t10
t10
t10
0.45 x
0.5 x
0.55 x
t10
t10
t10
Note /
Test Condition
fFPI
TCLK high time1)2)
TCLK low time1)2)
t11 CC
t12 CC
ns
TCLK rise time
t13 CC
−
−
0.3 x
ns
TCLK fall time
t14 CC
−
−
0.3 x
ns
Data Sheet
151
t103)
t103)
V 1.2, 2014-05
TC1793
Electrical ParametersAC Parameters
MLI Transmitter (cont’d)
Table 36
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
TDATA/TVALID output
delay time
t15 CC
-3
−
4.4
ns
TREADY setup time
before TCLK rising edge
t16 SR
18
−
−
ns
TREADY hold time after
TCLK rising edge
t17 SR
-2
−
−
ns
Note /
Test Condition
1) The following formula is valid: t11 + t12 = t10.
2) The min./max. TCLK low/high times t11/t12 include the PLL jitter of fSYS. Fractional divider settings must be
regarded additionally to t11 / t12.
3) For high-speed MLI interface, strong driver sharp or medium edge selection (class A2 pad) is recommended
for TCLK.
5.3.9
Micro Second Channel (MSC) Interface Timing
The MSC parameters are vaild for CL = 50 pF.
Table 37
MSC Parameters
Parameter
Symbol
FCLP clock period1)2)
t40 CC
SOP4)/ENx outputs delay
from FCLP4) rising edge
t45 CC
SDI bit time
t46 CC
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
2x
−
−
ns
-2
−
5
ns
ENx with strong
driver and
sharp (minus )
edge
-2
−
10
ns
ENx with strong
driver and
medium
(minus) edge
0
−
21
ns
ENx with strong
driver and soft
edge
8x
−
−
ns
TMSC3)
TMSC
Data Sheet
152
V 1.2, 2014-05
TC1793
Electrical ParametersAC Parameters
Table 37
MSC Parameters (cont’d)
Parameter
Symbol
t48 SR
t49 SR
SDI rise time
SDI fall time
Values
Unit
Min.
Typ.
Max.
−
−
200
ns
−
−
200
ns
Note /
Test Condition
1) FCLP signal rise/fall times are only defined by the pad rise/fall times.
2) FCLP signal high and low can be minimum 1xTMSC
3) TMSC = TSYS = 1 / fSYS.
4) SOP / FCLP either propagated by LVDS or by CMOS strong driver and non soft edge.
t40
0.9 VDDP
0.1 VDDP
FCLP
t45
t45
SOP
EN
t48
t49
0.9 VDDP
0.1 VDDP
SDI
t46
Figure 20
t46
MSC_Tmg_1.vsd
MSC Interface Timing
Note: The data at SOP should be sampled with the falling edge of FCLP in the target
device.
Data Sheet
153
V 1.2, 2014-05
TC1793
Electrical ParametersAC Parameters
5.3.10
SSC Master/Slave Mode Timing
The SSC parameters are vaild for CL = 50 pF and strong driver medium edge.
Table 38
SSC Parameters
Parameter
Symbol
1)2)3)
SCLK clock period
t50 CC
Values
Unit
Min.
Typ.
Max.
2x1/
−
−
ns
Note /
Test Condition
fFPI
MTSR/SLSOx delay form
SCLK rising edge
t51 CC
0
−
8
ns
MRST setup to SCLK
latching edge3)
t52 SR
16.5
−
−
ns
MRST hold from SCLK
latching edge3)
t53 SR
0
−
−
ns
SCLK input clock
period1)3)
t54 SR
4x1/
−
−
ns
SCLK input clock duty
cycle
t55_t54
45
−
55
%
MTSR setup to SCLK
latching edge3)4)
t56 SR
1 / fFPI
−
−
ns
MTSR hold from SCLK
latching edge
t57 SR
1 / fFPI
+5
−
−
ns
SLSI setup to first SCLK
latching edge
t58 SR
1 / fFPI
+5
−
−
ns
SLSI hold from last SCLK t59 SR
latching edge5)
7
−
−
ns
MRST delay from SCLK
shift edge
t60 CC
0
−
16.5
ns
SLSI to valid data on
MRST
t61 CC
−
−
16.5
ns
fFPI
SR
1) SCLK signal rise/fall times are the same as the rise/fall times of the pad.
2) SCLK signal high and low times can be minimum 1xTSSC.
3) TSSCmin = TSYS = 1/fSYS.
4) Fractional divider switched off, SSC internal baud rate generation used.
Data Sheet
154
V 1.2, 2014-05
TC1793
Electrical ParametersAC Parameters
5) For CON.PH=1 slave select must not be removed before the following shifting edge. This mean, that what ever
is configured (shifting / latching first), SLSI must not be de-actived before the last trailing edge from the pair
of shifting / latching edges.
t50
SCLK1)2)
t51
t51
MTSR1)
t52
t53
Data
valid
1)
MRST
t51
2)
SLSOn
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
2) The transition at SLSOn is based on the following setup: SSOTC.TRAIL = 0
and the first SCLK high pulse is in the first one of a transmission.
SSC_TmgMM
Figure 21
Data Sheet
SSC Master Mode Timing
155
V 1.2, 2014-05
TC1793
Electrical ParametersAC Parameters
t54
First latching
SCLK edge
First shift
SCLK edge
SCLK1)
t55
t56
Last latching
SCLK edge
t55
t56
t57
Data
valid
1)
MTSR
t57
Data
valid
t60
t60
1)
MRST
t61
SLSI
t59
t58
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
Figure 22
Data Sheet
SSC_TmgSM
SSC Slave Mode Timing
156
V 1.2, 2014-05
TC1793
Electrical ParametersAC Parameters
5.3.11
ERAY Interface Timing
The timings of this section are valid for the strong driver and either sharp edge or medium
edge settings of the output drivers with CL = 25 pF.
The ERAY interface is only available for the SAK-TC1793F-512F270EF / SAKTC1793F-512F270EB / SAK-TC1793F-512F200EF / SAK-TC1793F512F200EB / SAK-TC1793S-512F270EF.
Table 39
ERAY Parameters
Parameter
Symbol
Values
Time span from last BSS
to FES without the
influence of quartz
tolerancies (d10Bit_TX)1)
t60 CC
997.75 −
1002.2 ns
5
TxD data valid from
fsample flip flop txd_reg
TxDA, TxDB
(dTxAsym)2)3)
t61-t62
−
−
1.5
Time span between last
BSS and FES without
influence of quartz
tolerancies
(d10Bit_RX)1)4)5)
t63 SR
966
−
1046.1 ns
RxD capture by fsample
(RxDA/RxDB sampling
flip-flop) (dRxAsym)6)
t64-t65
−
−
3.0
ns
Asymmetrical
delay of rising
and falling edge
(RxDA, RxDB)
TxD data delay from
sampling flip-flop
dTxdly
−
−
10.0
ns
Px_PDR.PDy =
000B
−
−
15.0
ns
Px_PDR.PDy =
001B
−
−
10.0
ns
Min.
RxD capture delay by
sampling flip-flop
Typ.
Unit
Max.
ns
CC
CC
CC
dRxdly
Note /
Test Condition
Asymmetrical
delay of rising
and falling edge
(TxDA, TxDB)
CC
1) This includes the PLL_ERAY accumulated jitter.
2) Refers to delays caused by the asymmetries of the output drivers of the digital logic and the GPIO pad drivers.
Quarz tolerance and PLL_ERAY accumulated jitter are not included.
3) E-Ray TxD output drivers have an asymmetry of rising and falling edges of |tFA2 - tRA2| ≤ 1 ns.
4) Limits of 966ns and 1046.1ns correspond to (30%, 70%) * VDDP FlexRay standard input thresholds. For input
thresholds of this product, a correction of - 0.5 ns and +0.1 ns has to be applied.
Data Sheet
157
V 1.2, 2014-05
TC1793
Electrical ParametersAC Parameters
5) Valid for output slopes of the bus driver of dRxSlope ≤ 5ns, 20% * VDDP to 80% * VDDP, according to the
FlexRay Electrical Physical Layer Specification V2.1B. For A2 pads, the rise and fall times of the incoming
signal have to satisfy the following inequality: -1.6ns ≤ tFA2 - tRA2 ≤ 1.3ns.
6) Valid for output slopes of the bus driver of dRxSlope ≤ 5ns, 20% * VDDP to 80% * VDDP, according to the
FlexRay Electrical Physical Layer Specification V2.1B. For A2 pads, the rise and fall times of the incoming
signal have to satisfy the following inequality: -1.6ns ≤ tFA2 - tRA2 ≤ 1.3ns.
Last CRC Byte
BSS
(Byte Start Sequence)
FES
(Frame End Sequence)
0.7 VDD
0.3 VDD
TXD
t60
tsample
TXD
0.9 VDD
0.1 VDD
t61
t62
Last CRC Byte
BSS
(Byte Start Sequence)
FES
(Frame End Sequence)
0.7 VDD
0.3 VDD
RXD
t63
tsample
RXD
0.7 VDD
0.3 VDD
t64
t65
ERAY_TIMING
Figure 23
Data Sheet
ERAY Timing
158
V 1.2, 2014-05
TC1793
Electrical ParametersAC Parameters
5.3.12
EBU Timings
5.3.12.1 BFCLKO Output Clock Timing
VSS = 0 V;VDD = 1.3 V ± 5%; VDDEBU = 2.5 V ± 5% and 3.3 V ± 5%,;
CL = 35 pF
BFCLK0 Output Clock Timing Parameters1)
Table 40
Parameter
Symbol
Values
Max.
Unit Note /
Test Con
dition
13.332) –
–
ns
–
3
–
–
ns
–
3
–
–
ns
–
–
–
3
ns
–
Min.
BFCLKO clock period
BFCLKO high time
BFCLKO low time
BFCLKO rise time
BFCLKO fall time
BFCLKO duty cycle t5/(t5 + t6)3)
tBFCLKO CC
t5
CC
t6
CC
t7
CC
t8
CC
DC
Typ.
–
–
3
ns
–
35
50
55
%
–
1) Not subject to production test, verified by design/characterization.
2) The PLL jitter characteristics add to this value according to the application settings. See the PLL jitter
parameters.
3) The PLL jitter is not included in this parameter. If the BFCLKO frequency is equal to fCPU, the K divider has to
be regarded.
tBFCLKO
BFCLKO
0.5 VDDP05
t5
t6
t8
t7
0.9 VDD
0.1 VDD
MCT04883_mod
Figure 24
BFCLKO Output Clock Timing
5.3.12.2 EBU Asynchronous Timings
VSS = 0 V;VDD = 1.3 V ± 5%; VDDEBU = 2.5 V ± 5% and 3.3 V ± 5%, Class B pins;
CL = 35 pF for address/data; CL = 40pF for the control lines.
For each timing, the accumulated PLL jitter of the programed duration in number of clock
periods must be added separately. Operating conditions apply and CL = 35 pF.
Data Sheet
159
V 1.2, 2014-05
TC1793
Electrical ParametersAC Parameters
Table 41
EBU Common Asynchronous Timings
Parameter
Symbol
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
Pulse wdih deviation from ta CC
the ideal programmed
width due to B pad
asymmetry, rise delay - fall
delay1)
-0.8
−
0.8
ns
edge= medium
-0.8
−
0.8
ns
edge= sharp
AD(31:0) output delay to
ADV# rising edge,
multiplexed read / write1)
t13 CC
-5.5
−
2
ns
AD(31:0) output delay to
ADV# rising edge,
multiplexed read / write1)
t14 CC
-5.5
−
2
ns
Address valid to CS falling t15 CC
edge (deviation from
programmed value)1)
-2
−
2
ns
Address valid to ADV
t16 CC
falling edge (deviation
from programmed value)1)
-2
−
2
ns
t17 CC
-2
−
2
ns
ADV falling edge
-> CSfalling edge
(deviation from
programmed value)1)
1) Not subject to production test, verified by design/characterization.
Data Sheet
160
V 1.2, 2014-05
TC1793
Electrical ParametersAC Parameters
Table 42
Parameter
EBU Asynchronous Read Timings
Symbol
Values
Unit
Min.
Typ.
Max.
A(23:0) output delay to RD t0 CC
rising edge, deviation from
the ideal programmed
value1)
-2.5
−
2.5
ns
A(23:0) output delay to RD t1 CC
rising edge, deviation from
the ideal programmed
value1)
-2.5
−
2.5
ns
CS rising edge to RD
t2 CC
rising edge, deviation from
the ideal programmed
value1)
-2
−
2.5
ns
ADV rising edge to RD
t3 CC
rising edge, deviation from
the ideal programmed
value1)
-1.5
−
4.5
ns
BC rising edge to RD
t4 CC
rising edge, deviation from
the ideal programmed
value1)
-2.5
−
2.5
ns
t5 SR
WAIT input setup to RD
rising edge, deviation from
the ideal programmed
value1)
12
−
−
ns
WAIT input hold to RD
t6 SR
rising edge, deviation from
the ideal programmed
value1)
0
−
−
ns
t7 SR
Data input setup to RD
rising edge, deviation from
the ideal programmed
value1)
12
−
−
ns
Data Sheet
161
Note /
Test Condition
V 1.2, 2014-05
TC1793
Electrical ParametersAC Parameters
Table 42
EBU Asynchronous Read Timings (cont’d)
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
Data input hold to RD
t8 SR
rising edge, deviation from
the ideal programmed
value1)
-2
−
−
ns
MR / W output delay to
t9 CC
RD# rising edge, deviation
from the ideal
programmed value1)
-2.5
−
1.5
ns
Data input hold from CS
rising edge1)
t18 CC
-2
−
−
ns
Data input setup to CS
rising edge1)
t19 CC
12
−
−
ns
Note /
Test Condition
1) Not subject to production test, verified by design/characterization.
Data Sheet
162
V 1.2, 2014-05
TC1793
Electrical ParametersAC Parameters
EBU
STATE
Address
Phase
Address Hold
Phase (opt.)
Command
Delay Phase
Command
Phase
Recovery
Phase (opt.)
New Addr.
Phase
Control Bitfield:
ADDRC
AHOLDC
CMDDELAY
RDWAIT
RDRECOVC
ADDRC
1...15
0...15
0...7
1...31
Duration Limits in
EBU_CLK Cycles
0...15
1...15
Next
Addr.
Valid Address
A[23:0]
pv + t0
pv + ta
CS[3:0]
CSCOMB
pv + ta
pv +
pv +
t1
t2
t3
ADV
pv +
ta
RD
pv +
ta
pv +
ta
t4
BC[3:0]
pv +
t5
t6
WAIT
pv +
AD[31:0]
MR/W
t13
pv +
t14
t7
Address Out
Data In
pv +
t9
pv = programmed value,
TEBU_CLK * sum (correponding bitfield values)
Figure 25
Data Sheet
t8
new_MuxRD_Async_10.vsd
Multiplexed Read Access
163
V 1.2, 2014-05
TC1793
Electrical ParametersAC Parameters
EBU
STATE
Control Bitfield:
Duration Limits in
EBU_CLK Cycles
Address
Phase
Address Hold
Phase (opt.)
Command
Phase
Recovery
Phase (opt.)
New Addr.
Phase
ADDRC
AHOLDC
RDWAIT
RDRECOVC
ADDRC
1...15
0...15
1...31
0...15
Next
Addr.
Valid Address
A[23:0]
pv +
pv + t1
t0
pv +
CS[3:0]
CSCOMB
pv +
1...15
t2
ta
pv + t3
ta
ADV
pv +
ta
RD
pv +
ta
pv + ta
t4
BC[3:0]
pv +
t5
t6
WAIT
t7
AD[31:0]
Data In
MR/W
pv +
pv = programmed value,
TEBU_CLK * sum (correponding bitfield values)
Figure 26
Data Sheet
t8
t9
new_DemuxRD_Async_10.vsd
Demultiplexed Read Access
164
V 1.2, 2014-05
TC1793
Electrical ParametersAC Parameters
Table 43
EBU Asynchnronous Write Timings
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
t30 CC
A(23:0) output delay to
WR rising edge, deviation
from the ideal
programmed value1)
-2.5
−
2.5
ns
A(23:0) output delay to
t31 CC
WR rising edge, deviation
from the ideal
programmed value1)
-2.5
−
2.5
ns
CS rising edge to WR
t32 CC
rising edge, deviation from
the ideal programmed
value1)
-2
−
2
ns
ADV rising edge to WR
t33 CC
rising edge, deviation from
the ideal programmed
value1)
-2.5
−
2
ns
BC rising edge to WR
t34 CC
rising edge, deviation from
the ideal programmed
value1)
-2.5
−
2
ns
WAIT input setup to WR t35 SR
rising edge, deviation from
the ideal programmed
value1)
12
−
−
ns
WAIT input hold to WR
t36 SR
rising edge, deviation from
the ideal programmed
value1)
0
−
−
ns
-5.5
−
2
ns
Data output delay to WR
falling edge, deviation
from the ideal
programmed value1)
Data Sheet
t37 CC
165
Note /
Test Condition
V 1.2, 2014-05
TC1793
Electrical ParametersAC Parameters
Table 43
Parameter
EBU Asynchnronous Write Timings (cont’d)
Symbol
Values
Unit
Min.
Typ.
Max.
Data output delay to WR t38 CC
rising edge, deviation from
the ideal programmed
value1)
-5.5
−
2
ns
MR / W output delay to
t39 CC
WR rising edge, deviation
from the ideal
programmed value1)
-2.5
−
1.5
ns
Note /
Test Condition
1) Not subject to production test, verified by design/characterization.
Data Sheet
166
V 1.2, 2014-05
TC1793
Electrical ParametersAC Parameters
EBU
STATE
Address
Phase
Address Hold
Phase (opt.)
Command
Phase
Data
Hold Phase
Recovery
Phase (opt.)
Control Bitfield:
ADDRC
AHOLDC
RDWAIT
DATAC
RDRECOVC
1...31
0...15
Duration Limits in
EBU_CLK Cycles
1...15
0...15
A[23:0]
0...15
pv + t30
pv +
ADDRC
1...15
Next
Addr.
Valid Address
CS[3:0]
CSCOMB
New Addr.
Phase
pv + t31
ta
pv + t32
pv + t33
pv + ta
ADV
pv +
ta
RD/WR
pv +
ta
pv + ta
BC[3:0]
t34
t35
WAIT
t36
t14
pv + t13
AD[31:0]
MR/W
pv + t37
pv + t38
Data Out
Address Out
pv + t39
pv = programmed value,
TEBU_CLK * sum (correponding bitfield values)
Figure 27
Data Sheet
new_MuxWR_Async_10.vsd
Multiplexed Write Access
167
V 1.2, 2014-05
TC1793
Electrical ParametersAC Parameters
EBU
STATE
Address
Phase
Control Bitfield:
ADDRC
Duration Limits in
EBU_CLK Cycles
1...15
Address Hold
Phase (opt.)
AHOLDC
0...15
A[23:0]
Command
Phase
Data
Hold Phase
RDWAIT
DATAC
1...31
0...15
Recovery
Phase (opt.)
RDRECOVC
0...15
New Addr.
Phase
ADDRC
1...15
Next
Addr.
Valid Address
pv + t30
pv +
CS[3:0]
CSCOMB
pv + t31
ta
pv + t32
pv + t33
pv + ta
ADV
pv +
ta
RD/WR
pv +
ta
pv + ta
BC[3:0]
t34
t35
WAIT
t36
pv + t37
AD[31:0]
MR/W
Data Out
pv + t39
pv = programmed value,
TEBU_CLK * sum (correponding bitfield values)
Figure 28
pv + t38
new_DemuxWR_Async_10.vsd
Demultiplexed Write Access
5.3.12.3 EBU Burst Mode Access Timing
VSS = 0 V;VDD = 1.3 V ± 5%; VDDEBU = 2.5 V ± 5% and 3.3 V ± 5%, Class B pins;
CL = 35 pF;
Data Sheet
168
V 1.2, 2014-05
TC1793
Electrical ParametersAC Parameters
Table 44
EBU Burst Read Timings
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
Output delay from
BFCLKO rising edge1)
t10 CC
-2
−
2
ns
RD and RD/WR
active/inactive after
BFCLKO active edge1)2)
t12 CC
-2
−
2
ns
CSx output delay from
BFCLKO active edge1)2)
t21 CC
-2.5
−
1.5
ns
ADV active/inactive after
BFCLKO active edge1)3)
t22 CC
-2
−
2
ns
BAA active/inactive after
BFCLKO active edge1)3)
t22a CC
-2.5
−
1.5
ns
Data setup to BFCLKI
rising edge1)
t23 SR
3
−
−
ns
Data hold from BFCLKI
rising edge1)
t24 SR
0
−
−
ns
WAIT setup (low or high)
to BFCLKI rising edge 1)
t25 SR
3
−
−
ns
WAIT hold (low or high)
t26 SR
from BFCLKI rising edge1)
0
−
−
ns
Note /
Test Condition
1) Not subject to production test, verified by design/characterization.
2) An active edge can be rising or falling edge, depending on the settings of bits BFCON.EBSE / ECSE and clock
divider ratio. Negative minimum values for these parameters mean that the last data read during a burst may
be corrupted. However, with clock feedback enabled, this value is oversampling not required for the LMB
transaction and will be discarded. If the clock feedback is not enabled, the input signals are latched using the
internal clock in the same way as at asynchronous access. So t14, t15, t16, t17, t18 and t19 from the
asynchronous timings apply.
3) For BUSCONx.EBSE=1B and BUSAPx.EXLCLK=00B, ADV will change normally on the clock edge so this
parameter is used directly.
For BUSCONx.EBSE=1B and other values of BUSAPx.EXTCLK, ADV and BAA add the high pulse width of
EBUCLK to this parameter.
For BUSCONx.EBSE=0B and BUSAPx.EXTCLK=00B add the high pulse width of EBUCLK to this parameter.
For BUSCONx.EBSE=0B and BUSAPx.EXTCLK=11B add two EBUCLK periodsto this parameter to get the
hold time from BFCLKO rising edge to the ADV.
For BUSCONx.EBSE=0B and BUSAPx.EXTCLK=01B or 10B add 1 EBUCLK period.
Please note that the high pulse width of EBUCLK is defined by the high pulse width of fVCO of the used PLL.
Data Sheet
169
V 1.2, 2014-05
TC1793
Electrical ParametersAC Parameters
Address
Phase(s)
BFCLKI
BFCLKO
Command
Phase(s)
Burst
Phase(s)
Burst
Phase(s)
Recovery
Phase(s)
Next Addr.
Phase(s)
1)
t10
t10
A[23:0]
Next
Addr.
Burst Start Address
t22
t22
t22
ADV
t21
t21
t21
CS[3:0]
CSCOMB
t12
t12
RD
RD/WR
t22a
t22a
BAA
t24
t23
D[31:0]
(32-Bit)
D[15:0]
(16-Bit)
t25
t24
t23
Data (Addr+0)
Data (Addr+4)
Data (Addr+0)
Data (Addr+2)
t26
WAIT
1)
Figure 29
Data Sheet
Output delays are always referenced to BCLKO. The reference clock for input
characteristics depends on bit EBU_BFCON.FDBKEN.
EBU_BFCON.FDBKEN = 0: BFCLKO is the input reference clock.
EBU_BFCON.FDBKEN = 1: BFCLKI is the input reference clock (EBU clock
feedback enabled).
BurstRDWR_4.vsd
EBU Burst Mode Read / Write Access Timing
170
V 1.2, 2014-05
TC1793
Electrical ParametersAC Parameters
5.3.12.4 EBU Arbitration Signal Timing
VSS = 0 V;VDD = 1.5 V ± 5%; VDDEBU = 2.5 V ± 5% and 3.3 V ± 5%, Class B pins;
TA = -40°C to +125 °C; CL = 35 pF;
Table 45
EBU EBU Arbitration Timings
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
Output delay from
BFCLKO rising edge1)
t27 CC
−
−
3
ns
Data setup to BFCLKO
falling edge1)
t28 SR
8
−
−
ns
Data hold from BFCLKO
falling edge1)
t29 SR
2
−
−
ns
Note /
Test Condition
1) Not subject to production test, verified by design/characterization.
BFCLKO
t27
t27
HLDA Output
t27
t27
BREQ Output
BFCLKO
t28
t28
t29
t29
HOLD Input
HLDA Input
Figure 30
Data Sheet
EBUArb_1
EBU Arbitration Signal Timing
171
V 1.2, 2014-05
TC1793
Electrical ParametersFlash Memory Parameters
5.4
Flash Memory Parameters
The data retention time of the TC1793’s Flash memory depends on the number of times
the Flash memory has been erased and programmed.
Table 46
FLASH32 Parameters
Parameter
Symbol
Values
Typ.
Max.
Data Flash Erase Time
per Sector
tERD CC −
−
4.21)
s
Program Flash Erase
Time per 256 KByte
Sector
tERP CC −
−
5
s
Program time data flash
per page2)
tPRD CC −
−
5.3
ms
without
reprogramming
−
−
15.9
ms
with two
reprogramming
cycles
tPRP CC −
−
5.3
ms
without
reprogramming
−
−
10.6
ms
with one
reprogramming
cycle
−
cycle Min. data
s
retention time 5
years
Min.
Program time program
flash per page3)
Data Flash Endurance
NE CC
60000 −
4)
Unit
Note /
Test Condition
tFL_ErSusp −
−
15
ms
tFL_Margin 10
−
−
μs
Program Flash Retention
Time, Physical Sector5)6)
tRET CC 20
−
−
year
s
Max. 1000
erase/program
cycles
Program Flash Retention
Time, Logical Sector5)6)
tRETL CC 20
−
−
year
s
Max. 100
erase/program
cycles
UCB Retention Time5)6)
tRTU CC 20
−
−
year
s
Max. 4
erase/program
cycles per UCB
Erase suspend delay
CC
Wait time after margin
change
Data Sheet
Del CC
172
V 1.2, 2014-05
TC1793
Electrical ParametersFlash Memory Parameters
Table 46
FLASH32 Parameters (cont’d)
Parameter
Wake-Up time
DFlash wait state
configuration
PFlash wait state
configuration
Symbol
tWU CC
WSDF
CC
WSPF
CC
Values
Unit
Min.
Typ.
Max.
−
−
270
50 ns x −
−
fFSI
26 ns x −
fFSI
−
Note /
Test Condition
μs
1) In case of wordline oriented defects (see robust EEPROM emulation in the User's Manual) this erase time can
increase by up to 100%.
2) In case the Program Verify feature detects weak bits, these bits will be programmed up to twice more. Each
reprogramming takes additional 5 ms.
3) In case the Program Verify feature detects weak bits, these bits will be programmed once more. The
reprogramming takes additional 5 ms.
4) Only valid when a robust EEPROM emulation algorithm is used. For more details see the User´s Manual.
5) Storage and inactive time included.
6) At average weighted junction temperature Tj = 100°C, or the retention time at average weighted temperature
of Tj = 110°C is minimum 10 years, or the retention time at average weighted temperature of Tj = 150°C is
minimum 0.7 years.
Data Sheet
173
V 1.2, 2014-05
TC1793
Electrical ParametersPackage and Reliability
5.5
Package and Reliability
5.5.1
Package Parameters
Table 47
Thermal Characteristics of the Package
Device
Package
TC1793
PG-BGA- 416
RΘJCT
RΘJCB RΘJA
1)
1)
3,3
4,5
12,1
Unit
Note
K/W
1) The top and bottom thermal resistances between the case and the ambient (RTCAT, RTCAB) are to be combined
with the thermal resistances between the junction and the case given above (RTJCT, RTJCB), in order to calculate
the total thermal resistance between the junction and the ambient (RTJA). The thermal resistances between
the case and the ambient (RTCAT, RTCAB) depend on the external system (PCB, case) characteristics, and are
under user responsibility.
The junction temperature can be calculated using the following equation: TJ = TA + RTJA × PD, where the RTJA
is the total thermal resistance between the junction and the ambient. This total junction ambient resistance
RTJA can be obtained from the upper four partial thermal resistances.
Thermal resistances as measured by the ’cold plate method’ (MIL SPEC-883 Method 1012.1).
Data Sheet
174
V 1.2, 2014-05
TC1793
Electrical ParametersPackage and Reliability
5.5.2
Figure 31
Package Outline
Package Outlines PG-BGA- 416
You can find all of our packages, sorts of packing and others in our Infineon Internet
Page “Products”: http://www.infineon.com/products.
5.5.3
Table 48
Parameter
Quality Declarations
Quality Parameters
Symbol
Values
Unit
Note / Test Condition
Min. Typ. Max.
Operation
Lifetime1)
tOP
ESD susceptibility VHBM
according to
Human Body
Model (HBM)
Data Sheet
–
–
24000 hours –2)
–
–
2000
175
V
Conforming to
JESD22-A114-B
V 1.2, 2014-05
TC1793
Electrical ParametersPackage and Reliability
Table 48
Quality Parameters
Parameter
Symbol
Values
Unit
Note / Test Condition
Min. Typ. Max.
ESD susceptibility VHBM1
of the LVDS pins
–
–
500
V
–
ESD susceptibility VCDM
according to
Charged Device
Model (CDM)
–
–
500
V
Conforming to
JESD22-C101-C
Moisture
Sensitivity Level
–
–
3
–
Conforming to Jedec
J-STD-020C for 240°C
MSL
1) This lifetime refers only to the time when the device is powered on.
2) For worst-case temperature profile equivalent to:
1200 hours at Tj = 125...150oC
3600 hours at Tj = 110...125oC
7200 hours at Tj = 100...110oC
11000 hours at Tj = 25...100oC
1000 hours at Tj = -40...25oC
Data Sheet
176
V 1.2, 2014-05
TC1793
History
6
History
The following changes where done between Version 0.6 and 0.62 of this document:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Change for port 1.7 the symbol from CC60INB to CC61INB for the CCU60 input
Add footnote to port 4.1 alternate output 3 MTSR2
change function description for port 4.1 alternate output 3 MTSR2 from Slave to
Master Transmit
Add footnote to port 6.4 alternate output 1 MTSR1
Add footnote to port 7.1 alternate output 2 MTSR3
Change for port 8.2 the symbol from CC61 (CCU60) to COUT63 (CCU61)
Change for port 8.3 the symbol from OUT43 (GPTA1) to CC62 (CCU60)
correct typo for port 9.4 from COUT&= to COUT60
correct typo for port 9.5 from COUT&! to COUT61
Change for port 15.4 and 15.5 the type from B1 to B
Change for port 15 the type from S to D / S
add clarification that table 11 defines the conditions for all other parameters
add conditions for MLI, MSC, SSC, parameters
add parameters dTxdly and dRxdly to ERAY parameters
correct footnotes for ERAY parameters
split flash parameters tPRD and tPRP in two conditions
add conditions to LVDS pad parameters
remove Pin Reliability in Overload section
add parameters IIN and Sum IIN to absolute ratings
add parameter HYSX to PSC_XTAL
added RDSON values for all driver settings (weak, medium, and strong)
removed footnote 2 of table 10
change load for timing of SSC, MSC, and MLI from CL = 25 pF to CL = 50 pF (typical)
add to parameters tRF and tFF condition CL = 50 pF
add new footnote 7) to ADC parameter table
add min and max value for QCONV and adapt typ value
add load conditions for tFF1 and tRF1
add conditions to PLL parameter tL
change DAP parameter t19 from SR to CC classification
remove footnote 2 for the FADC
adapt IDs for AB step
removed footnote 2 in table 9
change max value for ADC parameter tS from 255 to 257
The following changes where done between Version 0.62 and 0.63 of this document:
•
•
shift Output function CC62 of CCU60 for P8.3 from O3 to O2
remove output function OUT43 for GPTA1 for P8.3
Data Sheet
1
V 1.2, 2014-05
TC1793
History
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
add output function TData1 for MLI1 as O3 for P8.3
remove O2 OUT105 for GPTA1 of P14.9
add O2 T3OUt for GPT121 of P14.9
changed the name for O3 from EVTO2 to EVTO1 for P0.5
changed the name for O3 from EVTO3 to EVTO2 for P0.6
changed the name for O3 from EVTO4 to EVTO3 for P0.7
changed the name for O1 and O2 from OUT70 to OUT71 for P1.15
add input function SLSI2 for SSC2 to P4.9
change input function T13HRE from CCU60 to CCU63 for P3.14
change for port 8.2 the symbol from CC61(CCU60) to COUT63(CCU61)
change for port 14.10 the symbol from T3OUT(GPT120) to T6OUT(GPT121)
add to all SSC signal the associated SSC module where is was missing in the pinning
add section Pin Reliability in Overload
increase values for absolute maximum parameters IIN and SumIIN
correct P14.8 O2 as this was uncorrected label as O1
The following changes where done between Version 0.63 and 0.7 of this document:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
update value of RTID registers in section Identification Registers for AB step
remove sentence ‘Exposure to conditions within the maximum ratings will not affect
device reliability. To replace this sentence section Pin Reliability in Overload was
added.
add footnote 1 to table 12 (Operating Conditions)
increase values for absolute maximum parameters IIN and SumIIN
remove capacitance conditions for LVDS pad parameters as loads are defined by
interface (MSC) timings
add parameter VILSD for class S pads
add VDDM supply limitation for class S parameters
add footnote 10 to table 23 (ADC parameters)
remove old footnote 2 from table 24 (FADC parameters)
remove term typical from load of Peripheral Timings
add definition of driver strength settings for ERAY Interface Timing
update formulas for frequency modulation
change SSC parameter from t59 CC to SR
add figures for EBU Multiplexer and Demultiplexed Write Access
change footnote 4 wording for ERAY timing back to TC1797 wording
increase flash parameters tPRD and tPRP values
increase flash parameter tERD
add section 5.2.6.1.
change in legende of table 2 definition of class S pad
remove condition for VDDEBU
correct section Extended Range Operating Conditions for the 3.3 V area
increase limit in Extended Range Operating Conditions from 1 hour to 1000 hours
Data Sheet
2
V 1.2, 2014-05
TC1793
History
•
•
•
•
•
•
•
•
•
•
•
•
specify wording for limitation of pad performance in section Extended Range
Operating Conditions
remove incorrect test conditions for RDSONx parameters
remove ADC 3 from ADC parameters
adjust typo in temperature profile
removed RDSON parameters for class F pads weak driver as only medium is
available
add parameter fSYSD for the SYSPLL
changed RDSON values for class F pads
updated class B pads rise and fall times definitions
add RDSON parameters to class B pads
supply range of 1.8 V for VDDEBUwas removed
update all current values of table 28 (Power Supply Parameters)
rework the 3.3 V current part of the Power Supply Parameters for better description
and usage
– Parameters IDDP_FP, IDDFL3E and IDDFL3R are removed and replaced in the following
way
– IDDP_FP is replaced by IDDP with the condition including flash programming current
– IDDFL3E is replaced by IDDP with the condition including flash erase verify current
– IDDFL3R is replaced by IDDP with the condition including flash read current
– parameter IDDFL3R was renamed to IDDFL3
The rework of the 3.3 V current part of the Power Supply Parameters was done for
simplification and clarification. Former given values could still be used if liked, the new
definition results in the same resulting values or slightly better values. The flash module
is supplied via IDDFL3 and IDDP. For the different flash operating modes in worst case
different allocations for the two domains resulting.
The application typical case ‘flash read’ has max IDDP of 25 mA and max IDDFL3 of 98 mA
resulting is a sum of 123 mA.
The case ‘flash programming’ has max IDDP of 55 mA and max IDDFL3 of 29 mA resulting
is a sum of 84 mA.
The case ‘flash erase verify’ has max IDDP of 40 mA and max IDDFL3 of 98 mA resulting
is a sum of 138 mA.
So
for the old parameter IDDP with 35 mA, the new version reads as
IDDP = 25+IDDP_PORST = 32 mA for the same application relevant case.
The following changes where done between Version 0.7 and 1.0 of this document:
•
•
•
•
•
•
improve parameters IDDFL3
change for parameter NE note from Max. data retention to Min.
change description of parameter tCAL for the ADC
correct typo for class D pads in tables 14 and 15
adapt Absolute Maximun Rating
add footnote to Flash parameter tERD
Data Sheet
3
V 1.2, 2014-05
TC1793
History
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
add note at the end of Pin Reliability in Overload section
clearify pad supply levels in Pin Reliability in Overload section
add footnote for D-Flash currents in power section
clearify wording for valid operating conditions
add negative limit for class S pad leakage
increase max values for parameter tB
change formula 10
change MLI parameter t17 min value
change footnote 3 for EBU parameter t22
change package naming
add products SAK-TC1793N-512F270EF and SAK-TC1793N-512F270EB
split FADC DNL parameter into two conditions and change value for gain 4 and 8
update footnote 10 for the ADC
update package outline
update parmeter description for SSC parameters t52 and t53
change SSC parameters from CC to SR Symbol for t56, t57, t58 and t59
increase value range for BFCLKO duty cycle
The following changes where done between Version 1.0 and 1.1 of this document:
•
•
•
•
•
•
•
•
•
add product option SAK-TC1793S-512F270EF
update block diagrams to cover new option
add identification registers for new product option
rework first sentence for chapter 5.3
reduce min value for tL for both PLLs
split fVCO for system PLL into two conditions
add for MLI and SSC parameter: valid strong driver medium edge only
add footnote 5) for SSC parameters
add parameters t15, t16, t17, and t19 to the EBU
The following changes where done between Version 1.1 and 1.1.1 of this document:
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update the incoorect CHIPID values for copper and non copper bond options.
product SAK-TC-1793N-512F270EB not longer supported and replaced by SAKTC1793N-512F270EF
The following changes where done between Version 1.1.1 and 1.2 of this document:
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•
•
•
•
•
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remove the following product options:
– SAK-TC1793F-512F270EB
change VILS from 2.1V to 1.9V in table 23
change t48 from 100ns to 200ns in table 42
change t49 from 100ns to 200ns in table 42
extend KOVAN conditon from IOV≤ 0 mA; IOV≥ -1 mA to IOV≤ 0 mA; IOV≥ -2 mA
change t8 from -4ns to -2ns in table 43
change t18 from -4ns to -2ns in table 43
Data Sheet
4
V 1.2, 2014-05
TC1793
History
•
change t37 parameter description from ‘Data output delay to WR rising edge,
deviation from the ideal programmed value’ to ‘Data output delay to WR falling edge,
deviation from the ideal programmed value’ in table 43
Data Sheet
5
V 1.2, 2014-05
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG