TC1784 Data Sheet

32-Bit
Microcontroller
TC1784
32-Bit Single-Chip Microcontroller
Data Sheet
V 1.1.1 2014-05
Microcontrollers
Edition 2014-05
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2014 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
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be endangered.
32-Bit
Microcontroller
TC1784
32-Bit Single-Chip Microcontroller
Data Sheet
V 1.1.1 2014-05
Microcontrollers
TC1784
Table of Contents
1
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
2
2.1
System Overview of the TC1784 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
TC1784 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
3
3.1
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
TC1784 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
4
Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-42
5
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.6.1
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.3.8.1
5.3.8.2
5.3.8.3
5.3.8.4
5.3.8.5
5.4
5.4.1
5.4.2
Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-44
General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-44
Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-44
Pad Driver and Pad Classes Summary . . . . . . . . . . . . . . . . . . . . . . . 5-45
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-46
Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-47
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49
DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-53
Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-53
Analog to Digital Converters (ADCx) . . . . . . . . . . . . . . . . . . . . . . . . . 5-68
Fast Analog to Digital Converter (FADC) . . . . . . . . . . . . . . . . . . . . . . 5-73
Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-77
Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-78
Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-79
Calculating the 1.3 V Current Consumption . . . . . . . . . . . . . . . . . 5-81
AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-83
Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-83
Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-84
Power, Pad and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-86
Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-88
ERAY Phase Locked Loop (ERAY_PLL) . . . . . . . . . . . . . . . . . . . . . . 5-90
JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-91
DAP Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-93
Peripheral Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-95
Micro Link Interface (MLI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . 5-95
Micro Second Channel (MSC) Interface Timing . . . . . . . . . . . . . . 5-97
SSC Master/Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 5-99
ERAY Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-101
EBU Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-103
Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-111
Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-111
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-112
Data Sheet
I-1
V 1.1.1, 2014-05
TC1784
5.4.3
5.4.4
6
Data Sheet
Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-112
Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-114
History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-115
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TC1784
Data Sheet
3
V 1.1.1, 2014-05
TC1784
Data Sheet
4
V 1.1.1, 2014-05
TC1784
Summary of Features
1
Summary of Features
The SAK-TC1784F-320F180EL / SAK-TC1784F-320F180EP
features:
•
•
•
•
•
•
•
has
the
following
High-performance 32-bit super-scalar TriCore V1.3.1 CPU with 4-stage pipeline
– Superior real-time performance
– Strong bit handling
– Fully integrated DSP capabilities
– Single precision Floating Point Unit (FPU)
– 180 MHz operation at full temperature range
32-bit Peripheral Control Processor with single cycle instruction (PCP2)
– 16 Kbyte Parameter Memory (PRAM)
– 32 Kbyte Code Memory (CMEM)
– 180 MHz operation at full temperature range
Multiple on-chip memories
– 2.5 Mbyte Program Flash Memory (PFLASH) with ECC
– 64 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation
– 128 Kbyte Data Memory (LDRAM)
– Instruction Cache: up to 16 Kbyte (ICACHE, configurable)
– 40 Kbyte Code Scratchpad Memory (SPRAM)
– Data Cache: up to 4 Kbyte (DCACHE, configurable)
– 8 Kbyte Overlay Memory (OVRAM)
– 16 Kbyte BootROM (BROM)
16-Channel DMA Controller
Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels
serviced by CPU or PCP2
High performing on-chip bus structure
– 64-bit Local Memory Buses between CPU, Flash and Data Memory
– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
– One bus bridge (LFI Bridge)
Versatile On-chip Peripheral Units
– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,
parity, framing and overrun error detection
– Three High-Speed Synchronous Serial Channels (SSC) with programmable data
length and shift direction
– One serial Micro Second Bus interface (MSC) for serial port expansion to external
power devices
– One High-Speed Micro Link interface (MLI) for serial inter-processor
communication
– One External Bus Interface (EBU) with
32-bit demultiplexed / 16-bit multiplexed external bus interface
Scalable external bus timing up to 75 MHz
Data Sheet
1
V 1.1.1, 2014-05
TC1784
Summary of Features
•
•
•
•
•
•
•
•
– One MultiCAN Module with 3 CAN nodes and 128 free assignable message
objects for high efficiency data handling via FIFO buffering and gateway data
transfer (one CAN node supports TTCAN functionality)
– One FlexRayTM module with 2 channels (E-Ray).
– One General Purpose Timer Array Module (GPTA) with additional Local Timer Cell
Array (LTCA2) providing a powerful set of digital signal filtering and timer
functionality to realize autonomous and complex Input/Output management
32 analog input lines for ADC
– 2 independent kernels (ADC0 and ADC1)
– Analog supply voltage range from 3.3 V to 5 V (single supply)
4 different FADC input channels
– channels with impedance control and overlaid with ADC1 inputs
– Extreme fast conversion, 21 cycles of fFADC clock
– 10-bit A/D conversion (higher resolution can be achieved by averaging of
consecutive conversions in digital data reduction filter)
91 digital general purpose I/O lines (GPIO), 4 input lines
Digital I/O ports with 3.3 V capability
On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Bus)
Dedicated Emulation Device chip available (TC1784ED)
– multi-core debugging, real time tracing, and calibration
– four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface
Power Management System
Clock Generation Unit with PLL
Data Sheet
2
V 1.1.1, 2014-05
TC1784
Summary of Features
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies:
•
•
The derivative itself, i.e. its function set, the temperature range, and the supply
voltage
The package and the type of delivery.
For the available ordering codes for the TC1784 please refer to the “Product Catalog
Microcontrollers”, which summarizes all available microcontroller variants.
This document describes the derivatives of the device.The Table 1 enumerates these
derivatives and summarizes the differences.
Table 1
TC1784 Derivative Synopsis
Derivative
Ambient Temperature Range
SAK-TC1784F-320F180EL
TA = -40oC to +125oC
SAK-TC1784F-320F180EP
TA = -40oC to +125oC
Data Sheet
3
V 1.1.1, 2014-05
TC1784
System Overview of the TC1784
2
System Overview of the TC1784
The TC1784 combines three powerful technologies within one silicon die, achieving new
levels of power, speed, and economy for embedded applications:
•
•
•
Reduced Instruction Set Computing (RISC) processor architecture
Digital Signal Processing (DSP) operations and addressing modes
On-chip memories and peripherals
DSP operations and addressing modes provide the computational power necessary to
efficiently analyze complex real-world signals. The RISC load/store architecture
provides high computational bandwidth with low system cost. On-chip memory and
peripherals are designed to support even the most demanding high-bandwidth real-time
embedded control-systems tasks.
Additional high-level features of the TC1784 include:
•
•
•
•
•
•
•
•
•
Efficient memory organization: instruction and data scratch memories, caches
Serial communication interfaces – flexible synchronous and asynchronous modes
Peripheral Control Processor – standalone data operations and interrupt servicing
DMA Controller – DMA operations and interrupt servicing
General-purpose timers
High-performance on-chip buses
On-chip debugging and emulation facilities
Flexible interconnections to external components
Flexible power-management
The TC1784 is a high-performance microcontroller with TriCore CPU, program and data
memories, buses, bus arbitration, an interrupt controller, a peripheral control processor
and a DMA controller and several on-chip peripherals. The TC1784 is designed to meet
the needs of the most demanding embedded control systems applications where the
competing issues of price/performance, real-time responsiveness, computational power,
data bandwidth, and power consumption are key design elements.
The TC1784 offers several versatile on-chip peripheral units such as serial controllers,
timer units, and Analog-to-Digital converters. Within the TC1784, all these peripheral
units are connected to the TriCore CPU/system via the Flexible Peripheral Interconnect
(FPI) Bus and the Local Memory Bus (LMB). Several I/O lines on the TC1784 ports are
reserved for these peripheral units to communicate with the external world.
Data Sheet
4
V 1.1.1, 2014-05
TC1784
System Overview of the TC1784TC1784 Block Diagram
2.1
TC1784 Block Diagram
Figure 1 shows the block diagram of the TC1784.
FPU
PMI
TriCore
CPU
24 KB SPRAM
16 KB ICACHE
(Configurable)
Abbreviations:
ICACHE:
Instruction Cache
DCACHE
Data Cache
SPRAM:
Scratch-Pad RAM
LDRAM:
Local Data RAM
OVRAM:
Overlay RAM
BROM:
Boot ROM
PFlash:
Program Flash
DFlash:
Data Flash
PRAM:
Parameter RAM in PCP
PCODE:
Code RAM in PCP
DMI
124 KB LDRAM
LDRAM
4 KB DCACHE
(Configurable)
DCACHE
CPS
Local Memory Bus
BCU
(LMB)
PMU
M
2,5 MB PFlash
128 KB DFlash
8 KB OVRAM
16 KB BROM
DMA
Bridge
16 channels
SMIF
EBU
OCDS L1 Debug
Interface/JTAG
M/ S
MLI0
System Peripheral Bus
(SPB)
MemCheck
16 KB PRAM
E-Ray
GPTA 0
System Peripheral Bus
Interrupts
ASC1
(2 Channels)
Interrupt
System
FPI-Bus Interface
ASC0
PCP2
Core
STM
5V (3.3V supported as well)
Ext. ADC Supply
32 KB CMEM
SCU
ADC0
28
( 5V max)
SBCU
PLL
E-RAY
Ports
ADC1
4
PLL
SSC0
FADC
( 3.3V max)
LTCA2
4
SSC1
Ext.
Request
Unit
Figure 1
Multi
CAN
(3 Nodes,
128 MO)
MSC0
SSC2
(LVDS)
3.3V
Ext. FADC Supply
BlockDiagram
TC1784F
V1.1
TC1784F Block Diagram
Figure 1 shows the block diagram of the SAK-TC1784F-320F180EL / SAK-TC1784F320F180EP.
Data Sheet
5
V 1.1.1, 2014-05
TC1784
PinningTC1784 Pin Configuration
3
Pinning
Figure 3-1 is showing the TC1784 Logic Symbol.
General Control
PORST
TESTMODE
ESR0
ESR1
Alternate Functions
16
16
TRST
OCDS /
JTAG Control
Analog Inputs
14
TCK / DAP0
16
TDI / BRKIN
TDO / DAP2 /
BRKOUT
TMS / DAP1
4
16
AN [35:0]
4
V DDM
VSSM
VDDMF
Analog Power
Supply
16
V SSMF
VDDAF
15
VAREF0
VAREF1
VAGND0
V FAREF
VFAGND
8
V DDFL3
VDD
Digital Circuitry
Power Supply
TC1784
VDDP
V SS
VSSP
14
Port 3
GPTA, SCU. E-RAY,
MSC0
GPTA, SSC1,
ADC0, OCDS
GPTA, SSC0/1,
MLI0, MSC0
GPTA, ASC0/1, SSC 0/1,
SCU, CAN, MSC 0
Port 4
GPTA, SCU, CAN
Port 5
GPTA, MLI0, E-RAY,
SSC2
Port 6
GPTA, MSC 0
Port 7
GPTA, EBU
Port 8
GPTA, EBU
Port 9
GPTA, SCU, CAN
Port 10
GPTA, SSC 2
Port 0
Port 1
Port 2
XTAL1
XTAL2
2
VDDOSC
VDDOSC3
12
11
Oscillator
VSSOSC
48
V DDPF
15
V DDPF3
TC1784_LogSym_292
Figure 3-1
3.1
TC1784 Logic Symbol
TC1784 Pin Configuration
This chapter shows the pin configuration of package variant PG-LFBGA-292-6.
Data Sheet
,
3-6
V 1.1.1, 2014-05
TC1784
PinningTC1784 Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
N.C.2
P10.9
P10.8
P10.6
P10.4
VSSP
P2.12
P2.11
P6.2
P6.0
VSSP
P0.12
P0.10
P0.8
P3.13
P3.15
P3.4
P3.2
P3.8
VSSP
A
B
VDDP
VSSP
P10.7
P10.5
P10.3
VDDP
P0.15
P2.10
P6.3
P6.1
VDDP
P0.13
P0.11
P0.9
P3.12
P3.14
P3.7
P3.3
VSSP
VDDP
B
C
P10.10
VDDP
VDDP
P3.6
C
D
P5.0
P10.11
VSSP
D
E
P5.5
P5.1
F
P5.6
P5.7
G
VSSP
H
Top-View
P10.2
P10.0
P0.14
P0.6
P2.13
P2.9
P0.2
P0.1
P10.12
VSSP
P10.1
P0.7
P0.5
P0.4
P2.8
P0.3
P0.0
P5.2
P10.13
VDDP
P9.0
P5.3
P5.15
P5.8
P9.1
P5.4
VDD
J
P5.10
P5.9
P9.3
P9.2
VSS
VSS
K
P5.12
P5.11
P9.4
P9.5
VSS
VSS
L
P5.14
P5.13
P9.6
P9.7
VSS
VSS
VSSP
VDDP
N.C.3
N.C.4
VSS
VSS
M
N
VDDMF VDDAF
VDD
VFAREF VFAGND
VDD
VDDFL3 VDDFL3
P3.11
P3.9
P3.0
P3.10
P3.1
VSSP
P3.5
ESR0
VSSP
P1.1
ESR1
PORST
E
P1.15
P1.0
TEST
MODE
TCK
F
P1.6
P1.7
TRST
TDO
G
VDD
P1.5
TMS
TDI
VSS
VSS
P1.4
VDDPF3
XTAL2
XTAL1
J
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P1.3
VDDPF
VDDOSC
VSSOSC
K
VSS
VSS
VSS
VSS
VSS
VSS
P1.10
P1.8
P1.9
P1.11
L
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VSS
VDDOSC3 H
VSS
P1.2
P8.14
VDDP
VSSP
M
VDD
P8.13
P8.12
P8.11
P8.4
N
P8.10
P8.9
P8.8
P8.7
P
VDD
P7.2
P8.6
P8.5
R
P
AN35
VSSAF
VSSMF
AN34
AN33
R
AN32
AN31
AN30
AN29
T
AN28
AN7
AN25
AN24
VAGND0
VAREF1
AN6
AN2
P1.12
P2.3
P2.7
P4.0
P7.4
P7.7
VSS
VDD
P8.2
P8.3
T
U
AN27
AN26
AN21
AN15
VAREF0
AN8
AN3
P1.14
P1.13
P2.2
P2.6
P4.1
P7.3
P7.8
P7.0
VSS
P8.0
P8.1
U
VDD
VDD
V
AN23
AN22
VDD
P7.15
V
W
AN20
AN14
AN16
AN18
AN17
AN19
VSSM
AN5
AN1
VDDP
P2.1
P2.5
P4.2
P7.6
P7.9
VDDP
P7.11
P7.13
VSS
VDD
W
Y
N.C.1
AN13
AN12
AN11
AN10
AN9
VDDM
AN4
AN0
VSSP
P2.0
P2.4
P4.3
P7.1
P7.5
VSSP
P7.10
P7.12
P7.14
VSS
Y
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Figure 3-2
Data Sheet
,
TC1784 Pinning for PG-LFBGA-292-6 Package
3-7
V 1.1.1, 2014-05
TC1784
PinningTC1784 Pin Configuration
Table 3-1
Pin
Pin Definitions and Functions (PG-LFBGA-292-6)
Symbol
Ctrl. Type Function
Port 0
E12
D12
D11
E11
P0.0
I/O0
IN0
I
A1/
PU
IN0
I
LTCA2 Input 0
HWCFG0
I
Hardware Configuration Input 0
OUT0
O1
GPTA0 Output 0
OUT56
O2
GPTA0 Output 56
Port 0 General Purpose I/O Line 0
GPTA0 Input 0
OUT0
O3
P0.1
I/O0
IN1
I
IN1
I
LTCA2 Input 1
SDI1
I
MSC0 Serial Data Input 1
HWCFG1
I
Hardware Configuration Input 1
OUT1
O1
GPTA0 Output 1
OUT57
O2
GPTA0 Output 57
LTCA2 Output 0
A1/
PU
Port 0 General Purpose I/O Line 1
GPTA0 Input 1
OUT1
O3
P0.2
I/O0
IN2
I
IN2
I
LTCA2 Input 2
HWCFG2
I
Hardware Configuration Input 2
OUT2
O1
GPTA0 Output 2
OUT58
O2
GPTA0 Output 58
OUT2
O3
LTCA2 Output 2
LTCA2 Output 1
A1/
PU
GPTA0 Input 2
P0.3
I/O0
IN3
I
IN3
I
LTCA2 Input 3
HWCFG3
I
Hardware Configuration Input 3
OUT3
O1
GPTA0 Output 3
OUT59
O2
GPTA0 Output 59
OUT3
O3
LTCA2 Output 3
Data Sheet
,
A1+/
PU
Port 0 General Purpose I/O Line 2
Port 0 General Purpose I/O Line 3
GPTA0 Input 3
3-8
V 1.1.1, 2014-05
TC1784
PinningTC1784 Pin Configuration
Table 3-1
Pin Definitions and Functions (PG-LFBGA-292-6) (cont’d)
Pin
Symbol
Ctrl. Type Function
E9
P0.4
I/O0
IN4
I
IN4
I
LTCA2 Input 4
HWCFG4
I
Hardware Configuration Input 4
OUT4
O1
GPTA0 Output 4
OUT60
O2
GPTA0 Output 60
OUT4
O3
LTCA2 Output 4
E8
D8
E7
A1/
PU
GPTA0 Input 4
P0.5
I/O0
IN5
I
IN5
I
LTCA2 Input 5
HWCFG5
I
Hardware Configuration Input 5
OUT5
O1
GPTA0 Output 5
OUT61
O2
GPTA0 Output 61
OUT5
O3
LTCA2 Output 5
P0.6
I/O0
IN6
I
IN6
I
LTCA2 Input 6
HWCFG6
I
Hardware Configuration Input 6
REQ2
I
External Request Input 2
OUT6
O1
GPTA0 Output 6
OUT62
O2
GPTA0 Output 62
OUT6
O3
LTCA2 Output 6
P0.7
I/O0
IN7
I
IN7
I
LTCA2 Input 7
HWCFG7
I
Hardware Configuration Input 7
REQ3
I
External Request Input 3
OUT7
O1
GPTA0 Output 7
OUT63
O2
GPTA0 Output 63
OUT7
O3
LTCA2 Output 7
Data Sheet
,
A1/
PU
Port 0 General Purpose I/O Line 4
A1/
PU
A1/
PU
Port 0 General Purpose I/O Line 5
GPTA0 Input 5
Port 0 General Purpose I/O Line 6
GPTA0 Input 6
Port 0 General Purpose I/O Line 7
GPTA0 Input 7
3-9
V 1.1.1, 2014-05
TC1784
PinningTC1784 Pin Configuration
Table 3-1
Pin Definitions and Functions (PG-LFBGA-292-6) (cont’d)
Pin
Symbol
Ctrl. Type Function
A14
P0.8
I/O0
IN8
I
IN8
I
LTCA2 Input 8
RXDA0
I
E-Ray Channel A Receive Data Input 0
OUT8
O1
GPTA0 Output 8
OUT64
O2
GPTA0 Output 64
OUT8
O3
LTCA2 Output 8
P0.9
I/O0
IN9
I
B14
A13
B13
A12
A1/
PU
A1/
PU
Port 0 General Purpose I/O Line 8
GPTA0 Input 8
Port 0 General Purpose I/O Line 9
GPTA0 Input 9
IN9
I
LTCA2 Input 9
RXDB0
I
E-Ray Channel B Receive Data Input 0
OUT9
O1
GPTA0 Output 9
OUT65
O2
GPTA0 Output 65
OUT9
O3
LTCA2 Output 9
P0.10
I/O0
IN10
I
OUT10
O1
GPTA0 Output 10
TXDA0
O2
E-Ray Channel A transmit Data Output
OUT10
O3
LTCA2 Output 10
P0.11
I/O0
IN11
I
OUT11
O1
GPTA0 Output 11
TXDB0
O2
E-Ray Channel B transmit Data Output
A2/
PU
A2/
PU
Port 0 General Purpose I/O Line 10
GPTA0 Input 10
Port 0 General Purpose I/O Line 11
GPTA0 Input 11
OUT11
O3
P0.12
I/O0
IN12
I
OUT12
O1
GPTA0 Output 12
TXENA
O2
E-Ray Channel A transmit Data Output enable
OUT12
O3
LTCA2 Output 12
Data Sheet
,
LTCA2 Output 11
A2/
PU
Port 0 General Purpose I/O Line 12
GPTA0 Input 12
3-10
V 1.1.1, 2014-05
TC1784
PinningTC1784 Pin Configuration
Table 3-1
Pin Definitions and Functions (PG-LFBGA-292-6) (cont’d)
Pin
Symbol
Ctrl. Type Function
B12
P0.13
I/O0
IN13
I
OUT13
O1
GPTA0 Output 13
TXENB
O2
E-Ray Channel B transmit Data Output enable
OUT13
O3
P0.14
I/O0
IN14
I
D7
B7
A2/
PU
Port 0 General Purpose I/O Line 13
GPTA0 Input 13
LTCA2 Output 13
A1+/
PU
Port 0 General Purpose I/O Line 14
GPTA0 Input 14
REQ4
I
External Request Input 4
OUT14
O1
GPTA0 Output 14
FCLP0C
O2
MSC0 Clock Output Positive C
OUT14
O3
LTCA2 Output 14
P0.15
I/O0
IN15
I
REQ5
I
External Request Input 5
OUT15
O1
GPTA0 Output 15
A1+/
PU
Port 0 General Purpose I/O Line 15
GPTA0 Input 15
SOP0C
O2
MSC0 Serial Data Output Positive C
OUT15
O3
LTCA2 Output 15
P1.0
I/O0
IN16
I
Port 1
F17
E17
A2/
PU
Port 1 General Purpose I/O Line 0
GPTA0 Input 16
BRKIN
I
Break Input
OUT16
O1
GPTA0 Output 16
OUT72
O2
GPTA0 Output 72
OUT16
O3
LTCA2 Output 16
BRKOUT
O
Break Output (controlled by OCDS module)
P1.1
I/O0
IN17
I
OUT17
O1
GPTA0 Output 17
OUT73
O2
GPTA0 Output 73
OUT17
O3
LTCA2 Output 17
Data Sheet
,
A1/
PU
Port 1 General Purpose I/O Line 1
GPTA0 Input 17
3-11
V 1.1.1, 2014-05
TC1784
PinningTC1784 Pin Configuration
Table 3-1
Pin Definitions and Functions (PG-LFBGA-292-6) (cont’d)
Pin
Symbol
Ctrl. Type Function
M16
P1.2
I/O0
IN18
I
OUT18
O1
GPTA0 Output 18
OUT74
O2
GPTA0 Output 74
OUT18
O3
P1.3
I/O0
IN19
I
IN19
I
LTCA2 Input 19
OUT19
O1
GPTA0 Output 19
OUT75
O2
GPTA0 Output 75
OUT19
O3
LTCA2 Output 19
P1.4
I/O0
IN20
I
IN20
I
LTCA2 Input 20
EMGSTOP
I
Emergency Stop Input
OUT20
O1
GPTA0 Output 20
OUT76
O2
GPTA0 Output 76
OUT20
O3
P1.5
I/O0
IN21
I
IN21
I
LTCA2 Input 21
OUT21
O1
GPTA0 Output 21
OUT77
O2
GPTA0 Output 77
OUT21
O3
P1.6
I/O0
IN22
I
IN22
I
LTCA2 Input 22
OUT22
O1
GPTA0 Output 22
OUT78
O2
GPTA0 Output 78
OUT22
O3
LTCA2 Output 22
K16
J16
H16
G16
Data Sheet
,
A1/
PU
Port 1 General Purpose I/O Line 2
GPTA0 Input 18
LTCA2 Output 18
A1/
PU
A1/
PU
Port 1 General Purpose I/O Line 3
GPTA0 Input 19
Port 1 General Purpose I/O Line 4
GPTA0 Input 20
LTCA2 Output 20
A1/
PU
Port 1 General Purpose I/O Line 35
GPTA0 Input 21
LTCA2 Output 21
A1/
PU
Port 1 General Purpose I/O Line 6
GPTA0 Input 22
3-12
V 1.1.1, 2014-05
TC1784
PinningTC1784 Pin Configuration
Table 3-1
Pin Definitions and Functions (PG-LFBGA-292-6) (cont’d)
Pin
Symbol
Ctrl. Type Function
G17
P1.7
I/O0
IN23
I
IN23
I
LTCA2 Input 23
OUT23
O1
GPTA0 Output 23
OUT79
O2
GPTA0 Output 79
OUT23
O3
LTCA2 Output 23
P1.8
I/O0
IN24
I
IN48
I
GPTA0 Input 48
MTSR1B
I
SSC1 Slave Receive Input B (Slave Mode)
OUT24
O1
GPTA0 Output 24
OUT48
O2
GPTA0 Output 48
L17
L19
L16
A1/
PU
A1+/
PU
Port 1 General Purpose I/O Line 7
GPTA0 Input 23
Port 1 General Purpose I/O Line 8
GPTA0 Input 24
MTSR1B
O3
P1.9
I/O0
IN25
I
IN49
I
GPTA0 Input 49
MRST1B
I
SSC1 Master Receive Input B (Master Mode)
OUT25
O1
GPTA0 Output 25
OUT49
O2
GPTA0 Output 49
MRST1B
O3
SSC1 Slave Transmit Output B (Slave Mode)
SSC1 Master Transmit Output B (Master Mode)
A1+/
PU
GPTA0 Input 25
P1.10
I/O0
IN26
I
IN50
I
GPTA0 Input 50
OUT26
O1
GPTA0 Output 26
OUT50
O2
GPTA0 Output 50
SLSO17
O3
SSC1 Slave Select Output 7
Data Sheet
,
A1+/
PU
Port 1 General Purpose I/O Line 9
Port 1 General Purpose I/O Line 10
GPTA0 Input 26
3-13
V 1.1.1, 2014-05
TC1784
PinningTC1784 Pin Configuration
Table 3-1
Pin Definitions and Functions (PG-LFBGA-292-6) (cont’d)
Pin
Symbol
Ctrl. Type Function
L20
P1.11
I/O0
IN27
I
IN51
I
GPTA0 Input 51
SCLK1B
I
SSC1 Clock Input B
OUT27
O1
GPTA0 Output 27
OUT51
O2
GPTA0 Output 51
SCLK1B
O3
SSC1 Clock Output B
T10
U10
U9
F16
A1+/
PU
A1/
PU
Port 1 General Purpose I/O Line 11
GPTA0 Input 27
P1.12
I/O0
IN16
I
AD0EMUX0
O1
ADC0 External Multiplexer Control Output 0
AD0EMUX0
O2
ADC0 External Multiplexer Control Output 0
OUT16
O3
LTCA2 Output 16
A1/
PU
Port 1 General Purpose I/O Line 12
LTCA2 Input 16
P1.13
I/O0
IN17
I
AD0EMUX1
O1
ADC0 External Multiplexer Control Output 1
AD0EMUX1
O2
ADC0 External Multiplexer Control Output 1
OUT17
O3
LTCA2 Output 17
A1/
PU
Port 1 General Purpose I/O Line 13
LTCA2 Input 17
P1.14
I/O0
IN18
I
AD0EMUX2
O1
ADC0 External Multiplexer Control Output 2
AD0EMUX2
O2
ADC0 External Multiplexer Control Output 2
OUT18
O3
LTCA2 Output 18
P1.15
I/O0
A2/
PU
Port 1 General Purpose I/O Line 14
LTCA2 Input 18
Port 1 General Purpose I/O Line 15
BRKIN
I
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
BRKOUT
O
OCDS Break Output
OCDS Break Input
Port 2
Data Sheet
,
3-14
V 1.1.1, 2014-05
TC1784
PinningTC1784 Pin Configuration
Table 3-1
Pin Definitions and Functions (PG-LFBGA-292-6) (cont’d)
Pin
Symbol
Ctrl. Type Function
Y11
P2.0
I/O0
IN32
I
OUT32
O1
GPTA0 Output 32
TCLK0
O2
MLI0 Transmitter Clock Output 0
OUT28
O3
W11 P2.1
IN33
U11
T11
Y12
I/O0
I
A2/
PU
Port 2 General Purpose I/O Line 0
GPTA0 Input 32
LTCA2 Output 28
A2/
PU
Port 2 General Purpose I/O Line 1
GPTA0 Input 33
TREADY0A
I
MLI0 Transmitter Ready Input A
OUT33
O1
GPTA0 Output 33
SLSO03
O2
SSC0 Slave Select Output Line 3
SLSO13
O3
SSC1 Slave Select Output Line 3
P2.2
I/O0
IN34
I
OUT34
O1
GPTA0 Output 34
TVALID0
O2
MLI0 Transmitter Valid Output
OUT29
O3
P2.3
I/O0
IN35
I
OUT35
O1
GPTA0 Output 35
TDATA0
O2
MLI0 Transmitter Data Output
OUT30
O3
P2.4
I/O0
IN36
I
RCLK0A
I
MLI Receiver Clock Input A
OUT36
O1
GPTA0 Output 36
OUT36
O2
GPTA0 Output 36
OUT31
O3
LTCA2 Output 31
Data Sheet
,
A2/
PU
Port 2 General Purpose I/O Line 2
GPTA0 Input 34
LTCA2 Output 29
A2/
PU
Port 2 General Purpose I/O Line 3
GPTA0 Input 35
LTCA2 Output 30
A2/
PU
Port 2 General Purpose I/O Line 4
GPTA0 Input 36
3-15
V 1.1.1, 2014-05
TC1784
PinningTC1784 Pin Configuration
Table 3-1
Pin
Pin Definitions and Functions (PG-LFBGA-292-6) (cont’d)
Symbol
W12 P2.5
U12
T12
E10
D10
Ctrl. Type Function
I/O0
A2/
PU
Port 2 General Purpose I/O Line 5
IN37
I
OUT37
O1
GPTA0 Output 37
RREADY0A
O2
MLI0 Receiver Ready Output A
OUT110
O3
P2.6
I/O0
IN38
I
RVALID0A
I
MLI Receiver Valid Input A
OUT38
O1
GPTA0 Output 38
OUT38
O2
GPTA0 Output 38
OUT111
O3
LTCA2 Output 111
P2.7
I/O0
GPTA0 Input 37
LTCA2 Output 110
A2/
PU
A2/
PU
Port 2 General Purpose I/O Line 6
GPTA0 Input 38
Port 2 General Purpose I/O Line 7
IN39
I
RDATA0A
I
MLI Receiver Data Input A
OUT39
O1
GPTA0 Output 39
OUT39
O2
GPTA0 Output 39
Reserved
O3
-
P2.8
I/O0
SLSO04
O1
SLSO14
O2
A2/
PU
GPTA0 Input 39
Port 2 General Purpose I/O Line 8
SSC0 Slave Select Output 4
SSC1 Slave Select Output 4
EN00
O3
P2.9
I/O0
SLSO05
O1
SLSO15
O2
SSC1 Slave Select Output 5
EN01
O3
MSC0 Enable Output 1
Data Sheet
,
MSC0 Enable Output 0
A2/
PU
Port 2 General Purpose I/O Line 9
SSC0 Slave Select Output 5
3-16
V 1.1.1, 2014-05
TC1784
PinningTC1784 Pin Configuration
Table 3-1
Pin Definitions and Functions (PG-LFBGA-292-6) (cont’d)
Pin
Symbol
Ctrl. Type Function
B8
P2.10
I/O0
A8
A7
D9
A1+/
PU
Port 2 General Purpose I/O Line 10
MRST1A
I
IN10
I
LTCA2 Input 10
MRST1A
O1
SSC1 Slave Transmit Output
OUT0
O2
LTCA2 Output 0
Reserved
O3
-
P2.11
I/O0
A1+/
PU
SSC1 Master Receive Input A
Port 2 General Purpose I/O Line 11
SCLK1A
I
IN11
I
LTCA2 Input 11
SCLK1A
O1
SSC1 Clock Output A
OUT1
O2
LTCA2 Output 1
FCLP0B
O3
MSC0 Clock Output Positive B
P2.12
I/O0
MTSR1A
I
IN12
I
LTCA2 Input 12
MTSR1A
O1
SSC1 Master Transmit Output A
OUT2
O2
LTCA2 Output 2
SOP0B
O3
P2.13
I/O0
SLSI11
I
A1+/
PU
SSC1 Clock Input A
Port 2 General Purpose I/O Line 12
SSC1 Slave Receive Input A
MSC0 Serial Data Output Positive B
A1/
PU
Port 2 General Purpose I/O Line 13
SSC1 Slave Select Input 1
SDI0
I
MSC0 Serial Data Input 0
IN13
I
LTCA2 Input 13
OUT3
O1
LTCA2 Output 3
Reserved
O2
-
Reserved
O3
-
Port 3
Data Sheet
,
3-17
V 1.1.1, 2014-05
TC1784
PinningTC1784 Pin Configuration
Table 3-1
Pin Definitions and Functions (PG-LFBGA-292-6) (cont’d)
Pin
Symbol
Ctrl. Type Function
D15
P3.0
I/O0
RXD0A
I
RXD0A
O1
ASC0 Clock Output (Sync. Mode)
RXD0A
O2
ASC0 Clock Output (Sync. Mode)
OUT84
O3
P3.1
I/O0
TXD0
O1
D16
A18
B18
A17
D19
A1+/
PU
Port 3 General Purpose I/O Line 0
ASC0 Receiver Input A (Async. & Sync. Mode)
GPTA0 Output 84
A1+/
PU
Port 3 General Purpose I/O Line 1
ASC0 Transmit
TXD0
O2
ASC0 Transmit
OUT85
O3
GPTA0 Output 85
P3.2
I/O0
SCLK0
I
SCLK0
O1
SSC0 Clock Output (Master Mode)
SCLK0
O2
SSC0 Clock Input (Master Mode)
OUT86
O3
GPTA0 Output 86
P3.3
I/O0
MRST0
I
MRST0
O1
SSC0 Slave Transmit Output (Slave Mode)
MRST0
O2
SSC0 Slave Transmit Output (Slave Mode)
OUT87
O3
GPTA0 Output 87
P3.4
I/O0
MTSR0
I
MTSR0
O1
SSC0 Master Transmit Output (Master Mode)
MTSR0
O2
SSC0 Master Transmit Output (Master Mode)
OUT88
O3
P3.5
I/O0
SLSO00
O1
SLSO10
O2
SLSOANDO0 O3
Data Sheet
,
A1+/
PU
A1+/
PU
A2/
PU
Port 3 General Purpose I/O Line 2
SSC0 Clock Input (Slave Mode)
Port 3 General Purpose I/O Line 3
SSC0 Master Receive Input (Master Mode)
Port 3 General Purpose I/O Line 4
SSC0 Slave Receive Input (Slave Mode)
GPTA0 Output 88
A1+/
PU
Port 3 General Purpose I/O Line 5
SSC0 Slave Select Output 0
SSC1 Slave Select Output 0
SSC0 AND SSC1 Slave Select Output 0
3-18
V 1.1.1, 2014-05
TC1784
PinningTC1784 Pin Configuration
Table 3-1
Pin Definitions and Functions (PG-LFBGA-292-6) (cont’d)
Pin
Symbol
Ctrl. Type Function
C20
P3.6
I/O0
SLSO01
O1
SLSO11
O2
A1+/
PU
A19
E14
E15
E13
SSC0 Slave Select Output 1
SSC1 Slave Select Output 1
SLSOANDO1 O3
B17
Port 3 General Purpose I/O Line 6
SSC0 AND SSC1 Slave Select Output 1
P3.7
I/O0
SLSI0
I
A2/
PU
SLSO02
O1
SSC0 Slave Select Output 2
SLSO12
O2
SSC1 Slave Select Output 2
OUT89
O3
GPTA0 Output 89
A2/
PU
Port 3 General Purpose I/O Line 7
SSC0 Slave Select Input 1
P3.8
I/O0
SLSO06
O1
TXD1
O2
OUT90
O3
P3.9
I/O0
RXD1A
I
RXD1A
O1
ASC1 Receiver Output A (Synchronous Mode)
RXD1A
O2
ASC1 Receiver Output A (Synchronous Mode)
Port 3 General Purpose I/O Line 8
SSC0 Slave Select Output 6
ASC1 Transmit Output
GPTA0 Output 90
A1/
PU
Port 3 General Purpose I/O Line 9
ASC1 Receiver Input A
OUT91
O3
P3.10
I/O0
REQ0
I
Reserved
O1
-
Reserved
O2
-
OUT92
O3
GPTA0 Output 92
P3.11
I/O0
REQ1
I
Reserved
O1
-
Reserved
O2
-
OUT93
O3
GPTA0 Output 93
Data Sheet
,
GPTA0 Output 91
A1/
PU
A1/
PU
Port 3 General Purpose I/O Line 10
External Request Input 0
Port 3 General Purpose I/O Line 11
External Request Input 1
3-19
V 1.1.1, 2014-05
TC1784
PinningTC1784 Pin Configuration
Table 3-1
Pin Definitions and Functions (PG-LFBGA-292-6) (cont’d)
Pin
Symbol
Ctrl. Type Function
B15
P3.12
I/O0
RXDCAN0
I
RXD0B
I
ASC0 Receiver Input B
RXD0B
O1
ASC0 Receiver Output B (Synchronous Mode)
RXD0B
O2
ASC0 Receiver Output B (Synchronous Mode)
OUT94
O3
GPTA0 Output 94
P3.13
I/O0
TXDCAN0
O1
TXD0
O2
A15
B16
A16
A1/
PU
A2/
PU
Port 3 General Purpose I/O Line 12
CAN Node 0 Receiver Input
Port 3 General Purpose I/O Line 13
CAN Node 0 Transmitter Output
ASC0 Transmit Output
OUT95
O3
P3.14
I/O0
RXDCAN1
I
RXD1B
I
ASC1 Receiver Input B
SDI2
I
MSC0 Serial Data Input 2
RXD1B
O1
ASC1 Receiver Output B (Synchronous Mode)
RXD1B
O2
ASC1 Receiver Output B (Synchronous Mode)
OUT96
O3
GPTA0 Output 96
P3.15
I/O0
TXDCAN1
O1
TXD1
O2
ASC1 Transmit Output
OUT97
O3
GPTA0 Output 97
P4.0
I/O0
IN28
I
IN52
I
GPTA0 Input 52
RXDCAN2
I
CAN Node 2 Receiver Input
OUT28
O1
GPTA0 Output 28
OUT28
O1
GPTA0 Output 28
OUT52
O2
GPTA0 Output 52
GPTA0 Output 95
A1/
PU
A2/
PU
Port 3 General Purpose I/O Line 14
CAN Node 1 Receiver Input
Port 3 General Purpose I/O Line 15
CAN Node 1 Transmitter Output
Port 4
T13
Data Sheet
,
A1+/
PU
Port 4 General Purpose I/O Line 0
GPTA0 Input 28
3-20
V 1.1.1, 2014-05
TC1784
PinningTC1784 Pin Configuration
Table 3-1
Pin Definitions and Functions (PG-LFBGA-292-6) (cont’d)
Pin
Symbol
Ctrl. Type Function
U13
P4.1
I/O0
IN29
I
IN53
I
GPTA0 Input 53
OUT29
O1
GPTA0 Output 29
OUT53
O2
GPTA0 Output 53
TXDCAN2
O3
CAN Node 2 Transmitter Output
W13 P4.2
Y13
I/O0
A1+/
PU
A2/
PU
Port 4 General Purpose I/O Line 1
GPTA0 Input 29
Port 4 General Purpose I/O Line 2
IN30
I
IN54
I
GPTA0 Input 54
OUT30
O1
GPTA0 Output 30
OUT54
O2
GPTA0 Output 54
EXTCLK1
O3
External Clock 1 Output
A2/
PU
GPTA0 Input 30
P4.3
I/O0
IN31
I
IN55
I
GPTA0 Input 55
OUT31
O1
GPTA0 Output 31
OUT55
O2
GPTA0 Output 55
EXTCLK0
O3
External Clock 0 Output
P5.0
I/O0
IN40
I
IN26
I
LTCA2 Input 26
OUT40
O1
GPTA0 Output 40
OUT8
O2
LTCA2 Output 8
SLSO20
O3
SSC2 Slave Select Output 0
Port 4 General Purpose I/O Line 3
GPTA0 Input 31
Port 5
D1
Data Sheet
,
A1+/
PU
Port 5 General Purpose I/O Line 0
GPTA0 Input 40
3-21
V 1.1.1, 2014-05
TC1784
PinningTC1784 Pin Configuration
Table 3-1
Pin Definitions and Functions (PG-LFBGA-292-6) (cont’d)
Pin
Symbol
Ctrl. Type Function
E2
P5.1
I/O0
IN41
I
IN27
I
LTCA2 Input 27
OUT41
O1
GPTA0 Output 41
OUT9
O2
LTCA2 Output 9
SLSO21
O3
SSC2 Slave Select Output 1
P5.2
I/O0
IN42
I
IN28
I
LTCA2 Input 28
OUT42
O1
GPTA0 Output 42
OUT10
O2
LTCA2 Output 10
SLSO22
O3
SSC2 Slave Select Output 2
F4
G5
H5
A1+/
PU
A1+/
PU
A1+/
PU
Port 5 General Purpose I/O Line 1
GPTA0 Input 41
Port 5 General Purpose I/O Line 2
GPTA0 Input 42
P5.3
I/O0
IN43
I
OUT43
O1
GPTA0 Output 43
OUT11
O2
LTCA2 Output 11
SLSO23
O3
SSC2 Slave Select Output 3
A1+/
PU
Port 5 General Purpose I/O Line 3
GPTA0 Input 43
P5.4
I/O0
IN44
I
IN29
I
LTCA2 Input 29
Port 5 General Purpose I/O Line 4
GPTA0 Input 44
SLSI2A
I
SSC2 Slave Select Input A
OUT44
O1
GPTA0 Output 44
OUT12
O2
LTCA2 Output 12
SLSO24
O3
SSC2 Slave Select Output 4
Data Sheet
,
3-22
V 1.1.1, 2014-05
TC1784
PinningTC1784 Pin Configuration
Table 3-1
Pin Definitions and Functions (PG-LFBGA-292-6) (cont’d)
Pin
Symbol
Ctrl. Type Function
E1
P5.5
I/O0
IN45
I
IN30
I
LTCA2 Input 30
MRST2A
I
SSC2 Master Receive Input (Master Mode)
OUT45
O1
GPTA0 Output 45
OUT13
O2
LTCA2 Output 13
MRST2
O3
SSC2 Slave Transmit Output (Slave Mode)
F1
F2
H2
J2
A1+/
PU
A1+/
PU
Port 5 General Purpose I/O Line 5
GPTA0 Input 45
P5.6
I/O0
IN46
I
IN31
I
LTCA2 Input 31
MTSR2A
I
SSC2 Slave Receive Input (Slave Mode)
OUT46
O1
GPTA0 Output 46
OUT14
O2
LTCA2 Output 14
MTSR2
O3
SSC2 Master Transmit Output (Master Mode)
P5.7
I/O0
IN47
I
SCLK2A
I
SSC0 Clock Input (Slave Mode)
OUT47
O1
GPTA0 Output 47
OUT15
O2
LTCA2 Output 15
SCLK2
O3
SSC0 Clock Output (Master Mode)
A1+/
PU
A2/
PU
Port 5 General Purpose I/O Line 6
GPTA0 Input 46
Port 5 General Purpose I/O Line 7
GPTA0 Input 47
P5.8
I/O0
RDATA0B
I
Reserved
O1
-
TXDA1
O2
E-Ray Channel A transmit Data Output
OUT89
O3
LTCA2 Output 89
MLI0 Receiver Data Input B
P5.9
I/O0
RVALID0B
I
Reserved
O1
-
TXDB1
O2
E-Ray Channel B transmit Data Output
OUT90
O3
LTCA2 Output 90
Data Sheet
,
A2/
PU
Port 5 General Purpose I/O Line 8
Port 5 General Purpose I/O Line 9
MLI0 Receiver Data Valid Input B
3-23
V 1.1.1, 2014-05
TC1784
PinningTC1784 Pin Configuration
Table 3-1
Pin Definitions and Functions (PG-LFBGA-292-6) (cont’d)
Pin
Symbol
Ctrl. Type Function
J1
P5.10
I/O0
RREADY0B
O1
TXENA
O2
E-Ray Channel A transmit Data Output enable
OUT91
O3
LTCA2 Output 91
K2
K1
L2
L1
H1
A2/
PU
A2/
PU
Port 5 General Purpose I/O Line 10
MLI0 Receiver Ready Input B
P5.11
I/O0
RCLK0B
I
Reserved
O1
-
TXENB
O2
E-Ray Channel B transmit Data Output enable
OUT92
O3
LTCA2 Output 92
P5.12
I/O0
TDATA0
O1
SLSO07
O2
OUT93
O3
P5.13
I/O0
TVALID0B
O1
SLSO16
O2
SSC1 Slave Select Output 6
Reserved
O3
-
A1+/
PU
Port 5 General Purpose I/O Line 11
MLI0 Receiver Clock Input B
Port 5 General Purpose I/O Line 12
MLI0 Transmitter Data Output
SSC0 Slave Select Output 7
LTCA2 Output 93
A1+/
PU
A1+/
PU
Port 5 General Purpose I/O Line 13
MLI0 Transmitter Valid Input B
P5.14
I/O0
TREADY0B
I
RXDA1
I
E-Ray Channel A Receive Data Input 1
Reserved
O1
-
Reserved
O2
-
OUT94
O3
LTCA2 Output 94
A1+/
PU
Port 5 General Purpose I/O Line 14
MLI0 Transmitter Ready Input B
P5.15
I/O0
RXDB1
I
TCLK0
O1
MLI0 Transmitter Clock Output
Reserved
O2
-
OUT95
O3
LTCA2 Output 95
Port 5 General Purpose I/O Line 15
E-Ray Channel B Receive Data Input 1
Port 6
Data Sheet
,
3-24
V 1.1.1, 2014-05
TC1784
PinningTC1784 Pin Configuration
Table 3-1
Pin Definitions and Functions (PG-LFBGA-292-6) (cont’d)
Pin
Symbol
Ctrl. Type Function
A10
P6.0
I/O0
IN14
I
FCLN0
O1
MSC0 Clock Output Negative
OUT80
O2
GPTA0 Output 80
OUT4
O3
P6.1
I/O0
IN15
I
B10
A9
B9
F/
PU
Port 6 General Purpose I/O Line 0
LTCA2 Input 14
LTCA2 Output 4
F/
PU
Port 6 General Purpose I/O Line 1
LTCA2 Input 15
FCLP0A
O1
MSC0 Clock Output Positive A
OUT81
O2
GPTA0 Output 81
OUT5
O3
P6.2
I/O0
IN24
I
LTCA2 Output 5
F/
PU
Port 6 General Purpose I/O Line 2
LTCA2 Input 24
SON0
O1
MSC0 Serial Data Output Negative
OUT82
O2
GPTA0 Output 82
OUT6
O3
LTCA2 Output 6
P6.3
I/O0
IN25
I
F/
PU
Port 6 General Purpose I/O Line 3
LTCA2 Input 25
SOP0A
O1
MSC0 Serial Data Output Positive A
OUT83
O2
GPTA0 Output 83
OUT7
O3
LTCA2 Output 7
P7.0
I/O0
AD0
I/O
OUT32
O1
GPTA0 Output 32
Reserved
O2
-
Reserved
O3
-
Port 7
U16
Data Sheet
,
A2/
PU
Port 7 General Purpose I/O Line 0
EBU Address/Data Bus Line 0
3-25
V 1.1.1, 2014-05
TC1784
PinningTC1784 Pin Configuration
Table 3-1
Pin Definitions and Functions (PG-LFBGA-292-6) (cont’d)
Pin
Symbol
Ctrl. Type Function
Y14
P7.1
I/O0
R17
U14
T14
Y15
A2/
PU
Port 7 General Purpose I/O Line 1
AD1
I/O
OUT33
O1
GPTA0 Output 33
Reserved
O2
-
EBU Address/Data Bus Line 1
Reserved
O3
P7.2
I/O0
AD2
I/O
OUT34
O1
GPTA0 Output 34
Reserved
O2
-
A2/
PU
Port 7 General Purpose I/O Line 2
EBU Address/Data Bus Line 2
Reserved
O3
P7.3
I/O0
AD3
I/O
OUT35
O1
GPTA0 Output 35
Reserved
O2
-
Reserved
O3
-
A2/
PU
A2/
PU
Port 7 General Purpose I/O Line 3
EBU Address/Data Bus Line 3
P7.4
I/O0
AD4
I/O
OUT36
O1
GPTA0 Output 36
Reserved
O2
-
Reserved
O3
-
EBU Address/Data Bus Line 4
P7.5
I/O0
AD5
I/O
OUT37
O1
GPTA0 Output 37
Reserved
O2
-
Reserved
O3
-
W14 P7.6
I/O0
A2/
PU
Port 7 General Purpose I/O Line 4
A2/
PU
Port 7 General Purpose I/O Line 5
EBU Address/Data Bus Line 5
Port 7 General Purpose I/O Line 6
AD6
I/O
OUT38
O1
GPTA0 Output 38
Reserved
O2
-
Reserved
O3
-
Data Sheet
,
EBU Address/Data Bus Line 6
3-26
V 1.1.1, 2014-05
TC1784
PinningTC1784 Pin Configuration
Table 3-1
Pin Definitions and Functions (PG-LFBGA-292-6) (cont’d)
Pin
Symbol
Ctrl. Type Function
T15
P7.7
I/O0
U15
I/O
OUT39
O1
GPTA0 Output 39
Reserved
O2
-
EBU Address/Data Bus Line 7
Reserved
O3
P7.8
I/O0
AD8
I/O
OUT40
O1
GPTA0 Output 40
Reserved
O2
-
Reserved
A2/
PU
O3
I/O0
Port 7 General Purpose I/O Line 8
EBU Address/Data Bus Line 8
A2/
PU
Port 7 General Purpose I/O Line 9
AD9
I/O
OUT41
O1
GPTA0 Output 41
Reserved
O2
-
Reserved
O3
-
P7.10
I/O0
AD10
I/O
OUT42
O1
GPTA0 Output 42
Reserved
O2
-
Reserved
O3
-
W17 P7.11
Y18
Port 7 General Purpose I/O Line 7
AD7
W15 P7.9
Y17
A2/
PU
I/O0
A2/
PU
A2/
PU
EBU Address/Data Bus Line 9
Port 7 General Purpose I/O Line 10
EBU Address/Data Bus Line 10
Port 7 General Purpose I/O Line 11
AD11
I/O
OUT43
O1
GPTA0 Output 43
Reserved
O2
-
Reserved
O3
-
P7.12
I/O0
AD12
I/O
OUT44
O1
GPTA0 Output 44
Reserved
O2
-
Reserved
O3
-
Data Sheet
,
A2/
PU
EBU Address/Data Bus Line 11
Port 7 General Purpose I/O Line 12
EBU Address/Data Bus Line 12
3-27
V 1.1.1, 2014-05
TC1784
PinningTC1784 Pin Configuration
Table 3-1
Pin
Pin Definitions and Functions (PG-LFBGA-292-6) (cont’d)
Symbol
W18 P7.13
Y19
V20
Ctrl. Type Function
I/O0
A2/
PU
Port 7 General Purpose I/O Line 13
AD13
I/O
OUT45
O1
GPTA0 Output 45
Reserved
O2
-
EBU Address/Data Bus Line 13
Reserved
O3
P7.14
I/O0
AD14
I/O
OUT46
O1
GPTA0 Output 46
Reserved
O2
-
A2/
PU
Port 7 General Purpose I/O Line 14
EBU Address/Data Bus Line 14
Reserved
O3
P7.15
I/O0
AD15
I/O
OUT47
O1
GPTA0 Output 47
Reserved
O2
-
Reserved
O3
-
P8.0
I/O0
A2/
PU
Port 7 General Purpose I/O Line 15
EBU Address/Data Bus Line 15
Port 8
U19
U20
A2/
PU
Port 8 General Purpose I/O Line 0
Reserved
O1
OUT48
O2
GPTA0 Output 48
OUT95
O3
LTCA2 Output 95
A16
O
P8.1
I/O0
Reserved
O1
OUT49
O2
GPTA0 Output 49
OUT96
O3
LTCA2 Output 96
A17
O
EBU Address Bus Line Output 17
Data Sheet
,
-
EBU Address Bus Line Output 16
A2/
PU
Port 8 General Purpose I/O Line 1
-
3-28
V 1.1.1, 2014-05
TC1784
PinningTC1784 Pin Configuration
Table 3-1
Pin Definitions and Functions (PG-LFBGA-292-6) (cont’d)
Pin
Symbol
Ctrl. Type Function
T19
P8.2
I/O0
T20
N20
R20
R19
P20
A2/
PU
Port 8 General Purpose I/O Line 2
Reserved
O1
OUT50
O2
GPTA0 Output 50
OUT97
O3
LTCA2 Output 97
A18
O
P8.3
I/O0
Reserved
O1
OUT51
O2
GPTA0 Output 51
OUT98
O3
LTCA2 Output 98
A19
O
P8.4
I/O0
Reserved
O1
OUT52
O2
GPTA0 Output 52
OUT99
O3
LTCA2 Output 99
A20
O
EBU Address Bus Line Output 20
P8.5
I/O0
Reserved
O1
-
EBU Address Bus Line Output 18
A2/
PU
Port 8 General Purpose I/O Line 3
-
EBU Address Bus Line Output 19
A2/
PU
A2/
PU
Port 8 General Purpose I/O Line 4
-
Port 8 General Purpose I/O Line 5
-
OUT53
O2
GPTA0 Output 53
OUT100
O3
LTCA2 Output 100
CS0
O
EBU Chip Select Output 0
P8.6
I/O0
Reserved
O1
A2/
PU
OUT54
O2
OUT101
O3
LTCA2 Output 101
CS1
O
EBU Chip Select Output 1
Port 8 General Purpose I/O Line 6
GPTA0 Output 54
P8.7
I/O0
Reserved
O1
OUT55
O2
OUT102
O3
LTCA2 Output 102
CS2
O
EBU Chip Select Output 2
Data Sheet
,
A2/
PU
Port 8 General Purpose I/O Line 7
GPTA0 Output 55
3-29
V 1.1.1, 2014-05
TC1784
PinningTC1784 Pin Configuration
Table 3-1
Pin Definitions and Functions (PG-LFBGA-292-6) (cont’d)
Pin
Symbol
Ctrl. Type Function
P19
P8.8
I/O0
P17
P16
N19
N17
N16
A2/
PU
Port 8 General Purpose I/O Line 8
Reserved
O1
OUT56
O2
GPTA0 Output 56
OUT103
O3
LTCA2 Output 103
CS3
O
P8.9
I/O0
Reserved
O1
-
EBU Chip Select Output 3
A2/
PU
Port 8 General Purpose I/O Line 9
-
OUT57
O2
GPTA0 Output 57
OUT104
O3
LTCA2 Output 104
BC0
O
P8.10
I/O0
Reserved
O1
EBU Byte Control Line Output 0
A2/
PU
Port 8 General Purpose I/O Line 10
-
OUT58
O2
GPTA0 Output 58
OUT105
O3
LTCA2 Output 105
BC1
O
EBU Byte Control Line Output 1
P8.11
I/O0
Reserved
O1
A2/
PU
Port 8 General Purpose I/O Line 11
-
OUT59
O2
GPTA0 Output 59
OUT106
O3
LTCA2 Output 106
RD
O
EBU Read Control Line
P8.12
I/O0
Reserved
O1
A2/
PU
OUT60
O2
OUT107
O3
LTCA2 Output 107
RD/WR
O
EBU Write Control Line
Port 8 General Purpose I/O Line 12
GPTA0 Output 60
P8.13
I/O0
Reserved
O1
OUT61
O2
GPTA0 Output 61
OUT108
O3
LTCA2 Output 108
ADV
O
EBU Address Valid Line
Data Sheet
,
A2/
PU
Port 8 General Purpose I/O Line 13
-
3-30
V 1.1.1, 2014-05
TC1784
PinningTC1784 Pin Configuration
Table 3-1
Pin Definitions and Functions (PG-LFBGA-292-6) (cont’d)
Pin
Symbol
Ctrl. Type Function
M17
P8.14
I/O0
A1/
PU
Port 8 General Purpose I/O Line 14
WAIT
I
Reserved
O1
-
OUT62
O2
GPTA0 Output 62
OUT109
O3
LTCA2 Output 109
P9.0
I/O0
RXDCAN2
I
Reserved
O1
-
OUT80
O2
GPTA0 Output 80
OUT80
O3
LTCA2 Output 80
P9.1
I/O0
EBU Wait Line
Port 9
G4
H4
J5
J4
A1/
PU
A2/
PU
Port 9 General Purpose I/O Line 0
CAN Node 2 Receiver Input
Port 9 General Purpose I/O Line 1
Reserved
I
TXDCAN2
O1
CAN Node 2 Transmitter Output
OUT81
O2
GPTA0 Output 81
OUT81
O3
P9.2
I/O0
Reserved
I
Reserved
O1
-
OUT82
O2
GPTA0 Output 82
OUT82
O3
P9.3
I/O0
Reserved
I
-
LTCA2 Output 81
A1/
PU
Port 9 General Purpose I/O Line 2
-
LTCA2 Output 82
A1/
PU
Port 9 General Purpose I/O Line 3
-
Reserved
O1
-
OUT83
O2
GPTA0 Output 83
OUT83
O3
LTCA2 Output 83
Data Sheet
,
3-31
V 1.1.1, 2014-05
TC1784
PinningTC1784 Pin Configuration
Table 3-1
Pin Definitions and Functions (PG-LFBGA-292-6) (cont’d)
Pin
Symbol
Ctrl. Type Function
K4
P9.4
I/O0
Reserved
I
Reserved
O1
-
OUT84
O2
GPTA0 Output 84
OUT84
O3
P9.5
I/O0
Reserved
I
K5
L4
L5
A1/
PU
Port 9 General Purpose I/O Line 4
-
LTCA2 Output 84
A1/
PU
Port 9 General Purpose I/O Line 5
-
Reserved
O1
-
OUT85
O2
GPTA0 Output 85
OUT85
O3
P9.6
I/O0
Reserved
I
LTCA2 Output 85
A1/
PU
Port 9 General Purpose I/O Line 6
-
Reserved
O1
-
OUT86
O2
GPTA0 Output 86
OUT86
O3
LTCA2 Output 86
P9.7
I/O0
Reserved
I
A1/
PU
Port 9 General Purpose I/O Line 7
-
Reserved
O1
-
OUT87
O2
GPTA0 Output 87
OUT87
O3
LTCA2 Output 87
Port 10
D6
P10.0
I/O0
MRST2B
I
MRST2
O1
SSC2 Master Transmit Input (Slave Mode)
EVTO0
O2
MCDS Event Output 0
Reserved
O3
-
Data Sheet
,
A1+/
PU
Port 10 General Purpose I/O Line 0
SSC2 Master Receive Input (Master Mode)
3-32
V 1.1.1, 2014-05
TC1784
PinningTC1784 Pin Configuration
Table 3-1
Pin Definitions and Functions (PG-LFBGA-292-6) (cont’d)
Pin
Symbol
Ctrl. Type Function
E6
P10.1
I/O0
D5
B5
A5
B4
A4
A1+/
PU
Port 10 General Purpose I/O Line 1
Reserved
I
MTSR2
O1
SSC0 Slave Receive Input (Slave Mode)
EVTO1
O2
MCDS Event Output 1
-
Reserved
O3
P10.2
I/O0
SCLK2B
I
SCLK2
O1
SSC0 Clock Output (Master Mode)
EVTO2
O2
MCDS Event Output 2
Reserved
O3
P10.3
I/O0
SLSI2B
I
A1+/
PU
Port 10 General Purpose I/O Line 2
SSC0 Clock Input (Slave Mode)
A1+/
PU
Port 10 General Purpose I/O Line 3
SSC2 Slave Select Input B
SLSO20
O1
SSC2 Slave Select Output 0
EVTO3
O2
MCDS Event Output 3
Reserved
O3
LTCA2 Output 83
P10.4
I/O0
Reserved
I
SLSO21
O1
SSC2 Slave Select Output 1
Reserved
O2
GPTA0 Output 84
Reserved
O3
-
P10.5
I/O0
Reserved
I
SLSO22
O1
SSC2 Slave Select Output 0
Reserved
O2
GPTA0 Output 85
Reserved
O3
-
P10.6
I/O0
Reserved
I
SLSO23
O1
SSC2 Slave Select Output 3
SLSOAND03
O2
SSC0 AND SSC2 Slave Select Output 3
Reserved
O3
-
Data Sheet
,
A1+/
PU
A1+/
PU
A1+/
PU
Port 10 General Purpose I/O Line 4
-
Port 10 General Purpose I/O Line 5
-
Port 10 General Purpose I/O Line 6
-
3-33
V 1.1.1, 2014-05
TC1784
PinningTC1784 Pin Configuration
Table 3-1
Pin Definitions and Functions (PG-LFBGA-292-6) (cont’d)
Pin
Symbol
Ctrl. Type Function
B3
P10.7
I/O0
Reserved
I
SLSO24
O1
SSC2 Slave Select Output 4
SLSOAND04
O2
SSC1 AND SSC2 Slave Select Output 4
A3
A2
C1
D2
E4
A1+/
PU
Port 10 General Purpose I/O Line 7
-
Reserved
O3
P10.8
I/O0
Reserved
I
Reserved
O1
-
Reserved
O2
-
A1/
PU
Port 10 General Purpose I/O Line 8
-
Reserved
O3
P10.9
I/O0
Reserved
I
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
A1/
PU
A1/
PU
Port 10 General Purpose I/O Line 9
-
P10.10
I/O0
RXDCAN2
I
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
CAN Node 2 Receiver Input
P10.11
I/O0
Reserved
I
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
P10.12
I/O0
Reserved
I
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
Data Sheet
,
A1/
PU
Port 10 General Purpose I/O Line 10
A1/
PU
Port 10 General Purpose I/O Line 11
-
Port 10 General Purpose I/O Line 12
-
3-34
V 1.1.1, 2014-05
TC1784
PinningTC1784 Pin Configuration
Table 3-1
Pin Definitions and Functions (PG-LFBGA-292-6) (cont’d)
Pin
Symbol
Ctrl. Type Function
F5
P10.13
I/O0
Reserved
I
Reserved
O1
-
Reserved
O2
-
Reserved
O3
-
A1/
PU
Port 10 General Purpose I/O Line 13
-
Analog Input Port
Y9
AN0
W9
AN1
T9
AN2
U8
AN3
Y8
AN4
W8
I
D
Analog Input 0
I
D
Analog Input 1
I
D
Analog Input 2
I
D
Analog Input 3
I
D
Analog Input 4
AN5
I
D
Analog Input 5
T8
AN6
I
D
Analog Input 6
T2
AN7
I
D
Analog Input 7
U7
AN8
I
D
Analog Input 8
Y6
AN9
I
D
Analog Input 9
Y5
AN10
I
D
Analog Input 10
Y4
AN11
I
D
Analog Input 11
Y3
AN12
I
D
Analog Input 12
Y2
AN13
I
D
Analog Input 13
W2
AN14
I
D
Analog Input 14
U5
AN15
I
D
Analog Input 15
W3
AN16
I
D
Analog Input 16
W5
AN17
I
D
Analog Input 17
W4
AN18
I
D
Analog Input 18
W6
AN19
I
D
Analog Input 19
W1
AN20
I
D
Analog Input 20
U4
AN21
I
D
Analog Input 21
V2
AN22
I
D
Analog Input 22
V1
AN23
I
D
Analog Input 23
Data Sheet
,
3-35
V 1.1.1, 2014-05
TC1784
PinningTC1784 Pin Configuration
Table 3-1
Pin Definitions and Functions (PG-LFBGA-292-6) (cont’d)
Pin
Symbol
Ctrl. Type Function
T5
AN24
I
D
Analog Input 24
T4
AN25
I
D
Analog Input 25
U2
AN26
I
D
Analog Input 26
U1
AN27
I
D
Analog Input 27
T1
AN28
I
D
Analog Input 28
R5
AN29
I
D
Analog Input 29
R4
AN30
I
D
Analog Input 30
R2
AN31
I
D
Analog Input 31
R1
AN32
I
D
Analog Input 32
P5
AN33
I
D
Analog Input 33
P4
AN34
I
D
Analog Input 34
P1
AN35
I
D
Analog Input 35
Y7
VDDM
VSSM
VAREF0
VAREF1
VAGND0
VDDMF
VDDAF
VSSMF
VSSAF
VFAREF
VFAGND
-
-
ADC Analog Part Power Supply (3.3V - 5V)
-
-
ADC Analog Part Ground
-
-
ADC0 Reference Voltage
-
-
ADC1 Reference Voltage
-
-
ADC Reference Ground
-
-
FADC Analog Part Power Supply (3.3V)
-
-
FADC Analog Part Logic Power Supply (1.3V)
-
-
FADC Analog Part Ground
-
-
FADC Analog Part Ground
-
-
FADC Reference Voltage
-
-
FADC Reference Ground
W7
U6
T7
T6
N1
N2
P2
P2
N4
N5
Data Sheet
,
3-36
V 1.1.1, 2014-05
TC1784
PinningTC1784 Pin Configuration
Table 3-1
Pin
Pin Definitions and Functions (PG-LFBGA-292-6) (cont’d)
Symbol
Ctrl. Type Function
G8, VDD
G13,
H7,
H14,
N7,
N14,
P8,
P13,
R16,
T17,
V19,
W20
-
-
Digital Core Power Supply (1.3V)
VDDP
B1,
B6,
B11,
B20,
C2,
C19,
G2,
M2,
M19,
W10,
W16
-
-
Port Power Supply (3.3V)
M4,
M5
-
-
Emulation Stand-by SRAM Power Supply
(1.3V) (Emulation device only)
VDDE(SB)
Note: This pin is N.C. in a productive device.
Data Sheet
,
3-37
V 1.1.1, 2014-05
TC1784
PinningTC1784 Pin Configuration
Table 3-1
Pin
Pin Definitions and Functions (PG-LFBGA-292-6) (cont’d)
Symbol
Ctrl. Type Function
A6,
VSSP
A11,
A20,
B2,
B19,
D4,
D17,
E5,
E16,
G1,
M1,
M20,
Y10,
Y16
-
-
Digital Ground
G9, VSS
G10,
G11,
G12
-
-
Digital Ground
H9, VSS
H10,
H11,
H12
-
-
Digital Ground
J7,
J8,
J10,
J11,
J13,
J14
VSS
-
-
Digital Ground
K7,
VSS
K8,
K9,
K10,
K11,
K12,
K13,
K14
-
-
Digital Ground
Data Sheet
,
3-38
V 1.1.1, 2014-05
TC1784
PinningTC1784 Pin Configuration
Table 3-1
Pin Definitions and Functions (PG-LFBGA-292-6) (cont’d)
Pin
Symbol
Ctrl. Type Function
L7,
L8,
L9,
L10,
L11,
L12,
L13,
L14
VSS
-
-
Digital Ground
M7, VSS
M8,
M10,
M11,
M13,
M14
-
-
Digital Ground
N9, VSS
N10,
N11,
N12
-
-
Digital Ground (cont´d)
P9,
VSS
P10,
P11,
P12
-
-
Digital Ground (cont´d)
T16, VSS
U17,
W19,
Y20
-
-
Digital Ground (cont´d)
K19
-
-
Main Oscillator and PLL Power Supply (1.3V)
-
-
Main Oscillator Power Supply (3.3V)
-
-
Flexray Oscillator and PLL Power Supply
(1.3V)
J17
VDDPF3
VSSOSC
D13, VDDFL3
-
-
Flexray Oscillator Power Supply (3.3V)
K20
-
-
Main Oscillator and PLL Ground
-
-
Power Supply for Flash (3.3V)
J20
XTAL1
I
Oscillator/PLL/Clock Generator Input
J19
XTAL2
O
Oscillator/PLL/Clock Generator Output
H20
K17
VDDOSC
VDDOSC3
VDDPF
D14
Data Sheet
,
3-39
V 1.1.1, 2014-05
TC1784
PinningTC1784 Pin Configuration
Table 3-1
Pin Definitions and Functions (PG-LFBGA-292-6) (cont’d)
Pin
Symbol
Ctrl. Type Function
H19
TDI
I
BRKIN
I
BRKOUT
O
H17
TMS
I
DAP1
I/O
G20
TDO
I/O
DAP2
I/O
BRKIN
I
OCDS Break Input (Alternate Input)
BRKOUT
O
OCDS Break Output (Alternate Output)
G19
TRST
I
A1/
PD
JTAG Reset Input
F20
TCK
I
JTAG Clock Input
DAP0
I
A1/
PD
F19
TESTMODE
I
PU
Test Mode Select Input
E19
ESR1
I/O
A2/
PD
External System Request Reset Input 1
E20
PORST
I
PD
Power On Reset Input
D20
ESR0
I/O
A2
External System Request Reset Input 0
Default configuration during and after reset is
open-drain driver. The driver drives low during
power-on reset.
A1,
Y1
N.C.
-
-
Not connected. These pins are reserved for
future extension and shall not be connected
externally
A2/
PU
JTAG Serial Data Input
OCDS Break Input (Alternate Input)
OCDS Break Output (Alternate Output)
A2/
PD
JTAG State Machine Control Input
A2/
PU
JTAG Serial Data Output
Device Access Port Line 1
Device Access Port Line 2
Device Access Port Line 0
Legend for Table 3-1
Column “Ctrl.”:
I = Input (for GPIO port lines with IOCR bit field selection PCx = 0XXXB)
O = Output
O0 = Output with IOCR bit field selection PCx = 1X00B
O1 = Output with IOCR bit field selection PCx = 1X01B (ALT1)
O2 = Output with IOCR bit field selection PCx = 1X10B(ALT2)
O3 = Output with IOCR bit field selection PCx = 1X11(ALT3)
Column “Type”:
Data Sheet
,
3-40
V 1.1.1, 2014-05
TC1784
PinningTC1784 Pin Configuration
A1 = Pad class A1 (LVTTL)
A1+ = Pad class A1+ (LVTTL)
A2 = Pad class A2 (LVTTL)
F = Pad class F (LVDS/CMOS)
D = Pad class D (ADC)
I = Pad class I (LVTTL)
PU = with pull-up device connected during reset (PORST = 0)
PD = with pull-down device connected during reset (PORST = 0)
TR = tri-state during reset (PORST = 0)
Data Sheet
,
3-41
V 1.1.1, 2014-05
TC1784
Identification Registers
4
Identification Registers
The Identification Registers uniquely identify the whole device.
Table 2
SAK-TC1784F-320F180EL Identification Registers
Short Name
Value
Address
Stepping
CBS_JDPID
0000 6350H
F000 0408H
BA
CBS_JTAGID
1018 E083H
F000 0464H
BA
SCU_CHIPID
0500 9610H
F000 0640H
BA
SCU_MANID
0000 1820H
F000 0644H
BA
SCU_RTID
0000 0000H
F000 0648H
BA
Table 3
SAK-TC1784F-320F180EP Identification Registers
Short Name
Value
Address
Stepping
CBS_JDPID
0000 6350H
F000 0408H
BA
CBS_JTAGID
1018 E083H
F000 0464H
BA
SCU_CHIPID
8500 9610H
F000 0640H
BA
SCU_MANID
0000 1820H
F000 0644H
BA
SCU_RTID
0000 0000H
F000 0648H
BA
Data Sheet
42
V 1.1.1, 2014-05
TC1784
Identification Registers
Data Sheet
43
V 1.1.1, 2014-05
TC1784
Electrical ParametersGeneral Parameters
5
Electrical Parameters
This specification provides all electrical parameters of the TC1784.
5.1
General Parameters
5.1.1
Parameter Interpretation
The parameters listed in this section partly represent the characteristics of the TC1784
and partly its requirements on the system. To aid interpreting the parameters easily
when evaluating them for a design, they are marked with an two-letter abbreviation in
column “Symbol”:
•
•
CC
Such parameters indicate Controller Characteristics which are a distinctive feature of
the TC1784 and must be regarded for a system design.
SR
Such parameters indicate System Requirements which must provided by the
microcontroller system in which the TC1784 designed in.
Data Sheet
44
V 1.1.1, 2014-05
TC1784
Electrical ParametersGeneral Parameters
5.1.2
Pad Driver and Pad Classes Summary
This section gives an overview on the different pad driver classes and its basic
characteristics. More details (mainly DC parameters) are defined in the Section 5.2.1.
Table 4
Pad Driver and Pad Classes Overview
Class Power Type
Supply
Sub Class
Speed Load
Grade 1)
Leakage
150oC 1)
Termination
1)
A
F
3.3 V
3.3 V
LVTTL
I/O,
LVTTL
outputs
A1
(e.g. GPIO)
6 MHz
100 pF 500 nA
A1+
(e.g. serial
I/Os)
25
MHz
50 pF
1 μA
Series
termination
recommended
A2
(e.g. serial
I/Os)
40
MHz
50 pF
3 μA
Series
termination
recommended
LVDS
–
50
MHz
–
–
Parallel
termination,
100 Ω ± 10% 2)
CMOS
–
6 MHz
50 pF
–
DE
5V
ADC
–
–
–
–
I
3.3 V
LVTTL
(input
only)
–
–
–
–
No
1) These values show typical application configurations for the pad. Complete and detailed pad parameters are
available in the individual pad parameter table on the following pages.
2) In applications where the LVDS pins are not used (disabled), these pins must be either left unconnected, or
properly terminated with the differential parallel termination of 100 Ω ± 10%.
Data Sheet
45
V 1.1.1, 2014-05
TC1784
Electrical ParametersGeneral Parameters
5.1.3
Absolute Maximum Ratings
Stresses above the values listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Table 5
Absolute Maximum Rating Parameters
Parameter
Symbol
Values
Min. Typ. Max.
Storage temperature
TST
Voltage at 1.3 V power supply VDD
pins with respect to VSS
Voltage at 3.3 V power supply VDDP
pins with respect to VSS
SR
Voltage at 5 V power supply VDDM
pins with respect to VSS
Voltage on any Class A input VIN
Unit Note /
Test Con
dition
SR -65
–
150
°C
–
SR –
–
2.0
V
–
–
–
4.33
V
–
SR –
–
7.0
V
–
SR -0.7 –
VDDP + 0.5 V
or max. 4.33
Whatever
is lower
-0.6 –
7.0
V
–
Voltage on any shared Class VAINF
-0.6 –
D analog input pin with
SR
respect to VSSAF, if the FADC
is switched through to the pin.
7.0
V
–
Input current on any pin
during overload condition
pin and dedicated input pins
with respect to VSS
Voltage on any Class D
analog input pin with respect
to VAGND0
VAIN
VAREFx
SR
IIN
-10
–
+10
mA
–
Absolute maximum sum of all IIN
input circuit currents for one
port group during overload
condition1)
-25
–
+25
mA
–
Absolute maximum sum of all ΣIIN
input circuit currents during
overload condition
-200 –
200
mA
–
1) The port groups are defined in Table 10.
Data Sheet
46
V 1.1.1, 2014-05
TC1784
Electrical ParametersGeneral Parameters
5.1.4
Pin Reliability in Overload
When receiving signals from higher voltage devices, low-voltage devices experience
overload currents and voltages that go beyond their own IO power supplies specification.
Table 6 defines overload conditions that will not cause any negative reliability impact if
all the following conditions are met:
•
•
full operation life-time (24000 h) is not exceeded
Operating Conditions are met for
– pad supply levels (VDDP or VDDM)
– temperature
If a pin current is out of the Operating Conditions but within the overload parameters,
then the parameters functionality of this pin as stated in the Operating Conditions can no
longer be guaranteed. Operation is still possible in most cases but with relaxed
parameters.
Note: An overload condition on one or more pins does not require a reset.
Table 6
Overload Parameters
Parameter
Min. Typ. Max.
Unit Note /
Test Con
dition
Input current on any digital pin IIN
during overload condition
except LVDS pins
-5
mA
Input current on LVDS pins
IINLVDS
IING
-3
–
+3
mA
–
-20
–
+20
mA
–
IINANA
IINSAS
-3
–
+3
mA
–
-15
–
+15
mA
–
ΣIINS
-100 –
100
mA
–
Absolute sum of all input
circuit currents for one port
group during overload
condition1)
Input current on analog pins
Absolute sum of all analog
input currents for analog
inputs of a single ADC during
overload condition
Absolute sum of all input
circuit currents during
overload condition
Symbol
Values
–
+5
–
1) The port groups are defined in Table 10.
Note: FADC input pins count as analog pin as they are overlayed with an ADC pins.
Data Sheet
47
V 1.1.1, 2014-05
TC1784
Electrical ParametersGeneral Parameters
Table 7
PN-Junction Characterisitics for positive Overload
Pad Type
IIN = 3 mA
IIN = 5 mA
A1 / A1+ / F
UIN = VDDP + 0.6 V
UIN = VDDP + 0.5 V
UIN = VDDP + 0.7 V
UIN = VDDM + 0.6 V
UIN = VDDP + 0.7 V
UIN = VDDP + 0.6 V
A2
LVDS
D
Table 8
-
PN-Junction Characterisitics for negative Overload
Pad Type
IIN = -3 mA
IIN = -5 mA
A1 / A1+ / F
UIN = VSS - 0.6 V
UIN = VSS - 0.5 V
UIN = VSS - 0.7 V
UIN = VSSM - 0.6 V
UIN = VSS - 0.7 V
UIN = VSS - 0.6 V
A2
LVDS
D
-
Note: A series resistor at the pin to limit the current to the maximum permitted overload
current is sufficient to handle failure situations like short to battery without having
any negative reliability impact on the operational life-time.
Data Sheet
48
V 1.1.1, 2014-05
TC1784
Electrical ParametersGeneral Parameters
5.1.5
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation and reliability of the TC1784. All parameters specified in the following tables
refer to these operating conditions, unless otherwise noticed.
Digital supply voltages applied to the TC1784 must be static regulated voltages which
allow a typical voltage swing of ± 5 %.
All parameters specified in the following tables (Table 11 and following) refer to these
operating conditions (Table 9), unless otherwise noticed in the Note / Test Condition
column.
The Extended Range Operating Conditions did not increase area of validity of the
parameters defined in table 9 and later.
Table 9
Operating Conditions Parameters
Parameter
Symbol
Overload coupling factor KOVAN
for analog inputs, negative CC
Values
Unit
Min.
Typ.
Max.
−
−
0.0001
Note /
Test Condition
IOV≤ 0 mA;
IOV≥ -2 mA;
analog
pad= 5.0 V
Overload coupling factor KOVAP
for analog inputs, positive CC
−
−
IOV≤ 3 mA;
IOV≥ 0 mA;
0.0000
1
analog
pad= 5.0 V
fCPU SR
FPI bus frequency
fFPI SR
LMB frequency
fLMB CC
fPCP SR
PCP Frequency
Inactive device pin current IID SR
CPU Frequency
−
−
180
MHz
−
−
90
MHz
−
−
180
MHz
−
−
180
MHz
-1
−
1
mA
Short circuit current of
digital outputs1)
ISC SR
-5
−
5
mA
Absolute sum of short
circuit currents of the
device
ΣISC_D
CC
−
−
100
mA
Data Sheet
49
All power
supply
voltagesVDDx =
0
V 1.1.1, 2014-05
TC1784
Electrical ParametersGeneral Parameters
Table 9
Operating Conditions Parameters (cont’d)
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
−
−
20
mA
TA SR
Junction temperature
TJ SR
Core Supply Voltage
VDD SR
Flash supply voltage 3.3V VDDFL3
-40
−
125
°C
-40
−
150
°C
1.235
1.3
1.3652) V
3.13
3.3
3.474)
V
ADC analog supply
voltage
VDDM
3.13
3.3
5.53)
V
VDDOSC
1.235
1.3
1.3652) V
3.3
3.474)
Absolute sum of short
circuit currents per pin
group
ΣISC_PG
CC
Ambient Temperature
Note /
Test Condition
SR
Oscillator core supply
voltage
Oscillator 3.3V supply
voltage
SR
SR
VDDOSC3 3.05
V
SR
VDDPF
1.235
1.3
1.3652) V
E-Ray PLL 3.3V supply
voltage
VDDPF3
3.05
3.3
3.474)
Digital supply voltage for
IO pads
VDDP SR 3.13
3.3
3.47 4) V
VDDP voltage to ensure
defined pad states5)
VDDPPA
0.65
−
−
Digital ground voltage
VSS SR
0
E-Ray PLL core supply
voltage
SR
V
SR
V
CC
Analog ground voltage for VSSM SR -0.1
−
−
V
0
0.1
V
VDDM
VDDAF
1.235
1.3
1.3652) V
VDDMF
3.13
3.3
3.474)
V
Analog ground voltage for VSSAF
SR
-0.1
0
0.1
V
Analog core supply
SR
FADC / ADC analog
supply voltage
SR
VDDMF
1) Applicable for digital outputs.
Data Sheet
50
V 1.1.1, 2014-05
TC1784
Electrical ParametersGeneral Parameters
2) Voltage overshoot to 1.7V is permissible at Power-Up and PORST low, provided the pulse duration is less
than 100 μs and the cumulated sum of the pulses does not exceed 1 h.
3) Voltage overshoot to 6.5V is permissible at Power-Up and PORST low, provided the pulse duration is less
than 100 μs and the cumulated sum of the pulses does not exceed 1 h.
4) Voltage overshoot to 4.0V is permissible at Power-Up and PORST low, provided the pulse duration is less
than 100 μs and the cumulated sum of the pulses does not exceed 1 h.
5) This parameter is valid under the assumption the PORST signal is constantly at low level during the powerup/power-down of VDDP.
Extended Range Operating Conditions
The following extended operating conditions are defined:
•
•
•
1.3V + 5% < VDD / VDDPF / VDDOSC / VDDAF < 1.3V + 7.5% (overvoltage condition):
– limited to 10000 hour duration cumulative in lifetime, due to the reliability reduction
of the chip caused by the overvoltage stress.
1.3V + 7.5% < VDD / VDDOSC / VDDAF < 1.3V + 10% (overvoltage condition):
– limited to 1000 hour duration cumulative in lifetime, due to the reliability reduction
of the chip caused by the overvoltage stress.
VDDP / VDDOSC3 / VDDFL3 / VDDMF< 3.3 V ± 10%
– 3.3V + 5% < VDDP / VDDOSC3 / VDDFL3 / VDDMF< 3.3V + 10%
(overvoltage condition):
limited to 1000 hour duration cumulative in lifetime, due to the reliability reduction
of the chip caused by the overvoltage stress.
– 3.3V - 10% < VDDP / VDDOSC3 / VDDFL3 / VDDMF< 3.3 V − 5%
(undervoltage condition):
-reduces GPIO pads performance
Table 10
Pin Groups for Overload / Short-Circuit Current Sum Parameter
Group
Pins
1
P5.[7:2], P5.15
2
P5.[9:8]
3
P5.[11:10]
4
P5.[14:12]
5
P1.[14:12], P2.0
6
P2.[4:1]
7
P2.[7:5]
8
P4.[2:0]
Data Sheet
51
V 1.1.1, 2014-05
TC1784
Electrical ParametersGeneral Parameters
Table 10
Pin Groups for Overload / Short-Circuit Current Sum Parameter
Group
Pins
9
P4.3
10
P1.2, P1.8
11
P1.[10:9]
12
P1.3, P1.11
13
P1.[7:4]
14
P1.[1:0], P1.15
15
P3.[8:5], P3.[3:2]
16
P3.[1:0], P3.4, P3.[10:9], P3.[15:14]
17
P0.[1:0], P3.[13:11]
18
P0.[3:2], P0.[9:8]
19
P0.[11:10]
20
P6.[3:0]
21
P2.[13:8]
22
P0.[5:4], P0.[13:12]
23
P0.[7:6], P0.[15:14], P5.[1:0]
Data Sheet
52
V 1.1.1, 2014-05
TC1784
Electrical ParametersDC Parameters
5.2
DC Parameters
5.2.1
Input/Output Pins
Table 11
Standard_Pads Parameters
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note /
Test Condition
TA= 25 °C;
f= 1 MHz
Vi≥ 0.6 x VDDP V
Vi≥ 0.36 x
VDDP V
Vi≤ 0.6 x VDDP V
Vi≤ 0.36 x
VDDP V
Pin capacitance (digital
inputs/outputs)
CIO CC
−
−
10
pF
Pull-down current
|IPDL|
CC
−
−
150
μA
10
−
−
μA
|IPUH|
CC
10
−
−
μA
−
−
100
μA
Spike filter always blocked tSF1 CC
pulse duration
−
−
10
ns
only PORST pin
Spike filter pass-through
pulse duration
100
−
−
ns
only PORST pin
Unit
Note /
Test Condition
Pull-Up current
Table 12
tSF2 CC
Standard_Pads Class_A1
Parameter
Input Hysteresis for A1
pads 1)
Input Leakage Current
Class A1
Ratio Vil/Vih, A1 pads
Symbol
Values
Min.
Typ.
Max.
HYSA1
0.1 x
−
−
V
CC
VDDP
IOZA1
-500
−
500
nA
VILA1 /
VIHA1
0.6
−
−
−
450
600
Ohm IOH> -0.5 mA;
P_MOS
−
210
340
Ohm IOL< 0.5 mA;
N_MOS
CC
Vi≥ 0 V;
Vi≤ VDDP V
CC
On-Resistance of the
RDSONW
class A1 pad, weak driver CC
Data Sheet
53
V 1.1.1, 2014-05
TC1784
Electrical ParametersDC Parameters
Table 12
Standard_Pads Class_A1 (cont’d)
Parameter
Symbol
On-Resistance of the
class A1 pad, medium
driver
CC
Fall time, pad type A1
tFA1 CC
RDSONM
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
−
−
155
Ohm IOH> -2 mA;
P_MOS
−
−
110
Ohm IOL< 2 mA;
N_MOS
−
−
150
ns
CL= 20 pF; pin
out
driver= weak
−
−
50
ns
CL= 50 pF; pin
out
driver= medium
−
−
140
ns
CL= 150 pF; pin
out
driver= medium
−
−
550
ns
CL= 150 pF; pin
out
driver= weak
−
−
18000
ns
CL= 20000 pF;
pin out
driver= medium
−
−
65000
ns
CL= 20000 pF;
pin out
driver= weak
Data Sheet
54
V 1.1.1, 2014-05
TC1784
Electrical ParametersDC Parameters
Table 12
Standard_Pads Class_A1 (cont’d)
Parameter
Symbol
Values
Min.
Rise time, pad type A1
Typ.
Max.
tRA1 CC −
−
150
−
−
Unit
Note /
Test Condition
ns
CL= 20 pF; pin
out
driver= weak
50
ns
CL= 50 pF; pin
out
driver= medium
−
−
140
ns
CL= 150 pF; pin
out
driver= medium
−
−
550
ns
CL= 150 pF; pin
out
driver= weak
−
−
18000
ns
CL= 20000 pF;
pin out
driver= medium
−
−
65000
ns
CL= 20000 pF;
pin out
driver= weak
Input high voltage class
A1 pads
VIHA1
SR
0.6 x
min(V V
DDP+
0.3,3.6
)
−
Input low voltage class A1 VILA1 SR -0.3
pads
Data Sheet
−
VDDP
0.36 x
V
VDDP
55
V 1.1.1, 2014-05
TC1784
Electrical ParametersDC Parameters
Table 12
Standard_Pads Class_A1 (cont’d)
Parameter
Symbol
Values
Min.
Output voltage high class
A1 pads
VOHA1
CC
Typ.
Unit
Note /
Test Condition
V
IOH≥ -1.4 mA;
Max.
VDDP - −
−
−
−
0.4
2.4
pin out
driver= medium
V
IOH≥ -2 mA; pin
out
driver= medium
VDDP - −
−
V
IOH≥ -400 μA;
pin out
driver= weak
2.4
−
−
V
IOH≥ -500 μA;
pin out
driver= weak
−
−
0.4
V
IOL≤ 2 mA; pin
0.4
Output voltage low class
A1 pads
VOLA1
CC
out
driver= medium
−
−
0.4
V
IOL≤ 500 μA;
pin out
driver= weak
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be
guaranteed that it suppresses switching due to external system noise.
Table 13
Standard_Pads Class_A1+
Parameter
Symbol
Input Hysteresis for A1+
pads 1)
HYSA1
+ CC
IOZA1+
VDDP
RDSONW
Input Leakage Current
Class A1+
On-Resistance of the
class A1+ pad, weak
driver
Data Sheet
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
0.1 x
−
−
V
-1000
−
1000
nA
−
450
600
Ohm IOH> -0.5 mA;
P_MOS
−
210
340
Ohm IOL< 0.5 mA;
N_MOS
CC
CC
56
V 1.1.1, 2014-05
TC1784
Electrical ParametersDC Parameters
Table 13
Standard_Pads Class_A1+ (cont’d)
Parameter
Symbol
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
−
−
155
Ohm IOH> -2 mA;
P_MOS
−
−
110
Ohm IOL< 2 mA;
N_MOS
On-Resistance of the
class A1+ pad, strong
driver
RDSON1+ −
−
100
Ohm IOH> -2 mA;
P_MOS
−
−
80
Ohm IOL< 2 mA;
N_MOS
Fall time, pad type A1+
tFA1+ CC −
−
150
ns
−
−
On-Resistance of the
class A1+ pad, medium
driver
RDSONM
CC
CC
CL= 20 pF; pin
out
driver= weak
28
ns
CL= 50 pF;
edge= slow ;
pin out
driver= strong
−
−
16
ns
CL= 50 pF;
edge= soft ; pin
out
driver= strong
−
−
50
ns
CL= 50 pF; pin
out
driver= medium
−
−
140
ns
CL= 150 pF; pin
out
driver= medium
−
−
550
ns
CL= 150 pF; pin
out
driver= weak
−
−
18000
ns
CL= 20000 pF;
pin out
driver= medium
−
−
65000
ns
CL= 20000 pF;
pin out
driver= weak
Data Sheet
57
V 1.1.1, 2014-05
TC1784
Electrical ParametersDC Parameters
Table 13
Standard_Pads Class_A1+ (cont’d)
Parameter
Symbol
Values
Min.
Rise time, pad type A1+
Typ.
Max.
tRA1+ CC −
−
150
−
−
Unit
Note /
Test Condition
ns
CL= 20 pF; pin
out
driver= weak
28
ns
CL= 50 pF;
edge= slow ;
pin out
driver= strong
−
−
16
ns
CL= 50 pF;
edge= soft ; pin
out
driver= strong
−
−
50
ns
CL= 50 pF; pin
out
driver= medium
−
−
140
ns
CL= 150 pF; pin
out
driver= medium
−
−
550
ns
CL= 150 pF; pin
out
driver= weak
−
−
18000
ns
CL= 20000 pF;
pin out
driver= medium
−
−
65000
ns
CL= 20000 pF;
pin out
driver= weak
Input high voltage, Class
A1+ pads
Input low voltage Class
A1+ pads
Ratio Vil/Vih, A1+ pads
VIHA1+
SR
VILA1+
0.6 x
−
VDDP
0.3,3.6
)
−
-0.3
SR
VILA1+ /
VIHA1+
min(V V
DDP+
0.36 x
V
VDDP
−
0.6
−
CC
Data Sheet
58
V 1.1.1, 2014-05
TC1784
Electrical ParametersDC Parameters
Table 13
Standard_Pads Class_A1+ (cont’d)
Parameter
Symbol
Values
Min.
Output voltage high class
A1+ pads
VOHA1+
CC
Typ.
Unit
Note /
Test Condition
V
IOH≥ -1.4 mA;
Max.
VDDP - −
−
VDDP - −
−
−
−
0.4
pin out
driver= medium
V
0.4
2.4
IOH≥ -1.4 mA;
pin out
driver= strong
V
IOH≥ -2 mA; pin
out
driver= medium
−
2.4
−
V
IOH≥ -2 mA; pin
out
driver= strong
VDDP - −
−
V
IOH≥ -400 μA;
pin out
driver= weak
2.4
−
−
V
IOH≥ -500 μA;
pin out
driver= weak
−
−
0.4
V
IOL≤ 2 mA; pin
0.4
Output voltage low class
A1+ pads
VOLA1+
CC
out
driver= medium
−
−
0.4
V
IOL≤ 2 mA; pin
out
driver= strong
−
−
0.4
V
IOL≤ 500 μA;
pin out
driver= weak
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be
guaranteed that it suppresses switching due to external system noise.
Data Sheet
59
V 1.1.1, 2014-05
TC1784
Electrical ParametersDC Parameters
Table 14
Standard_Pads Class_A2
Parameter
Input Hysteresis for A2
pads 1)
Input Leakage current
Class A2
Symbol
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
HYSA2
0.1 x
−
−
V
CC
VDDP
IOZA2
-6000
−
6000
nA
-3000
−
3000
nA
0.6
−
−
−
450
600
Ohm IOH> -0.5 mA;
P_MOS
−
210
340
Ohm IOL< 0.5 mA;
N_MOS
−
−
155
Ohm IOH> -2 mA;
P_MOS
−
−
110
Ohm IOL< 2 mA;
N_MOS
−
−
28
Ohm IOH> -2 mA;
P_MOS
−
−
22
Ohm IOL< 2 mA;
N_MOS
CC
Vi< VDDP / 2 1 V; Vi> VDDP / 2
+ 1 V; Vi≥ 0 V;
Vi≤ VDDP V
Vi> VDDP / 2 1 V; Vi< VDDP / 2
+1V
Ratio Vil/Vih, A2 pads
VILA2 /
VIHA2
CC
On-Resistance of the
RDSONW
class A2 pad, weak driver CC
On-Resistance of the
class A2 pad, medium
driver
RDSONM
CC
On-Resistance of the
RDSON2
class A2 pad, strong driver CC
Data Sheet
60
V 1.1.1, 2014-05
TC1784
Electrical ParametersDC Parameters
Table 14
Standard_Pads Class_A2 (cont’d)
Parameter
Fall time, pad type A2
Symbol
tFA2 CC
Values
Min.
Typ.
Max.
−
−
150
Unit
Note /
Test Condition
ns
CL= 20 pF; pin
out
driver= weak
−
−
7
ns
CL= 50 pF;
edge= medium
; pin out
driver= strong
−
−
10
ns
CL= 50 pF;
edge= mediumminus ; pin out
driver= strong
−
−
3.7
ns
CL= 50 pF;
edge= sharp ;
pin out
driver= strong
−
−
5
ns
CL= 50 pF;
edge= sharpminus ; pin out
driver= strong
−
−
16
ns
CL= 50 pF;
edge= soft ; pin
out
driver= strong
−
−
50
ns
CL= 50 pF; pin
out
driver= medium
−
−
7.5
ns
CL= 100 pF;
edge= sharp ;
pin out
driver= strong
−
−
140
ns
CL= 150 pF; pin
out
driver= medium
Data Sheet
61
V 1.1.1, 2014-05
TC1784
Electrical ParametersDC Parameters
Table 14
Parameter
Standard_Pads Class_A2 (cont’d)
Symbol
Values
Min.
Typ.
Max.
−
−
550
Unit
Note /
Test Condition
ns
CL= 150 pF; pin
out
driver= weak
−
−
18000
ns
CL= 20000 pF;
pin out
driver= medium
−
−
65000
ns
CL= 20000 pF;
pin out
driver= weak
Data Sheet
62
V 1.1.1, 2014-05
TC1784
Electrical ParametersDC Parameters
Table 14
Standard_Pads Class_A2 (cont’d)
Parameter
Symbol
Values
Min.
Rise time, pad type A2
Typ.
Max.
tRA2 CC −
−
150
−
−
Unit
Note /
Test Condition
ns
CL= 20 pF; pin
out
driver= weak
7.0
ns
CL= 50 pF;
edge= medium
; pin out
driver= strong
−
−
10
ns
CL= 50 pF;
edge= mediumminus ; pin out
driver= strong
−
−
3.7
ns
CL= 50 pF;
edge= sharp ;
pin out
driver= strong
−
−
5
ns
CL= 50 pF;
edge= sharpminus ; pin out
driver= strong
−
−
16
ns
CL= 50 pF;
edge= soft ; pin
out
driver= strong
−
−
50
ns
CL= 50 pF; pin
out
driver= medium
−
−
7.5
ns
CL= 100 pF;
edge= sharp ;
pin out
driver= strong
−
−
140
ns
CL= 150 pF; pin
out
driver= medium
Data Sheet
63
V 1.1.1, 2014-05
TC1784
Electrical ParametersDC Parameters
Table 14
Standard_Pads Class_A2 (cont’d)
Parameter
Symbol
Values
Min.
Typ.
Max.
−
−
550
Unit
Note /
Test Condition
ns
CL= 150 pF; pin
out
driver= weak
−
−
18000
ns
CL= 20000 pF;
pin out
driver= medium
−
−
65000
ns
CL= 20000 pF;
pin out
driver= weak
Input high voltage, class
A2 pads
VIHA2
SR
0.6 x
VOHA2
CC
min(V V
DDP +
0.3,
3.6)
−
Input low voltage Class A2 VILA2 SR -0.3
pads
Output voltage high class
A2 pads
−
VDDP
0.36 x
V
VDDP
VDDP - −
−
VDDP - −
−
−
−
V
0.4
pin out
driver= medium
V
0.4
2.4
IOH≥ -1.4 mA;
IOH≥ -1.4 mA;
pin out
driver= strong
V
IOH≥ -2 mA; pin
out
driver= medium
−
2.4
−
V
IOH≥ -2 mA; pin
out
driver= strong
VDDP - −
−
V
IOH≥ -400 μA;
pin out
driver= weak
−
−
V
IOH≥ -500 μA;
pin out
driver= weak
0.4
2.4
Data Sheet
64
V 1.1.1, 2014-05
TC1784
Electrical ParametersDC Parameters
Table 14
Standard_Pads Class_A2 (cont’d)
Parameter
Symbol
Output voltage low class
A2 pads
VOLA2
Values
Min.
Typ.
Max.
−
−
0.4
Unit
Note /
Test Condition
V
IOL≤ 2 mA; pin
CC
out
driver= medium
−
−
0.4
V
IOL≤ 2 mA; pin
out
driver= strong
−
−
0.4
V
IOL≤ 500 μA;
pin out
driver= weak
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be
guaranteed that it suppresses switching due to external system noise.
Table 15
Standard_Pads Class_F
Parameter
Input Hysteresis F1)
Input Leakage Current
Class F
Symbol
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
HYSF
0.05 x
−
−
V
CC
VDDP
IOZF CC -6000
−
6000
nA
-3000
−
3000
nA
−
−
−
170
Ohm IOH> -2 mA;
P_MOS
−
−
145
Ohm IOL< 2 mA;
N_MOS
Vi< VDDP / 2 1 V; Vi> VDDP / 2
+ 1 V; Vi≥ 0 V;
Vi≤ VDDP V
Vi> VDDP / 2 1 V; Vi< VDDP / 2
+1V
Ratio Vil/ Vih, F pads
On-Resistance of the
class F pad, medium
driver
VILF /
0.6
VIHF CC
RDSONM −
CC
Fall time, pad type F,
CMOS mode
tFF CC
−
−
60
ns
CL= 50 pF
Rise time, pad type F,
CMOS mode
tRF CC
−
−
60
ns
CL= 50 pF
Data Sheet
65
V 1.1.1, 2014-05
TC1784
Electrical ParametersDC Parameters
Table 15
Standard_Pads Class_F (cont’d)
Parameter
Symbol
Values
Min.
Input high voltage, pad
class F, CMOS mode
VIHF SR 0.6 x
VDDP
Input low voltage, Class F VILF SR
pads, CMOS mode
Output high voltage, class VOHF
F pads, CMOS mode
CC
−
min(V V
DDP+
Note /
Test Condition
0.3,
3.6)
0.36 x
V
VDDP
VDDP-
−
−
V
IOH≥ -1.4 mA
−
−
V
−
0.4
V
IOH≥ -2 mA
IOL≤ 2 mA
0.4
2.4
Output low voltage, class
F pads, CMOS mode
Max.
−
-0.3
Unit
Typ.
VOLF CC −
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be
guaranteed that it suppresses switching due to external system noise.
Table 16
Standard_Pads Class_I
Parameter
Symbol
Min.
Typ.
Max.
Input Hysteresis Class I1)
HYSI
0.1 x
−
−
V
CC
VDDP
IOZI CC -1000
VILI / VIHI 0.6
−
1000
nA
−
−
VIHI SR
−
min(V V
DDP+
Input Leakage Current
Ratio between low and
high input threshold
Input high voltage, class I
pins
Input low voltage, Class I
pads
Values
Unit
Note /
Test Condition
CC
0.6 x
VDDP
VILI SR
0.3,
3.6)
−
-0.3
0.36 x
V
VDDP
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be
guaranteed that it suppresses switching due to external system noise.
Data Sheet
66
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TC1784
Electrical ParametersDC Parameters
Table 17
LVDS_Pads Parameters
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
Note /
Test Condition
Output impedance, pad
class F, LVDS mode
RO CC
40
−
140
Ohm
Fall time, pad type LVDS
tFL CC
−
−
2
ns
termination
100 Ω ± 1 %;
differential
capacitance = 10
pF; input
capacitance = 20
pF
Rise time, pad type LVDS tRL CC
−
−
2
ns
termination
100 Ω ± 1 %;
differential
capacitance = 10
pF; input
capacitance = 20
pF
tSET_LVD −
−
13
μs
termination
100 Ω ± 1 %
−
400
mV
termination
100 Ω ± 1 %
Pad set-up time
S CC
Output Differential Voltage VOD CC 150
Output voltage high, pad
class F, LVDS mode
VOH CC −
−
1525
mV
termination
100 Ω ± 1 %
Output voltage low, pad
class F, LVDS mode
VOL CC
−
−
mV
termination
100 Ω ± 1 %
Output Offset Voltage
VOS CC 1075
−
1325
mV
termination
100 Ω ± 1 %
Data Sheet
875
67
V 1.1.1, 2014-05
TC1784
Electrical ParametersDC Parameters
5.2.2
Analog to Digital Converters (ADCx)
ADC parameter are valid for VDDM = 4.75 V to 5.25 V.
Table 18
ADC Parameters
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
CAINSW
Switched capacitance at
the analog voltage inputs1) CC
−
9
20
pF
Total capacitance of an
analog input
−
20
30
pF
Switched capacitance at
the positive reference
voltage input2)3)
CAREFSW −
15
30
pF
Total capacitance of the
voltage reference inputs2)
CAREFTO −
20
40
pF
Differential Non-Linearity
Error4)5)6)7)
Gain Error4)6)5)7)
CAINTOT
CC
CC
T CC
EADNL
-3
−
3
LSB
ADC
resolution= 12bit 8) 9)
EAGAIN
-3.5
−
3.5
LSB
ADC
resolution= 12bit 8) 9)
EAINL
-3
−
3
LSB
ADC
resolution= 12bit 8) 9)
EAOFF
-4
−
4
LSB
ADC
resolution= 12bit 8) 9)
fADC SC 4
fADCI CC 1
QCONV 70
−
90
MHz fADC= fFPI
18
MHz
100
pC
CC
CC
Integral NonLinearity4)6)5)7)
Offset Error4)6)5)7)
CC
CC
Converter clock
Internal ADC clock
Charge consumption per
conversion
Note /
Test Condition
−
10)
85
CC
charge needs to
be provided via
VAREFx
Data Sheet
68
V 1.1.1, 2014-05
TC1784
Electrical ParametersDC Parameters
Table 18
ADC Parameters (cont’d)
Parameter
Symbol
Values
Min.
Input leakage at analog
inputs11)
IOZ1 CC -100
Typ.
Max.
−
500
Unit
Note /
Test Condition
nA
Vi≤ VDDM V;
Vi≥ 0.97 x
VDDM V;
overlayed= No
−
-100
600
nA
Vi≥ 0.97 x
VDDM V;
Vi≤ VDDM V;
overlayed= Yes
-500
−
100
nA
Vi≤ 0.03 x
VDDM V;
Vi≥ 0 V;
-600
−
100
nA
Vi≤ 0.03 x
VDDM V;
Vi≥ 0 V;
-100
−
200
nA
Vi> 0.03 x
VDDM V;
Vi< 0.97 x
VDDM V;
overlayed= No
overlayed= Yes
overlayed= No
−
-100
300
nA
Vi< 0.97 x
VDDM V;
Vi> 0.03 x
VDDM V;
overlayed= Yes
Input leakage current at
Varef0
IOZ2 CC -1
−
1
μA
VAREF0≤ VDDM V
Input leakage current at
Varef1
-1
−
1
μA
VAREF1≤ VDDM V
Input leakage current at
Vagnd0
IOZ3 CC -2
−
2
μA
VAGND0≤ VDDM V
ON resistance of the
transmission gates in the
analog voltage path
RAIN CC −
900
1500
Ohm
Data Sheet
69
V 1.1.1, 2014-05
TC1784
Electrical ParametersDC Parameters
Table 18
ADC Parameters (cont’d)
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
ON resistance for the ADC RAIN7T
test (pull down for AIN7)
CC
180
550
900
Ohm
Resistance of the
reference voltage input
path
−
500
1000
Ohm
tS CC
2
tCAL CC −
−
257
TADCI
−
4352
cycle
s
TUE CC -4
−
413)
LSB
Sample time
Calibration time after bit
ADC_GLOBCFG.SUCAL
is set
Total Unadjusted
Error6)5)12)
RAREF
CC
Analog reference ground2) VAGND0
SR
Analog input voltage
VSSM - −
0.05
VAIN SR VAGND0 −
VAGND0 −
Analog reference voltage2) VAREFx
SR
Analog reference voltage
range6)5)2)
Note /
Test Condition
+1
ADC
resolution= 12bit
VAREFx V
-1
VAREFx V
VDDM + V
0.0514)
15)
VAREFx - VDDM/2 −
VAGND0
VDDM + V
0.05
SR
1) The sampling capacity of the conversion C-network is pre-charged to VAREFx/2 before the sampling moment.
Because of the parasitic elements the voltage measured at AINx can deviate from VAREFx/2.
2) Applies to AINx, when used as auxiliary reference input.
3) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage
at once. Instead smaller capacitances are successively switched to the reference voltage.
4) The sum of DNL/INL/GAIN/OFF errors does not exceed the related TUE total unadjusted error.
5) If a reduced analog reference voltage between 1V and VDDM / 2 is used, then there are additional decrease in
the ADC speed and accuracy.
6) If the analog reference voltage range is below VDDM but still in the defined range of VDDM / 2 and VDDM is used,
then the ADC converter errors increase. If the reference voltage is reduced by the factor k (k<1),
TUE,DNL,INL,Gain, and Offset errors increase also by the factor 1/k.
7) If the analog reference voltage is > VDDM, then the ADC converter errors increase.
8) For 10-bit conversions the error value must be multiplied with a factor 0.25.
9) For 8-bit conversions the error value must be multiplied with a factor 0.0625.
10) For a conversion time of 1 µs a rms value of 85µA result for IAREFx.
Data Sheet
70
V 1.1.1, 2014-05
TC1784
Electrical ParametersDC Parameters
11) The leakage current definition is a continuos function, as shown in figure ADCx Analoge Input Leakage. The
numerical values defined determine the characteristic points of the given continuous linear approximation they do not define step function.
12) Measured without noise.
13) For 10-bit conversion the TUE is ±2LSB; for 8-bit conversion the TUE is ±1LSB
14) A running conversion may become inexact in case of violating the normal conditions (voltage overshoot).
15) If the reference voltage VAREFx increase or the VDDM decrease, so that VAREF = (VDDM + 0.05V to VDDM + 0.07V),
then the accuracy of the ADC decrease by 4LSB12.
Table 19
Conversion Time (Operating Conditions apply)
Parameter
Symbol
tC
Conversion
time with
post-calibration
Values
Unit Note
CC 2 × TADC + (4 + STC + n) × TADCI μs
2 × TADC + (2 + STC + n) × TADCI
Conversion
time without
post-calibration
n = 8, 10, 12 for
n - bit conversion
TADC = 1 / fFPI
TADCI = 1 / fADCI
The power-up calibration of the ADC requires a maximum number of 4352 fADCI cycles.
REXT
VAIN =
Analog Input Circuitry
RAIN, On
ANx
CEXT
CAINTOT - CAINSW
VAGNDx
CAINSW
RAIN7T
Reference Voltage Input Circuitry
RAREF, On
VAREFx
VAREF
CAREFTOT - CAREFSW
CAREFSW
VAGNDx
Analog_InpRefDiag
Figure 2
Data Sheet
ADCx Input Circuits
71
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Electrical ParametersDC Parameters
Ioz1
Single ADC Input
500nA
200nA
100nA
-100nA
VIN[VDDM%]
3%
97% 100%
-500nA
Ioz1
Overlayed ADC/FADC Input
600nA
300nA
100nA
-100nA
VIN[VDDM%]
3%
97% 100%
-600nA
Figure 3
Data Sheet
ADCx Analog Inputs Leakage
72
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Electrical ParametersDC Parameters
5.2.3
Table 20
Fast Analog to Digital Converter (FADC)
FADC Parameters
Parameter
Input current at VFAREF
Symbol
Values
Unit
Min.
Typ.
Max.
IFAREF
−
−
120
μA
IFOZ2
-500
−
500
nA
IFOZ3
-500
−
500
nA
EFDNL
-1
−
1
LSB
Note /
Test Condition
CC
Input leakage current at
VFAREF1)
CC
Input leakage current at
VFAGND
CC
DNL error
CC
VFAREF≤ VDDMF
V; VFAREF≥ 0 V
VIN mode=
differential;
Gain = 1 or 2
−
-2
2
LSB
VIN mode=
differential;
Gain = 4 or 82)
−
-1
1
LSB
VIN mode=
single ended;
Gain = 1 or 2
−
-2
2
LSB
VIN mode=
single ended;
Gain = 4 or 82)
GRADient error
EFGRAD -5
−
-5
−
5
%
CC
VIN mode=
differential ;
Gain≤ 4
5
%
VIN mode=
single ended ;
Gain≤ 4
−
-6
6
%
VIN mode=
differential ;
Gain= 8
−
-6
6
%
VIN mode=
single ended ;
Gain= 8
Data Sheet
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Electrical ParametersDC Parameters
Table 20
FADC Parameters (cont’d)
Parameter
INL error
Symbol
EFINL
Values
Unit
Note /
Test Condition
4
LSB
VIN mode=
4
LSB
VIN mode=
Min.
Typ.
Max.
-4
−
-4
−
CC
differential
single ended
Offset error
EFOFF
−
-90
90
mV
CC
VIN mode=
differential ;
Calibration= No
−
-90
90
mV
VIN mode=
single ended ;
Calibration= No
−
-20
20
mV
VIN mode=
differential ;
Calibration= Ye
s 3)4)
−
-20
20
mV
VIN mode=
single ended ;
Calibration= Ye
s 3)4)
EFREF
-60
−
60
mV
Channel amplifier cutoff
frequency
fCOFF
2
−
−
MHz
Converter clock
fFADC
1
−
90
MHz fFADC= fFPI
tC CC
−
−
21
1/
Input resistance of the
analog voltage path (Rn,
Rp)
RFAIN
100
Settling time of a channel
amplifier after changing
ENN or ENP
tSET CC −
Analog input voltage
range
VAINF
Error of commen mode
voltage VFAREF/2
CC
CC
SC
Conversion time
Data Sheet
−
200
kOh
m
−
5
μs
VDDMF
V
CC
SR
For 10-bit
fFADC conversion
VFAGND −
74
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Electrical ParametersDC Parameters
Table 20
FADC Parameters (cont’d)
Parameter
Symbol
Values
Min.
Analog reference ground
VFAGND
VSSAF - −
VFAREF
3.0
SR
Analog reference voltage
Typ.
0.05
−
SR
Unit
Max.
VSSAF
V
3.635)
V
Note /
Test Condition
+ 0.05
6)
1) This value applies in power-down mode.
2) No missing codes.
3) Calibration should be preformed at each power-up. In case of a continous operation, it should be performed
minimium once per week.
4) The offser error voltage drifts over the whole temperature range maximum +-3LSB.
5) Voltage overshoot to 4V is permissible, provided the pulse duration is less than 100 μs and the cumulated sum
of the pulses does not exceed 1 h.
6) A running conversion may become inexact in case of violating the nomal operating conditions (voltage
overshoots).
The calibration procedure should run after each power-up, when all power supply
voltages and the reference voltage have stabilized.
Data Sheet
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TC1784
Electrical ParametersDC Parameters
FADC Analog Input Stage
FAINxN
-
=
VFAGND
RN
VFAREF /2
+
+
FAINxP
RP
-
FADC Reference Voltage
Input Circuitry
VFAREF
IFAREF
VFAREF
VFAGND
FADC_InpRefDiag
Figure 4
Data Sheet
FADC Input Circuits
76
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Electrical ParametersDC Parameters
5.2.4
Table 21
Oscillator Pins
OSC_XTAL Parameters
Parameter
Symbol
Values
Unit
Note /
Test Condition
VIN<VDDOSC3 ;
VIN>0 V
Min.
Typ.
Max.
-25
−
25
μA
Input current at XTAL1
IIX1 CC
Input frequency
fOSC SR 4
−
40
MHz Direct Input
Mode selected
8
−
25
MHz External Crystal
Mode selected
−
−
10
ms
VDDOS
V
Oscillator start-up time1)
tOSCS
CC
Input high voltage at
XTAL12)
VIHX SR 0.7 x
VDDOS
Input low voltage at
XTAL1
VILX SR -0.5
Input Hysteresis for
XTAL1 pad 3)
HYSAX
−
+
0.5
C3
C3
−
0.3 x
V
VDDOS
C3
−
−
200
mV
CC
1) tOSCS is defined from the moment when VDDOSC3 = 3.13V until the oscillations reach an amplitude at XTAL1 of
0.3 * VDDOSC3. The external oscillator circuitry must be optimized by the customer and checked for negative
resistance as recommended and specified by crystral suppliers.
2) If the XTAL1 pin is driven by a crystal, reaching a minimum amplitude (peak-to-peak) of 0.4 * VDDOSC3 is
necessary.
3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be
guaranteed that it suppresses switching due to external system noise.
Note: It is strongly recommended to measure the oscillation allowance (negative
resistance) in the final target system (layout) to determine the optimal parameters
for the oscillator operation. Please refer to the limits specified by the crystal or
ceramic resonator supplier.
Data Sheet
77
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TC1784
Electrical ParametersDC Parameters
5.2.5
Table 22
Temperature Sensor
DTS Parameters
Parameter
Symbol
Values
Min.
Measurement time
Temperature sensor
range
tM CC
TSR SR
Unit
Typ.
Max.
−
−
100
μs
-40
−
150
°C
Sensor Accuracy
(calibrated)
TTSA CC -6
−
6
°C
Start-up time after resets
inactive
tTSST SR −
−
20
μs
Note /
Test Condition
The following formula calculates the temperature measured by the DTS in [oC] from the
RESULT bit field of the DTSSTAT register.
(1)
DTSSTAT RESULT – 596
Tj = ------------------------------------------------------------------2, 03
Data Sheet
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Electrical ParametersDC Parameters
5.2.6
Power Supply Current
The total power supply current defined below consists of leakage and switching
component.
Application relevant values are typically lower than those given in the following
two tables and depend on the customer's system operating conditions (e.g.
thermal connection or used application configurations).
The operating conditions for the parameters in the following table are:
VDD=1.365 V, VDDP=3.47 V, VDDM=5.1 V, fLMB=180, TJ=150 oC
The realisic power pattern defines the following conditions:
•
•
•
•
•
•
TJ=150 oC
fLMB = fPCP = fCPU = 180 MHz
fFPI = 90 MHz
VDD = VDDOSC = VDDAF = 1.326 V
VDDP = VDDOSC3 = VDDFL3 = VDDMF = 3.366 V
VDDM = 5.1 V
The max power pattern defines the following conditions:
•
•
•
•
•
•
TJ=150 oC
fLMB = fPCP = fCPU = 180 MHz
fFPI = 90 MHz
VDD = VDDOSC = VDDAF = 1.365 V
VDDP = VDDOSC3 = VDDFL3 = VDDMF = 3.47 V
VDDM = 5.5 V
Table 23
Power Supply Parameters
Parameter
Symbol
Values
Unit
Note / Test Condition
5853)
mA
power pattern= max
4)
power pattern= realistic
Min.
Typ.
Max.
−
−
Core active
mode supply
current1)2)
IDD CC
−
−
433
mA
IDD current at
PORST Low
IDD_PORS −
−
300
mA
CC
−
−
291
mA
Analog core
supply current
IDDAF
−
−
23
mA
IDDOSC
−
−
2
mA
−
−
2
mA
Oscillator core
supply current
T
CC
CC
E-Ray PLL core IDDPF
supply current CC
Data Sheet
VDD=1.326 V
79
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Electrical ParametersDC Parameters
Table 23
Power Supply Parameters (cont’d)
Parameter
Symbol
Values
Min.
IDDP current at
PORST Low
IDDP_POR −
ST
Unit
Typ.
Max.
−
2.5
−
IDDP_P
mA
CC
IDDP current no IDDP CC −
pad activity,
LVDS off 5)
mA
including flash read current
IDDP_P
mA
including flash programming
current 6)
IDDP_P
mA
including flash erase current
ORST
+
12
−
−
ORST +
27
−
−
ORST +
20 7)
Flash memory
current 5)
Note / Test Condition
IDDFL3
CC
6)
−
−
56
mA
flash read current
−
−
21
mA
flash programming current 6)
−
−
56
mA
flash erase current 6)
Oscillator
power supply
current, 3.3V
IDDOSC3
−
−
11.5
mA
E-Ray PLL
supply current,
3.3V
IDDPF3
−
−
3.5
mA
FADC analog
supply current,
3.3V
IDDMF
−
−
15
mA
Current
ILVDS
Consumption of CC
LVDS Pad
Pairs
−
−
24
mA
ADC 5V power
supply current
IDDM CC −
−
2
mA
Maximum
power
dissipation
PD CC
−
−
1277
mW
power pattern= max
−
−
1042
mW
power pattern= realistic
CC
CC
CC
for all LVDS pads in total
1) Infineon Power Loop: CPU and PCP running, all peripherals active. The power consumption of each customer
application will most probably be lower than this value, but must be evaluated seperately.
2) This current includes the E-Ray module power consumption, including the PCP operation component.
Data Sheet
80
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Electrical ParametersDC Parameters
3) The IDD decreases typically by 79mA if the fCPU decreases by 50MHz, at constant TJ
4) The IDD decreases typically by 38mA if the fCPU decreases by 50MHz, at constant TJ
5) For operations including the D-Flash the required currents are always lower than the currents for non D-Flash
operation.
6) Relevant for the power supply dimensioning, not for thermal considerations.
7) In case of erase of Program Flash PF, internal flash array loading effects may generate transient current spikes
of up to 15 mA for maximum 5 ms per flash module.
5.2.6.1
Calculating the 1.3 V Current Consumption
The current consumption of the 1.3 V rail compose out of two parts:
•
•
Static current consumption
Dynamic current consumption
The static current consumption is related to the device temperature TJ and the dynamic
current consumption depends of the configured clocking frequencies and the software
application executed. These two parts needs to be added in order to get the rail current
consumption.
(2)
I
0
mA
= 2, 20897 --------- × e 0, 02696 × T J [ C ]
C
(3)
mA
I 0 = 10, 68 --------- × e 0, 02203 × T J [ C ]
C
Function 2 defines the typical static current consumption and Function 3 defines the
maximum static current consumption. Both functions are valid for VDD = 1.326 V.
For the dynamic current consumption using the application pattern and fLMB = 2 * fFPI the
function 4 applies:
(4)
mA
I D y m = 0, 77 ------------- × f CPU [ MHz ]
MHz
Data Sheet
81
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Electrical ParametersDC Parameters
and this finally results in
(5)
I DD = I 0 + I DYM
Data Sheet
82
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TC1784
Electrical ParametersAC Parameters
5.3
AC Parameters
That means, keeping the pads constantly at maximum strength.
5.3.1
Testing Waveforms
VD D P
90%
90%
10%
10%
VSS
tR
tF
rise_fall
Figure 5
Rise/Fall Time Parameters
VD D P
VD D E / 2
Test Points
VD D E / 2
VSS
mct04881_a.vsd
Figure 6
Testing Waveform, Output Delay
VLoad+ 0.1 V
VLoad- 0.1 V
Timing
Reference
Points
VOH - 0.1 V
VOL - 0.1 V
MCT04880_new
Figure 7
Data Sheet
Testing Waveform, Output High Impedance
83
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Electrical ParametersAC Parameters
5.3.2
Power Sequencing
V
5.5V
5V
4.5V
VAREF
3.63V
3.3V
2.97V
-12%
1.43V
1.3V
1.17V
0.5V
-12%
0.5V
0.5V
t
VDDP
PORST
Figure 8
power
power
down
fail
5 V / 3.3 V / 1.3 V Power-Up/Down Sequence
t
The following list of rules applies to the power-up/down sequence:
•
•
•
All ground pins VSS must be externally connected to one single star point in the
system. Regarding the DC current component, all ground pins are internally directly
connected.
At any moment in time to avoid increased latch-up risk,
each power supply must be higher then any lower_power_supply - 0.5 V, or:
VDD5 > VDD3.3 - 0.5 V; VDD5 > VDD1.3 - 0.5 V;VDD3.3 > VDD1.3 - 0.5 V, see Figure 8.
– The latch-up risk is minimized if the I/O currents are limited to:
– 20 mA for one pin group
– AND 100 mA for the completed device I/Os
– AND additionally before power-up / after power-down:
1 mA for one pin in inactive mode (0 V on all power supplies)
During power-up and power-down, the voltage difference between the power supply
pins of the same voltage (3.3 V, 1.3 V, and 5 V) with different names (for example
VDDP, VDDFL3 ...), that are internally connected via diodes, must be lower than 100 mV.
On the other hand, all power supply pins with the same name (for example all VDDP),
Data Sheet
84
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Electrical ParametersAC Parameters
1.
2.
3.
4.
5.
6.
are internally directly connected. It is recommended that the power pins of the same
voltage are driven by a single power supply.
The PORST signal may be deactivated after all VDD5, VDD3.3, VDD1.3, and VAREF powersupplies and the oscillator have reached stable operation, within the normal
operating conditions.
At normal power down the PORST signal should be activated within the normal
operating range, and then the power supplies may be switched off. Care must be
taken that all Flash write or delete sequences have been completed.
At power fail the PORST signal must be activated at latest when any 3.3 V or 1.3 V
power supply voltage falls 12% below the nominal level. If, under these conditions,
the PORST is activated during a Flash write, only the memory row that was the target
of the write at the moment of the power loss will contain unreliable content. In order
to ensure clean power-down behavior, the PORST signal should be activated as
close as possible to the normal operating voltage range.
In case of a power-loss at any power-supply, all power supplies must be powereddown, conforming at the same time to the rules number 2 and 4.
Although not necessary, it is additionally recommended that all power supplies are
powered-up/down together in a controlled way, as tight to each other as possible.
Additionally, regarding the ADC reference voltage VAREF:
– VAREF must power-up at the same time or later then VDDM, and
– VAREF must power-down either earlier or at latest to satisfy the condition
VAREF < VDDM + 0.5 V. This is required in order to prevent discharge of VAREF filter
capacitance through the ESD diodes through the VDDM power supply. In case of
discharging the reference capacitance through the ESD diodes, the current must
be lower than 5 mA.
Data Sheet
85
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TC1784
Electrical ParametersAC Parameters
5.3.3
Table 24
Power, Pad and Reset Timing
Reset Timings Parameters
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note /
Test Condition
fCPU = 180 MHz
Application Reset Boot
Time1)2)
tB CC
150
−
665
μs
Power on Reset Boot
Time3)4)
tBP CC
−
−
2.5
ms
−
−
ns
−
−
ns
HWCFG pins hold time
from ESR0 rising edge
tHDH SR 16 /
fFPI
HWCFG pins setup time to tHDS CC 0
ESR0 rising edge
Ports inactive after ESR0
reset active
tPI CC
−
−
8 / fFPI
ns
Ports inactive after
PORST reset active5)
tPIP CC
−
−
150
ns
Minimum PORST active
time after power supplies
are stable at operating
levels
tPOA CC 10
−
−
ms
TESTMODE / TRST hold
time from PORST rising
edge
tPOH SR 100
−
−
ns
PORST rise time
tPOR SR −
tPOS SR 0
−
50
ms
−
−
ns
−
40 6)
μs
TESTMODE / TRST
setup time to PORST
rising edge
Application Reset inactive tPOR_APP −
after PORST deassertion SR
1) The duration of the boot time is defined between the rising edge of the internal application reset and the clock
cycle when the first user instruction has entered the CPU pipeline and its processing starts.
2) The given time includes the time of the internal reset extension for a configured value of
SCU_RSTCNTCON.RELSA = 0x05BE.
3) The duration of the boot time is defined between the rising edge of the PORST and the clock cycle when the
first user instruction has entered the CPU pipeline and its processing starts.
Data Sheet
86
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Electrical ParametersAC Parameters
4) The given time includes the internal reset extension time for the System and Application Reset which is visible
through ESR0.
5) This parameter includes the delay of the analog spike filter in the PORST pad.
6) Application Reset is assumed not to be extended from external, otherwise the time extends by the time the
Application Reset is extended.
VDD P -12%
VD D PPA
V D DPPA
VDDP
VDD
VD D -12%
tPOA
tPOA
PORST
tPOH
TRST
TESTMODE
ESR0
tPOH
t hd
t hd
tHDH
tHDH
tHDH
HWCFG
t PIP
tPI
Pads
tPI
t PIP
tPI
tPI
t PIP
tPI
Pad-state undefined
Tri-state or pull device active
reset_beh2
As programmed
Figure 9
Data Sheet
Power, Pad and Reset Timing
87
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Electrical ParametersAC Parameters
5.3.4
Table 25
Phase Locked Loop (PLL)
PLL_SysClk Parameters
Parameter
Symbol
Values
Min.
Typ.
DP CC -7
fPLLBASE 50
Accumulated Jitter
PLL base frequency
Unit
Max.
−
7
ns
200
320
MHz
−
16
MHz
−
720
MHz
Note /
Test Condition
CC
VCO input frequency
fREF CC 8
fVCO CC 400
tL CC
14
VCO frequency range
PLL lock-in time
14
−
200
μs
N > 32
−
400
μs
N ≤ 32
Phase Locked Loop Operation
When PLL operation is enabled and configured, the PLL clock fVCO (and with it the LMBBus clock fLMB) is constantly adjusted to the selected frequency. The PLL is constantly
adjusting its output frequency to correspond to the input frequency (from crystal or clock
source), resulting in an accumulated jitter that is limited. This means that the relative
deviation for periods of more than one clock cycle is lower than for a single clock cycle.
This is especially important for bus cycles using wait states and for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
Two formulas are defined for the (absolute) approximate maximum value of jitter Dm in
[ns] dependent on the K2 - factor, the LMB clock frequency fLMB in [MHz], and the
number m of consecutive fLMB clock periods.
for
( K2 ≤ 100 )
( m ≤ ( f LMB [ MHz ] ) ⁄ 2 )
and
( 1 – 0, 01 × K2 ) × ( m – 1 )
D m [ ns ] = ⎛⎝ --------------------------------------------- + 5⎞⎠ × ⎛⎝ ---------------------------------------------------------------- + 0, 01 × K2⎞⎠
K2 × f LMB [ MHz ]
0, 5 × f LMB [ MHz ] – 1
740
else
740
D m [ ns ] = --------------------------------------------- + 5
K2 × f LMB [ MHz ]
(6)
(7)
With rising number m of clock cycles the maximum jitter increases linearly up to a value
of m that is defined by the K2-factor of the PLL. Beyond this value of m the maximum
Data Sheet
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Electrical ParametersAC Parameters
accumulated jitter remains at a constant value. Further, a lower LMB-Bus clock
frequency fLMB results in a higher absolute maximum jitter value.
Note: The specified PLL jitter values are valid if the capacitive load per pin does not
exceed CL = 20 pF with the maximum driver and sharp edge.
Note: The maximum peak-to-peak noise on the pad supply voltage, measured between
VDDOSC3 and VSSOSC, is limited to a peak-to-peak voltage of VPP = 100 mV for noise
frequencies below 300 KHz and VPP = 40 mV for noise frequencies above
300 KHz.
The maximum peak-to peak noise on the pad supply voltage, measured between
VDDOSC and VSSOSC, is limited to a peak-to-peak voltage of VPP = 100 mV for noise
frequencies below 300 KHz and VPP = 40 mV for noise frequencies above
300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage
as near as possible to the supply pins and using PCB supply and ground planes.
Oscillator Watchdog (OSC_WDT)
The expected input frequency is selected via the bit field SCU_OSCCON.OSCVAL. The
OSC_WDT checks for too low frequencies and for too high frequencies.
The frequency that is monitored is fOSCREF which is derived for fOSC.
(8)
f O S C R EF
fO S C
= ---------------------------------OSCVAL + 1
The divider value SCU_OSCCON.OSCVAL has to be selected in a way that fOSCREF is
2.5 MHz.
Note: fOSCREF has to be within the range of 2 MHz to 3 MHz and should be as close as
possible to 2.5 MHz.
The monitored frequency is too low if it is below 1.25 MHz and too high if it is above
7.5 MHz. This leads to the following two conditions:
•
•
Too low: fOSC < 1.25 MHz × (SCU_OSCCON.OSCVAL+1)
Too high: fOSC > 7.5 MHz × (SCU_OSCCON.OSCVAL+1)
Note: The accuracy is 30% for these boundaries.
Data Sheet
89
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Electrical ParametersAC Parameters
5.3.5
Table 26
ERAY Phase Locked Loop (ERAY_PLL)
PLL_ERAY Parameters
Parameter
Symbol
Values
Min.
Unit
Typ.
Max.
Accumulated jitter at
SYSCLK pin
DPP CC -0.8
−
0.8
ns
Accumulated_Jitter
DP CC -0.5
fPLLBASE_ 50
−
0.5
ns
250
360
MHz
PLL Base Frequency of
the ERAY PLL
ERAY
Note /
Test Condition
CC
VCO input frequency of
the ERAY PLL
fREF CC 20
−
40
MHz
VCO frequency range of
the ERAY PLL
fVCO_ERA 450
−
500
MHz
Y CC
PLL lock-in time
tL CC
−
200
μs
5.6
Note: The specified PLL jitter values are valid if the capacitive load per pin does not
exceed CL = 20 pF with the maximum driver and sharp edge.
Note: The maximum peak-to-peak noise on the pad supply voltage, measured between
VDDPF3 and VSSOSC, is limited to a peak-to-peak voltage of VPP = 100 mV for noise
frequencies below 300 KHz and VPP = 40 mV for noise frequencies above
300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage
as near as possible to the supply pins and using PCB supply and ground planes.
Data Sheet
90
V 1.1.1, 2014-05
TC1784
Electrical ParametersAC Parameters
5.3.6
JTAG Interface Timing
The following parameters are applicable for communication through the JTAG debug
interface. The JTAG module is fully compliant with IEEE1149.1-2000.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Table 27
JTAG Interface Timing Parameters
(Operating Conditions apply)
Parameter
Min.
Typ.
Max.
Unit Note /
Test Condition
t1 SR
t2 SR
t3 SR
t4 SR
t5 SR
t6 SR
25
–
–
ns
–
10
–
–
ns
–
10
–
–
ns
–
–
–
4
ns
–
–
–
4
ns
–
6
–
–
ns
–
t7 SR
6
–
–
ns
–
TDO valid after TCK falling t8 CC
edge1) (propagation delay) t CC
8
–
–
13
ns
CL = 50 pF
3
–
–
ns
CL = 20 pF
TDO hold after TCK falling t18 CC
edge1)
2
–
–
ns
TDO high imped. to valid
from TCK falling edge1)2)
t9 CC
–
–
14
ns
CL = 50 pF
TDO valid to high imped.
from TCK falling edge1)
t10 CC
–
–
13.5
ns
CL = 50 pF
TCK clock period
TCK high time
TCK low time
TCK clock rise time
TCK clock fall time
TDI/TMS setup
to TCK rising edge
TDI/TMS hold
after TCK rising edge
Symbol
Values
1) The falling edge on TCK is used to generate the TDO timing.
2) The setup time for TDO is given implicitly by the TCK cycle time.
Data Sheet
91
V 1.1.1, 2014-05
TC1784
Electrical ParametersAC Parameters
t1
0.9 VD D P
0.5 VD D P
t5
t2
0.1 VD D P
t4
t3
MC_ JTAG_ TCK
Figure 10
Test Clock Timing (TCK)
TCK
t6
t7
t6
t7
TMS
TDI
t9
t8
t1 0
TDO
t18
Figure 11
Data Sheet
MC_JTAG
JTAG Timing
92
V 1.1.1, 2014-05
TC1784
Electrical ParametersAC Parameters
5.3.7
DAP Interface Timing
The following parameters are applicable for communication through the DAP debug
interface.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Table 28
DAP Parameters
Parameter
Symbol
DAP0 clock period1)
tTCK SR
t12 SR
t13 SR
t14 SR
t15 SR
t16 SR
DAP0 high time
1)
DAP0 low time
DAP0 clock rise time
DAP0 clock fall time
DAP1 setup to DAP0
rising edge
Values
Unit
Min.
Typ.
Max.
12.5
−
−
ns
4
−
−
ns
4
−
−
ns
−
−
2
ns
−
−
2
ns
6.0
−
−
ns
DAP1 hold after DAP0
rising edge
t17 SR
6.0
−
−
ns
DAP1 valid per DAP0
clock period2)
t19 CC
8
−
−
ns
10
−
−
ns
Note /
Test Condition
CL= 20 pF;
f= 80 MHz
CL= 50 pF;
f= 40 MHz
1) See the DAP chapter for clock rate restrictions in the Active:IDLE protocol state.
2) The Host has to find a suitable sampling point by analyzing the sync telegram response.
t11
0.9 VD D P
0.5 VD D P
t1 5
t1 2
t14
0.1 VD D P
t1 3
MC_DAP0
Figure 12
Data Sheet
Test Clock Timing (DAP0)
93
V 1.1.1, 2014-05
TC1784
Electrical ParametersAC Parameters
DAP0
t1 6
t1 7
DAP1
MC_ DAP1_RX
Figure 13
DAP Timing Host to Device
t1 1
DAP1
t1 9
MC_ DAP1_TX
Figure 14
Data Sheet
DAP Timing Device to Host
94
V 1.1.1, 2014-05
TC1784
Electrical ParametersAC Parameters
5.3.8
Peripheral Timings
Note: Peripheral timing parameters are not subject to production test. They are verified
by design/characterization.
5.3.8.1
Micro Link Interface (MLI) Timing
MLI Transmitter Timing
t13
t14
t10
t12
TCLKx
t11
t15
t15
TDATAx
TVALIDx
t16
t17
TREADYx
MLI Receiver Timing
t23
t24
t20
RCLKx
t22
t21
t25
t26
RDATAx
RVALIDx
t27
t27
RREADYx
MLI_Tmg_2.vsd
Figure 15
MLI Interface Timing
Note: The generation of RREADYx is in the input clock domain of the receiver. The
reception of TREADYx is asynchronous to TCLKx.
Data Sheet
95
V 1.1.1, 2014-05
TC1784
Electrical ParametersAC Parameters
The MLI parameters are vaild for CL = 50 pF and strong driver medium edge.
Table 29
MLI Receiver
Parameter
Symbol
Values
Unit
Min.
Typ.
1 / fFPI
−
−
ns
−
0.5 x
−
ns
−
ns
−
4
ns
−
−
4
ns
4.2
−
−
ns
RDATA/RVALID hold time t26 CC
after RCLK falling edge
2.2
−
−
ns
RREADY output delay
time
0
−
16
ns
RCLK clock period
RCLK high time1)2)
t20 SR
t21 SR
Max.
Note /
Test Condition
t20
RCLK low time1)2)
t22 SR
−
0.5 x
t20
RCLK rise time3)
RCLK fall time
3)
RDATA/RVALID setup
time before RCLK falling
edge
t23 SR
t24 SR
t25 SR
t27 CC
−
1) The following formula is valid: t21 + t22 = t20.
2) Min and Max values for this parameter can be derived from the typ. value by considering the other receiver
timing parameters.
3) The RCLK max. input rise/fall times are best case parameters for fSYS = 90 MHz. For reduction of EMI, slower
input signal rise/fall times can be used for longer RCLK clock periods.
Table 30
MLI Transmitter
Parameter
TCLK clock period
Symbol
t10 CC
Values
Unit
Min.
Typ.
Max.
2x1/
−
−
ns
0.45 x
0.5 x
0.55 x
ns
t10
t10
t10
0.45 x
0.5 x
0.55 x
t10
t10
t10
−
−
0.3 x
Note /
Test Condition
fFPI
TCLK high time1)2)
TCLK low time1)2)
TCLK rise time
Data Sheet
t11 CC
t12 CC
t13 CC
96
t103)
ns
ns
V 1.1.1, 2014-05
TC1784
Electrical ParametersAC Parameters
MLI Transmitter (cont’d)
Table 30
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
TCLK fall time
t14 CC
−
−
0.3 x
ns
TDATA/TVALID output
delay time
t15 CC
-3
−
4.4
ns
TREADY setup time
before TCLK rising edge
t16 SR
18
−
−
ns
TREADY hold time after
TCLK rising edge
t17 SR
-2
−
−
ns
t103)
Note /
Test Condition
1) The following formula is valid: t11 + t12 = t10.
2) The min./max. TCLK low/high times t11/t12 include the PLL jitter of fSYS. Fractional divider settings must be
regarded additionally to t11 / t12.
3) For high-speed MLI interface, strong driver sharp or medium edge selection (class A2 pad) is recommended
for TCLK.
5.3.8.2
Micro Second Channel (MSC) Interface Timing
The MSC parameters are vaild for CL = 50 pF.
Table 31
MSC Parameters
Parameter
Symbol
FCLP clock period1)2)
t40 CC
SOP4)/ENx outputs delay
from FCLP4) rising edge
t45 CC
Data Sheet
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
2x
−
−
ns
-2
−
5
ns
ENx with strong
driver and
sharp (minus )
edge
-2
−
10
ns
ENx with strong
driver and
medium
(minus) edge
0
−
21
ns
ENx with strong
driver and soft
edge
TMSC3)
97
V 1.1.1, 2014-05
TC1784
Electrical ParametersAC Parameters
Table 31
MSC Parameters (cont’d)
Parameter
Symbol
SDI bit time
t46 CC
Values
Unit
Min.
Typ.
Max.
8x
−
−
ns
−
−
200
ns
−
−
200
ns
Note /
Test Condition
TMSC
SDI rise time
t48 SR
t49 SR
SDI fall time
1) FCLP signal rise/fall times are only defined by the pad rise/fall times.
2) FCLP signal high and low can be minimum 1xTMSC
3) TMSC = TSYS = 1 / fSYS.
4) SOP / FCLP either propagated by LVDS or by CMOS strong driver and non soft edge.
t40
0.9 VDDP
0.1 VDDP
FCLP
t45
t45
SOP
EN
t48
t49
0.9 VDDP
0.1 VDDP
SDI
t46
Figure 16
t46
MSC_Tmg_1.vsd
MSC Interface Timing
Note: The data at SOP should be sampled with the falling edge of FCLP in the target
device.
Data Sheet
98
V 1.1.1, 2014-05
TC1784
Electrical ParametersAC Parameters
5.3.8.3
SSC Master/Slave Mode Timing
The SSC parameters are vaild for CL = 50 pF and strong driver medium edge.
Table 32
SSC Parameters
Parameter
SCLK clock period1)2)3)
Symbol
t50 CC
Values
Unit
Min.
Typ.
Max.
2x1/
−
−
ns
Note /
Test Condition
fFPI
MTSR/SLSOx delay form
SCLK rising edge
t51 CC
0
−
8
ns
MRST setup to SCLK
latching edge3)
t52 SR
16.5
−
−
ns
MRST hold from SCLK
latching edge3)
t53 SR
0
−
−
ns
SCLK input clock
period1)3)
t54 SR
4x1/
−
−
ns
SCLK input clock duty
cycle
t55_t54
45
−
55
%
MTSR setup to SCLK
latching edge3)4)
t56 SR
1 / fFPI
−
−
ns
MTSR hold from SCLK
latching edge
t57 SR
1 / fFPI
+5
−
−
ns
SLSI setup to first SCLK
latching edge
t58 SR
1 / fFPI
+5
−
−
ns
SLSI hold from last SCLK t59 SR
latching edge 5)
7
−
−
ns
MRST delay from SCLK
shift edge
t60 CC
0
−
16.5
ns
SLSI to valid data on
MRST
t61 CC
−
−
16.5
ns
fFPI
SR
1) SCLK signal rise/fall times are the same as the rise/fall times of the pad.
2) SCLK signal high and low times can be minimum 1xTSSC.
3) TSSCmin = TSYS = 1/fSYS.
4) Fractional divider switched off, SSC internal baud rate generation used.
5) For CON.PH=1 slave select must not be removed before the following shifting edge. This mean, that what ever
is configured (shifting / latching first), SLSI must not be de-actived before the last trailing edge from the pair
of shifting / latching edges.
Data Sheet
99
V 1.1.1, 2014-05
TC1784
Electrical ParametersAC Parameters
t50
SCLK1)2)
t51
t51
MTSR1)
t52
t53
Data
valid
1)
MRST
t51
2)
SLSOn
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
2) The transition at SLSOn is based on the following setup: SSOTC.TRAIL = 0
and the first SCLK high pulse is in the first one of a transmission.
SSC_TmgMM
Figure 17
SSC Master Mode Timing
t54
First latching
SCLK edge
First shift
SCLK edge
SCLK1)
t55
t56
Last latching
SCLK edge
t55
t56
t57
Data
valid
1)
MTSR
t57
Data
valid
t60
t60
1)
MRST
t61
SLSI
t59
t58
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
Figure 18
Data Sheet
SSC_TmgSM
SSC Slave Mode Timing
100
V 1.1.1, 2014-05
TC1784
Electrical ParametersAC Parameters
5.3.8.4
ERAY Interface Timing
The timings of this section are valid for the strong driver and either sharp edge or medium
edge settings of the output drivers with CL = 25 pF.
Table 33
ERAY Parameters
Parameter
Symbol
Values
Time span from last BSS
to FES without the
influence of quartz
tolerancies (d10Bit_TX)1)
t60 CC
997.75 −
1002.2 ns
5
TxD data valid from
fsample flip flop txd_reg
TxDA, TxDB
(dTxAsym)2)3)
t61-t62
−
−
1.5
Time span between last
BSS and FES without
influence of quartz
tolerancies
(d10Bit_RX)1)4)5)
t63 SR
966
−
1046.1 ns
RxD capture by fsample
(RxDA/RxDB sampling
flip-flop) (dRxAsym)5)
t64-t65
−
−
3.0
ns
Asymmetrical
delay of rising
and falling edge
(RxDA, RxDB)
TxD data delay from
sampling flip-flop
dTxdly
−
−
10.0
ns
Px_PDR.PDy =
000B
−
−
15.0
ns
Px_PDR.PDy =
001B
−
−
10.0
ns
Min.
RxD capture delay by
sampling flip-flop
Typ.
Unit
Max.
ns
CC
CC
CC
dRxdly
Note /
Test Condition
Asymmetrical
delay of rising
and falling edge
(TxDA, TxDB)
CC
1) This includes the PLL_ERAY accumulated jitter.
2) Refers to delays caused by the asymmetries of the output drivers of the digital logic and the GPIO pad drivers.
Quarz tolerance and PLL_ERAY accumulated jitter are not included.
3) E-Ray TxD output drivers have an asymmetry of rising and falling edges of |tFA2 - tRA2| ≤ 1 ns.
4) Limits of 966ns and 1046.1ns correspond to (30%, 70%) * VDDP FlexRay standard input thresholds. For input
thresholds of this product, a correction of - 0.5 ns and +0.1 ns has to be applied.
5) Valid for output slopes of the bus driver of dRxSlope ≤ 5ns, 20% * VDDP to 80% * VDDP, according to the
FlexRay Electrical Physical Layer Specification V2.1B. For A2 pads, the rise and fall times of the incoming
signal have to satisfy the following inequality: -1.6ns ≤ tFA2 - tRA2 ≤ 1.3ns.
Data Sheet
101
V 1.1.1, 2014-05
TC1784
Electrical ParametersAC Parameters
Last CRC Byte
BSS
(Byte Start Sequence)
FES
(Frame End Sequence)
0.7 VDD
0.3 VDD
TXD
t60
tsample
TXD
0.9 VDD
0.1 VDD
t61
t62
Last CRC Byte
BSS
(Byte Start Sequence)
FES
(Frame End Sequence)
0.7 VDD
0.3 VDD
RXD
t63
tsample
RXD
0.7 VDD
0.3 VDD
t64
t65
ERAY_TIMING
Figure 19
Data Sheet
ERAY Timing
102
V 1.1.1, 2014-05
TC1784
Electrical ParametersAC Parameters
5.3.8.5
EBU Timings
EBU Asynchronous Timings
VSS = 0 V;VDD = 1.3 V ± 5%; VDDEBU = 2.5 V ± 5% and 3.3 V ± 5%, Class A2 pins;
CL = 35 pF for address/data; CL = 40pF for the control lines.
For each timing, the accumulated PLL jitter of the programed duration in number of clock
periods must be added separately. Operating conditions apply and CL = 35 pF.
Table 34
EBU Common Asynchronous Timings
Parameter
Symbol
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
Pulse wdih deviation from ta CC
the ideal programmed
width due to B pad
asymmetry, rise delay - fall
delay
-0.8
−
0.8
ns
edge= medium
-0.8
−
0.8
ns
edge= sharp
AD(31:0) output delay to
ADV# rising edge,
multiplexed read / write
t13 CC
-5.5
−
2
ns
AD(31:0) output delay to
ADV# rising edge,
multiplexed read / write
t14 CC
-5.5
−
2
ns
Table 35
Parameter
EBU Asynchronous Read Timings
Symbol
Values
Unit
Min.
Typ.
Max.
A(23:0) output delay to RD t0 CC
rising edge, deviation from
the ideal programmed
value
-2.5
−
2.5
ns
A(23:0) output delay to RD t1 CC
rising edge, deviation from
the ideal programmed
value
-2.5
−
2.5
ns
Data Sheet
103
Note /
Test Condition
V 1.1.1, 2014-05
TC1784
Electrical ParametersAC Parameters
Table 35
Parameter
EBU Asynchronous Read Timings (cont’d)
Symbol
Values
Unit
Min.
Typ.
Max.
CS rising edge to RD
t2 CC
rising edge, deviation from
the ideal programmed
value
-2
−
2.5
ns
ADV rising edge to RD
t3 CC
rising edge, deviation from
the ideal programmed
value
-1.5
−
4.5
ns
BC rising edge to RD
t4 CC
rising edge, deviation from
the ideal programmed
value
-2.5
−
2.5
ns
WAIT input setup to RD
t5 SR
rising edge, deviation from
the ideal programmed
value
12
−
−
ns
WAIT input hold to RD
t6 SR
rising edge, deviation from
the ideal programmed
value
0
−
−
ns
Data input setup to RD
t7 SR
rising edge, deviation from
the ideal programmed
value
12
−
−
ns
Data input hold to RD
t8 SR
rising edge, deviation from
the ideal programmed
value
0
−
−
ns
t9 CC
MR / W output delay to
RD# rising edge, deviation
from the ideal
programmed value
-2.5
−
1.5
ns
Data Sheet
104
Note /
Test Condition
V 1.1.1, 2014-05
TC1784
Electrical ParametersAC Parameters
EBU
STATE
Address
Phase
Address Hold
Phase (opt.)
Command
Delay Phase
Command
Phase
Recovery
Phase (opt.)
New Addr.
Phase
Control Bitfield:
ADDRC
AHOLDC
CMDDELAY
RDWAIT
RDRECOVC
ADDRC
1...15
0...15
0...7
1...31
Duration Limits in
EBU_CLK Cycles
0...15
1...15
Next
Addr.
Valid Address
A[23:0]
pv + t0
pv + ta
CS[3:0]
CSCOMB
pv + ta
pv +
pv +
t1
t2
t3
ADV
pv +
ta
RD
pv +
ta
pv +
ta
t4
BC[3:0]
pv +
t5
t6
WAIT
pv +
AD[31:0]
MR/W
t13
pv +
t14
t7
Address Out
Data In
pv +
t9
pv = programmed value,
TEBU_CLK * sum (correponding bitfield values)
Figure 20
Data Sheet
t8
new_MuxRD_Async_10.vsd
Multiplexed Read Access
105
V 1.1.1, 2014-05
TC1784
Electrical ParametersAC Parameters
EBU
STATE
Control Bitfield:
Duration Limits in
EBU_CLK Cycles
Address
Phase
Address Hold
Phase (opt.)
Command
Phase
Recovery
Phase (opt.)
New Addr.
Phase
ADDRC
AHOLDC
RDWAIT
RDRECOVC
ADDRC
1...15
0...15
1...31
0...15
Next
Addr.
Valid Address
A[23:0]
pv +
pv + t1
t0
pv +
CS[3:0]
CSCOMB
pv +
1...15
t2
ta
pv + t3
ta
ADV
pv +
ta
RD
pv +
ta
pv + ta
t4
BC[3:0]
pv +
t5
t6
WAIT
t7
AD[31:0]
Data In
MR/W
pv +
pv = programmed value,
TEBU_CLK * sum (correponding bitfield values)
Figure 21
Data Sheet
t8
t9
new_DemuxRD_Async_10.vsd
Demultiplexed Read Access
106
V 1.1.1, 2014-05
TC1784
Electrical ParametersAC Parameters
Table 36
Parameter
EBU Asynchnronous Write Timings
Symbol
Values
Unit
Min.
Typ.
Max.
t30 CC
A(23:0) output delay to
WR rising edge, deviation
from the ideal
programmed value
-2.5
−
2.5
ns
A(23:0) output delay to
t31 CC
WR rising edge, deviation
from the ideal
programmed value
-2.5
−
2.5
ns
CS rising edge to WR
t32 CC
rising edge, deviation from
the ideal programmed
value
-2
−
2
ns
ADV rising edge to WR
t33 CC
rising edge, deviation from
the ideal programmed
value
-2.5
−
2
ns
BC rising edge to WR
t34 CC
rising edge, deviation from
the ideal programmed
value
-2.5
−
2
ns
WAIT input setup to WR t35 SR
rising edge, deviation from
the ideal programmed
value
12
−
−
ns
WAIT input hold to WR
t36 SR
rising edge, deviation from
the ideal programmed
value
0
−
−
ns
Data output delay to WR t37 CC
rising edge, deviation from
the ideal programmed
value
-5.5
−
2
ns
Data Sheet
107
Note /
Test Condition
V 1.1.1, 2014-05
TC1784
Electrical ParametersAC Parameters
Table 36
Parameter
EBU Asynchnronous Write Timings (cont’d)
Symbol
Values
Unit
Min.
Typ.
Max.
Data output delay to WR t38 CC
rising edge, deviation from
the ideal programmed
value
-5.5
−
2
ns
MR / W output delay to
t39 CC
WR rising edge, deviation
from the ideal
programmed value
-2.5
−
1.5
ns
Data Sheet
108
Note /
Test Condition
V 1.1.1, 2014-05
TC1784
Electrical ParametersAC Parameters
EBU
STATE
Address
Phase
Address Hold
Phase (opt.)
Command
Phase
Data
Hold Phase
Recovery
Phase (opt.)
Control Bitfield:
ADDRC
AHOLDC
RDWAIT
DATAC
RDRECOVC
1...31
0...15
Duration Limits in
EBU_CLK Cycles
1...15
0...15
A[23:0]
0...15
pv + t30
pv +
ADDRC
1...15
Next
Addr.
Valid Address
CS[3:0]
CSCOMB
New Addr.
Phase
pv + t31
ta
pv + t32
pv + t33
pv + ta
ADV
pv +
ta
RD/WR
pv +
ta
pv + ta
BC[3:0]
t34
t35
WAIT
t36
t14
pv + t13
AD[31:0]
MR/W
pv + t37
pv + t38
Data Out
Address Out
pv + t39
pv = programmed value,
TEBU_CLK * sum (correponding bitfield values)
Figure 22
Data Sheet
new_MuxWR_Async_10.vsd
Multiplexed Write Access
109
V 1.1.1, 2014-05
TC1784
Electrical ParametersAC Parameters
EBU
STATE
Address
Phase
Control Bitfield:
ADDRC
Duration Limits in
EBU_CLK Cycles
1...15
Address Hold
Phase (opt.)
AHOLDC
0...15
A[23:0]
Command
Phase
Data
Hold Phase
RDWAIT
DATAC
1...31
0...15
Recovery
Phase (opt.)
RDRECOVC
0...15
pv + t30
pv +
ADDRC
1...15
Next
Addr.
Valid Address
CS[3:0]
CSCOMB
New Addr.
Phase
pv + t31
ta
pv + t32
pv + t33
pv + ta
ADV
pv +
ta
RD/WR
pv +
ta
pv + ta
BC[3:0]
t34
t35
WAIT
t36
pv + t37
AD[31:0]
MR/W
Data Out
pv + t39
pv = programmed value,
TEBU_CLK * sum (correponding bitfield values)
Figure 23
Data Sheet
pv + t38
new_DemuxWR_Async_10.vsd
Demultiplexed Write Access
110
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TC1784
Electrical ParametersPackage and Reliability
5.4
Package and Reliability
5.4.1
Package Parameters
Table 37
Thermal Characteristics of the Package
Device
Package
TC1784
PG-LFBGA-292- 6,8
6
RΘJCT1)
RΘJCB1) RΘJLead Unit Note
4,8
17,0
K/W
1) The top and bottom thermal resistances between the case and the ambient (RTCAT, RTCAB) are to be combined
with the thermal resistances between the junction and the case given above (RTJCT, RTJCB), in order to calculate
the total thermal resistance between the junction and the ambient (RTJA). The thermal resistances between the
case and the ambient (RTCAT, RTCAB) depend on the external system (PCB, case) characteristics, and are
under user responsibility.
The junction temperature can be calculated using the following equation: TJ = TA + RTJA × PD, where the RTJA
is the total thermal resistance between the junction and the ambient. This total junction ambient resistance
RTJA can be obtained from the upper four partial thermal resistances.
Thermal resistances as measured by the ’cold plate method’ (MIL SPEC-883 Method 1012.1).
Data Sheet
111
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TC1784
Electrical ParametersPackage and Reliability
Package Outline
292x
0.5 ±0.05
0.15 M C A B
0.08 M C
1.7 MAX
A
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1 7 ±0 .1
0.1 C
CODE
COPLANARITY
INDEX MARKING
(LASERED )
S E A TIN G P LA N E
292x
0.15
C
Y W V U T R P N M L K J HG F E D C B A
19 x 0 .8 = 1 5. 2
17 ±0. 1
B
0 .8
5.4.2
INDEX
MARKING
0.8
19 x 0.8 = 15.2
0.33 MIN
STANDOFF
Figure 24
Package Outlines PG-LFBGA-292-6
You can find all of our packages, sorts of packing and others in our Infineon Internet
Page “Products”: http://www.infineon.com/products.
5.4.3
Flash Memory Parameters
The data retention time of the TC1784’s Flash memory depends on the number of times
the Flash memory has been erased and programmed.
Table 38
FLASH32 Parameters
Parameter
Symbol
Values
Min.
Unit
Typ.
Max.
Data Flash Erase Time
per Sector
tERD CC −
−
31)
s
Program Flash Erase
Time per 256 KByte
Sector
tERP CC −
−
5
s
Data Sheet
112
Note /
Test Condition
V 1.1.1, 2014-05
TC1784
Electrical ParametersPackage and Reliability
Table 38
FLASH32 Parameters (cont’d)
Parameter
Symbol
Values
Unit
Note /
Test Condition
5.3
ms
without
reprogramming
−
15.9
ms
with two
reprogramming
cycles
tPRP CC −
−
5.3
ms
without
reprogramming
−
−
10.6
ms
with one
reprogramming
cycle
−
cycle Min. data
s
retention time 5
years
Min.
Program time data flash
per page2)
Program time program
flash per page3)
Data Flash Endurance
Typ.
Max.
tPRD CC −
−
−
NE CC
60000 −
4)
tFL_ErSusp −
−
15
ms
tFL_Margin 10
−
−
μs
Program Flash Retention
Time, Physical Sector5)6)
tRET CC 20
−
−
year
s
Max. 1000
erase/program
cycles
Program Flash Retention
Time, Logical Sector5)6)
tRETL CC 20
−
−
year
s
Max. 100
erase/program
cycles
UCB Retention Time5)6)
tRTU CC 20
−
−
year
s
Max. 4
erase/program
cycles per UCB
Wake-Up time
tWU CC
WSDF
−
270
μs
Erase suspend delay
CC
Wait time after margin
change
DFlash wait state
configuration
PFlash wait state
configuration
Del CC
CC
WSPF
CC
−
50 ns x −
fFSI
26 ns x −
fFSI
−
−
1) In case of wordline oriented defects (see robust EEPROM emulation in the User's Manual) this erase time can
increase by up to 100%.
2) In case the Program Verify feature detects weak bits, these bits will be programmed up to twice more. Each
reprogramming takes additional 5 ms.
Data Sheet
113
V 1.1.1, 2014-05
TC1784
Electrical ParametersPackage and Reliability
3) In case the Program Verify feature detects weak bits, these bits will be programmed once more. The
reprogramming takes additional 5 ms.
4) Only valid when a robust EEPROM emulation algorithm is used. For more details see the User´s Manual.
5) Storage and inactive time included.
6) At average weighted junction temperature Tj = 100°C, or the retention time at average weighted temperature
of Tj = 110°C is minimum 10 years, or the retention time at average weighted temperature of Tj = 150°C is
minimum 0.7 years.
5.4.4
Table 39
Quality Declarations
Quality Parameters
Parameter
Symbol
Values
Unit
Note / Test Condition
Min. Typ. Max.
–
–
24000 hours –2)
ESD susceptibility VHBM
according to
Human Body
Model (HBM)
–
–
2000
V
Conforming to
JESD22-A114-B
ESD susceptibility VHBM1
of the LVDS pins
–
–
500
V
–
ESD susceptibility VCDM
according to
Charged Device
Model (CDM)
–
–
500
V
Conforming to
JESD22-C101-C
Moisture
Sensitivity Level
–
–
3
–
Conforming to Jedec
J-STD-020C for 240°C
Operation
Lifetime1)
tOP
MSL
1) This lifetime refers only to the time when the device is powered on.
2) For worst-case temperature profile equivalent to:
1200 hours at Tj = 125...150oC
3600 hours at Tj = 110...125oC
7200 hours at Tj = 100...110oC
11000 hours at Tj = 25...100oC
1000 hours at Tj = -40...25oC
Data Sheet
114
V 1.1.1, 2014-05
TC1784
History
6
History
The Version 0.7 is the first version of this document:
The following changes where done between Version 0.7 and 0.71 of this document:
•
•
update and coorect figure 3-2
update and correct table 3-1
The following changes where done between Version 0.71 and 1.0 of this document:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
adapt Absolute Maximum Rating
clarify pad supply levels in Pin Reliability in Overload section
add note at the end of Pin Reliability in Overload section
clarify wording for valid operating conditions
split FADC DNL parameter into two conditions and change value for gain 4 and 8
add footnote 5 to IDDP
add footnote for D-Flash currents in power section
rework first sentence for chapter 5.3
reduce min value for tL for both PLLs
add for MLI and SSC timing parameter: valid strong driver medium edge only
change MLI parameter t17 min value
update parameter description for SSC parameters t52, t53, t56, t57, t58, and t59
change SSC parameters from CC to SR Symbol for t56, t57, t58 and t59
add footnote to Flash parameter tERD
The following changes where done between Version 1.0 and 1.1 of this document:
•
•
•
•
•
•
•
remove the following product options:
– SAK-TC1784N-320F180EL
add the following product options:
– SAK-TC1784F-320F180EP
change t48 from 100ns to 200ns in table 42
change t49 from 100ns to 200ns in table 42
extend KOVAN conditon from IOV≤ 0 mA; IOV≥ -1 mA to IOV≤ 0 mA; IOV≥ -2 mA
change parameter EFOFF from +-90mV to +-120 for condition Calibration = No
change package version from PG-LFBGA-292-3 to PG-LFBGA-292-6
The following changes where done between Version 1.1 and 1.1.1 of this document:
•
change parameter EFOFF from +-120mV to +-90 for condition Calibration = No
Data Sheet
115
V 1.1.1, 2014-05
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG