[AKD4141-A] AKD4141-A Evaluation board Rev.2 for AK4141 GENERAL DESCRIPTION The AKD4141 is an evaluation board for the AK4141, digital stereo decoder with stereo sample rate converter, digital switches and sound processing functions. The AKD4141 has the analog/digital audio interface and can achieve the interface with analog/digital audio systems via BNC/RCA/OPT-connector. Ordering guide AKD4141-A --- Evaluation board for AK4141 (Cable for connecting with printer port of IBM-AT,compatible PC and control software are packed with this. This control software does not support Windows NT.) FUNCTION • DIT/DIR with optical input/output • 10pin Header for digital audio I/F and serial control I/F • BNC connector for an external clock input 9V, 5V, 3.3V, 1.8V AK4114 (DIR) Opt In AGND, DGND AK4114 (DIT) 9V Æ 5V 5V Æ 3.3V 3.3V Æ 1.8V Opt Out Regulator COAX COAX EXT 10pin Header 10pin Header AK4141 DSP Data Opt Out DSP Data 10pin Header Serial Control X’tal LOUT1 SIF1 LIN1 ROUT1 AK4682 (CODEC) SIF2 LOUT2 ROUT2 RIN1 Figure 1. AKD4141 Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual <KM088102> 2007/11 -1- [AKD4141-A] Evaluation Board Manual Operation sequence 1) Set up the power supply lines. (1-1) In case of using the regulator.<Default> [9V] (red) [TVDD] (red) [AVDD1] (red) [AVDD2] (red) [Logic] (red) [DVDD] (red) [AGND] (black) [DGND] (black) = = = = = = = = +9V open open open open open 0V 0V (for regulator and PVDD of AK4682) (analog ground) (digital ground) (Note) TVDD, AVDD1, AVDD2 of AK4141 and Logic is supplied “3.3V” from regulator (T2). DVDD of AK4141 is supplied “1.8V” from regulator (T3). AVDD1, AVDD2, DVDD1 and DVDD2 of AK4682 is supplied “5V” from regulator (T1). (1-2) In case of using the power supply connectors. [9V] (red) [TVDD] (red) [AVDD1] (red) [AVDD2] (red) [Logic] (red) [DVDD] (red) [AGND] (black) [DGND] (black) = = = = = = = = +9V +3.3V +3.3V +3.3 V +3.3V +1.8V 0V 0V (for PVDD of AK4682) (for TVDD of AK4682 and AK4141) (for AVDD of AK4141) (for AVDD2 of AK4141) (for VDD of AK4114 (DIR, DIT) and logic) (for DVDD of AK4141) (analog ground) (digital ground) (Note) AVDD1, AVDD2, DVDD1 and DVDD2 of AK4682 is supplied “5V” from regulator (T1). 2) Set up the jumper pins and switches. (See the followings.) 3) Power on. The AK4141, AK4682, AK4114 (DIR), AK4114 (DIT) should be reset once bringing toggle SW “L” upon power-up. Please refer to Talble 1.on this page about setting of toggle SW. Setting of the toggle SW SW2 PDN_AK4141 SW3 PDN-CODEC SW5 PDN-DIR SW7 PDN-DIT PDN SW of AK4141 (U2). Keep “H” during normal operation. PDN SW of AK4682 (U5). Keep “H” during normal operation. Keep “L” when AK4682 is not used. PDN SW of AK4114 (U7). Keep “H” during normal operation. Keep “L” when AK4114 is not used. PDN SW of AK4114 (U9). Keep “H” during normal operation. Keep “L” when AK4114 is not used. Table 1. Setting of the toggle SW <KM088102> 2007/11 -2- [AKD4141-A] Indication for LED LED1 INT LED2 INT0 Output of INT pin of the AK4141 (U2). Turns on when PLL of the AK4141 (U2) is unlocked. Output of INT0 pin of the AK4114 (U7). Turns on when the AK4114 (U7) is unlocked. Table 2. Indication for LED Setting of jumper pins No 21 Name TVDD 23 AVDD1 24 AVDD2 26 Logic 22 DVDD 25 GND 20 M/S CODEC 27 TXIN 28 RX 34 TX 2 EXT-T 132 MCKI Setting TVDD power supply REG: TVDD is supplied from regulator (T2). “TVDD” connector should be open.<Default> TM: TVDD is supplied from “TVDD” connector. AVDD1 power supply REG: AVDD1 is supplied from regulator (T2). “AVDD1” connector should be open.<Default> TM: AVDD1 is supplied from “AVDD1” connector. AVDD2 power supply REG: AVDD2 is supplied from regulator (T2). “AVDD2” connector should be open.<Default> TM: AVDD2 is supplied from “AVDD2” connector. VDD (Logic) power supply REG: VDD is supplied from regulator (T2). “Logic” connector should be open.<Default> TM: VDD is supplied from “Logic” connector. DVDD power supply REG: DVDD is supplied from regulator (T3). “DVDD” connector should be open.<Default> TM: DVDD is supplied from “DVDD” connector. Analog GND and Digital GND Open: Separated. Short: Common. <Default> Mode Setting of AK4682 Master: Master Mode. Slave: Slave Mode. <Default> Input of AK4141’s TXIN OPT: OPT of PORT3 (RX). GND: GND. <Default> Input of AK4114 (DIR)’s RX OPT: OPT of PORT3 (RX). <Default> COAX: BNC of J10 (COAX). Output of AK4114 (DIT)’s TX1 OPT: OPT of PORT5 (TX) <Default> COAX: BNC of J11 (COAX) Termination of J2 (External Clock) Open: No termination. <Default> Short: 51Ω. Input of AK4141’s MCKI DIR: IMCLK. <Default> EXT: External clock from J11. <KM088102> 2007/11 -3- [AKD4141-A] 4 LRCK5 5 SCLK5 6 LRCK4 7 SCLK4 9 SDTI5 12 SDTI4 13 SDTI3 15 SDTI2 17 SDTI1 8 SDTO 14 SDTIA1 16 SDTIA2 32 IMCLK 31 ILRCK 29 IBICK1 Input of AK4141’s LRCK5 OLRCK: OLRCK. ILRCK: ILRCK. <Default> Input of AK4141’s SCLK5 OBICK: OBICK. IBICK: IBICK. <Default> Input of AK4141’s LRCK4 OLRCK: OLRCK. ILRCK: ILRCK. <Default> Input of AK4141’s SCLK4 OBICK: OBICK IBICK: IBICK <Default> Input of AK4141’s SDTI5 DIR: SDTO of DIR (U7) <Default> ADC: SDTOB of AK4682 (U5). GND: GND. Input of AK4141’s SDTI4 DIR: SDTI of DIR (U7) <Default> ADC: SDTOB of AK4682 (U5). GND: GND. Input of AK4141’s SDTI3 DIR: SDTI of DIR (U7) <Default> ADC: SDTOB of AK4682 (U5). GND: GND. Input of AK4141’s SDTI2 DIR: SDTI of DIR (U7) <Default> ADC: SDTOB of AK4682 (U5). GND: GND. Input of AK4141’s SDTI2 DIR: SDTI of DIR (U7) <Default> ADC: SDTOB of AK4682 (U5). GND: GND. Input of DIT (U9)’s DAUX SDTO1: Output of AK4141’s SDTO1 <Default> SDTO2: Output of AK4141’s SDTO2 SDTO3: Output of AK4141’s SDTO3 Input of AK4682 (U5)’s SDTIA1 SDTO1: Output of AK4141’s SDTO1 <Default> SDTO2: Output of AK4141’s SDTO2 SDTO3: Output of AK4141’s SDTO3 Input of AK4682 (U5)’s SDTIA2 SDTO1: Output of AK4141’s SDTO1 <Default> SDTO2: Output of AK4141’s SDTO2 SDTO3: Output of AK4141’s SDTO3 IMCLK and DIR (U7)’s MCKO1 Open: Separated. Short: Connected. <Default> ILRCK and DIR (U7)’s LRCK Open: Separated. Short: Connected. <Default> IBICK and DIR (U7)’s BICK Open: Separated. Short: Connected. <Default> <KM088102> 2007/11 -4- [AKD4141-A] 30 SDTI 33 IBICK2 39 ILRCK 38 OLRCK 37 IBICK 36 OBICK1 35 SDTO 41 OBICK2 SDTI and DIR (U7)’s SDTO Open: Separated. Short: Connected. <Default> Polarity of IBICK THR: Through. <Default> INV: Invert. ILRCK and DIT (U9)’s LRCK Open: Separated. <Default> Short: Connected. OLRCK and DIT (U9)’s LRCK Open: Separated. <Default> Short: Connected. IBICK and DIT (U9)’s BICK Open: Separated. <Default> Short: Connected. OBICK and DIT (U9)’s BICK Open: Separated. <Default> Short: Connected. SDTO and DIT (U9)’s DAUX Open: Separated. <Default> Short: Connected. Polarity of OBICK THR: Through. <Default> INV: Invert. Table 3. Setting of jumper pins <KM088102> 2007/11 -5- [AKD4141-A] Evaluation mode The setup sequence from the initial state The AKD4141 can evaluate various mode using AK4682 (CODEC), AK4114 (DIR) and AK4114 (DIT). Set jumper pins and SW to condition to evaluate. About AK4141 and AK4682, refer to each datasheet. About DIR and DIT, refer to Table 5.~ Table 10. in this manual. Follows are setting examples of AK4141’s decoder. Measurement path : ٠SIF (J1) → AK4141 (Stereo decoder) → DAC (AK4682) → LOUT1/ROUT1 ٠SIF (J1) → AK4141 (Stereo decoder) → DIT (AK4141) → TX (PORT1) Setting of AK4141 : Using X’tal Oscillator, Master mode MCLK=256fjs, fs=48kHz. (1) Setting of MCLK. X’tal Oscillator (X1) is used. 12.288MHz (fs=48kHz, MCLK=256fs) is equipped on the board by initial setting. When evaluate it in other conditions, please attach a X’tal oscillator according to evaluation mode. (2) Setting of DIP SW1. (2-1) Setting of Master Mode Please set MSN (No.6) of DIP SW1 to “H”. (Master Mode : MCKI=256fs) (2-2) Setting of SIF input. Please set 6M5 pin and 4M5[2-0] pin according to carrier frequency. (2-2-1) In case of including the 6.5MHz carrier. 6M5 (No.5) of DIP SW1 = “L” : L NICAM. 6M5 (No.5) of DIP SW1 = “H” : D/K (2-2-2) In case of including the 4.5MHz carrier. 4M5[2-0] (No.4-2) of DIP SW1 = “LHL” : EIAJ. 4M5[2-0] (No.4-2) of DIP SW1 = “LLH” : M-Korea. 4M5[2-0] (No.4-2) of DIP SW1 = “LLL” : PAL (Chroma Carrier) 4M5[2-0] (No.4-2) of DIP SW1 = “HLL” : FM-Stereo Radio EU 4M5[2-0] (No.4-2) of DIP SW1 = “HHH” : FM-Stereo Radio US (Note.) The details please refer to Table 4. in this manual. (3) Setting of the jumper pins. Jumper pins should be set as follows. Please set JP14 and JP16 according to the output of AK4141. The following are setting examples of JP14=SDTO1 and JP16=SDTO2. JP10 LRCK ILRCK OLRCK JP11 SCLK IBICK OBICK Master Slave JP16 SDTIA2 JP14 SDTIA1 JP20 M/S CODEC SDTO1 SDTO2 SDTO3 SDTO1 SDTO2 SDTO3 (4) Please set toggle SW2 (AK4141) to “H”. (5) Please write register of AK4141 with control software. The following is register setting from the initial state of AK4141. 01H : MCKE bit & MCKD bit “0” → “1” (MCKO output for AK4682 : MCKO=256fs) (6) Please supply SIF signal from J1 (SIF1). (7) Please write register of AK4141 with control software. 41H : ASD bit = “0” → “1”. (Automatic system detection ON) <KM088102> 2007/11 -6- [AKD4141-A] (8) Please set toggle SW3 (CODEC) to “H”. (9) Please write register of AK4682 with control software. The following is register setting from the initial state of AK4682. 1. 02H : DIFA[1-0] bit “11” → “10” (Audio interface format : Left justified) (Note) In case of AK4141 evaluation using AK4682, it is necessary to correspond to audio interface format for AK4141 and AK4682. Audio interface format of AK4141’s initial state is Left justified. <KM088102> 2007/11 -7- [AKD4141-A] Setting of DIP SW (1). Setting of SW1 (AK4141) SW1 No. 1 Name ON (“H”) IIS 2 3 4 4M50 4M51 4M52 5 6M5 6 MSN 7 8 CAD0 CAD1 OFF (“L”) Default Audio Data Format Select Pin. ORed with ODIF bit, ORed with IDIF0 bit. “L”: 24 bit Left Justified if IDIF0 bit = “0” (default). “H”: 24/16 bit IIS. Decoder Standard Preference Control 0 for 4.5MHz carrier. 4M5 [2:0] pin “LLL”: PAL (Chroma Carrier) “LLH”: M-Korea “LHL”: EIAJ “LHH”: Reserved “HLL”: FM-Stereo Radio EU “HLH”: FM-Stereo Radio EU “HHL”: FM-Stereo Radio EU “HHH”: FM-Stereo Radio US This Pin is internally XORed with 4M5[2-0] bit (default = “011”). Decoder Standard Preference Control for 6.5MHz carrier. “L”: SECAM L NICAM “H”: D/K1, D/K2, D/K3 or D/K NICAM This Pin is internally XORed with 6M5 bit (default = “0”). Master Mode Select Pin. ORed with CKS [1:0] bits. “L”: Slave mode if CKS [2:0] bits = “000” (default). “H”: Master mode of MCLK=256fs if CKS2 bit = “0” (default). Chip Address 0 pin. Should match CAD0 bit in IIC first byte. Chip Address 1 pin. Should match CAD1 bit in IIC first byte. Table 4. SW1 Setting L L L L L L L L (2). Setting of SW4 (DIR: AK4114) SW4 Name ON (“H”) OFF (“L”) Default No. 1 DIF2 H AK4114 Output Audio Interface Format Setting 2 DIF1 L refer to Table 6. 3 DIF0 L 4 CM1 L AK4114 Clock Mode Setting Fixed to “L”. 5 CM0 L 6 OCKS1 H AK4114 Master Clock Frequency Setting refer to Table 7 7 OCKS0 L Table 5. SW4 Setting Mode 0 1 2 3 4 5 6 7 DIF2 pin L L L L H H H H DIF1 pin L L H H L L H H DIF0 LRCK BICK SDTO Format pin I/O L 16bit, Right justified H/L O 64fs H 18bit, Right justified H/L O 64fs L 20bit, Right justified H/L O 64fs H 24bit, Right justified H/L O 64fs L 24bit, Left justified H/L O 64fs H 24bit, I2S Compatible L/H O 64fs L 24bit, Left justified H/L I 64-128fs H 24bit, I2S Compatible L/H I 64-128fs Table 6. AK4114 Output Audio Interface Format Setting <KM088102> I/O O O O O O O I I (Default) 2007/11 -8- [AKD4141-A] OCKS1 OCKS0 MCKO1 fs (max) pin pin 0 L L 256fs 96 kHz 1 L H 256fs 96 kHz 2 H L 512fs 48 kHz 3 H H 128fs 192 kHz Table 7. AK4114 Master Clock Frequency Setting Mode (Default) (3). Setting of SW6 (DIT: AK4114) SW6 Name ON (“H”) OFF (“L”) Default No. 1 DIF2 H AK4114 Input Audio Interface Format Setting 2 DIF1 L refer to Table 9. 3 DIF0 L 4 CM1 AK4114 Clock Mode Setting Fixed to “L”. L 5 CM0 AK4114 Clock Mode Setting Fixed to “H”. H 6 OCKS1 L AK4114 Master Clock Frequency Setting refer to Table 10. 7 OCKS0 L Table 8. SW6 Setting Mode 0 1 2 3 4 5 6 7 DIF2 pin L L L L H H H H DIF1 pin L L H H L L H H DIF0 LRCK BICK DAUX Format pin I/O L 24bit, Left justified H/L O 64fs H 24bit, Left justified H/L O 64fs L 24bit, Left justified H/L O 64fs H 24bit, Left justified H/L O 64fs L 24bit, Left justified H/L O 64fs H 24bit, I2S Compatible L/H O 64fs L 24bit, Left justified H/L I 64-128fs H 24bit, I2S Compatible L/H I 64-128fs Table 9. AK4114 Input Audio Interface Format Setting I/O O O O O O O I I (Default) OCKS1 OCKS0 MCKO1 fs (max) pin pin 0 L L 256fs 96 kHz (Default) 1 L H 256fs 96 kHz 2 H L 512fs 48 kHz 3 H H 128fs 192 kHz Table 10. AK4114 Master Clock Frequency Setting Mode <KM088102> 2007/11 -9- [AKD4141-A] Serial Control GND GND GND 10 GND PORT2 uP I/F GND The AK4141 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT2 (CTRL) with PC by 10 wire flat cable packed with the AKD4141. 6 CCLK CSN CDTI CDTO 1 NC Red 5 Figure 2. Connect of 10 wire flat cable <KM088102> 2007/11 - 10 - [AKD4141-A] Control Software Manual Set-up of evaluation board and control software 1. Set up the AKD4141-A according to previous term. 2. Connect IBM-AT compatible PC with AKD4141-A by 10-line type flat cable (packed with AKD4141-A). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control software”. In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled “AK4141-A Evaluation Kit” into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of “akd4141.exe” and “akd4682 .exe” to set up the control program. 5. Then please evaluate according to the follows. Operation flow Keep the following flow. 1. Set up the control program according to explanation above. 2. Click “Port Reset” button. 3. Click “Write default” button Explanation of each buttons [Port Reset] : [Write default] : [All Write] : [All Read] : [Function1] : [Function2] : [Function3] : [Function4] : [Function5]: [SAVE] : [OPEN] : [Write] : [Read]: Set up the USB interface board (AKDUSBIF-A) . Initialize the register of AK4141. Write all registers that is currently displayed. Read all registers of the AK4141. Dialog to write data by keyboard operation. Dialog to write data by keyboard operation. The sequence of register setting can be set and executed. The sequence that is created on [Function3] can be assigned to buttons and executed. The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. Save the current register setting. Write the saved values to all register. Dialog to write data by mouse operation. Dialog to read data by mouse operation. Indication of data Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”. Blank is the part that is not defined in the datasheet. <KM088102> 2007/11 - 11 - [AKD4141-A] Explanation of each dialog 1. [Write Dialog] : Dialog to write data by mouse operation There are dialogs corresponding to each register. Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data becomes “H” or “1”. If not, “L” or “0”. If you want to write the input data to AK4141, click [OK] button. If not, click [Cancel] button. 2. [Function1 Dialog] : Dialog to write data by keyboard operation Address Box: Data Box: Input registers address in 2 figures of hexadecimal. Input registers data in 2 figures of hexadecimal. If you want to write the input data to AK4141, click [OK] button. If not, click [Cancel] button. 3. [Function2 Dialog] : Dialog to evaluate VOL Address Box: Input registers address in 2 figures of hexadecimal. Start Data Box: Input starts data in 2 figures of hexadecimal. End Data Box: Input end data in 2 figures of hexadecimal. Interval Box: Data is written to AK4141 by this interval. Step Box: Data changes by this step. Mode Select Box: If you check this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 If you do not check this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 If you want to write the input data to AK4141, click [OK] button. If not, click [Cancel] button. <KM088102> 2007/11 - 12 - [AKD4141-A] 4. [Save] and [Open] 4-1. [Save] Save the current register setting data. The extension of file name is “akr”. <Operation flow> (1) Click [Save] Button. (2) Set the file name and push [Save] Button. The extension of file name is “akr”. 4-2. [Open] The register setting data saved by [Save] is written to AK4141. The file type is the same as [Save]. <Operation flow> (1) Click [Open] Button. (2) Select the file (*.akr) and Click [Open] Button. <KM088102> 2007/11 - 13 - [AKD4141-A] 5. [Function3 Dialog] The sequence of register setting can be set and executed. (1) Click [F3] Button. (2) Set the control sequence. Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be paused. (3) Click [Start] button. Then this sequence is executed. The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step. This sequence can be saved and opened by [Save] and [Open] button on the Function3 window. The extension of file name is “aks”. Figure 3. Window of [F3] <KM088102> 2007/11 - 14 - [AKD4141-A] 6. [Function4 Dialog] The sequence that is created on [Function3] can be assigned to buttons and executed. When [F4] button is clicked, the window as shown in Figure 4. opens. Figure 4. [F4] window <KM088102> 2007/11 - 15 - [AKD4141-A] 6-1. [OPEN] buttons on left side and [START] buttons (1) Click [OPEN] button and select the sequence file (*.aks). The sequence file name is displayed as shown in Figure 5. Figure 5. [F4] window (2) (2) Click [START] button, then the sequence is executed. 6-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The sequence file names can assign be saved. The file name is *.ak4. [OPEN] : The sequence file names assign that are saved in *.ak4 are loaded. 6-3. Note (1) This function doesn't support the pause function of sequence function. (2) All files need to be in same folder used by [SAVE] and [OPEN] function on right side. (3) When the sequence is changed in [Function3], the file should be loaded again in order to reflect the change. <KM088102> 2007/11 - 16 - [AKD4141-A] 7. [Function5 Dialog] The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. When [F5] button is clicked, the following window as shown in Figure 6.opens. Figure 6. [F5] window 7-1. [OPEN] buttons on left side and [WRITE] button (1) Click [OPEN] button and select the register setting file (*.akr). The register setting file name is displayed as shown in Figure 7. (2) Click [WRITE] button, then the register setting is executed. <KM088102> 2007/11 - 17 - [AKD4141-A] Figure 7. [F5] windows(2) 7-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The register setting file names assign can be saved. The file name is *.ak5. [OPEN] : The register setting file names assign that are saved in *.ak5 are loaded. 7-3. Note (1) All files need to be in same folder used by [SAVE] and [OPEN] function on right side. (2) When the register setting is changed by [Save] Button in main window, the file should be loaded again in order to reflect the change. <KM088102> 2007/11 - 18 - [AKD4141-A] MEASUREMENT RESULTS [Measurement condition] • Measurement unit • fs • Power Supply • Temperature : Audio Precision, System Two Cascade ROHDE & SCHWARZ, TV TEST TRANSMITTER SFM : 48kHz : AVDD = TVDD = 3.3V, DVDD = 1.8V : Room [Measurement Results] FM Characteristics ( BG A2) Result (Lch / Rch) Unit S / (N+D) 0dB Input 63.2 / 68.4 dB S/N No Signal, A-weighting 69.5 / 73.4 dB Result (Lch / Rch) Unit NICAM Characteristics ( BG NICAM) S / (N+D) 0dB Input 67.4 / 67.3 dB Dynamic Range -60dB Input, A-weighting 79.0 / 78.8 dB Result (Mono) Unit AM Characteristics ( L ) S / (N+D) 0dB Input 40.1 dB S/N No Signal, A-weighting 72.2 dB <KM088102> 2007/11 - 19 - [AKD4141-A] [Plots] FM : BG A2 AKM BG A2 FFT (0dBr) +0 -20 -40 -60 d B r -80 -100 1 -120 -140 -160 -180 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 8. FFT (0dB Input) AKM BG A2 FFT (No Signal) +0 -20 -40 -60 d B r -80 -100 1 -120 -140 -160 -180 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 9. FFT (No Signal) <KM088102> 2007/11 - 20 - [AKD4141-A] NICAM : BG NICAM AKM NICAM FFT (0dBr) +0 -20 -40 -60 d B r -80 -100 1 -120 -140 -160 -180 20 50 100 200 500 1k 2k 5k 10k 20k 2k 5k 10k 20k Hz Figure 10. FFT (0dB Input) AKM NICAM FFT (-60dBr) +0 -20 -40 -60 d B r -80 -100 1 -120 -140 -160 -180 20 50 100 200 500 1k Hz Figure 11. FFT (-60dB Input) <KM088102> 2007/11 - 21 - [AKD4141-A] AM : L AKM AM Mono FFT (0dBr) +0 -20 -40 -60 d B r -80 -100 1 -120 -140 -160 -180 20 50 100 200 500 1k 2k 5k 10k 20k 2k 5k 10k 20k Hz Figure 12. FFT (0dB Input) AKM AM Mono FFT (No Signal) +0 -20 -40 -60 d B r -80 -100 1 -120 -140 -160 -180 20 50 100 200 500 1k Hz Figure 13. FFT (No Signal) <KM088102> 2007/11 - 22 - [AKD4141-A] Revision History Date (yy/mm/dd) 07/05/30 Manual Board Revision Revision KM088100 0 Reason Page Contents First Edition 07/06/26 KM088101 1 Change 07/11/13 KM088102 2 Change Change Addition 24 Circuit diagram was changed. C12: 0.1uF → 1uF Device revision was changed. Rev.A → Rev.B 24 Circuit diagram was changed. C14: 47nF → 4.7nF 19-22 Table data and plot data were added. IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification. <KM088102> 2007/11 - 23 - A SIF1 J1 BNC-R-PC B C C1 10n D E AK4141-AVDD1 R1 (Open) AK4141-AVDD2 AGND AGND CN1 49 50 51 52 53 54 55 56 57 58 59 A 64pin_4 60 C2 10n 61 J3 BNC-R-PC 62 SIF2 63 A AGND AGND 64 AGND R3 (Open) C3 AGND SW1 DSS108 9 8 7 6 5 4 3 2 1 IIS 4M50 4M51 4M52 6M5 MSN CAD0 CAD1 1 2 3 4 5 6 7 8 10u C6 C8 22p C7 0.1u VDD 10u X1 22p 2 16 15 14 13 12 11 10 9 C5 AGND + RP1 M9-1-473 47K AGNDC4 AGNDAGND + AGND C9 C10 1 HC-49/U 12.288MHz 0.1u C11 C12 0.1u 0.1u 0.1u 1u CN2 64pin_1 CN3 64pin_3 MODE-AK4141 3 VREFH 37 38 VREFL AVSS1 SIF2 39 40 41 SIF1 VCOM 42 43 AVSS1 44 46 47 45 XTI AVDD1 C13 XTO 2 AVSS2 47 B C14 1 FILT2 FILT1 36 2 IIS CAD1 35 46 OLRCK OLRCK ILRCK ILRCK OBICK OBICK IBICK IBICK 45 CAD1 JP4 HIF3G-50P-2.54DSA (3x1) LRCK5 5 R4 51 3 LRCK5 CAD0 34 44 CAD0 JP5 HIF3G-50P-2.54DSA (3x1) SCLK5 6 R5 51 4 SCLK5 MSN 33 43 MSN 7 R6 51 5 SDTI5 6M5 32 42 6M5 JP6 HIF3G-50P-2.54DSA (3x1) LRCK4 8 R8 51 6 LRCK4 INT 31 JP7 HIF3G-50P-2.54DSA (3x1) SCLK4 9 R9 51 7 SCLK4 SDTO1 30 R10 51 40 10 R11 51 8 SDTI4 SDTO2 29 R12 51 39 ILRCK OBICK IBICK 11 R13 51 9 SDTI3 SDTO3 28 R14 51 38 12 R15 51 10 SDTI2 LRCK 27 R16 JP9 HIF3G-50P-2.54DSA (3x2) SDTI5 DIR ADC GND SDTI AK4682-SDTOB U1B 3 74AC14 OLRCK C 4.7n 4 14 0.68u IIS AK4141 R7 4 R17 13 51 11 SDTI1 SCLK 26 4M50 MCKO 25 JP15 HIF3G-50P-2.54DSA (3x2) SDTI2 DIR ADC GND 51 37 R18 51 36 R19 51 35 TXOUT 34 24 SDA 4M52 23 22 TVDD 21 20 19 TVSS DVSS DVDD TXIN 18 17 MCKI PDN 16 13 SDTI3 SCL 15 15 12 14 14 4M50 4M51 JP13 HIF3G-50P-2.54DSA (3x2) SDTI3 DIR ADC GND 16 33 JP8 HIF3G-50P-2.54DSA (3x2) SDTO1 SDTO2 SDTO3 SDTO SDTO JP17 HIF3G-50P-2.54DSA (3x2) SDTI1 DIR ADC GND C15 AK4682-SDTIA1 SDTIA1 AK4682-SDTIA2 SDTO1 32 31 30 29 28 SDTO2 27 AGND 10u 25 24 23 C18 26 + 1 3 SDTO3 U3A 10k 470 74LS07 4 PORT2 A1-10PA-2.54DSA 6 7 8 9 10 C20 0.1u PDN-AK4141 DGND 5 4 3 2 1 up-I/F R28 U3B 10k 470 74LS07 3 R30 AK4141-TVDD C19 0.1u IN VCC 1 GND 4141TX(OPT) DGND 10k VDD R29 E AK4682-SDA (short) SDA(ACK) 51 Title Size DGND A2 Date: A 3 2 AK4682-SCL R26 4 VDD 100 R24 14 R27 SCL SDA SDA(ACK) 10k 2 7 1 PORT1 TOTX141 VDD 4M52 R23 7 3 74HC14 2 SW2 ATE1D-2M3 U4B 2 7 1 74HC14 R22 14 U4A H 7 14 2 1 R25 10k 14 R21 VDD L 10u AK4141-DVDD AK4141-TXIN DGND VDD E AGND AGND AGND JP2 HIF3G-50P-2.54DSA (2x1) D1 HSU119 JP14 HIF3G-50P-2.54DSA (3x2) SDTO1 SDTO2 SDTO3 64pin_2 4M51 DGND EXT-T IBICK AK4141-MCKO 0.1u C17 22 21 20 19 CN4 18 JP132 HIF3G-50P-2.54DSA (3x1) MCKI 17 14 EXT OBICK IBICK 7 74AC14 R2 51 2 ILRCK OBICK + 1 OLRCK ILRCK SDTIA2 C16 0.1u IMCLK EXT HIF3G-50P-2.54DSA (3x1) JP11 SCLK OLRCK D R20 100 SDTI1 DIR HIF3G-50P-2.54DSA (3x1) JP10 LRCK JP16 HIF3G-50P-2.54DSA (3x2) SDTO1 SDTO2 SDTO3 SDTI2 U1A VDD 41 SDTI4 J2 BNC-R-PC 1 C JP12 HIF3G-50P-2.54DSA (3x2)SDTI4 DIR ADC GND AGND LED1 SML-210LT 2 INT SDTI5 D 1k 7 B 48 U2 48 1 IIS 4M50 4M51 4M52 6M5 MSN CAD0 CAD1 AVDD2 DGND B C -24- D AKD4141-A Document Number Rev AK4141 Stereo Decoder Monday, June 18, 2007 E Sheet 1 2 of 5 B C D E AK4682-DVDD1 A A A + C21 10u 1 AK4141-MCKO LIN3 38 RIN3 37 39 NC 41 40 LIN4 RIN4 42 NC RIN5 LIN5 45 44 46 NC LIN6 RIN6 AGND DVSS1 RIN2 36 LIN2 35 AGND (short) 2 MCLKB 3 TVDD NC 34 4 LRCKB RIN1 33 (short) 5 BICKB LIN1 32 (short) 6 SDTOB AVDD1 31 AK4682-TVDD C23 10u + R32 AGND (short) R34 R35 C24 0.1u AGND R33 (Short) B J4 RIN1 C25 + R31 47 48 DVDD1 U5 AGND 43 AGND C22 0.1u 2 3 1 2.2u B MR-552LS AGND (short) 8 R38 (short) 9 AK4141-MCKO R39 (short) 10 AK4682-SDTIA1 R40 (short) 11 AK4682-SDTIA2 R42 (short) 12 30 VCOM3 29 VCOM36 28 MCLKA AVSS2 27 SDTIA1 AVDD2 26 SDTIA2 ROUT3 25 BICKA C29 0.1u C31 0.1u C30 10u C32 10u C33 0.1u C34 10u 2.2u AGND MR-552LS AGND AK4682-AVDD2 C35 22u LOUT3 PVSS 23 C39 22u + C44 22u Slave + + M/S CODEC ROUT1 MR-552LS AGND R47 220 (short) R51 10k AGND J8 AGND MR-552LS AGND R49 220 J9 ROUT2 2 3 1 + C47 4.7n AGND LOUT2 2 3 1 + C45 4.7n R48 10k C46 22u R50 J7 AGND C 2 3 1 + C42 4.7n AGND JP20 HIF3G-50P-2.54DSA (3x1) MR-552LS AGND R44 220 AGND LOUT1 AGND AK4682-DVDD2 Master AGND R46 10k DGND D J6 2 3 1 + C36 4.7n AGND + 2 PDN-CODEC R41 220 R43 10k C41 10u AGND AK4682-PVDD C43 0.1u SW3 ATE1D-2M3 + C40 10u 8 AK4682-SCL 9 74HC14 AK4682-SDA U4D 6 7 74HC14 1 3 H 14 U4C 5 L 7 14 1 D2 HSU119 C38 0.1u AK4682-DVDD2 2 R45 10k C37 0.1u 2 3 1 AGND 24 PVDD 22 LOUT2 ROUT2 21 20 MSB 19 ROUT1 LOUT1 17 18 DVSS2 16 SCL DVDD2 15 VDD 14 13 SDA C J5 LIN1 C28 + R36 (Short) + OBICK LRCKA AVSS1 + R37 OLRCK AK4682 PDN +C27 10u + 7 AK4682-AVDD1 C26 0.1u + AK4682-SDTOB D MR-552LS AGND AGND E E Title Size A2 Date: A B C -25- D AKD4141-A Document Number Rev AK4682 CODEC Tuesday, November 13, 2007 Sheet E 2 2 of 5 B C 9V-->5V 5V-->3.3V IN 3 1 AGND AGND + C51 47u C50 0.1u 2 C49 0.1u OUT AGND AGND IN C52 + C53 47u 0.1u AGND AGND AGND L1 OUT T3 LT1963AEST-1.8 2 1 C54 0.1u AGND AGND + C55 + C56 47u 47u AGND C57 0.1u AGND AGND R52 AK4682-PVDD REG (Short) OUT 3 A TM TVDD JP21 (3X1) TVDD AGND 47u AGND R53 REG AK4682-TVDD (Short) TM DVDD JP22 (3X1) DVDD R54 AK4141-DVDD (Short) R56 R55 AK4141-TVDD L2 AK4682-AVDD2 (Short) B + C59 C58 0.1u AGND AK4682-AVDD1 (short) IN 2 C48 + 47u E 3.3V-->1.8V T2 TA48M033F 3 1 A GND T1 NJM78M05FA GND 9V D GND A (short) C60 + 47u R57 L3 (Short) (short) C61 + 47u B AK4682-DVDD1 (Short) AGND AGND R58 REG AK4682-DVDD2 (Short) TM AVDD1 JP23 (3X1) AVDD1 R59 AK4141-AVDD1 (Short) L4 C62 + 47u 1 AGND DGND T-45(BK) T-45(BK) 1 DVDD T-45(R) 1 Logic T-45(R) 1 AVDD2 T-45(R) 1 AVDD1 T-45(R) 1 TVDD T-45(R) 1 1 9V T-45(R) AGND C 9V TVDD AVDD1 AVDD2 Logic DVDD AGND (short) C REG DGND TM AVDD2 JP24 (3X1) AVDD2 R60 AK4141-AVDD2 (Short) L5 (short) C67 + 47u AGND REG 74AC14 14 7 14 D C107 0.1u C108 0.1u C109 0.1u DGND DGND 8 DGND 14 11 74LS07 U3F 10 13 74LS07 DGND JP25 (2x1) GND E DGND 12 AGND Title A3 DGND Date: A B 0.1u for for for for for DGND 74HC14 74HC14 74AC14 74AC14 74LS07 (Rx) (Tx) Size DGND C110 (short) C68 + 47u 7 7 14 U3E 12 VDD (Short) C104 0.1u L6 7 9 74LS07 12 7 13 10 13 74AC14 14 U1F U8F 10 7 11 E 11 74AC14 U3D R141 14 8 6 (3X1) 7 U1E 74AC14 14 14 7 9 74AC14 5 74LS07 7 12 U8E 8 TM Logic U3C 14 13 74HC14 9 74AC14 7 12 U1D 6 14 U6F 7 13 74HC14 5 74AC14 14 14 U4F 10 VDD U8D 7 11 74HC14 VDD U1C 7 10 7 11 74HC14 U6E 7 U4E VDD 14 VDD 14 VDD 14 D JP26 Logic C -26- D AKD4141-A Document Number Rev 2 POWER SUPPLY Monday, June 18, 2007 Sheet E 3 of 5 A B R62 OPT PORT3 TORX141 C69 0.1u DGND DGND R64 DGND A 470 OPT COAX J10 BNC-R-PC AK4141-TXIN C70 JP28 HIF3G-50P-2.54DSA (3x1) RX DGND 0.1u VDD C71 10u C72 0.1u DGND 14 13 12 11 10 9 8 R66 18k 1 38 37 INT0 36 1 74AC14 2 NC OCKS0 35 3 DIF0 OCKS1 34 4 TEST2 CM1 33 5 DIF1 CM0 32 6 NC LED2 SML-210LT 14 AVSS INT1 42 41 43 NC RX0 45 46 44 RX1 NC R U8A IPS0 2 R67 1k 2 1 VDD B INT0 7 INPUT-AK4114 RX2 48 47 U7 8 7 6 5 4 3 2 1 B C73 0.47u VDD TEST1 RP2 M8-1-473 1 2 3 4 5 6 7 RX3 DIF2 DIF1 DIF0 CM1 CM0 OCKS1 OCKS0 SW4 DSS107 + DGND + R65 75 AVDD 3 2 1 E JP27 HIF3G-50P-2.54DSA (3x1) TXIN 40 RX(COAX) VCC GND OUT GND 39 RX(OPT) R63 (Open) VCOM A D 470 VDD L7 47u C 47K DGND U6A 1 3 H U6B 2 3 74HC14 8 PDN 31 DIF2 XTI 30 IPS1 XTO 29 AK4114 DGND 4 C74 0.1u 9 P/SN DAUX 28 10 XTL0 MCKO2 27 11 XTL1 BICK 26 JP29 HIF3G-50P-2.54DSA (2x1) IBICK1 SDTO 25 JP30 HIF3G-50P-2.54DSA (2x1) SDTI VDD 2 SW5 ATE1D-2M3 C PDN-DIR LRCK DGND 24 DVSS MCKO1 23 22 VOUT DVDD C76 0.1u JP31 HIF3G-50P-2.54DSA (2x1) ILRCK JP32 HIF3G-50P-2.54DSA (2x1) IMCLK + C78 10u + C77 10u 21 20 COUT UOUT 19 18 TX1 BOUT 17 C75 0.1u 16 14 13 DGND TX0 VIN TVDD 12 15 DGND DVSS C 74HC14 7 1 L 7 14 R68 10k 7 D3 HSU119 14 1 2 VDD VDD VDD DGND DGND D D IMCLK THR JP33 HIF3G-50P-2.54DSA (3x1) U8B ILRCK 4 51 R70 51 R71 51 R72 51 INV 7 3 74AC14 IBICK2 14 IBICK R69 SDTI R73 (Open) R74 (Open) R75 (Open) R76 (Open) E PORT4 A1-10PA-2.54DSA DGND 2 IMCLK 1 3 4 SDTI5 IBICK 6 SDTI4 ILRCK 5 7 8 SDTI3 SDTI SDTI1 9 10 SDTI2 SDTI1 INPUT SDTI2 SDTI3 E SDTI4 SDTI5 DGND Title Size A2 Date: A B C -27- D AKD4141-A Document Number Rev S/PDIF INPUT Monday, June 18, 2007 E Sheet 2 4 of 5 A B C D E PORT5 TOTX141 IN VCC 3 2 GND 1 TX(OPT) VDD C79 0.1u OPT COAX DGND JP34 HIF3G-50P-2.54DSA (3x1) TX DGND A R77 240 C80 A VDD + J11 T4 BNC-R-PC DA-02F TX(COAX) 0.1u C81 10u R78 150 C82 0.1u 1:1 RP3 M8-1-473 1 B 37 INT1 AVDD 39 R 41 40 VCOM AVSS RX0 42 43 NC RX1 45 44 46 RX2 INT0 36 NC OCKS0 35 DIF0 OCKS1 34 CM1 33 CM0 32 IPS0 2 3 4 TEST2 5 DIF1 6 NC 7 DIF2 OUTPUT-AK4114 8 7 6 5 4 3 2 1 NC VDD TEST1 U9 14 13 12 11 10 9 8 48 SW6 DSS107 1 2 3 4 5 6 7 RX3 DIF2 DIF1 DIF0 CM1 CM0 OCKS1 OCKS0 47 DGND 38 C83 0.47u + DGND B 47K DGND AK4114 PDN 31 XTI 30 R79 0 AK4141-MCKO 1 3 14 9 74HC14 VDD XTO 9 P/SN DAUX 28 10 XTL0 MCKO2 27 11 XTL1 BICK 26 12 VIN SDTO 25 SDTO 8 C84 0.1u JP36 HIF3G-50P-2.54DSA (2x1) 2 SW7 ATE1D-2M3 74HC14 U6D 6 7 H IPS1 29 JP35 U6C 5 L 8 R80 10k 7 D4 HSU119 14 1 2 VDD OBICK1 C88 10u + LRCK MCKO1 JP37 HIF3G-50P-2.54DSA (2x1) IBICK 24 23 C86 0.1u C87 10u 22 DVSS DVDD 21 VOUT UOUT 20 19 BOUT COUT 18 17 TX0 TX1 16 C85 0.1u 15 TVDD 13 DGND 14 DGND + C DVSS PDN-DIT C IBICK JP38 HIF3G-50P-2.54DSA (2x1) OLRCK JP39 HIF3G-50P-2.54DSA (2x1) ILRCK VDD DGND VDD ILRCK DGND D D AK4141-MCKO OBICK U8C 14 THR JP41 HIF3G-50P-2.54DSA (3x1) 74AC14 OLRCK 6 INV 51 R82 51 OBICK2 7 5 R81 SDTO R85 (Open) R86 (Open) PORT6 A1-10PA-2.54DSA DGND 2 MCKO 1 OBICK 3 4 6 OLRCK 5 7 8 SDTO3 SDTO SDTO1 9 10 SDTO2 R83 51 R84 51 SDTO1 R87 (Open) OUTPUT SDTO2 SDTO3 DGND E E Title Size A2 Date: A B C -28- D AKD4141-A Document Number Rev S/PDIF OUTPUT Tuesday, November 13, 2007 E Sheet 5 2 of 5 -29- -30- -31- -32-