AKM AK4141

[AK4141]
= Preliminary =
AK4141
NICAM/A2/EIA-J Digital Stereo Decoder
GENERAL DESCRIPTION
The AK4141 is a NICAM/A2/EIA-J stereo decoder, which is optimized for Digital TV application. The
AK4141 achieves no alignment, few external components and high audio performance by digital stereo
decoding architecture. The AK4141 integrates a stereo sample rate converter (SRC) for asynchronous
digital audio sources such as HDMI, digital tuner, digital switches and sound processing functions such as
5-band equalizers. The AK4141 supports major audio data formats (MSB/LSB justified, I2S and TDM) to
interface with DSP, ADC, DAC. Therefore, the AK4141 is suitable for the AV systems such as Digital TV
and DVR.
FEATURES
1. Stereo Decoding
† Capable of receiving Sound Intermediate Frequency (SIF) with Selector
and FM Demodulation
† Automatic Gain Control (AGC: 100mVpp ~ 1Vpp) for SIF input
† Alignment Free Digital Stereo Decoding
EIA-J
NICAM: B/G, L, I, D/K with FM/AM Mono
A2: B/G, D/K1, D/K2, D/K3, M/N
† Automatic/Manual Stereo Decoding Standard Selection
† Automatic/Manual Audio Mode (Stereo/MONO/two sounds) Selection
† Signal Quality Detection for Auto Selection Mode
† High FM Deviation Option (max: 540kHz)
† I2S sampling rate (fs): 32k/44.1k/48kHz
2. Audio Processing (Two Stereos)
† Automatic Level Control (ALC)
† Balance
† 5-band Equalizer
† Stereo Separation Emphasis
† Digital Volume Control with Soft Mute (+12dB~-115dB, 0.5dB/step)
† Audio Data Interface:
I2S input x 5 (2 inputs: SRC available)
I2S output x 3
Master/Slave Mode
Audio Format: 24bit Left justified /Right justified / I2S or TDM
3. Asynchronous Sample Rate Converter (SRC)
† Input Sample Rate: 8k~192kHz
† fso/fsi: 1/6~6
4. Digital Audio Interface Transmitter (DIT) with Through Mode
5. Integrated X’tal Oscillator
6. Master Clock: 256fs/384fs/512fs/768fs/1024fs
7. I2C-bus Control Interface
8. Power Supply: 1.8V±0.1V, 3.3V±0.3V
9. Ta: -20 ~ 85°C
10. Package: 48pin LQFP
Rev. 0.3-PB
2008/01
-1-
[AK4141]
VCOM LFLT1 LFLT2 AVDD2 GND5 AVDD1 GND3 GND4 LRCK SCLK
DVDD
GND1
TVDD GND2
VREFH
VREFL
AGC
SIF1
ADC
(SIF)
SIF2
FM Demod &
Stereo Decode
EIAJ
NICAM
A2
SDTI1
SDTI2
SDTI3
DIT
Prescale
1/2/3/4
LRCK4
SCLK4
SDTI4
LRCK5
SCLK5
SDTI5
TXOUT
Decoder
Prescale
TXIN
ALC, Vol1
Balance1
Bass/Tre1
3D
Switch
Matrix
SDTO1
ALC, Vol2
Balance2
Bass/Tre2
3D
SDTO2
SRC
SRC
Prescale
X’tal Osc PLL
Clock Gen
MCLKI XTI XTO MCKO
SDTO3
Control
Register
CAD0 CAD1 SCL SDA INT
Rev. 0.3-PB
PDN
6M5 4M50 4M51 4M52 MSN
IIS
2008/01
-2-
[AK4141]
■ Ordering Guide
AK4141EQ
AKD4141
-20 ∼ +85°C 48pin LQFP (0.5mm pitch)
Evaluation Board for AK4141
LFLT1
CAD1
CAD0
MSN
A6M5
INT
SDTO1
SDTO2
SDTO3
LRCK
SCLK
MCLKO
36
35
34
33
32
31
30
29
28
27
26
25
■ Pin Layout
VREFH
37
24
TXOUT
VREFL
38
23
A4M52
GND3
39
22
SDA
SIF2
40
21
TVDD
VCOM
41
20
GND2
SIF1
42
19
GND1
AVDD1
43
18
DVDD
17
TXIN
AK4141EQ
Top View
9
10
11
12
SDTI2
SDTI1
A4M50
A4M51
SDTI3
13
8
48
SDTI4
AVDD2
7
SCL
SCLK4
14
6
47
LRCK4
GND5
5
PDN
SDTI5
15
4
46
SCLK5
XTO
3
MCLKI
LRCK5
16
2
45
IIS
XTI
1
44
LFLT2
GND4
Rev. 0.3-PB
2008/01
-3-
[AK4141]
PIN/FUNCTION
No.
Pin Name
I/O
1
FILT2
O
2
IIS
I
3
4
5
6
7
LRCK5
SCLK5
SDTI5
LRCK4
SCLK4
I
I
I
I
I
8
SDTI4
I
9
10
11
SDTI3
SDTI2
SDTI1
I
I
I
12
A4M50
I
13
A4M51
I
14
SCL
I
15
PDN
I
16
MCKI
I
17
TXIN
I
18
19
20
21
22
DVDD
GND1
GND2
TVDD
SDA
I/O
23
A4M52
I
24
25
TXOUT
MCKO
O
O
26
SCLK
I/O
27
LRCK
I/O
28
SDTO3
O
29
SDTO2
O
30
SDTO1
O
Function
PLL Loop Filter 2 Pin
A 0.68μF capacitor should be connected to GND5 externally.
Hi-Z when PDN Pin = “L”.
Audio Data Format Select Pin. ORed with ODIF bit, ORed with IDIF0 bit.
“L”: 24bit Left justified if IDIF0 bit = “0”(default)
“H”: 24/16 bit IIS
Input Channel Clock 5 Pin
Audio Serial Data Clock 5 Pin
Audio Serial Data Input 5 Pin
Input Channel Clock 4 Pin
Audio Serial Data Clock 4 Pin
Audio Serial Data Input 4 Pin
Should be synchronized to LRCK and SCLK when SRC is not used.
Audio Serial Data Input 3 Pin
Audio Serial Data Input 2 Pin
Audio Serial Data Input 1 Pin
Decoder Standard Preference Control 0 Pin for 4.5MHz Carrier
This pin is internally XORed with A4M50 bit (default = “1”).
Decoder Standard Preference Control 1 Pin for 4.5MHz Carrier
This pin is internally XORed with A4M51 bit (default = “1”).
Control Data Clock Pin for I2C bus
Power-Down Mode & Reset Pin
When “L”, the AK4141 is powered-down, all registers are reset. And then all
digital output pins go “L”. The AK4141 must be reset once upon power-up.
Master Clock Input Pin
S/PDIF Input Pin
For through output. No Input Amplifier integrated.
Digital Power Supply Pin, 1.7V~1.9V
Ground Pin, 0V
Ground Pin, 0V
I/O Buffer Power Supply Pin, 1.7V~3.6V
Control Data Pin for I2C bus
Decoder Standard Preference Control 2 Pin for 4.5MHz Carrier
This pin is internally ORed with A4M52 bit (default = “0”).
S/PDIF Output pin. Outputs “L” when PDN Pin = “L”.
Master Clock Output Pin. Outputs “L” when PDN Pin = “L”.
Audio Serial Data Clock Pin.
Outputs “L” when PDN Pin = “L” and MSN Pin = “H”.
Hi-Z when PDN Pin = “L” and MSN Pin = “L”.
Input Channel Clock Pin
Outputs “L” when PDN Pin = “L” and MSN Pin = “H”.
Hi-Z when PDN Pin = “L” and MSN Pin = “L”.
Audio Serial Data Output 3 Pin
Outputs “L” when PDN Pin = “L”.
Audio Serial Data Output 2 Pin
Outputs “L” when PDN Pin = “L”.
Audio Serial Data Output 1 Pin
Outputs “L” when PDN Pin = “L”.
Rev. 0.3-PB
2008/01
-4-
[AK4141]
PIN/FUNCTION
Interrupt Pin
Outputs “L” when PDN Pin = “L”.
Decoder Standard Preference Control for 6.5MHz carrier.
“L”: SECAM L NICAM
32
A6M5
I
“H”: D/K1, D/K2, D/K3 or D/K NICAM
This Pin is internally ORed with A6M5 bit (default = “0”).
Master Mode Select Pin
33
MSN
I
“L”: Slave mode if CKS[2:0] bits = “000”(default)
“H”: Master mode of MCLK = 256fs if CKS2 bit = “0”(default)
Chip Address 0 pin
34
CAD0
I
Should match CAD0 bit in I2C first byte.
Chip Address 1 pin
35
CAD1
I
Should match CAD1 bit in I2C first byte.
PLL Loop Filter 1 Pin
36
FILT1
O
A 4.7nF capacitor should be connected to GND3 externally.
Hi-Z when PDN Pin = “L”.
ADC Voltage Reference High Pin
37
VREFH
O
A 0.1μF capacitor should be connected to GND3, and another 0.1μF capacitor
should be connected to VREFL Pin externally. Hi-Z when PDN Pin = “L”.
ADC Voltage Reference Low Pin
38
VREFL
O
A 0.1μF capacitor should be connected to GND3 externally.
Hi-Z when PDN Pin = “L”.
39
GND3
Ground Pin, 0V
40
SIF2
I
Sound Intermediate Frequency(SIF) Input 2 Pin
ADC Common Voltage Output Pin.
41
VCOM
O
A 1μF capacitor should be connected to GND3 externally. Hi-Z when PDN Pin =
“L”.
42
SIF1
I
Sound Intermediate Frequency(SIF) Input 1 Pin
43
AVDD1
Analog Power Supply Pin, 3.0V~3.6V
44
GND4
Ground Pin, 0V
45
XTI
I
X'tal Input Pin
X'tal Output Pin.
46
XTO
O
Outputs “L” when PDN pin = “L”.
47
GND5
Ground Pin, 0V
48
AVDD2
Analog Power Supply Pin, 3.0V~3.6V
Note: All digital input pins should not be left floating.
31
INT
O
Rev. 0.3-PB
2008/01
-5-
[AK4141]
■ Handling of Unused Pin
The unused I/O pins should be processed appropriately as below.
Classification
Pin Name
Setting
These pins should be connected to GND
through 10nF capacitor.
These pins should be open.
Analog
SIF1, SIF2
Digital
TXOUT, MCLKO, SDTO1, SDTO2, SDTO3, INT,
LRCK(master mode), SCLK(master mode)
LRCK5, SCLK5, SDTI5, LRCK4, SCLK4, SDTI4,
These pins should be connected to GND.
LRCK(slave mode), SCLK(slave mode), SDTI3,
SDTI2, SDTI1, A4M50, A4M51, A4M52, A6M5,
SCL, MCLKI, TXIN, SDA, IIS, MSN, CAD1, CAD0
ABSOLUTE MAXIMUM RATINGS
(GND1=GND2=GND3=GND4=GND5=0V; Note 1)
Parameter
Symbol
Power Supplies
Analog
AVDD
Digital
DVDD
Digital I/O
TVDD
Input Current, Any Pin Except Supply
IIN
Analog Input Voltage (SIF1, SIF2 pin)
VINA
Digital Input Voltage (Note 2)
VIND
Ambient Temperature (powered applied)
Ta
Storage Temperature
Tstg
min
-0.3
-0.3
-0.3
−0.3
−0.3
−20
−65
max
4.3
2.4
4.3
±10
AVDD+0.3
TVDD+0.3
85
150
Units
V
V
V
mA
V
V
°C
°C
Note 1. All voltages with respect to ground.
Note 2. LRCK5, SCLK5, SDTI5, LRCK4, SCLK4, SDTI4, LRCK(slave mode), SCLK(slave mode), SDTI3, SDTI2,
SDTI1, A4M50, A4M51, A4M52, A6M5, SCL, MCLKI, TXIN, SDA, IIS, MSN, CAD1 and CAD0 pin.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(GND1=GND2=GND3=GND4=GND5=0V; Note 1)
Parameter
Symbol
min
typ
Power Supplies
AVDD
AVDD
3.0
3.3
DVDD
DVDD
1.7
1.8
TVDD
TVDD
DVDD
3.3
max
3.6
1.9
3.6
Units
V
V
V
WARNING: AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet.
Rev. 0.3-PB
2008/01
-6-
[AK4141]
AUDIO CHARACTERISTICS
(Ta=25°C; AVDD=3.3V, DVDD=1.8V, TVDD=3.3V; GND1=GND2=GND3=GND4=GND5=0V; fs=48kHz;
SCLK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement frequency=50Hz ∼ 13kHz; unless otherwise specified)
SIF & Demodulator Parameter
min
typ
max
Units
SIF Input Impedance
GSEL bit = 0
4.05
4.50
kohm
GSEL bit = 1
5.09
5.66
kohm
SIF Separation (Note 3)
40
dB
AGC step width
0.64
dB
Input Voltage
1 or 2 FM Carriers
GSEL bit = “0”
0.1
1.4
Vpp
GSEL bit = “1”
0.1
1.0
Vpp
1 FM and 1 NICAM Carrier
GSEL bit = “0”
0.1
1.4
Vpp
GSEL bit = “1”
0.1
1.0
Vpp
1 AM and 1 NICAM Carrier
GSEL bit = “0”
0.1
0.8
Vpp
GSEL bit = “1”
0.1
0.8
Vpp
1 NICAM Only
GSEL bit = “0”
0.05
1.0
Vpp
GSEL bit = “1”
0.05
1.0
Vpp
Max FM-deviation (approx.)
Normal
+/-180
kHz
High deviation
+/-360
kHz
Very High Deviation
+/-540
kHz
NICAM Characteristics
min
typ
max
Units
Output level (1kHz, 0dBr)
-1.5
+1.5
dB
S/N
74
80
dB
THD+N
0.05
0.15
%
NICAM Bit Error Rate (FM+ NICAM, normal condition)
1
10-7
Frequency response (20 ~ 15kHz, -12dB, dual)
-1
+1
dB
NICAM Crosstalk attenuation (dual)
80
dB
Channel separation (stereo)
80
dB
FM Characteristics (Note 4)
min
typ
max
Units
Output level (1kHz, 0dBr)
-1.5
+1.5
dB
S/N
67
73
dB
THD+N
0.1
0.3
%
Frequency response (20 ~ 12kHz, -12dB, dual)
-1
+1
dB
FM Crosstalk attenuation (dual)
75
85
dB
Channel separation (stereo)
30
40
dB
AM Characteristics
min
typ
max
Units
S/N
47
62
dB
THD+N
1.2
3
%
Frequency response (20 ~ 12kHz, -12dB, dual)
-2.5
+1
dB
Note 3. Selected SIF pin is connected to GND through 10nF capacitor.
Note 4. 1 FM-Carrier, 5.5MHz.
Rev. 0.3-PB
2008/01
-7-
[AK4141]
AUDIO CHARACTERISTICS (Continued)
(Ta=25°C; AVDD=3.3V, DVDD=1.8V, TVDD=3.3V; GND1=GND2=GND3=GND4=GND5=0V; fs=48kHz;
SCLK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement frequency=50Hz ∼ 13kHz; unless otherwise specified)
EIAJ Characteristics
min
typ
max
Units
S/N
Stereo
54
60
dB
Sub
54
60
dB
THD+N (1kHz L or R or Sub 100%)
Stereo
0.3
0.9
%
Sub
0.3
0.9
%
Frequency response
Stereo (20 ~ 12kHz, 100%EIM)
-1
+1
dB
Sub (20 ~ 12kHz, 100%EIM)
-1
+1
dB
Channel separation (stereo)
30
40
dB
SRC CHARACTERISTICS
(Ta=25°C; AVDD=3.3V, DVDD=1.8V, TVDD=3.3V; GND1=GND2=GND3=GND4=GND5=0V; fs=48kHz;
SCLK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement frequency=20Hz ~ FSO/2; unless otherwise specified)
Parameter
Symbol
min
typ
max
Units
SRC Characteristics:
Resolution
20
Bits
Input Sample Rate
FSI
8
216
kHz
Output Sample Rate
FSO
32
48
kHz
THD+N
(Input = 1kHz, 0dBFS, Note 5)
FSO/FSI = 48kHz/8kHz
-100
dB
FSO/FSI = 48kHz/32kHz
-100
dB
FSO/FSI = 48kHz/192kHz
-100
dB
Worst Case (FSO/FSI = 32kHz/176.4kHz)
TBD
dB
Dynamic Range (Input = 1kHz, −60dBFS, A-weighted, Note 5)
FSO/FSI = 48kHz/8kHz
103
dB
FSO/FSI = 48kHz/32kHz
103
dB
FSO/FSI = 48kHz/192kHz
103
dB
Worst Case (FSO/FSI = 48kHz/32kHz)
TBD
dB
Ratio between Input and Output Sample Rate
FSO/FSI
1/6
6
Note 5. Measured by Audio Precision System Two Cascade.
Power Supplies
Parameter
Power Supply Current
Normal Operation (PDN pin = “H”)
TVDD
AVDD1+AVDD2
DVDD
Power-Down Mode (PDN pin = “L”; Note: 1)
TVDD
AVDD1+AVDD2
DVDD
min
typ
max
Units
5
20
70
TBD
TBD
TBD
mA
mA
mA
10
10
10
100
100
100
μA
μA
μA
Note: 1. All digital inputs including clock pins are held at DVDD or GND.
Rev. 0.3-PB
2008/01
-8-
[AK4141]
SRC FILTER CHARACTERISTICS
(Ta=25°C; AVDD=3.0 ∼ 3.6V, DVDD=1.7V∼ 1.9V, TVDD=1.7 ∼ 3.6V; GND1=GND2=GND3=GND4=GND5=0V)
Parameter
Symbol
min
typ
max
Units
Digital Filter
0.4583FSI
Passband −0.01dB
0.985 ≤ FSO/FSI ≤ 6.000
PB
0
kHz
0.4167FSI
0.905 ≤ FSO/FSI < 0.985
PB
0
kHz
0.3195FSI
0.714 ≤ FSO/FSI < 0.905
PB
0
kHz
0.2852FSI
0.656 ≤ FSO/FSI < 0.714
PB
0
kHz
0.2182FSI
0.536 ≤ FSO/FSI < 0.656
PB
0
kHz
0.2177FSI
0.492 ≤ FSO/FSI < 0.536
PB
0
kHz
0.1948FSI
0.452 ≤ FSO/FSI < 0.492
PB
0
kHz
0.1458FSI
0.357 ≤ FSO/FSI < 0.452
PB
0
kHz
0.1302FSI
0.324 ≤ FSO/FSI < 0.357
PB
0
kHz
0.0917FSI
0.246 ≤ FSO/FSI < 0.324
PB
0
kHz
0.0826FSI
0.226 ≤ FSO/FSI < 0.246
PB
0
kHz
0.0583FSI
0.1667 ≤ FSO/FSI < 0.226
PB
0
kHz
Stopband
0.985 ≤ FSO/FSI ≤ 6.000
SB
0.5417FSI
kHz
0.905 ≤ FSO/FSI < 0.985
SB
0.5021FSI
kHz
0.714 ≤ FSO/FSI < 0.905
SB
0.3965FSI
kHz
0.656 ≤ FSO/FSI < 0.714
SB
0.3643FSI
kHz
0.536 ≤ FSO/FSI < 0.656
SB
0.2974FSI
kHz
0.492 ≤ FSO/FSI < 0.536
SB
0.2813FSI
kHz
0.452 ≤ FSO/FSI < 0.492
SB
0.2604FSI
kHz
0.357 ≤ FSO/FSI < 0.452
SB
0.2116FSI
kHz
0.324 ≤ FSO/FSI < 0.357
SB
0.1969FSI
kHz
0.246 ≤ FSO/FSI < 0.324
SB
0.1573FSI
kHz
0.226 ≤ FSO/FSI < 0.246
SB
0.1471FSI
kHz
0.1667 ≤ FSO/FSI < 0.226
SB
0.1020FSI
kHz
Passband Ripple
PR
±0.01
dB
Stopband
0.985 ≤ FSO/FSI ≤ 6.000
SA
102.2
dB
Attenuation
0.905 ≤ FSO/FSI < 0.985
SA
100.4
dB
0.714 ≤ FSO/FSI < 0.905
SA
99.0
dB
0.656 ≤ FSO/FSI < 0.714
SA
101.6
dB
0.536 ≤ FSO/FSI < 0.656
SA
99.5
dB
0.492 ≤ FSO/FSI < 0.536
SA
95.2
dB
0.452 ≤ FSO/FSI < 0.492
SA
96.6
dB
0.357 ≤ FSO/FSI < 0.452
SA
97.0
dB
0.324 ≤ FSO/FSI < 0.357
SA
94.4
dB
0.246 ≤ FSO/FSI < 0.324
SA
95.8
dB
0.226 ≤ FSO/FSI < 0.246
SA
95.0
dB
0.1667 ≤ FSO/FSI < 0.226
SA
73.7
dB
Group Delay
(Note 6)
GD
56
1/fs
Note 6. This value is the time from the rising edge of LRCK after data is input to rising edge of LRCK after data is output,
when LRCK for Output data corresponds with LRCK for Input.
Rev. 0.3-PB
2008/01
-9-
[AK4141]
DC CHARACTERISTICS
(Ta=25°C; AVDD=3.0 ∼ 3.6V, DVDD=1.7V∼ 1.9V, TVDD=1.7 ∼ 3.6V; GND1=GND2=GND3=GND4=GND5=0V)
Parameter
Symbol
min
typ
max
Units
High-Level Input Voltage
TVDD < 2.7V
VIH
80%TVDD
V
VIH
70%TVDD
V
TVDD ≥ 2.7V
Low-Level Input Voltage
VIL
20%TVDD
V
TVDD < 2.7V
VIL
30%TVDD
V
TVDD ≥ 2.7V
High-Level Output Voltage ( Iout=-400μA)
VOH
TVDD-0.4
V
Low-Level Output Voltage
VOL
0.4
V
(Iout= -400μA(except SDA pin), 3mA(SDA pin))
Input Leakage Current
±10
μA
Iin
SWITCHING CHARACTERISTICS
(Ta=-20∼ 85°C; AVDD= 3.0~3.6V, DVDD=1.7~1.9V TVDD=1.7~3.6V; GND1=GND2=GND3=GND4=GND5=0V;
CL=20pF, Cb=400pF(SDA pin))
Parameter
Symbol
min
typ
max
Units
Crystal Resonator Frequency
fXTAL
256fs
fs=32kHz
8.192
MHz
fs=44.1kHz
11.2896
MHz
fs=48kHz
12.288
MHz
Master Clock Timing
Master Clock
128fs:
fCLK
4.096
6.144
MHz
Pulse Width Low
tCLKL
65
ns
Pulse Width High
tCLKH
65
ns
192fs:
fCLK
6.144
9.216
MHz
Pulse Width Low
tCLKL
43
ns
Pulse Width High
tCLKH
43
ns
256fs:
fCLK
8.192
12.288
MHz
Pulse Width Low
tCLKL
27
ns
Pulse Width High
tCLKH
27
ns
384fs:
fCLK
12.288
18.432
MHz
Pulse Width Low
tCLKL
20
ns
Pulse Width High
tCLKH
20
ns
512fs:
fCLK
16.384
24.576
MHz
Pulse Width Low
tCLKL
16
ns
Pulse Width High
tCLKH
16
ns
768fs:
fCLK
24.576
36.864
MHz
Pulse Width Low
tCLKL
11
ns
Pulse Width High
tCLKH
11
ns
1024fs:
fCLK
32.768
49.152
MHz
Pulse Width Low
tCLKL
8
ns
Pulse Width High
tCLKH
8
ns
Rev. 0.3-PB
2008/01
- 10 -
[AK4141]
SWITCHING CHARACTERISTICS (Continued)
(Ta=-20∼ 85°C; AVDD= 3.0~3.6V, DVDD=1.7~1.9V TVDD=1.7~3.6V; GND1=GND2=GND3=GND4=GND5=0V;
CL=20pF, Cb=400pF(SDA pin))
Parameter (Note 8)
Symbol
min
typ
max
Units
LRCK Timing (Slave Mode)
Normal mode (TDM=“0”)
LRCK Frequency
fs
32
48
kHz
Duty Cycle
Duty
45
55
%
TDM256 mode (TDM=“1”)
LRCK Frequency
fs
32
48
kHz
“H” time
tLRH
1/256fs
ns
“L” time
tLRL
1/256fs
ns
SRC Input
LRCK Frequency
fs
8
192
KHz
Duty Cycle
Duty
45
55
%
LRCK Timing (Master Mode)
Normal mode (TDM=“0”)
LRCK Frequency
fs
32
48
kHz
Duty Cycle
Duty
50
%
TDM256 mode (TDM=“1”)
fs
LRCK Frequency
32
48
kHz
tLRH
“H” time
(Note 7)
1/8fs
ns
Audio Interface Timing (Slave mode)
Normal mode (TDM=“0”)
SCLK Period
tBCK
160
ns
SCLK Pulse Width Low
tBCKL
65
ns
Pulse Width High
tBCKH
65
ns
LRCK Edge to SCLK “↑”
(Note 9)
tLRB
30
ns
SCLK “↑” to LRCK Edge
(Note 9)
tBLR
30
ns
LRCK to SDTO(MSB) (Except I2S mode)
tLRS
35
ns
SCLK “↓” to SDTO
tBSD
35
ns
SDTI Hold Time
tSDH
10
ns
SDTI Setup Time
tSDS
10
ns
TDM256 mode (TDM=“1”)
SCLK Period
tBCK
81
ns
SCLK Pulse Width Low
tBCKL
32
ns
Pulse Width High
tBCKH
32
ns
LRCK Edge to SCLK “↑”
(Note 9)
tLRB
20
ns
SCLK “↑” to LRCK Edge
(Note 9)
tBLR
20
ns
SCLK “↓” to SDTO
tBSD
20
ns
TDMIN Hold Time
tSDH
10
ns
TDMIN Setup Time
tSDS
10
ns
SRC Input (Note 10)
SCLK Period
tBCK
81
ns
SCLK Pulse Width Low
tBCKL
32
ns
Pulse Width High
tBCKH
32
ns
LRCK Edge to SCLK “↑”
(Note 9)
tLRB
20
ns
SCLK “↑” to LRCK Edge
(Note 9)
tBLR
20
ns
SDTI Hold Time
tSDH
10
ns
SDTI Setup Time
tSDS
10
ns
Rev. 0.3-PB
2008/01
- 11 -
[AK4141]
SWITCHING CHARACTERISTICS (Continued)
(Ta=-20∼ 85°C; AVDD= 3.0~3.6V, DVDD=1.7~1.9V TVDD=1.7~3.6V; GND1=GND2=GND3=GND4=GND5=0V;
CL=20pF, Cb=400pF(SDA pin))
Parameter (Note 8)
Symbol
min
typ
max
Units
Audio Interface Timing (Master mode)
Normal mode (TDM=“0”)
SCLK Frequency
fBCK
64fs
Hz
SCLK Duty
dBCK
50
%
SCLK “↓” to LRCK
tMBLR
−20
20
ns
SCLK “↓” to SDTO
tBSD
−40
40
ns
TDM256 mode (TDM=“1”)
SCLK Frequency
fBCK
256fs
Hz
SCLK Duty
(Note 11)
dBCK
50
%
SCLK “↓” to LRCK
tMBLR
−12
12
ns
SCLK “↓” to SDTO
tBSD
−20
20
ns
TDMIN Hold Time
tSDH
10
ns
TDMIN Setup Time
tSDS
10
ns
Power-Down & Reset Timing
PDN Pulse Width
(Note 12)
tPD
150
ns
PDN “↑” to SDTO valid
(Note 13)
tPDV
TBD
1/fs
Note 7. “L” time at I2S format.
Note 8. SCLK= SCLK/SCLK4/SCLK5, LRCK= SCLK/LRCK4/LRCK5 unless otherwise specified.
Note 9. SCLK rising edge must not occur at the same time as LRCK edge.
Note 10. SCLK= SCLK4/SCLK5, LRCK= LRCK4/LRCK5.
Note 11. This value is MCLK=512fs. Duty cycle is not guaranteed when MCLK=256fs/384fs.
Note 12. The AK4141 can be reset by bringing the PDN pin = “L”.
Note 13. This cycle is the number of LRCK rising edges from the PDN pin = “H”.
Parameter
Control Interface Timing (I2C Bus):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time
(prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 14)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise
Suppressed by Input Filter
Capacitive load on bus
Symbol
min
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
Cb
typ
max
Units
1.3
0.6
400
-
kHz
μs
μs
1.3
0.6
0.6
0
0.1
0.6
0
0.9
0.3
0.3
50
μs
μs
μs
μs
μs
μs
μs
μs
ns
0
400
pF
Note 14. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 15. I2C is a registered trademark of Philips Semiconductors.
Rev. 0.3-PB
2008/01
- 12 -
[AK4141]
■ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tBCK
VIH
SCLK
VIL
tBCKH
tBCKL
Figure 1. Clock Timing (TDM bit = “0”)
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tLRH
tLRL
tBCK
VIH
SCLK
VIL
tBCKH
tBCKL
Figure 2. Clock Timing (TDM bit = “1”)
Rev. 0.3-PB
2008/01
- 13 -
[AK4141]
VIH
LRCK
VIL
tBLR
tLRB
VIH
SCLK
VIL
tLRS
tBSD
SDTO
50%TVDD
Figure 3. Audio Interface Timing (Slave mode, Normal Mode)
VIH
LRCK
VIL
tBLR
tLRB
VIH
SCLK
VIL
tBSD
SDTO
50%TVDD
tSDS
tSDH
VIH
SDTI
VIL
Figure 4. Audio Interface Timing (Slave mode, TDM Mode)
Rev. 0.3-PB
2008/01
- 14 -
[AK4141]
LRCK
50%TVDD
tMBLR
50%TVDD
SCLK
tBSD
50%TVDD
SDTO
tDXS
tDXH
VIH
SDTI
VIL
Figure 5. Audio Interface Timing (Master mode, Normal Mode)
LRCK
50%TVDD
tMBLR
50%TVDD
SCLK
tBSD
SDTO
50%TVDD
tSDS
tSDH
VIH
TDMIN
VIL
Figure 6. Audio Interface Timing (Master mode, TDM Mode)
VIH
PDN
VIL
tPDV
SDTO
50%VDD
tPD
PDN
VIL
Figure 7. Power Down & Reset Timing
Rev. 0.3-PB
2008/01
- 15 -
[AK4141]
VIH
SDA
VIL
tBUF
tLOW
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
Start
tSU:STA
tSU:STO
Start
Stop
Figure 8. I2C Bus mode Timing
Rev. 0.3-PB
2008/01
- 16 -
[AK4141]
PACKAGE
48pin LQFP(Unit:mm)
1.70Max
9.0 ± 0.2
0.13 ± 0.13
7.0
36
1.40 ± 0.05
24
48
13
7.0
37
1
0.5
9.0 ± 0.2
25
12
0.22 ± 0.1
0.10 M
0° ∼ 10°
0.10
0.3~0.75
■ Package & Lead frame material
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder (Pb free) plate
Rev. 0.3-PB
2008/01
- 17 -
[AK4141]
MARKING
AK4141EQ
XXXXXXX
1
XXXXXXX: Date code identifier
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
EMD Corporation (AKEMD) or authorized distributors as to current status of the products.
z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or
use of any information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKEMD. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform
may reasonably be expected to result in loss of life or in significant injury or damage to person or property.
z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and conditions, and the
buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any
and all claims arising from the use of said product in the absence of such notification.
Rev. 0.3-PB
2008/01
- 18 -
[AK4141]
Thank you for your access to AKEMD products information.
More detail product information is available, please contact our
sales office or authorized distributors.
Rev. 0.3-PB
2008/01
- 19 -