Advanced Power Factor Correction Agenda • Introduction Basic solutions for power factor correction New needs to address • Interleaved PFC Basic characteristics A discrete solution Performance • Bridgeless PFC Why should we care of the input bridge? Main solutions Ivo Barbi solution Performance of a wide mains, 800 W application • Conclusion www.onsemi.com 2 Agenda • Introduction Basic solutions for power factor correction New needs to address • Interleaved PFC Basic characteristics A discrete solution Performance • Bridgeless PFC Why should we care of the input bridge? Main solutions Ivo Barbi solution Performance of a wide mains, 800 W application • Conclusion www.onsemi.com 3 Why Implement PFC? Vin (t ) = 2 ⋅ Vin( rms ) ⋅ sin(ω t ) Iin (t ) = ? Ac line • The mains utility provides a sinusoidal voltage Vin(t). • The shape and phase of Iin(t) depend on the load. www.onsemi.com 4 AC Line Rectification Leads to Current Spikes… Rectifiers Cbulk is refueled when Vin(t) > Vout Converter VIN Ac Line Bulk Storage Capacitor Load 3 2 1 Iin(t) Vin(t) High current spike! • Only the fundamental component produces real power • Harmonic currents circulate uselessly (reactive power) • The line rms current increases www.onsemi.com 5 Too High rms Currents!... • High rms currents reduce outlet capability n°1 Pin(avg) = 119 W, Vin(rms) = 85 V Iin(rms) = 2.5 A n°2 Pin(avg) = 119 W, Vin(rms) = 85 V Iin(rms) = 1.4 A PF = 0.56 Same power (W) PF = 1.00 n°1 n°2 16/2.5 = 6 monitors 16/1.4 = 11 resistors Iin( rms ) = (Iin(rms))max = 16 A www.onsemi.com 6 Pin(avg ) Vin( rms ) ⋅ PF Power Factor Standard Class ClassCC YES Lighting Lighting Equipment? Equipment? IEC61000-3-2 Class ClassBB YES NO NO Portable PortableTool? Tool? NO Special Special Waveform Waveform P<=600W? P<=600W? YES YES Motor Motor Equipment? Equipment? NO NO Three ThreePhase Phase Equipment? Equipment? Class ClassDD YES Class ClassAA Mandatory for PC, TV sets Monitors P > 75 W • The standard specifies a maximum level up to harmonic 39 www.onsemi.com 7 Need for a PFC Stage PFC Stage Diode Bridge Power Supply + AC Line Controller Controller IN Bulk Capacitor LOAD LOAD - Current reference Icoil,pk Iline(t) • A boost pre-converter draws a sinusoidal current from the line to provide a dc voltage (bulk voltage) • The current within the coil is made sinusoidal by: – Forcing it to follow a sinusoidal reference (current mode) – Controlling the duty-cycle appropriately (voltage mode) www.onsemi.com 8 Operating Modes Overview • ON Semiconductor offers solutions for three modes Operating Mode IL IL IL Tclamp www.onsemi.com 9 Tclamp Main Feature Continuous Conduction Mode (CCM) Always hard-switching Inductor value is largest Minimized rms current e.g.: NCP1654 Critical conduction Mode (CrM) Large rms current Switching frequency is not fixed e.g.: NCP1606 Frequency Clamped Critical Conduction Mode (FCCrM) Large rms current Frequency is limited Reduced coil inductance e.g.: NCP1605 FCCrM: an Efficient Mode • Frequency Clamped CrM seems the most efficient solution • Efficiency of a 300 W, wide mains PFC has been measured: Efficiency at 100 Vrms NCP1605 (FCCrM) NCP1606 (CrM) 20% 30% www.onsemi.com 10 40% The complete study will be published in the PFC handbook revision that will be released in Q1 2009. NCP1654 (CCM) 50% 60% 70% Output Load 80% 90% 100% New Needs to Address • High efficiency for ATX power supplies: – Efficiency is measured at: • 20% Pout(max) • 50% Pout(max) • 100% Pout(max) • Slim LCD TVs: – Components height is limited www.onsemi.com 11 Agenda • Introduction Basic solutions for power factor correction New needs to address • Interleaved PFC Basic characteristics A discrete solution Performance • Bridgeless PFC Why should we care of the input bridge? Main solutions Ivo Barbi solution Performance of a wide mains, 800 W application • Conclusion www.onsemi.com 12 Interleaved PFC • Two small PFC stages delivering (Pin(avg) / 2) in lieu of a single big one IL1 Ac line Iin (t ) ID1 1 8 2 7 3 6 4 5 NCP1601 Vin (t ) EMI Filter IL(tot ) IL 2 ID 2 1 8 2 7 3 6 4 5 NCP1601 ID(tot ) Cbulk Vout LOAD • If the two phases are out-of-phase, the resulting currents (IL(tot)) and (ID(tot)) exhibit a dramatically reduced ripple. www.onsemi.com 13 Interleaved Benefits • More components but: – A 150 W PFC is easier to design than a 300 W one – Modular approach – Two DCM PFCs look like a CCM PFC converter… • Eases EMI filtering and reduces the output rms current • Only interleaving of DCM PFCs will be considered 0 Iin 3 0 2 0 (Icoil)phase1 (Icoil)phase2 1 time 0 www.onsemi.com 14 Input Current Ripple What is the ripple of the IL(tot) total input current? IL1 ID1 1 Ac line Iin (t ) 8 2 7 3 6 4 5 NCP1601 Vin (t ) EMI Filter IL(tot ) IL2 ID2 1 8 2 7 3 6 4 5 NCP1601 www.onsemi.com 15 ID(tot ) Cbulk Vout LOAD Computing the Input Current Ripple • Let’s assume that: – Vin and the switching period are constant over few cycles – The two branches operate in CrM • There are two cases: – Vin <Vout /2 (or d>0.5): The on-times of the two phases overlap. The input current peaks at the end of the conduction intervals. – Vin >Vout /2 (or d<0.5): There is no overlap but still, the input current peaks at the end of the each conduction time • Using ⎛ ton Vin = = − 1 d ⎜⎜ Tsw Vout ⎝ www.onsemi.com 16 ⎞ ⎟⎟, ⎠ we can derive the current ripple Finally,… Vin (t ) ≤ Averaged input current (line current) ( Peak Current envelop ( www.onsemi.com 17 Iin (t ) = IL(tot ) Peak to peak ripple Valley Current envelop Vout 2 ΔIL(tot ) IL( tot ) ) )pp pk Tsw ⎛ Vin = Iin ⋅ ⎜⎜ 1 − ⎝ Vout − Vin v Vout = Iin ⋅ 2 ⋅ (Vout − Vin ) Vout 2 Vin Vin ⋅ Pin(avg ) = = Rin Vin( rms )2 ⎞ ⎟⎟ ⎠ ⎛ ⎞ Vout = 2 ⋅ Iin ⋅ ⎜ 1 − ⎟ ⎜ ⎟ V V 4 ⋅ − ( ) out in ⎠ ⎝ (I ( ) ) L tot Vin (t ) ≥ ( ΔIL(tot ) (I ( ) ) L tot )pp ⎞ ⎟⎟ ⎠ ⎛ Vout ⎞ = 2 ⋅ Iin ⋅ ⎜⎜ 1 − ⎟⎟ ⋅ V 4 in ⎠ ⎝ pk (I ( ) ) L tot ⎛ V = Iin ⋅ ⎜⎜ 2 − out Vin ⎝ v = Pin(avg ) ⋅ Vout 2 ⋅ Vin( rms )2 Peak to Peak Ripple of the Input Current ( ΔIL(tot ) )pp Iin 120 P k to pk rip ple (% ) 100 ⎛V (%) vs ⎜⎜ V in ⎝ out • The input ripple only depends on the ratio (Vin /Vout): • Unlike in CCM: ⎞ ⎟⎟ ⎠ Ripple is 0 at Vin = Vout / 2 80 – L plays no role – The ripple percentage does not depend on the load 60 40 • At low line (Vin /Vout = 0.3), the ripple is +/-28% (at the 20 0 0 0.25 0.5 Vin/Vout www.onsemi.com 18 0.75 1 sinusoid top, assuming 180° phase shift and CrM operation) Input Current Ripple at Low Line • When Vin remains lower than Vout / 2, the input current looks like that of a CCM, hysteretic PFC • (IL(tot)) swings between two nearly sinusoidal envelops Peak, averaged and valley current @ 90 Vrms, 320 W input (Vout = 390 V) Peak, valley and averaged Input Current (A) 7 Iin(t) 6 Envelop for the peak currents 5 4 3 Envelop for the valley currents 2 1 0 0.00% 25.00% 50.00% 75.00% time as a percentage of a period (%) www.onsemi.com 19 100.00% Input Current Ripple at High Line • When Vin exceeds (Vout / 2), the valley current is constant! ⎛ Vout • It equates ⎜⎜ ⎝ 2 ⋅ Rin ⎞ ⎟⎟ where Rin is the PFC input impedance ⎠ Peak, averaged and valley current @ 230 Vrms, 320 W input (Vout = 390 V) Peak, valley and averaged Input Current (A) 3.0 Iin(t) 2.5 2.0 1.5 1.0 0.5 0.0 0.00% Pin(avg )⋅Vout 25.00% 50.00% 75.00% time as a percentage of a period (%) www.onsemi.com 20 No ripple when Vin = Vout / 2 100.00% 2 ⋅ Vin( rms )2 = Vout 2 ⋅ Rin Line Input Current • For each branch, somewhere within the sinusoid: 2 ⋅ IL1 Tsw IL1 IL1 Tsw • The sum of the two averaged, sinusoidal phases currents gives the total line current: Iin = IL( tot ) Tsw 2 = IL1 Tsw + IL 2 Tsw • Assuming a perfect current balacing: 2 ⋅ IL1 Tsw = 2 ⋅ IL 2 Tsw = Iin • The peak current in each branch is Iin(t) www.onsemi.com 21 Ac Component of the Refueling Current • The refueling current (output diode(s) current) depends on the mode: 2.I in Iin Iin Single phase CCM Single phase CrM Interleaved CrM rms value over Tsw rms value over Tsw rms value over Tsw Iin ⋅ Vin Vout www.onsemi.com 22 Phase 1 Phase 2 2 3 ⋅ Iin Vin Vout Iin Vin 2 ⋅ Iin 3 Vout A Reduced RMS Current in the Bulk Capacitor • Integration over the sinusoid leads to (resistive load): Single phase CCM PFC Diode(s) rms current (ID(rms)) Single phase CrM or FCCrM PFC 2 2 ⎛P ⎞ 8 2 ⋅ ⎜ out ⎟ ⎝ η ⎠ 3π ⋅Vin( rms ) ⋅Vout ⎛P ⎞ 8 2 ⋅ ⎜ out ⎟ ⎝ η ⎠ − ⎛ Pout ⎜ 3π ⋅ Vin( rms ) ⋅ Vout ⎜⎝ Vout 300 W, Vout=390V Vin(rms)=90 V ID(rms) = 1.9 A IC(rms) = 1.7 A 2 ⎛P ⎞ 8 2 ⋅ ⎜ out ⎟ 2 ⎝ η ⎠ ⋅ 3π ⋅Vin( rms ) ⋅ Vout 3 ⎛P ⎞ 8 2 ⋅ ⎜ out ⎟ 2 ⎝ η ⎠ ⋅ 3 3π ⋅Vin( rms ) ⋅Vout 2 2 Capacitor rms current (IC(rms)) ⎞ ⎟⎟ ⎠ 2 ⎛P ⎞ 32 2 ⋅ ⎜ out ⎟ ⎝ η ⎠ − ⎛ Pout ⎜ 9π ⋅ Vin( rms ) ⋅ Vout ⎜⎝ Vout ID(rms) = 2.2 A IC(rms) = 2.1 A Interleaved CrM or FCCrM PFC 2 ⎞ ⎟⎟ ⎠ 2 ⎛P ⎞ 16 2 ⋅ ⎜ out ⎟ ⎝ η ⎠ − ⎛ Pout ⎜ 9π ⋅ Vin( rms ) ⋅ Vout ⎜⎝ Vout ID(tot)(rms) = 1.5 A IC(rms) = 1.3 A • Interleaving dramatically reduces the rms currents Î reduced losses, lower heating, increased reliability www.onsemi.com 23 ⎞ ⎟⎟ ⎠ 2 Summary www.onsemi.com 24 Agenda • Introduction Basic solutions for power factor correction New needs to address • Interleaved PFC Basic characteristics A discrete solution Performance • Bridgeless PFC Why should we care of the input bridge? Main solutions Ivo Barbi solution Performance of a wide mains, 800 W application • Conclusion www.onsemi.com 25 Interleaving: Master/Slave Approach… • The master branch operates freely • The slave follows with a 180° phase shift • Main challenge: maintaining the CrM operation (no CCM, no dead-time) L2 < L1 Tsw 2 Tsw 2 Tsw 2 Current mode: inductor unbalance www.onsemi.com 26 Tsw 2 Tsw 2 Tsw 2 Voltage mode: on-time shift Interleaving: Independent Phases Approach… • Each phase properly operates in CrM or FCCrM. • The two branches interact to set the 180° phase shift • Main challenge: to keep the proper phase shift On-time perturbation for one phase Tsw 2 Tsw 2 • We selected this approach www.onsemi.com 27 Tsw 2 CrM operation is maintained but a perturbation of the on-time may degrade the 180° phase shift General Principle on a Two-NCP1601 Solution • The solution lies on the Frequency Clamp Critical Conduction mode, unique scheme developed by ON Semiconductor (NCP1601) • Two NCP1601 drive two independent PFC branches: – Auxiliary windings are used to detect the core reset of each branch – The current sensing is shared by the two stages for protection only (Over Current Limitation) • The two branches are operating in voltage mode www.onsemi.com 28 Synchronization: the Main Challenge • One driver (DRV2) synchronizes the two branches so that: – Branch 1 (DRV1) cannot turn high until a time τ has elapsed – Branch 2 (DRV2) cannot dictate a new conduction phase within 2τ • Hence: – In fixed frequency operation, the switching period for each branch is 2τ and the two phases are naturally interleaved – In CrM, the switching frequency is that imposed by the current cycle (Tsw>2τ) and must stabilize out of phase. • Possible slippages are contained by a phase compensation circuitry (refer to www.onsemi.com for detailed AN available in Q4 2008). www.onsemi.com 29 NCP1601 Synchronization Capability 50 µA OSC pin + 100 µA Cosc 5.0 V / 3.5 V • The oscillator oscillates between 3.5 and 5V • The NCP1601 generates a clock when the oscillator goes below 3.5 V • The clock signal is stored until ZCD is detected S CLOCK Q Q R DRV 5V Vosc 3.5 V IL(coil current) Dead-time ZCD CLOCK Fixed Frequency www.onsemi.com 30 Critical Conduction Mode Operation @ 230 Vrms, Medium Load • SYNC2 2τ • DRV2 SYNC1 • • τ • DRV1 Each stage operates in fixed frequency mode Both branches are synchronized to DRV2 A new DRV2 pulse can take place after 2τ A new DRV1 pulse can occur after τ The switching period for each branch is then 2τ and they operate out of phase. A new drive sequence cannot take place as long as the SYNC signal remains higher than 3.5 V (see NCP1601 operation). www.onsemi.com 31 Operation at Low Line, Full Load • SYNC2 • DRV2 • SYNC1 • DRV1 www.onsemi.com 32 The circuit operates in critical conduction mode The operation of both branches are synchronized to DRV2 A new DRV2 pulse can take place after 2τ, but the MOSFET turn on is delayed until the core is reset A new DRV1 pulse can occur after τ, but again, the MOSFET turn on is delayed until the core is reset Remarks on the Solution • • • The NCP1601 operates in voltage mode Same on-time and hence switching period in the two branches A coil imbalance – Does not affect the switching period – “Only” causes a difference in the power amount conveyed by each branch Iin(1) Iin(2) L1 > L2 L = 2 L1 Phase 1 Phase 2 ton • ton time The two branches are synchronized but they operate independently: – Discontinuous conduction mode is guaranteed (zero current detection) – No risk of CCM operation – Both branches enter CrM at full load www.onsemi.com 33 D16 1N5406 X5 LPRIM = 150u LSEC = 1.5u Application Schematic D5 MUR550 6 D15 1N4148 Vaux2 R17 2.2 22 16 Q2 2N2907 23 X6 SPP11N60 R20 10k R21 47 EMI filter X1 LPRIM = 150u LSEC = 1.5u U1 KBU6K 9 27 18 - C8 100pF Q1 2N2907 40 R2 1k 28 X4 SPP11N60 R11 10k R31 820k R16 47 14 D10 5V The NCP1601 controllers are fed by an external 15 V power source C2x 100µF / 450V R7 2.2 33 C10x 4.7nF Type = Y1 Vbulk 11 D14 1N4148 C5 680nF Type = X2 IN D4 MUR550 24 + C18 680nF DRV2 R32 270k 45 D1 1N4148 15 R18 820k C21 1nF DRV1 CM1 R33 1k C6 680nF Type = X2 36 DRV1 C11 1.2nF 31 5 R22 75m / 3 W 7 13 3 6 19 4 5 26 7 R4 33k R29 82k Vfr R14 820k R27 270k 2 R8 1k 46 Vbulk 35 R5 820k C13 1nF D11 5V R30 10 vcc D6 1N4148 C19 100nF C7 100nF Vcontrol 54 R36 1k R26 10k R38 4.7k R24 100 R19 3.9k C1 1.2nF 12 C10 100µF /25 V X3 NCP1601 4 DRV2 Vaux 8 1 2 7 29 3 6 44 4 5 DRV2 D3 1N4148 SYNC2 Circuitry for Frequency Foldback R28 100k R25 150k vcc DRV2 DRV1 R39 2.2k 34 C12 470pF R12 2.2k 21 R35 2.2k DRV1 R6 10k DRV2 R9 10k R15 10k 10 R40 2.2k DRV2 25 Vfr Circuitry for compensation of possible phase shift C17 2.2nF R10 100 8 C9 470pF D2 1N4148 www.onsemi.com D7 1N4148 SYNC1 C14 100pF Earth Wide mains, 300 W, PFC pre-converter DRV1 Circuitry for zero current detection (branch 2) Vaux2 90-265VAC 34 2 41 N C20 100nF 8 1 C4 470pF D12 1N5406 L 17 R23 100 Current sensing X2 NCP1601 vcc R37 3.9k R1 3.9k 20 38 Vcontrol R3 10k Circuitry for zero current detection (branch 1) 39 L4 150µH C2 100nF 1 C16 4.7nF Type = Y1 Q3 2N2222 C3 10nF D9 6.8V R13 1k The Board… Wide mains, 300 W, PFC pre-converter MUR550 Two NCP1601 circuits www.onsemi.com 35 Buck converter to provide Vcc (not used for test) Input Voltage and Current IL(tot) (2 A/div) Vin (50 V/div) Full load, 90 Vrms IL(tot) (2 A/div) Full load, 230 Vrms Vin (100 V/div) • As expected, the input current looks like a CCM one • At high line, frequency foldback influences the ripple www.onsemi.com 36 Zoom of the Precedent Plots IL(tot) (2 A/div) Full load, 90 Vrms IL(tot) (1 A/div) DRV1 Full load, 230 Vrms DRV1 DRV2 DRV2 • These plots were obtained at the sinusoid top • The current swings at twice the frequency of each phase • At low and high line, the phase shift is substantially 180° www.onsemi.com 37 No Overlap between the Refueling Sequences Full load, 90 Vrms IL(tot) (2 A/div) IL(tot) (1 A/div) Full load, 230 Vrms Vds2 Vds1 Vds1 Vds2 • CrM at low line with valley switching • Fixed frequency operation at high line (frequency foldback) • No overlap between the demag. phases in both cases www.onsemi.com 38 Performance Measurements • Conditions for the measurements: – The measurements were made after the board was 30 mn operated full load, low line – All the measurements were made consecutively without interruption – PF, THD, Iin(rms) were measured by a power meter PM1200 – Vin(rms) was measured directly at the input of the board by a HP 34401A multimeter – Vout was measured by a HP 34401A multimeter – The input power was computed according to: Pin ( avg ) = Vin ( rms ) ⋅ Iin ( rms ) ⋅ PF – Open frame, ambient temperature, no fan www.onsemi.com 39 Efficiency versus Load 100.0% Results obtained in a relatively high frequency application allowing the use of small inductors: (85 kHz in each phase at 90 Vrms, full load, L1 = L2 =150 µH) 98.8% Efficiency (%) 230 Vrms 97.5% 120 Vrms 96.3% 95.0% 90 Vrms 93.8% 92.5% 30 60 90 20% Pmax 120 150 180 210 240 270 Output power (W) 300 330 Pmax The plot portrays the efficiency over the line range, from 20% to 100% of the load The efficiency remains higher than 95%! www.onsemi.com 40 Switching Frequency (at the Sinusoid Top) 100.0 85 kHz Switching frequency (kHz) 90.0 90 Vrms 80.0 70.0 60.0 120 Vrms 50.0 40.0 CrM lowers the switching frequency 230 Vrms 30.0 Frequency foldback 20.0 30 60 90 120 150 180 210 240 270 300 330 Output power (W) The plot portrays fsw (sinusoid top) over the line range, as a function of the load The PFC stages operate in CrM at full load www.onsemi.com 41 Conclusion • Interleaved PFCs – Reduce the input current ripple – Lower the bulk capacitor rms current • Two NCP1601 provide an efficient solution for interleaving • Besides interleaving, this solution takes benefit of: – The FCCrM mode that optimizes the efficiency – MUR550 diodes optimized for DCM PFC applications – Frequency foldback (light load) • The solution has been tested on a 300 W, wide mains board • 95% efficiency at 90 Vrms over a large load range (from 20% to 100% load) • A 16-pin interleaved PFC controller is under development www.onsemi.com 42 Agenda • Introduction Basic solutions for power factor correction New needs to address • Interleaved PFC Basic characteristics A discrete solution Performance • Bridgeless PFC Why should we care of the input bridge? Main solutions Ivo Barbi solution Performance of a wide mains, 800 W application • Conclusion www.onsemi.com 43 No bridge! The Diodes Bridge Ac line EMI filter + + PFC stage • The diodes bridge rectifies the ac line voltage • Two diodes conduct simultaneously • The PFC input current flows through two series diodes www.onsemi.com 44 Efficiency Loss caused by the Diodes Bridge • Average current flowing through the input diodes: Ibridge Tline = Iline (t ) T = line 2 2 π ⋅ Pout η ⋅Vin ( rms ) • Dissipation in the diodes bridge: Pbridge = 2 ⋅Vf ⋅ Ibridge ≈ 2 ⋅Vf ⋅ • If Vf = 1 V and (Vin(rms))LL = 90 V: 2 2 ⋅ Pout η ⋅ π ⋅Vin ( rms ) Pbridge ≈ 2% ⋅ Pout η Î In low mains applications (@ 90 Vrms), the diodes bridge wastes about 2% efficiency! www.onsemi.com 45 Basic Bridgeless PFC Switching cell when PH2 is high M1 is off PH1 D1 D2 M1 M2 L Ac Line PH2 Switching cell when PH1 is high M2 is off www.onsemi.com 46 Operation with Positive Half-Wave PH1 is high, PH2 is low: M1 is on: conduction time M1 is open: off time D1 PH1 Ac Line M2 Body diode PH2 M1 M2 body diode grounds PH2 as would a diode bridge. www.onsemi.com 47 Operation with Negative Half-Wave PH1 is low, PH2 is high: M2 is on: conduction time M1 is open: off time D2 PH1 Ac Line PH2 M1 Body diode M2 Both line terminals are pulsating at the switching frequency The pulsation swing is high (VOUT) HF noise that leads to a tedious EMI filtering www.onsemi.com 48 Ivo Barbi Bridgeless Boost PH1 Ac Line « PH1 » PFC stage « PH2 » PFC stage PH2 DRV Two PFC stages but: – One driver with no need for detecting the active half-wave – Improved thermal performance – As with convential PFC stages, the negative phase is always attached to ground. EMI issue is solved. www.onsemi.com 49 Current Sharing Phase 1 current (5 A/div) 0A 0A Part of the active phase current flows throught the inactive MOSFET and coil! Phase 2 current (5 A/div) Part of the current flows… … through the supposedly inactive MOSFET and coil www.onsemi.com 50 Two Return Paths… Small low frequency impedance PH2 is the positive terminal PH1 Ac Line PH2 Body diode 0V Vin DRV Rsense MOSFET is on MOSFET is off Need for current sense transformers www.onsemi.com 51 Schematic for 800 W Prototype « PH1 » PFC stage D7 CSD10060 L1 0.2m X4 Diode bridge PH1 2 PH1 + C15 1µF Type = X2 C16 1µF Type = X2 IN DRV1 RETURN R12 15k R18 10 D1 1N4007 C17 1µF Type = X2 CM2 49 R14 390k R13x 680k R12x 680k 24 Vpin1 23 R1 2200k C14 1 µF Type = X2 30 C7 10nF / 63 V D2x 1N4007 10 C18 4.7 nF Type = Y2 C1 100nF / 63V R23 680k 43 36 X5 NCP1653 C2 100nF R6 100k R22 680k F1 10 A 39 CS 40 D3 1N5817 R5 390 1 NC 2 InA OutA 7 D8 CSD10060 L4 0.2m 22 NC 8 D4 1N4148 X7 CS 33 1 FB Vcc 8 15 2 Vctrl Drv 7 13 3 In Gnd 6 CS Vm 5 12 4 R4xx 2.2k « PH2 » PFC stage C28 220nF PH2 53 R13 100 6 NCP1653 3 Gnd 4 InB OutB 5 Vcc 7 MC33152 Vcc2 DRV1 18 R20 15k R17 10 R21 3R 32 C27 100pF 37 R21x 680k C6 22µF C24 220nF C25 22µF 28 R3 470k 42 C13 1 µF Type = X2 Vcc2 R15 10 Vcc1 C3 220nF 5 RETURN 51 R36 100 R2 2700k X2 2*SPP20N60 (TO220) R19 10k Vout R16 3R 31 9 R11 180k Vaux C5 10nF 27 CM1 CS 7 PH2 - C19 4.7 nF Type = Y2 D2 1N4148 X3 X1 2*SPP20N60 (TO220) 20 1 R7 56k C4 1nF R20x 10k Vout RETURN 3 R4x 2.2k L N Earth 90 to 265 Vrms 50 or 60 Hz line voltage www.onsemi.com 52 R4 33m RETURN C11 330u / 450 V C12 330u / 450 V Board Photograph NCP1653 And MC33152 MOSFET driver Bulk converter to generate the Vcc voltage (NCP1012) www.onsemi.com 53 Typical Waveforms Iline (10 A/div) 90 Vrms 230 Vrms Iline (10 A/div) Vout Vout CS (negative sensing) CS (negative sensing) Vin,1 (input voltage for branch 1) Vin,1 • • • These plots portray typical waveforms at full load (Iout = 2.1 A) “CS” is representative of the current flowing into the MOSFETs of the two branches (common output of the current transformers) The input current is sinusoidal www.onsemi.com 54 Zoom of the Precedent Plots (Top of the Sinusoid) 90 Vrms 230 Vrms Iline (10 A/div) Iline (10 A/div) Vout Vout Vin,1 Vsense (negative sensing) Vin,1 (input voltage for branch 1) • • The switching frequency is 100 kHz The waveforms are similar to those of a traditional CCM PFC www.onsemi.com 55 Vsense (negative sensing) Performance Measurements • Conditions for the measurements: – The measurements were made after the board was 30 mn operated full load, low line – All the measurements were made consecutively without interruption – PF, THD, Iin(rms) were measured by a power meter PM1200 – Vin(rms) was measured directly at the input of the board by a HP 34401A multimeter – Vout was measured by a HP 34401A multimeter – The input power was computed according to: Pin ( avg ) = Vin ( rms ) ⋅ Iin ( rms ) ⋅ PF – Open frame, ambient temperature, no fan www.onsemi.com 56 Efficiency versus Load 100.0% 230 Vrms Efficiency (%) 98.0% 120 Vrms 96.0% 90 Vrms 94.0% 92.0% 90.0% 100 200 20% Pmax 300 400 500 Output power (W) 600 700 800 Pmax The plot portrays the efficiency from 20% to 100% of the load At 90 Vrms, full load, it is about 94% without fan (95% at 100 Vrms) At 20% of full load, efficiency is in the range or higher than 96% www.onsemi.com 57 THD versus Load 20.0 THD (%) 15.0 90 Vrms 10.0 230 Vrms 5.0 120 Vrms 0.0 100 200 20% Pmax • 400 500 600 Output power (W) THD remains very low on the whole range www.onsemi.com 58 300 700 800 Pmax 900 Conclusion • A bridgeless PFC controlled by the NCP1653 has been developed (100 kHz) • The prototype was tested at full load (800 W output) without fan (open frame, ambient temperature) • In these conditions, the efficiency was measured in the range of 94% at 90 Vrms and 95% at 100 Vrms • The THD remains very low • Bridgeless can be an efficient solution for high power applications. • An application note is being prepared and should be posted in Q4 this year. www.onsemi.com 59 Agenda • Introduction Basic solutions for power factor correction New needs to address • Interleaved PFC Basic characteristics A discrete solution Performance • Bridgeless PFC Why should we care of the input bridge? Main solutions Ivo Barbi solution Performance of a wide mains, 800 W application • Conclusion www.onsemi.com 60 Conclusion • New requirements: • Compactness and form factor (LCD TV) • Efficiency (ATX power supplies) • New solutions can address them • Interleaved PFC brings: • • • • • Efficiency Flat design Improved heat distribution Reduced rms current through the PFC stage Modular approach • Bridgeless PFC: • halves the losses in the input rectification • Improves the heat distribution • ON Semiconductor supports these innovative approaches www.onsemi.com 61 For More Information • View the extensive portfolio of power management products from ON Semiconductor at www.onsemi.com • View reference designs, design notes, and other material supporting the design of highly efficient power supplies at www.onsemi.com/powersupplies www.onsemi.com 62