Voltage Regulators
AN8049SH
1.8-volt 3-channel step-up, step-down, and polarity inverting
DC-DC converter control IC
Unit : mm
■ Overview
6.5±0.3
+0.10
5.5±0.3
7.5±0.3
13
0° to 10°
1
(0.50)
12
0.50
Seating plane
0.2±0.1
0.65±0.10
1.5±0.2
(0.50)
0.65±0.10
0.1±0.1
■ Features
24
0.15 – 0.05
The AN8049SH is a three-channel PWM DC-DC
converter control IC that features low-voltage operation.
This IC can form a power supply that provides two stepup outputs and one step-down or polarity inverted output
with a minimal number of external components. The
AN8049SH features the ability to operate from a supply
voltage as low as 1.8 V, and thus can be operated from
two dry-batteries.
Seating plane
• Wide operating supply voltage range: 1.8 V to 14 V
• High-precision reference voltage circuit
SSOP024-P-0300A
— VREF pin voltage: ±1%
— Error amplifier: ±1.5%
• Surface mounting package for miniaturized and thinner power supplies
Package: SSOP-24D
0.5-mm lead pitch
7.8 mm × 6.8 mm × t 1.9 mm
• Supports control over a wide output frequency range: 20 kHz to 1 MHz
• On/off (sequence control) pins provided for each channel for easy sequence control setup
• The negative supply error amplifier supports 0-volt input.
Common-mode input voltage range: − 0.1 V to VCC −1.4 V
This allows the number of external components to be reduced by two resistors.
• Fixed duty factor: 86%
However, the duty can be adjusted to anywhere from 0% to 100% with an external resistor.
• Timer latch short-circuit protection circuit (charge current: 1.1 µA typical)
• Low input voltage malfunction prevention circuit (U.V.L.O.) (operation start voltage: 1.67 V typical)
• Standby function (active-high control input, standby mode current: 1 µA maximum)
• Alternate package versions also available.
Part No.: AN8049FHN
Package: QFN-24
0.5-mm lead pitch
5.4 mm × 4.4 mm × t 0.8 mm
■ Applications
• Electronic equipment that requires a power supply system
1
AN8049SH
Voltage Regulators
DT3
CTL3
Error
amplifier 2
VREF
5
8
1.1 µA
VCC
20 kΩ
3
1.26 V
CTL2
6
27 kΩ
VREF
45 kΩ
14
55 kΩ
OUT3
RB2
OUT2
GND
DT2
20 kΩ
22
13
1.1 µA
FB2
21
IN−2
10
PWM2
1.26 V
1.26 V
OUT1
27 kΩ
15
PWM3
Error
amplifier 3
RB1
PWM1
0.9 V
2
12
R Q
S
Latch
1.26 V
S.C.P. comp.
20
55 kΩ
U.V.L.O.
1.1 µA
Off
OSC
17
DT1
0.7 V On/off VCC
0.3 V
control
11
VCC
1
18
IN+3
19
IN−3
4
1.26 V
56 kΩ 44 kΩ
FB3
Sawtooth wave generator
20 kΩ
1.26 V
S.C.P.
1.26 V
(Allowance: ±1%)
45 kΩ
Reference voltage
supply VREF
1.1 µA
Error
amplifier 1
VREF
9
16
7
VCC
CTL1
FB1
24
23
IN-1
■ Block Diagram
■ Pin Descriptions
2
Pin No.
Symbol
Description
Pin No.
Symbol
Description
1
S.C.P.
Connection for the capacitor
that provides the shortcircuit protection circuit time
constant
12
OUT1
OUT1 block push-pull output
13
OUT2
OUT2 block push-pull output
14
GND
Ground
15
OUT3
OUT3 block open-collector output
16
VCC
Supply voltage
17
OSC
Oscillator circuit timing resistor and
capacitor connection
2
DT3
Channel 3 soft start setting
3
DT2
Channel 2 soft start setting
4
DT1
Channel 1 soft start setting
5
CTL3
Channel 3 on/off control
6
CTL2
Channel 2 on/off control
18
IN+3
Error amplifier 3 noninverting input
7
CTL1
Channel 1 on/off control
19
IN−3
Error amplifier 3 inverting input
8
Off
On/off control
20
FB3
Error amplifier 3 output
9
VREF
Reference voltage output
21
IN−2
Error amplifier 2 inverting input
10
RB2
Connection for the OUT2
block output source current
setting resistor
22
FB2
Error amplifier 2 output
23
IN−1
Error amplifier 1 inverting input
11
RB1
Connection for the OUT1
block output source current
setting resistor
24
FB1
Error amplifier 1 output
Voltage Regulators
AN8049SH
■ Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Supply voltage
VCC
14.2
V
Off pin allowable application
voltage
VOFF
14.2
V
CTL pin allowable application
voltage
VCTL
VCC − 0.2
V
Error amplifier input pin
allowable application voltage *2
VIN
6
V
Supply current
ICC
mA
ISO(OUT)
−50
mA
IO
+50
mA
PD
146
mW
Operating temperature
Topr
−30 to +85
°C
Storage temperature
Tstg
−55 to +125
°C
OUT1 and OUT2 pin output
source current
OUT3 pin output current
Power dissipation
*1
Note) 1. Do not apply external currents or voltages to any pins not specifically mentioned. For circuit currents, '+' denotes current
flowing into the IC, and '−' denotes current flowing out of the IC.
2. Items other than the storage temperature, operating temperature, and power dissipation are all stipulated for an ambient
temperature Ta = 25°C.
3. *1: Ta = 85°C. See the "Application Notes" for details on the relationship between IC power dissipation and the ambient
temperature.
2:
* When VCC < 6 V, the following condition must hold: VIN−1 = VIN−2 = VCC − 0.2 V.
■ Recommended Operating Range
Parameter
Symbol
Range
Unit
VOFF
0 to 14
V
ISO(OUT)
−40 to −1
mA
OUT3 pin output current
IO
40 (max.)
Timing resistance
RT
3 to 33
kΩ
Timing capacitance
CT
100 to 10 000
pF
Oscillator frequency
fOUT
20 to 1 000
kHz
Short-circuit protection time-constant setting capacitance
CSCP
1 000 (min.)
pF
RB
750 to 15 000
Ω
Off pin application voltage
OUT1 and OUT2 pin output source current
Output current setting resistance
3
AN8049SH
Voltage Regulators
■ Electrical Characteristics at VCC = 2.4 V, CREF = 0.1 µF, Ta = 25°C
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
1.247
1.26
1.273
V
Reference voltage block
Reference voltage
VREF
IREF = − 0.1 mA
Line regulation with input fluctuation
Line
VCC = 1.8 V to 14 V
2
20
mV
Load regulation
Load
IREF = − 0.1 mA to −1 mA
−20
−3
mV
VUON
1.59
1.67
1.75
V
VTH1
1.241
1.26
1.279
V
IB1
0.1
0.2
µA
High-level output voltage 1
VEH1
1.0
1.2
1.4
V
Low-level output voltage 1
VEL1
0.2
V
Output source current 1
ISO(FB)1
−38
−31
−24
µA
Output sink current 1
ISI(FB)1
0.5
mA
VTH2
1.241
1.26
1.279
V
IB2
0.1
0.2
µA
High-level output voltage 2
VEH2
1.0
1.2
1.4
V
Low-level output voltage 2
VEL2
0.2
V
Output source current 2
ISO(FB)2
−38
−31
−24
µA
Output sink current 2
ISI(FB)2
0.5
mA
Input offset voltage
VIO
−6
6
mV
Common-mode input voltage range
VICR
− 0.1
VCC
−1.4
V
IB3
− 0.6
− 0.3
µA
High-level output voltage 3
VEH3
1.0
1.2
1.4
V
Low-level output voltage 3
VEL3
0.2
V
Output source current 3
ISO(FB)3
−38
−31
−24
µA
Output sink current 3
ISI(FB)3
0.5
mA
170
190
210
kHz
U.V.L.O. block
Circuit operation start voltage
Error amplifier 1 block
Input threshold voltage 1
Input bias current 1
Error amplifier 2 block
Input threshold voltage 2
Input bias current 2
Error amplifier 3 block
Input bias current 3
Oscillator block
Oscillator frequency
4
fOUT
RT = 7.5 kΩ, CT = 680 pF
Voltage Regulators
AN8049SH
■ Electrical Characteristics at VCC = 2.4 V, CREF = 0.1 µF, Ta = 25°C (continued)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Output 1 block
Output duty factor 1
Du1
RT = 7.5 kΩ, CT = 680 pF
80
86
92
%
High-level output voltage 1
VOH1
IO = −10 mA, RB = 1 kΩ
VCC −1
V
Low-level output voltage 1
VOL1
IO = 10 mA, RB = 1 kΩ
0.2
V
Output source current 1
ISO(OUT)1 VO = 0.7 V, RB = 1 kΩ
−34
−29
−24
mA
Output sink current 3
ISI(OUT)1
VO = 0.7 V, RB = 1 kΩ
40
mA
Pull-down resistor 1
RO1
17
27
37
kΩ
Output 2 block
Output duty factor 2
Du2
RT = 7.5 kΩ, CT = 680 pF
80
86
92
%
High-level output voltage 2
VOH2
IO = −10 mA, RB = 1 kΩ
VCC −1
V
Low-level output voltage 2
VOL2
IO = 10 mA, RB = 1 kΩ
0.2
V
Output source current 2
ISO(OUT)2 VO = 0.7 V, RB = 1 kΩ
−34
−29
−24
mA
Output sink current 2
ISI(OUT)2
VO = 0.7 V, RB = 1 kΩ
40
mA
Pull-down resistor 2
RO2
17
27
37
kΩ
RT = 7.5 kΩ, CT = 680 pF
80
86
92
%
VO(SAT)
IO = 40 mA
0.5
V
IOLE
V13 = 14 V
1
µA
Output 3 block
Output duty factor 3
Output saturation voltage
Du3
Output leakage current
Short-circuit protection circuit block
Input standby voltage
VSTBY
0.1
V
Input threshold voltage
VTHPC
0.8
0.9
1.0
V
Input latch voltage
VIN
0.1
V
Charge current
ICHG
VSCP = 0 V
−1.43
−1.1 − 0.77
µA
On/off control block
Input threshold voltage
VON(TH)
0.6
0.9
1.2
V
VTHCTL
1.07
1.26
1.45
V
−1.43
−1.1 − 0.77
µA
4.2
5.5
mA
1
µA
CTL block
Input threshold voltage
Charge current
ICTL
VCTL = 0 V
Whole Device
Average consumption current
ICC(OFF)
Standby mode current
ICC(SB)
RB = 9.1 kΩ, duty = 50%
5
AN8049SH
Voltage Regulators
■ Electrical Characteristics at Ta = 25°C (continued)
• Design reference data
Note: The characteristics listed below are reference values related to the IC design and are not guaranteed.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Reference voltage block
VREF temperature characteristics
VRFEdT
Ta = −30°C to +85°C
1
%
VTHdT1
Ta = −30°C to +85°C
1.5
%
AV1
80
dB
VTHdT2
1.5
%
AV2
80
dB
AV3
80
dB
Error amplifier 1 block
VTH temperature characteristics
Open loop gain 1
Error amplifier 2 block
VTH temperature variation
Open loop gain 2
Error amplifier 3 block
Open loop gain 3
Oscillator block
Frequency supply voltage
characteristics
fDV
VCC = 1.8 V to 14 V
RT = 7.5 kΩ, CT = 680 pF
1
%
Frequency temperature
characteristics
fDT
Ta = −30°C to +85°C
RT = 7.5 kΩ, CT = 680 pF
3
%
1.26
V
38
µA
Short-circuit protection circuit block
Comparator threshold voltage
VTHL
On/off control block
Off pin current
6
IOFF
VOFF = 5 V
Voltage Regulators
AN8049SH
■ Terminal Equivalent Circuits
Pin No.
1
Equivalent circuit
VCC
1.1 µA
Latch
S
Q
1.26 V R
Output
shutoff
1.5 kΩ
Description
I/O
S.C.P.:
Connection for the capacitor that sets
the timer latch short-circuit protection
circuit time constant. Use a capacitor
with a value of 1 000 pF or higher.
The charge current ICHG is 1.1 µA
typical.
O
DT3:
Sets the channel 3 soft start time.
Set the time by connecting a capacitor
between this pin and ground.
(See the "Application Notes, [7]" section.)
Note that although the channel 3
maximum on duty is set internally to
86%, the maximum on duty can be
adjusted by connecting resistors between
this pin and ground, and between this
pin and the VREF pin. (See the "Application
I
1
2
9 20 17
PWM3
44 kΩ
2
46 kΩ
Notes, [6]" section.)
3
9 22 17
PWM2
45 kΩ
3
55 kΩ
4
9 24 17
45 kΩ
4
55 kΩ
PWM1
DT2:
Sets the channel 2 soft start time.
Set the time by connecting a capacitor
between this pin and ground.
(See the "Application Notes, [7]" section.)
Note that although the channel 2
maximum on duty is set internally to
86%, the maximum on duty can be
adjusted by connecting resistors
between this pin and ground, and
between this pin and the VREF pin.
(See the "Application Notes, [6]" section.)
I
DT1:
Sets the channel 1 soft start time.
Set the time by connecting a capacitor
between this pin and ground.
(See the "Application Notes, [7]" section.)
Note that although the channel 1
maximum on duty is set internally to
86%, the maximum on duty can be
adjusted by connecting resistors
between this pin and ground, and
between this pin and the VREF pin.
(See the "Application Notes, [6]" section.)
I
7
AN8049SH
Voltage Regulators
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
5
VCC
1.1 µA
20 kΩ
High
Channel 3
1.26 V output operation
5
6
VCC
1.1 µA
20 kΩ
High
Channel 2
1.26 V output operation
6
7
VCC
1.1 µA
20 kΩ
7
8
High
Channel 1
1.26 V output operation
Description
I/O
CTL3:
Controls the on/off state of channel 3. A
delay can be provided in the power supply
turn-on start time by connecting a capacitor
between this pin and ground.
(See the "Application Notes, [9]" section.)
tDLY3 = 1.26 (V) × CCTL3 (µF)/1.1 (µA) (s)
This pin can also be used to control the
on/off state with an external signal. In that
case, the allowable input voltage range is
from 0 V to VCC. Note that during
U.V.L.O. and timer latch operation, this
pin is connected to ground through a
20 kΩ resistor.
I
CTL2:
Controls the on/off state of channel 2.
A delay can be provided in the power
supply turn-on start time by connecting
a capacitor between this pin and
ground.
(See the "Application Notes, [9]" section.)
tDLY2 = 1.26 (V) × CCTL2 (µF)/1.1 (µA) (s)
This pin can also be used to control the
on/off state with an external signal.
In that case, the allowable input voltage
range is from 0 V to VCC. Note that
during U.V.L.O. and timer latch operation,
this pin is connected to ground through a
20 kΩ resistor.
I
CTL1:
Controls the on/off state of channel 1.
A delay can be provided in the power
supply turn-on start time by connecting
a capacitor between this pin and
ground. (See the "Application Notes, [9]"
section.)
tDLY1 = 1.26 (V) × CCTL1 (µF)/1.1 (µA) (s)
This pin can also be used to control the
on/off state with an external signal.
In that case, the allowable input voltage
range is from 0 V to VCC. Note that
during U.V.L.O. and timer latch operation,
this pin is connected to ground through a
20 kΩ resistor.
I
Voltage Regulators
AN8049SH
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
8
8
100 kΩ
Start and stop of
internal circuits.
9
VCC
9
10
16
ISO(OUT)2
Description
I/O
Off:
Controls the on/off state.
When the input is high: normal
operation
(VOFF > 1.2 V)
When the input is low: standby mode
(VOFF < 0.6 V)
In standby mode, the total current
consumption is held to under 1 µA.
I
VREF:
Outputs the internal reference voltage.
The reference voltage is 1.26 V
(allowance: ±1%) when VCC is
2.4 V and IREF is − 0.1 mA. Insert a
capacitor of at least 0.1 µF between
VREF and ground for phase
compensation.
O
RB2:
Connection for a resistor that sets the
channel 2 output current.
Use a resistor in the range 750 Ω to
15 kΩ.
I
RB1:
Connection for a resistor that sets the
channel 1 output current.
Use a resistor in the range 750 Ω to
15 kΩ.
I
OUT1:
Push-pull output.
The absolute maximum rating for the
output source current is −50 mA.
The output source current is set by the
external resistor connected to the RB1
pin.
O
13
200 Ω
ISI(OUT)2
30 kΩ
10
11
16
ISO(OUT)1
12
200 Ω
ISI(OUT)1
30 kΩ
11
12
See pin 11.
9
AN8049SH
Voltage Regulators
■ Terminal Equivalent Circuits (continued)
Pin No.
13
Equivalent circuit
See pin 10.
14
14
15
16
15
16
16
17
VCC
Latch
S
Q
0.2 V R
17
18
16
19
19
100 Ω
20
100 Ω
18
9
31 µA
OSC PWM3
18
19
0.5 mA
20
10
Description
I/O
OUT2:
Push-pull output.
The absolute maximum rating for the
output source current is −50 mA.
The output source current is set by the
external resistor connected to the RB2
pin.
O
GND:
Ground
OUT3:
Open-collector output.
The absolute maximum rating for the
output current is +50 mA.
O
VCC:
Power supply.
Provide the oprating supply voltage in
the range 1.8 V to 14 V.
OSC:
Connection for the capacitor and
resistor that determine the oscillator
frequency. Use a capacitor in the range
100 pF to 1 000 pF and a resistor in
the range 3 kΩ to 33 kΩ. Use an
oscillator frequency in the range
20 kHz to 1 MHz.
O
IN+3:
Noninverting input to the error
amplifier 3.
I
IN−3:
Inverting input to the error amplifier 3.
I
FB3:
Output from the error amplifier 3.
This circuit can provide a source
current of −31 µA or a sink current of
0.5 mA (minimum).
O
Voltage Regulators
AN8049SH
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
21
Description
16
21
I/O
IN−2:
Inverting input to the error amplifier 2.
I
FB2:
Output from the error amplifier 2.
This circuit can provide a source
current of −31 µA or a sink current of
0.5 mA (minimum).
O
IN−1:
Inverting input to the error amplifier 1.
I
FB1:
Output from the error amplifier 1.
This circuit can provide a source
current of −31 µA or a sink current of
0.5 mA (minimum).
O
1.5 kΩ
1.26 V
22
16
31 µA
OSC
21
1.19 V
PWM2
0.5 mA
min.
22
23
16
23
1.5 kΩ
1.26 V
24
16
31 µA
OSC
23
1.19 V
PWM1
0.5 mA
min.
24
11
AN8049SH
Voltage Regulators
■ Usage Notes
[1] Allowable power dissipation
1. Since the power dissipation (P) in this IC increases proportionally with the supply voltage, applications must be
careful to operate so that the loss does not exceed the allowable power dissipation, PD, for the package. See the PD
Ta curve.
Reference formula:
P = (VCC −VBEQ1) × ISO(OUT)1 × Du1+ (VCC −VBEQ2) × ISO(OUT)2 × Du2+VO(SAT)3 × IOUT3 × Du3+VCC × ICC
< PD
VBEQ1
: The voltage between the base and emitter of the channel 1 npn transistor
ISO(OUT)1 : The OUT1 pin output source current
(This is set by the resistor connected to the RB1 pin. When RB is 1 kΩ, ISO(OUT)1 will be 34 mA,
maximum.)
Du1
: The output 1 on-duty
VBEQ2
: The voltage between the base and emitter of the channel 2 npn transistor
ISO(OUT)2 : The OUT2 pin output source current
(This is set by the resistor connected to the RB2 pin. When RB is 1 kΩ, ISO(OUT)2 will be 34 mA,
maximum.)
Du2
: The output 2 on-duty
VO(SAT)3 : The OUT3 pin saturation voltage (0.5 V maximum when IOUT3 is 40 mA.)
IOUT3
: The OUT3 pin current (This will be {VCC − VBEQ3 − VO(SAT)3}/RO3.)
Du3
: The output 3 on-duty
ICC
: The VCC pin current
2. If the IC is shorted to ground, shorted to VCC, or inserted incorrectly, either the device itself or peripheral
components will be destroyed.
[2] Allowable VCC ripple
VCC ripple due to the switching transistor being turned on and off can cause this IC's U.V.L.O. circuit, which is
biased by VCC, to operate incorrectly, and can cause the S.C.P. capacitor charging operation to fail to start when the
output is shorted.
The figure shows the allowable range for VCC ripple. Applications should reduce VCC ripple either by inserting a
ripple filter in the VCC line or by inserting a capacitor between the IC GND and VCC pins and locating that capacitor
as close to the IC as possible.
Note that the allowable range shown here is the result of testing the IC independently, and that the allowable range
may differ depending on the actual system of the power supply circuit. Also note that this allowable range is a design
target, and is not guaranteed by testing of all samples.
Allowable VCC ripple
Ripple frequency (Hz)
10 M
Allowable range
when VCC is 3 V.
1M
100 k
Allowable range
when VCC is 10 V.
10 k
0
1
2
3
4
5
6
VCC ripple voltage VCC(AC) (V[p-p])
12
7
8
Voltage Regulators
AN8049SH
■ Usage Notes (continued)
[3] Notes on MOS drive
Since the AN8049SH channel 1 and 2 output circuits were designed to drive bipolar transistors, the following points
require care if this device is used to drive n-channel MOS transistors directly.
1. Use an n-channel MOS transistor with a low input capacitance.
VIN
VOUT
The AN8049SH is designed to drive bipolar transistors, and adopts a circuit structure that can provide a constant-current (50 mA maximum) output source current.
Furthermore, it has a sink current capacity of 80 mA maxiOUT1/2
mum. This means that designs must be concerned about
increased loss due to longer rise- and fall-times. If a probFigure 1. Output boosting circuit
lem occurs, an inverter may be inserted as shown in figure
1 to provide amplification.
2. Use an n-channel MOS transistor with a low gate-thresh-
VIN
old voltage.
Since the AN8049SH OUT1 and OUT2 pin high-level
output voltage is VCC − 1.0 V (minimum), low VT MOS
transistors with an adequately low on-resistance must be
used. Also, if a large VGS is required, one solution is to use
a transformer as shown in figure 2, and apply a voltage that
is twice the input voltage to the IC's VCC pin.
VOUT
VCC
OUT1/2
VCC ≈ 2 × VIN−VD
Figure 2. Gate drive voltage boosting
technique
■ Application Notes
[1] SSOP024-P-0300A package power dissipation
PD T a
700
658
Glass epoxy printed circuit board
(75 × 75 × t1.6 mm3)
Rth(j−a) = 152°C/W
PD = 658 mW(25°C)
Power dissipation PD (mW)
600
500
Independent IC
without a heat sink
Rth(j−a) = 273°C/W
PD = 366 mW(25°C)
400
366
300
263
200
146
100
0
0
25
50
75 85
100
125
Ambient temperature Ta (°C)
13
AN8049SH
Voltage Regulators
■ Application Notes (continued)
[2] Main characteristics
Timing capacitance Oscillator frequency
DT1 and DT2 pin voltage Maximum on-duty
1M
100
90
80
f = 190 kHz
RT = 3 kΩ
Du (%)
fOUT (Hz)
70
100k
RT = 7.5 kΩ
f = 1 MHz
60
50
40
30
20
RT = 33 kΩ
10k
10p
1n
10
0
0.2
10n
0.3
0.4
0.5
0.6
0.7
0.8
VDT (V)
CT (F)
DT3 pin voltage Maximum on-duty
fOSC Maximum output duty
(RT = 3 kΩ)
100
95
90
80
f = 190 kHz
Du3 (%)
Du1 , Du2 , Du3 (%)
90
70
f = 1 MHz
60
50
40
30
Du3
Du1 , Du2
85
80
20
10
0
0.2
0.3
0.4
0.5
0.6
0.7
75
10k
0.8
100k
1M
fOSC (Hz)
VDT3 (V)
fOSC Maximum output duty
fOSC Maximum output duty
(RT = 7.5 kΩ)
(RT = 33 kΩ)
95
95
90
90
85
Du1 , Du2 , Du3 (%)
Du1 , Du2 , Du3 (%)
Du2
Du3
Du1 , Du2
100k
fOSC (Hz)
14
Du1
85
80
80
75
10k
Du3
1M
75
10k
100k
fOSC (Hz)
1M
Voltage Regulators
AN8049SH
■ Application Notes (continued)
[2] Main characteristics (continued)
RB ISO(OUT)
RB ISI(OUT)
0
100
−10
90
80
−20
70
ISI(OUT) (mA)
ISO(OUT) (mA)
VCC = 1.8 V
−30
2.4 V
−40
−50
8V
VCC = 14 V
60
50
40
30
−60
20
−70
−80
100
14 V
8V
10
1k
10k
RB (Ω)
100k
0
100
1.8 V, 2.4 V
1k
10k
100k
RB (Ω)
15
AN8049SH
Voltage Regulators
■ Application Notes (continued)
[3] Timing charts
VCC pin voltage
waveform
1.67 V
Output short
1.26 V
S.C.P. pin
voltage
waveform
VCC
1.26 V
0V
CTL pin
voltage
waveform
FB
OSC
DT
OSC
OUT1/2 pin
voltage waveform
Totem pole circuit output
OUT3 pin
voltage waveform
Open-collector output
16
Voltage Regulators
AN8049SH
■ Application Notes (continued)
[4] Function descriptions
1. Reference voltage block
This circuit is composed of a band gap circuit, and outputs a 1.26 V (typical) reference voltage that is
temperature compensated to a precision of ±1%. This reference voltage is stabilized when the supply voltage is 1.8
V or higher. This reference voltage is used by error amplifiers 1 and 2.
2. Triangular wave generator
This circuit generates a triangular wave like a
sawtooth with a peak of 0.7 V and a trough of 0.2
V using a capacitor CT (for the time constant) and
resistor RT connected to the OSC1 pin (pin 17). The
oscillator frequency can be set to an arbitrary value
by selecting appropriate values for the external capacitor CT and resistor R T. This IC can use an
oscillator frequency in the range 20 kHz to 1 MHz.
The triangular wave signal is provided to the
noninverting input of the PWM comparator in each
channel internally to the IC. Use the formulas below for rough calculation of the oscillator frequency.
fOSC ≈ −
1
CT × RT × ln
VOSCL
VOSCH
≈ 0.8 ×
1
CT × RT
VOSCH
≈ 0.7 V
t2
t1
VOSCL
≈ 0.2 V
Discharge
Rapid charge
T
Figure 1. Triangular oscillator waveform
(Hz)
Note, however, that the above formulas do not take the rapid charge time, overshoot, and undershoot into
account. See the experimentally determined graph of the oscillator frequency vs. timing capacitance value provided in the main characteristics section.
3. Error amplifier 1
This circuit is an npn-transistor input error
amplifier that detects and amplifies the DC-DC
converter output voltage, and inputs that signal to
a PWM comparator. The 1.26 V internal reference
voltage is applied to the noninverting input. Arbitrary gain and phase compensation can be set up
by inserting a resistor and capacitor in series between the FB1 pin (pin 24) and the IN−1 pin (pin
23). The output voltage VOUT1 can be set using the
circuit shown in the figure.
FB1
24
VOUT1
R1
Error
amplifier1
23
IN−1
R2
VOUT1 = 1.26 ×
1.26 V To the PWM
comparator input
R1 + R2
R2
Figure 2. Connection method of error amplifier 1
(Step-up output)
17
AN8049SH
Voltage Regulators
■ Application Notes (continued)
[4] Function descriptions (continued)
4. Error amplifier 2
This circuit is an npn-transistor input error
amplifier that detects and amplifies the DC-DC
converter output voltage and inputs that signal to
a PWM comparator. The 1.26 V internal reference
voltage is applied to the noninverting input. Arbitrary gain and phase compensation can be set up
by inserting a resistor and capacitor in series between the FB2 pin (pin 22) and the IN−2 pin (pin
21). The output voltage VOUT2 can be set using the
circuit shown in the figure.
FB2
22
VOUT2
R1
Error
amplifier2
21
IN−2
1.26 V To the PWM
comparator input
R2
VOUT2 = 1.26 ×
R1 + R2
R2
Figure 3. Connection method of error amplifier 2 (Step-up output)
5. Error amplifier 3
This circuit is an pnp-transistor input error amplifier that detects and amplifies the DC-DC converter output
voltage and inputs that signal to a PWM comparator. Arbitrary gain and phase compensation can be set up by
inserting a resistor and capacitor in series between the FB3 pin (pin 20) and the IN−3 pin (pin 19). The output voltage
VOUT3 can be set using the circuit shown in the figure.
Step-down output
FB3
Inverting output
FB3
20
VREF VOUT3
R1
VREF
R3
IN+3
R2
R4
20
IN−3
R1
Error
amplifier3
18
19
IN+3
To the PWM
comparator input
R +R
R2
VOUT3 =
× 3 4 × VREF
R4
R1+R2
Error
amplifier3
18
19
R2
To the PWM
comparator input
IN−3
VOUT3
VOUT3 = −VREF ×
R2
R1
Figure 4. Connection method of error amplifier 3
6. Timer latch short-circuit protection circuit
This circuit protects the external main switching elements, flywheel diodes, choke coils, and other components
against degradation or destruction if an excessive load or a short circuit of the power supply output continues for
longer than a certain fixed period.
The timer latch short-circuit protection circuit detects the output of the error amplifiers. If the DC-DC converter
output voltage drops and an FB pin (pins 20, 22, or 24) voltage exceeds 0.9 V, the S.C.P. comparator outputs a low
level and the timer circuit starts. This starts charging the external protection circuit delay time capacitor.
If the error amplifier output does not return to the normal voltage range before that capacitor reaches 1.26 V,
the latch circuit latches, the output drive transistors are turned off, and the dead-time is set to 100%. (See the "[5]
Time constant setup for the timer latch short-circuit protection circuit" section later in this document.)
18
Voltage Regulators
AN8049SH
■ Application Notes (continued)
[4] Function descriptions (continued)
7. Low input voltage malfunction prevention circuit (U.V.L.O.)
This circuit protects the system against degradation or destruction due to incorrect control operation when the
power supply voltage falls during power on or power off.
The low input voltage malfunction prevention circuit detects the internal reference voltage that changes with
the supply voltage level. While the supply voltage is rising, this circuit cuts off the output drive transistor until the
reference voltage reaches 1.67 V. It also sets the dead-time to 100 % and at the same time holds the S.C.P. pin (pin
1) and the DT pins (pins 2, 3, and 4) at 0 V, and the OSC pin (pin 17) at about 1.2 V.
8. PWM comparators
The PWM comparators control the on-period of the output pulse according to their input voltage. The PWM
1 and PWM 2 comparators reverse the logic of their inputs when adjusting the on-period of their respective
output.
The output transistors are turned on during periods when the OSC pin (pin 17) triangular waveform is lower
than both of the corresponding FB pin (pins 20, 22, or 24) and the corresponding DT pin (pins 2, 3, or 4).
The maximum duty is set to 86 % internally, but can be set to a value in the range 0% to 100% by inserting a
resistor between the DT pin and ground, or the DT pin and VREF pin. (See the "[6] Setting the maximum duty"
section later in this document.)
The IC's soft start function operates to gradually increase the width of the output pulse on-period during startup
if a capacitor is inserted between the DT pin and ground. See the "[7] Setting the soft start time" section later in
this document.
9. Output 1 and output 2 blocks
These output circuits have a totem pole structure. A constant-current source output with good line regulation
can be set up freely by connecting current setting resistors to the RB pins (pins 10 and 11).
See the "[2] Main characteristics" section earlier in this document for details on the RB vs. ISO(OUT) and RB vs.
ISI(OUT) characteristics.
10. Output 3 block
This output circuit has an open collector structure.
An output current of up to 50 mA can be provided, and the output pin has a breakdown voltage of 14.2 V.
11. CTL block
This block controls the on/off state of each channel. See the "[9] Sequential operation" section later in this
document.
19
AN8049SH
Voltage Regulators
■ Application Notes (continued)
[5] Time constant setup for the timer latch short-circuit protection circuit
Figure 6 shows the structure of the timer latch short-circuit protection circuit. The short-circuit protection
comparator continuously compares a 0.9 V reference voltage with the FB1, FB2, and FB3 error amplifier outputs.
When the DC-DC converter output load conditions are stable, the short-circuit protection comparator holds its
average value since there are no fluctuations in the error amplifier outputs. At this time, the output transistor Q1 will
be in the conducting state, and the S.C.P. pin will be held at 0 V.
If the output load conditions change rapidly and a high-level signal (0.9 V or higher) is input to the short-circuit
protection comparator from the error amplifier output, the short-circuit protection comparator will output a low level
and the output transistor Q1 will shut off. Then, the capacitor CSCP connected to the S.C.P. pin will start to charge.
When the external capacitor CSCP is charged to about 1.26 V by the constant current of about 1.1 mA, the latch circuit
will latch and the dead-time will be set to 100% with the output held fixed at the low level. Once the latch circuit has
latched, the S.C.P. pin capacitor will be discharged to about 0 V, but the latch circuit will not reset unless either power
is turned off or the power supply is re-started by on/off control.
1.26 V = ICHG ×
tPE
CSCP
VSCP (V)
∴tPE (s) = 1.15 × CSCP (µF)
At power supply startup, the output appears to be
in the shorted state, and the IC starts to charge the
S.C.P. pin capacitor. Therefore, users must select an
external capacitor that allows the DC-DC converter
output voltage to rise before the latch circuit in the
later stage latches. In particular, care is required if the
soft start function is used, since that function makes
the startup time longer.
1.26
Short-circuit detection time tPE
0.06
t (s)
Figure 5. S.C.P. pin charging waveform
On/off control
Internal reference voltage
VCC
U.V.L.O
FB1
FB2
22
20
S.C.P. comp. Q1
Latch
R
Q
S
High level detection comparator
VREF
0.9 V
1
FB3
1.1 µA
24
S.C.P.
Figure 6. Short-circuit protection circuit
20
Output shutoff
Voltage Regulators
AN8049SH
■ Application Notes (continued)
[6] Setting the maximum duty
The maximum duty is set to 86% internally to the IC. However, this setting can be changed to be any value in the
range 0% to 100% by adding an external resistor.
1. To use a duty lower than the current duty (80% to 92%)
Insert the resistor RDT between the DT pin and ground.
Determine the DT pin voltage for the required duty from the provided DT pin voltage vs. maximum on-duty
characteristics in the "[2] Main characteristics" section and determine the value of the external resistor RDT from
formula A.
Note that there is a sample-to-sample variation of −19% to +33% due to temperature characteristics and sampleto-sample variations of the internal resistors R1 and R2. (However, the direction of the sample-to-sample variations is identical for R1 and R2.) Determine the size of the sample-to-sample variations in the DT pin voltage VDT
from formula B, and estimate the size of the sample-to-sample variation in the duty from the provided DT pin
voltage vs. maximum on-duty characteristics in the "[2] Main characteristics" section .
RDT =
VDT =
R1
VDT
··········A
1
VREF
1
− ( + ) × VDT
R1
R1 R2
R2/RDT
R1+R2/RDT
×VREF
··········B
VREF
1.26 V
DT
R2
RDT
ch.1, 2
ch.3
R1 45 kΩ 44 kΩ
R2 55 kΩ 56 kΩ
2. To use a duty higher than the current duty (80% to 92%)
Insert the resistor RDT between the DT pin and the VREF pin.
Use formulas C and D to determine the value of the external resistor RDT and the size of the sample-to-sample
variations in the same manner as in item 1 above.
RDT =
VDT =
VREF−VDT
1 1
VREF
( + ) × VDT −
R1 R2
R1
R2
×VREF
R2+R1/RDT
··········C
··········D
VREF
1.26 V
RDT
R1
R2
DT
21
AN8049SH
Voltage Regulators
■ Application Notes (continued)
[7] Setting the soft start time
The soft start time is determined by the value of the capacitor connected between the DT pin and ground.
OSC pin waveform
DT pin waveform
VDT
0.2 V
Soft start time, tD
Use the following formula to set the soft start time tD.
VDT
R
tD = −R2 × CDT × ln (1−
× 1)
VREF − VDT
R2
R1
VREF
1.26 V
DT
R2
22
CDT
ch.1, 2
ch.3
R1 45 kΩ 44 kΩ
R2 55 kΩ 56 kΩ
Voltage Regulators
AN8049SH
■ Application Notes (continued)
[8] Parallel synchronous operation of multiple ICs
Multiple instances of this IC can be operated in parallel. If the OSC pins (pin 17) and OFF pins (pin 8) are connected
to each other as shown in figure 7, the ICs will operate at the same frequency.
It is also possible to operate a one-channel control IC (e.g. the AN8016SH or AN8016NSH) and a two-channel
control IC (e.g. the AN8017SA or AN8018SA) in this parallel synchronous mode. In this case, short the OSC and Off
pins together.
OSC
17
IC1
17 OSC
OSC pins
connected
together
IC2
AN8049SH
AN8049SH
VREF 9
Off 8
H
VREF 9
S.C.P. 1
Off 8
S.C.P. 1
L
Off pins
connected
together
Figure 7. Synchronous parallel operation
Notes on parallel operation:
1. The remote on/off state of each individual IC cannot be controlled independently.
In this sort of circuit, always connect all the Off pins together, and control the on/off states of the multiple ICs
at the same time.
The reason for this is that if, for example, IC1 is solely turned on/off, the sawtooth wave will be stopped
temporarily and the OSC pin held fixed at about 1.2 V. As a result the IC2 OUT1 to OUT3 pins will be forced
temporarily to the full off-state and the DC-DC converter output voltage will fall.
2. All ICs are shut down when an output shorted state occurs.
For example, if the IC1 output voltage falls, its output short-circuit protection circuit will operate, and the latch
circuit will latch. When this happens, the IC1 output stops, and at the same time the sawtooth oscillator stops, and
the OSC pin is held fixed at about 1.2 V.
As a result, the IC2 OUT1 to OUT3 pins temporarily go to the full off-state, and the DC-DC converter output
voltage will drop. Finally, the IC2 output short-circuit protection circuit will operate, and the latch will go to the
latched state. This behavior will also occur if the IC2 output falls first.
23
AN8049SH
Voltage Regulators
■ Application Notes (continued)
[9] Sequential operation
Sequential operation under the control of external capacitors
Delays can be provided in the startup times by inserting capacitors (CCTL) between the CTL pins and ground.
Delay time: tDLY = 1.26 (V) × CCTL (µF)/1.1 (µA) (s)
VCTL ≈ VCC
AN8049SH
CTL1
CTL2
CTL3
CCTL3
CTL1 7
CTL2 6
CTL3 5
1.26 V
CCTL1
CCTL2
CCTL1 < CCTL2 < CCTL3
Stop
Start
Stop
Start
Stop
Start
ch.1
ch.2
ch.3
U.V.L.O. cleared
Figure 8. Sequential operation using external capacitors
24
Voltage Regulators
AN8049SH
■ Application Notes (continued)
[10] Notes on power supply printed circuit board design
Careful attention must be paid to the following points when designing the printed circuit board layout to achieve
low noise and high efficiency.
1. Use extremely wide lines for the ground lines, and isolate the IC ground from the power system ground.
In particular, during light-load operation (when the on-duty is low) switching noise can enter the system at the
lower limit of the sawtooth waveform causing the operating frequency to vary every period and resulting in
unstable control.
Take measures described as 1) and 2) below, and assure that switching noise does not appear on the sawtooth
waveform.
1) Use a ground line separate from the power system ground for the capacitor and resistor connected to the OSC
pin.
2) Lower the OSC pin impedance by either decreasing the value of the resistor RT or increasing the value of the
capacitor CT.
(See the figures below.)
VIN
The frequency changes at each period.
RT
OUT1 12
OSC 17
Small
CT
Large
VOUT
Q1
Lower limit voltage
GND of the sawtooth wave
during stable operation
Common impedance
Noise is picked up
and the IC switches
from charge to
discharge operation.
RT
OUT1 12
OSC 17
VIN
CT
VOUT
Q1
GND
(2) Modify the
values of the
capacitor and
resistor.
(1) Use separate lines.
2. Position input filter capacitors as close as possible to the VCC and ground pins.
If switching noise cannot be suppressed even with exceptionally large capacitors, or if there are limitations on
the size of capacitors that can be used, install an CR filter in the input to reduce switching noise. Problems may
occur if switching noise enters the IC by any route.
3. Keep the length of the line between the OUT pin and the switching device as short as possible to provide a clean
switching waveform to the switching device.
4. Use longer lines for the low-impedance side of the output voltage detection resistors.
25
AN8049SH
Voltage Regulators
■ Application Notes (continued)
[11] Differences between this IC and the AN8049FHN
The pin arrangements differ. The AN8049FHN is a alternative package version of this IC.
OUT2
13
12
OUT1
RB1
11
14
GND
OUT3
15
VREF
RB2
10
16
8
Off
9
17
VCC
OSC
IN+3
CTL1
7
18
IN−3
19
6
CTL3
CTL2
5
20
FB3
IN−2
DT1
4
21
FB2
22
DT2
3
23
2
DT3
S.C.P.
1
24
FB1
IN−1
AN8049SH
OUT3
13
VCC
14
OSC
15
IN+3
16
IN−3
17
8
VREF
Off
CTL1
CTL2
7
24
6
9
5
23
4
10
DT2
26
FB3
22
1
DT3
11
CTL3
S.C.P.
21
3
FB1
12
DT1
IN−1
20
2
FB2
18
19
IN−2
AN8049FHN
GND
OUT2
OUT1
RB1
RB2
Voltage Regulators
AN8049SH
■ Application Notes (continued)
[12] Error amplifier frequency characteristics
1. Error amplifiers 1 and 2
(Test circuit)
40
100 kΩ
30
1 kΩ
IN−1
100 kΩ
VOUT
FB1
Amp.1
VREF
1.26 V
2.3 V
20
Gain (dB)
10 µF
VIN
4 mV[P-P]
10
0
−10
−20
180
Phase (°)
135
90
45
0
−45
1k
10k
100k
1M
10M
100M
Frequency (Hz)
2. Error amplifier 3
(Test circuit)
40
1V
Amp.3
1 kΩ
IN+3
1 kΩ
FB3
VOUT
20
Gain (dB)
VIN
4 mV[P-P]
30
1 kΩ
IN−3
10
0
100 kΩ
−10
10 µF
−20
0
−45
Phase (°)
10 µF
−90
−135
−180
−225
1k
10k
100k
1M
10M
100M
Frequency (Hz)
27
AN8049SH
Voltage Regulators
23 kΩ
100 Ω
10 kΩ 10 kΩ
14 kΩ
Step-down
VOUT1
3.3 V
300 mA
Q1
10 µF
12 kΩ
125.1 kΩ
Step-up
VOUT2
13.3 V
300 mA
0.033 µF
13 kΩ
VREF
1 kΩ
Input
Q2 10 µF
100 pF
2.2 kΩ
Q3
10 µF
150 kΩ
Inverting
VOUT3
−15 V
10 mA
■ Application Circuit Example
100 pF
13
GND 14
10 µF
470 pF
0.12 µF
OUT3 15
7.5 kΩ
11 RB1
9.1 kΩ
10 RB2
1 kΩ
9 VREF
OSC 17
0.12 µF
8 Off
IN+3 18
7 CTL1
IN−3 19
6 CTL2
FB3 20
5 CTL3
IN−2 21
4 DT1
1 MΩ
FB2 22
3 DT2
IN−1 23
2 DT3
1 MΩ
0.01 µF
0.01 µF
OUT1
VCC 16
0.01 µF
28
12
FB1 24
On/Off
OUT2
0.12 µF
0.12 µF
0.12 µF
1 S.C.P.