Datasheet RAA23040x 3-ch Step-Down Switching Regulator + 1-ch LDO R18DS0004EJ0102 Rev.1.02 Jul.09, 2013 Description The RAA23040x is a power supply IC that has 3-ch step-down Switching Regulator containing power MOSFETs and 1-ch LDO. Features • Switching Regulator (ch1, ch3, ch4) Synchronous rectification type step-down circuit Integrated power MOSFETs Internal phase compensator Power good function (ch1) Low power mode (ch1, ch3 and ch4 operate at low frequency and reduce the power consumption of the IC.) Switching frequency: 1.3 MHz to 2 MHz (variable) Internal timer-latch-type short-circuit protector • LDO (ch2) Internal over current protector (foldback-current limiting) • Common part Independent On/Off control for each channel Internal digital soft-start function (adjustable soft-start time) Internal discharge circuit Internal timer-latch-type thermal shutdown circuit (shutdown temperature: 150°C or higher) Internal recovery-type under voltage lockout circuit PKG and Packing Part No. RAA23040xGNP RAA23040xGFT R18DS0004EJ0102 Rev. 1.02 Jul.09, 2013 Package 32-pin VQFN 32-pin TQFP Packing Embossed taping. 4,000pcs/reel Tray. 1,250pcs/Inner box Page 1 of 26 Product Lineup Table The following 9 products are developed based on output voltage. ch RAA230401 RAA230402 RAA230403 RAA230404 RAA230405 RAA230406 RAA230407 RAA230408 RAA230409 1 1.8 V 2.5 V 3.0 V 3.3 V 1.8 V 2.5 V 3.0 V 3.3 V Adjustable 2 3 3.3 V 4 Adjustable Output voltage is selectable. 1.2 V preset voltage by internal resistor or adjustable by external resistor. Note: ch1, ch2: RAA230401 to RAA230408 output preset voltage by internal resistor. RAA230409 outputs adjustable voltage by external resistor. ch3: RAA230401 to RAA230404 output preset voltage by internal resistor. RAA230405 to RAA230409 output adjustable voltage by external resistor. ch4: All products have switchable output voltage between 1.2 V preset voltage by internal resistor and adjustable voltage by external resistor. Constitution Example • Input Voltage: 2.5 V to 5.5 V ch 1 2 3 4 Type Synchronous rectification type step-down circuit (Current mode) LDO Synchronous rectification type step-down circuit (Current mode) Synchronous rectification type step-down circuit (Current mode) R18DS0004EJ0102 Rev. 1.02 Jul.09, 2013 Power MOSFET Integrated Output Voltage 0.9 V to VIN × 0.8 V Maximum Output Current Example 500 mA — Integrated 0.9 V to VIN × 0.8 V 0.9 V to VIN × 0.8 V 100 mA 1500 mA Integrated 0.9 V to VIN × 0.8 V 1500 mA Page 2 of 26 Application Circuit Example ch1 to ch3: Preset output voltage by internal resistor. ch4: Preset output voltage by internal resistor is selected. (CTL4 = H) RT Control-IC SCP Short-Circuit Protection Circuit SCP SHDNB0 SHDNB1 SHDNB2 SHDNB3 SHDNB4 VREF Control Circuit Thermal Shutdown Circuit TSD • ON/OFF • Soft Start • Discharge VREG AGND Internal Power Supply VREG AVDD Reference Voltage VREF Input voltage Under Voltage Lockout Circuit UVLO TEST1 Oscillator OSC SAVE VREG TEST Circuit AVDD TEST2 CTL4 SS VPIN1 ch1 OUT E/A1 II1 0.8V + + – Output Control (Current mode /current limit) PGND1 Phase Compensator Discharge Control PG1 VPIN2 Control LDO II2 VPIN3 II3 E/A3 0.8V + + – Output Control (Current mode /current limit) 1.8V 2.5V 3.0V 3.3V ch2 OUT OUT2 Discharge Control ch3 OUT ch1 OUT LOUT1 1.8V 2.5V 3.0V 3.3V ch3 OUT LOUT3 PGND3 3.3V Phase Compensator Discharge Control VPIN4 ch4 OUT E/A4 II4 0.8V + + – Output Control (Current mode /current limit) ch4 OUT LOUT4 PGND4 1.2V Phase Compensator Discharge Control R18DS0004EJ0102 Rev. 1.02 Jul.09, 2013 Page 3 of 26 ch1 to ch3: Adjustable output voltage by external resistor. ch4: Adjustable output voltage by external resistor is selected. (CTL4 = L) RT Control-IC SCP Short-Circuit Protection Circuit SCP SHDNB0 SHDNB1 SHDNB2 SHDNB3 SHDNB4 VREF Control Circuit Thermal Shutdown Circuit TSD • ON/OFF • Soft Start • Discharge VREG AGND Internal Power Supply VREG AVDD Reference Voltage VREF Input voltage Under Voltage Lockout Circuit UVLO TEST1 Oscillator OSC SAVE VREG TEST Circuit AVDD TEST2 CTL4 SS VPIN1 ch1 OUT E/A1 II1 0.8V + + – Output Control (Current mode /current limit) ch1 OUT LOUT1 PGND1 0.9V~AVDD Phase Compensator Discharge Control PG1 VPIN2 Control LDO Discharge Control II2 VPIN3 ch3 OUT E/A3 II3 0.8V + + – Output Control (Current mode /current limit) ch2 OUT OUT2 0.9V~ AVDD-0.5V ch3 OUT LOUT3 PGND3 0.9V~AVDD Phase Compensator ch4 OUT Discharge Control VPIN4 E/A4 II4 0.8V + + – Output Control (Current mode /current limit) ch4 OUT LOUT4 PGND4 0.9V~AVDD Phase Compensator Discharge Control R18DS0004EJ0102 Rev. 1.02 Jul.09, 2013 Page 4 of 26 Pin Configuration LOUT3 VPIN3 PGND3 II3 II4 PGND4 VPIN4 LOUT4 32-pin VQFN 24 23 22 21 20 19 18 17 SHDNB4 25 16 TEST1 SHDNB3 26 15 VREG SAVE 27 14 TEST2 SS 28 13 AGND RT 29 SHDNB2 30 12 AVDD 11 VREF SHDNB1 31 10 OUT2 SHDNB0 32 9 5 6 LOUT1 VPIN1 PGND1 II1 PG1 CTL4 7 8 LOUT3 4 II2 3 SCP 2 VPIN3 1 VPIN2 (Top view) PGND3 II3 II4 VPIN4 LOUT4 PGND4 32-pin TQFP 24 23 22 21 20 19 18 17 SHBND4 25 16 TEST1 SHBND3 26 15 VREG SAVE 27 14 TEST2 SS 28 13 AGND RT 29 12 AVDD SHBND2 30 11 VREF SHBND1 31 10 OUT2 SHBND0 32 9 VPIN2 Exposed PAD 4 5 6 7 8 PG1 CTL4 SCP II2 VPIN1 LOUT1 3 II1 2 PGND1 1 (Top view) R18DS0004EJ0102 Rev. 1.02 Jul.09, 2013 Page 5 of 26 Pin Function Pin No. 1 Symbol LOUT1 I/O Output Inductor connection for ch1 2 3 4 5 VPIN1 PGND1 II1 PG1 Power supply Ground Input Output Output stage power input of ch1 Power ground Inverted input for error amplifier of ch1 Power-good output of ch1 (open-drain) 6 7 8 9 CTL4 SCP II2 VPIN2 Input — Input Power supply Output voltage setting mode of ch4 Capacitor connection pin for timer latch Inverted input for error amplifier of ch2 Output stage power input of ch2 10 11 12 13 OUT2 VREF AVDD AGND Output Output Power supply Ground Output of ch2 Reference voltage output Analog block power supply Analog ground 14 15 16 17 TEST2 VREG TEST1 LOUT3 — Output — Output Test pin 2 (connect to VREG) Internal power supply output Test pin 1 (connect to AGND) Inductor connection for ch3 18 19 20 21 VPIN3 PGND3 II3 II4 Power supply Ground Input Input Output stage power input of ch3 Power ground Inverted input for error amplifier of ch3 Inverted input for error amplifier of ch4 22 23 24 25 PGND4 VPIN4 LOUT4 SHDNB4 Ground Power supply Output Input Power ground Output stage power input of ch4 Inductor connection for ch4 Output ON/OFF of ch4 26 27 28 29 SHDNB3 SAVE SS RT Input Input — — Output ON/OFF of ch3 Low power operation mode setting pin Resistance connection for soft start time setting Resistance connection for triangular wave generation 30 31 32 SHDNB2 SHDNB1 SHDNB0 Input Input Input Output ON/OFF of ch2 Output ON/OFF of ch1 Output ON/OFF of IC R18DS0004EJ0102 Rev. 1.02 Jul.09, 2013 Function Page 6 of 26 Absolute Maximum Ratings (Unless otherwise specified, TA = 25°C) Parameter Analog power supply (AVDD pin) VPIN pin applied voltage SHDNB pin applied voltage CTL4 pin applied voltage SAVE pin applied voltage PG pin applied voltage II pin applied voltage VPIN1 pin sink current (peak) VPIN2 pin sink current (DC) VPIN3 pin sink current (peak) VPIN4 pin sink current (peak) LOUT1 pin output source current (peak) OUT2 pin output source current (DC) LOUT3 pin output source current (peak) LOUT4 pin output source current (peak) LOUT1, OUT2, LOUT3, LOUT4 pin output source current (DC) Symbol AVDD VPIN VSHDNB VCTL4 VSAVE VPG VII IPIN1(peak)– IPIN2(DC)– IPIN3(peak)– IPIN4(peak)– ILO1(peak)+ IO2(DC)+ ILO3(peak)+ ILO4(peak)+ ILO1,O2,LO3,4(DC)– Total power dissipation PT Operating ambient temperature Junction temperature TA TJ Ratings –0.5 to +6.5 –0.5 to +6.5 –0.5 to +6.5 –0.5 to +6.5 –0.5 to +6.5 –0.5 to +6.5 –0.5 to +6.5 600 200 2000 2000 600 200 2000 2000 100 *1 VQFN: 1850 TQFP: 21001 –40 to +85 –40 to +150 Unit V V V V V V V mA mA mA mA mA mA mA mA mA mW Condition AVDD VPIN1 to VPIN4 SHDNB0 to SHDNB4 CTL4 SAVE PG1 II1 to II4 VPIN1 VPIN2 VPIN3 VPIN4 LOUT1 OUT2 LOUT3 LOUT4 when discharge circuit is operation. TA ≤ +25°C °C °C Storage temperature Tstg –55 to +150 °C Note: *1 This is the value at TA ≤ +25°C. At TA > +25°C, the total power dissipation is derated by –18.5 mW/°C (VQFN) or -21mW/°C (LQFP). Board specification: VQFN:4-layers glass epoxy board. 76.2mm x 114.3mm x 1.664mm. Copper coverage area: 50% (top and bottom layers)/95% ( layers 2 and 3). TQFP:4-layers glass epoxy board. 80mm x 80mm x 1.6mm. Renesas Evaluation Board for the case of that Exposed PAD is not soldered to GND copper pattern on board. Caution: Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. R18DS0004EJ0102 Rev. 1.02 Jul.09, 2013 Page 7 of 26 Recommended Operating Condition (Unless otherwise specified, TA = 25°C) Parameter Analog power supply voltage (AVDD pin) VPIN pin applied voltage SHDNB pin applied voltage CTL4 pin applied voltage SAVE pin applied voltage PG pin applied voltage II pin applied voltage Oscillation frequency Oscillator timing resistance Soft start resistance SCP pin capacitance VREF pin capacitance VREG pin capacitance Operating junction temperature R18DS0004EJ0102 Rev. 1.02 Jul.09, 2013 Symbol AVDD Min 2.5 Typ 5.0 Max 5.5 Unit V VPIN VSHDNB VCTL4 VSAVE VPG VII fOSC RT RSS CSCP CREF CREG TJO — 0 0 0 0 0 1300 — — — — — –40 AVDD — — — — — — 10 1000 0.1 1.0 1.0 — — AVDD AVDD AVDD AVDD AVDD 2200 — — — — — +125 V V V V V V kHz kΩ kΩ µF µF µF °C Condition AVDD VPIN1 to VPIN4 SHDNB0 to SHDNB4 CTL4 SAVE PG1 II1 to II4 RT SS SCP VREF VREG Page 8 of 26 Electrical Characteristics (Unless otherwise specified, TA = 25°C, AVDD = VPIN1 to VPIN4 = 5.0 V, fOSC = 2 MHz) Parameter Total Standby current Symbol IDD(STNBY) Min Typ Max Unit — 1 2 µA Condition AIDD+IPIN1+IPIN2+IPIN3+IPIN4 SHDNB0 to SHDNB4 = AGND Circuit operation current 1 IDD1 — 1.2 2 mA AIDD, SHDNB0 = AVDD SHDNB1 to SHDNB4 = AGND SAVE = GND Circuit operation current 2 IDD2 — 0.7 1.0 mA AIDD, SHDNB0 = AVDD SHDNB1 to SHDNB4 = AGND SAVE = AVDD Reference Reference voltage voltage Temperature characteristic VREF 0.98 1.00 1.02 V IREF = 0mA — 0.5 — % TA = –10°C to +60°C VREG 2.3 2.4 2.5 V IREG = 0mA AVDD(L-H) 1.9 2.1 2.3 V AVDD pin voltage is detected block (VREF) Internal Internal power supply power voltage supply block (VREG) Under Operation start voltage voltage lock during rise time out circuit Operation stop voltage AVDD(H-L) 1.7 1.9 2.1 V AVDD pin voltage is detected Short-circuit II1 input detection voltage VTH(II)1 65 75 85 % II1 pin, Ratio to the output voltage protection (ch1) circuit (SCP) II3 input detection voltage VTH(II)3 65 75 85 % II3 pin, Ratio to the output voltage VTH(II)4 65 75 85 % II4 pin, Ratio to the output voltage VTH(DLY) 0.6 0.9 1.2 V SCP pin µA (UVLO) (ch3) II4 input detection voltage (ch4) DLY detection voltage Short-circuit source current IOUT 0.6 1.0 1.4 Oscillation Frequency setting accuracy fOSC –10 — +10 % RT = 10kΩ block Input stability ∆fOSC –3 — +3 % AVDD = 2.5V to 5.5V Soft start Soft start time tss — 2.0 4.0 ms ch1 to ch4, RSS = 1000kΩ block PWM block Maximum duty DMAX.(PWM) — 100 — % ch1, ch3, ch4 Output ch1 output voltage accuracy VOUT1 –2 — +2 % IO1 = 10mA, (with internal resistor) voltage ch2 output voltage accuracy VOUT2 –1 — +1 % IO2 = 10mA, (with internal resistor) accuracy ch3 output voltage accuracy VOUT3 –2 — +2 % IO3 = 200mA, (with internal resistor) ch4 output voltage accuracy VOUT4 –2 — +2 % IO4 = 200mA, (with internal resistor) E/A block E/A 1 input threshold VITH1 0.784 0.800 0.816 V (with resistor voltage outside) E/A 2 input threshold (with resistor inside) VITH2 0.792 0.800 0.808 V voltage E/A 3 input threshold VITH3 0.784 0.800 0.816 V VITH4 0.784 0.800 0.816 V Including input offset, (with external resistor) Ron-p1 — 0.4 0.6 Ω IO = 100mA N-ch output ON resistance Ron-n1 — 0.4 0.6 Ω IO = –100mA P-ch output ON resistance Ron-p1 — 0.4 0.6 Ω IO = 100mA N-ch output ON resistance Ron-n1 — 0.4 0.6 Ω IO = –100mA Discharging Output ON resistance1 Rondc1 — 100 200 Ω ch1, ch3, ch4, IDC = 20mA circuit block Output ON resistance2 Rondc2 — 200 400 Ω ch2, IDC = 20mA (ch1) Output block (ch3, ch4) P-ch output ON resistance Including input offset, (with external resistor) voltage Output block Including input offset, (with external resistor) voltage E/A 4 input threshold Including input offset, (with external resistor) R18DS0004EJ0102 Rev. 1.02 Jul.09, 2013 Page 9 of 26 Electrical Characteristics (cont.) (Unless otherwise specified, TA = 25°C, AVDD = VPIN1 to VPIN4 = 5.0 V, fOSC = 2 MHz) Parameter Series The voltage between the regulator input and output block (ch2) Input regulation Power-good Symbol Min Typ Max Unit Condition VDIF2 0.5 — — V REGIN2 — — 50 mV IO2 = 20mA, VPIN2 > VOUT2+0.5V IO2 = 20mA Load regulation REGL2 — — 50 mV IO2 = 1mA to 100mA Output short-circuit current IO2short — 80 — mA OUT2=AGND Peak output current IO2peak 150 — — mA T.B.D. Threshold voltage VTH(PG)1 86 90 94 % circuit block PG1 = "HiZ"→"L", "L"→"HiZ" Detection of II1 pin (ch1) Ratio to the output voltage PG pin output voltage VPG — — 0.1 V IPG– = 0.1mA PG pin leakage current ILEAK-PG — — 1 µA SHDNB0 to SHDNB4 = AGND Delay time tDLY-PG — — 2 ms Time from detecting of output startup until change form L to HiZ on PG pin ON/OFF Threshold voltage VTH 0.8 — 2.0 V SHDNB0 to SHDNB4, SAVE controller Input pull-down resistance RIND 200 400 700 kΩ SHDNB0 to SHDNB4, SAVE block R18DS0004EJ0102 Rev. 1.02 Jul.09, 2013 Page 10 of 26 Typical Performance Characteristics (Unless otherwise specified, TA = 25°C, AVDD = VPIN1 to VPIN4 = 5.0 V, fOSC = 2 MHz) Efficiency vs. Output Current ch1 Efficiency VOUT1 = 3.3V 2MHz ch3 Efficiency VOUT3 = 3.3V 2MHz SAVE(0.3MHz) SAVE(0.3MHz) ch3 Efficiency VOUT3 = 2.5V ch4 Efficiency VOUT4 = 1.2V 2MHz 2MHz SAVE(0.3MHz) SAVE(0.3MHz) R18DS0004EJ0102 Rev. 1.02 Jul.09, 2013 Page 11 of 26 Start-up waveforms Example 1 ch1(3.3V) ->ch2(3.3V) ->ch3(2.5V) ->ch4(1.2V) Configuration Example 2 Waveform ch1(1.2V) ->ch2(1.2V) ->ch3(1.2V) ->ch4(1.2V) Configuration Waveform SHDNB pins have pull-down resistors (400kΩ). Please make sure that input voltage divided by external resistor on SHDNB pins shall not be lower than 1.4V. R18DS0004EJ0102 Rev. 1.02 Jul.09, 2013 Page 12 of 26 IC Surface Temperature vs. Time • • • • • All channel operating (normal mode) VIN=5V ch1: 3.3 V, 0.5 A ch2: 3.3 V, 0.1A ch3: 3.3 V, 1.5 A ch4: 1.2 V, 1.5 A TA=25°C Measured on Renesas Evaluation board IC Surface Temperature vs. Time Temperature (ºC) 90 80 VQFN 70 TQFP 60 50 40 30 20 10 0 0 5 10 15 20 25 30 Time (min.) Temperature Derating Curve 2250 2000 TQFP VQFN 1750 PT (W) 1500 1250 1000 750 500 250 0 0 R18DS0004EJ0102 Rev. 1.02 Jul.09, 2013 25 50 TA ( °C) 75 100 125 Page 13 of 26 Load Transient Waveforms ch1 normal mode, Vout1 = 3.3V L1 = 4.7µH, Cin1 = 10µF, Cout1 = 22µF Vout1 200mV/Div. ch2, Vout2 = 3.3V Cin2 = 10µF, Cout2 = 2.2µF Vout2 100mV/Div. Iout1 = 500mA Iout1 200mA/Div. Iout2 = 100mA Iout2 50mA/Div. Iout1 = 10mA Iout2 = 0mA 500µs/Div. 100µs/Div. ch3 normal mode, Vout3 = 3.3V L3 = 2.2µH, Cin3 = 10µF, Cout3 = 22µF ch3 normal mode, Vout3 = 2.5V L3 = 2.2µH, Cin3 = 10µF, Cout3 = 22µF Vout3 200mV/Div. Vout3 200mV/Div. Iout3 = 1500mA Iout3 500mA/Div. Iout3 = 1500mA Iout3 500mA/Div. Iout3 = 10mA 100µs/Div. Iout3 = 10mA 100µs/Div. ch4 normal mode, Vout4 = 1.2V L4 = 2.2uH, Cin4 = 10uF, Cout4 = 22uF Vout4 100mV/Div. Iout4 = 1500mA Iout4 500mA/Div. Iout4 = 10mA 100µs/Div. R18DS0004EJ0102 Rev. 1.02 Jul.09, 2013 Page 14 of 26 Control Block SHDNB0 to SHDNB4: ON/OFF Setting SHDNB0 L SHDNB1 L or H SHDNB2 L or H SHDNB3 L or H SHDNB4 L or H Common Circuit OFF ch1 OFF ch2 OFF ch3 OFF ch4 OFF H H H H L H L L L L H L L L L H L L L L ON ON ON ON OFF ON OFF OFF OFF OFF ON OFF OFF OFF OFF ON OFF OFF OFF OFF H H L H L H L H H H ON ON OFF ON OFF ON OFF ON ON ON Note: L: Low level, H: High level Common Circuit: Reference voltage block, internal power supply block, oscillator block and so forth OFF: circuit stand-by, ON: circuit operation status SAVE: IC Low Power Mode Setting SAVE L IC Operation Normal operation (ch1, ch3, ch4 operate at oscillation frequency set by RT) H Note: Low power mode operation (ch1, ch3, ch4 operate at 15% oscillation frequency of normal operation) L: Low level, H: High level CTL4: ch4 Output Voltage Setting CTL4 L H Note: ch4 Output Voltage Setting External resistor setting Internal resistor setting (fixed 1.2 V) L: Low level, H: High level R18DS0004EJ0102 Rev. 1.02 Jul.09, 2013 Page 15 of 26 Output Status VREG, VREF Pin Status SHDNB0 L H L: Low level, H: High level Note: VREG AGND VREF AGND 2.4 V 1.0 V ch1 to ch4 Output Pin Status SHDNB0 L SHDNB1 to SHDNB4 L or H ch1 LOUT1 HiZ (Discharge circuit, OFF) ch2 OUT2 AGND (Discharge circuit, ON) H L PGND (Discharge circuit, ON) Pulse (VPIN1 or PGND) AGND (Discharge circuit, ON) ch2 (set voltage) H Note: ch3 LOUT3 ch4 LOUT4 HiZ (Discharge circuit, OFF) PGND (Discharge circuit, ON) Pulse Pulse (VPIN3 or PGND) (VPIN4 or PGND) L: Low level, H: High level, HiZ: High impedance PG1 Pin Status SHDNB0 = H Note: IC Operation Status SHDNB0 = L The ch1 output voltage is under 90% of the set voltage The ch1 output voltage is over 90% of the set voltage L: Low level, HiZ: High impedance PG1 Output Status HiZ L HiZ Caution: When using power good (PG1 pin), connect it to ch1 output. R18DS0004EJ0102 Rev. 1.02 Jul.09, 2013 Page 16 of 26 Timing Chart • Input AVDD SHDNB0 SHDNB1 SHDNB2 SHDNB3 SHDNB4 • Output 2.4 V VREG 1.0 V VREF 90% ch1 OUT PG1 (Open) PG1 (Connect to ch1 OUT) 90% HiZ HiZ HiZ HiZ ch1 OUT ch2 OUT ch3 OUT ch4 OUT The output voltage of each channel can be turned on/off individually. R18DS0004EJ0102 Rev. 1.02 Jul.09, 2013 When SHDNB0 is set to OFF, the discharge circuit doesn't operate. (Naturally discharge) Page 17 of 26 Operation of Each Block (Overview) Short-Circuit Protection Circuit (ch1, ch3 and ch4) When the voltage of ch1, ch3 and ch4 drops, the voltage of the E/A inverted input pin to which the output is being fed back also drops. If this inverted input pin voltage falls below the input detection voltage of the short-circuit protection circuit (under 75% of output voltage), the timer circuit starts operating and the capacitor connected to the SCP pin (CSCP) starts charging. When the voltage of the capacitor connected to the SCP pin reaches 0.9 V (TYP.), all the outputs are latched to OFF. At this time, common circuits (such as the reference voltage block, internal power supply block, and oscillator, etc.) continue operating. As long as the voltage of any of the E/A inverted input pins of ch1 to ch4 is below the input detection voltage of the short-circuit protection circuit, the capacitor connected to the SCP pin continues charging. When the short-circuit protection circuit is operating, to reset the latch circuit, either change the level of the SHDNB0 pin from high to low or drop the level of the power supply voltage (AVDD) to the level below the operation stop voltage of the under voltage lockout circuit (1.7 V to 2.1 V). • Timing Chart (when ch1 is short circuited) SHDNB0 SHDNB1 II1 SCP The input detection voltage 0.9V (1) (2) (3) (1) (1) At starting A short circuit will not be detected while a channel is undergoing a soft start (that is, short-circuit protection is not triggered). If a short circuit occurs while a channel is operating, short-circuit protection will start after the soft start time elapses following startup. If a short circuit occurs in a channel that is operating while another channel is being soft-started, short-circuit protection will start immediately. (2) Short-circuit protection operation If a short circuit is detected in any of channel 1, 3 and 4 (channels whose II pin voltage is lower than the input detection voltage except channels that are being soft-started), the capacitor connected to the SCP pin starts charging. If short circuits occur in multiple channels, the capacitor connected to the SCP pin continues to charge until the short-circuit state of all channels is canceled (that is, until the II pin voltage is restored over the input detection voltage). Once the SCP pin voltage reaches 0.9 V, output from all channels stops (and is latched to OFF). Common circuits (such as the reference voltage block, internal power supply block, and oscillator, etc.) continue operating. (3) Cancelling short-circuit protection To reset the latch circuit, either change the level of the SHDNB0 pin from high to low, or drop the level of the power supply voltage (AVDD) to the operation stop voltage of the under voltage lockout circuit (1.7 V to 2.1 V). R18DS0004EJ0102 Rev. 1.02 Jul.09, 2013 Page 18 of 26 Thermal Shutdown Circuit (Timer Latch Type) After overheating has been detected (shutdown temperature: 150°C or higher), the timer circuit starts operating and the capacitor connected to the SCP pin (CSCP) starts charging. When the voltage of the capacitor connected to the SCP pin reaches 0.9 V (TYP.), all the outputs are latched to OFF (as same as SCP). Common circuits (such as the reference voltage block, internal power supply block, and oscillator, etc.) continue operating. When the thermal shutdown circuit is operating, to reset the latch circuit, either change the level of the SHDNB0 pin from high to low, or drop the level of the power supply voltage (AVDD) to the operation stop voltage of the under voltage lockout circuit (1.7 V to 2.1 V). Under Voltage Lockout Circuit (Auto Recovery Type) (1) Under voltage lockout operation When the power supply voltage (AVDD) falls to the operation stop voltage (1.7 V to 2.1 V), output from all channels stops. Common circuits (such as the reference voltage block, internal power supply block, and oscillator, etc.) continue operating. (2) Restoring output Once AVDD voltage is restored to the operation start voltage (1.9 V to 2.3 V), the under voltage lockout operation is canceled and output automatically resumes. The output voltage cannot be restored while the under voltage lockout circuit is operating, not even by manipulating the SHDNB0 pin. Current Limiting Ch1, ch3, and ch4 operate under the current control mode. If an overcurrent occurs, the current is limited on a pulse-bypulse basis. If the current sensor detects an overcurrent, the current is limited and the switching operation of the Power MOSFET in the output stage stops until the next cycle. When the current is limited, the output voltage of the channel on which the overcurrent occurred drops. If the II pin voltage falls below the input detection voltage, the short-circuit protection circuit starts operating. Reference data (Unless otherwise specified, TA = 25°C, AVDD = VPIN1 to VPIN4 = 5.0 V, fOSC = 2 MHz) Item Symbol Min Typ Max unit Measurement condition Current limit ch1 Current limet ILIM1 — 1.6 — A ch1OUT = 3.3V value ch3, ch4 Current limet 1 ILIM34_1 — 2.6 — A ch3OUT = ch4OUT = 3.3V ch3, ch4 Current limet 2 ILIM34_2 — 2.1 — A ch3OUT = ch4OUT = 1.2V Note: These data are for reference and not guaranteed as specifications. Over Current Protection (ch2) Ch2 have a fold back type current protection circuit. If load current exceeds 150 mA, protection operation is started and load current is limited (output short-circuit current: 80 mA). Low Power Mode This IC has the low power mode. By setting SAVE pin into a high level, the oscillation frequency of a switching regulator (ch1, ch3, ch4) is dropped on 15% oscillation frequency of normal operation, and the power consumption of the IC is reduced. When switching to the low power mode, please switch the mode in a condition that the output current of a switching regulator (ch1, ch3, ch4) is below 100 mA. Please be cautious of increasing the ripple voltage of each channel at the low power mode. R18DS0004EJ0102 Rev. 1.02 Jul.09, 2013 Page 19 of 26 Advance on Designing Setting Output Voltage (When the output voltage is set by external resistor) The output voltage settings are shown in the figures below. The output voltage can be calculated by using the equations shown in these figures. [Setting output voltage of ch1 to ch4 by external resistor] VOUT = (1+R1/R2) × 0.8 VOUT (Output voltage) R1 E/A1, E/A2, E/A3, E/A4 – R2 + 0.8V(TYP.) Setting Oscillation Frequency The oscillation frequency (fOSC) can be arbitrarily set by the timing resistance (RT) connected to the RT pin. Approximate equation: f OSC[MHz] = –0.107 × RT[kΩ] + 3.05 Calculating the Soft Start Time The soft start time (tSS) can be arbitrarily set by the resistance (RSS) connected to the SS pin. Approximate equation: tSS[ms] = 1.8 × RSS[MΩ] + 0.24 Note: Soft start time is the same by all channels. Calculating the Delay Time of the Short-circuit Protection Circuit The following approximate expression is for calculating the delay time tDLY of the short-circuit protection circuit. The delay time of the short-circuit protection circuit (tDLY) can be arbitrarily set by the capacitor (CSCP) connected to the SCP pin. Approximate equation: tDLY[s] = 0.9 × CSCP [µF] Pin handling when Short-circuit Protection Circuit is not used When the short-circuit protection circuit is not used, connect the SCP pin to the AGND pin. At this time, closely monitor heating because the overheat protection circuit does not operate. R18DS0004EJ0102 Rev. 1.02 Jul.09, 2013 Page 20 of 26 Handling of pins when not used Connect unused pins as below. Always connect AVDD pin, VPIN1 pin, VPIN2 pin, VPIN3 pin and VPIN4 pin with power supplies, and connect PGND1 pin, PGND3 pin, PGND4 pin and AGND with the ground. When ch1 is not used:. Pin number 31 Pin name SHDNB1 Connection AGND 2 1 3 4 VPIN1 LOUT1 PGND1 II1 AVDD, or VPIN of other ch PGND PGND AGND Pin number 30 9 10 Pin name SHDNB2 VPIN2 OUT2 Connection AGND AVDD, or VPIN of other ch AGND 8 II2 AGND Pin number 26 Pin name SHDNB3 Connection AGND 18 17 19 20 VPIN3 LOUT3 PGND3 II3 AVDD, or VPIN of other ch PGND PGND AGND Pin number 25 23 24 Pin name SHDNB4 VPIN4 LOUT4 Connection AGND AVDD, or VPIN of other ch PGND 22 21 6 PGND4 II4 CTL4 PGND AGND AGND Pin number Pin name Connection 5 PG1 AGND When ch2 is not used: When ch3 is not used: When ch4 is not used: When PG1 pin is not used R18DS0004EJ0102 Rev. 1.02 Jul.09, 2013 Page 21 of 26 Inductor selection It is recommended to choose a inductor which ripple current (∆IL) becomes 20 to 40 % of Iout(max). When ∆IL increases, inductor current peak raises, so ripple of Vout gets larger and power loss increases. But, large inductor is required to lower ∆IL. ∆IL can be calculated by an equation below. ∆IL = (Vin-Vout) / L x Vout / Vin x 1 / fsw fsw : Switching frequency of DCDC, 1.3MHz to 2MHz Peak current of inductor (ILpeak) can be calculated by an equation below. ILpeak = Iout(max) + ∆IL / 2 Choose a inductor which saturation current is higher than ILpeak . Inductor Example ch Output Current Inductor Manufacturer Inductance ITEMP (A) ISAT (A) (uH) ch1 ch3 less than 0.5A less than 1A ch4 1A to 1.5A Size (LxWxT, mm) CPL2512T4R7M TDK 4.7 0.65 0.65 2.5x1.5x1.2 NRS2012T4R7MGJ TAIYO YUDEN 4.7 0.82 0.76 2x2x1.2 74479787247A WURTH 4.7 1.5 0.27 2.5x2x1 744028004 WURTH 4.7 0.85 0.7 2.8x2.8x1.1 VLS201612ET-2R2M TDK 2.2 1.15 1.05 2x1.6x1.2 NRS2012T2R2MGJ TAIYO YUDEN 2.2 1.37 1.35 2x2x1.2 744029002 WURTH 2.2 1.5 1.15 2.8x2.8x1.35 LQH44PN2R2MP0 MURATA 2.2 1.8 2.5 4x4x1.65 NRS4018T2R2MDGJ TAIYO YUDEN 2.2 2.2 3 4x4x1.8 744025002 WURTH 2.2 1.8 2.4 2.8x2.8x2.8 Note ITEMP : Rated current by temperature rising ISAT : Rated current by inductance loss These inductors are examples. About inductor detail, contact each manufacturer. R18DS0004EJ0102 Rev. 1.02 Jul.09, 2013 Page 22 of 26 Output capacitor selection Each channel of RAA23040x has a phase compensation circuit which is optimized to each operation. In order to operate stably with the phase compensation, connect the output capacitor : Switching Regulator (ch1, ch3, ch4) : over 22uF LDO (ch2) : over 2.2uF Ceramic capacitor can be used for output capacitor. It has low ESR, so VOUT ripple is decreased. VOUT ripple (∆Vrpl) can be calculated by an equation below. ∆Vrpl = ∆IL x (ESR + 1 / (8 x Cout x fsw )) Input capacitor selection Recommended input capacitor of switching regulator can be calculated by an equation below. Connect the capacitor that value is over calculated one. Cin > (Iout(max) x Vout / Vin) / (∆Vin x fsw) About LDO, connect the capacitor that value is over 1uF. R18DS0004EJ0102 Rev. 1.02 Jul.09, 2013 Page 23 of 26 Notes on Use Condition where Protection Circuits do not operate When the SCP pin is connected to the AGND pin, the short-circuit protection circuit and thermal shutdown circuit do not operate. Pin Connection Be sure to apply the same voltage to AVDD pin and VPIN pin (except VPIN2). VPIN2 Input Voltage VPIN2 input voltage should be same or less than AVDD. PG1 Connection When using power good (PG1 pin), connect it to ch1 output. If PG1 is connected to AVDD, PG1 outputs high (AVDD) when SHDNB0 is low (because PG1 is high impedance when SHDNB0 is low). Actual Pattern Wiring To actually perform pattern wiring, separate the ground of the control signals from the ground of the power signals, so that these signals do not have a common impedance as much as possible. In addition, lower the high-frequency impedance by using a capacitor, so that noise is not superimposed on the VREF pin, VREG pin. Connection of Exposed PAD (only TQFP package) TQFP package has an exposed pad on the bottom to improve radiation performance. On the mounting board, connect this exposed pad to AGND. Fixed Usage of Control Input Pin When using fixed input pins SHDNB0 to SHDNB4, CTL4 and SAVE input pins, connect each input to the pins listed below. Connect Pin Input Pin SHDNB0 Fixed to Low Level AGND Fixed to High Level AVDD SHDNB1 SHDNB2 SHDNB3 SHDNB4 AGND AGND AGND AGND AVDD AVDD AVDD AVDD CTL4 SAVE AGND AGND AVDD AVDD R18DS0004EJ0102 Rev. 1.02 Jul.09, 2013 Page 24 of 26 Package Dimensions 32-pin VQFN 5 mm × 5 mm 0.4 mm pitch JEITA Package Code P-VQFN32-5x5-0.40 RENESAS Code PVQN0032LA-A Previous Code MASS[Typ.] 0.05g HD D A 17 e 24 25 16 E HE B Reference Symbol ZE LP 9 32 1 8 ZD 4x t b b1 S A B A1 y S R18DS0004EJ0102 Rev. 1.02 Jul.09, 2013 A A2 c c1 y1 S S M S AB D E A2 A A1 b b1 e Lp x y y1 t HD HE ZD ZE c c1 Dimension in Millimeters Min Nom 5.0 5.0 0.89 0.005 0.13 0.02 0.18 0.16 0.4 0.60 0.50 0.17 5.2 5.2 1.1 1.1 0.22 0.20 Max 0.95 0.04 0.23 0.70 0.05 0.05 0.2 0.2 0.25 Page 25 of 26 32-pin TQFP 7 mm × 7 mm 0.8 mm pitch R18DS0004EJ0102 Rev. 1.02 Jul.09, 2013 Page 26 of 26 Revision History Rev. 1.01 1.02 Date Oct 18, 2012 Jul 09, 2013 RAA23040x Data Sheet Description Summary Page 1 5 7 21 22 23 24 First Edition issued Changed package name from LQFP to TQFP. Added packing unit. Added Pin Configuration of 32-pin TQFP. Added Total power dissipation and Board specification. Changed Short-circuit source current from Min 0.7uA to 0.6uA and Max 1.3uA to 1.4uA. Changed Output short-circuit current from Typ 40mA to 80mA. Added condition of Input regulation, Load regulation and Output short-circuit current. Added start-up waveforms. Added input voltage VIN condition. Changed output voltage/current condition. Added TQFP product’s data. Added Temperature Derating Curve. Changed Output Pin Status of ch2 at SHDNB0=L from HiZ to GND. Added Reference data of Current limit value. Changed Output short-circuit current of Over Current Protection (ch2) from Typ 40mA to 80mA. Added Handling of pins when not use. Added Inductor selection Added Output capacitor selection and Input capacitor selection. Added Connection of Exposed PAD. 26 Added Package Dimensions of TQFP package. 9 10 12 13 16 19 All trademarks and registered trademarks are the property of their respective owners. C-1 NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). (2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. (4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. (5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. (6) INPUT OF SIGNAL DURING POWER OFF STATE: Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pullup power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Notice 1. 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