DATA SHEET BiCMOS INTEGRATED CIRCUIT µ PC1934 DC-DC CONVERTER CONTROL IC DESCRIPTION The µ PC1934 is an IC that controls a low-voltage input DC-DC converter. This IC is suitable for an operation with 3-V, 3.3-V input or a lithium ion secondary battery input, because the minimum operation supply voltage is 2.5 V. Because of its wide operating voltage range, it can also be used to control DC-DC converters that use an AC adapter for input. FEATURES • Low supply voltage: 2.5 V (MIN.) • Operating voltage range: 2.5 to 20 V (breakdown voltage: 30 V) • Timer latch circuit for short-circuit protection. • Ceramic capacitor with low capacitance (0.1 µ F) can be used for short-circuit protection. • Open drain outputs (Each of the outputs can be used to control a step-down converter, a step-up converter and an inverted converter.) • Can control two output channels. ORDERING INFORMATION Part Number Package µ PC1934GR-1JG 16-pin plastic SSOP (5.72 mm (225)) µ PC1934GR-PJG 16-pin plastic TSSOP (5.72 mm (225)) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. G13567EJ3V0DS00 (3rd edition) Date Published April 2000 NS CP (K) Printed in Japan The mark ★ shows major revised points. 1998 µ PC1934 BLOCK DIAGRAM Channel 2 VREF DLY IN2 II2 FB2 DTC2 OUT2 VCC 16 15 14 13 12 11 10 9 MOS output Reference voltage section – Timer latch for short-circuit protection section – – + + E/A2 PWM2 MOS input MOS input MOS output + – – + Oscillation section – E/A1 PWM1 1 2 3 4 5 6 7 8 CT RT IN1 II1 FB1 DTC1 OUT1 GND Channel 1 2 Data Sheet G13567EJ3V0DS00 µ PC1934 PIN CONFIGURATION (Top View) 16-pin plastic SSOP (5.72 mm (225)) • µ PC1934GR-1JG 16-pin plastic TSSOP (5.72 mm (225)) • µ PC1934GR-PJG CT 1 16 VREF RT 2 15 DLY IN1 3 14 IN2 II1 4 13 II2 FB1 5 12 FB2 DTC1 6 11 DTC2 OUT1 7 10 OUT2 GND 8 9 VCC PIN FUNCTIONS Pin No. Symbol Function Pin No. Symbol Function 1 CT Frequency setting capacitor connection 9 VCC Power supply 2 RT Frequency setting resistor connection 10 OUT2 Channel 2 open drain output 3 IN1 Channel 1 error amplifier non-inverted 11 DTC2 Channel 2 dead time setting input 4 II1 Channel 1 error amplifier inverted input 12 FB2 Channel 2 error amplifier output 5 FB1 Channel 1 error amplifier output 13 II2 Channel 2 error amplifier inverted input 6 DTC1 Channel 1 dead time setting 14 IN2 Channel 2 error amplifier non-inverted input 7 OUT1 Channel 1 open drain output 15 DLY Delay capacitor connection of shortcircuit protection 8 GND Ground 16 VREF Data Sheet G13567EJ3V0DS00 Reference voltage output 3 µ PC1934 CONTENTS 1. ELECTRICAL SPECIFICATIONS ................................................................................................................ 5 2. CONFIGURATION AND OPERATION OF EACH BLOCK.................................................................... 10 2.1 Reference Voltage Generator ...........................................................................................................................10 2.2 Oscillator ...........................................................................................................................................................10 2.3 Under Voltage Lock-out Circuit ........................................................................................................................11 2.4 Error Amplifiers.................................................................................................................................................11 2.5 PWM Comparators............................................................................................................................................11 2.6 Timer Latch-Method Short Circuit Protection Circuit ....................................................................................11 2.7 Output Circuit....................................................................................................................................................11 3. NOTES ON USE........................................................................................................................................ 12 3.1 Setting the Output Voltage ...............................................................................................................................12 3.2 Setting the Oscillation Frequency ...................................................................................................................13 3.3 Preventing Malfunction of the Timer Latch-Method Short Circuit Protection Circuit..................................13 3.4 Connecting Unused Error Amplifiers ..............................................................................................................13 3.5 ON/OFF Control.................................................................................................................................................14 3.6 Notes on Actual Pattern Wiring........................................................................................................................14 4. APPLICATION EXAMPLE ......................................................................................................................... 15 4.1 Application Example.........................................................................................................................................15 4.2 List of External Parts ........................................................................................................................................15 5. PACKAGE DRAWINGS.............................................................................................................................. 16 6. RECOMMENDED SOLDERING CONDITIONS ....................................................................................... 18 4 Data Sheet G13567EJ3V0DS00 µ PC1934 1. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (unless otherwise specified, TA = 25 °C) Parameter Symbol µ PC1934GR-1JG µ PC1934GR-PJG Unit Supply voltage VCC 30 V Output voltage VO 30 V Output current (open drain output) IO 21 mA Total power dissipation PT Operating ambient temperature TA –20 to + 85 °C Storage temperature Tstg –55 to + 150 °C Caution 417 400 mW Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Conditions Parameter Symbol MIN. TYP. MAX. Unit Supply voltage VCC 2.5 20 V Output voltage VO 0 20 V Output current IO 20 mA Operating temperature TA −20 +85 °C Oscillation frequency fOSC 20 1000 kHz Caution The recommended operating range may be exceeded without causing any problems provided that the absolute maximum ratings are not exceeded. However, if the device is operated in a way that exceeds the recommended operating conditions, the margin between the actual conditions of use and the absolute maximum ratings is small, and therefore thorough evaluation is necessary. The recommended operating conditions do not imply that the device can be used with all values at their maximum values. Data Sheet G13567EJ3V0DS00 5 µ PC1934 Electrical Characteristics (unless otherwise specified, TA = 25 °C, VCC = 3 V, fOSC = 100 kHz) Block Parameter Symbol Conditions MIN. TYP. MAX. Unit Under Start-up voltage VCC (L-H) IREF = 0.1 mA 1.57 V voltage Operation stop voltage VCC (H-L) IREF = 0.1 mA 1.5 V Lock-out Hysteresis voltage VH IREF = 0.1 mA 70 mV Reset voltage (timer latch) VCCR IREF = 0.1 mA 1.0 V Reference Reference voltage VREF IREF = 1 mA Voltage Line regulation REGIN section Load regulation section 30 2.1 2.2 V 2.5 V≤VCC≤20 V 2 12.5 mV REGL 0.1 mA≤IREF≤1 mA 2 7.5 mV Temperature coefficient ∆VREF/∆T −20 °C≤TA≤+85 °C, IREF = 0 A Oscillation fOSC setting accuracy ∆fOSC RT = 11 kΩ, CT = 330 pF −15 +15 % section fOSC total stability ∆fOSC −20 °C≤TA≤+85 °C, −30 +30 % 1.0 µA 2.5 2.0 V≤VCC≤20 0.5 % V Dead time Input bias current IBD 0.4 control Low-level threshold voltage VTH (L) Duty = 100 % 1.2 V section High-level threshold voltage VTH (H) Duty = 0 % 1.6 V Error Input offset voltage VIO −10 +10 mV Amplifier Input offset current IIO −100 +100 nA section Input bias current IB −100 +100 nA Common mode input voltage range VIMC 0 0.4 V Open loop gain Av Unity gain funity VO = 0.3 V VO = 0.3 V + VOM Maximum output voltage (+) 70 − IO = −45 µ A 1.6 80 dB 1.5 MHz 2 V Maximum output voltage (−) VOM IO = 45 µ A Output sink current IOsink VFB = 0.5 V Output source current IOsource VFB = 1.6 V Output Drain cutoff current ILEAK VO = 30 V section Output ON voltage VOL RL = 150 Ω 0.2 Rise time tr RL = 150 Ω 50 ns Fall time tf RL = 150 Ω 60 ns Short-circuit Input sense voltage VTH 0.5 0.63 0.75 V Protection UV sense voltage VUV 0.6 0.8 0.95 V section Source current on short-circuiting IOUV 1.0 1.6 2.5 µA Delay time tDLY CDLY = 0.1 µ F Circuit operation current ICC VCC = 3 V Overall 0.02 0.8 CREF = 0.01 to 10 µF 8 6 Data Sheet G13567EJ3V0DS00 2.2 V mA −45 µA 100 µA 0.6 V 50 1.4 16 µ PC1934 1.4 −70 Caution Connect a capacitor of 0.01 to 10 µ F to the VREF pin. 0.5 ms 3.7 mA Timing Charts Channel 1 soft start Normal operation Short-load Stop output DTC1 Channel 1 CT FB1 VTH OUT1 Data Sheet G13567EJ3V0DS00 ON OFF DTC2 Channel 2 CT FB2 OUT2 ON OFF DLY VUV circuit protection circuit starts operation by detecting a short- load of channel 2. 7 µ PC1934 Remark These timings are an example when the channel 1 output has been a short- load. The outputs of channel 1 and 2 are also stopped when a short- µ PC1934 Typical Characteristic Curves (unless otherwise specified, VCC = 3 V, fOSC = 100 kHz, TA = 25 °C) (Nominal) PT vs TA VREF vs VCC 2.5 IREF = 0 A Reference voltage VREF (V) Total power dissipation PT (W) 0.5 0.4 µ PC1934GR-1JG 300 °C/W 0.3 0.2 µ PC1934GR-PJG 312.5 °C/W 0.1 0 2.0 1.5 1.0 0.5 25 50 75 100 125 150 Operating ambient temperature TA (°C) 0 1 2 3 4 Supply voltage VCC (V) 5 fOSC vs RT VREF vs TA 1000 2.13 Oscillation frequency fOSC (kHz) Reference voltage VREF (V) IREF = 0 A 2.12 2.11 2.10 2.09 2.08 CT = 150 pF 100 CT = 330 pF 10 CT = 1500 pF 2.07 –25 0 25 50 75 100 Operating ambient temperature TA (°C) 1 10 100 Timing resistance RT (kΩ) 8 VOL vs TA 6 4 0.5 CT = 330 pF RT = 10 kΩ IO = 20 mA Output ON voltage VOL (V) Oscillation frequency accuracy ∆fOSC (%) ∆fOSC vs TA 1000 2 0 –2 –4 –6 –25 0 25 50 75 100 Operating ambient temperature TA (°C) 0.4 0.3 0.2 0.1 0 –25 0 25 50 75 100 Operating ambient temperature TA (°C) Data Sheet G13567EJ3V0DS00 Short-circuit protection circuit delay time tDLY (ms) µ PC1934 VOL vs IO Output ON voltage VOL (V) 0.5 0.4 0.3 0.2 0.1 0 4 8 12 16 Output current IO (mA) 20 tDLY vs CDLY 600 500 400 300 200 100 0 0.2 0.4 0.6 0.8 1.0 DLY pin capacitor capacitance CDLY ( µ F) ICC vs VCC 80 135 φ 60 40 90 45 Av 20 0 –20 0 –20 100 1k 10 k 100 k 1 M Frequency f (Hz) –90 10 M 4 Circuit operation ICC (mA) 180 Phase φ (deg) Gain Av (dB) Av, φ vs f 100 3 2 1 0 Data Sheet G13567EJ3V0DS00 5 10 15 20 25 Supply voltage VCC (V) 30 9 µ PC1934 2. CONFIGURATION AND OPERATION OF EACH BLOCK Figure 2-1 Block Diagram Oscillation section DTC1 6 FB1 5 II1 4 IN1 3 DTC2 11 FB2 12 II2 13 IN2 14 16 VCC 9 7 OUT1 10 OUT2 8 GND Error amplifier Output section Reference voltage section Under voltage lock-out section S Q1 Q Q2 0.63 V Q Timer latch for short-circuit protection section 15 CDLY 2.1 CT Output section PWM comparator SCP comparator DLY RT 1 Error amplifier PWM comparator VREF 2 Reference Voltage Generator The reference voltage generator is comprised of a band-gap reference circuit, and outputs a temperature-compensated reference voltage (2.1 V). The reference voltage can be used as the power supply for internal circuits, or as a reference voltage, and can also be accessed externally via the VREF pin (pin 16). 2.2 Oscillator The oscillator self-oscillates if a timing resistor is attached to the RT pin (pin 2). Also, the oscillator outputs the symmetrical triangular waveform if a timing capacitor is attached to the CT pin (pin 1). This oscillator waveform is input to the non-inverted input pins of the two PWM comparators to determine the oscillation frequency. 10 Data Sheet G13567EJ3V0DS00 µ PC1934 2.3 Under Voltage Lock-out Circuit The under voltage lock-out circuit prevents malfunctioning of the internal circuits when the supply voltage is low, such as when the supply voltage is first applied, or when the power supply is interrupted. When the voltage is low, the two output transistors are cut off at the same time. 2.4 Error Amplifiers The circuits of the error amplifiers E/A1 and E/A2 are exactly the same. The first stage of the error amplifier is a Pchannel MOS transistor input. Be careful of the input voltage ranges (the common mode input voltage ranges are all 0 to 0.4 V (TYP.)). 2.5 PWM Comparators The output ON duty is controlled according to the outputs of the error amplifiers and the voltage input to the Dead Time Control pin. A triangular waveform is input to the non-inverted pin, and the error amplifier output and Dead Time Control pin voltage are input to the inverted pins of the PWM comparators. Therefore, the output transistor ON period is the period when the triangular waveform is higher than the error amplifier output and Dead Time Control pin voltage (refer to Timing Charts). 2.6 Timer Latch-Method Short Circuit Protection Circuit When the converter outputs either a channel or both channels drop, the FB outputs of the error amplifiers of those outputs go low. If the FB output goes lower than the timer latch input detection voltage (VTH = 0.63 V)), then the output of the SCP comparator goes low, and Q1 goes off. When Q1 turns OFF, the constant-current supply charges CDLY via the DLY pin. The DLY pin is internally connected to a flip-flop. When the DLY pin voltage reaches the UV detection voltage (VUV = 0.8 V (TYP.)), the output Q of the flip-flop goes low, and the output stage of each channel is latched to OFF (refer to Figure 2-1 Block Diagram). Make the power supply voltage briefly less than the reset voltage (VCCR, 1.0 V TYP.) to reset the latch circuit when the short-circuit protection circuit has operated. 2.7 Output Circuit The output circuit has an N-channel open-drain output providing an output withstand voltage of 30 V (absolute maximum rating), and an output current of 21 mA (absolute maximum rating). Data Sheet G13567EJ3V0DS00 11 µ PC1934 3. NOTES ON USE 3.1 Setting the Output Voltage Figure 3-1 illustrates the method of setting the output voltage. The output voltage is obtained using the formula shown in the figure. The common mode input voltage range of the error amplifier is 0 to 0.4 V (TYP.) for both the error amplifiers, E/A1 and E/A2. Therefore, select a resistor value that gives this voltage range. Figure 3-1 Setting the Output Voltage (1) When setting a positive output voltage using error amplifier E/A1. VOUT (positive voltage) R1 R4 VOUT = 1 + R1 • • VREF R2 R3 + R 4 16 VREF 4 CNF R3 E/A1 R2 3 R4 RNF 5 (2) When setting a negative output voltage using error amplifier E/A2. 16 VREF R1 13 R2 R3 CNF E/A2 14 R4 RNF 12 VOUT (negative voltage) 12 VOUT = R1R4−R2R3 • VREF R1 (R3+R4) Data Sheet G13567EJ3V0DS00 µ PC1934 3.2 Setting the Oscillation Frequency Choose RT according to the oscillation frequency (fOSC) vs timing resistor (CT, RT) characteristics (refer To Typical Characteristics Curves fOSC vs CT, RT). The formula below (3-1) gives an approximation of fOSC. However, the result of formula 3-1 is only an approximation, and the value must be confirmed in actual operation, especially for high-frequency operation. fOSC [Hz] ≅ 0.375/(CT [F] x RT [Ω]) (3-1) 3.3 Preventing Malfunction of the Timer Latch-Method Short Circuit Protection Circuit The timer latch short-circuit protection circuit operates when the error amplifier outputs (pin 5 and 12) goes below approximately 0.63 V, and cuts off the output. However, if the rise of the power supply voltage is fast, or if there is noise on the DLY pin (pin 15), the latch circuit may malfunction and cut the output off. To prevent this, lower the wiring impedance between the DLY pin and the GND pin (pin 8), and avoid applying noise to the DLY pin. 3.4 Connecting Unused Error Amplifiers When one of the two control circuits is used, connect the circuit so that the output of the error amplifier of unused circuit is high. Figure 3-2 shows examples of how to connect unused error amplifiers. Figure 3-2 Examples of Connecting Unused Error Amplifiers (1) Error amplifier E/A1 16 VREF 3 E/A1 4 5 6 DTC1 (2) Error amplifier E/A2 16 VREF 14 E/A2 13 12 11 DTC2 Data Sheet G13567EJ3V0DS00 13 µ PC1934 3.5 ON/OFF Control The ON/OFF control method of the output oscillation is to input the ON/OFF signal from ON as shown in Figure 3-3. The PWM converter can be turned ON/OFF by controlling the level of the DTC pin. However, it is necessary to keep the level of the FB output high so that the timer latch does not start when the PWM converter is OFF. In this circuit example, the FB output level is controlled by controlling the level of the II pin. Figure 3-3 ON/OFF Control VO VREF FB R5 R1 SCP comparator (common to each channel) II – + + R2 Q3 IN Error 0.3 V amplifier R6 Q – CDLY 0.63 V VREF Q2 DLY To output stage – – + R3 PWM comparator C1 DTC ON Q1 Oscillation section (common to each channel) R4 (1) When ON is high: OFF status Q1: ON → Q2: ON → DTC pin: High level → Output duty of PWM comparator: 0 % Q3: ON → II pin: Low level → FB output: High level → SCP comparator output: High level → Q is ON. → Timer latch stops. (2) When ON3 is low: ON status Q1: OFF → Q2 is OFF. → C1 is charged in the sequence of [VREF → C1 → R4] → DTC pin voltage drops. → Soft start Q3: OFF → II pin: High level → FB output: Low level → SCP comparator output: Low level → Q: OFF → Charging CDLY starts (timer latch start). Caution Keep the high-level voltage of the DTC pin at 1.6 V or higher and the low-level voltage of the II pin within (R6/(R5+R6))••VREF. The maximum voltage that is applied to the II pin must be equal to or lower than VREF. 3.6 Notes on Actual Pattern Wiring When actually carrying out the pattern wiring, it is necessary to separate control-related grounds and power-related grounds, and make sure that they do not share impedances as far as possible. In addition, make sure the high-frequency impedance is lowered using capacitors and other components to prevent noise input to the VREF pin. 14 Data Sheet G13567EJ3V0DS00 µ PC1934 4. APPLICATION EXAMPLE 4.1 Application Example Figure 4-1 shows an example circuit for obtaining ±5 V/50 mA from a +3 V power supply. Figure 4-1 Chopper-Method Step-up/Inverting-Type Switching Regulator VIN = 3 V COM C1 1 µ F C2 10 µ F R28 15 kΩ R24 2 kΩ R27 5 kΩ D21 R23 12 kΩ C21 R26 1 µ F 10 kΩ C23 3300 pF CDLY R25 12 kΩ 0.1 µ F 16 R29 510 Ω 15 14 13 12 11 10 9 VREF DLY IN2 II2 FB2 DTC2 OUT2 VCC R210 470 Ω CH2 VO = +5.0 V L11 100 µ H R111 100 Ω R212 10 Ω Q23 R21 IO = 50 mA 47 kΩ Q23 R211 24 kΩ Q23 R214 10 kΩ C23 100 pF C24 68 µ F R22 5 kΩ GND C11 0.1 µ F µ PC1934 D11 Q13 CT 1 CT 100 pF RT IN1 2 3 II1 4 FB1 DTC1 OUT1 GND 5 R18 12 kΩ R18 2 kΩ R18 12 kΩ 6 7 L11 100 µ H R19 80 Ω Q12 R111 10 Ω R15 12 kΩ CH1 VO = −5.0 V IO = 50 mA Q11 R113 10 kΩ R112 20 Ω 8 C23 3300 pF RT 5.1 kΩ R111 470 Ω C113 100 pF C14 68 µ F R12 20 kΩ GND R17 5 kΩ R16 10 kΩ R11 5.1 kΩ C11 1 µ F 4.2 List of External Parts The list below shows the external parts. Table 4-1 List of External Parts Symbol Parameter Function Part number Maker Remark C2 10 µ F Input stable capacitor 25SC10M SANYO OS-CON, SC series C14 68 µ F Output capacitor 20SA68M SANYO OS-CON, SA series Schottkey diode D1FS4 SHINDENGEN Choke inductor 636FY-101M TOKO D73F series Transistor array D11 L11 100 µ H Q11, Q12 Buffer transistor µ PA609T NEC Q13 Switching transistor 2SB1572 NEC Output capacitor 20SA68M SANYO Schottkey diode D1FS4 SHINDENGEN C21 68 µ F D21 L21 100 µ H OS-CON, SA series Choke inductor 636FY-101M TOKO D73F series Q21, Q22 Buffer transistor µ PA609T NEC Transistor array Q23 Switching transistor 2SD2403 NEC Remarks 1. The capacitors that are not specified in the above list are multilayer ceramic capacitors. 2. The resistors that are not specified in the above list are 1/4W resistors. Data Sheet G13567EJ3V0DS00 15 µ PC1934 5. PACKAGE DRAWINGS 16-PIN PLASTIC SSOP (5.72 mm (225)) 16 9 detail of lead end P 1 8 A H F G I J S C D M N L B S K M E NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. ITEM A MILLIMETERS 5.2±0.3 B 0.475 MAX. C 0.65 (T.P.) D 0.22±0.8 E 0.125±0.075 F 1.565±0.235 G 1.44 H 6.2±0.3 I 4.4±0.2 J 0.9±0.2 K 0.17 +0.08 −0.07 L 0.5±0.2 M N 0.10 0.10 P 5°±5° P16GM-65-225B-4 16 Data Sheet G13567EJ3V0DS00 µ PC1934 16-PIN PLASTIC TSSOP (5.72 mm (225)) 9 16 detail of lead end F G R P S 8 1 L E A H A' I J S C D M M K N S B NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. ITEM A MILLIMETERS 5.15±0.15 A' B 5.0±0.1 0.375 MAX. C 0.65 (T.P.) D 0.24 +0.06 −0.04 E 0.09 +0.06 −0.04 F 1.01 +0.09 −0.06 G 0.92 H 6.4±0.2 I 4.4±0.1 J 1.0±0.2 K 0.145+0.055 −0.045 L 0.5 M 0.10 N 0.10 P 3° +5° −3° R 0.25 S 0.6±0.15 S16GR-65-PJG-1 Data Sheet G13567EJ3V0DS00 17 µ PC1934 6. RECOMMENDED SOLDERING CONDITIONS Recommended solder conditions for this product are described below. For details on recommended soldering conditions, refer to Information Document “Semiconductor Device Mounting Technology Manual” (C10535E). For soldering methods and conditions other than those recommended, consult NEC. Surface Mount Type µ PC1934GR-1JG: 16-pin plastic SSOP (5.72 mm (225)) µ PC1934GR-PJG: 16-pin plastic TSSOP (5.72 mm (225)) Soldering Method Soldering Conditions Symbol of Recommended Conditions Infrared reflow Package peak temperature: 235 °C, Time: 30 seconds MAX. (210 °C MIN.), IR35-00-3 Number of times: 3 MAX. VPS Package peak temperature: 215 °C, Time: 40 seconds MAX. (200 °C MIN.), Wave soldering Soldering bath temperature: 260 °C MAX., Time: 10 seconds MAX., VP15-00-3 Number of times: 3 MAX. Number of times: 1, Preheating temperature: 120 °C MAX. (package surface temperature) Caution Do not use two or more soldering methods in combination. 18 Data Sheet G13567EJ3V0DS00 WS60-00-1 µ PC1934 NOTES FOR BiCMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS Note: No connection for device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. Input levels of devices must be fixed high or low by using a pull-up or pulldown circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF BiCMOS DEVICES Note: Power-on does not necessarily define initial status of device. Production process of BiCMOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet G13567EJ3V0DS00 19 µ PC1934 [MEMO] • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. • NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98. 8