HI3256 TM Data Sheet June 1999 File Number 4642.1 8-Bit, 120MSPS, Flash A/D Converter Features The HI3256 is an 8-bit, high-speed, flash analog-to-digital converter optimized for high speed, low power, and ease of use. With a 120MSPS encode rate capability and full-power analog bandwidth of 250MHz, this component is ideal for applications requiring the highest possible dynamic performance. • Differential Linearity Error. . . . . . . . . . . . . . . . . . ±0.5 LSB • Integral Linearity Error . . . . . . . . . . . . . . . . . . . . ±0.5 LSB • Low Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . 10pF • Wide Analog Input Bandwidth . . . . . . . . . . . . . . . 250MHz • Low Power Consumption . . . . . . . . . . . . . . . . . . . 500mW To minimize system cost and power dissipation, only a +5V power supply is required. The HI3256 clock input interfaces directly to TTL, ECL or PECL logic and will operate with singleended inputs. The user may select 16-bit demultiplexed output or 8-bit single channel digital outputs. The demultiplexed mode interleaves the data through two 8-bit channels at 1/2 the clock rate. Operation in demultiplexed mode reduces the speed and cost of external digital interfaces, while allowing the A/D converter to be clocked to the full 120MSPS conversion rate. • Output Voltage Control Function (VOCLP pin) • 1:2 Demultiplexed Output Pin • Internal 1/2 Frequency Divider Circuit (w/Reset Function) • CLK/2 Clock Output • Compatible with PECL, ECL and TTL Digital Input Levels • Direct Replacement for Sony CXA3256R Fabricated with an advanced Bipolar process, the HI3256 is provided in a space-saving 48-lead LQFP surface mount plastic package and is specified over the -20oC to 75oC temperature range. Applications • LCD/PDP Monitors and Projectors (RGB Video) • Digital Oscilloscopes Ordering Information 48 Ld LQFP • Magnetic Recording (PRML) PKG. NO. Q48.7x7-S Pinout PBD4 PBD7 PBD6 PBD5 DVCC2 DGND2 CLKOUT DVEE3 1 48 47 46 45 44 43 42 41 40 39 38 37 36 VRB AGND VRM1 2 3 35 34 PBD2 4 5 33 32 31 PBD0 DGND2 DVCC2 30 29 DVCC1 PBD3 PBD1 DGND1 PAD7 PAD6 PAD5 PAD4 PAD3 PAD2 DGND2 PAD0 PAD1 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 CLK/E DGND3 28 27 PS VRM3 AGND VRT 8 9 10 CLK/T SELECT2 AVCC 6 7 CLKN/E AVCC VIN VRM2 3-1 RESETN/T RESETN/E RESET/E HI3256 (LQFP) TOP VIEW DVCC2 -20 to 75 PACKAGE VOCLP HI3256JCQ TEMP. RANGE (oC) SELECT1 INV PART NUMBER • Digital Communications (QPSK, QAM) CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 HI3256 Block Diagram AVCC 5 8 INV DVCC1 44 30 DVCC2 DGND3 19 31 42 12 VRT 11 R1 R/2 R/2 (MSB) 40 PBD7 1 R 39 PBD6 2 6 BITS 38 PBD5 9 (8 BITS) R 64 37 PBD4 TTLOUT 63 VRM3 LATCHA R 36 PBD3 R 35 PBD2 65 6 BITS R 6-BIT LATCH AND ENCODER 34 PBD1 126 127 VRM2 7 VIN 6 R 128 ENCODER R R 129 33 P1D0 (LSB) 8 BITS (MSB) 28 PAD7 6 BITS R 27 PAD6 191 4 R 26 PAD5 LATCHB 192 R 193 TTLOUT VRM1 25 PAD4 24 PAD3 6 BITS R 23 PAD2 254 R 22 PAD1 255 R/2 VRB 2 CLK/T 15 CLK/E 13 CLKN/E 14 21 PAD0 (LSB) R/2 DELAY 16 SELECT2 17 VOCLP 18 PS D Q 43 CLKOUT SELECT1 RESETN/T 46 RESETN/E 48 RESET/E 47 Q 3 10 AGND 3-2 45 29 SELECT1 DGND1 20 32 41 DGND2 1 DVEE3 HI3256 Absolute Maximum Ratings TA = 25oC Thermal Information Supply Voltage (AVCC , DVCC1, DVCC2) . . . . . . . . . . -0.5V to +7.0V (DGND3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V (DVEE3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -7.0V to +0.5V (DGND3 - DVEE3) . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V Analog Input Voltage (VIN). . . . . . . . . . . . . . . . . VRT - 2.7V to AVCC Reference Input Voltage (VRT). . . . . . . . . . . . . . . . . +2.7V to AVCC (VRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VIN - 2.7V to AVCC (|VRT - VRB|) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.5V Digital Input Voltage PECL/ECL . . . . . . . . . . . . . . . . . . . DVEE3 - 0.5 to DGND3 + 0.5 TTL . . . . . . . . . . . . . . . . . . . . . . . . . DGND3 - 0.5 to DVCC1 + 0.5 VID (|***/E - ***N/E| (Note 2)) . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V Thermal Resistance (Typical, Note 1) θJA (oC/W) LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (Lead Tips Only) Recommended Operating Conditions WITH A SINGLE POWER SUPPLY MIN TYP MAX Supply Voltage DVCC1 , DVCC2 , AVCC . . . . . . . . . . . . . . . +4.75 +5.0 +5.25V DGND1, DGND2, AGND . . . . . . . . . . . . . -0.05 0 +0.05V DGND3. . . . . . . . . . . . . . . . . . . . . . . . . . . +4.75 +5.0 +5.25V DVEE3 . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05 0 +0.05V Analog Input Voltage (VIN). . . . . . . . . . . . . . VRB VRT Reference Input Voltage VRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.9 +4.1V VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.4 +2.6V |VRT - VRB|. . . . . . . . . . . . . . . . . . . . . . . . +1.5 +2.1V Digital Input Voltage PECL (***/E) VIH . . . . . . . . . . . . . . DVEE3 + 1.5 DGND3 PECL (***/E) VIL . . . . . . . . . . . . . . . DVEE3 + 1.1 VIH - 0.4V TTL (***/T, INV) VIH . . . . . . . . . . . . . . . . . +2.0V TTL (***/T, INV) VIL . . . . . . . . . . . . . . . . . +0.8V Other (SELECT1/2) VIH . . . . . . . . . . . . . . DVCC1 Other (SELECT1/2) VIL . . . . . . . . . . . . . . DGND1 VID (Note 2) (|***/E- ***N/E|) . . . . . . . . . . +0.4 +0.8 Max Conversion Rate (fC, Straight Mode) . . . 100 MSPS Max Conversion Rate (fC, DMUX Mode) . . . . 120 MSPS Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . -20oC to 75oC WITH DUAL POWER SUPPLIES MIN TYP MAX Supply Voltage DVCC1 , DVCC2 , AVCC . . . . . . . . . . . . . . . +4.75 +5.0 +5.25V DGND1, DGND2, AGND . . . . . . . . . . . . . -0.05 0 +0.05V DGND3. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05 0 +0.05V DVEE3 . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.5 -5.0 -4.75V Analog Input Voltage (VIN). . . . . . . . . . . . . . VRB VRT Reference Input Voltage VRT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.9 +4.1V VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.4 +2.6V |VRT - VRB|. . . . . . . . . . . . . . . . . . . . . . . . +1.5 +2.1V Digital Input Voltage PECL/ECL VIH . . . . . . . . . . . . . . . . . . . . . . . DVEE3 + 1.5 DGND3 PECL/ECL VIL . . . . . . . . . . . . . . . . . . . . . . . DVEE3 + 1.1 VIH - 0.4 TTL (***/T, INV) VIH . . . . . . . . . . . . . . . . . 2.0 TTL (***/T, INV) VIL . . . . . . . . . . . . . . . . . +0.8V Other (SELECT1/2) VIH . . . . . . . . . . . . . . DVCC1 Other (SELECT1/2) VIL . . . . . . . . . . . . . . DGND1 VID (Note 2) (|***/E- ***N/E|) . . . . . . . . . . +0.4 0.8 Max Conversion Rate (fC, Straight Mode) . . . 100 MSPS Max Conversion Rate (fC, DMUX Mode) . . . . 120 MSPS Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . -20oC to 75oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured with the component mounted on an evaluation PC board in free air. 2. VID : Input Voltage Differential. Electrical Specifications PARAMETER DVCC1 , 2 , AVCC, DGND3 = +5V, DGND1, 2, AGND, DVEE3 = 0V, VRT = 4V, VRB = 2V, TA = 25oC TEST CONDITIONS Resolution MIN TYP MAX UNITS - 8 - Bits - - ±0.5 LSB - - ±0.5 LSB DC CHARACTERISTICS Integral Linearity Error, INL VIN = 2VP-P , fC = 5MSPS Differential Linearity Error, DNL ANALOG INPUT Analog Input Capacitance, CIN - 10 - pF Analog Input Resistance, RIN 7 20 40 kΩ Analog Input Current, IIN 0 100 285 µA 3-3 VIN = +3.0V, +0.07VRMS HI3256 Electrical Specifications DVCC1 , 2 , AVCC, DGND3 = +5V, DGND1, 2, AGND, DVEE3 = 0V, VRT = 4V, VRB = 2V, TA = 25oC (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Reference Resistance (Note 3), RREF 400 600 740 Ω Reference Current (Note 4), IREF 2.7 3.3 5.0 mA REFERENCE INPUT Offset Voltage VRT Side, EOT 6 8 10 mV Offset Voltage VRB Side, EOB 0 1.5 3 mV Digital Input Voltage: High, VIH DVEE3 + 1.5 - DGND3 V Digital Input Voltage: Low, VIL DVEE3 + 1.1 - VIH - 0.4 V - DGND3 - 1.2 - V DIGITAL INPUT (PECL/ECL) Threshold Voltage, VTH Digital Input Current: High, IIH VIH = DGND3 - 0.8V -50 - +50 µA Digital Input Current: Low, IIL VIL = DGND3 - 1.6V -50 - 0 µA - - 5 pF Digital Input Voltage: High, VIH 2.0 - - V Digital Input Voltage: Low, VIL - - 0.8 V Threshold Voltage, VTH - 1.5 - V - 0 µA Digital Input Capacitance DIGITAL INPUT (TTL) Digital Input Current: High, IIH VIH = 3.5V -10 Digital Input Current: Low, IIL VIL = 0.2V -20 - 0 µA - - 5 pF Digital Input Capacitance DIGITAL OUTPUT (TTL) Digital Output Voltage: High, VOH IOH = -2mA 2.4 - - V Digital Output Voltage: Low, VOL IOL = 1mA - - 0.5 V SWITCHING CHARACTERISTICS Maximum Conversion Rate, fC DEMUX Mode Aperture Jitter, tAJ Sampling Delay, tDS 120 - - MSPS - 10 - ps 1.2 1.4 1.6 ns Clock High Pulse Width, tPW1 CLK 3.0 - - ns Clock Low Pulse Width, tPW0 CLK 4.5 - - ns RESET Signal Setup Time, tRS RESETN-CLK 1.0 - - ns RESET Signal Hold Time, tRH RESETN-CLK -0.5 - - ns CLKOUT Output Delay, tDCLK CL = 5pF Data Output Delay (Note 5), DEMUX Mode tDO1 tDO2 3.0 4.5 7.0 ns (CL = 5pF) - t + 0.5 - ns (CL = 5pF) 3.5 5.0 7.0 ns Output Rise Time, tr 0.8 to 2.0V (CL = 5pF) - 1 - ns Output Fall Time, tf 0.8 to 2.0V (CL = 5pF) - 1 - ns DYNAMIC CHARACTERISTICS Input Bandwidth VIN = 2VP-P , -3dB 250 - - MHz S/N Ratio fC = 120MSPS, fIN = 1kHz Full Scale, DEMUX Mode - 46 - dB fC = 120MSPS, fIN = 29.999MHz Full Scale, DEMUX Mode - 42 - dB fC = 120MSPS, fIN = 1kHz Full Scale, DEMUX Mode, Error > 16 LSB - - 10-12 TPS fC = 120MSPS, fIN = 29.999MHz Full Scale, DEMUX Mode, Error > 16 LSB - - 10-9 TPS fC = 100MSPS, fIN = 24.999MHz Full Scale, Straight Mode, Error > 16 LSB - - 10-9 TPS 70 98 140 mA Error Rate (Note 6) POWER SUPPLY OPERATING (PS = 1) Total Supply Current, ICC + IEE 3-4 HI3256 DVCC1 , 2 , AVCC, DGND3 = +5V, DGND1, 2, AGND, DVEE3 = 0V, VRT = 4V, VRB = 2V, TA = 25oC (Continued) Electrical Specifications MIN TYP MAX UNITS AVCC Pin Supply Current, AICC PARAMETER TEST CONDITIONS 45 - 87 mA DVCC1 Pin Supply Current, DICC1 20 - 36 mA DVCC2 Pin Supply Current, DICC2 5 - 15 mA DGND3 Pin Supply Current, IEE 0.5 - 1.5 mA Power Consumption, PD*6 400 500 700 mW Total Supply Current, PS ICC + IEE - - 5 mA AVCC Pin Supply Current, PS AICC - - 1.5 mA DVCC1 Pin Supply Current, PS DICC1 - - 1.5 mA DVCC2 Pin Supply Current, PS DICC2 - - 1.5 mA DGND3 Pin Supply Current, PS IEE - - 0.5 mA Power Consumption, PS PD*6 - - 25 mW POWER SUPPLY IN POWER SAVING MODE (PS = 0) NOTES: 3. RREF: Resistance value between VRT and VRB . V RT – V RB -. 4. I REF = ---------------------------R REF 1 5. t = ----- . fC 6. The unit of measure TPS: Times Per Sample. ( V RT – V RB ) 2 -. 7. P D = ( I CC + I EE ) • V CC + -----------------------------------V REF Timing Diagrams N-1 N+2 VIN N+3 tDS N N+1 t CLK tPW1 tD02 tPW0 2V N-2 PAD0 TO D7 N N+2 N+1 N+3 0.8V PBD0 TO D7 2V N-1 0.8V tD01 tDCLK t + 1ns CLK OUT 2V 2V 0.8V 0.8V RESET PULSE tPWR FIGURE 1. DEMUX MODE TIMING CHART (SELECT1 = VCC) 3-5 HI3256 Timing Diagrams (Continued) N+2 N-1 VIN N+3 N+1 tDS N t CLK tPW1 tPW0 PAD0 TO D7 N-4 2.0V 0.8V N-3 N-2 N-1 N PBD0 TO D7 N-5 2.0V 0.8V N-4 N-3 N-2 N-1 tD02 CLK OUT (CLK IS INVERTED AND OUTPUT) 8ns 2.0V 0.8V tDCLK RESET PULSE FIGURE 2. STRAIGHT MODE TIMING CHART (SELECT1 = GND) DGND3 VIH (MAX) VIL VTH (DGND3 - 1.2V) VID VIH VIL (MIN) FIGURE 3. PECL SWITCHING LEVEL Pin Descriptions PIN NO SYMBOL TYPICAL VOLTAGE LEVEL 3, 10 AGND GND Analog Ground. Separated from the digital ground. 5, 8 AVCC +5V (Typ) Analog Power Supply. Separated from the digital power supply. 20, 29 32, 41 DGND1 DGND2 GND Digital Ground. 19, 30 31, 42 DVCC1 DVCC2 +5V (Typ) Digital Power Supply. 12 DGND3 +5V (Typ) (With a Single Power Supply) Digital Power Supply. Apply -5V for PECL and TTL input. 1 DVEE3 I/O EQUIVALENT CIRCUIT DESCRIPTION GND (With Dual Power Supplies) GND (With a Single Power Supply) +5V (Typ) (With Dual Power Supplies) 3-6 Digital Power Supply. Apply -5V for PECL and TTL input. HI3256 Pin Descriptions (Continued) PIN NO SYMBOL I/O TYPICAL VOLTAGE LEVEL 16 SELECT2 I DVCC1, DGND1 or Open Data Output Switching. Data is output from both PA and PD when left open. If pin is connected to DVCC1, only PA is used as output with PB high impedance. If pin is connected to DGND1, only PB is used as output with PA high impedance. 17 VOCLP I Clamp Voltage Defines TTL output high level. If left open the high level is ~ 2.8V. 18 PS I TTL Power Savings Pin. When left open or at high level the device operates normally. When set to low level the power saving mode enabled. 13 CLK/E I PECL/ECL Clock Input. 14 CLK/NE I EQUIVALENT CIRCUIT DESCRIPTION CLK/E Complementary Input. When left open, this pin goes to the threshold potential. Only CLK/E can be used for operation, but complementary input is recommended to attain fast and stable operation. DGND3 13 48 48 RESETN/E I 47 RESET/E I 15 CLK/T I 46 RESETN/T I 14 47 Reset Input. When the input is set to low level, the built-in CLK frequency divider circuit can be reset. DVEE3 TTL RESETN/E Complementary Input. When left open, this pin goes to the threshold voltage. Only RESETN/E can be used for operation. Clock input. DVCC1 15 46 OR 44 , 45 Reset Input. When left open, this input goes to high level. When the input is set to low level, the built-in CLK frequency divider circuit can be reset. 1.5V DGND1 DVEE3 44 INV I TTL DVCC1 44 DGND1 DVEE3 3-7 Data Output Polarity Inversion Input. When left open, this input goes to high level. (See Table 1; I/O Correspondence Table). HI3256 Pin Descriptions PIN NO SYMBOL 45 SELECT1 (Continued) TYPICAL VOLTAGE LEVEL I/O VCC or Ground EQUIVALENT CIRCUIT DESCRIPTION Data Output Mode Selection. (See Table 2; Operating Mode Table). DVCC1 45 DGND1 DVEE3 11 VRT I 4.0V (Typ) Top Reference Voltage. Bypass to AGND with a 1µF tantal capacitor and a 0.1µF chip capacitor. R1 11 R/2 9 7 4 2 VRM3 VRB + 3 --- (VRT - VRB) 4 VRM2 VRB + 2 --- (VRT - VRB) 4 VRB + 1 --- (VRT - VRB) 4 VRM1 VRB I Reference Voltage Mid Point. Bypass to AGND with a 0.1µF chip capacitor. R COMPARATOR 1 Reference Voltage Mid Point. Bypass to AGND with a 0.1µF chip capacitor. R COMPARATOR 63 9 R COMPARATOR 64 2.0V (Typ) COMPARATOR 127 R 7 COMPARATOR 128 Reference Voltage Mid Point. Bypass to AGND with a 0.1µF chip capacitor. Bottom Reference Voltage. Bypass to AGND with a 1µF tantal capacitor and a 0.1µF chip capacitor. COMPARATOR 191 4 R COMPARATOR 192 R COMPARATOR 255 R2 R/2 2 6 VIN I VRT to VRB Analog Input. COMPARATOR AVCC AVCC VREF 6 AGND DVEE3 33 to 40 PBD0 to PBD7 O 21 to 28 PAD0 to PAD7 O 43 CLKOUT O TTL Port 1 Side Data Output. DVCC1 DVCC2 21 TO 28 33 TO 40 43 DGND2 DGND1 3-8 DVEE3 Port 2 Side Data Output. Clock Output. (See Table 2; Operating Mode Table). HI3256 TABLE 1. A/D CODE INV 1 VIN STEP VRT 255 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 254 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 • • • VRM2 D0 D7 • • • D0 • • • 128 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 127 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 • • • VRB D7 0 • • • • • • 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Notes on Operation • The HI3256 is a high-speed A/D converter which is capable of TTL, ECL and PECL level clock input. Characteristic impedance should be properly matched to ensure optimum performance during high-speed operation. • The power supply and grounding have a profound influence on converter performance. The power supply and grounding method are particularly important during highspeed operation. General points for caution are as follows: - The ground pattern should be as large as possible. It is recommended to make the power supply and ground patterns wider at an inner layer using a multi-layer board. - To prevent interference between AGND and DGND and between AVCC and DVCC , make sure the respective patterns are separated. To prevent a DC offset in the power supply pattern, connect the AVCC and DVCC lines at one point each, via a ferrite-bead filter. Shorting the AGND and DGND patterns in one place immediately under the A/D converter improves A/D converter performance. - Ground the power supply pins (AVCC , DVCC1 , DVCC2 , DVEE3) as close to each pin as possible with a 0.1µF or larger ceramic chip capacitor. (Connect the AVCC pin to the AGND pattern and the DVCC1 , DVCC2 , DVEE3 pins to the DGND pattern). - The digital output wiring should be as short as possible. If the digital output wiring is long, the wiring capacitance will increase, deteriorating the output slew rate and resulting in reflection to the output waveform since the original output slew rate is quite fast. • The analog input pin VIN has an input capacitance of approximately 21pF. To drive the A/D converter with proper frequency response, it is necessary to prevent performance deterioration due to parasitic capacitance or parasitic inductance by using a large capacity drive circuit; keeping wiring as short as possible, and using chip parts for resistors and capacitors, etc. • The VRT and VRB pins must have adequate bypass to protect them from high-frequency noise. Bypass them to AGND with approximately 1µF tantal capacitor and, 0.1µF capacitor. At this time, approximately DGND3 - 1.2V voltage is generated. However, this is not recommended for use as threshold voltage VBB as it is too weak. When the digital input level is PECL level, ***/E pins should be used and ***/T pins left open. When the digital input level is TTL, ***/T pins should be used and III/E pins left open. Test Circuits +V 4V 1.95V VRT 5V 5V A ICC A AVCC DVCC1 DVCC2 VIN S2 - IEE VRB -V CLK/E DGND2 DGND1 AGND S1: ON WHEN A < B S2: ON WHEN A > B DGND3 A<B A>B COMPARATOR 5MHz PECL VIN 2V S1 + DVEE3 HI3256 8 “0” A8 TO A1 B8 TO B1 A0 B0 CONTROLLER 3-9 BUFFER “1” DVM FIGURE 4. CURRENT CONSUMPTION MEASUREMENT CIRCUIT 8 000...00 TO 111..10 FIGURE 5. INTEGRAL LINEARITY ERROR/DIFFERENTIAL LINEARITY ERROR MEASUREMENT CIRCUIT HI3256 Test Circuits (Continued) A SIGNAL SOURCE fC 4 HI3256 8 VIN CLK -1kHz LATCH B CLK COMPARATOR A>B PULSE COUNTER LATCH + 2VP-P SINE WAVE SIGNAL SOURCE 1/ fC 16 LSB 8 FIGURE 6. ERROR RATE MEASUREMENT CIRCUIT VRT 100MHz VIN VRM2 VRB AMP OSC1 φ: VARIABLE fR CLK VIN 8 HI3256 LOGIC ANALYZER ∆υ 129 ∆t 128 127 VIN σ (LSB) 126 CLK 125 1024 SAMPLES SAMPLING TIMING FLUCTUATION (= APERTURE JITTER) CLK OSC2 NOTE: Where σ (LSB) is the deviation of the output codes when the largest slew rate point is sampled at the clock which has exactly the same frequency as the analog input signal, the aperture jitter tAJ is: PECL BUFFER 100MHz ∆υ 256 t AJ = σ / ------- = σ/ ---------- x 2πf . 2 ∆t FIGURE 7. SAMPLING DELAY/APERTURE JITTER MEASUREMENT CIRCUIT FIGURE 8. APERTURE JITTER MEASUREMENT METHOD Operating Modes The HI3256 has two types of operating modes which are selected with Pin 45 (SELECT1). TABLE 2. OPERATING MODE OPERATING MODE SELECT1 MAXIMUM CONVERSION RATE DATA OUTPUT CLOCK OUTPUT DMUX Mode VCC 120MSPS Demultiplexed Output 60MBPS The input clock is 1/2 frequency divided and output at Straight Mode GND 100MSPS Straight Output 100MBPS The input clock is inverted and output at 100MHz. 60MHz. DMUX Mode (See Application Circuits, Figures 18, 19) Straight Mode (See Application Circuits, Figures 20, 21) Set the SELECT1 pin to VCC for this mode. In this mode, the clock frequency is divided by 2 in the IC, and the data is output after being demultiplexed by this 1/2 frequency divided clock. The 1/2 frequency divided clock, which has adequate setup time and hold time for the output data, is output from the CLKOUT pin. Set the SELECT1 pin to GND for this mode. In this mode, data output can be obtained in accordance with the clock frequency applied to the A/D converter for applications which use the clock applied to the A/D converter as the system clock. When using multiple HI3256 units in parallel in this mode, differences in the start timing of the 1/2 frequency divided clock may cause operation as shown in Figure 9. As a countermeasure, the HI3256 is equipped with a function which resets the 1/2 frequency divided clock. When resetting this clock, the RESET pulse must be input to the RESET pin. See the Timing Charts for the RESET pulse input timing. The A/D converter can operate at fC (Min) = 120MSPS in this mode. 3-10 The A/D converter can operate at fC (Min) = 100MSPS in this mode. Digital Input Level and Supply Voltage Settings The logic input level for the HI3256 supports PECL and TTL levels. The power supplies (DVEE3 , DGND3) for the logic input block must be set to match the logic input (CLK and RESET signals) level. HI3256 TABLE 3. LOGIC INPUT LEVEL AND POWER SUPPLY SETTINGS DIGITAL INPUT LEVEL DVEE3 DGND3 SUPPLY VOLTAGE APPLICATION CIRCUITS PECL 0V +5V +5V Figures 18, 20 TTL 0V +5V +5V Figures 19, 21 CLK HI3256 CLK CLK CLKOUT A 8 BITS DATA RESETN HI3256 CLK CLKOUT B 8 BITS DATA RESETN FIGURE 9. WHEN THE RESET PULSE IS NOT USED CLK RESET PULSE HI3256 CLK CLK CLKOUT A 8 BITS DATA RESETN HI3256 CLK RESET PULSE CLKOUT B 8 BITS DATA RESETN FIGURE 10. WHEN THE RESET PULSE IS USED Typical Performance Curves 110 CURRENT CONSUMPTION (mA) CURRENT CONSUMPTION (mA) 110 105 100 95 90 -25 25 TA , AMBIENT TEMPERATURE (oC) FIGURE 11. CURRENT CONSUMPTION vs AMBIENT TEMPERATURE CHARACTERISTICS 3-11 75 105 100 95 f fIN = CLK -1kHz 4 DMUX MODE CL = 5pF 90 0 60 fC , CONVERSION RATE (MSPS) 120 FIGURE 12. CURRENT CONSUMPTION vs CONVERSION RATE CHARACTERISTICS RESPONSE HI3256 (Continued) VRT = 4V VRB = 2V 4 REFERENCE CURRENT (mA) ANALOG INPUT CURRENT (µA) Typical Performance Curves 100 50 3 2 0 2 3 25 -25 4 75 TA , AMBIENT TEMPERATURE (oC) ANALOG INPUT VOLTAGE (V) FIGURE 13. ANALOG INPUT CURRENT vs ANALOG INPUT VOLTAGE CHARACTERISTICS FIGURE 14. REFERENCE CURRENT vs AMBIENT TEMPERATURE CHARACTERISTICS 50 fC = 120MSPS ERROR RATE (TPS) 10-6 30 fCLK -1kHz 4 ERROR > 16 LSB 10-7 10-8 10-9 10-10 20 1 3 5 10 30 120 50 INPUT FREQUENCY (MHz) 170 140 fC , CONVERSION RATE (MSPS) FIGURE 15. SNR vs INPUT FREQUENCY RESPONSE fC , MAXIMUM CONVERSION (MSPS) SNR (dB) 40 fIN = fIN = FIGURE 16. ERROR RATE vs CONVERSION RATE CHARACTERISTICS fCLK -1kHz 4 ERROR > 16 LSB ERROR RATE: 10-9 TPS 160 150 140 130 -25 25 75 TA , AMBIENT TEMPERATURE (Co) FIGURE 17. MAXIMUM CONVERSION RATE vs AMBIENT TEMPERATURE CHARACTERISTICS 3-12 160 HI3256 Application Circuits +5V (D) DG PECL RESET PULSE 48 47 46 45 44 43 42 41 40 39 38 37 DG 8-BIT DIGITAL DATA 2 36 P1D0 TO P1D7 35 8-BIT DIGITAL DATA 3 34 4 33 +5V (A) 5 32 AG 6 31 7 30 8 29 9 28 AG 10 27 AG 11 26 P2D0 TO P2D7 8-BIT DIGITAL DATA 25 1 DG AG 2V +5V (A) +5V (D) 4V 12 LATCH DG +5V (D) DG 8-BIT DIGITAL DATA LATCH 13 14 15 16 17 18 19 20 21 22 23 24 PECL - CLK DG +5V (D) FIGURE 18. DMUX PECL INPUT +5V (D) DG TTL RESET PULSE 48 47 46 45 44 43 42 41 40 39 38 37 DG 8-BIT DIGITAL DATA 2 36 P1D0 TO P1D7 35 8-BIT DIGITAL DATA 3 34 4 33 +5V (A) 5 32 AG 6 31 7 30 8 29 9 28 AG 10 27 AG 11 26 P2D0 TO P2D7 8-BIT DIGITAL DATA 25 1 AG AG 2V +5V (A) +5V (D) 4V 12 DG +5V (D) DG 13 14 15 16 17 18 19 20 21 22 23 24 TTL - CLK DG +5V (D) FIGURE 19. DMUX TTL INPUT 3-13 LATCH 8-BIT DIGITAL DATA LATCH HI3256 Application Circuits (Continued) DG +5V (D) DG 48 47 46 45 44 43 42 41 40 39 38 37 DG 8-BIT DIGITAL DATA 2 36 P1D0 TO P1D7 35 8-BIT DIGITAL DATA 3 34 4 33 +5V (A) 5 32 AG 6 31 7 30 8 29 9 28 AG 10 27 AG 11 26 1 AG AG 2V +5V (A) +5V(D) 4V LATCH DG +5V (D) DG 25 12 13 14 15 16 17 18 19 20 21 22 23 24 PECL - CLK PECL - TTL DG +5V (D) FIGURE 20. STRAIGHT PECL INPUT DG +5V (D) DG 48 47 46 45 44 43 42 41 40 39 38 37 DG 8-BIT DIGITAL DATA 2 36 P1D0 TO P1D7 35 8-BIT DIGITAL DATA 3 34 4 33 +5V (A) 5 32 AG 6 31 7 30 8 29 9 28 AG 10 27 AG 11 26 AG AG 1 2V +5V (A) +5V(D) 4V DG +5V (D) DG 25 12 13 14 15 16 17 18 19 20 21 22 23 24 TTL - CLK DG +5V (D) FIGURE 21. STRAIGHT TTL INPUT 3-14 LATCH HI3256 Application Circuits (Continued) AG ANALOG INPUT + - +5V AG (A) + AG 11 10 9 8 7 6 5 4 3 2 VRT AGND VRM3 AVCC VRM2 VIN AVCC VRM1 AGND VRB 1 RESETN/E 48 13 CLK/E 14 CLKN/E 15 CLK/T 16 NC SELECT 45 17 NC INV 44 18 NC CLKOUT 43 19 DVCC2 DVCC2 42 20 DGND2 DGND2 41 21 P2D0 P1D7 40 22 P2D1 P1D6 39 23 P2D2 P1D5 38 24 P2D3 P1D4 37 RESET/E 47 P2D6 (MSB) P2D7 32 33 34 35 36 P1D6 (MSB) P1D7 P2D5 P1D3 31 P1D3 DVCC2 30 P1D2 DVCC1 29 P1D2 DGND1 28 P1D1 P2D7 27 P1D1 P2D6 26 P1D0 P2D5 25 (LSB) P1D0 P2D4 RESETN/T 46 P2D4 P2D2 P2D3 12 DGND3 SHORT TTL CLK AG 10µF P1D4 P1D5 10µF 1µF - + SHORT 2V - + DG + (LSB) P2D0 P2D1 + 1µF DGND2 (D) AG + +5V DVEE3 4V SHORT THE ANALOG SYSTEM AND DIGITAL SYSTEM AT ONE POINT IMMEDIATELY UNDER THE A/D CONVERTER. SEE THE NOTES ON OPERATION. IS THE CHIP CAPACITOR OF 0.1µF. FIGURE 22. STRAIGHT MODE TTL I/O (WHEN A SINGLE POWER SUPPLY IS USED) All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com 3-15