CXA3256R
8-bit 120MSPS Flash A/D Converter
Description
The CXA3256R is an 8-bit high-speed flash A/D
converter capable of digitizing analog signals at the
maximum rate of 120MSPS. ECL, PECL or TTL can
be selected as the digital input level in accordance
with the application. The TTL digital output level
allows 1: 2 demultiplexed output.
The CXA3256R is easier to be used by adding the
new functions to the CXA3246Q and adopting a
ultra-small package.
48 pin LQFP (Plastic)
LEAD TREATMENT: PALLADIUM PLATING
Features
• Differential linearity error: ±0.5LSB or less
• Integral linearity error: ±0.5LSB or less
• High-speed operation with a maximum conversion
rate of 120MSPS
• Low input capacitance: 10pF
• Wide analog input bandwidth: 250MHz
• Low power consumption: 500mW
• Power saving function
• 1: 2 demultiplexed output
• 1/2 frequency-divided clock output
(with reset function)
• Compatible with ECL, PECL and TTL digital input
levels
• TTL output "H" levels: 2.8V (Typ.)
• Output voltage control function (VOCLP)
• +3.3V line CMOS IC direct connecting available
• Single +5V power supply operation available
• Ultra-small surface mounting package (48-pin LQFP)
DVEE3
6
VRB
7
AGND
VIN
8
AVCC
VRM2
9
VRM1
VRM3
Applications
• Magnetic recording (PRML)
• Communications (QPSK, QAM)
• LCDs
• Digital oscilloscopes
AVCC
12 11 10
VRT
AGND
DGND3
Pin Configuration (Top View)
Structure
Bipolar silicon monolithic IC
5
4
3
2
1
CLK/E 13
48 RESETN/E
47 RESET/E
CLKN/E 14
CLK/T 15
46 RESETN/T
SELECT2 16
45 SELECT1
44 INV
VOCLP 17
43 CLKOUT
PS 18
DVCC2 19
42 DVCC2
DGND2 20
41 DGND2
PAD0 21
40 PBD7
PAD1 22
39 PBD6
PAD2 23
38 PBD5
PAD3 24
37 PBD4
PBD3
PBD2
PBD1
PBD0
DGND2
DVCC1
DVCC2
DGND1
PAD7
PAD6
PAD5
PAD4
25 26 27 28 29 30 31 32 33 34 35 36
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E98305A8X-PS
CXA3256R
Absolute Maximum Ratings (Ta = 25°C)
Unit
AVCC, DVCC1, DVCC2
–0.5 to +7.0
V
DGND3
–0.5 to +7.0
V
DVEE3
–7.0 to +0.5
V
DGND3 – DVEE3
–0.5 to +7.0
V
VRT – 2.7 to AVCC
V
• Analog input voltage
VIN
• Reference input voltage
VRT
2.7 to AVCC
V
VIN – 2.7 to AVCC
V
VRB
|VRT – VRB|
2.5
V
• Digital input voltage
ECL/PECL input pin
DVEE3 – 0.5 to DGND3 + 0.5
V
V
TTL input pin
DGND1 – 0.5 to DVCC1 + 0.5
SELECT2 pin
DGND1 – 0.5 to DVCC1 + 0.5
V
V
VOCLP pin
DGND1 – 0.5 to DVCC1 + 0.5
VID∗1 (|∗∗∗/E – ∗∗∗N/E|)
2.7
V
• Storage temperature
Tstg
–65 to +150
°C
• Allowable power dissipation PD
1.4
W
(when mounted on a two-layer glass fabric base epoxy board with dimentions of 50mm × 50mm, 1.6mm thick)
• Supply voltage
Recommended Operating Conditions
•
•
•
•
•
•
With a single power supply With dual power supply Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
Supply voltage
DVCC1, DVCC2, AVCC
+4.75
+5.0
+5.25 +4.75
+5.0
+5.25
V
DGND1, DGND2, AGND –0.05
0
+0.05 –0.05
0
+0.05
V
DGND3
+4.75
+5.0
+5.25 –0.05
0
+0.05
V
–0.05
0
+0.05
–5.5
–5.0
–4.75
V
DVEE3
Analog input voltage
VIN
VRB
VRT
VRB
VRT
V
Reference input voltage VRT
+2.9
+4.1
+2.9
+4.1
V
VRB
+1.4
+2.6
+1.4
+2.6
V
|VRT – VRB|
1.5
2.1
1.5
2.1
V
Digital input voltage
ECL/PECL input pin : VIH DVEE3 + 1.5
DGND3 DVEE3 + 1.5
DGND3
V
: VIL DVEE3 + 1.1
VIH – 0.4 DVEE3 + 1.1
VIH – 0.4 V
TTL input pin
: VIH
2.0
2.0
V
: VIL
0.8
0.8
V
SELECT2 pin
: VIH
DVCC1
DVCC1
V
: VIL
DGND1
DGND1
V
VOCLP pin
DGND1 + 2.4
DVCC1 DGND1 + 2.4
DVCC1
V
VID∗1 (|∗∗∗/E – ∗∗∗N/E|)
0.4
0.8
0.4
0.8
V
Maximum conversion rate Fc (Straight mode)
100
100
MSPS
(DMUX mode)
120
120
MSPS
Ambient temperature Ta
–20
+75
–20
+75
°C
∗1 VID: Input Voltage Differential
ECL and PECL switching level
DGND3
VIH (max.)
VIL
VTH (DGND3 – 1.2V)
VID
VIH
VIL (min.)
–2–
CXA3256R
Pin Description
[Symbol]
DVEE3
VRB
AGND
VRM1
AVCC
VIN
VRM2
AVCC
VRM3
AGND
VRT
DGND3
CLK/E
CLKN/E
CLK/T
SELECT2
VOCLP
PS
DVCC2
DGND2
PAD0 to PAD7
DGND1
DVCC1
DVCC2
DGND2
PBD0 to PBD7
DGND2
DVCC2
CLKOUT
INV
SELECT1
RESETN/T
RESET/E
RESETN/E
[Pin No.]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21 to 28
29
30
31
32
33 to 40
41
42
43
44
45
46
47
48
Typical voltage
level with a single
power supply
[Description]
Digital power supply
Bottom reference voltage
Analog ground
Reference voltage mid point
Analog power supply
Typical voltage
level with dual
power supply
0V
–5.0V
1.4 to 2.6V
1.4 to 2.6V
0V
0V
—
—
+5V
+5V
VRB to VRT
VRB to VRT
Analog signal input
—
—
Reference voltage mid point
Analog power supply
+5V
+5V
Reference voltage mid point
—
—
Analog ground
0V
0V
Reference voltage (typ.)
2.9 to 4.1V
2.9 to 4.1V
Digital power supply
+5V
0V
ECL/PECL clock input
PECL
ECL
ECL/PECL clock input
PECL
ECL
TTL clock input
TTL
TTL
Data output switching
DGND1 or Open or DVcc1 DGND1 or Open or DVcc1
TTL high level clamp
Clamp voltage
Clamp voltage
Power saving
TTL
TTL
Digital power supply
+5V
+5V
Digital ground
0V
0V
PA side data output
TTL
TTL
Digital ground
0V
0V
Digital power supply
+5V
+5V
Digital power supply
+5V
+5V
Digital ground
0V
0V
PB side data output
TTL
TTL
Digital ground
0V
0V
Digital power supply
+5V
+5V
Clock output
TTL
TTL
Data output polarity inversion
TTL
TTL
Output mode selection
TTL
TTL
TTL reset input
TTL
TTL
ECL/PECL reset input
PECL
ECL
ECL/PECL reset input
PECL
ECL
–3–
CXA3256R
Block Diagram
AVCC
5
8
INV
DVCC1
44
30
DVCC2
DGND3
19 31 42
12
VRT 11
r1
r/2
(MSB)
r
40 PBD7
1
r
39 PBD6
2
6bit
38 PBD5
63
VRM3 9
8bit
r
64
TTLOUT
•
•
•
LATCH B
r
37 PBD4
36 PBD3
r
35 PBD2
65
6bit
•
•
•
126
127
r
VIN 6
128
r
ENCODER
r
VRM2 7
129
r
•
•
•
34 PBD1
6bit LATCH + ENCODER
r
33 PBD0
(LSB)
(MSB)
28 PAD7
6bit
27 PAD6
191
VRM1 4
26 PAD5
r
•
•
•
TTLOUT
8bit
193
LATCH B
192
r
LATCH A
r
25 PAD4
24 PAD3
6bit
23 PAD2
254
r
22 PAD1
255
r2
VRB 2
21 PAD0
(LSB)
r/2
CLK/T 15
16 SELECT2
CLK/E 13
17 VOCLP
18 PS
CLKN/E 14
D
Q
Select
43 CLKOUT
Q
RESETN/T 46
RESETN/E 48
RESET/E 47
3 10
AGND
45
29
SELECT1
DGND1
–4–
20 32 41
DGND2
1
DVEE3
CXA3256R
Pin Description and I/O Pin Equivalent Circuit
Pin
No.
Symbol
I/O
Standard
voltage level
Equivalent circuit
Description
3, 10
AGND
GND
Analog ground.
Separated from the digital ground.
5, 8
AVCC
+5V
(typ.)
Analog power supply.
Separated from the digital power
supply.
20, 29 DGND1
32, 41 DGND2
GND
Digital ground.
19, 30 DVCC1
31, 42 DVCC2
+5V
(typ.)
Digital power supply.
12
+5V (typ.)
(With a
single
power
supply)
DGND3
Digital power supply.
Ground for ECL input.
+5V for PECL and TTL inputs.
GND
(With dual
power
supply)
1
GND
(With a
single
power
supply)
DVEE3
Digital power supply.
–5V for ECL input.
Ground for PECL and TTL inputs.
–5V (typ.)
(With dual
power
supply)
DVCC1
16
SELECT2
I
DVCC1
or
Open
or
DGND1
r
r
16
r
DGND1
DVCC2
3k
17
VOCLP
I
Clamp
voltage
17
3.5k
–5–
DGND2
Data output switching.
Data is output from both the PA side
and PB side by setting this pin open.
When set to DVcc1 level, only the
PA side output port outputs the data,
makes the PB side high impedance.
When set to DGND1 level, only the
PB side output port outputs the data,
makes the PA side high impedance.
TTL output high level clamp.
The TTL high level voltage is
clamped to the approximately same
value as the voltage applied to this
pin.
Even if this pin is left open, the TTL
high level is clamped to
approximately 2.8V.
CXA3256R
Pin
No.
Symbol
I/O
Standard
voltage level
Equivalent circuit
Description
DVCC1
18
PS
I
Power saving.
When left open, this pin goes to high
level.
When set to low level, the power
saving state is established.
TTL
18
DGND1
13
14
CLK/E
CLKN/E
I
Clock input.
I
CLK/E complementary input.
When left open, this pin goes to the
threshold voltage.
Only CLK/E can be used for
operation, but complementary inputs
are recommended to attain fast and
stable operation.
DGND3
ECL/
PECL
48
RESETN/E
I
13 48
Reset signal input.
When set to low level, the built-in
CLK frequency divider circuit can be
reset.
14 47
47
RESET/E
I
RESETN/E complementary input.
When left open, this pin goes to the
threshold voltage. Only RESETN/E
can be used for operation.
15
CLK/T
I
Clock input.
DVEE3
46
44
RESETN/T
INV
TTL
DVCC1
TTL
15 46
or
44 , 45
Reset signal input.
When left open, this pin goes to high
level. When set to low level, the
built-in CLK frequency divider circuit
can be reset.
I
I
1.5V
DGND1
DVEE3
45
SELECT1
Vcc
or
GND
Data output polarity inversion input.
When left open, this input goes to
high level.
(See Table 1. I/O Correspondence
Table.)
Data output mode selection.
(See Table 2. Operation Mode
Table.)
–6–
CXA3256R
Pin
No.
11
Symbol
VRT
I/O
Standard
voltage level
I
4.0V
(typ.)
Equivalent circuit
Description
Top reference voltage.
By-pass to AGND with a 1µF tantal
capacitor and a 0.1µF chip capacitor.
r1
11
r/2
r
9
VRB +
VRM3
3 (VRT – VRB)
4
r
4
Comparator 63
r
9
7
Comparator 64
VRB +
VRM2
VRM1
Reference voltage mid point.
By-pass to AGND with a 0.1µF chip
capacitor.
Comparator 1
2
(VRT – VRB)
4
7
VRB +
4
Comparator 127
r
Comparator 128
Comparator 191
r
Comparator 192
1
(VRT – VRB)
4
r
Reference voltage mid point.
By-pass to AGND with a 0.1µF chip
capacitor.
Reference voltage mid point.
By-pass to AGND with a 0.1µF chip
capacitor.
Comparator 255
2
VRB
I
2.0V
(typ.)
r/2
2
AVCC
Bottom reference voltage.
By-pass to AGND with a 1µF tantal
capacitor and a 0.1µF chip capacitor.
r2
Comparator
AVCC
6
VIN
I
VRT
to
VRB
Analog input.
DVEE3
21
to
28
PAD0
to
PAD7
O
33
to
40
PBD0
to
PBD7
O
Vref
6
AGND
DVCC1
DVCC2
21 to 28
TTL
100k
33 to 40
DGND1
43
CLKOUT
O
–7–
43
DGND2
DVEE3
Port A side data output.
TTL output; the high level is
clamped to approximately 2.8V.
Port B side data output.
TTL output; the high level is
clamped to approximately 2.8V.
Clock output.
(See Table 2. Operation Mode Table.)
TTL output; the high level is
clamped to approximately 2.8V.
CXA3256R
Electrical Characteristics
(AVCC, DVCC1, 2, DGND3 = +5V, AGND, DGND1, 2, DVEE3 = 0V, VRT = 4V, VRB = 2V, Ta = 25°C)
Item
Symbol
Conditions
Min.
DC characteristics
Integral linearity error
Differential linearity error
EIL
EDL
Analog input
Analog input capacitance
Analog input resistance
Analog input current
CIN
RIN
IIN
Reference input
Reference resistance
Reference current
Offset voltage VRT side
VRB side
Rref∗2
Iref∗3
EOT
EOB
Digital input (ECL, PECL)
Digital input voltage: High
: Low
Threshold voltage
Digital input current : High
: Low
Digital input capacitance
VIH
VIL
VTH
IIH
IIL
Digital input (TTL)
Digital input voltage: High
: Low
Threshold voltage
Digital input current : High
: Low
Digital input capacitance
VIH
VIL
VTH
IIH
IIL
VIH = 3.5V
VIL = 0.2V
–10
–20
VOH
VOL
IOH = –2mA
IOL = 1mA
2.4
Fc
Taj
Tds
Tpw1
Tpw0
T_rs
T_rh
Td_clk
Tdo1
Tdo2
Tr
Tf
DMUX mode
120
Switching characteristics
Maximum conversion rate
Aperture jitter
Sampling delay
Clock high pulse width
Clock low pulse width
Reset signal setup time
Reset signal hold time
Clock output delay
Data output delay
Output rise time
Output fall time
Max.
8
Resolution
Digital output (TTL)
Digital output voltage : High
: Low
Typ.
VIN = 2Vp-p, Fc = 5MSPS
bits
±0.5
±0.5
LSB
LSB
7
0
10
20
100
40
285
pF
kΩ
µA
400
2.7
6
0
600
3.3
8
1.5
740
5.0
10
3
Ω
mA
mV
mV
DGND3
VIH – 0.4
V
V
V
µA
µA
pF
VIN = +3.0V + 0.07Vrms
DVEE3 + 1.5
DVEE3 + 1.1
DGND3 – 1.2
VIH = DGND3 – 0.8V
VIL = DGND3 – 1.6V
–50
–50
20
20
5
5
0
5
V
V
V
µA
µA
pF
0.5
V
V
2.0
1.5
CLK
CLK
RESETN – CLK
RESETN – CLK
DMUX mode
0.8 to 2.0V
0.8 to 2.0V
(CL = 5pF)
(CL = 5pF)
(CL = 5pF)
(CL = 5pF)
(CL = 5pF)
∗ These characteristics are for PECL input unless otherwise specified.
–8–
Unit
1.2
3.0
4.5
1.0
–0.5
3.0
3.5
10
1.4
4.5
T∗4 + 0.5
5.0
1
1
0.8
1.6
7.0
7.5
MSPS
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CXA3256R
Item
Symbol
Dynamic characteristics
Input bandwidth
SNR
VIN = 2Vp-p, –3dB
Fc = 120MSPS,
fin = 1kHz Fs
DMUX mode
Fc = 120MSPS,
fin = 29.999MHz Fs
DMUX mode
Fc = 120MSPS,
fin = 1kHz Fs
DMUX mode
Error > 16LSB
Fc = 120MSPS,
fin = 29.999MHz Fs
DMUX mode
Error > 16LSB
Fc = 100MSPS,
fin = 24.999MHz Fs
Straight mode
Error > 16LSB
Supply current for PS
AVcc pin supply current
for PS
DVcc1 pin supply current
for PS
DVcc2 pin supply current
for PS
DGND3 pin supply current
for PS
Min.
Typ.
Max.
Unit
46
MHz
dB
42
dB
250
{
{
10–12
TPS∗5
10–9
TPS
10–9
TPS
140
87
36
15
1.5
mA
mA
mA
mA
mA
5
mA
AICC
1.5
mA
DICC1
1.5
mA
DICC2
1.5
mA
IEE
0.5
mA
700
25
mW
mW
Error rate
Power supply
Supply current
AVcc Pin supply current
DVcc1 pin supply current
DVcc2 pin supply current
DGND3 pin supply current
Conditions
{
{
{
ICC + IEE
AICC
DICC1
DICC2
IEE
70
45
20
5
0.5
98
ICC+IEE
Power consumption
Pd∗6
Power consumption for PS Pd∗7
400
0.3
∗2 Rref: Resistance value between VRT and VRB
∗3 Iref = VRT – VRB
Rref
∗4 T = 1
Fc
∗5 TPS: Times Per Sample
2
∗6 Pd = (ICC + IEE) · VCC + (VRT – VRB)
Rref
∗7 Pd = (ICC + IEE) · VCC
–9–
500
CXA3256R
INV
VIN
1
Step
D7
VRT
VRM2
VRB
255
254
..
.
128
127
..
.
1
0
1 1 1 1 1
1 1 1 1 1
..
.
1 0 0 0 0
0 1 1 1 1
..
.
0 0 0 0 0
0 0 0 0 0
0
D0 D7
1 1 1
1 1 0
0 0 0
1 1 1
0 0 1
0 0 0
D0
0 0 0 0 0
0 0 0 0 0
..
.
0 1 1 1 1
1 0 0 0 0
..
.
1 1 1 1 1
1 1 1 1 1
Table 1. I/O Correspondence Table
– 10 –
0 0 0
0 0 1
1 1 1
0 0 0
1 1 0
1 1 1
CXA3256R
Electrical Characteristics Measurement Circuit
Sampling Delay Measurement Circuit
Aperture Jitter Measurement Circuit
Current Consumption Measurement Circuit
5V
Icc
1.95V
Amp
OSC1
φ: Variable
IEE
DGND3
AVCC
DVCC1
DVCC2
PS
VRT
4V
100MHz
5V
VIN
fr
8
Logic
Analizer
CXA3256R
CLK
CLK/E
VIN
5MHz PECL
1024
samples
OSC2
ECL
Buffer
DGND2
DGND1
AGND
VRB
2V
100MHz
DVEE3
Aperture Jitter Measurement Method
Integral Linearity Error Measurement Circuit
Differential Linearity Error Measurement Circuit
+V
VRT
VIN
VRM2
S2
VRB
S1: ON when A < B
S2: ON when A > B
S1
CLK
VIN
A<B A>B
Comparator
VIN
CXA3256R
8
A8
to
A1
B8
to
B1
A0
B0
“0”
8
Buffer
CLK
000···00
to
111···10
Controller
VIN
Fc
– 1kHz
4
2Vp-p Sine Wave
8
CLK
∆υ
∆t
= σ/ ( 256 × 2πf )
2
A
Latch
CXA3256R
B
CLK
+
16LSB
Signal
Source
Where σ (LSB) is the deviation of the output codes when
the largest slew rate point is sampled at the clock which
has exactly the same frequency as the analog input
signal, the aperture jitter Taj is:
Taj = σ/
Error Rate Measurement Circuit
σ (LSB)
Sampling timing fluctuation
(= aperture jitter)
“1”
DVM
Signal
Source
129
128
127
126
125
∆υ
∆t
–V
1/8
Fc
– 11 –
Latch
Comparator
A>B
Pulse
Counter
CXA3256R
Description of Operation Modes
The CXA3256R has two types of operation modes which are selected with Pin 45 (SELECT).
Operation
mode
SELECT1 Maximum
pin
conversion rate
Data output
Clock output
The input clock is 1/2 frequency divided
and output.
60MHz
DMUX mode
VCC
120MSPS
Demultiplexed output
60Mbps
Straight mode
GND
100MSPS
Straight output
100Mbps
The input clock is inverted and output.
100MHz
Table 2. Operation Mode Table
1. DMUX mode (See Application Circuit 1-(1), (2) and (3).)
Set the SELECT1 pin to Vcc for this mode. In this mode, the clock frequency is divided by 2 in the IC, and the
data is output after being demultiplexed by this 1/2 frequency-divided clock. The 1/2 frequency-divided clock,
which has adequate setup time and hold time for the output data, is output from the clock output pin.
When using the multiple CXA3256R in DMUX mode, the start timing of the 1/2 frequency-divided clocks
becomes out of phase, producing operation such as that shown in the example on the next page. As a
countermeasure, the CXA3256R has a function that resets the 1/2 frequency-divided clocks.
When resetting this 1/2 frequency-divided clock, the low level of the reset signal should be input to the
RESETN pin (Pin 46 or 48). The reset signal requires the setup time (T_rs ≥ 1.0ns) and hold time (T_rh ≥
–0.5ns) to the clock rising edge because it is synchronized with and taken in the clock.
The reset period can be extended by making the low level period of the reset signal longer because the clock
output pin is fixed to low (reset) during the low level period at the clock rising edge. If the reset start timing is
regarded as not important, the timing where the reset signal is set from high to low is not so consequence.
However, when the reset is released the timing where the reset signal is set from low to high must become
significant because the timing is used to commence the 1/2 frequency-divided clock. In this case, the setup
time (T_rs) is also necessary.
See the timing chart for detail. (This chart shows the example of reset for 2T.)
The A/D converter can operate at Fc (min.) = 120MSPS in this mode.
– 12 –
CXA3256R
When the reset signal is not used
AAA
AAA
AAA
AAA
AAA
CLK
CXA3256R
CLK
CLK
A A
CLKOUT
8bit
DATA
RESETN
CXA3256R
CLK
B B
RESETN
CLKOUT
8bit
DATA
When the reset signal is used
AAA
AAA
AAA
AAA
AAA
CLK
Reset signal
CXA3256R
CLK
CLK
A
CLKOUT
DATA
RESETN
CXA3256R
CLK
Reset signal
B
RESETN
(Reset period)
8bit
CLKOUT
(Reset period)
8bit
DATA
2. Straight mode (See Application Circuits 1-(4), (5) and (6).)
Set the SELECT1 pin to GND for this mode. In this mode, data output can be obtained in accordance with the
clock frequency applied to the A/D converter for applications which use the clock applied to the A/D converter
as the system clock.
The A/D converter can operate at Fc (min.) = 100MSPS in this mode.
Digital input level and supply voltage settings
The logic input level for the CXA3256R supports ECL, PECL and TTL levels.
The power supplies (DVEE3, DGND3) for the logic input block must be set to match the logic input (CLK and
reset signals) level.
Digital input level
DVEE3
DGND3
ECL
PECL
TTL
–5V
0V
0V
0V
+5V
+5V
Supply voltage Application circuits
±5V
+5V
+5V
(1) (4)
(2) (5)
(3) (6)
Table 3. Logic Input Level and Power Supply Settings
Description of SELECT2 pin
The CXA3256R has the two systems of data output. The SELECT2 pin is used to select the port where the
data is output.
SELECT2 pin
Data output
Open
Output possible to both PA and PB
Vcc1
Output possible to PA, and PB output is high impedance.
GND1
Output possible to PB, and PA output is high impedance.
– 13 –
CXA3256R
Application Circuit 1
(1) DMUX ECL input
+5V(D)
DG
3
34
4
33
4V
DG AG AG
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
PBD0 to PBD7
8 bit Digital Data
8 bit Digital Data
Latch
DG
35
+5V(D)
36
2
DG
2V
48 47 46 45 44 43 42 41 40 39 38 37
1
+5V(A)
+5V(A)
–5V(D)
AG AG
AG
ECL RESET signal
8 bit Digital Data
PAD0 to PAD7
8 bit Digital Data
Latch
13 14 15 16 17 18 19 20 21 22 23 24
ECL-CLK
DG
+5V(D)
(2) DMUX PECL input
+5V(D)
DG
4V
+5V(D)
AG AG
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
PBD0 to PBD7
8 bit Digital Data
8 bit Digital Data
Latch
DG
36
2
+5V(D)
1
DG
2V
48 47 46 45 44 43 42 41 40 39 38 37
+5V(A)
+5V(A)
AG AG DG
AG
PECL RESET signal
8 bit Digital Data
PAD0 to PAD7
8 bit Digital Data
Latch
PBD0 to PBD7
8 bit Digital Data
Latch
13 14 15 16 17 18 19 20 21 22 23 24
PECL-CLK
DG
+5V(D)
(3) DMUX TTL input
+5V(D)
DG
4V
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
TTL-CLK
DG
+5V(D)
– 14 –
8 bit Digital Data
DG
36
2
+5V(D)
+5V(D)
+5V(A)
AG AG
1
DG
2V
48 47 46 45 44 43 42 41 40 39 38 37
+5V(A)
AG
AG AG DG
TTL RESET signal
8 bit Digital Data
PAD0 to PAD7
8 bit Digital Data
Latch
CXA3256R
(4) Straight ECL input
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
PBD0 to PBD7
8 bit Digital Data
8 bit Digital Data
Latch
DG
36
2
+5V(D)
1
DG
2V
4V
+5V(A)
DG AG AG
+5V(D)
DG
48 47 46 45 44 43 42 41 40 39 38 37
+5V(A)
AG
–5V(D)
AG AG
DG
13 14 15 16 17 18 19 20 21 22 23 24
ECL-CLK
ECL → TTL
DG
DG
+5V(D)
(5) Straight PECL input
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
PBD0 to PBD7
8 bit Digital Data
8 bit Digital Data
Latch
DG
36
2
+5V(D)
1
DG
2V
4V
+5V(D)
AG AG
+5V(D)
DG
48 47 46 45 44 43 42 41 40 39 38 37
+5V(A)
+5V(A)
AG AG DG
AG
DG
13 14 15 16 17 18 19 20 21 22 23 24
PECL-CLK
PECL → TTL
DG
DG
+5V(D)
(6) Straight TTL input
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
TTL-CLK
DG
+5V(D)
+5V(D)
– 15 –
DG
36
2
+5V(D)
1
DG
2V
4V
+5V(D)
AG AG
+5V(D)
DG
48 47 46 45 44 43 42 41 40 39 38 37
+5V(A)
+5V(A)
AG AG DG
AG
DG
8 bit Digital Data
PAD0 to PAD7
8 bit Digital Data
Latch
CXA3256R
Application Circuit 2
A
A
DMUX Mode TTL I/O (When a single power supply is used)
AG
Analog
input
AG
4V
+5V (A)
AG
1µF
2V
1µF
AG
AG
short
10µF
10µF
12
11
10
9
8
7
6
5
4
3
2
DGND3
VRT
AGND
VRM3
AVCC
VRM2
VIN
AVCC
VRM1
AGND
VRB
short
13 CLK/E
1
DVEE3
+5V
(D) DG
RESETN/E 48
14 CLKN/E
RESET/E 47
15 CLK/T
RESETN/T 46
TTL CLK
SELECT1 45
16 SELECT2
INV 44
17 VOCLP
Clamp voltage
18 PS
19 DVCC2
DVCC2 42
20 DGND2
DGND2 41
PBD0
PBD1
PBD2
PBD3
PBD4 37
DGND2
24 PAD3
DVCC2
PBD5 38
DVCC1
23 PAD2
DGND1
PBD6 39
PAD7
22 PAD1
PAD6
PBD7 40
PAD5
21 PAD0
PAD4
C∗
CLKOUT 43
25
26
27
28
29
30
31
32
33
34
35
36
C∗
PBD2
PBD3
PBD6
(MSB) PBD7
PBD1
PBD4
PBD5
(LSB) PBD0
(MSB) PAD7
PAD6
PAD5
PAD4
PAD2
PAD3
(LSB) PAD0
PAD1
C∗
Short the analog system and digital system at one point immediately
under the A/D converter. See the Notes on Operation.
is the chip capacitor of 0.1µF. Also, C∗ is important to suppress the noise
generated during the TTL output circuit is operating. Place C∗ at the fixed position
between the pins with the shortest distance.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 16 –
CXA3256R
DMUX Mode Timing Chart (Select = VCC)
Tds
N–2
1.4ns (typ.)
N +5
VIN
(Pin 6)
N+6
N+4
N+2
N–1
T
N
N+3
N+1
CLK
(Pin 13)
Tpw1
Tpw0
Tdo2; 5.0ns (typ.)
3.5ns (min)
7.5ns (max)
PAD0 to D7
(Pins 21 to 28)
N
PBD0 to D7
(Pins 33 to 40)
N+1
2.0V
2.0V
N+3
0.8V
Tdo1
Td_clk; 4.5ns (typ.)
T + 0.5ns (typ.)
7.0ns (max)
3.0ns (min)
CLK OUT
(Pin 43)
T_rh
N+2
0.8V
(Reset period)
T_rs
T_rh
T_rs
AA
AA
AA
AAAAAA
2.0V
2.0V
2.0V
0.8V
0.8V
0.8V
RESETN
(Pin 48)
– 17 –
≈T
≈T
CXA3256R
Straight Mode Timing Chart (Select = GND)
N+3
N–1
VIN
(Pin 6)
N+2
Tds
N+1
N
1.4ns (typ.)
T
CLK
(Pin 13)
Tpw1
Tpw0
Tdo2; 5.0ns (typ.)
3.5ns (min)
7.5ns (max)
PAD0 to D7
(Pins 21 to 28)
N–4
PBD0 to D7
(Pins 33 to 40)
N–3
2.0V
N–3
N–2
N–1
N
N–2
N–1
N
N+1
0.8V
2.0V
0.8V
Td_clk; 4.5ns (typ.)
3.0ns (min)
7.0ns (max)
CLK OUT
(CLK is inverted
and output.)
(Pin 43)
2.0V
0.8V
– 18 –
CXA3256R
Notes on Operation
• The CXA3256R has the PECL and TTL input pins for the clock and reset input pins. When the clock is input
in PECL level, inputting the reset signal in PECL level is recommended. Also, when the clock is input in TTL
level, inputting the reset signal in TTL is recommended.
• The impedance of the input signal should be properly matched to ensure the CXA3256R's stable operation at
the high speed.
• In the CXA3256R, all the TTL input pins become the high level when left open.
• The power supply and grounding have a profound influence on converter performance. The power supply
and grounding method are particularly important during high-speed operation. General points for caution are
as follows.
— The ground pattern should be as large as possible. It is recommended to make the power supply and
ground patterns wider at an inner layer using a multi-layer board.
— To prevent interference between AGND and DGND and between AVcc and DVcc, make sure the
respective patterns are separated. To prevent a DC offset in the power supply pattern, connect the AVcc
and DVcc lines at one point each via a ferrite-bead filter, etc. Shorting the AGND and DGND patterns in
one place immediately under the A/D converter improves A/D converter performance.
— Be sure to turn the analog and digital power supplies on simultaneously. If not simultaneously, the IC does
not operate correctly.
— Ground the power supply pins (AVcc, DVcc1, DVcc2, DVEE3) as close to each pin as possible with a
0.1µF or larger ceramic chip capacitor.
(Connect the AVcc pin to the AGND pattern and the DVcc1, DVcc2 and DVEE3 pins to the DGND pattern.)
— It is recommended to place the ceramic chip capacitor of 0.1µF or more, in particular, between DVcc2
and DGND2 with the shortest distance. This has the effect to suppress the noise generated when the
CXA3256R TTL output circuit operates.
— The digital output wiring should be as short as possible. If the digital output wiring is long, the wiring
capacitance will increase, deteriorating the output slew rate and resulting in reflection to the output
waveform since the original output slew rate is quite fast.
• The analog input pin VIN has an input capacitance of approximately 10pF. To drive the A/D converter with the
proper frequency response, it is necessary to prevent performance deterioration due to parasitic capacitance
or parasitic inductance by using a large capacity drive circuit, keeping wiring as short as possible, and using
chip parts for resistors and capacitors, etc.
• The VRT and VRB pins must have adequate by-pass to protect them from high-frequency noise. By-pass them
to AGND with approximately 1µF tantal capacitor and 0.1µF chip capacitor as short as possible.
• If the CLKN/E pin is not used, by-pass this pin to DGND with an approximately 0.1µF capacitor. At this time,
approximately DGND3 – 1.2V voltage is generated. However, this is not recommended for use as the threshold
voltage VBB because it is too weak.
– 19 –
CXA3256R
• When the digital input level is ECL or PECL level, ∗∗∗/E pins should be used and ∗∗∗/T pins left open. When
the digital input level is TTL, ∗∗∗/T pins should be used and ∗∗∗/E pins left open.
• The CXA3256R TTL output high level is clamped to approximately 2.8 V in the IC.This makes it possible to
directly interface with the 3.3V system CMOS IC. However,the CXA3256R has the VOCLP pin which is used
to clamp the TTL output high level. See the Example of Representative Characteristics for the relationship
between the VOCLP pin and the TTL high level.
• The CXA3026Q has the output pins P1∗∗ and P2∗∗. However, in the CXA3256R, these symbols are changed
as PA∗∗and PB∗∗. At this time, the P1 side of the CXA3026Q is changed to the PB side for the CXA3256R;
the P2 side of the CXA3026Q to the PA side for the CXA3256R.
• The pipeline delay of the CXA3256R is smaller by one clock, compared to that of CXA3026Q.
– 20 –
CXA3256R
Example of Representative Characteristics
Current consumption vs.
Ambient temperature characteristics
Current consumption vs.
Conversion rate characteristics
110
Current consumption [mA]
Current consumption [mA]
110
105
100
95
105
fin =
100
fCLK
– 1kHz
4
DMUX mode
CL = 5pF
95
90
90
–25
25
75
60
0
Ta – Ambient temperature [°C]
Fc – Conversion rate [MSPS]
Analog input current vs.
Analog input voltage characteristics
Reference current vs.
Ambient temperature characteristics
120
4
Reference current [mA]
Analog input current [µA]
100
VRT = 4V
VRB = 2V
50
3
2
0
2
3
4
–25
Analog input voltage [V]
25
Ta – Ambient temperature [°C]
– 21 –
75
CXA3256R
SNR vs. Input frequency response
Error rate vs. Conversion rate characteristics
50
10–6
10–7
Error Rate [TPS]
SNR [dB]
40
30
Fc = 120MSPS
fin =
fCLK
– 1kHz
4
Error > 16LSB
10–8
10–9
10–10
20
3
10
5
30
120
50
140
160
Input frequency [MHz]
Fc – Conversion rate [MSPS]
Maximum conversion rate vs.
Ambient temperature characteristics
TTL output high level vs. VOCLP pin
170
3
fCLK
– 1kHz
4
Error > 16LSB
Error rate: 10–9 TPS
fin =
160
TTL output high level [V]
Fc – Maximum conversion rate [MSPS]
1
150
140
TTL high level when
VOCLP is open.
2
1
130
–25
25
75
Ta – Ambient temperature [°C]
0.5 1
3
VOCLP pin voltage [V]
– 22 –
5
CXA3256R
Package Outline
Unit: mm
48PIN LQFP (PLASTIC)
9.0 ± 0.2
∗
7.0 ± 0.1
36
S
25
A
13
48
0.5 ± 0.2
(8.0)
24
37
(0.22)
12
1
+ 0.05
0.127 – 0.02
0.5
+ 0.08
0.18 – 0.03
+ 0.2
1.5 – 0.1
0.13 M
0.1
0° to 10°
S
0.5 ± 0.2
0.1 ± 0.1
NOTE: Dimension “∗” does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
LQFP-48P-L01
LEAD TREATMENT
SOLDER/PALLADIUM
PLATING
EIAJ CODE
LQFP048-P-0707
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
0.2g
JEDEC CODE
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
– 23 –