DA6283.002 11 November, 2010 MAS6283 IC FOR 1.5625 MHz – 40.0000 MHz VCXO Low Power Wide Supply Range CMOS (Square Wave) Output Very Low Phase Noise Low Cost Divider Function Tri State output • • • • • • • DESCRIPTION MAS6283 is an integrated circuit well suited to build a VCXO for telecommunication and other applications. To build a VCXO only one additional component, a crystal, is needed. FEATURES • • • • • APPLICATIONS Very small size Low current consumption Wide operating temperature range Phase noise < -130 dBc/Hz at 1 kHz offset CMOS (Square wave) output VCXO modules VCXO for telecommunications systems VCXO for set-top boxes VCXO for MPEG decoder • • • • BLOCK DIAGRAM PD VC 1/2 1/2 1/2 1/2 OUT VDD MAS6283 1 nF VSS XIN XOUT Figure 1. Block diagram of MAS6283. 1/13 DA6283.002 11 November, 2010 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Supply Voltage Input Pin Voltage Power Dissipation (max) Storage Temperature Latchup Current Limit VDD - VSS Conditions PMAX TST ILUT Min Max Unit Note -0.3 VSS -0.3 6.0 VDD + 0.3 100 150 V V mW o C mA 1) -55 ±100 Note: Stresses beyond the values listed may cause a permanent damage to the device. The device may not operate under these conditions, but it will not be destroyed Note: This is a CMOS device and therefore it should be handled carefully to avoid any damage by static voltages (ESD). Note 1: Not valid for pins XIN and XOUT. RECOMMENDED OPERATION CONDITIONS Parameter Supply Voltage Operating Temperature Crystal RS Symbol VDD TOP RS Conditions Min Typ Max 2.5 -40 3.3 5.5 +85 60 30 Unit Note V C Ω 1) o 2) Note 1: It is recommended to connect a 1 nF SMD capacitor between the VDD and VSS pins. Assure that rd capacitor resonance frequency is high enough to filter 3 harmonic. Note 2: See figure 5 for negative resistance at different frequencies. 2/13 DA6283.002 11 November, 2010 ELECTRICAL CHARACTERISTICS Parameter Symbol Conditions Min Typ Max Unit Note Crystal Frequency Range fc 25 40 MHz 1) Output Frequency Range fo 25 40 MHz 2) Output Frequency Range fo 1.5625 20 MHz 3) Voltage Control Range VC 0 VDD V Voltage Control impedance ZVC Supply Current VDD = 3.3V, fc = 35 MHz IDD Supply Current VDD = 5.0V, fc = 35 MHz IDD Supply Current XPD = 0 V IXPD 1.2 No Load CLOUT = 10 pF CLOUT = 30 pF CLOUT = 50 pF No Load CLOUT = 10 pF CLOUT = 30 pF CLOUT = 50 pF VDD = 3.3 V VDD = 5.0 V Output Symmetry Startup Time Output Buffer Enabled Disabled Crystal Load Capacitance Pulling Range 0.0V < VC < 5.0V 45 TSTART 0.9 0.9 48-52 MΩ 2.0 9.3 23.8 38.3 3.0 14.0 36.0 58.0 1.5 1.7 55 2 mA mA mA % ms XPD 1.6 0 CL VDD 0.55 V 4) VC = 1.65 V 8 pF 5) Crystal S= 30 ppm/pF 285 ppm 6) Note 1: Crystal frequency can be divided by 2, 4, 8 and 16. Note 2: Direct output. Note 3: Depending on chosen output divider. Note 4: If the XPD pin is floating the output buffer is active. Oscillator is always running. At power down mode the output is at high impedance. Note 5: Crystal load capacitance is dependent on a VC voltage. See figure 4 for CL for other VC voltages. Note 6: For calculating crystal pulling (S), see equation 1 on the page 5. 3/13 DA6283.002 11 November, 2010 PIN DESCRIPTION Pin Description Crystal Oscillator Output Voltage Control Input Power Supply Ground Buffer Output Power Supply Voltage Output Buffer Power Down Control Crystal/Varactor Oscillator Input Symbol x-coordinate y-coordinate XOUT VC VSS OUT VDD XPD XIN 214 885 1080 1106 579 339 153 141 142 141 699 698 698 698 Note: Because the substrate of the die is internally connected to VSS, the die has to be connected to VSS or left floating. Please make sure that VSS is the first pad to be bonded. Pick-and-place and all component assembly are recommended to be performed in ESD protected area. Note: Pad coordinates are measured from the left bottom corner of the chip to the center of the pads. The coordinates may vary depending on sawing width and location. However, the distances between pads are accurate. IC OUTLINES XIN XPD VDD OUT 840 um XOUT VC MAS6283 VSS Die Map Reference 1260 um Figure 2. IC outline of MAS6283. Note1: Die map reference is the actual left bottom corner of the sawn chip. Note2: See coordinates in pin description. Note3: Die dimensions include 80 µm scribes for both sides. The actual dimensions are a bit less due to the saw width. 4/13 DA6283.002 11 November, 2010 EXTERNAL COMPONENT SELECTION Quartz Crystal and VCXO Module Information To ensure the best system performance, the crystal parameters should be considered carefully. Pulling is an important parameter which can be calculated according to an equation 1. Layout guidelines in the following section should be followed. The frequency of the crystal is tuned by load capacitors. There are integrated variable load capacitors on the MAS6283 and they are controlled by an external voltage at the VC pin. It is recommended to connect a 1 nF capacitor between VDD and VSS. The external crystal should be located as close to the chip as possible. In case of a PCB mounted module, it is usually advisable to mount a crystal on the same side with the VCXO IC to minimize stray capacitance. Often vias between the crystal pins and the XIN and XOUT pins of the VCXO IC increase stray capacitance. There should be no noisy signal traces underneath or close to the crystal. Equation 1 Crystal Pulling Sensitivity S =− C1 ppm [values are given in the units described below] 2 2(C 0 + C L ) pF 10 6 Where, CL = Load capacitance in series with the crystal C0 = Shunt capacitance of the crystal C1 = Motional capacitance of the crystal Example 1 If we choose a crystal with the following values CL = 8.0 pF, C0 = 2.0 pF, C1 = 6.7 fF the equation 1 yields S= − 6.7 × 10 −15 ( 2 2.0 × 10 −12 + 8.0 × 10 10 6 ) −12 2 = −33.5 ppm pF If a crystal load differs from 8 pF the oscillator will have frequency offset at VC = 1.65 V. Thus if you need to use 1.65 V VC voltage with a crystal which CL is other than 8 pF you have to design the crystal for a specific nominal frequency. The following guidelines show how to define the crystal’s nominal frequency. Separate crystal CL as CL_XTAL and MAS IC CL as CL_IC. To define specific nominal frequency for the crystal first calculate load difference ∆CL [pF] as in an equation 2. Equation 2 ∆C L = C L _ IC − C L _ XTAL Calculate frequency difference ∆f [ppm] as in an equation 3. Pulling S comes from the equation 1. Equation 3 ∆f = ∆C L × S 5/13 DA6283.002 11 November, 2010 The crystal nominal frequency fNOM_XTAL is calculated, as shown in an equation 4. Equation 4 f NOM _ XTAL = f NOM ∆f × 1 + 6 10 Where, fNOM = Desired nominal frequency of the VCXO module fNOM_XTAL = Crystal nominal frequency (without MAS IC load capacitance) Crystal nominal frequency optimization is calculated in an example 2. Example 2 VCXO module target frequency fNOM is 35 MHz. Crystal characteristics are crystal load CL_XTAL = 12.5 pF and pulling S = 30 ppm/pF. MAS6283 CL_IC = 8 pF when VC = 1.65 V. Calculate load difference ∆CL according to the equation 2. ∆C L = C L _ IC − C L _ XTAL = 8 pF − 12.5 pF = −4.5 pF Calculate frequency difference ∆f according to the equation 3. ∆f = ∆C L × S = −4.5 pF × 30 ppm = −135 ppm pF Now fNOM = 35 MHz. According to the equation 4 ∆f − 135 f NOM _ XTAL = f NOM × 1 + 6 = 35 × 10 6 × 1 + = 34995275 Hz 10 6 10 The specified crystal has to have a nominal frequency of 34.995275 MHz without load capacitance. This offset is compensated with 8 pF load capacitance though a crystal CL = 12.5 pF. 6/13 DA6283.002 11 November, 2010 VOLTAGE CONTROL (VC) MAS6283 VC Sensitivity INL % / pulling 1.5 1 0.5 0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -1 -1.5 -2 -2.5 -3 VC (V) Figure 3. MAS6283AA VC sensitivity measured as INL % / pulling vs VC (V). MAS6283 Voltage control sensitivity graph in figure 3 is measured by using 40.0 MHz crystal (CL = 8.5 pF, C1 = 4.9 fF, CL = 1.5 pF). For crystal pulling see equation 1 in a page 5. MAS6283 CL (pF) vs VC (V) CL (pF) 14 12 10 8 6 4 2 0 0 1 2 3 4 5 VC (V) Figure 4. MAS6283 CL vs VC voltage Figure 4 shows MAS6283 CL over the different VC voltages. 7/13 DA6283.002 11 November, 2010 Negative Resistance Frequency [Hz] 1,000,000 10,000,000 100,000,000 0 Negative Resistance [ohm] -500 -1000 -1500 VC 0.0V VC 1.65V VC 3.3V VC 5.5V -2000 -2500 -3000 Figure 5. MAS6283 negative resistance. Figure 5 shows MAS6283 negative resistance vs frequency with different VC voltage values measured at a room temperature. Negative resistance should be at least three times crystal RS to ensure a reliable oscillation. 8/13 DA6283.002 11 November, 2010 SAMPLES IN SB20 DIL PACKAGE XIN 1 20 2 19 XOUT 3 18 XPD 4 17 MAS6283 YYWW XXXXX.X VC 5 6 15 7 14 8 13 VSS 9 12 10 Top marking: YYWW = Year, Week XXXXX.X = Lot number 16 VDD 11 OUT Figure 8. MAS6283 SB20 DIL package. DEVICE OUTLINE CONFIGURATION pin 1 XOUT 6283 AX VSS YWW VC XIN XPD Top View VDD OUT A = product version X = MAS internal code Y = year WW= week MSOP8 Figure 9. MAS6283 MSOP-8 package. 9/13 DA6283.002 11 November, 2010 PACKAGE (MSOP-8) OUTLINE Gage plane F E1 E Land Pattern Recommendation P R A Q L A R1 N e c D G A2 c1 M b1 (b) A A1 Section A - A b Symbol Min A A1 A2 b b1 c c1 D E E1 e F G L (Terminal length for soldering) M N P Q R R1 0 0.75 0.22 0.22 0.08 0.08 0.40 Nom 0.85 0.30 3.00 BSC 4.90 BSC 3.00 BSC 0.65 BSC 4.8 0.65 0.60 Max Unit 1.10 0.15 0.95 0.38 0.33 0.23 0.18 mm mm mm mm mm mm mm mm mm mm mm mm mm mm 0.80 0.41 1.02 0° mm mm 8° 0.25 BSC 0.07 0.07 mm mm mm Dimensions do not include mold or interlead flash, protrusions or gate burrs. All measurement according to JEDEC standard MO-187. 10/13 DA6283.002 11 November, 2010 SOLDERING INFORMATION ◆ For Pb-Free Maximum Temperature Maximum Number of Reflow Cycles Reflow profile Seating Plane Co-planarity Lead Finish Moisture Sensitivity Level (MSL) 260°C 3 Thermal profile parameters stated in JESD22-A113 should not be exceeded. http://www.jedec.org max 0.08 mm Solder plate 7.62 - 25.4 µm, material Matte Tin 1 EMBOSSED TAPE SPECIFICATIONS (MSOP-8) P1 T DO PO P2 E W F BO A AO KO D1 Section A-A User Direction of Feed Pin 1 Designator Dimension Min/Max Unit Ao Bo Do D1 E F Ko Po P1 P2 T W 5.00 ±0.10 3.20 ±0.10 1.50 +0.1/-0.0 1.50 min 1.75 5.50 ±0.05 1.45 ±0.10 4.0 8.0 ±0.10 2.0 ±0.05 0.3 ±0.05 12.00 +0.30/-0.10 mm mm mm mm mm mm mm mm mm mm mm mm 11/13 DA6283.002 11 November, 2010 REEL SPECIFICATIONS (MSOP-8) W2 A D C Tape Slot for Tape Start N B W1 5000 Components on Each Reel Reel Material: Conductive, Plastic Antistatic or Static Dissipative Carrier Tape Material: Conductive Cover Tape Material: Static Dissipative Carrier Tape Cover Tape End Start Trailer Dimension A B C D N W 1 (measured at hub) W 2 (measured at hub) Trailer Leader Weight Leader Components Min 1.5 12.80 20.2 50 12.4 Max Unit 330 mm mm mm mm mm mm mm mm mm 13.50 14.4 18.4 160 390, of which minimum 160 mm of empty carrier tape sealed with cover tape 1500 g 12/13 DA6283.002 11 November, 2010 ORDERING INFORMATION Product Code Output Frequency Package MAS6283AATG00 MAS6283AASN06 MAS6283ABTG00 MAS6283ACTG00 MAS6283AETG00 fc fc fc / 2 fc / 4 fc / 16 EWS tested wafers 215 µm MSOP-8, T&R 5000 pcs / r, Pb free RoHS EWS tested wafers 215 µm EWS tested wafers 215 µm EWS tested wafers 215 µm Contact Micro Analog Systems Oy for divider options. Contact Micro Analog Systems Oy for other wafer thickness. ◆ The formation of product code Product name MAS6283 Design version A Output frequency A = fc B = fc / 2 C = fc / 4 E = fc / 16 Package type Delivery format TG = 215 µm thick EWS tested wafer SN = MSOP Pb free RoHS 00 = tested wafer 06 = tape & reel LOCAL DISTRIBUTOR MICRO ANALOG SYSTEMS OY CONTACTS Micro Analog Systems Oy Kutomotie 16 FI-00380 Helsinki, FINLAND Tel. +358 10 835 1100 Fax +358 10 835 1119 http://www.mas-oy.com NOTICE Micro Analog Systems Oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or performance and to supply the best possible products. Micro Analog Systems Oy assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Micro Analog Systems Oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. 13/13