DA6279D8.000 16 June 2016 MAS6279D8 IC FOR 5.00 – 64.00 MHz VCTCXO Fifth Order Compensation Frequency Stability ± 0.10 ppm Wide Frequency Range Very Low Phase Noise Minimum Operating Temperature –40 °C EEPROM Selectable Output Tri State Output DESCRIPTION The MAS6279D8 is an integrated circuit well suited to build high end VCTCXO for telecommunication. The trimming is done through a serial bus and the calibration information is stored in an internal EEPROM. FEATURES Very small size Minimal current consumption Wide operating temperature range Very low phase noise Minimum operating temperature –40 °C Oscillator frequency output selectable by EEPROM direct or fXTAL/2. Output waveform selectable by EEPROM: clipped sine wave or CMOS. Possibility to use just a compensation part To build a VCTCXO only a crystal is required in addition to MAS6279D8. The compensation method is fully analog, working continuously without generating any steps or other interference. APPLICATIONS (VC)TCXO for high end telecommunications systems (VC)TCXO for GPS (VC)TCXO for Stratum (VC)TCXO for Picocell (VC)TCXO for Femtocell 1 (12) DA6279D8.000 16 June 2016 BLOCK DIAGRAM VDD DA CLK EEPROM+RO TEST(3:0) INF(7:0) LIN(8:0) SQ(7:0) CUB(7:0) FOUR(7:0) FIFTH(7:0) OFS(4:0) TCXO CDACC(4:0) DRV CDACF(4:0) DIV PGM SC (from XOPD testmux) NF POLYNOMIAL TIN Thermal sensor f(T) = Ax5+Bx4 + Cx3+ Dx2+Ex+F TEST MUX VREF bandgap MOUT NOISE FILTER XO core f | f/2 OUT VC VDD CDACC To all blocks VSS XIN Buffers+dividers (Clipped sinewave/ CMOS output) CDACF XOUT Figure 1. Block diagram of MAS6279D8. 2 (12) DA6279D8.000 16 June 2016 ABSOLUTE MAXIMUM RATINGS All Voltages with Respect to Ground Parameter Symbol Supply Voltage Voltage Range for All Pins VDD VIN Latchup Current Limit ILUT Junction Temperature Storage Temperature TJ max TS Conditions For all pins, test according to JESD78A. Min Max Unit -0.3 -0.3 5.0 VDD +0.3 V V -100 +100 mA oC -55 +150 +125 ±1 kV Human Body Model (HBM) ESD Rating oC Note 1) Note 1: See EEPROM memory data retention at hot temperature. Storage or bake at hot temperatures will reduce data retention time of programmed EEPROM bits. Note: The absolute maximum rating values are stress ratings only. Functional operation of the device at conditions between maximum operating conditions and absolute maximum ratings is not implied. Exposure to these conditions for extended periods may affect device reliability (e.g. hot carrier degradation, oxide breakdown). Applying conditions above absolute maximum ratings may be destructive to the devices. Note: This is a CMOS device and therefore it should be handled carefully to avoid any damage by static voltages (ESD). RECOMMENDED OPERATION CONDITIONS All Voltages with Respect to Ground Parameter Symbol Supply Voltage Supply Voltage at EEPROM Programming Operating Temperature Crystal Pulling Sensitivity Crystal Load Capacitance VDD VDD Crystal Rs Rs TA S CL Conditions Min Typ Max Unit Note T=+25°C 2.6 3.0 3.3 3.3 3.6 3.6 V V 1) -40 +25 32 8 +85 44 20 50 °C ppm/pF pF Ω VC = 1.65V Note 1: The recommended condition for EEPROM programming is room temperature. Note: The device performance may deteriorate in the long run if the Recommended Operation Conditions limits are continuously exceeded. ELECTRICAL CHARACTERISTICS (recommended operating conditions) Parameter Symbol Conditions Min EEPROM size EEPROM data retention Serial Bus (DA/CLK) Clock Frequency Input High Voltage (DA/CLK) Input Low Voltage (DA/CLK) TA = +85 °C TA = +125 °C 10 fCLK VIH VIL 80% VDD 0% VDD Typ Max Unit 70 bit 24 1 years 100 kHz 100% VDD 20% VDD V Note V 3 (12) DA6279D8.000 16 June 2016 ELECTRICAL CHARACTERISTICS TA = -40oC to +85oC, VDD = 2.6V to 3.6V, Typ TA = 25oC, Typ VDD = 3.3 V, Typ VC = 1.65 V, fXTAL = 26MHz unless otherwise noted Parameter Symbol Conditions Min Typ Max Unit Note Crystal Frequency Range fXTAL 10.00 64.00 MHz 1) Output Frequency Range fo 5.00 64.00 MHz 1) Voltage Control Range VC 0 VDD V 2) Voltage Control Sensitivity VCSENS 5 ppm/V 3) Voltage Control Linearity Frequency vs. Supply Voltage, Clipped Sinewave Output Frequency vs. Supply Voltage, CMOS Output Frequency vs. Load Change VCLIN ±10 % 4) ±0.1 ppm 5) ±0.1 ppm 5) ±0.1 ppm 6) Output Voltage (10 kΩ || 10 pF) Vout Vpp 7) Output Voltage (15 pF) Vout Vpp 8) Output Voltage Levels dfo dfo VDD ± 5% VDD ± 5% dfo 0.8 1.0 VDD VOHOUT 0.8*VDD VDD 8) VOLOUT 0 0.2*VDD 8) Rise and Fall Time 3 Duty Cycle 40 Supply Current, Clipped Sinewave Output IDD Supply Current, CMOS Output IDD Compensated Frequency Stability Over Temperature dfo Compensation Range Linear Part Compensation Range Inflection Point Compensation Range Cubic Part Amplitude Start up Time Tri State Output Control Input Output OFF State (High-Z) Output ON State 1.65 10 MHz 26 MHz 40 MHz 52.5 MHz 10 MHz 26 MHz 40 MHz 52.5 MHz -40 oC …+85 oC -20 oC …+70 oC 0 oC …+60 oC 0.9 1.6 50 1.3 2.0 2.5 2.7 1.8 2.8 4.1 6.3 ns 60 2.8 3.6 % mA mA ±0.28 ±0.14 ±0.10 ppm a1 -0.6 -0.37 -0.1 ppm/K INF 20 28 36 oC a3 VILDA VIHDA 12/K3 2 DA pin voltage DA LOW DA HIGH 0 VDD-0.6 9) 10- 105 TSTART 8) ms 0.55 VDD V Note 1: Frequency division by two is selected by EEPROM bit DIV: 0=no division, 1=div by 2. Thus output frequency range is 5-64 MHz. Note 2: If VC is not needed, it should be left unconnected (floating) and TCXO bit set TCXO=1. Note 3: Depending on a crystal pulling Note 4: VC=1.65V ± 1.0V, VDD=3.3V Note 5: With divider Note 6: Clipped sinewave output: 10 kΩ || 10 pF ± 10%. CMOS output: 15 pF ± 10% Note 7: Clipped sinewave output only Note 8: CMOS output only Note 9: With proper crystals 4 (12) DA6279D8.000 16 June 2016 ELECTRICAL CHARACTERISTICS TA = -40oC to +85oC, VDD = 2.6V to 3.6V, Typ TA = 25oC, Typ VDD = 3.3 V, Typ VC = 1.65 V, fXTAL = 26MHz unless otherwise noted Parameter Symbol Conditions Min Typ Max Unit Note -57 -83 -113 -138 -148 -152 dBc/Hz 1) φn CLIPPED SINEWAVE @ 1Hz @ 10Hz @ 100Hz @ 1kHz @ 10kHz @ 100kHz -62 -82 -113 -139 -149 -153 dBc/Hz 1) φn CMOS @ 1Hz @ 10Hz @ 100Hz @ 1kHz @ 10kHz @ 100kHz -56 -88 -118 -135 -145 -151 dBc/Hz 1) φn CLIPPED SINEWAVE + DIVIDER @ 1Hz @ 10Hz @ 100Hz @ 1kHz @ 10kHz @ 100kHz -62 -89 -119 -135 -146 -152 dBc/Hz 1) φn CMOS + DIVIDER @ 1Hz @ 10Hz @ 100Hz @ 1kHz @ 10kHz @ 100kHz Phase Noise Note 1: Not measured in production testing PHASE NOISE (fXTAL=26MHz) -50 -60 -70 -80 PN [dBc/Hz] -90 -100 -110 -120 -130 -140 -150 -160 1 10 100 1000 10000 100000 1000000 Offset [Hz] CLIPPED SINE WAVE CMOS CLIPPED SINE WAVE WITH DIVIDER CMOS WITH DIVIDER Figure 2. Phase noise with 26MHz crystal at clipped sinewave / CMOS output and without / with divider 5 (12) DA6279D8.000 16 June 2016 RECOMMENDED CRYSTAL TEMPERATURE CHARACTERISTIC Crystal cut angle determines crystal’s temperature characteristic. The cut angle can be selected to minimize crystal’s temperature dependency in the temperature range of interest. Table 1 below shows theoretical AT-cut crystal cut angles minimizing crystal batch temperature dependency at five different temperature ranges. In the optimization calculations the inflection temperature of the crystal has been +29°C and cut angle control tolerance ±0.12’. The cut angle values are in angular minutes (1‘=1/60th of 1°) relative to AT-cut crystal angle 35° 15’. Table 1. AT-cut crystal cut angles to minimize crystal’s temperature dependency Temperature range AT crystal cut angle Nominal crystal’s temperature dependency 0°C…+60°C 1.13’ ±1.1ppm (2.2ppm p-p) -10°C…+60°C -20°C…+70°C -30°C…+85°C -40°C…+85°C 1.70’ 2.55’ 3.57’ 4.77’ ±2.1ppm (4.2ppm p-p) ±3.8ppm (7.6ppm p-p) ±6.3ppm (12.6ppm p-p) ±9.7ppm (19.8ppm p-p) Figure 3 below illustrates theoretical temperature characteristic of above five cut angle crystals for different temperature ranges. The widest temperature range -40°C…+85°C requires largest cut angle and the narrowest temperature range 0°C…+60°C smallest cut angle. Figure 3. Temperature characteristic of five AT-cut crystals with different cut angles 6 (12) DA6279D8.000 16 June 2016 DEVICE OUTLINE CONFIGURATION DFN-10 3 x 3 x 0.75 Top View G = Green D8 = Version Y = Year WW = Week 7 (12) DA6279D8.000 16 June 2016 PACKAGE (DFN-10 3x3x0.75) OUTLINE D D/2 E/2 TOP VIEW A3 A PIN 1 MARK AREA SIDE VIEW A1 SEATING PLANE D2 b D2/2 E2/2 E2 L SHAPE OF PIN #1 IDENTIFICATION IS OPTIONAL BOTTOM VIEW e Symbol Min Nom EXPOSED PAD Max PACKAGE DIMENSIONS A 0.700 0.750 0.800 A1 0.000 0.020 0.050 A3 0.178 --0.228 b 0.200 --0.300 D 2.950 3.000 3.050 D2 (Exposed.pad) 2.500 --2.700 E 2.950 3.000 3.050 E2 (Exposed.pad) 1.650 --1.750 e 0.500 BSC L 0.350 --0.450 Dimensions do not include mold or interlead flash, protrusions or gate burrs. Unit mm mm mm mm mm mm mm mm mm mm 8 (12) DA6279D8.000 16 June 2016 SOLDERING INFORMATION For Lead-Free / Green DFN 3mm x 3mm x 0.75mm Resistance to Soldering Heat Maximum Temperature Maximum Number of Reflow Cycles Reflow profile According to RSH test IEC 68-2-58/20 260C 3 Thermal profile parameters stated in IPC/JEDEC J-STD-020 should not be exceeded. http://www.jedec.org 7.62 - 25.4 µm, Matte Tin Lead Finish EMBOSSED TAPE SPECIFICATIONS P2 PO P1 D0 T X E F W B0 R 0.25 typ K0 X A0 User Direction of Feed Orientation on tape Dimension Ao Bo Do E F Ko Po P1 P2 T W Min/Max 3.30 0.10 3.30 0.10 1.50 +0.1/-0.0 1.75 5.50 0.05 1.10 0.10 4.0 8.0 0.10 2.0 0.05 0.3 0.05 12.00 0.3 All dimensions in millimeters Unit mm mm mm mm mm mm mm mm mm mm mm 9 (12) DA6279D8.000 16 June 2016 REEL SPECIFICATIONS W2 A D C Tape Slot for Tape Start N B W1 Carrier Tape Cover Tape End Start Trailer Dimension Components Min A B C D N W 1 (measured at hub) W 2 (measured at hub) Trailer Leader 1.5 12.80 20.2 100 12.4 Leader Max Unit 330 mm mm mm mm mm mm mm mm mm 13.50 14.4 18.4 160 390, of which minimum 160 mm of empty carrier tape sealed with cover tape 3000 Components on Each Reel Reel Material: Conductive, Plastic Antistatic or Static Dissipative Carrier Tape Material: Conductive Cover Tape Material: Static Dissipative 10 (12) DA6279D8.000 16 June 2016 ORDERING INFORMATION Product Code Product Package MAS6279D8WAD00 MAS6279D8WAB05 MAS6279D8HP06 IC for VCTCXO IC for VCTCXO IC for VCTCXO EWS Tested wafer, thickness 370 μm Tested 180 μm thick dice in waffle pack DFN-10 3x3x0.75, T&R 3000 pcs / reel, Pb free RoHS Contact Micro Analog Systems Oy for other wafer and die thickness options. Product code details Product name Design version Package type Delivery format MAS6279 D8 WAB = 180 μm thick EWS tested wafer or die WAD = 370 μm thick EWS tested wafer or die HP = DFN-10 3x3x0.75 mm 00 = tested wafer 05 = waffle pack 06 = T&R 3000 pcs LOCAL DISTRIBUTOR MICRO ANALOG SYSTEMS OY CONTACTS Micro Analog Systems Oy Kutomotie 16 FI-00380 Helsinki, FINLAND Tel. +358 10 835 1100 Telefax +358 10 835 1119 http://www.mas-oy.com NOTICE Micro Analog Systems Oy (MAS) reserves the right to make changes to the products contained in this data sheet in order to improve the design or performance and to supply the best possible products. MAS assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and MAS makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. MAS products are not authorized for use in safety-critical applications (such as life support) where a failure of the MAS product would reasonably be expected to cause severe personal injury or death. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safetyrelated requirements concerning their products and any use of MAS products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by MAS. Further, Buyers must fully indemnify MAS and its representatives against any damages arising out of the use of MAS products in such safety-critical applications. MAS products are neither designed nor intended for use in military/aerospace applications or environments. Buyers acknowledge and agree that any such use of MAS products which MAS has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. MAS products are neither designed nor intended for use in automotive applications or environments. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, MAS will not be responsible for any failure to meet such requirements. 11 (12) DA6279D8.000 16 June 2016 DOCUMENT VERSION HISTORY 000 Initial version 12 (12)