ISL8200AM Datasheet

DATASHEET
Complete Current Share 10A DC/DC Power Module
ISL8200AM
Features
The ISL8200AM is a simple and easy to use high power,
current-sharing DC/DC power module for Datacom/Telecom/
FPGA power hungry applications. All that is needed is the
ISL8200AM, a few passive components and one VOUT setting
resistor to have a complete 10A design ready for market.
• Complete switch mode power supply in one package
• Patented current share architecture reduces layout
sensitivity when modules are paralleled
• Programmable phase shift (1- to 6-phase)
• Extremely low profile (2.2mm height)
The ease of use virtually eliminates the design and
manufacturing risks while dramatically improving time to
market.
• Input voltage range +3V to +20V at 10A, current share up to
60A
Need more output current? Parallel up to six ISL8200AM
modules to scale up to a 60A solution (see Figure 7 on
page 10).
• A single resistor sets VOUT from +0.6V to +6V
The simplicity of the ISL8200AM is in its "off-the-shelf",
unassisted implementation versus a discrete implementation.
Patented current sharing in multiphase operation greatly
reduces ripple currents, BOM cost and complexity. For
example, parallel 2 for 20A and up to 6 for 60A. The output
voltage can be precisely regulated to as low as 0.6V with ±1%
output voltage regulation over line, load and temperature
variations.
• RoHS compliant
• Output overvoltage, overcurrent and over-temperature
protection and undervoltage indication
The ISL8200AM’s thermally enhanced, compact QFN package,
operates at full load and over-temperature, without requiring
forced air cooling. It's so thin it can even fit on the backside of
the PCB. Easy access to all pins with few external components,
reduces the PCB design to a component layer and a simple
ground layer.
Complete Functional Schematic
EN
FF
ISL8200AM
POWER MODULE
VOUT_SET
• Industrial and medical equipment
• Point of load regulation
Related Literature
• AN1738 “ISL8200AMEV1PHZ Evaluation Board User’s
Guide”
• ISL8200AM iSim Model - (Product Information Page)
• AN1786 “Reducing the Switching Frequency of the
ISL8200M and ISL8200AM Power Modules”
ISL8200AM Package
V0UT =
0.6V TO 6.0V
RSET
2.2mm
VSEN_REM-
ISHARE
PGND
PVCC
CIN2
CIN1
VOUT
PVIN
VIN
ISET
R2
R1
PVIN = 3V TO 20V
• Servers, telecom and datacom applications
330µF
VIN = 4.5V TO 20V
Applications
PGND1
10µF
15
5k
NOTE: For input voltage higher than 4.5V, VIN can be tied to PVIN directly
(see Figure 24 on page 13 for details).
FIGURE 1. COMPLETE 10A DESIGN, JUST SELECT RSET FOR THE
DESIRED VOUT
July 30, 2015
FN8271.5
1
m
m
15
mm
FIGURE 2. THE 2.2mm HEIGHT IS IDEAL FOR THE BACKSIDE OF
PCB WHEN SPACE AND HEIGHT IS A PREMIUM
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2012, 2013, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL8200AM
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
TEMP.
RANGE (°C)
PART MARKING
ISL8200AMIRZ
ISL8200AM
ISL8200AMEV1PHZ
Evaluation Board
PACKAGE
(RoHS Compliant)
-40°C to +85°C
23 Ld QFN
PKG.
DWG. #
L23.15x15
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8200AM. For more information on MSL please see techbrief TB363.
Pinout Internal Circuit
VCC
PVCC
PVIN
21
14
17
RCC
ISL8200AM
MODULE
5
CF1
CF2
BOOT1
LDO
VIN 13
UGATE1
Q1
CBOOT1
EN 12
LOUT1
PHASE1
FF 11
330nH
19
VOUT
18
PGND
16
PHASE
20
OCSET
1
VOUT_SET
2
VSEN_REM-
VCC
RPG
10k
PGOOD 22
VCC
LGATE1
INTERNAL PGOOD
RCLK
10k
CLKOUT
8
PH_CNTRL
9
Q2
ISEN1A
VCC
RPHC
10k
RISEN-IN
CONTROLLER
2.2k
ISEN1B
ISET
5
CF3
ISHARE
COMP
6
ZCOMP1
CF4
FB1
ISHARE_BUS 10
VMON1
ISFETDRV
3
FSYNC_IN
7
ZCOMP2
VSEN1+
RFS
59k
VSEN1-
15
4
PGND1
PGND1
RCSR
CVSEN
ROS1
2.2k
FIGURE 3. PINOUT INTERNAL CIRCUIT
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ISL8200AM
Pin Configuration
(1) VOUT_SET
(2) VSEN_REM-
(3) ISFETDRV
(4) PGND1
(5) ISET
(6) ISHARE
(7) FSYNC_IN
(8) CLKOUT
(9) PH_CNTRL
(10) ISHARE_BUS
(11) FF
ISL8200AM
(23 LD QFN)
TOP VIEW
(12) EN
(23) N.C.
(13) VIN
(22) PGOOD
(21) VCC
(14) PVCC
(20) OCSET
(15) PGND1
(16) PHASE
PD1
(17) PVIN
PD2
PD3
(18) PGND
PD4
(19) VOUT
Pin Descriptions
PIN #
PIN NAME
PIN DESCRIPTION
1
VOUT_SET
2
VSEN_REM-
3
ISFETDRV
4, 15
PGND1
Normal Ground - All voltage levels are referenced to this pad. This pad provides a return path for the low-side MOSFET drivers
and internal power circuitries as well as all analog signals. PGND and PGND1 should be connected together with a ground
plane.
5
ISET
Analog Current Output - This pin sources a 15µA offset current plus Channel 1’s average current. The voltage (VISET) set by
an external resistor (RISET) represents the average current level of the local active module. For full-scale current, RISET
should be ~10kΩ. The output current range is 15µA to 126µA typical.
The ISET and ISHARE pins are used for current sharing purposes with multiple ISL8200AM modules. In the single module
configuration, this pin can be tied to the ISHARE pin. In multiphase operation, if noise is a concern, add an additional 10pF
capacitor to the ISET line.
Analog Voltage Input - Used with VOUT to program the regulator output voltage. The typical input impedance of VOUT_SET
with respect to VSEN_REM- is 500kΩ. The voltage input typical is 0.6V.
Analog Voltage Input - This pin is the negative input of standard unity gain operational amplifier for differential remote sense
for the regulator, and should connect to the negative rail of the load/processor. This pin can be used for VOUT trimming by
connecting a resistor from this pin to the VOUT_SET pin.
Digital Output - This pin is used to drive an optional NFET, which will connect ISHARE with the system ISHARE bus upon
completing a pre-bias start-up. The voltage output range is 0V to 5V.
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Pin Descriptions (Continued)
PIN #
PIN NAME
PIN DESCRIPTION
6
ISHARE
Analog Current Output - Cascaded system level overcurrent shutdown pin. This pin is used where you have multiple modules
configured for current sharing and is used with a common current share bus. The bus sums each of the modules' average
current contribution to the load to protect for a overcurrent condition at the load. The pin sources 15µA plus average module's
output current. The shared bus voltage (VISHARE) is developed across an external resistor (RISHARE). VISHARE represents the
average current of all active channel(s) that are connected together.
The ISHARE bus voltage is compared with each module's internal reference voltage set by each module's RISET resistor. This
will generate an individual current share error signal in each cascaded controller. The share bus impedance RISHARE should
be set as RISET/NCTRL, RISET divided by the number of active current sharing controllers. The output current from this pin
generates a voltage across the external resistor. This voltage, VISHARE, is compared to an internal 1.2V threshold for average
overcurrent protection. For full-scale current, RISHARE should be ~10kΩ. Typically 10kΩ is used for RSHARE and RSET. The
output current range is 15µA to 126µA typical.
7
FSYNC_IN
Analog Input Control Pin - An optional external resistor (RFS-ext) connected to this pin and ground will increase the oscillator
switching frequency. It has an internal 59kΩ resistor for a default frequency of 700kHz. The internal oscillator will lock to an
external frequency source when connected to a square waveform. The external source is typically the CLKOUT signal from
another ISL8200AM or an external clock. The internal oscillator synchronizes with the leading positive edge of the input
signal. The input voltage range for the external source is 0V to 5V square wave. When not synchronized to an external clock,
a 100pF capacitor between FSYNC_IN and PGND1 is recommended.
8
CLKOUT
Digital Voltage Output - This pin provides a clock signal to synchronize with other ISL8200AM(s). When there is more than
one ISL8200AM in the system, the two independent regulators can be programmed via PH_CNTRL for different degrees of
phase delay.
9
PH_CNTRL
Analog Input - The voltage level on this pin is used to program the phase shift of the CLKOUT clock signal to synchronize with
other module(s).
10
ISHARE_BUS
Open pin until first PWM pulse is generated. Then, via an internal FET, this pin connects the module’s ISHARE to the system’s
ISHARE bus after pre-bias is complete and soft-start is initiated.
11
FF
Analog Voltage Input - The voltage on this pin is fed into the controller, adjusting the sawtooth amplitude to generate the
feed-forward function. The input voltage range is 0.8V to VCC. Typically, FF is connected to EN.
12
EN
This is a double function pin: Analog Input Voltage - The input voltage to this pin is compared with a precision 0.8V reference
and enables the digital soft-start. The input voltage range is 0V to VCC or VIN through a pull-up resistor maintaining a typical
current of 5mA.
Analog Voltage Output - This pin can be used as a voltage monitor for input bus undervoltage lockout. The hysteresis levels
of the lockout can be programmed via this pin using a resistor divider network. Furthermore, during fault conditions (such as
overvoltage, overcurrent, and over-temperature), this pin is used to communicate the information to other cascaded modules
by pulling the wired OR low as it is an open drain. The output voltage range is 0V to VCC.
13
VIN
Analog Voltage Input - This pin should be tied directly to the input rail when using the internal linear regulator. It provides
power to the internal linear drive circuitry. When used with an external 5V supply, this pin should be tied directly to PVCC. The
internal linear device is protected against the reversed bias generated by the remaining charge of the decoupling capacitor
at VCC when losing the input rail. The input voltage range is 4.5V to 20V.
14
PVCC
Analog Output - This pin is the output of the internal series linear regulator. It provides the bias for both low-side and high-side
drives. Its operational voltage range is 4.5V to 5.6V. The decoupling ceramic capacitor in the PVCC pin is 10µF.
16
PHASE
17
PVIN
Analog Input - This input voltage is applied to the power FETs with the FETs ground being the PGND pin. It is recommended
to place input decoupling capacitance, 22µF, directly between the PVIN pin and the PGND pin as close as possible to the
module. The input voltage range is 3V to 20V.
18
PGND
All voltage levels are referenced to this pad. This is the low-side MOSFET ground. PGND and PGND1 should be connected
together with a ground plane.
19
VOUT
Output voltage from the module. The output voltage range is 0.6V to 6V.
20
OCSET
Analog Input - This pin is used with the PHASE pin to set the current limit of the module. The input voltage range is 0V to 30V.
21
VCC
Analog Input - This pin provides bias power for the analog circuitry. It’s operational range is 4.5V to 5.6V. In 3.3V applications,
VCC, PVCC and VIN should be shorted to allow operation at the low end input as it relates to the VCC falling threshold limit.
This pin can be powered either by the internal linear regulator or by an external voltage source.
22
PGOOD
Analog Output - This pin, pulled up to VCC via an internal 10kΩ resistor, provides a power-good signal when the output is within
9% of nominal output regulation point with 4% hysteresis (13%/9%) and soft-start is complete. An external pull-up is not
required. PGOOD monitors the outputs (VMON1) of the internal differential amplifiers. The output voltage range is 0V to VCC.
Analog Output - This pin is the phase node of the regulator. The output voltage range is 0V to 30V.
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ISL8200AM
Pin Descriptions (Continued)
PIN #
PIN NAME
23
N.C.
PIN DESCRIPTION
Not internally connected
PD1 Phase Thermal Pad Used for both the PHASE pin (Pin 16) and for heat removal connecting to heat dissipation layers using vias. Connect this pad
to a copper island on the PCB board with the same shape as the pad; this is electrically connected to PHASE Pin 16.
PD2
PVIN Thermal Pad Used for both the PVIN pin (Pin 17) and for heat removal connecting to heat dissipation layers using vias. Connect this pad
to a copper island on the PCB board with the same shape as the pad; this is electrically connected to PVIN Pin 17.
PD3 PGND Thermal Pad Used for both the PGND pin (Pin 18) and for heat removal connecting to heat dissipation layers using vias. Connect this pad
to a copper island on the PCB board with the same shape as the pad; this is electrically connected to PGND Pin 18.
PD4
VOUT Thermal Pad Used for both the VOUT pin (Pin 19) and for heat removal connecting to heat dissipation layers using vias. Connect this pad
to a copper island on the PCB board with the same shape as the pad; this is electrically connected to VOUT Pin 19.
Typical Application Circuits
RSET
VOUT_SET
FF
2.2k
ISL8200AM
FSYNC_IN
PGOOD
CLKOUT
VCC
PVCC
PGND1
PGND
PHASE
OCSET
ISET
VCC
10µF
C209
RSET CAN CHANGE VOUT
Refer to Table 1
5k
ISHARE
ISFETDRV
RISHARE1
DO NOT TIE EN DIRECTLY TO A POWER SOURCE
PGOOD
PH_CNTRL
ISHARE_BUS
SET R1 AND R2 SUCH THAT
0.8V ≤ VEN ≤ 5.0V
GROUND
VSEN_REM-
EN
ISFETDRV1
330µF
VIN
VOUT
VOUT
VOUT
C9
22µF
PVIN
1nF
2.05k
R2
GROUND
C211
R1
8.25k
C203
270µF
C3
PVIN
FIGURE 4. SINGLE PHASE 10A 1.2V OUTPUT CIRCUIT
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22µF
C203
R1
PVIN
26.7k
270µF
PVIN
C3
VOUT
1nF
C211
R2
C9
100µF (x6)
VOUT_SET
FF
10k
GROUND
VSEN_REM-
EN
ISL8200AM
FSYNC_IN
6
CLKOUT
PGOOD
PGOOD
2.2nF
PH_CNTRL
ISHARE_BUS
VCC
VCC1
PVCC
PGND1
PGND
PHASE
ISET
OCSET
ISFETDRV
ISHARE
ISFETDRV1
VOUT
VOUT
RSET1
VIN
GROUND
2.61k
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Typical Application Circuits (continued)
22µF
C303
10µF
C209
10k
RISET1
PVIN
VOUT
VIN
VOUT
RSET2
VOUT_SET
1nF
C311
FF
10k
VSEN_REM-
EN
ISL8200AM
FSYNC_IN
CLKOUT
PGOOD
PH_CNTRL
ISHARE_BUS
VCC
VCC2
PVCC
PGND1
PGND
PHASE
ISET
OCSET
ISFETDRV
ISHARE
ISFETDRV2
PGOOD
10µF
C309
10k
RISET2
ISHARE
FN8271.5
July 30, 2015
FIGURE 5. TWO PHASE 20A 3.3V OUTPUT CIRCUIT
2.2nF
ISL8200AM
RISHARE1 5k
ISHARE
ISL8200AM
Absolute Maximum Ratings
Thermal Information
Input Voltage, PVIN, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +27V
Driver Bias Voltage, PVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V
Signal Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
BOOT/UGATE Voltage, VBOOT . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +36V
Phase Voltage, VPHASE . . . . . . . . . . . . . . . . . . . VBOOT - 7V to VBOOT + 0.3V
BOOT to PHASE Voltage,
VBOOT - VPHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V
Input, Output or I/O Voltage . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 2kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 200V
Charge Device Model (Tested per JESD22-C101C). . . . . . . . . . . . . . . 1kV
Latch-up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
QFN Package (Notes 4, 5) . . . . . . . . . . . . . .
13
2
Maximum Storage Temperature Range . . . . . . . . . . . . . .-55°C to +150°C
Typical Reflow Profile . . . . . . . . . . . . . . . . . . . . . . See Figure 42 on page 21
Recommended Operating Conditions
Input Voltage
PVIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 20V
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 20V
Driver Bias Voltage, PVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.6V
Signal Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.6V
Boot to Phase Voltage
VBOOT - VPHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <6V
Industrial Ambient Temperature Range . . . . . . . . . . . . . . . -40°C to +85°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board (i.e., 4-layer type without thermal vias see tech brief TB379) per JEDEC standards except that the top and bottom layers assume solid plains.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL
TEST CONDITIONS
MIN
(Note 7)
TYP
(Note 6)
MAX
(Note 7)
UNIT
VCC SUPPLY CURRENT
Nominal Supply VIN Current
IQ_VIN
PVIN = VIN = 20V; No Load; fSW = 700kHz
36
mA
Nominal Supply VIN Current
IQ_VIN
PVIN = VIN = 4.5V; No Load; fSW = 700kHz
27
mA
IVCC
EN = 0V, VCC = 2.97V
9
mA
Maximum Current
IPVCC
PVCC = 4V to 5.6V
320
mA
Saturated Equivalent Impedance
RLDO
P-Channel MOSFET (VIN = 5V)
1
Ω
PVCC Voltage Level (Note 8)
PVCC
IPVCC = 0mA, VIN = 12V
Shutdown Supply VCC Current
INTERNAL LINEAR REGULATOR
5.15
5.4
5.60
V
Rising VCC Threshold
2.85
2.97
V
Falling VCC Threshold
2.65
2.75
V
Rising PVCC Threshold
2.85
2.97
V
Falling PVCC Threshold
2.65
2.75
V
POWER-ON RESET (Note 8)
System Soft-start Delay
tSS_DLY
After PLL, VCC, and PVCC PORs, and EN above
their thresholds
384
Cycles
ENABLE (Note 8)
Turn-On Threshold Voltage
Hysteresis Sink Current
IEN_HYS
Undervoltage Lockout Hysteresis
VEN_HYS
0.75
0.8
0.86
V
21
30
35
µA
VEN_RTH = 10.6V; VEN_FTH = 9V
1.6
RUP = 53.6kΩ, RDOWN = 5.23kΩ
Sink Current
IEN_SINK
VEN = 1V
Sink Impedance
REN_SINK
VEN = 1V
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V
15.4
mA
64
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ISL8200AM
Electrical Specifications
PARAMETER
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
TEST CONDITIONS
MIN
(Note 7)
TYP
(Note 6)
MAX
(Note 7)
UNIT
OSCILLATOR
Oscillator Frequency
FOSC
Total Variation (Note 8)
RFS = 59kΩFigure 35
VCC = 5V;
700
-9
kHz
+9
%
1500
kHz
FREQUENCY SYNCHRONIZATION AND PHASE LOCK LOOP (Note 7)
Synchronization Frequency
VCC = 5.4V
PLL Locking Time
VCC = 5.4V; fSW = 700kHz
Input Signal Duty Cycle Range
FOSC
210
10
µs
90
%
410
ns
PWM (Note 8)
Minimum PWM OFF Time
tMIN_OFF
Current Sampling Blanking Time
tBLANKING
310
345
175
ns
OUTPUT CHARACTERISTICS
Output Continuous Current Range
IOUT(DC)
VOUT/VIN
Line Regulation Accuracy
VOUT/IOUT
Load Regulation Accuracy
VOUT
Output Ripple Voltage
PVIN = VIN = 12V, VOUT = 1.2V
0
10
A
VOUT = 1.2V, IOUT = 0A, PVIN = VIN = 3.5V to 20V
0.15
%
VOUT = 1.2V, IOUT = 10A, PVIN = VIN = 5V to 20V
0.15
%
IOUT = 0A to 10A, VOUT = 1.2V, PVIN = VIN = 12V
0.1
%
IOUT = 10A, VOUT = 1.2V, PVIN = VIN = 12V
27
mVP-P
IOUT = 0A, VOUT = 1.2V, PVIN = VIN = 12V
19
mVP-P
DYNAMIC CHARACTERISTICS
Voltage Change for Positive Load Step
VOUT-DP
IOUT = 0A to 5A. Current slew rate = 2.5A/µs,
PVIN = VIN = 12V, VOUT = 1.2V
45
mVP-P
Voltage Change for Negative Load Step
VOUT-DN
IOUT = 5A to 0A. Current slew rate = 2.5A/µs,
PVIN = VIN = 12V, VOUT = 1.2V
55
mVP-P
0.6
V
REFERENCE (Note 8)
Reference Voltage (Include Error and
Differential Amplifiers’ Offsets)
VREF
-0.75
0.75
%
DIFFERENTIAL AMPLIFIER (Note 8)
DC Gain
UG_DA
Unity Gain Bandwidth
Unity Gain Amplifier
UGBW_DA
VSEN+ Pins Input Current
IVSEN+
Maximum Source Current for Current
Sharing
IVSEN1-
RVSEN+_to
_VSEN-
Input Impedance
0.2
VSEN1- source current for current sharing
when parallel multiple modules each of which
has its own voltage loop
VVSEN+/IVSEN+, VVSEN+ = 0.6V
Output Voltage Swing
Input Common Mode Range
Disable Threshold
VVSEN-
0
dB
5
MHz
1.16
2.5
µA
350
µA
-500
kΩ
0
VCC - 1.8
V
-0.2
VCC - 1.8
V
VMON1 = Tri-state
VCC - 0.4
V
111
µA
OVERCURRENT PROTECTION (Note 8)
Channel Overcurrent Limit
Channel Overcurrent Limit
Share Pin OC Threshold
ISOURCE
VCC = 2.97V to 5.6V
ISOURCE
VCC = 5V;
VOC_ISHARE
Comparator offset included
89
111
129
µA
1.16
1.20
1.22
V
CURRENT SHARE
External Current Share Accuracy
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Up to 3 phases
8
±10
%
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ISL8200AM
Electrical Specifications
PARAMETER
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
TEST CONDITIONS
MIN
(Note 7)
TYP
(Note 6)
MAX
(Note 7)
UNIT
-15
-13
-11
%
POWER GOOD MONITOR (Note 8)
Undervoltage Falling Trip Point
VUVF
Undervoltage Rising Hysteresis
VUVR_HYS
Overvoltage Rising Trip Point
VOVR
Overvoltage Falling Hysteresis
VOVF_HYS
Percentage below reference point
Percentage above UV trip point
Percentage above reference point
4
11
Percentage below OV trip point
13
%
15
4
%
%
PGOOD Low Output Voltage
IPGOOD = 2mA
0.35
V
Sinking Impedance
IPGOOD = 2mA
70
Ω
Maximum Sinking Current
VPGOOD < 0.8V
10
mA
OVERVOLTAGE PROTECTION (Note 8)
OV Latching Trip Point
EN = UGATE = LATCH Low, LGATE = High
OV Non-latching Trip Point
EN = Low, UGATE = Low, LGATE = High
LGATE Release Trip Point
EN = Low/HIGH, UGATE = Low, LGATE = Low
118
120
122
%
113
%
87
%
Over-temperature Trip
150
°C
Over-temperature Release Threshold
125
°C
RCC
5
Ω
Internal Resistor Between PHASE and
OCSET Pins
RISEN-IN
2.2k
Ω
Internal Resistor Between FSYNC_IN
and PGND1 Pins
RFS
59k
Ω
Internal Resistor Between PGOOD and
VCC Pins
RPG
10k
Ω
Internal Resistor Between CLKOUT and
VCC Pins
RCLK
10k
Ω
Internal Resistor Between PH_CNTRL
and VCC Pins
RPHC
10k
Ω
Internal Resistor Between VOUT_SET
and VSEN_REM- pin
ROS1
2.2k
Ω
OVER-TEMPERATURE PROTECTION CONTROLLER JUNCTION TEMPERATURE
INTERNAL COMPONENT VALUES
Internal Resistor Between PVCC and
VCC pin
NOTES:
6. Parameters with TYP limits are not production tested, unless otherwise specified.
7. Parameters with MIN and/or MAX limits are 100% tested for internal IC prior to module assembly, unless otherwise specified. Temperature limits
established by characterization and are not production tested.
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
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FN8271.5
July 30, 2015
ISL8200AM
RSET 2.2k
VOUT_SET
VSEN_REMISL8200AM
FSYNC_IN
47µF (x8)
GROUND
10nF
PGOOD
CLKOUT
PH_CNTRL
ISHARE_BUS
VCC
VOUT = 1.2V for RSET = 2.2k
Refer to Table 1 for RESET vs VOUT
VCC
PVCC
PGND1
PGND
OCSET
PHASE
ISET
10µF
C209
RISHARE1
ISHARE
ISFETDRV
5k
ISFETDRV1
C9
C205
FF
EN
VOUT
VOUT
VOUT
VIN
1nF
4.12k
C211
GROUND
R2
PVIN
22µF
C203
R1
16.5k
270µF
C3
PVIN
FIGURE 6. TEST CIRCUIT FOR ALL PERFORMANCE AND DERATING GRAPHS
Typical Performance Characteristics
TA = +25°C, PVIN = VIN, CIN = 220µFx1, 10µF/ceramic x 2, COUT = 47µF/ceramic x 8.
100
100
95
95
90
90
EFFICIENCY (%)
EFFICIENCY (%)
Efficiency Performance
85
80
3.3V
75
2.5V
1.5V
70
1.2V
0.8V
2
4
6
8
80
75
70
65
65
60
0
85
10
60
0
3.3V
1.5V
1.2V
0.8V
5.0V
2
LOAD CURRENT (A)
FIGURE 7. EFFICIENCY vs LOAD CURRENT (5VIN)
2.5V
4
6
LOAD CURRENT (A)
8
10
FIGURE 8. EFFICIENCY vs LOAD CURRENT (12VIN)
VOUT
100
3.3V
EFFICIENCY (%)
95
2.5V
5.0V
90
VIN = 12V
VOUT = 1.2V
IOUT = 0A TO 5A
85
80
75
70
1.5V
65
60
0
2
4
6
1.2V
8
10
LOAD CURRENT (A)
FIGURE 9. EFFICIENCY vs LOAD CURRENT (20VIN)
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FIGURE 10. 1.2V TRANSIENT RESPONSE
FN8271.5
July 30, 2015
ISL8200AM
Typical Performance Characteristics (Continued)
Transient Response Performance
TA = +25°C, PVIN = VIN = 12V, CIN = 220µFx1, 10µF/ceramic x 2, COUT = 47µF/ceramic x 8
IOUT = 0A to 5A, Current slew rate = 2.5A/µs.
VOUT
VOUT
VIN = 12V
VOUT = 1.8V
IOUT = 0A TO 5A
VIN = 12V
VOUT = 1.5V
IOUT = 0A TO 5A
FIGURE 11. 1.5V TRANSIENT RESPONSE
FIGURE 12. 1.8V TRANSIENT RESPONSE
VOUT
VOUT
VIN = 12V
VOUT = 2.5V
IOUT = 0A TO 5A
VIN = 12V
VOUT = 1.8V
IOUT = 0A TO 5A
FIGURE 13. 2.5V TRANSIENT RESPONSE
FIGURE 14. 3.3V TRANSIENT RESPONSE
PHASE1-M
PHASE2-M
PHASE3-M
PHASE4-S
FIGURE 15. FOUR MODULE CLOCK SYNC (VIN = 12V)
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FN8271.5
July 30, 2015
ISL8200AM
Typical Performance Characteristics (Continued)
Output Ripple Performance
TA = +25°C, PVIN = VIN = 12V, CIN = 220µFx1, 10µF/ceramic x 2, COUT = 100µF/ceramic x 6 IOUT =
No Load, 5, 10A.
VIN = 0V TO 18V
VOUT = 1.2V
IOUT = NO LOAD
VOUT
EN
PGOOD
VOUT
PHASE
FIGURE 16. OVERCURRENT PROTECTION
VOUT NO LOAD
VOUT 5A
VOUT 10A
FIGURE 18. 1.2V OUTPUT RIPPLE
VOUT NO LOAD
VOUT 5A
VOUT 10A
FIGURE 20. 2.5V OUTPUT RIPPLE
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PVIN
PHASE
FIGURE 17. 50% PRE-BIAS START-UP
VOUT NO LOAD
VOUT 5A
VOUT 10A
FIGURE 19. 1.5V OUTPUT RIPPLE
VOUT NO LOAD
VOUT 5A
VOUT 10A
FIGURE 21. 3.3V OUTPUT RIPPLE
FN8271.5
July 30, 2015
ISL8200AM
VOUT
0.6
0.8
1.0
1.2
RSET (Ω)
0
732
1.47k
2.2k
VOUT (V)
1.5
1.8
2.0
2.5
RSET (Ω)
3.32k
4.42k
5.11k
6.98k
VOUT (V)
3.3
5.0
6.0
RSET (Ω)
10k
16.2k
20k
ISL8200AM
POWER MODULE
RSET
VOUT_SET
EN
VSEN_REM-
FF
ISHARE
PVCC
VEN
COUT
PVIN
TABLE 1. VOUT - RSET
VOUT (V)
VOUT
VIN
R2
Note: ISL8200AM has integrated 2.2kΩ resistances into the
module dividing resistor for the bottom side (ROS). The
resistances for different output voltages in single-phase
operation are listed in Table 1.
PVIN = 3.3V
VIN = 5.0V
PGND
(EQ. 1)
ISET
R SET

V OUT = 0.6   1 + ---------------
R OS 

The circuit shown in Figure 25 ensures proper start-up by
injecting current into the ISHARE line until all phases are ready to
start regulating.
CIN1
The ISL8200AM has an internal 0.6V ±0.7% reference voltage.
Programming the output voltage requires a dividing resistor
(RSET) between the VOUT_SET pin and the VOUT regulation point.
The output voltage can be calculated as shown in Equation 1:
CIN2
Programming the Output Voltage (RSET)
as that is the voltage limit on the PVCC pin. Figure 24 is a more
general setup and can accommodate VIN ranges up to 20V; PVCC
is not tied to VIN and hence the control circuitry is powered by the
internal LDO.
R1
Applications Information
PGND1
PVCC = 5.0V
10µF
5k
FIGURE 22. 3.3V OPERATION
CIN
R1
PVIN
VEN
R2
VSEN_REMPVCC
PGND
ISHARE
PGND1
PVCC = VIN
10µF
5k
The equation to determine the minimum PVIN to support the
required VOUT is given by Equations 2 and 3; it is recommended
to add 0.5V to the result to account for temperature variations.
FIGURE 23. 5.0V OPERATION
(EQ. 2)
VIN is the input to the internal LDO that powers the control
circuitry while PVCC is the output of the aforementioned LDO.
PVIN is the power input to the power stage. Figure 22 shows a
scenario where the power stage is running at 3.3V and the
control circuitry is running at 5V; keep in mind that the PVCC pin
is also at 5V to ensure that the LDO is not functioning. Figure 23
shows a setup where both the control circuitry and the power
stage is at a 5V rail. It is imperative to not cross 5.5V in this setup
VEN
R2
For 3.3V input voltage operation, the VIN voltage is
recommended to be 5V for sufficient gate drive voltage. This can
be accomplished by using a voltage greater than or equal to 5V
on VIN, or directly connecting the 5V source to both VIN and PVCC.
RSET
COUT
ISL8200AM
POWER MODULE
VOUT_SET
EN
VSEN_REM-
FF
ISHARE
PVCC
(EQ. 3)
13
PVIN
CIN
PV IN_MIN = 1.43  V OUT
R1
for the 700kHz switching frequency = 1428ns
VOUT
VOUT
VIN
PGND
VIN = 5V-20V
ISET
tSW = switching period = 1/fSW
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RSET
VOUT_SET
EN
FF
The module has a minimum input voltage at a given output
voltage, which needs to be a minimum of 1.43x the output
voltage if operating at fSW = 700kHz switching frequency. This is
due to the Minimum PWM OFF time (tMIN-OFF).
V OUT  t SW
PV IN_MIN = -----------------------------------------t SW – t MIN_OFF
ISL8200AM
POWER MODULE
ISET
The output voltage accuracy can be improved by maintaining the
impedance at VOUTSET (internal VSEN1+) at or below 1kΩ
effective impedance. Note: the impedance between VSEN1+ and
VSEN1- is about 500kΩ.
VOUT
VOUT
VIN
COUT
VIN = 5.0V
DO NOT CROSS 5.5V
PGND1
10µF
5k
FIGURE 24. 5V TO 20V OPERATION
FN8271.5
July 30, 2015
ISL8200AM
Selection of the Input Capacitor
VCC (PHASE 1)
The input filter capacitor should be based on how much ripple
the supply can tolerate on the DC input line. The larger the
capacitor, the less ripple expected, but consideration should be
taken for the higher surge current during power-up. The
ISL8200AM provides the soft-start function that controls and
limits the current surge. The value of the input capacitor can be
calculated by Equation 4:
D  1 – D
C IN  MIN  = I O  ----------------------------------------------f
V
P-P  MAX 
RINC
RPH1
ISFETDRV (PHASE 1)
QSHR
DPH2
(EQ. 4)
ISFETDRV (PHASE 2)
CG
SW
DPH2
Where:
ISFETDRV (PHASE 3)
ISHARE
CIN(MIN) is the minimum input capacitance (µF) required
ADD ADDITIONAL
DIODES PER PHASE
IO is the output current (A)
FIGURE 25. START-UP CIRCUITRY
D is the duty cycle (VO/VIN)
VP-P(MAX) is the maximum peak-to-peak voltage (V)
Functional Description
fSW is the switching frequency (Hz)
Initialization
In addition to the bulk capacitance, some low Equivalent Series
Inductance (ESL) ceramic capacitance is recommended to
decouple between the drain terminal of the high-side MOSFET
and the source terminal of the low-side MOSFET. This is used to
reduce the voltage ringing created by the switching current
across parasitic circuit elements.
The ISL8200AM requires VCC and PVCC to be biased by a single
supply. Power-on Reset (POR) circuits continually monitor the
bias voltages (PVCC and VCC) and the voltage at the EN pin. The
POR function initiates soft-start operation 384 clock cycles after
the EN pin voltage is pulled to be above 0.8V; all input supplies
exceed their POR thresholds and the PLL locking time expires.
The enable pin can be used as a voltage monitor and to set
desired hysteresis with an internal 30µA sinking current going
through an external resistor divider. The sinking current is
disengaged after the system is enabled. This feature is especially
designed for applications that require higher input rail POR for
better undervoltage protection. For example, in 12V applications,
RUP = 53.6k and RDOWN = 5.23k will set the turn-on threshold
(VEN_RTH) to 10.6V and turn-off threshold (VEN_FTH) to 9V, with
1.6V hysteresis (VEN_HYS). These numbers are explained in
Figure 30 on page 15.
Output Capacitors
The ISL8200AM is designed for low output voltage ripple. The
output voltage ripple and transient requirements can be met with
bulk output capacitors (COUT) with low enough Equivalent Series
Resistance (ESR); the recommended ESR is <10mΩ. When the
total ESR is below 4mΩ, a capacitor (CFF) between 2.2nF to 10nF
is recommended; CFF is placed in parallel with RSET, in between
the VOUT and VOUT_SET pin. COUT can be a low ESR tantalum
capacitor, a low ESR polymer capacitor or a ceramic capacitor.
The typical capacitance is 330µF and decoupled ceramic output
capacitors are used per phase. The internally optimized loop
compensation provides sufficient stability margins for all
ceramic capacitor applications with a recommended total value
of 300µF per phase. Additional output filtering may be needed if
further reduction of output ripple or dynamic transient spike is
required.
Using Multiple Phases
The ISL8200AM can be easily connected in parallel with other
ISL8200AM modules and current share providing an additional
10A per phase. For 2 phases, simply follow the schematic shown
in Figure 5 on page 6. A rough summary shows that the modules
share VIN, VOUT, GND and have their ISHARE pins tied together
with a 10kΩ resistor to ground (per phase). When using 3 phases
or more, it is recommended that you add the following circuitry
(see Figure 25) to ensure proper start-up. The circuit shown in
Figure 25 ensures proper start-up by injecting current into the
ISHARE line until all phases are ready to start regulating. For
additional phases, the RC time constant, using RINC­ and CG,
might have to be adjusted to increase the turn on time of the
PFET (QSHR). For 3 to 4 phases, these are the values, RINC =
243k, RPH1 = 15k, QSHR = Small Signal PFET, CG = 22nF).
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14
During shutdown or fault conditions, the soft-start is quickly reset
while UGATE and LGATE immediately change state (<100ns)
upon the input dropping below POR.
HIGH = ABOVE POR; LOW = BELOW POR
VCC POR
PVCC POR
EN POR
AND
384
CYCLES
SOFT-START
OF MODULE
PLL LOCKING
FIGURE 26. SOFT-START INITIALIZATION LOGIC
Soft-start
The ISL8200AM has an internal digital precharged soft-start
circuitry, which has a rise time inversely proportional to the
switching frequency and is determined by a digital counter that
increments with every pulse of the phase clock. The full soft-start
time from 0V to 0.6V can be estimated by Equation 5.
2560
t SS = ------------f SW
(EQ. 5)
FN8271.5
July 30, 2015
ISL8200AM
The ISL8200AM has the ability to work under a precharged output.
The PWM outputs will not be fed to the drivers until the first PWM
pulse is seen. The low-side MOSFET is held low for the first clock
cycle to provide charge for the bootstrap capacitor. If the precharged
output voltage is greater than the final target level but less than the
113% setpoint, switching will not start until the output voltage is
reduced to the target voltage and the first PWM pulse is generated.
The maximum allowable precharged level is 113%. If the
precharged level is above 113% but below 120%, the output will
hiccup between 113% (LGATE turns on) and 87% (LGATE turns off)
while EN is pulled low. If the precharged load voltage is above 120%
of the targeted output voltage, then the controller will be latched off
and not be able to power-up.
OV = 113%
FIRST PWM PULSE
VOUT TARGET VOLTAGE
FIGURE 29. SOFT-START WITH VOUT BELOW OV BUT ABOVE FINAL
TARGET VOLTAGE
Voltage Feedforward
The voltage applied to the FF pin is fed to adjust the sawtooth
amplitude of the channel. The amplitude the sawtooth is set to is
1.25x the corresponding FF voltage when the module is enabled.
This configuration helps to maintain a constant gain
(GM = VIN • DMAX/VRAMP) and input voltage to achieve
optimum loop response over a wide input voltage range. The
sawtooth ramp offset voltage is 1V (equal to 0.8V*1.25), and the
peak of the sawtooth is limited to VCC - 1.4V. With VCC = 5.4V, the
ramp has a maximum peak-to-peak amplitude of VCC - 2.4V (equal
to 3V); so the feed-forward voltage effective range is typically 3x
as the ramp amplitude ranges from 1V to 3V.
SS SETTLING AT VREF + 100mV
FIRST PWM PULSE
VOUT TARGET VOLTAGE
0.0V
2560
t ss  ------------f SW
-100mV
384
t ss_DLY  ---------f SW
A 384 cycle delay is added after the system reaches its rising
POR and prior to the soft-start. The RC timing at the FF pin should
be sufficiently small to ensure that the input bus reaches its
static state and the internal ramp circuitry stabilizes before
soft-start. A large RC could cause the internal ramp amplitude
not to synchronize with the input bus voltage during output
start-up or when recovering from faults. A 1nF capacitor is
recommended as a starting value for typical applications. The
voltage on the FF pin needs to be above 0.8V prior to soft-start
and during PWM switching to ensure reliable regulation. In a
typical application, FF pin can be shorted to the EN pin.
FIGURE 27. SOFT-START WITH VOUT = 0V
FIRST PWM PULSE
SS SETTLING AT VREF + 100mV
VOUT TARGET VOLTAGE
INIT. VOUT
-100mV
FIGURE 28. SOFT-START WITH VOUT < TARGET VOLTAGE
R
V
EN_HYS
= ----------------------------------UP
NxI
EN_HYS
R
R UP  V
EN_REF
= --------------------------------------------------------------DOWN
V
–V
EN_FTH
EN_REF
VCC
GRAMP = 1.25
Where N is number of EN pins connected together
VCC - 1.4V
UPPER LIMIT

V EN_FTH = V EN_RTH – V EN_HYS
0.8V
V RAMP = max(V CC_FF  G RAMP , VCC - 1.4V - V RAMP_OFFSET 
V CC_FF = max(0.8V, V FF 
VCC_FF
LIMITER
SAWTOOTH
AMPLITUDE
(VRAMP)
VIN
VRAMP_OFFSET = 1.0V
FF
LOWER LIMIT
(RAMP OFFSET)
0.8V
RUP
SYSTEM DELAY
RDOWN
EN
EN_POR
IEN_HYS = 30µA
OV, OT, OC, AND PLL LOCKING FAULTS
FIGURE 30. SIMPLIFIED ENABLE AND VOLTAGE FEEDFORWARD CIRCUIT
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FN8271.5
July 30, 2015
ISL8200AM
Power-good
Overvoltage Protection (OVP)
The power-good comparators monitor the voltage on the internal
VMON1 pin. The trip points are shown in Figure 31. PGOOD will
not be asserted until after the completion of the soft-start cycle.
The PGOOD pulls low upon both EN’s disabling it or the internal
VMON1 pin’s voltage is out of the threshold window. PGOOD will
not be asserted until after the completion of the soft-start cycle.
PGOOD will not pull low until the fault is present for three
consecutive clock cycles.
The Overvoltage (OV) protection indication circuitry monitors the
voltage on the internal VMON1 pin.
The UV indication is not enabled until the end of soft-start. In a UV
event, if the output drops below -13% of the target level due to
some reason (cases when EN is not pulled low) other than OV,
OC, OT, and PLL faults, PGOOD will be pulled low.
Current Share
The IAVG_CS is the current of the module. ISHARE and ISET pins
source a copy of IAVG_CS with 15µA offset, i.e., the full scale will
be 126µA.
The share bus voltage (VISHARE) set by an external resistor
(RISHARE = RISET/NCTRL) represents the average current of all
active modules. The voltage (VISET) set by RISET represents the
average current of the corresponding module and is compared
with the share bus (VISHARE). The current share error signal
(ICSH_ER) is then fed into the current correction block to adjust
each module’s PWM pulse accordingly. The current share
function provides at least 10% overall accuracy between ICs, up
to 3 phases. The current share bus works for up to 6-phase.
Figure 5 on page 6 further illustrates the current sharing aspects
of the ISL8200AM.
CHANNEL 1 UV/OV
AND
PGOOD
END OF SS1
+20%
+13%
VMON1
+9%
VREF
-9%
-13%
PGOOD LATCH OFF
AFTER 120% OV
PGOOD
FIGURE 31. POWER-GOOD THRESHOLD WINDOW
When there is only one module in the system, the ISET and
ISHARE pins can be shorted together and grounded via a single
resistor to ensure zero share error - a resistor value of 5k
(paralleling 10k on ISET and ISHARE) will allow operation up to
the OCP level.
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16
The overvoltage protection is active from the beginning of
soft-start. An OV condition (>120%) would latch the IC off (the
high-side MOSFET to latch off permanently; the low-side MOSFET
turns on immediately at the time of OV trip and then turns off
permanently after the output voltage drops below 87%). The EN
and PGOOD are also latched low at OV event. The latch condition
can be reset only by recycling VCC.
There is another non-latch OV protection (113% of target level).
At the condition of EN low and the output over 113% OV, the
lower side MOSFET will turn on until the output drops below 87%.
This is to protect the overall power trains in case of a
single-channel of a multimodule system detecting OV. The
low-side MOSFET always turns on at the conditions of EN = LOW
and the output voltage above 113% (all EN pins are tied together)
and turns off after the output drops below 87%. Thus, in a high
phase count application (multimodule mode), all cascaded
modules can latch off simultaneously via the EN pins (EN pins
are tied together in multiphase mode), and each IC shares the
same sink current to reduce the stress and eliminate the
bouncing among phases.
Over-temperature Protection (OTP)
When the junction temperature of the IC is greater than +150°C
(typically), EN pin will be pulled low to inform other cascaded
channels via their EN pins. All connected ENs stay low and
release after the IC’s junction temperature drops below +125°C
(typically), a +25°C hysteresis (typically).
Overcurrent Protection (OCP)
The OCP function is enabled at start-up. The load current
sampling ICS1 is sensed by sampling the voltage across Q2
MOSFET rDS(ON) during turn on through the resistor between
OCSET and PHASE pin. IC1 is compared with the Channel
Overcurrent Limit ‘111µA OCP’ comparator, and waits 7-cycles
before OCP condition is declared. The module’s output current
(ICS1) plus a fixed internal 15µA offset forms a voltage (VISHARE)
across the external resistor, RISHARE. VISHARE is compared with a
precision internal 1.2V threshold for a second method to detect
OCP condition.
Multi-module operation can be achieved by connecting the
ISHARE pin of two or more modules together. In multi-module
operation the voltage on the ISHARE pin correlates to the
average current of all active channels. The output current of each
module in multi-module operation is compared to a precise 1.2V
threshold to determine the overcurrent condition. Additionally,
each module has an overcurrent trip point of 111µA with 7-cycle
delay. Note that it is not necessary for the RISHARE to be scaled
to trip at the same level as the 111µA OCP comparator. Typically
the ISHARE pin average current protection level should be higher
than the phase current protection level.
With an internal RISEN-IN of 2.2kΩ, the OCP level is set to the
default value. To lower the OCP level, an external RISEN-EX is
connected between OCSET and PHASE pin. The relationships
between the external RISEN-EX values and the typical output
current IOUT(MAX) OCP levels for ISL8200AM are shown in
FN8271.5
July 30, 2015
ISL8200AM
Figures 32 through 34. It is important to note that the OCP level
shown in these graphs is the average output current and not the
inductor ripple current.
16
1.8VOUT
14
OCP (A)
When OCP is triggered, the controller pulls EN low immediately to
turn off UGATE and LGATE.
2.5VOUT
12
10
1.2VOUT
8
6
4
2
0
0
5
10
RSEN (kΩ)
15
20
FIGURE 32. 5VIN
16
5.0VOUT
In a multi-module system, with the EN pins wired OR’ed together,
all modules can immediately turn off, at one time, when a fault
condition occurs in one or more modules. A fault would pull the
EN pin low, disabling all the modules and therefore not creating
current bounce. Thus, no single channel would be overstressed
when a fault occurs.
OCP (A)
12
1.8VOUT
10
8
6
2.5VOUT
4
2
0
0
10
20
30
40
50
Since the EN pins are pulled down under fault conditions, the
pull-up resistor (RUP) should be scaled to sink no more than 5mA
current from EN pin. Essentially, the EN pins cannot be directly
connected to VCC.
Oscillator
RSEN (kΩ)
The oscillator is a sawtooth waveform, providing for leading edge
modulation with 350ns minimum dead time. The oscillator
(sawtooth) waveform has a DC offset of 1.0V. Each channel’s
peak-to-peak of the ramp amplitude is set to be proportional to
the voltage applied to its corresponding FF pin.
FIGURE 33. 12VIN
16
1.8VOUT
14
For overload and hard short conditions, the overcurrent
protection reduces the regulator RMS output current much less
than full load by putting the controller into hiccup mode. A delay
time, equal to 3 soft-start intervals, is entered to allow the
disturbance to be cleared out. After the delay time, the controller
then initiates a soft-start interval. If the output voltage comes up
and returns to the regulation, PGOOD transitions high. If the OC
trip is exceeded during the soft-start interval, the controller pulls
EN low again. The PGOOD signal will remain low and the
soft-start interval will be allowed to expire. Another soft-start
interval will be initiated after the delay interval. If an overcurrent
trip occurs again, this same cycle repeats until the fault is
removed.
Fault Handshake
1.2VOUT
14
In a high input voltage, high output voltage application, such as
20V input to 5V output, the inductor ripple becomes excessive
due to the fixed internal inductor value. In such applications, the
output current will be limited from the rating to approximately
70% of the module’s rated current.
OCP (A)
12
1.2VOUT
10
8
2.5VOUT
6
5.0VOUT
4
2
0
0
20
40
60
80
100
RSEN (kΩ)
FIGURE 34. 20VIN
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FN8271.5
July 30, 2015
ISL8200AM
Frequency Synchronization and
Phase Lock Loop
The FSYNC_IN pin has two primary capabilities: fixed frequency
operation and synchronized frequency operation. By tying a
resistor (RFS) to PGND1 from the FSYNC_IN pin, the switching
frequency can be set at any frequency between 700kHz and
1.5MHz. The ISL8200AM has an integrated 59kΩ resistor between
FSYNC_IN and PGND1, which sets the default frequency to
700kHz. The frequency setting curve shown in Figure 35 is
provided to assist in selecting an externally connected resistor
RFS-ext between FSYNC_IN and PGND1 to increase the switching
frequency.
SWITCHING FREQUENCY (kHz)
1500
DECODING
PH_CNTRL RANGE
PHASE FOR CLKOUT WRT
CHANNEL 1
REQUIRED
PH_CNTRL
<29% of VCC
-60°
15% VCC
29% to 45% of VCC
90°
37% VCC
45% to 62% of VCC
120°
53% VCC
62% to VCC
180°
VCC
Layout Guide
To achieve stable operation, low losses, and good thermal
performance, some layout considerations are necessary, which
are illustrated in Figures 36 and 37.
• The ground connection between PGND1 (pin 15) and PGND
(pin 18) should be a solid ground plane under the module.
1400
1300
• Place a high frequency ceramic capacitor between (1) PVIN
and PGND (pin 18) and (2) a 10µF between PVCC and PGND1
(pin 15) as close to the module as possible to minimize high
frequency noise. High frequency ceramic capacitors close to
the module between VOUT and PGND will help to minimize
noise at the output ripple.
1200
1100
1000
900
• Use large copper areas for power path (PVIN, PGND, VOUT) to
minimize conduction loss and thermal stress. Also, use
multiple vias to connect the power planes in different layers.
800
700
TABLE 2.
0
100
200
300
400
RFS-ext (kΩ)
FIGURE 35. RFS-ext vs SWITCHING FREQUENCY
By connecting the FSYNC_IN pin to an external square pulse
waveform (such as the CLKOUT signal, typically 50% duty cycle
from another ISL8200AM), the ISL8200AM will synchronize its
switching frequency to the fundamental frequency of the input
waveform. The voltage range on the FSYNC_IN pin is VCC/2 to
VCC. The Frequency Synchronization feature will synchronize the
leading edge of the CLKOUT signal with the falling edge of
Channel 1’s PWM clock signal. CLKOUT is not available until the
PLL locks.
The locking time is typically 210µs for fSW = 700kHz. EN is not
released for a soft-start cycle until FSYNC_IN is stabilized and the
PLL is in locking. It is recommended to connect all EN pins
together in multiphase configuration.
The loss of a synchronization signal for 13 clock cycles causes
the IC to be disabled until the PLL returns locking, at which point
a soft-start cycle is initiated and normal operation resumes.
Holding FSYNC_IN low will disable the IC.
Setting Relative Phase-shift on CLKOUT
Depending upon the voltage level at PH_CNTRL, set by the VCC
resistor divider output, the ISL8200AM operates with CLKOUT
phase shifted, as shown in Table 2. The phase shift is latched as
VCC raises above POR so it cannot be changed on the fly.
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• Keep the trace connection to the feedback resistor short.
• Use remote sensed traces to the regulation point to achieve a
tight output voltage regulation, and keep them in parallel.
Route a trace from VSEN_REM- to a location near the load
ground, and a trace from feedback resistor to the point-of-load
where the tight output voltage is desire.
• Avoid routing any sensitive signal traces, such as the VOUT and
VSENREM- sensing point near the PHASE pin or any other
noise-prone areas.
• FSYNC_IN is a sensitive pin. If it is not used for receiving an
external synchronization signal, then keep the trace
connecting to the pin short. A bypass capacitor value of 100pF,
connecting between FSYNC_IN pin and GND1, can help to
bypass the noise sensitivity on the pin.
The recommended layout considerations for operating multiple
modules in parallel follows the single-phase guidelines as well as
these additional points:
• Orient VOUT towards the load on the same layer and connect
with thick direct copper etch directly to minimize the loss.
• Place modules such that pins 1 to 11 point away from power
pads (PD1-4) so that signal busses (EN, ISHARE,
CLKOUT-to-FSYNCIN) can be routed without going under the
module. Run them along the perimeter as in Figure 37.
• Keep remote sensing traces separate, and connect only at the
regulation point. Four separate traces for VSEN_REM- and
RFBT (which stands for remote feedback) as the example
shows in Figure 37.
FN8271.5
July 30, 2015
ISL8200AM
To
Load GND
To
VOUT
RFBT
CEN
CPVCC
CIN
PVIN
COUT
PGND
VOUT
FIGURE 36. RECOMMENDED LAYOUT FOR SINGLE PHASE SETUP
CLKOUT to FSYNC_IN
EN
ISHARE
TO LOAD GND
TO VOUT
TO LOAD GND
TO VOUT
RFBT
RFBT
CEN
CEN
CPVCC
CPVCC
CIN
COUT
CIN
COUT
FIGURE 37. RECOMMENDED LAYOUT FOR DUAL PHASE SETUP
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FN8271.5
July 30, 2015
ISL8200AM
3.5
12
LOSS (W)
2.5
MAX LOAD CURRENT (A)
3.0
3.3V
2.0
1.5V
1.5
0.8V
1.0
0.5
0.0
0
2
6
4
8
10
8
3.3V
1.5V
6
0.8V
4
2
0
60
10
70
FIGURE 38. POWER LOSS vs LOAD CURRENT (5VIN) 0 LFM FOR
VARIOUS OUTPUT VOLTAGES
90
100
110
FIGURE 39. DERATING CURVE (5VIN) 0 LFM FOR VARIOUS OUTPUT
VOLTAGES
12
5.0
MAX LOAD CURRENT (A)
4.5
5.0V
4.0
3.5
LOSS (W)
80
AMBIENT TEMPERATURE (°C)
LOAD CURRENT (A)
3.3V
3.0
2.5
0.8V
2.0
1.5V
2.5V
1.5
1.0
0.5
0.0
0
2
4
6
8
10
10
8
5.0V
3.3V
6
Thermal Considerations
Empirical power loss curves, shown in Figures 38 to 41, along
with JA from thermal modeling analysis can be used to evaluate
the thermal consideration for the module. The derating curves
are derived from the maximum power allowed while maintaining
the temperature below the maximum junction temperature of
+125°C. In actual application, other heat sources and design
margin should be considered.
Package Description
The structure of the ISL8200AM belongs to the Quad Flat-pack
No-lead package (QFN). This kind of package has advantages,
such as good thermal and electrical conductivity, low weight and
small size. The QFN package is applicable for surface mounting
technology and is being more readily used in the industry. The
ISL8200AM contains several types of devices, including resistors,
capacitors, inductors and control ICs. The ISL8200AM is a copper
lead-frame based package with exposed copper thermal pads,
which have good electrical and thermal conductivity. The copper
lead frame and multi component assembly is overmolded with
polymer mold compound to protect these devices.
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1.5V
0.8V
4
2
0
60
70
80
90
100
110
AMBIENT TEMPERATURE (°C)
LOAD CURRENT (A)
FIGURE 40. POWER LOSS vs LOAD CURRENT (12VIN) 0 LFM FOR
VARIOUS OUTPUT VOLTAGES
2.5V
FIGURE 41. DERATING CURVE (12VIN) 0 LFM FOR VARIOUS
OUTPUT VOLTAGES
The package outline and typical PCB layout pattern design and
typical stencil pattern design are shown in the package outline
drawing L23.15x15 on page 23. The module has a small size of
15mm x 15mm x 2.2mm. Figure 42 shows typical reflow profile
parameters. These guidelines are general design rules. Users
could modify parameters according to their application.
PCB Layout Pattern Design
The bottom of ISL8200AM is a lead-frame footprint, which is
attached to the PCB by surface mounting process. The PCB
layout pattern is shown in the Package Outline Drawing
L23.15x15 on page 23. The PCB layout pattern is essentially 1:1
with the QFN exposed pad and I/O termination dimensions,
except for the PCB lands being a slightly extended distance of
0.2mm (0.4mm max) longer than the QFN terminations, which
allows for solder filleting around the periphery of the package.
This ensures a more complete and inspectable solder joint. The
thermal lands on the PCB layout should match 1:1 with the
package exposed die pads.
Thermal Vias
A grid of 1.0mm to 1.2mm pitch thermal vias, which drops down
and connects to buried copper plane(s), should be placed under
the thermal land. The vias should be from 0.3mm to 0.33mm in
diameter with the barrel plated with 1.0 ounce copper. Although
adding more vias (by decreasing via pitch) will improve the
thermal performance, diminishing returns will be seen as more
FN8271.5
July 30, 2015
ISL8200AM
Stencil Pattern Design
Reflowed solder joints on the perimeter I/O lands should have
about a 50µm to 75µm (2mil to 3mil) standoff height. The solder
paste stencil design is the first step in developing optimized,
reliable solder joins. Stencil aperture size to land size ratio should
typically be 1:1. The aperture width may be reduced slightly to
help prevent solder bridging between adjacent I/O lands. To
reduce solder paste volume on the larger thermal lands, it is
recommended that an array of smaller apertures be used
instead of one large aperture. It is recommended that the stencil
printing area cover 50% to 80% of the PCB layout pattern. A
typical solder stencil pattern is shown in the Package Outline
Drawing L23.15x15 on page 24. The gap width between pad to
pad is 0.6mm. The user should consider the symmetry of the
whole stencil pattern when designing its pads. A laser cut,
stainless steel stencil with electropolished trapezoidal walls is
recommended. Electropolishing “smooths” the aperture walls
resulting in reduced surface friction and better paste release,
which reduces voids. Using a trapezoidal section aperture (TSA)
also promotes paste release and forms a "brick like" paste
deposit that assists in firm component placement. A 0.1mm to
0.15mm stencil thickness is recommended for this large pitch
(1.3mm) QFN.
Reflow Parameters
Due to the low mount height of the QFN, "No Clean" Type 3 solder
paste per ANSI/J-STD-005 is recommended. Nitrogen purge is
also recommended during reflow. A system board reflow profile
depends on the thermal mass of the entire populated board, so it
is not practical to define a specific soldering profile just for the
QFN. The profile given in Figure 42 is provided as a guideline, to
be customized for varying manufacturing practices and
applications.
300
PEAK TEMPERATURE +230°C~+245°C;
TYPICALLY 60s-70s ABOVE +220°C
KEEP LESS THAN 30s WITHIN 5°C OF PEAK TEMP.
250
TEMPERATURE (°C)
and more vias are added. Simply use as many vias as practical
for the thermal land size and your board design rules allow.
200 SLOW RAMP (3°C/s MAX)
AND SOAK FROM +100°C
TO +180°C FOR 90s~120s
150
100
RAMP RATE 1.5°C FROM +70°C TO +90°C
50
0
0
100
150
200
250
300
350
DURATION (s)
FIGURE 42. TYPICAL REFLOW PROFILE
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FN8271.5
July 30, 2015
ISL8200AM
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
REVISION
CHANGE
July 30, 2015
FN8271.5
On page 1, in Features, changed "Input Voltage Range +4.5V to +20V at 10A" to "Input Voltage Range
+3.0V to +20V at 10A"
Updated Graphic on page 1
Added Evaluation Board ISL8200AMEV1PHZ to Ordering Information on page 2.
Added Note 8 to Electrical Spec Table on page 9.
March 7, 2013
FN8271.4
Features on page 1 Input Voltage Range updated from 3V to 20V to 4.5V to 20V.
January 24, 2013
FN8271.3
Made correction in Abs Max Ratings Table under Recommended Operating Conditions on page 7 by
separating in the Input Voltage PVIN and VIN. PVIN is 3V to 20V and VIN 4.5V to 20V.
January 2, 2013
Abs Max Ratings Table under Recommended Operating Conditions on page 7 changed Input Voltage, PVIN,
VIN from 3V to 20V to 4.5 to 20V.
October 8, 2012
Pin Description Table on page 4 changed in Description column operational voltage range for PVCC and VCC
from “4.5V to 5.5V” to “4.5 to 5.6”
Abs Max Ratings Table under Recommended Operating Conditions on page 7 changed Driver Bias Voltage,
PVCC and Signal Bias Voltage, VCC from “3V to 5.6V” to “4.5V to 5.6V”
September 13, 2012
FN8271.2
Initial Release.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
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FN8271.5
July 30, 2015
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Package Outline Drawing
L23.15x15
23 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (PUNCH QFN)
Rev 3, 10/10
A
3.22
2.2
0.2 H AB
1.02
23
23 22 21 20
20 21 22
0.05 M H AB
1
2
3
4
5
19
9.9
13.8
4.7
4.26
2.36
1.34
18
3.4
4.38
X4
17
0.8
2.28
16
0.2 H AB
17
15.0±0.2
3.4
18
15.0±0.2 15.8±0.2
16
1
2
4.7
19
35x 0.5
0.82
4.8
(35x 0.40)
15.8±0.2
7x 1.9 ±0.05
23
18x 0.75
3
4
B
5
6
7
8
10x 1.1 ±0.1
9
10
11
15
11x 0.7
0.90
14 13 12
2.0
5.82
11x 1.85 ±0.05
7x 0.8
TOP VIEW
BOTTOM VIEW
8° ALL AROUND
2.2 ±0.2
NOTES:
S 0.2
S
SIDE VIEW
0.25
S 0.05
1.
Dimensions are in millimeters.
2.
Unless otherwise specified, tolerance : Decimal ± 0.2;
Body Tolerance ±0.2mm
3.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
ISL8200AM
6
7
8
9
10
11
12 13 14 15
18x 1.3 ±0.1
X4
3x 2.6
FN8271.5
July 30, 2015
5.18
4.73
4.68
4.03
4.08
3.63
8.15
3.58
2.93
6.88
2.98
5.58
2.48
23
1
0.00
0.00
3.02
4.13
2.13
2.83
3.43
0.83
1.53
1.07
0.00
1.77
1.47
3.52
1.92
4.64
4.13
6.03
6.73
6.78
8.09
6.11
5.67
4.97
4.37
3.67
3.07
2.37
1.77
1.07
0.60
6.48
4.88
5.68
6.88
8.14
5.53
5.03
2.08
1.58
0.78
0.18
1.82
0.65
0.00
2.32
4.12
4.72
5.22
5.82
6.07
3.12
4.07
4.77
5.17
5.87
6.02
3.62
3.02
3.62
STENCIL PATTERN WITH SQUARE PADS-1
TYPICAL RECOMMENDED LAND PATTERN
6.73
6.23
4.18
4.68
4.38
3.88
1.83
2.33
1.53
1.53
0.00
0.52
0.82
2.87
3.17
4.69
4.99
6.52
0.00
0.52
0.82
2.82
3.67
5.50
5.80
6.52
6.48
4.58
4.28
2.23
1.48
0.88
0.13
0.00
0.60
FN8271.5
July 30, 2015
STENCIL PATTERN WITH SQUARE PADS-2
ISL8200AM
8.15
3.67
3.43
5.62
2.97
2.92
3.62
4.22
4.92
5.52
6.82
8.10
2.52
0.00
2.57
2.83
1.87
2.13
1.47
4.42
2.37
0.32
0.77
1.48
0.37
0.77
0.78
0.28
0.88
0.00
1.68
0.13
0.33
4.92
3.07
1.38
2.18
6.06
5.72
3.67
1.88
1.43
0.73
0.93
2.75
3.05
4.03
4.83
24
8.10
6.48
5.48
4.88
4.18
3.58
2.88
2.28
1.58
0.98
0.28
0.00
0.32
1.02
1.62
2.32
0.00
2.53
1.83
4.37
5.78
5.13
4.97
6.03
t
5.72
8.14
6.88
4.68
4.18
0.78
1.02
0.00
1.82
2.32
3.12
3.62
4.42
4.92
5.83
5.72
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5.98