Application Note 1739 ISL8200AMEVAL2PHZ Evaluation Board User’s Guide MODULE GROUP 1 (U201) MODULE GROUP 2 (U301) PGOOD VIN = UP TO 20V VOUT = 1V LOAD UP TO 20A FIGURE 1. ISL8200AMEVAL2PHZ EVALUATION BOARD ISL8200AMEVAL2PHZ Evaluation Board TABLE 2. RECOMMENDED COMPONENT SELECTION FOR QUICK EVALUATION The ISL8200AM is a complete 10A step-down current shareable switch mode power module in a low profile package. It can be used in a standalone single-phase operation as well as current shared applications where multiple modules are connected in parallel. The ISL8200AMEVAL2PHZ evaluation board is used to demonstrate performance of the ISL8200AM 2-phase current shared application. The input voltage range can be up to 20V, and the output voltage is 1V and 20A maximum load. The output voltage can support a range up to 6V with the proper output capacitor rating. TABLE 1. EVALUATION BOARD ELECTRICAL SPECIFICATIONS DESCRIPTION MIN Input Voltage 5 Output Voltage 0.6 Output Current 1 MAX UNIT 20 V 6 V 20 Switching Frequency 700 Efficiency, VIN = 8V, VOUT = 5V, FSW = 900kHz, IOUT = 10A April 22, 2014 AN1739.0 TYP 800 94.1 1 VOUT (V) IOUT (A) C213/C313 (pF) FSW (kHz) RFSYNC (kΩ) 1 20 OPEN 800 59 2.5 20 OPEN 850 55 3.3 20 680/680 1050 45 5 20 680/680 1150 41 Recommended Equipment • 0V to 20V power supply with at least 15A source current capability • One Electronic Load capable of sinking current up to 20A • Digital multi-meters (DMMs) • 100MHz quad-trace oscilloscope • Signal generator (for synchronization demonstration) A 1500 kHz % CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2014. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. Application Note 1739 1300 PVIN1 and GND banana plugs are the input power terminals. 1200 Two input electrolytic capacitor footprints are provided to handle the input current ripple. 1100 Two SANYO POSCAP 2TPF330M6 (330µF, ESR 6mΩ) are used as output E-caps for each channel. Also, capacitor footprints are available for the user to evaluate different output capacitors. J3, J4 are output lugs for load connections. TP301 is the clock output. The default phase shift of the CLKOUT signal from module 1 (U201) causes the second to switch with a phase shift of 180°, which can be observed by the relative phase between PHASE2 and PHASE3 signals as shown in Figures 37 and 38. R203, R303 and C210, C310 are small added filters for the VIN pins. Quick Start 1. Ensure that the circuit is correctly connected to the supply (PVIN1 and GND banana plugs) and load (J3 and J4) prior to applying any power. 2. Adjust the input supply to be 5V. Turn on the input power supply. 3. Verify the two outputs’ voltages are correct. If the PGOOD is set high, LED301 will be green. If the PGOOD is set low, LED301 will be red. TP300 is the test post to monitor PGOOD. Evaluating Other Output Voltages where VREF = 0.6V ROS = 2.2k internal 12VIN 15VIN 1000 8VIN 900 20VIN 800 5VIN 700 600 1.0 1.5 (EQ. 1) The output capacitors must be changed to support the corresponding output voltage. The onboard output capacitors are rated at 6.3V max. 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VOUT (V) FIGURE 2. OPTIMUM FREQUENCY vs VOUT Programming the Input Voltage UVLO and its Hysteresis By programming the voltage divider at the EN pin connected to the input rail, the input UVLO and its hysteresis can be programmed. The ISL8200AMEVAL2PHZ has R1 = 8.25k and R2 = 2.05k; the IC will be disabled when the input voltage drops below 4.5V and will restart after VIN recovers to be above 4.0V. The UVLO equations are re-stated in the following, where RUP and RDOWN are the upper and lower resistors of the voltage divider at EN pin, VHYS is the desired UVLO hysteresis and VFTH is the desired UVLO falling threshold. V HYS R UP = --------------I HYS The ISL8200AMEVAL2PHZ kit outputs are preset to 1.0V/20A. VOUT can also be adjusted between 0.6V to 6V by changing the value of R221 and R321 simultaneously as given by Equation 1. V OUT – V REF R 221 = ------------------------------------------ ROS V REF FREQUENCY (kHz) Circuits Description where IHYS = N x 30µA N = number of phases (= 2) R UP V ENREF R DOWN = -------------------------------------------- where VENREF = 0.6V V FTH – V ENREF (EQ. 3) (EQ. 4) For 12V applications, if it is desired to have the IC disabled when the input voltage drops below 9V and restart when VIN recovers above 10.6V, then R1 = 16.5k and R2 = 2.6k. For different output voltage, adjust FSW according to Figure 2. The frequency selection resistor (RFSYNC) can be estimated by Equation 2. 4 R FSYNC k = 4.671 10 Fsw kHz – 1.04 (EQ. 2) Where RFSYNC = R223//59k, 59k is the internal resistor. For high output applications, the feedback gain is reduced, so the 0dB cross-over frequency is pushed closer to the LC resonance frequency. Please add a zero in the loop to have better stability. We recommend using 680pF capacitors at C213 and C313 to boost the phase margin. Submit Document Feedback 2 AN1739.0 April 22, 2014 Application Note 1739 Efficiency Measurement Figures 12 through 27 show the efficiency measurement for the ISL8200AMEVAL2PHZ Evaluation Board. The voltage and current meter can be used to measure input/output voltage and current. In order to obtain an accurate measurement and prevent the voltage drop of PCB or wire trace, the voltage meter must be close to the input/output terminals. For simplicity, the measuring point for the input voltage meter is at the TP1 terminal, and the measuring point for the output voltage meter is at the TP3 terminal. The efficiency equation is shown in Equation 5: V OUT I OUT P OUT Output Power Efficiency = ------------------------------------ = ---------------- = ---------------------------------------P IN V IN I IN Input Power (EQ. 5) Output Ripple/Noise Measurement Simple steps should be taken to ensure that there is minimum pickup noise due to high frequency events, which can be magnified by the large ground loop formed by the oscilloscopeprobe ground. This means that even a few inches of ground wire on the oscilloscope probe may result in hundreds of millivolts of noise spikes when improperly routed or terminated. This effect can be overcome by using the short loop measurement method to minimize the measurement loop area for reducing the pickup noise. The short loop measurement method is shown in Figure 3. For ISL8200AMEVAL2PHZ evaluation board, the output ripple/noise measurement point is located at the C202/C302 terminal. OUTPUT CAP OUTPUT OUTPUT CAP CAP OR MOSFET FIGURE 3. OUTPUT RIPPLE/NOISE MEASUREMENT Submit Document Feedback 3 AN1739.0 April 22, 2014 Submit Document Feedback ISL8200AMEVAL2PHZ Schematic PVIN1 TP1 TP3 PVIN1 R1 8.25k FF_BUS 1 C9 330uF C25 DNP C21 DNP C19 330uF C24 DNP C12 DNP C51 DNP C35 DNP VOUT C39 DNP C34 DNP C47 DNP J4 1 R4 DNP R2 2.05k JP1 C18 DNP GND TP4 2 4 C15 DNP 1 VOUT VOUT EN_BUS C3 680uf J3 R3 DNP TP2 GND VCC3 3 1 R325 3.3k LED301 TP301 CLK_OUT 22 PGOOD 21 VCC2 20 OCSET2 15 C309 10u PHASE3 18 17 16 C203 22u C201 C206 22u C202 DNP PHASE2 TP302 VOUT 22uF AN1739.0 April 22, 2014 FIGURE 4. 1 VOUT_SET ISFETDRV3 2 VSEN_REM-3 3 5 4 ISET 6 C304 1000p C313 DNP N.C. U301 VIN PGOOD ISL8200AM PVCC VCC PGND1.23 OCSET PHASE PVIN1 PVIN1 ISHARE 9 7 ISET3 PH_CNTRL3 FSYNC_IN FF PVCC3 14 C310 2.2u 10 11 1 R209 DNP PHASE TP204 PVIN1 13 EN VOUT OCSET VIN3 ISHARE_BUS 1 VOUT_SET ISFETDRV2 2 VSEN_REM-2 3 ISFETDRV VSEN_REM- ISET2 5 4 ISET PGND1.4 FSYNC_IN2 7 6 ISHARE CLK_23 8 FSYNC_IN PH_CNTRL2 9 CLKOUT PH_CNTRL 10 PGND1.23 R303 23 12 0 C314 DNP VOUT_SET3 C303 22u C306 22u 19 PHASE2 16 PGOOD VCC PVIN 10u ISHARE_BUS 11 15 C209 EN_BUS 0 ISL8200AM PVCC 1n VOUT PGND 2.2u U201 VIN C311 RM+2 18 C210 TP34 13 14 PVCC2 VSEN_REM+2 PVIN TP203 R306 0 R221 1.47k 17 1 C204 1000p C213 DNP N.C. VOUT VIN2 PVIN1 VOUT_SET2 EN FF_BUS 19 1n R203 FF EN_BUS 12 PGND C211 0 C214 DNP 8 RM-2 FF_BUS 0 RM-3 DNP DNP R206 10k R311 R217 10k DNP R211 TP202 R317 CLKOUT R223 1 ISFETDRV DNP DNP C305 JP301 2 VSEN_REM- 2 C212 PGND1.4 DNP R315 10k 2N7002LT1 1 PGOOD 2 10k C205 SYS_ISH_BUS CLK_23 Q302 DNP R215 GREEN PH_CNTRL C215 CLK_12 TP201 RED 34 TP300 SYS_ISH_BUS C301 C302 DNP 22uF VOUT 23 1.47k VSEN_REM+3 RM+3 VOUT 0 22 PGOOD 21 R321 VCC3 20 OCSET3 R309 DNP PHASE3 Application Note 1739 R324 3.3k Submit Document Feedback ISL8200AMEVAL2PHZ Bill of Materials COMMON COMPONENTS VALUE 5 CH2 CH3 PART NUMBER PART DESCRIPTION U201 U301 R206 R306 0 RES, SMD, 0603, 0Ω, 1/16W, TF, ROHS FF-EN Connection R203 R303 1 RES, SMD, 0603, 1Ω, 1/10W, 1%, TF, ROHS PVIN-VIN R215 R315 10k RES, SMD, 0603, 10k, 1/10W, 1%, TF, ROHS RISHARE R217 R317 10k RES, SMD, 0603, 10k, 1/10W, 1%, TF, ROHS RISET R221 R321 1.47k RES, SMD, 0603, 1.47k, 1/10W, 1%, TF, ROHS RFB_TOP RM+2, RM-2 RM+3, RM-3 0 RES, SMD, 0603, 0Ω, 1/16W, TF, ROHS REM_SENS+/- ISL8200AM COMMENTS Module 8.25k RES, SMD, 0603, 8.25kΩ, 1/10W, 1%, TF, ROHS EN-Top R2 2.05k RES, SMD, 0603, 2.05k, 1/10W, 1%, TF, ROHS EN-Bottom CAP, SMD, 0603, 1000pF, 50V, 10%, X7R, ROHS CEN-Bottom C211 C311 1nF C209 C309 10µF CAP, SMD, 0805, 10µF, 16V, 10%, X5R, ROHS PVCC_cap C210 C310 2.2µF CAP, SMD, 0805, 2.2µF, 25V, 10%, X5R, ROHS VIN_cap C204 C304 1000p CAP, SMD, 0603, 1000pF, 50V, 5%, COG, ROHS SENS_FILTER 680µF CAP, ALUMINUM, RADIAL, 680µF, 35V Cin_elec_common Cin_Ceremic_1 C3 C203, C206 C303, C306 22µF CAP, SMD, 1210, 22µF, 25V, 20%, X5R, ROHS C202 C302 22µF CAP, SMD, 1206, 22µF, 16V, 10%, X5R, ROHS C9, C19 330µF 6TPF330M6L POSCAP 6.3V 9mΩ Cout_Bulk1 PGOOD and Additional Placeholder Q302 2N7002 LED301 C205 SSL-LXA3025IGC-TR LED, SMD, 3x2.5mm, 4P, RED/GREEN, 2V, ROHS PGOOD_LED AN1739.0 April 22, 2014 3.3k C12, C18, C21, C24, C25, C34, C35, C39, C47, C51 DNP Cout C212 DNP FSYNC_IN2_cap R223 DNP FSYNC_IN2_resistor DNP ISET_cap DNP ISHARE_cap C305 R309 RES, SMD, 0603, 3.32k, 1/10W, 1%, TF, ROHS PGOOD_NFET R324, R325 C215 R209 TRANSISTOR, N-CHANNEL, SOT-23, 60V, 115mA, ROHS PGOOD_RES DNP C15 DNP Cin_elec_common Application Note 1739 R1 Submit Document Feedback ISL8200AMEVAL2PHZ Bill of Materials CH2 CH3 (Continued) COMMON COMPONENTS VALUE R3, R4 DNP FF-Top, FF-Bottom PART NUMBER PART DESCRIPTION COMMENTS 6 R211 R311 DNP PH_CNTRL C213 C313 DNP CFB_TOP C214 C314 DNP CFB_BOTTOM C201 C301 DNP Connectors and Test Points TP201 CONN-MINI TEST POINT, VERTICAL, WHITE, ROHS CLK_12 test point 5002 CONN-MINI TEST POINT, VERTICAL, WHITE, ROHS CLK_23 test point TP202 5002 CONN-MINI TEST POINT, VERTICAL, WHITE, ROHS EN_BUS test point TP203 5002 CONN-MINI TEST POINT, VERTICAL, WHITE, ROHS PVCC_test point 5002 CONN-MINI TEST POINT, VERTICAL, WHITE, ROHS PHASE test point 5003 CONN-MINI TEST POINT, VERTICAL, WHITE, ROHS PGOOD test point 1514-2 CONN-TURRET, TERMINAL POST, TH, ROHS PVIN1, GND, VOUT, GND Turret Posts J3, J4 KPA8CTP HDWARE, MTG, CABLE TERMINAL, 6-14AWG, LUG&SC Lug PVIN1 111-0702-001 CONN-BINDING POST, INSUL-RED, THMBNUT-GND, ROHS Binding Post RED GND 111-0703-001 CONN-BINDING POST, INSUL-BLK, THMBNUT-GND, ROHS Binding Post BLACK TP301 TP204 TP304 TP300 TP1, TP2, TP3, TP4 JP1, JP301 DNP Application Note 1739 5002 AN1739.0 April 22, 2014 Application Note 1739 ISL8200AMEVAL2PHZ Board Layout FIGURE 5. ASSEMBLY TOP FIGURE 6. TOP SILK Submit Document Feedback 7 AN1739.0 April 22, 2014 Application Note 1739 ISL8200AMEVAL2PHZ Board Layout (Continued) FIGURE 7. COMPONENT SIDE - TOP FIGURE 8. LAYER 2 Submit Document Feedback 8 AN1739.0 April 22, 2014 Application Note 1739 ISL8200AMEVAL2PHZ Board Layout (Continued) FIGURE 9. LAYER 3 FIGURE 10. BOTTOM LAYER Submit Document Feedback 9 AN1739.0 April 22, 2014 Application Note 1739 ISL8200AMEVAL2PHZ Board Layout (Continued) FIGURE 11. SILKSCREEN BOTTOM (MIRRORED) Submit Document Feedback 10 AN1739.0 April 22, 2014 Application Note 1739 Test Data for ISL8200AMEVAL2PHZ Efficiency 94.4 92.1 94.2 92.0 94.0 91.9 900kHz 850kHz 93.6 93.4 950kHz 93.2 91.8 EFFICIENCY (%) EFFICIENCY (%) 93.8 93.0 1.15MHz 91.6 91.5 91.4 92.8 1.05MHz 91.3 92.6 VIN = 8V VOUT = 5V 92.4 92.2 1.1MHz 91.7 5 VIN = 12V VOUT = 5V 91.2 10 15 91.1 20 5 10 LOAD (A) FIGURE 12. EFFICIENCY (V IN = 8V, VOUT = 5V) 89.2 91.0 89.0 1.1MHz 1.15MHz 90.8 88.8 90.6 EFFICIENCY (%) EFFICIENCY (%) 20 FIGURE 13. EFFICIENCY (V IN = 12V, VOUT = 5V) 91.2 1.05MHz 90.4 90.2 90.0 89.8 89.6 88.6 88.4 88.2 1.15MHz 88.0 1.05MHz 1.1MHz 87.8 87.6 VIN = 15V VOUT = 5V 89.4 89.2 15 LOAD (A) 5 VIN = 20V VOUT = 5V 87.4 10 15 87.2 20 5 10 FIGURE 14. EFFICIENCY (VIN = 15V, VOUT = 5V) 20 FIGURE 15. EFFICIENCY (V IN = 20V, VOUT = 5V) 92.8 12VIN FSW = 1.15MHz VOUT = 5V 92.2 91.6 EFFICIENCY(%) 15 LOAD (A) LOAD (A) 15VIN 91.0 90.4 89.8 20VIN 89.2 88.6 88.0 87.4 86.8 5 10 15 20 LOAD (A) FIGURE 16. EFFICIENCY (F SW = 1.15MHz, VOUT = 5V) Submit Document Feedback 11 AN1739.0 April 22, 2014 Application Note 1739 Test Data for ISL8200AMEVAL2PHZ (Continued) 92.0 90.4 900kHz 91.5 850kHz 89.6 EFFICIENCY (%) EFFICIENCY (%) 91.0 90.0 950kHz 90.5 90.0 89.5 89.0 88.5 950kHz 89.2 88.8 1.05MHz 88.4 900kHz 88.0 1MHz 87.6 88.0 87.2 VIN = 5V VOUT = 2.5V 87.5 87.0 5 VIN = 8V VOUT = 2.5V 86.8 10 15 86.4 20 5 10 LOAD (A) FIGURE 17. EFFICIENCY (VIN = 5V, VOUT = 2.5V) 87.0 900kHz 850kHz 87.2 86.7 86.4 950kHz 86.8 EFFICIENCY (%) EFFICIENCY (%) 87.0 86.6 86.4 86.2 86.0 750kHz 86.1 VIN = 12V VOUT = 2.5V 85.6 85.8 85.5 850kHz 85.2 84.9 5 VIN = 15V VOUT = 2.5V 84.3 10 15 84.0 20 5 10 LOAD (A) 87.4 83.4 86.6 83.1 85.8 EFFICIENCY (%) 88.2 83.7 750kHz 800kHz 82.5 82.2 20 FIGURE 20. EFFICIENCY (V IN = 15V, VOUT = 2.5V) 84.0 82.8 15 LOAD (A) FIGURE 19. EFFICIENCY (V IN = 12V, VOUT = 2.5V) EFFICIENCY (%) 800kHz 84.6 85.8 850kHz 81.9 12VIN 15VIN 85.0 84.2 20VIN 83.4 82.6 81.8 81.6 VIN = 20V VOUT = 2.5V 81.3 81.0 20 FIGURE 18. (V IN = 8V, VOUT = 2.5V) 87.4 85.4 15 LOAD (A) 5 10 15 LOAD (A) FIGURE 21. EFFICIENCY (V IN = 20V, VOUT = 2.5V) Submit Document Feedback 12 FSW = 850kHz VOUT = 2.5V 81.0 20 80.2 5 10 15 20 LOAD (A) FIGURE 22. EFFICIENCY (F SW = 850kHz, VOUT = 2.5V) AN1739.0 April 22, 2014 Application Note 1739 (Continued) 91.4 89.6 91.2 89.4 91.0 89.2 950kHz 90.8 90.6 1MHz EFFICIENCY (%) EFFICIENCY (%) Test Data for ISL8200AMEVAL2PHZ 1.05MHz 90.4 90.2 90.0 89.8 1.1MHz 89.0 1MHz 88.8 1.15MHz 88.6 900kHz 88.4 88.2 88.0 VIN = 8V VOUT = 3.3V 89.6 89.4 1.05MHz 5 10 15 87.8 VIN = 12V VOUT = 3.3V 87.6 5 20 10 LOAD (A) 15 20 LOAD (A) FIGURE 23. EFFICIENCY (V IN = 8V, VOUT = 3.3V) FIGURE 24. EFFICIENCY (V IN = 12V, VOUT = 3.3V) 88.2 86.2 1MHz 88.0 86.0 950kHz 85.8 1.05MHz 87.6 EFFICIENCY (%) EFFICIENCY (%) 87.8 87.4 87.2 87.0 86.8 86.6 800kHz 85.4 85.2 750kHz 85.0 850kHz 84.8 84.6 VIN = 15V VOUT = 3.3V 86.4 86.2 85.6 5 10 15 VIN = 20V VOUT = 3.3V 84.4 84.2 20 5 10 LOAD (A) 15 20 LOAD (A) FIGURE 25. EFFICIENCY (VIN = 15V, VOUT = 3.3V) FIGURE 26. EFFICIENCY (V IN = 20V, VOUT = 3.3V) 91.6 8VIN 91.0 EFFICIENCY (%) 90.4 89.8 12VIN 89.2 88.6 15VIN 88.0 87.4 86.8 FSW = 1.05MHz VOUT = 3.3V 86.2 85.6 5 10 15 20 LOAD (A) FIGURE 27. EFFICIENCY (F SW = 1.05MHz, VOUT = 3.3V) Submit Document Feedback 13 AN1739.0 April 22, 2014 Application Note 1739 Test Data for ISL8200AMEVAL2PHZ (Continued) Load Regulation 5.10 5.10 FSW = 1.05MHz VOUT = 5V 5.09 20VIN 5.08 15VIN 5.06 5.07 VOUT (V) VOUT (V) 20VIN 5.08 5.07 15VIN 5.06 5.05 5.05 12VIN 5.04 12VIN 5.04 5.03 5.02 FSW = 1.1MHz VOUT = 5V 5.09 5.03 5 10 15 5.02 20 5 10 LOAD (A) 15 20 LOAD (A) FIGURE 28. LOAD REGULATION (F SW = 1.05MHz, VOUT = 5V) FIGURE 29. LOAD REGULATION (F SW = 1.1MHz, VOUT = 5V) 2.530 2.520 FSW = 850kHz 2.528 VOUT = 2.5V fsw=950kHz F SW = 950kHz Vout=2.5V V OUT = 2.5V 2.519 20VIN 2.526 2.518 2.517 VOUT (V) VOUT (V) 2.524 12VIN 2.516 8VIN 15VIN 2.522 2.520 2.518 12VIN 2.515 8VIN 2.516 2.514 2.513 2.514 5 10 15 2.512 20 5 10 LOAD (A) 15 20 LOAD (A) FIGURE 30. LOAD REGULATION (FSW = 950kHz, VOUT = 2.5V) 3.348 FIGURE 31. LOAD REGULATION (F SW = 850kHz, VOUT = 2.5V) FSW = 1.05MHz VOUT = 3.3V 3.346 15VIN 3.344 VOUT (V) 3.342 3.340 3.338 3.336 12VIN 3.334 8VIN 3.332 3.330 3.328 5 10 15 20 LOAD (A) FIGURE 32. LOAD REGULATION (F SW = 1.05MHz, VOUT = 3.3V) Submit Document Feedback 14 AN1739.0 April 22, 2014 Application Note 1739 Test Data for ISL8200AMEVAL2PHZ (Continued) 1V Waveforms VOUT 500mV/DIV VOUT 500mV/DIV PG 2V/DIV PG 2V/DIV 1ms/DIV 200ms/DIV FIGURE 33. START-UP AT NO LOAD, V IN = 12V, VOUT = 1V FIGURE 34. SHUTDOWN AT NO LOAD VOUT 500mV/DIV IOUT 5A/DIV VOUT 500mV/DIV PG 2V/DIV IOUT 5A/DIV PG 2V/DIV 2ms/DIV 200µs/DIV FIGURE 35. START-UP AT 20A LOAD FIGURE 36. SHUTDOWN AT NO LOAD M1: VOUT RIPPLE 5VIN 50mV/DIV M1: VOUT RIPPLE 5VIN 50mV/DIV M2: VOUT RIPPLE 12VIN 50mV/DIV M2: VOUT RIPPLE 12VIN 50mV/DIV M4: VOUT RIPPLE 20VIN 50mV/DIV M4: VOUT RIPPLE 20VIN 50mV/DIV 1µs/DIV 1µs/DIV FIGURE 37. STEADY STATE NO LOAD FIGURE 38. STEADY STATE AT FULL LOAD Submit Document Feedback 15 AN1739.0 April 22, 2014 Application Note 1739 Test Data for ISL8200AMEVAL2PHZ (Continued) PHASE2 5V/DIV PHASE2 5V/DIV VOUT RIPPLE 50mV/DIV VOUT RIPPLE 50mV/DIV PHASE3 5V/DIV PHASE3 5V/DIV 1µs/DIV 1µs/DIV FIGURE 39. STEADY STATE AT NO LOAD, VIN = 5V FIGURE 40. STEADY STATE AT 20A LOAD, V IN = 5V M1: VOUT 5VIN 20mV/DIV M2: VOUT 12VIN 50mV/DIV M4: VOUT 20VIN 50mV/DIV IOUT 10A/DIV 100µs/DIV FIGURE 41. LOAD TRANSIENT 5V Waveforms VOUT 2V/DIV VOUT 2V/DIV PG 2V/DIV PG 2V/DIV 1ms/DIV FIGURE 42. START-UP AT NO LOAD, V IN = 12V, VOUT = 5V Submit Document Feedback 16 200ms/DIV FIGURE 43. SHUTDOWN AT NO LOAD, V IN = 12V, VOUT = 5V AN1739.0 April 22, 2014 Application Note 1739 Test Data for ISL8200AMEVAL2PHZ VOUT 2V/DIV (Continued) VOUT 2V/DIV IOUT 5A/DIV IOUT 5A/DIV PG 2V/DIV PG 2V/DIV 1ms/DIV 1ms/DIV FIGURE 44. START-UP AT 20A LOAD, V IN = 12V, VOUT = 5V FIGURE 45. SHUTDOWN AT 20A LOAD, V IN = 12V, VOUT = 5V M2: VOUT RIPPLE 12VIN 50mV/DIV M4: VOUT RIPPLE 20VIN 50mV/DIV M2: VOUT RIPPLE 12VIN 50mV/DIV M4: VOUT RIPPLE 20VIN 50mV/DIV 1µs/DIV 1µs/DIV FIGURE 46. STEADY STATE NO LOAD, 5VOUT FIGURE 47. STEADY STATE AT FULL LOAD, 5VOUT PHASE2 10V/DIV PHASE2 10V/DIV VOUT RIPPLE 50mV/DIV VOUT RIPPLE 50mV/DIV PHASE3 10V/DIV PHASE3 10V/DIV 1µs/DIV 1µs/DIV FIGURE 48. STEADY STATE AT NO LOAD, 12VIN , 5VOUT FIGURE 49. STEADY STATE AT FULL LOAD, 12V IN , 5VOUT Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 17 AN1739.0 April 22, 2014