REVISIONS LTR DESCRIPTION DATE APPROVED A Make following changes to figure 2; ISET and ISHARE descriptions, delete output current limit of 108 µA and substitute 123µA ; VOUT description, delete output voltage limit of 6 V and substitute 7.5 V. Under figure 5, add voltages 6.5 V and 7.5 V. - ro 10-11-23 C. SAFFLE B Add device type 02. Split out the input voltage range limits PVIN and VIN under paragraph 1.4. Make following changes to device type 01 parameters; driver bias voltage (delete 3 V and substitute 4.5 V) and signal bias voltage (delete 3 V and substitute 4.5 V) under paragraph 1.3; maximum current (delete 250 mA and substitute 320 mA), maximum current (delete 150 mA entirely), output ripple voltage (delete 30 mVpp and substitute 27 mVpp) under table I; FF (delete 0.7 V and substitute 0.8 V), PVCC (delete 5.5 V and substitute 5.6 V), PVIN (delete 0 V and substitute 3 V), and VCC (delete 2.97 V and substitute 4.5 V) descriptions under figure 2. - ro 12-11-14 C. SAFFLE CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV B B PAGE 18 19 REV STATUS OF PAGES REV B B B B B B B B B B B B B B B B B PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY RICK OFFICER Original date of drawing YY-MM-DD CHECKED BY RAJESH PITHADIA 10-07-15 TITLE MICROCIRCUIT, LINEAR, CURRENT SHARING 10 A DC/DC POWER SUPPLY, MONOLITHIC SILICON APPROVED BY CHARLES F. SAFFLE SIZE A REV AMSC N/A DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 CODE IDENT. NO. DWG NO. V62/10608 16236 B PAGE 1 OF 19 5962-V101-12 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a current sharing 10A DC/DC power supply microcircuit, with an operating temperature range of -55°C to +125°C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/10608 - Drawing number 01 X B Device type (See 1.2.1) Case outline (See 1.2.2) Lead finish (See 1.2.3) 1.2.1 Device type(s). Device type Generic 01 02 Circuit function ISL8200M ISL8200AM Current sharing 10A DC/DC power supply Current sharing 10A DC/DC power supply 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins X 23 JEDEC PUB 95 Package style See figure 1 Plastic quad leadless flat pack 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator A B C D E Z DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/10608 PAGE 2 1.3 Absolute maximum ratings. 1/ Input voltage range PVIN (VIN) .................................................................................. Driver bias voltage, PVCC: Device type 01 ....................................................................................................... Device type 02 ....................................................................................................... Signal bias voltage, VCC ............................................................................................ -0.3 V to +27 V -0.3 V to +6.5 V -0.3 V to +6.0 V -0.3 V to +6.5 V BOOT/UGATE voltage, VBOOT .................................................................................. -0.3 V to +36 V Phase voltage, (VPHASE) ........................................................................................... VBOOT - 7 V to VBOOT + 0.3 V BOOT to PHASE voltage (VBOOT - VPHASE) ............................................................ -0.3 V to VCC + 0.3 V Input, output or I/O voltage ......................................................................................... Electrostatic discharge (ESD): Human body model (HBM) (tested per JESD22-A114) .......................................... Machine model (MM) (tested per JESD22-A115) ................................................... Charge device model (CDM) (tested per JESD22-C101) ....................................... Latch up current (tested per JESD-78, class 2, level A) ............................................. Power dissipation (PD) ............................................................................................... Maximum storage temperature range (TSTG) .............................................................. Thermal resistance, junction to case (θJC) ................................................................. -0.3 V to VCC + 0.3 V 2 kV 200 V 1 kV 100 mA 3.2 W 2/ -55°C to +150°C 2°C/W 3/ Thermal resistance, junction to ambient (θJA) ............................................................ 13°C/W 4/ 1.4 Recommended operating conditions. 5/ 6/ Input voltage range : PVIN ....................................................................................................................... VIN ......................................................................................................................... Driver bias voltage, PVCC ......................................................................................... Signal bias voltage, VCC ............................................................................................ 3 V to +20 V 7/ 4.5 V to +20 V 7/ 4.5 V to +5.6 V 7/ 4.5 V to +5.6 V BOOT to PHASE voltage (overcharged) (VBOOT - VPHASE) ..................................... < 6 V Junction temperature range (TJ) ................................................................................ -55°C to +125°C Operating ambient temperature range (TA) ................................................................ -55°C to +125°C 1/ 2/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. PVIN = VIN = 12 V, VOUT = 1.2 V, IOUT = 10 A. 3/ θJC case temperature location is the center of the package underside. 4/ θJA is measured in free air with the component mounted on a high effective thermal conductivity test board (for example, 4 layer type without thermal vias, see manufacturer’s technical brief TB379) per JEDEC standards except that the top and bottom layers assume solid planes. Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. The sequence to start up at < - 30°C is to hold EN pin to ground and release it after PVIN and VIN voltage has reached steady state. Utilizing multiple modules to current share below -40°C ambient is not recommended. However, the operation of a single module is acceptable. For 3.3 V PVIN operation, the voltage on PVCC is recommended to be 5 V for sufficient gate drive voltage. This can be accomplished by using a voltage greater than or equal to 5 V on VIN, or directly connect the 5 V source to both VIN and PVCC. 5/ 6/ 7/ DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/10608 PAGE 3 2. APPLICABLE DOCUMENTS JEDEC Solid State Technology Association JEDEC PUB 95 JESD78 JESD22-C101 - JESD22-A114 JESD22-A115 - Registered and Standard Outlines for Semiconductor Devices IC Latch-Up test Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronics Components Electrostatic Discharge Sensitivity Testing Human Body Model (HBM) Electrostatic Discharge Sensitivity Testing Machine Model (MM) (Applications for copies should be addressed to the JEDEC Office, 3103 North 10th Street, Suite 240-S, Arlington, VA 22201-2107 or online at http://www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as follows: A. B. C. Manufacturer’s name, CAGE code, or logo Pin 1 identifier ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/10608 PAGE 4 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/ Temperature, TA Device type Limits Min Unit Max VCC supply current section. Nominal supply VIN current IQ_VIN +25°C PVIN = VIN = 20 V, no load, 01,02 36 typical mA FSW = 700 kHz 27 typical +25°C PVIN = VIN = 4.5 V, no load, FSW = 700 kHz Shutdown supply VCC current IVCC EN = 0 V, VCC = 2.97 V +25°C 01,02 9 typical mA Internal linear regulator section. Maximum current IPVCC PVCC = 4 V to 5.6 V +25°C 01,02 320 typical mA Saturated equivalent impedance RLDO P-channel MOSFET (VIN = 5 V) +25°C 01,02 1 typical Ω Rising VCC threshold -55°C to +125°C 01,02 2.98 V Falling VCC threshold -55°C to +125°C 01,02 2.75 V Rising PVCC threshold -55°C to +125°C 01 3.05 V 02 2.98 -55°C to +125°C 01,02 2.75 +25°C 01,02 -55°C to +125°C 01,02 0.75 0.86 V -55°C to +125°C 01 21 35 µA 02 19 35 Power on reset section. 3/ Falling PVCC threshold System soft start delay tSS_DLY ENABLE section. 3/ After PLL, VCC, and PVCC PORs, and EN above their threshold Turn on threshold voltage Hysteresis sink current IEN_HYS Undervoltage lockout hysteresis VEN_HYS VEN_RTH = 10.6 V, VEN_FTH = 9 V, RUP = 53.6 kΩ, RDOWN = 5.23 kΩ, +25°C 01,02 Sink current IEN_SINK VEN = 1 V -55°C to +125°C 01,02 Sink impedance REN_SINK VEN = 1 V -55°C to +125°C 01,02 384 typical V cycles 1.6 typical V 10 mA Ω 64 See footnotes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/10608 PAGE 5 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ Temperature, TA Device type Limits Min Unit Max Oscillator section. Oscillator frequency FOSC Total variation 3/ RFS = 59 kΩ, see figure 3 VCC = 5 V +25°C 01,02 700 typical kHz -55°C to +125°C 01,02 -12 +12 % -55°C to +125°C 01,02 FOSC 1500 kHz -55°C to +125°C 01,02 10 90 % -55°C to +125°C 01,02 310 425 ns +25°C 01,02 175 typical ns +25°C 01,02 0 10 A +25°C 01,02 0.15 typical % Frequency synchronization and phase lock loop (PLL) section. 3/ Synchronization frequency Input signal duty cycle range VCC = 5.4 V 4/ Pulse width modulation (PWM) section. Minimum PWM off time tMIN_OFF Current sampling blanking time tBLANKING 3/ Output characteristics section. Output continuous current range IOUT(DC) Line regulation accuracy ∆VOUT / VOUT = 1.2 V, IOUT = 0 A, ∆VIN PVIN = VIN = 3.5 V to 20 V PVIN = VIN = 12 V, VOUT = 1.2 V, see figures 4 and 5 0.15 typical VOUT = 1.2 V, IOUT = 10 A, PVIN = VIN = 5 V to 20 V Load regulation accuracy ∆VOUT / IOUT = 0 A to 10 A, ∆IOUT VOUT = 1.2 V, +25°C 01,02 0.1 typical % +25°C 01,02 27 typical mVPP PVIN = VIN = 12 V Output ripple voltage ∆VOUT IOUT = 10 A, VOUT = 1.2 V, PVIN = VIN = 12 V See footnotes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/10608 PAGE 6 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ Temperature, TA Device type Limits Min Unit Max Dynamic characteristics section. Voltage change for positive load step ∆VOUT-DP IOUT = 0 A to 5 A, current slew rate = 2.5 A/µs, PVIN = VIN = 12 V, +25°C 01,02 45 typical mVPP +25°C 01,02 55 typical mVPP -55°C to +125°C 01 -0.9 0.9 02 -0.95 0.95 VOUT = 1.2 V Voltage change for negative load step ∆VOUT-DN IOUT = 5 A to 0 A, current slew rate = 2.5 A/µs, PVIN = VIN = 12 V, VOUT = 1.2 V Reference section. 3/ Reference voltage (include error and differential amplifiers’ offset) VREF1 % Differential amplifier section. 3/ DC gain UG_DA Unity gain bandwidth UGBW_DA Maximum source current for current sharing IVSEN1- Output voltage swing Unity gain amplifier +25°C 01,02 0 typical dB +25°C 01,02 5 typical MHz +25°C 01 350 typical µA -55°C to +125°C 01,02 0 V VMON1 = tri-state +25°C 01,02 VCC - 0.4 typical V VCC = 2.97 V to 5.6 V +25°C 01 108 typical µA VSEN1- source current for current sharing when parallel multiple modules each of which has its own voltage loop 4/ Disable threshold VVSEN- VCC 1.8 Overcurrent protection section. 3/ Channel overcurrent limit ISOURCE -55°C to +125°C VCC = 5 V Share pin OC threshold VOC_ISHARE 02 +25°C VCC = 2.97 V to 5.6 V VCC = 5 V -55°C to +125°C Comparator offset included -55°C to +125°C 01,02 84 122 111 typical 84 129 1.16 1.22 V See footnotes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/10608 PAGE 7 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ Temperature, TA Device type Limits Unit Min Max -15 -11 Power good monitor section. 3/ Undervoltage (UV) falling trip point VUVF Percentage below reference point Undervoltage (UV) rising hysteresis VUVR_HYS Percentage above UV trip point Overvoltage (OV) rising trip point VOVR Percentage above reference point Overvoltage (OV) falling hysteresis VOVF_HYS Percentage below OV trip point -55°C to +125°C 01,02 +25°C 01,02 -55°C to +125°C 01,02 +25°C 01,02 % 4 typical 11 % 15 % 4 typical % PGOOD low output voltage IPGOOD = 2 mA -55°C to +125°C 01,02 0.35 V Sinking impedance IPGOOD = 2 mA -55°C to +125°C 01,02 70 Ω Maximum sinking current VPGOOD < 0.8 V +25°C 01,02 Overvoltage (OV) protection section. 3/ OV latching trip point EN = UGATE = LATCH low, LGATE = high -55°C to +125°C 01,02 OV non-latching trip point EN = low, UGATE = low, LGATE = high +25°C 01,02 113 typical % LGATE release trip point EN = low / high, UGATE = low, LGATE = low +25°C 01,02 87 typical % Over temperature trip 01,02 150 typical °C Over temperature release threshold 01,02 125 typical °C 10 typical 118 mA 122 % Over temperature protection section. See footnotes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/10608 PAGE 8 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ Temperature, TA Device type Limits Min Unit Max Internal component values section. Internal resistor between PVCC and VCC pin RCC +25°C 01,02 5 typical Ω Internal resistor between PHASE and OCSET pin RISEN-IN +25°C 01,02 2.2 typical kΩ Internal resistor between FSYNC_IN and SGND pin RFS +25°C 01,02 59 typical kΩ Internal resistor between PGOOD and VCC pin RPG +25°C 01,02 10 typical kΩ Internal resistor between CLKOUT and VCC pin RCLK +25°C 01,02 10 typical kΩ Internal resistor between PH_CNTRL and VCC pin RPHC +25°C 01,02 10 typical kΩ Internal resistor between VOUT_SET and VSEN_REM- pin ROS1 +25°C 01,02 2.2 typical kΩ 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Unless otherwise specified, parameters with minimum and maximum limits are 100% tested at +25°C. Temperature limits established by characterization and are not production tested. 3/ Parameters are 100% tested for internal integrated circuit prior to module assembly. 4/ Limits are considered typical and are not production tested. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/10608 PAGE 9 Case X FIGURE 1. Case outline. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/10608 PAGE 10 Case X - continued. Dimensions Inches Symbol A Millimeters Min Max Min Max 0.079 0.094 2.0 2.4 A1 0.010 BSC 0.25 BSC b 0.020 BSC 0.5 BSC b1 --- 0.028 --- 0.7 b2 --- 0.031 --- 0.8 D 0.614 0.630 15.6 16.0 D1 0.583 0.598 14.8 15.2 D2 --- 0.127 --- 3.22 D3 --- 0.087 --- 2.2 D4 --- 0.134 --- 3.4 D5 --- 0.168 --- 4.26 D6 --- 0.031 --- 0.8 D7 --- 0.189 --- 4.8 D8 --- 0.229 --- 5.82 D9 --- 0.093 --- 2.36 D10 --- 0.053 --- 1.34 D11 --- 0.032 --- 0.82 D12 --- 0.079 --- 2.0 FIGURE 1. Case outline - continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/10608 PAGE 11 Case X - continued. Dimensions Inches Symbol Millimeters Min Max Min Max E 0.614 0.630 15.6 16.0 E1 0.583 0.598 14.8 15.2 E2 --- 0.543 --- 13.8 E3 --- 0.390 --- 9.9 E4 --- 0.185 --- 4.7 E5 --- 0.172 --- 4.38 E6 --- 0.185 --- 4.7 E7 --- 0.134 --- 3.4 E8 --- 0.090 --- 2.28 e 0.039 0.047 1.0 1.2 e1 0.047 0.055 1.2 1.4 e2 0.102 BSC 2.6 BSC L 0.008 0.024 0.2 0.6 L1 0.070 0.075 1.80 1.90 L2 --- 0.035 --- 0.90 L3 --- 0.029 --- 0.75 L4 0.073 0.077 1.85 1.95 s --- 0.040 --- 1.02 NOTES: 1. Controlling dimensions are millimeter, inch dimensions are given for reference only. 2. Unless otherwise specified, tolerance: decimal ±0.2, body tolerance ±0.2 mm. 3. The configuration of the pin 1 identifier is optional, but must be located within the zone indicated. The pin 1 identifier may be either a mold or mark feature. 4. See manufacturer’s datasheet for the recommended land pattern or stencil pattern. FIGURE 1. Case outline - continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/10608 PAGE 12 Device types 01 and 02 Case outline X Terminal number Terminal symbol 1 VOUT_SET 2 VSEN_REM- 3 ISFETDRV 4 PGND1 5 ISET 6 ISHARE 7 FSYNC IN 8 CLKOUT 9 PH_CNTRL 10 ISHARE_BUS 11 FF 12 EN 13 VIN 14 PVCC 15 PGND1 16 PHASE 17 PVIN 18 PGND 19 VOUT 20 OCSET 21 VCC 22 PGOOD 23 NC FIGURE 2. Terminal connections. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/10608 PAGE 13 Terminal number Terminal symbol Description VOUT_SET Analog voltage input. Used with VOUT to program the regulator output voltage. The typical input impedance of VOUT_SET with respect to VSEN_REM- is 600 kΩ for device type01 and VOUT_SET with respect to VSEN_REM- is 500 kΩ for device type 02. Voltage input typically 0.6 V. 2 VSEN_REM- Analog voltage input. This pin is the negative input of standard unity gain operational amplifier for differential remote sense for the regulator, and should connect to the negative rail of the load / processor. This pin can be used for VOUT trimming by connecting a resistor from this pin to the VOUT_SET pin. 3 ISFETDRV Digital output. This pin is used to drive an optional NFET, which will connect ISHARE with the system ISHARE bus upon completing a pre-bias startup. Voltage output range: 0 V to 5 V. 4, 15 PGND1 1 5 ISET 6 ISHARE Normal ground. All voltage levels are referenced to this pad. This pad provides a return path for the low side MOSFET drives and internal power circuitries as well as all analog signals. PGND and PGND1 should be connected together with a ground plane. Analog current output. This pin sources a 15 µA offset current plus channel 1’s average current. The voltage (VISET) set by an external resistor (RISET) represents the average current level of the local active module. For full scale current, RISET should be ~ 10 kΩ. Output current range: 15 µA to 123 µA typically for device type 01 and 15 µA to 126 µA typically for device type 02. The ISET and ISHARE pins are used for current sharing purposes with multiple device modules. In the single module configuration, this pin can be tied to the ISHARE pin. In multi-phase operation, if noise is a concern, add an additional 10pFcapacitor to the ISET line. Analog current output. Cascaded system level overcurrent shutdown pin. This pin is used where you have multiple modules configured for current sharing and is used with a common current share bus. The bus sums each of the modules’ average current contribution to the load to protect for an overcurrent condition at the load. The pin sources 15 µA plus average module’s output current. The shared bus voltage (VISHARE) is developed across an external resistor (RISHARE). VISHARE represents the average current of all active channel(s) that connected together. The ISHARE bus voltage is compared with each module’s internal reference voltage set by each module’s RISET resistor. This will generate and individual current share error signal in each cascaded controller. The share bus impedance RISHARE should be set as RISET/NCTRL, RISET divided by number of active current sharing controllers. The output current from this pin generates a voltage across the external resistor. This voltage, VISHARE, is compared to and internal 1.2 V threshold for average overcurrent protection. For full-scale current, RISHARE should be ~ 10 kΩ. Typically 10 kΩ is used for RSHARE and RSET. Output current range: 15 µA to 123 µA typically for device type 01 and 15 µA to 126 µA typically for device type 02. FIGURE 2. Terminal connections - continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/10608 PAGE 14 Terminal number Terminal symbol Description 7 FSYNC IN 8 CLKOUT 9 PH_CNTRL 10 ISHARE_BUS 11 FF 12 13 Analog input control pin. An optional external resistor (RFS-ext) connected to this pin and ground will increase the oscillator switching frequency. It has an internal 59 kΩ resistor for a default frequency of 700 kHz. The internal oscillator will lock to an external frequency source when connected to a square waveform. The external source is typically the CLKOUT signal from another identical device or an external clock. The internal oscillator synchronizes with the leading positive edge of the input signal. Input voltage range for external source: 0 V to 5 V square wave. When not synchronized to an external clock, a 100 pF capacitor between FSYNC_IN and PGND1 is recommended. Digital voltage output. This pin provides a clock signal to synchronize with other identical devices. When there is more than one identical device in the system, the two independent regulators can be programmed via PH_CNTRL for different degrees of phase delay. Analog input. The voltage level on this pin is used to program the phase shift of CLKOUT clock signal to synchronize with other module(s). Open pin until first PWM pulse is generated. Then, via an internal field effect transistor (FET), this pin connects the module’s ISHARE to the system’s ISHARE bus after pre-bias is complete and soft-start is initiated. Analog voltage input. The voltages on this pin is fed into the controller, adjusting the sawtooth amplitude to generate the feed forward function. Voltage input 0.8 V to VCC. Typically FF is connected to EN. EN This is a double function pin: Analog input voltage. The input voltage to this pin is compared with a precision 0.8 V reference and enables the digital soft start. Input voltage range is 0 V to VCC or VIN through a pull up resistor maintaining a typical current of 5 mA. Analog voltage output. This pin can be used as a voltage monitor for input bus undervoltage lockout. The hysteresis levels of the lockout can be programmed via this pin using a resistor divider network. Furthermore, during fault conditions (such as overvoltage, overcurrent, and over temperature), this pin is used to communicate the information to other cascaded modules by pulling low the wired OR as it is an open drain. Output voltage range is 0 V to VCC. VIN Analog voltage input. This pin should be tied directly to the input rail when using the internal linear regulator. It provides power to the internal linear drive circuitry. When used with an external 5 V supply, this pin should be tied directly to VCC. The internal linear device is protected against the reversed bias generated by the remaining charge of the decoupling capacitor at VCC when losing the input rail. Input voltage range 4.5 V to 20 V. FIGURE 2. Terminal connections - continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/10608 PAGE 15 Terminal number Terminal symbol Description 14 PVCC Analog output. This pin is the output of the internal series linear regulator. It provides the bias for both low side and high side drives. Its operational voltage range is 4.5 V to 5.6 V. The decoupling ceramic capacitor in the PVCC pin is 10 µF 16 PHASE Analog output. This pin is the phase node of the regulator. Output voltage range 0 V to 30 V. 17 PVIN Analog input. This input voltage is applied to the power FETS with the FET’s ground being the PGND pin. It is recommended to place input decoupling capacitance, 22 µF, directly between PVIN pin and PGND pin as close as possible to the module. Input voltage range: 3 V to 20 V. 18 PGND All voltage levels are referenced to this pad. This is the low side MOSFET ground. PGND and PGND1 should be connected together with a ground plane. 19 VOUT Output voltage from the module. Output voltage range: 0.6 V to 7.5 V. 20 OCSET Analog input. This pin is used with PHASE pin to set the current limit of the module. Input voltage range 0 V to 30 V. VCC Analog input. This pin provides bias power for the analog circuitry. It’s operational range is 4.5 V to 5.6 V. In 3.3 V application, VCC, PVCC, and VIN should be shorted to allow operation at the low end input as it relates to the VCC falling threshold limit. This pin can be powered either by the internal linear regulator or by an external voltage source. 22 PGOOD Analog output. This pin, pulled up to VCC via a 10 kΩ resistor, provides an power good signal when the output is within 9% of nominal output regulation point with 4 % hysteresis (13% / 9%), and soft start is complete. PGOOD monitors the outputs (VMON) of the internal differential amplifiers. Output voltage range: 0 V to VCC. 23 NC PD1 PHASE thermal pad Used for both the PHASE pin (pin 16) and for heat removal connecting to heat dissipation layers using vias. Potential should be floating and not electrically connected to anything except PHASE, pin 16. PD2 VIN thermal pad Used for both the PVIN (pin 17) and for heat removal connecting to heat dissipation layers using vias. Potential should be floating and not electrically connected to anything except PVIN, pin 17. PD3 PGND thermal pad Used for both the PGND pin (pin 18) and for heat removal connecting to heat dissipation layers using vias. Potential should be floating and not electrically connected to anything except PGND, pin 18. PD4 VOUT thermal pad Used for both the VOUT (pin 19) and for heat removal connecting to heat dissipation layers using vias. Potential should be floating and not electrically connected to anything except VOUT, pin 19. 21 Not internal connected. FIGURE 2. Terminal connections - continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/10608 PAGE 16 FIGURE 3. External frequency setting resistance versus switching frequency. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/10608 PAGE 17 FIGURE 4. Derating curve (5 VIN). FIGURE 5. Derating curve (12 VIN). DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/10608 PAGE 18 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Part marking Vendor part number 2/ V62/10608-01XB 34371 8200MMREP ISL8200MMREP V62/10608-02XB 34371 ISL8200AMMREP ISL8200AMMREP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. 2/ Add “-T” suffix for tape and reel. CAGE code 34371 DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Source of supply Intersil Corporation 1001 Murphy Ranch Road Milpitas, CA 95035-6803 SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/10608 PAGE 19