EL8170, EL8173 ® Data Sheet August 31, 2009 Micropower, Single Supply, Rail-to-Rail Input-Output Instrumentation Amplifiers The EL8170 and EL8173 are micropower instrumentation amplifiers optimized for single supply operation over the +2.4V to +5.5V range. Inputs and outputs can operate rail-to-rail. As with all instrumentation amplifiers, a pair of inputs provide very high common-mode rejection and are completely independent from a pair of feedback terminals. The feedback terminals allow zero input to be translated to any output offset, including ground. A feedback divider controls the overall gain of the amplifier. The EL8170 is compensated for a gain of 100 or more, and the EL8173 is compensated for a gain of 10 or more. The EL8170 and EL8173 have bipolar input devices for best offset and 1/f noise performance. The amplifiers can be operated from one lithium cell or two Ni-Cd batteries. The EL8170 and EL8173 input range includes ground to slightly above positive rail. The output stage swings to ground and positive supply (no pull-up or pull-down resistors are needed). FN7490.6 Features • 95µA Maximum Supply Current • Maximum Offset Voltage - 200µV (EL8170) - 1000µV (EL8173) • Maximum 3nA Input Bias Current • 396kHz -3dB Bandwidth (G = 10) • 192kHz -3dB Bandwidth (G = 100) • Single Supply Operation - Input Voltage Range is Rail-to-Rail - Output Swings Rail-to-Rail • Pb-Free (RoHS Compliant) Applications • Battery- or Solar-Powered Systems • Strain Gauges • Current Monitors • Thermocouple Amplifiers Pinouts Ordering Information EL8170 (8 LD SOIC) TOP VIEW DNC 1 IN- 2 + + Σ IN+ 3 V- 4 PART NUMBER (Note) 8 FB+ IN- 2 + Σ IN+ 3 PKG. DWG. # EL8170FSZ* 8170FSZ 8 Ld SOIC M8.15E EL8173FSZ* 8173FSZ 8 Ld SOIC M8.15E 6 VOUT *Add “-T7” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 EL8173 (8 LD SOIC) TOP VIEW + - PACKAGE (Pb-Free) 7 V+ 5 FB- DNC 1 PART MARKING 8 FB+ 7 V+ 6 VOUT V- 4 5 FB- 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2006-2009. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. EL8170, EL8173 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage, V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.75V, 1V/µs Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Differential Input Voltage EL8170 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V EL8173 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0V ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV Thermal Resistance (Typical Note 1) θJA (°C/W) 8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . 110 Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . . . . . .Indefinite Ambient Operating Temperature . . . . . . . . . . . . . . .-40°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER V+ = +5V, V- = GND, VCM = 1/2V+, RL = Open, TA = +25°C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. DESCRIPTION CONDITIONS MIN (Note 2) TYP MAX (Note 2) UNIT DC SPECIFICATIONS VOS TCVOS Input Offset Voltage Input Offset Voltage Temperature Coefficient EL8170 -200 -300 ±50 200 300 µV EL8173 -1000 -1500 ±200 1000 1500 µV EL8170 0.24 µV/°C EL8173 2.5 µV/°C IOS Input Offset Current between IN+, and IN- and between FB+ and FB- -2 -3 ±0.2 2 3 nA IB Input Bias Current (IN+, IN-, FB+, and FB- terminals) -3 -4 ±0.7 3 4 nA VIN Input Voltage Range Guaranteed by CMRR test 5 V CMRR Common Mode Rejection Ratio EL8170 VCM = 0V to +5V EL8173 PSRR Power Supply Rejection Ratio EL8170 V+ = +2.4V to +5.5V EL8173 EG Gain Error EL8170 RL = 100kΩ to +2.5V EL8173 VOUT Maximum Voltage Swing 0 90 85 114 dB 85 80 106 dB 85 80 106 dB 75 70 90 dB -1.5 2 +0.35 1.5 2 % -0.4 -0.8 +0.1 0.4 0.8 % 4 10 mV 0.13 0.2 0.25 V Output low, RL = 100kΩ to +2.5V Output low, RL = 1kΩ to +2.5V IS Supply Current VSUPPLY Supply Operating Range 2 Output high, RL = 100kΩ to +2.5V 4.985 4.980 4.996 V Output high, RL = 1kΩ to +2.5V 4.75 4.887 V 45 38 65 V+ to V- 2.4 95 110 µA 5.5 V FN7490.6 August 31, 2009 EL8170, EL8173 Electrical Specifications PARAMETER IO+ IO- V+ = +5V, V- = GND, VCM = 1/2V+, RL = Open, TA = +25°C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) DESCRIPTION CONDITIONS Output Source Current into 10Ω to V+/2 V+ = +5V Output Sink Current into 10Ω to V+/2 MIN (Note 2) TYP MAX (Note 2) UNIT 23 19 32 mA V+ = +2.4V 6 4.5 8 mA V+ = +5V 19 15 26 mA V+ = +2.4V 5 4 7 mA Gain = 100 192 kHz Gain = 200 93 kHz AC SPECIFICATIONS -3dB BW -3dB Bandwidth EL8170 EL8173 eN Input Noise Voltage EL8170 Gain = 500 30 kHz Gain = 1000 13 kHz Gain = 10 396 kHz Gain = 20 221 kHz Gain = 50 69 kHz Gain = 100 30 kHz f = 0.1Hz to 10Hz 3.5 µVP-P 3.6 µVP-P EL8173 Input Noise Voltage Density EL8170 fo = 1kHz EL8173 iN Input Noise Current Density CMRR @ 60Hz Input Common Mode Rejection Ratio Power Supply Rejection Ratio (V+) PSRR- @ 120Hz Power Supply Rejection Ratio (V-) nV/√Hz nV/√Hz EL8170 fo = 1kHz 0.38 pA/√Hz EL8173 fo = 1kHz 0.8 pA/√Hz EL8170 VCM = 1VP-P, RL = 10kΩ to VCM 100 dB 84 dB V+, V- = ±2.5V, VSOURCE = 1VP-P, RL = 10kΩ to VCM 98 dB 78 dB 106 dB 82 dB EL8173 PSRR+ @ 120Hz 58 220 EL8170 EL8173 EL8170 EL8173 V+, V- = ±2.5V, VSOURCE = 1VP-P, RL = 10kΩ to VCM TRANSIENT RESPONSE SR RL = 1kΩ to GND Slew Rate 0.4 0.35 0.55 0.7 0.7 V/µs NOTE: 2. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 3 FN7490.6 August 31, 2009 EL8170, EL8173 Typical Performance Curves V+ = +5V, V- = 0V, VCM = +2.5V, RL = Open, unless otherwise specified. 90 70 COMMON-MODE INPUT = 1/2V+ GAIN = 10,000V/V 80 COMMON-MODE INPUT = 1/2V+ GAIN = 1000 60 GAIN = 500 GAIN = 5,000V/V 50 GAIN = 2,000V/V GAIN (dB) GAIN (dB) 70 GAIN = 1,000V/V 60 GAIN = 500V/V 50 30 GAIN = 100V/V 1 10 GAIN = 100 40 GAIN = 50 30 GAIN = 200V/V 40 GAIN = 200 GAIN = 20 GAIN = 10 20 100 1k 10k 100k 10 1E+00 1M 1E+01 1E+02 1E+03 1E+04 FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 1. EL8170 FREQUENCY RESPONSE vs CLOSED LOOP GAIN 1E+05 1E+06 FIGURE 2. EL8173 FREQUENCY RESPONSE vs CLOSED LOOP GAIN 45 V+ = 5V V+ = 5V 40 20 35 25 GAIN (dB) GAIN (dB) V+ = 3.3V V+ = 3.3V 30 V+ = 2.4V 20 15 10 5 AV = 100 RL = 10kΩ CL = 10pF RF/RG = 99.02 RF = 221kΩ RG = 2.23kΩ 0 100 15 10 5 1k 10k 100k V+ = 2.4V AV = 10 R = 10kΩ CL = 10pF RF/RG = 9.08Ω RF = 178kΩ RG = 19.6kΩ 0 100 1M 1k FREQUENCY (Hz) FIGURE 3. EL8170 FREQUENCY RESPONSE vs SUPPLY VOLTAGE CL = 100pF 25 CL = 47pF CL = 820pF 20 GAIN (dB) CL = 470pF GAIN (dB) 1M 30 45 40 CL = 220pF 30 100k FIGURE 4. EL8173 FREQUENCY RESPONSE vs SUPPLY VOLTAGE 50 35 10k FREQUENCY (Hz) CL = 56pF AV = 100 V+, V- = ±2.5V RL = 10kΩ RF/RG = 99.02 RF = 221kΩ RG = 2.23kΩ 25 100 CL = 27pF 15 CL = 2.7pF 10 5 1k 10k 100k 1M AV = 10 V+ = 5V RL = 10kΩ RF/RG = 9.08Ω RF = 178kΩ RG = 19.6kΩ 0 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 5. EL8170 FREQUENCY RESPONSE vs CLOAD 4 FIGURE 6. EL8173 FREQUENCY RESPONSE vs CLOAD FN7490.6 August 31, 2009 EL8170, EL8173 Typical Performance Curves V+ = +5V, V- = 0V, VCM = +2.5V, RL = Open, unless otherwise specified. 120 (Continued) 90 80 100 70 60 CMRR CMRR (dB) CMRR (dB) 80 60 40 CMRR 50 40 30 20 10 20 0 0 -10 10 100 1k 10k 100k 1M 10 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 8. EL8173 CMRR vs FREQUENCY FIGURE 7. EL8170 CMRR vs FREQUENCY 140 90 120 80 PSRR+ PSRR+ 70 100 PSRR (dB) PSRR (dB) 60 80 PSRR- 60 PSRR50 40 30 40 20 20 10 0 10 100 1k 10k 100k 0 10 1M 100 100k 1M 2.5 INPUT VOLTAGE NOISE (µV/√Hz) 250 INPUT VOLTAGE NOISE (nV/√Hz) 10k FIGURE 10. EL8173 PSRR vs FREQUENCY FIGURE 9. EL8170 PSRR vs FREQUENCY 200 150 100 50 1k FREQUENCY (Hz) FREQUENCY (Hz) 2.0 1.5 1.0 0.5 0.0 1 10 100 1k 10k FREQUENCY (Hz) FIGURE 11. EL8170 VOLTAGE NOISE DENSITY 5 100k 1 10 100 1k 10k 100k FREQUENCY (Hz) FIGURE 12. EL8173 VOLTAGE NOISE DENSITY FN7490.6 August 31, 2009 EL8170, EL8173 Typical Performance Curves V+ = +5V, V- = 0V, VCM = +2.5V, RL = Open, unless otherwise specified. 5.0 4.5 0.9 CURRENT NOISE (pA/√Hz) CURRENT NOISE (pA/√Hz) 1.0 0.8 0.7 0.6 0.5 0.4 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.3 1 10 100 1k 10k 0.0 100k 1 10 100 FIGURE 13. EL8170 CURRENT NOISE DENSITY 100k 10k VOLTAGE NOISE (0.5µV/DIV) VOLTAGE NOISE (0.5µV/DIV) FIGURE 14. EL8173 CURRENT NOISE DENSITY TIME (1s/DIV) TIME (1s/DIV) FIGURE 15. EL8170 0.1Hz TO 10Hz INPUT VOLTAGE NOISE (GAIN = 100) FIGURE 16. EL8173 0.1Hz TO 10Hz INPUT VOLTAGE NOISE (GAIN = 10) 90 85 N = 2000 85 80 MAX 75 SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) 1k FREQUENCY (Hz) FREQUENCY (Hz) 70 65 MEDIAN 60 55 MIN 50 45 40 (Continued) N = 1000 80 MAX 75 MEDIAN 70 65 60 MIN 55 50 45 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 17. EL8170 SUPPLY CURRENT vs TEMPERATURE, V+, V- = ±2.5V, VIN = 0V 6 40 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 18. EL8173 SUPPLY CURRENT vs TEMPERATURE, V+, V- = ±2.5V, VIN = 0V FN7490.6 August 31, 2009 EL8170, EL8173 Typical Performance Curves V+ = +5V, V- = 0V, VCM = +2.5V, RL = Open, unless otherwise specified. 300 1000 N = 2000 N = 1000 MAX 200 MAX 500 VOS (µV) 100 VOS (µV) (Continued) MEDIAN 0 -100 MIN -300 -20 0 20 40 -500 MIN -1000 -200 -40 MEDIAN 0 60 80 100 -1500 120 -40 -20 20 40 60 80 TEMPERATURE (°C) 0 TEMPERATURE (°C) FIGURE 19. EL8170 VOS vs TEMPERATURE, V+, V- = ±2.5V, VIN = 0V 100 120 FIGURE 20. EL8173 VOS vs TEMPERATURE, V+, V- = ±2.5V, VIN = 0V 400 1000 N = 1000 N = 2000 MAX 300 MAX 500 VOS (µV) VOS (µV) 200 100 MEDIAN 0 -100 MIN 0 MEDIAN -500 -1000 -200 MIN -300 -1500 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 -40 120 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 21. EL8170 VOS vs TEMPERATURE, V+, V- = ±1.2V, VIN = 0V FIGURE 22. EL8173 VOS vs TEMPERATURE, V+, V- = ±1.2V, VIN = 0V 140 140 N = 2000 N = 1000 MAX MAX 130 120 CMRR (dB) 130 CMRR (dB) -20 MEDIAN 110 100 120 MEDIAN 110 100 MIN 90 90 80 -40 -20 0 20 40 60 80 100 TEMPERATURE (°C) FIGURE 23. EL8170 CMRR vs TEMPERATURE, VCM = +2.5V TO -2.5V, V+, V- = ±2.5V 7 120 80 -40 MIN -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 24. EL8173 CMRR vs TEMPERATURE, VCM = +2.5V TO -2.5V, V+, V- = ±2.5V FN7490.6 August 31, 2009 EL8170, EL8173 Typical Performance Curves V+ = +5V, V- = 0V, VCM = +2.5V, RL = Open, unless otherwise specified. 140 N = 2000 MAX 130 130 120 120 MEDIAN 110 PSRR (dB) PSRR (dB) 140 100 90 80 N = 1000 MAX 110 100 MEDIAN 90 80 MIN MIN 70 (Continued) 70 60 -40 -20 0 20 40 60 80 100 60 -40 120 -20 0 TEMPERATURE (°C) 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 26. EL8173 PSRR vs TEMPERATURE, V+, V- = ±1.2V TO ±2.5V FIGURE 25. EL8170 PSRR vs TEMPERATURE, V+, V- = ±1.2V TO ±2.5V 2.4 0.7 N = 1000 N = 2000 0.6 GAIN ERROR (%) GAIN ERROR (%) 1.9 MAX 1.4 0.9 MEDIAN 0.4 0.4 MAX 0.3 0.2 MEDIAN 0.1 0 MIN -0.1 -40 0.5 MIN -20 0 20 40 60 80 100 -0.1 -40 120 -20 0 TEMPERATURE (°C) FIGURE 27. EL8170 %GAIN ERROR vs TEMPERATURE, RL = 100k 60 80 100 120 4.91 N = 2000 N = 1000 4.90 4.90 MAX 4.89 MAX 4.89 VOUT (V) MEDIAN 4.88 4.87 MEDIAN 4.88 4.87 MIN MIN 4.86 4.86 4.85 4.85 4.84 -40 40 FIGURE 28. EL8173 %GAIN ERROR vs TEMPERATURE, RL = 100k 4.91 VOUT (V) 20 TEMPERATURE (°C) -20 0 20 40 60 80 100 TEMPERATURE (°C) FIGURE 29. EL8170 VOUT HIGH vs TEMPERATURE, RL = 1k, V+, V- = ±2.5V 8 120 4.84 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 30. EL8173 VOUT HIGH vs TEMPERATURE, RL = 1k, V+, V- = ±2.5V FN7490.6 August 31, 2009 EL8170, EL8173 Typical Performance Curves V+ = +5V, V- = 0V, VCM = +2.5V, RL = Open, unless otherwise specified. 200 200 N = 1000 180 180 160 160 VOUT (mV) VOUT (mV) N = 2000 MAX 140 MEDIAN 120 MAX 140 120 MIN -20 0 20 40 60 80 100 80 -40 120 -20 0 + SLEW RATE (V/µS) + SLEW RATE (V/µS) 100 120 MAX 0.65 MEDIAN 0.50 MIN 0.45 0.40 0.60 MEDIAN 0.55 0.50 MIN 0.45 0.35 -20 0 20 40 60 80 100 0.40 -40 120 -20 0 FIGURE 33. EL8170 + SLEW RATE vs TEMPERATURE, INPUT ±0.015V @ GAIN + 100 60 80 100 120 MAX N = 1000 MAX 0.65 40 FIGURE 34. EL8173 + SLEW RATE vs TEMPERATURE, INPUT ±0.015V @ GAIN + 100 0.70 N = 2000 20 TEMPERATURE (°C) TEMPERATURE (°C) 0.65 - SLEW RATE (V/µS) - SLEW RATE (V/µS) 80 N = 1000 MAX 0.55 0.60 MEDIAN 0.55 0.50 MIN 0.45 0.40 MEDIAN 0.60 0.55 MIN 0.50 0.45 0.35 0.30 -40 60 0.70 N = 2000 0.60 0.70 40 FIGURE 32. EL8173 VOUT LOW vs TEMPERATURE, RL = 1k, V+, V- = ±2.5V FIGURE 31. EL8170 VOUT LOW vs TEMPERATURE, RL = 1k, V+, V- = ±2.5V 0.30 -40 20 TEMPERATURE (°C) TEMPERATURE (°C) 0.65 MEDIAN MIN 100 100 80 -40 (Continued) -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 35. EL8170 - SLEW RATE vs TEMPERATURE, INPUT ±0.015V @ GAIN + 100 9 0.40 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 36. EL8173 - SLEW RATE vs TEMPERATURE, INPUT ±0.015V @ GAIN + 100 FN7490.6 August 31, 2009 EL8170, EL8173 Pin Descriptions EQUIVALENT CIRCUIT EL8170, EL8173 PIN NAME PIN FUNCTION 1 1 DNC 2 2 IN- Circuit 1A, Circuit 1B 3 3 IN+ Circuit 1A, Circuit 1B 4 4 V- Circuit 3 5 5 FB- Circuit 1A, Circuit 1B 8 8 FB+ Circuit 1A, Circuit 1B 7 7 V+ Circuit 3 Positive supply terminal. 6 6 VOUT Circuit 2 Output voltage. Do Not Connect; Internal connection - Must be left floating. High impedance input terminals. EL8170 input circuit is shown in Circuit 1A, and the EL8173 input circuit is shown in Circuit 1B. EL8173: to avoid offset drift, it is recommended that the terminals are not overdriven beyond 1V and the input current must never exceed 5mA. Negative supply terminal. High impedance feedback terminals. EL8170 input circuit is shown in Circuit 1A, and the EL8173 input circuit is shown in Circuit 1B. EL8173: to avoid offset drift, it is recommended that the terminals are not overdriven beyond 1V and the input current must never exceed 5mA. V+ INFB- V+ IN+ FB+ OUT V- V- V+ CAPACITIVELY COUPLED ESD CLAMP V- CIRCUIT 1A CIRCUIT 2 CIRCUIT 3 V+ INFB- IN+ FB+ V- CIRCUIT 1B 10 FN7490.6 August 31, 2009 EL8170, EL8173 Description of Operation and Applications Information Product Description The EL8170 and EL8173 are micropower instrumentation amplifiers (in-amps) which deliver rail-to-rail input amplification and rail-to-rail output swing on a single +2.4V to +5.5V supply. The EL8170 and EL8173 also deliver excellent DC and AC specifications while consuming only 65µA typical supply current. Because the EL8170 and EL8173 provide an independent pair of feedback terminals to set the gain and to adjust output level, these in-amps achieve high common-mode rejection ratio regardless of the tolerance of the gain setting resistors. The EL8173 is internally compensated for a minimum closed loop gain of 10 or greater, well suited for moderate to high gains. For higher gains, the EL8170 is internally compensated for a minimum gain of 100. Input Protection All input and feedback terminals of the EL8170 and EL8173 have internal ESD protection diodes to both positive and negative supply rails, limiting the input voltage to within one diode drop beyond the supply rails. The inverting inputs and FB- inputs have ESD diodes to the V-rail, and the non-inverting inputs and FB+ terminals have ESD diodes to the V+ rail. The EL8170 has additional back-to-back diodes across the input terminals and also across the feedback terminals. If overdriving the inputs is necessary, the external input current must never exceed 5mA. On the other hand, the EL8173 has no clamps to limit the differential voltage on the input terminals allowing higher differential input voltages at lower gain applications. It is recommended however, that the input terminals of the EL8173 are not overdriven beyond 1V to avoid offset drift. An external series resistor may be used as an external protection to limit excessive external voltage and current from damaging the inputs. Input Stage and Input Voltage Range The input terminals (IN+ and IN-) of the EL8170 and EL8173 are single differential pair bipolar PNP devices aided by an Input Range Enhancement Circuit to increase the headroom of operation of the common-mode input voltage. The feedback terminals (FB+ and FB-) also have a similar topology. As a result, the input common-mode voltage range of both the EL8170 and EL8173 is rail-to-rail. These in-amps are able to handle input voltages that are at or slightly beyond the supply and ground making these in-amps well suited for single +5V or +3.3V low voltage supply systems. There is no need to move the common-mode input of the in-amps to achieve symmetrical input voltage. 11 Input Bias Cancellation, Input Bias Compensation Both EL8170 and EL8173 feature an Input Bias Cancellation/Compensation Circuit for both the input and feedback terminals (IN+, IN-, FB+ and FB-), achieving a low input bias current all throughout the input common-mode range and the operating temperature range. While the PNP bipolar input stages are biased with an adequate amount of biasing current for speed and increased noise performance, the Input Bias Cancellation/Compensation Circuit sinks most of the base current of the input transistor leaving a small portion as input bias current, typically 500pA. In addition, the Input Bias Cancellation/Compensation Circuit maintains a smooth and flat behavior of input bias current over the common mode range and over the operating temperature range. The Input Bias Cancellation, Input Bias Compensation Circuit operates from input voltages of 10mV above the negative supply to input voltages slightly above the positive supply. See “Average Input Bias Current vs Common-Mode Input Voltage” in the “Typical Performance Curves” beginning on page 4. Output Stage and Output Voltage Range A pair of complementary MOSFET devices drives the output VOUT to within a few millivolts of the supply rails. At a 100kΩ load, the PMOS sources current and pulls the output up to 4mV below the positive supply, while the NMOS sinks current and pulls the output down to 4mV above the negative supply, or ground in the case of a single supply operation. The current sinking and sourcing capability of the EL8170 and EL8173 are internally limited to 26mA. Gain Setting VIN, the potential difference across IN+ and IN-, is replicated (less the input offset voltage) across FB+ and FB-. The objective of the EL8170 and EL8173 in-amp is to maintain the differential voltage across FB+ and FB- equal to IN+ and IN-; (FB- - FB+) = (IN+ - IN-). Consequently, the transfer function can be derived. The gain of the EL8170 and EL8173 is set by two external resistors, the feedback resistor RF, and the gain resistor RG. FN7490.6 August 31, 2009 EL8170, EL8173 +2.4V TO +5.5V +2.4V TO +5.5V 7 VIN/2 3 IN+ 2 IN- VIN/2 8 FB+ 5 FB- VCM 7 1 3 IN+ V+ + 2 IN- - EL8170, EL8173 + - 6 VIN/2 8 FB+ VOUT V+ + - EL8170, EL8173 + - 6 VOUT V4 REF R2 RF FIGURE 37. GAIN IS SET BY TWO EXTERNAL RESISTORS, RF AND RG RF ⎞ ⎛ V OUT = ⎜ 1 + --------⎟ V IN R G⎠ ⎝ 5 FB- +2.4V TO +5.5V VCM R1 V4 RG 1 VIN/2 (EQ. 1) In Figure 37, the FB+ pin and one end of resistor RG are connected to GND. With this configuration, Equation 1 is only true for a positive swing in VIN; negative input swings will be ignored and the output will be at ground. RG RF FIGURE 38. GAIN SETTING AND REFERENCE CONNECTION The FB+ pin can also be connected to the other end of resistor, RG (see Figure 39). Keeping the basic concept that the EL8170 and EL8173 in-amps maintain constant differential voltage across the input terminals and feedback terminals (IN+ - IN- = FB+ - FB-), the transfer function of Figure 39 can be derived (Equation 3). Note that the VREF gain term is eliminated, and susceptibility to external noise is reduced. Reference Connection +2.4V TO +5.5V Unlike a three op amp instrumentation amplifier, a finite series resistance seen at the REF terminal does not degrade the EL8170 and EL8173's high CMRR performance, eliminating the need for an additional external buffer amplifier. The circuit shown in Figure 38 uses the FB+ pin as a REF terminal to center or to adjust the output. Because the FB+ pin is a high impedance input, an economical resistor divider can be used to set the voltage at the REF terminal. The reference voltage error due to the input bias current is minimized by keeping the values of the voltage divider resistors, R1 and R2, as low as possible. Any voltage applied to the REF terminal will shift VOUT by VREF times the closed loop gain, which is set by resistors RF and RG according to Equation 2. Note that any noise or unwanted signals on the reference supply will be amplified at the output according to Equation 2. RF ⎞ RF ⎞ ⎛ ⎛ V OUT = ⎜ 1 + --------⎟ ( V IN ) + ⎜ 1 + --------⎟ ( V REF ) R R ⎝ ⎝ G⎠ G⎠ (EQ. 2) 7 VIN/2 3 IN+ 2 IN- VIN/2 8 FB+ 5 FB- VCM 1 V+ + - EL8170, EL8173 6 VOUT + - V4 VREF RG RF FIGURE 39. REFERENCE CONNECTION WITH AN AVAILABLE VREF RF ⎞ ⎛ V OUT = ⎜ 1 + --------⎟ ( V IN ) + ( V REF ) R ⎝ G⎠ (EQ. 3) External Resistor Mismatches Because of the independent pair of feedback terminals provided by the EL8170 and EL8173, the CMRR is not degraded by any resistor mismatches. Hence, unlike a three op amp and especially a two op amp in-amp, the EL8170 and EL8173 reduce the cost of external components by allowing the use of 1% or more tolerance resistors without sacrificing CMRR performance. The EL8170 and EL8173 CMRR is maintained regardless of the tolerance of the resistors used. 12 FN7490.6 August 31, 2009 EL8170, EL8173 Gain Error and Accuracy Power Dissipation The EL8173 has a Gain Error, EG, of 0.2% typical. The EL8170 has an EG of 0.3% typical. The gain error indicated in the “Electrical Specifications” table on page 2 is the inherent gain error of the EL8170 and EL8173 and does not include the gain error contributed by the resistors. There is an additional gain error due to the tolerance of the resistors used. The resulting non-ideal transfer function effectively becomes Equation 4: It is possible to exceed the +150°C maximum junction temperatures under certain load and power-supply conditions. It is therefore important to calculate the maximum junction temperature (TJMAX) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related in Equation 6: RF ⎞ ⎛ V OUT = ⎜ 1 + --------⎟ × [ 1 – ( E RG + E RF + E G ) ] × V IN R G⎠ ⎝ T JMAX = T MAX + ( θ JA xPD MAXTOTAL ) (EQ. 6) (EQ. 4) where: • PDMAXTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PDMAX) Where: ERG = Tolerance of RG • PDMAX for each amplifier can be calculated as shown in Equation 7: ERF= Tolerance of RF EG = Gain Error of the EL8170 or EL8173 V OUTMAX PD MAX = 2*V S × I SMAX + ( V S - V OUTMAX ) × ---------------------------RL (EQ. 7) The term [1 - (ERG + ERF + EG)] is the deviation from the theoretical gain. Thus, (ERG + ERF + EG) is the total gain error. For example, if 1% resistors are used for the EL8170, the total gain error would be as shown in Equation 5: where: = ± ( E RG + E RF + E G ( typical ) ) • θJA = Thermal resistance of the package (EQ. 5) = ± ( 0.01 + 0.01 + 0.003 ) = ± 2.3% • TMAX = Maximum ambient temperature • PDMAX = Maximum power dissipation of 1 amplifier • VS = Supply voltage (Magnitude of V+ and V-) • IMAX = Maximum supply current of 1 amplifier • VOUTMAX = Maximum output voltage swing of the application • RL = Load resistance All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 13 FN7490.6 August 31, 2009 EL8170, EL8173 Package Outline Drawing M8.15E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0, 08/09 4 4.90 ± 0.10 A DETAIL "A" 0.22 ± 0.03 B 6.0 ± 0.20 3.90 ± 0.10 4 PIN NO.1 ID MARK 5 (0.35) x 45° 4° ± 4° 0.43 ± 0.076 1.27 0.25 M C A B SIDE VIEW “B” TOP VIEW 1.75 MAX 1.45 ± 0.1 0.25 GAUGE PLANE C SEATING PLANE 0.10 C 0.175 ± 0.075 SIDE VIEW “A 0.63 ±0.23 DETAIL "A" (0.60) (1.27) NOTES: (1.50) (5.40) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. The pin #1 identifier may be either a mold or mark feature. 6. Reference to JEDEC MS-012. TYPICAL RECOMMENDED LAND PATTERN 14 FN7490.6 August 31, 2009