EL8176 ® Data Sheet October 26, 2006 Micropower Single Supply Rail-to-Rail Input-Output Precision Op Amp The EL8176 is a micropower precision operational amplifier optimized for single supply operation at 5V and can operate down to 2.4V. The EL8176 draws minimal supply current while meeting excellent DC-accuracy noise and output drive specifications. Competing devices seriously degrade these parameters to achieve micropower supply current. The EL8176 can be operated from one lithium cell or two Ni-Cd batteries. The input range includes both positive and negative rail. The output swings to both rails. Ordering Information PART PART NUMBER MARKING EL8176FWZ-T7 (Note) BBVA (Bottom) EL8176FWZ-T7A BBVA (Note) (Bottom) EL8176FSZ (Note) 8176FSZ EL8176FSZ-T7 (Note) 8176FSZ FN7436.6 Features • 55µA supply current • 100µV max offset voltage (8 Ld SO) • 2nA input bias current • 400kHz gain-bandwidth product • Single supply operation down to 2.4V • Rail-to-rail input and output • Output sources 31mA and sinks 26mA load current • Pb-free plus anneal available (RoHS compliant) Applications • Battery- or solar-powered systems TAPE & REEL 7” (3k pcs) PACKAGE PKG. DWG. # 6 Ld SOT-23 MDP0038 (Pb-free) 7” 6 Ld SOT-23 MDP0038 (250 pcs) (Pb-free) 7” (1k pcs) 8 Ld SO (Pb-free) MDP0027 8 Ld SO (Pb-free) MDP0027 • 4mA to 20mA current loops • Handheld consumer products • Medical devices • Thermocouple amplifiers • Photodiode pre amps • pH probe amplifiers NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pinouts EL8176 (6 LD SOT-23) TOP VIEW OUT 1 VS- 2 6 VS+ + - IN+ 3 5 ENABLE 4 IN- EL8176 (8 LD SO) TOP VIEW NC 1 IN- 2 IN+ 3 VS- 4 1 8 ENABLE + 7 VS+ 6 VOUT 5 NC CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL8176 Absolute Maximum Ratings (TA = +25°C) Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5V, 1V/µs Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V Current into IN+, IN-, and ENABLE . . . . . . . . . . . . . . . . . . . . . . 5mA Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5V to VS+0.5V Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . . . . . .Indefinite Ambient Operating Temperature Range . . . . . . . . .-40°C to +125°C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VOS VS = 5V, 0V, VCM = 0.1V, VO = 1.4V, VENH = 2.0V, VENL = 0.8V, TA = +25°C unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. DESCRIPTION Input Offset Voltage CONDITIONS 8 Ld SO MIN TYP MAX UNIT -100 ±25 100 µV 220 µV 350 µV 350 µV -220 6 Ld SOT-23 -350 ±80 -350 ΔV OS -----------------ΔTime Long Term Input Offset Voltage Stability 2.4 µV/Mo ΔV OS ---------------ΔT Input Offset Drift vs Temperature 0.7 µV/°C IOS Input Offset Current -1 ±0.4 -4 IB Input Bias Current -2 ±0.5 -5 eN 1 nA 4 nA 2 nA 5 nA Input Noise Voltage Peak-to-Peak f = 0.1Hz to 10Hz 1 µVPP Input Noise Voltage Density fO = 1kHz 25 nV/√Hz iN Input Noise Current Density fO = 1kHz 0.1 pA/√Hz CMIR Input Voltage Range Guaranteed by CMRR test 0 CMRR Common-Mode Rejection Ratio VCM = 0V to 5V 90 PSRR 5 110 dB 90 Power Supply Rejection Ratio VS = 2.4V to 5V 90 dB 110 dB 90 AVOL Large Signal Voltage Gain VO = 0.5V to 4.5V, RL = 100kΩ 200 dB 500 V/mV 200 VOUT Maximum Output Voltage Swing V/mV VO = 0.5V to 4.5V, RL = 1kΩ 25 VOL; Output low, RL = 100kΩ 3 VOL; Output low, RL = 1kΩ VOH; Output high, RL = 100kΩ 130 4.994 4.997 4.992 VOH; Output high, RL = 1kΩ 4.750 4.7 2 V V/mV 8 mV 10 mV 200 mV 300 mV V V 4.867 V V FN7436.6 October 26, 2006 EL8176 Electrical Specifications PARAMETER VS = 5V, 0V, VCM = 0.1V, VO = 1.4V, VENH = 2.0V, VENL = 0.8V, TA = +25°C unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) DESCRIPTION CONDITIONS SR Slew Rate GBW Gain Bandwidth Product fO = 100kHz BW -3dB Bandwidth Unity gain, CLOAD = 27pF, RF = 100Ω IS,ON Supply Current, Enabled MIN TYP MAX UNIT ±0.065 ±0.13 ±0.3 V/µs 35 400 kHz 1 MHz 55 30 IS,OFF Supply Current, Disabled IO+ IO- VS Short Circuit Output Sourcing RL = 10Ω Current 18 Short Circuit Output Sinking Current RL = 10Ω 17 Minimum Supply Voltage Guaranteed by PSRR test VINH Enable Pin High Level VINL Enable Pin Low Level IENH Enable Pin Input Current IENL 3 75 µA 90 µA 10 µA 10 µA 31 mA 18 mA 26 mA 15 mA 2.2 2.4 V 2.4 V 2 V 0.8 VEN = 5V Enable Pin Input Current 0.25 VEN = 0V -0.5 V 0.7 0 -1 2.0 µA 2.5 µA +0.5 µA +1 µA Typical Performance Curves 6 45 40 VS = ±1.25V 3 35 GAIN (dB) GAIN (dB) 30 0 VS = ±2.5V -3 -6 -9 1k AV = 1 CL = 2.7pF RF = 100Ω RG = OPEN 10k 25 15 VS = ±1.0V 10 5 100k 1M 10M FREQUENCY (Hz) FIGURE 1. UNITY GAIN FREQUENCY RESPONSE vs SUPPLY VOLTAGE 3 VS = ±2.5V 20 AV = 100 RL = 10kΩ CL = 2.7pF RF/RG = 99.02 RF = 221kΩ RG = 2.23kΩ 0 100 1k VS = ±1.25V VS = ±1.0V 10k 100k 1M FREQUENCY (Hz) FIGURE 2. FREQUENCY RESPONSE vs SUPPLY VOLTAGE FN7436.6 October 26, 2006 EL8176 Typical Performance Curves (Continued) INPUT BIAS, OFFSET CURRENTS (pA) 50 40 30 20 10 0 2 2.5 3 3.5 4 4.5 5 10k 1k IB+ 100 IOS 10 1 0 5.5 FIGURE 3. SUPPLY CURRENT vs SUPPLY VOLTAGE 2 3 4 5 FIGURE 4. INPUT BIAS + OFFSET CURRENTS vs COMMON-MODE INPUT VOLTAGE 0 200 VCM = VDD/2 150 AV = -1 INPUT OFFSET VOLTAGE (µV) INPUT OFFSET VOLTAGE (µV) 1 COMMON-MODE INPUT VOLTAGE (V) SUPPLY VOLTAGE (V) 100 50 VDD = 5V 0 VDD = 2.5V -50 -100 -150 -200 -20 VOS, µV -40 -60 -80 -100 0 1 2 3 4 0 5 FIGURE 5. INPUT OFFSET VOLTAGE vs OUTPUT VOLTAGE 100 200 80 150 PHASE 3 4 5 FIGURE 6. INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE 0 GAIN GAIN (dB) 40 PHASE (°) 50 120 80 80 40 40 0 0 -40 -40 -80 -50 0 -20 10 2 100 60 20 1 COMMON-MODE INPUT VOLTAGE (V) OUTPUT VOLTAGE (V) GAIN (dB) IB- PHASE (°) SUPPLY CURRENT (µA) 60 -100 100 1k 10k 100k -150 1M FREQUENCY (Hz) FIGURE 7. AVOL vs FREQUENCY @ 1kΩ LOAD 4 -80 1 10 100 1k 10k 100k 1M -120 10M FREQUENCY (Hz) FIGURE 8. AVOL vs FREQUENCY @ 100kΩ LOAD FN7436.6 October 26, 2006 EL8176 Typical Performance Curves (Continued) 1k VOLTAGE NOISE (nV/√Hz) CURRENT NOISE (pA/√Hz) 10.00 1.00 0.10 10 100 1k 10k 10 1 10 0.01 1 100 100k 100 FREQUENCY (Hz) 1k 10k 100k FREQUENCY (Hz) FIGURE 10. VOLTAGE NOISE vs FREQUENCY FIGURE 9. CURRENT NOISE vs FREQUENCY 120 110 VOLTAGE NOISE (200nV/DIV) 100 CMRR (dB) 90 VCM = 0.2VPP 80 70 60 50 40 30 20 1µVP-P VCM = 0.2VPP 10 0 1 10 100 TIME (1s/DIV) FIGURE 11. 0.1Hz TO 10Hz INPUT VOLTAGE NOISE 10k 100k 1M FIGURE 12. CMRR vs FREQUENCY 75 120 n = 12 110 70 100 PSRR+ MEDIAN CURRENT (µA) 90 PSRR (dB) 1k FREQUENCY (Hz) 80 70 60 50 40 PSRR- 65 MAX MIN 60 55 30 50 20 10 0 1 10 100 1k 10k 100k FREQUENCY (Hz) FIGURE 13. PSRR vs FREQUENCY 5 1M 45 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 14. SUPPLY CURRENT vs TEMPERATURE VS = ±2.5V ENABLED. RL = INF FIGURE 15. FN7436.6 October 26, 2006 EL8176 Typical Performance Curves 7 2.5 MAX n = 12 2 n = 12 MAX 5 CURRENT (nA) CURRENT (µA) 6 (Continued) MEDIAN 4 3 2 MIN 1 MEDIAN 0.5 0 1 0 -40 1.5 MIN -20 0 20 40 60 80 100 -0.5 -40 120 -20 0 TEMPERATURE (°C) FIGURE 16. SUPPLY CURRENT vs TEMPERATURE VS = ±2.5V DISABLED. RL= INF CURRENT (nA) CURRENT (nA) MEDIAN 0.5 1.5 1 MEDIAN 0.5 0 0 MIN -20 MIN 0 20 40 60 80 100 -0.5 -40 120 -20 0 FIGURE 18. I BIAS (+) vs TEMPERATURE VS = ±1.2V 40 60 80 100 120 FIGURE 19. I BIAS (-) vs TEMPERATURE VS = ±2.5V 2.5 3 n = 12 n = 12 2 MAX CURRENT (nA) CURRENT (nA) 20 TEMPERATURE (°C) TEMPERATURE (°C) 1.5 MEDIAN 0.5 1.5 MAX 1 MEDIAN 0.5 0 0 MIN MIN -0.5 -40 120 MAX MAX 1 1 100 2 1.5 2 80 n = 12 2.5 2.5 60 2.5 n = 12 -0.5 -40 40 FIGURE 17. I BIAS (+) vs TEMPERATURE VS = ±2.5V 3 2 20 TEMPERATURE (°C) -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 20. I BIAS (-) vs TEMPERATURE VS = ±1.2V 6 -0.5 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 21. INPUT OFFSET CURRENT vs TEMPERATURE VS = ±2.5V FN7436.6 October 26, 2006 EL8176 Typical Performance Curves (Continued) 2.5 200 150 MAX VOS (µV) CURRENT (nA) 2 1.5 1 0.5 MEDIAN 100 MAX MEDIAN 50 0 0 MIN -0.5 -40 SO PACKAGE n = 12 n = 12 -20 0 20 40 60 80 100 -50 -40 120 MIN -20 0 TEMPERATURE (°C) FIGURE 22. INPUT OFFSET CURRENT vs TEMPERATURE VS = ±1.2V 200 400 80 100 120 n = 12 SOT-23 PACKAGE MAX 200 MAX VOS (µV) VOS (µV) 50 60 300 150 100 40 FIGURE 23. INPUT OFFSET VOLTAGE vs TEMPERATURE VS = ±2.5V SO PACKAGE n = 12 20 TEMPERATURE (°C) MEDIAN 100 MEDIAN 0 0 -50 -40 -100 MIN -20 0 20 40 60 80 100 -200 -40 120 MIN -20 0 TEMPERATURE (°C) FIGURE 24. INPUT OFFSET VOLTAGE vs TEMPERATURE VS = ±1.2V 200 n = 12 80 100 120 n = 12 120 MAX CMRR (dB) VOS (µV) 60 125 SOT-23 PACKAGE 50 0 -50 40 FIGURE 25. INPUT OFFSET VOLTAGE vs TEMPERATURE VS = ±2.5V 150 100 20 TEMPERATURE (°C) MEDIAN MAX 115 110 MEDIAN 105 -100 100 -150 MIN -200 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 26. INPUT OFFSET VOLTAGE vs TEMPERATURE VS = ±1.2V 7 95 -40 MIN -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 27. CMRR vs TEMPERATURE VCM = +2.5V TO -2.5V FN7436.6 October 26, 2006 EL8176 Typical Performance Curves 4.91 n = 12 135 4.90 130 4.89 MAX 120 115 MAX MEDIAN MEDIAN 4.87 4.86 110 4.85 105 4.84 MIN 4.83 100 95 -40 n = 12 4.88 125 VOUT (V) PSRR (dB) 140 (Continued) MIN -20 0 20 40 60 80 100 4.82 -40 120 -20 0 20 TEMPERATURE (°C) FIGURE 28. PSRR vs TEMPERATURE VS = ±1.2V TO ±2.5V 240 40 60 80 100 120 TEMPERATURE (°C) FIGURE 29. POSITIVE VOUT vs TEMPERATURE RL = 1k VS = ±2.5V 4.9982 n = 12 n = 12 4.9980 220 MAX 4.9978 200 160 VOUT (V) VOUT (mV) 4.9976 180 MAX 140 MEDIAN MEDIAN 4.9974 4.9972 4.9970 MIN 4.9968 120 80 -40 4.9966 MIN 100 -20 0 4.9964 20 40 60 80 100 120 4.9962 -40 -20 0 FIGURE 30. NEGATIVE VOUT vs TEMPERATURE RL = 1k VS = ±2.5V 40 60 80 100 120 FIGURE 31. POSITIVE VOUT vs TEMPERATURE RL = 100k VS = ±2.5V 0.23 5.5 n = 12 n = 12 0.21 SLEW RATE (V/µs) 5.0 VOUT (mV) 20 TEMPERATURE (°C) TEMPERATURE (°C) 4.5 MAX 4.0 3.5 MEDIAN 3.0 0.19 MAX 0.17 MEDIAN 0.15 0.13 MIN 0.11 0 0.09 -40 MIN 2.5 -40 -20 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 32. NEGATIVE VOUT vs TEMPERATURE RL = 100k VS = ±2.5V 8 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 33. +SLEW RATE vs TEMPERATURE VS = ±2.5V INPUT = ±0.75V, AV = 2 FN7436.6 October 26, 2006 EL8176 Typical Performance Curves (Continued) 0.17 n = 12 900 MAX n = 12 SOT-23 800 0.15 700 MEDIAN 0.14 AVOL (V/mV) CURRENT (pA) 0.16 0.13 MIN 0.12 MAX 600 MEDIAN 500 400 MIN 300 200 0.11 0.10 -40 100 -20 0 20 40 60 80 100 120 0 -40 TEMPERATURE (°C) -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 34. -SLEW RATE vs TEMPERATURE VS = ±2.5V INPUT = ±0.75V, AV = 2 FIGURE 35. AVOL, RL = 100k VO @+2V/-2V @VS ±2.5V OUTPUT OUTPUT ENABLE INPUT ENABLE INPUT FIGURE 36. ENABLE DELAY TIME JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.7 SO T2 θJ 3-6 A =2 30 °C /W 0.4 0.2 0.5 8 /W SO 0 ° C 6 =1 435mW 0.6 625mW A A 8 /W S O 0° C 1 =1 0.6 JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD θJ POWER DISSIPATION (W) 909mW 0.8 θJ POWER DISSIPATION (W) 1 FIGURE 37. DISABLE DELAY TIME 0.4 391mW θ 0.3 SO JA = 0.2 25 T2 36 6° C/ W 0.1 0 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 38. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 9 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 39. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FN7436.6 October 26, 2006 EL8176 Applications Information Introduction The EL8176 is a rail-to-rail input and output micro-power precision single supply operational amplifier with an enable feature. The device achieves rail-to-rail input and output operation and eliminates the concerns introduced by a conventional rail-to-rail I/O operational amplifier as discussed below. Rail-to-Rail Input The input common-mode voltage range of the EL8176 goes from negative supply to positive supply without introducing offset errors or degrading performance associated with a conventional rail-to-rail input operational amplifier. Many rail-to-rail input stages use two differential input pairs, a long-tail PNP (or PFET) and an NPN (or NFET). Severe penalties have to be paid for this circuit topology. As the input signal moves from one supply rail to another, the operational amplifier switches from one input pair to the other causing drastic changes in input offset voltage and an undesired change in magnitude and polarity of input offset current. The EL8176 achieves input rail-to-rail without sacrificing important precision specifications and without degrading distortion performance. The EL8176's input offset voltage exhibits a smooth behavior throughout the entire common-mode input range. The input bias current versus the common-mode voltage range for the EL8176 gives us an undistorted behavior from typically 10mV above the negative rail all the way up to the positive rail. 10 Input Bias Current Compensation The input bias currents as low as 500pA are achieved while maintaining an excellent bandwidth for a micro-power operational amplifier. Inside the EL8176 is an input bias canceling circuit. The input stage transistors are still biased with an adequate current for speed but the canceling circuit sinks most of the base current, leaving a small fraction as input bias current. The input bias current compensation/cancellation is stable from -40°C to +125°C and operates from typically 10mV to the positive supply rail. Rail-to-Rail Output A pair of complementary MOSFET devices achieves rail-to-rail output swing. The NMOS sinks current to swing the output in the negative direction. The PMOS sources current to swing the output in the positive direction. The EL8176 with a 100kΩ load will swing to within 3mV of the supply rails. Enable/Disable Feature The EL8176 offers an EN pin. The active low EN pin disables the device when pulled up to at least 2.0V. When disabled, the output is in a high impedance state and the part consumes typically 3µA. When disabled, the high impedance output allows multiple parts to be MUXed together. When configured as a MUX, the outputs are tied together in parallel and a channel can be selected by pulling the EN pin to 0.8V or lower.The EN pin has an internal pull-down. If left open or floating, the EN pin will internally be pulled low, enabling the part by default. FN7436.6 October 26, 2006 EL8176 Proper Layout Maximizes Performance To achieve the maximum performance of the high input impedance and low offset voltage of the EL8176, care should be taken in the circuit board layout. The PC board surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. Surface coating of the circuit board will reduce surface moisture and provide a humidity barrier, reducing parasitic resistance on the board. The use of guard rings around the amplifier inputs will further reduce leakage currents. Figure 40 shows how the guard ring should be configured and Figure 41 shows the top view of how a surface mount layout can be arranged. The guard ring does not need to be a specific width, but it should form a continuous loop around both inputs. By setting the guard ring voltage equal to the voltage at the non-inverting input, parasitic capacitance is minimized as well. For further reduction of leakage currents, components can be mounted to the PC board using Teflon standoff insulators. V+ HIGH IMPEDANCE INPUT IN 3 6 EL8176 1 4 2 Typical Applications R4 100kΩ R3 10kΩ R2 K TYPE THERMOCOUPLE 10kΩ V+ + EL8176 V- 410µV/°C + 5V R1 100kΩ FIGURE 42. THERMOCOUPLE AMPLIFIER Thermocouples are the most popular temperature-sensing device because of their low cost, interchangeability, and ability to measure a wide range of temperatures. The EL8176 is used to convert the differential thermocouple voltage into single-ended signal with 10X gain. The EL8176's rail-to-rail input characteristic allows the thermocouple to be biased at ground and the converter to run from a single 5V supply. 5 FIGURE 40. FIGURE 41. 11 FN7436.6 October 26, 2006 EL8176 Small Outline Package Family (SO) A D h X 45° (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL “X” 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4° ±4° DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 SO16 (0.150”) SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference N 8 14 16 Rev. L 2/01 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 12 FN7436.6 October 26, 2006 EL8176 SOT-23 Package Family MDP0038 e1 D SOT-23 PACKAGE FAMILY A 6 N 4 E1 2 E 3 0.15 C D 1 2X 2 3 0.20 C 5 2X e 0.20 M C A-B D B b NX 0.15 C A-B 1 SOT23-5 SOT23-6 TOLERANCE A 1.45 1.45 MAX A1 0.10 0.10 ±0.05 A2 1.14 1.14 ±0.15 b 0.40 0.40 ±0.05 c 0.14 0.14 ±0.06 D 2.90 2.90 Basic E 2.80 2.80 Basic E1 1.60 1.60 Basic e 0.95 0.95 Basic e1 1.90 1.90 Basic L 0.45 0.45 ±0.10 L1 0.60 0.60 Reference N 5 6 Reference Rev. E 3/00 3 NOTES: D 2X SYMBOL 1. Plastic or metal protrusions of 0.25mm maximum per side are not included. C A2 SEATING PLANE 3. This dimension is measured at Datum Plane “H”. A1 0.10 C 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Index area - Pin #1 I.D. will be located within the indicated zone (SOT23-6 only). NX 6. SOT23-5 version has no center lead (shown as a dashed line). (L1) H A GAUGE PLANE c L 0.25 0° +3° -0° All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 13 FN7436.6 October 26, 2006