EL8178 ® Data Sheet March 29, 2007 Micropower Single Supply Rail-to-Rail Input-Output (RRIO) Precision Op Amp The EL8178 is a precision low power, operational amplifier. The device is optimized for single supply operation between 2.4V to 5V. This enables operation from one lithium cell or two Ni-Cd batteries. The input range includes both positive and negative rail. For power sensitive applications, the EL8178 has and EN pin that will shut the device down and reduce the supply current to 3µA typ. In the active state, the EL8178 draws minimal supply current (55μA) while meeting excellent DCaccuracy, noise, and output drive specifications. FN7504.5 Features • Typical 55μA supply current • 250μV max offset voltage • Typical 1pA input bias current • 266kHz gain-bandwidth product • Single supply operation between 2.4V to 5.0V • Rail-to-rail input and output • Ground sensing • Output sources and sinks 26mA load current • Pb-free plus anneal available (RoHS compliant) Ordering Information Applications PART NUMBER (Note) PART MARKING TAPE & REEL EL8178FWZ-T7 BBWA 7” (3k pcs) EL8178FWZ-T7A BBWA PACKAGE (Pb-free) PKG. DWG. # 6 Ld SOT-23 MDP0038 • Battery- or solar-powered systems • 4mA to 20mA current loops • Handheld consumer products 7” 6 Ld SOT-23 MDP0038 (250 pcs) • Medical devices EL8178FSZ 8178FSZ 97/Tube 8 Ld SO MDP0027 • Thermocouple amplifiers EL8178FSZ-T7 8178FSZ 7” (1k pcs) MDP0027 • Photodiode pre-amps 8 Ld SO • pH probe amplifiers NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pinouts EL8178 (6 LD SOT-23) TOP VIEW OUT 1 VS- 2 6 VS+ + - IN+ 3 5 EN 4 IN- EL8178 (8 LD SO) TOP VIEW NC 1 IN- 2 IN+ 3 VS- 4 1 8 EN + 7 VS+ 6 OUT 5 NC CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2004-2007. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. EL8178 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage (VS) and Pwr-up Ramp Rate . . . . . . . . 5.5V, 1V/μs Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V Current into IN+, IN-, and EN. . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Input Voltage . . . . . . . . . . . . . . . . . . . . . . . VS- - 0.5V to VS+ + 0.5V ESD Tolerance Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V Thermal Resistance θJA (°C/W) 6 Ld SOT Package . . . . . . . . . . . . . . . . . . . . . . . . . 230 8 Ld SO Package . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Ambient Operating Temperature Range . . . . . . . . -40°C to +125°C Storage Temperature Range . . . . . . . . . . . . . . . . . -65°C to +150°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . +125°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VOS VS+ = 5V, VS- = 0V, VCM = 2.5V, VO = 2.5V, TA = +25°C unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C DESCRIPTION TEST CONDITIONS Input Offset Voltage MIN TYP MAX UNIT -250 50 250 μV 450 μV -450 ΔV OS -----------------ΔTime Long Term Input Offset Voltage Stability ΔV OS ---------------ΔT Input Offset Drift vs Temperature IB Input Bias Current See Figures 18 and 19 -25 3 μV/Mo 1.1 μV/°C 1 -600 25 pA 600 pA Input Noise Voltage Peak-to-Peak f = 0.1Hz to 10Hz 2.8 μVP-P Input Noise Voltage Density fO = 1kHz 48 nV/√Hz iN Input Noise Current Density fO = 1kHz 0.15 pA/√Hz CMIR Input Voltage Range Guaranteed by CMRR test 0 CMRR Common-Mode Rejection Ratio VCM = 0V to 5V 80 eN 5 100 dB 75 PSRR Power Supply Rejection Ratio VS = 2.4V to 5V 80 dB 100 dB 80 AVOL VOUT Large Signal Voltage Gain Maximum Output Voltage Swing VO = 0.5V to 4.5V, RL = 100kΩ to (VS+ + VS-)/2 100 VOL; Output low, RL = 1kΩ to (VS+ + VS-)/2 SR dB 400 V/mV 3 10 mV 130 250 mV 350 mV VOH; Output high, RL = 100kΩ to (VS+ + VS-)/2 4.994 4.9975 V VOH; Output high, RL = 1kΩ to (VS+ + VS-)/2 4.750 4.875 V Slew Rate 4.7 0.10 V 0.15 0.07 GBWP Gain Bandwidth Product 2 V/mV 100 VOL; Output low, RL = 100kΩ to (VS+ + VS-)/2 V fO = 100kHz 266 0.19 V/μs 0.25 V/μs kHz FN7504.5 March 29, 2007 EL8178 Electrical Specifications PARAMETER IS(ON) VS+ = 5V, VS- = 0V, VCM = 2.5V, VO = 2.5V, TA = +25°C unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C (Continued) DESCRIPTION TEST CONDITIONS MIN TYP MAX UNIT 35 55 75 μA 85 μA 5 μA Supply Current, Enabled 30 IS(OFF) Supply Current, Disabled 3 ISC+ Short Circuit Output Sourcing Current RL = 10Ω to opposite supply 23 31 mA 18 ISC- Short Circuit Output Sinking Current RL = 10Ω to opposite supply mA 20 26 mA 15 Minimum Supply Voltage VS Guaranteed by PSRR 2.2 VINH EN Pin High Level VINL EN Pin Low Level IENH EN Pin Input Current VEN = 5V 0.25 IENL EN Pin Input Current VEN = 0V -0.5 2.4 V 2.4 V 2 Typical Performance Curves V 0.8 0.8 V 2.5 μA +0.5 μA VS = ±2.5V, TA = +25°C, Unless Otherwise Specified 1 80 RL ≥ 10kΩ VOUT = 0.2VP-P RL ≥ 10kΩ VOUT = 0.2VP-P GAIN = 1k 70 GAIN = 500 60 0 50 VS = ±1.25 GAIN (dB) GAIN (dB) mA -1 VS = ±2.5V GAIN = 200 40 GAIN = 100 GAIN = 10 30 GAIN = 5 20 10 -2 GAIN = 2 0 VS = ±1.0V -3 1k 10k -10 100k GAIN = 1 -20 1M 1 10 100 FREQUENCY (Hz) 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 1. UNITY GAIN FREQUENCY RESPONSE at VARIOUS SUPPLY VOLTAGES FIGURE 2. FREQUENCY RESPONSE at VARIOUS CLOSED LOOP GAINS 60 200 INPUT OFFSET VOLTAGE (μV) SUPPLY CURRENT (μA) 1k 50 40 30 20 10 0 2 2.5 3 3.5 4 4.5 5 5.5 SUPPLY VOLTAGE (V) FIGURE 3. SUPPLY CURRENT vs SUPPLY VOLTAGE 3 AV = -1 VCM = VDD/2 100 0 -100 -200 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 OUTPUT VOLTAGE (V) FIGURE 4. INPUT OFFSET VOLTAGE vs OUTPUT VOLTAGE FN7504.5 March 29, 2007 EL8178 250 100 150 80 0 60 45 50 -50 PHASE 90 40 20 -150 -250 -0.5 180 0 0.5 1.5 2.5 3.5 4.5 -20 10 5.5 10 90 0 80 -10 90 PHASE 135 30 20 180 GAIN ΔVCM = 1VP-P RL = 100kΩ AV = +1 -20 CMRR (dB) 60 PHASE SHIFT (°) -30 -40 -50 -60 -70 -80 0 -90 -10 10 100 1k 10k 100k -100 10 1M 100 FREQUENCY (Hz) 1k 100k FIGURE 8. CMRR vs FREQUENCY 100 1000 10 VOLTAGE NOISE (nV/√Hz) ΔVS = 1VP-P 0 RL = 100kΩ -10 AV = +1 -20 -30 -PSRR -40 -50 +PSRR -60 1M FREQUENCY (Hz) FIGURE 7. OPEN LOOP GAIN AND PHASE vs FREQUENCY (RL = 100kΩ) -70 -80 10 100 VOLTAGE 1 10 CURRENT -90 -100 10 10k CURRENT NOISE (pA/√Hz) GAIN (dB) 70 10 1M FIGURE 6. OPEN LOOP GAIN AND PHASE vs FREQUENCY (RL = 1kΩ) 100 40 100k 10k FREQUENCY (Hz) FIGURE 5. INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE 50 1k 100 COMMON-MODE INPUT VOLTAGE (V) PSRR (dB) 135 GAIN PHASE SHIFT (°) (Continued) VS = ±2.5V, TA = +25°C, Unless Otherwise Specified (Continued) GAIN (dB) NORMALIZED INPUT OFFSET VOLTAGE (μV) Typical Performance Curves 100 1k 10k 100k FREQUENCY (Hz) FIGURE 9. PSRR vs FREQUENCY 4 1M 1 1 10 100 1k 10k 0.1 100k FREQUENCY (Hz) FIGURE 10. INPUT VOLTAGE AND CURRENT NOISE vs FREQUENCY FN7504.5 March 29, 2007 EL8178 Typical Performance Curves (Continued) VS = ±2.5V, TA = +25°C, Unless Otherwise Specified (Continued) 20 10 VOS DRIFT (µV) VOLTAGE NOISE (500nV/DIV) 15 5 0 -5 2.8μVP-P -10 -15 0 500 TIME (1s/DIV) FIGURE 11. 0.1Hz TO 10Hz INPUT VOLTAGE NOISE 1000 TIME (HOURS) 1500 1800 FIGURE 12. IVOS DRIFT (SOT-23 PACKAGE) vs TIME 75 18 n = 1500 MAX 70 13 CURRENT (mA) VOS DRIFT (µV) 65 8 3 -2 MEDIAN 60 55 50 MIN 45 -7 -12 40 0 500 1000 35 -40 1500 -20 0 TIME (HOURS) 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 13. IVOS DRIFT (SOIC PACKAGE) vs TIME FIGURE 14. ENABLED SUPPLY CURRENT vs TEMPERATURE, VS = ±2.5V 5.0 400 n = 1500 n = 1500 MAX 300 MAX 4.5 VIO (µV) CURRENT (mA) 200 4.0 3.5 0 MEDIAN -100 3.0 MEDIAN -200 MIN 2.5 -300 MIN 2.0 -40 100 -20 0 20 40 60 80 TEMPERATURE (°C) FIGURE 15. DISABLED SUPPLY CURRENT vs TEMPERATURE, VS = ±2.5V 5 100 120 -400 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 16. VOS vs TEMPERATURE, VS = ±2.5V FN7504.5 March 29, 2007 EL8178 Typical Performance Curves (Continued) VS = ±2.5V, TA = +25°C, Unless Otherwise Specified (Continued) 800 600 160 n = 1500 MAX MAX 120 200 IBIAS + (pA) 400 VIO (μV) n = 1500 140 MEDIAN 0 -200 -400 100 80 60 MEDIAN 40 20 MIN MIN -600 0 -800 -40 -20 0 20 40 60 80 100 -20 -40 120 -20 0 TEMPERATURE (°C) 80 100 120 FIGURE 18. IBIAS+ vs TEMPERATURE, VS = ±2.5V 125 MAX n = 1500 120 MAX 115 MEDIAN CMRR (dB) IBIAS -(pA) 60 130 110 105 MEDIAN 100 95 90 20 40 60 80 TEMPERATURE (°C) 100 MIN 85 MIN 80 -40 120 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 19. IBIAS- vs TEMPERATURE, VS = ±2.5V FIGURE 20. CMRR vs TEMPERATURE, V+ = ±2.5V, ±1.5V 130 125 40 TEMPERATURE (°C) FIGURE 17. VOS vs TEMPERATURE, VS = ±1.2V 250 n = 1500 230 210 190 170 150 130 110 90 70 50 30 10 -10 -40 -20 0 20 4.90 n = 1500 MAX n = 1500 4.89 MAX 115 4.88 VOUT (V) PSRR (dB) 120 110 MEDIAN 105 100 4.87 MEDIAN 4.86 95 MIN 4.85 90 85 -40 MIN -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 21. PSRR vs TEMPERATURE ±1.5V TO ±2.5V 6 4.84 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 22. VOUT HIGH vs TEMPERATURE, VS = ±2.5V, RL = 1k FN7504.5 March 29, 2007 EL8178 Typical Performance Curves (Continued) VS = ±2.5V, TA = +25°C, Unless Otherwise Specified (Continued) 4.9984 190 n = 1500 4.9982 4.9980 MAX 170 VOUT (mV) MAX 4.9978 VOUT (V) n = 1500 180 4.9976 4.9974 MEDIAN 4.9972 160 MEDIAN 150 140 MIN 130 4.9970 120 4.9968 MIN 4.9966 110 4.9964 100 -40 -20 0 20 40 60 80 100 -40 120 -20 0 FIGURE 23. VOUT HIGH vs TEMPERATURE, VS = ±2.5V, RL = 100k 40 60 80 100 120 FIGURE 24. VOUT LOW vs TEMPERATURE, VS = ±2.5V, RL = 1k 510 5.0 4.8 20 TEMPERATURE (°C) TEMPERATURE (°C) n = 1500 n = 1500 MAX 460 MAX 4.6 410 MEDIAN AVOL (V/mV) VOUT (mV) 4.4 4.2 4.0 MIN 3.8 360 MEDIAN 310 260 3.6 3.4 MIN 210 3.2 160 3.0 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 25. VOUT LOW vs TEMPERATURE, VS = ±2.5V, RL = 100k 7 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 26. AVOL vs TEMPERATURE, RL = 100k, VO = ±2V @ VS = ±2.5V FN7504.5 March 29, 2007 EL8178 Pin Descriptions SO PIN NUMBER SOT-23 PIN NUMBER PIN NAME 1 EQUIVALENT CIRCUIT NC DESCRIPTION No internal connection 2 4 IN- Circuit 1 Amplifier’s inverting input 3 3 IN+ Circuit 1 Amplifier’s non-inverting input 4 2 VS- Circuit 4 Negative power supply 5 NC No internal connection 6 1 OUT Circuit 3 Amplifier’s output 7 6 VS+ Circuit 4 Positive power supply 8 5 EN Circuit 2 Amplifier’s enable pin with internal pull-down; Logic “1” selects the disabled state; Logic “0” selects the enabled state. VS+ VS+ IN- IN+ CAPACITIVELY COUPLED ESD CLAMP VS- VS- CIRCUIT 2 Application Information Introduction The EL8178 is a rail-to-rail input and output (RRIO), micro-power, precision, single supply op amp with an enable feature. This amplifier is designed to operate from single supply (2.4V to 5.0V) or dual supply (±1.2V to ±2.5V) while drawing only 55μA of supply current.The device achieves rail-to-rail input and output operation while eliminating the drawbacks of many conventional RRIO op amps. Rail-to-Rail Input The PFET input stage of the EL8178 has an input common-mode voltage range that includes the negative and positive supplies without introducing offset errors or degrading performance like some existing rail-to-rail input op amps. Many rail-to-rail input stages use two differential input pairs: a long-tail PNP (or PFET) and an NPN (or NFET). Severe penalties result from using this topology. As the input signal moves from one supply rail to the other, the op amp switches from one input pair to the other causing changes in input offset voltage and an undesired change in the input offset current’s magnitude and polarity. The EL8178 achieves rail-to-rail input performance without sacrificing important precision specifications and without degrading distortion performance. The EL8178's input offset voltage exhibits a smooth behavior throughout the entire common-mode input range. 8 VS+ OUT EN VS- CIRCUIT 1 VS+ VSCIRCUIT 3 CIRCUIT 4 Rail-to-Rail Output A pair of complementary MOSFET devices achieves rail-to-rail output swing. The NMOS sinks current to swing the output in the negative direction, while the PMOS sources current to swing the output in the positive direction. The EL8178 with a 100kΩ load swings to within 3mV of the supply rails. Results of Over-Driving the Output Caution should be used when over-driving the output for long periods of time. Over-driving the output can occur in three ways: 1. The input voltage times the gain of the amplifier exceeds the supply voltage by a large value. 2. The output current required is higher than the output stage can deliver. 3. Operating the device in Slew Rate Limit. These conditions can result in a shift in the Input Offset Voltage (VOS) as much as 1µV/hr of exposer under these condition. Enable/Disable Feature The EL8178 features an active low EN pin that when pulled up to at least 2V, disables the output and drops the ICC to a 3µA. The EN pin has an internal pull down, so an undriven pin pulls to the negative rail, thereby enabling the op amp by default. For applications where the EN pin is not being used, it is recommended that the EN pin be permanently tie to ground. The high impedance output during disable allows for connecting multiple EL8178s together to implement a Mux Amp. The outputs are connected together and activating the appropriate EN pin selects the desired channel. If utilizing FN7504.5 March 29, 2007 EL8178 non-unity gain op amp configurations, then the loading effects of the disabled amplifiers’ feedback networks must be considered when evaluating the active amplifier’s performance in Mux Amp configurations. Note that feed through from the IN+ to IN- pins occurs on any Mux Amp disabled channel where the input differential voltage exceeds 0.5V (e.g., active channel VOUT = 1V, while disabled channel VIN = GND), so the mux implementation is best suited for small signal applications. In any application where two or more amplifier outputs are muxed, use series IN+ resistors, or large value RFs in each amplifier to keep the feed through current low enough to minimize the impact on the active channel. See “Usage Implications” on page 9 for more details. IN+ and IN- Input Protection In addition to ESD protection diodes to each supply rail, the EL8178 has additional back-to-back protection diodes across the differential input terminals (see “Circuit 1” diagram on page 8). If the magnitude of the differential input voltage exceeds the diode’s VF, then one of these diodes will conduct. For elevated temperatures, the leakage of the protection diodes (Circuit 1 pin description table) increases, resulting in the increase in Ibias as seen in Figures 18 and 19. Usage Implications EN Input Protection The EN input has internal ESD protection diodes to both the positive and negative supply rails, limiting the input voltage range to within one diode beyond the supply rails (see “Circuit 2” diagram on page 8). If the input voltage is expected to exceed VS+ or VS-, then an external series resistor should be added to limit the current to 5mA. Output Current Limiting The EL8178 has no internal current-limiting circuitry. If the output is shorted, it is possible to exceed the “Absolute Maximum Rating” for “operating junction temperature”, potentially resulting in the destruction of the device. Power Dissipation It is possible to exceed the +150°C maximum junction temperature (TJMAX) under certain load and power-supply conditions. It is therefore important to calculate TJMAX for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related as follows: T JMAX = T MAX + ( θ JA xPDMAX ) (EQ. 1) where PDMAX is calculated using: If the input differential voltage is expected to exceed 0.5V, an external current limiting resistor must be used to ensure the input current never exceeds 5mA. For noninverting unity gain applications the current limiting can be via a series IN+ resistor, or via a feedback resistor of appropriate value. For other gain configurations, the series IN+ resistor is the best choice, unless the feedback (RF) and gain setting (RG) resistors are both sufficiently large to limit the input current to 5mA. V OUTMAX PD MAX = V S × I SMAX + ( V S - V OUTMAX ) × ---------------------------R L (EQ. 2) where: • TMAX = Maximum ambient temperature • θJA = Thermal resistance of the package Large differential input voltages can arise from several sources: • PDMAX = Maximum power dissipation of the amplifier 1) During open loop (comparator) operation. The IN+ and INinput voltages don’t track. • IMAX = Maximum supply current of the amplifier 2) When the amplifier is disabled but an input signal is still present. An RL or RG to GND keeps the IN- at GND, while the varying IN+ signal creates a differential voltage. Mux Amp applications are similar, except that the active channel VOUT determines the voltage on the IN- terminal. 3) When the slew rate of the input pulse is considerably faster than the op amp’s slew rate. If the VOUT can’t keep up with the IN+ signal, a differential voltage results, and visible distortion occurs on the input and output signals. To avoid this issue, keep the input slew rate below 0.2V/μs, or use appropriate current limiting resistors. Large (>2V) differential input voltages can also cause an increase in disabled ICC. 9 • VS = Supply voltage • VOUTMAX = Maximum output voltage swing of the application • RL = Load resistance Proper Layout Maximizes Precision To achieve the optimum levels of high input impedance (i.e., low input currents) and low offset voltage, care should be taken in the circuit board layout. The PC board surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. Surface coating of the circuit board will reduce surface moisture and provide a humidity barrier, reducing parasitic resistance on the board. When input leakage current is a paramount concern, the use of guard rings around the amplifier inputs will further reduce leakage currents. Figure 27 shows a guard ring example for a unity gain amplifier that uses the low impedance amplifier output at the same voltage as the high impedance input to eliminate surface leakage. The guard ring does not need to be a FN7504.5 March 29, 2007 EL8178 specific width, but it should form a continuous loop around both inputs. For further reduction of leakage currents, mount components to the PC board using Teflon standoffs. V+ HIGH IMPEDANCE INPUT a low-cost coax cable. The EL8178 PMOS high impedance input senses the pH probe output signal and buffers it to drive the coax cable. Its rail-to-rail input nature also eliminates the need for a bias resistor network required by other amplifiers in the same application. IN R4 100kΩ FIGURE 27. GUARD RING EXAMPLE FOR UNITY GAIN AMPLIFIER Typical Applications GENERAL PURPOSE COMBINATION pH PROBE R3 10kΩ R2 K TYPE THERMOCOUPLE 10kΩ VS+ + EL8178 VS- 410μV/°C + 5V R1 VS+ + EL8178 VS- 100kΩ FIGURE 29. THERMOCOUPLE AMPLIFIER + 3V COAX FIGURE 28. pH PROBE AMPLIFIER A general-purpose combination pH probe has extremely high output impedance typically in the range of 10GΩ to 12GΩ. Low loss and expensive Teflon cables are often used to connect the pH probe to the meter electronics. Figure 28 details a low-cost alternative solution using the EL8178 and 10 Thermocouples are the most popular temperature sensing devices because of their low cost, interchangeability, and ability to measure a wide range of temperatures. In Figure 29, the EL8178 converts the differential thermocouple voltage into single-ended signal with 10X gain. The EL8178's rail-to-rail input characteristic allows the thermocouple to be biased at ground and permits the op amp to operate from a single 5V supply. FN7504.5 March 29, 2007 EL8178 Small Outline Package Family (SO) A D h X 45° (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL “X” 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4° ±4° DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL SO-14 SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference - N SO-8 SO16 (0.150”) 8 14 16 Rev. M 2/07 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 11 FN7504.5 March 29, 2007 EL8178 SOT-23 Package Family MDP0038 e1 D SOT-23 PACKAGE FAMILY A MILLIMETERS 6 N SYMBOL 4 E1 2 E 3 0.15 C D 1 2X 2 3 0.20 C 5 2X e 0.20 M C A-B D B b NX 0.15 C A-B 1 3 SOT23-5 SOT23-6 TOLERANCE A 1.45 1.45 MAX A1 0.10 0.10 ±0.05 A2 1.14 1.14 ±0.15 b 0.40 0.40 ±0.05 c 0.14 0.14 ±0.06 D 2.90 2.90 Basic E 2.80 2.80 Basic E1 1.60 1.60 Basic e 0.95 0.95 Basic e1 1.90 1.90 Basic L 0.45 0.45 ±0.10 L1 0.60 0.60 Reference N 5 6 Reference D 2X Rev. F 2/07 NOTES: C A2 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. SEATING PLANE A1 0.10 C 1. Plastic or metal protrusions of 0.25mm maximum per side are not included. 3. This dimension is measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. NX 5. Index area - Pin #1 I.D. will be located within the indicated zone (SOT23-6 only). (L1) 6. SOT23-5 version has no center lead (shown as a dashed line). H A GAUGE PLANE c L 0.25 0° +3° -0° All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 FN7504.5 March 29, 2007