HMU16/883 16 x 16-Bit CMOS Parallel Multiplier April 1997 Features Description • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. The HMU16/883 is a high speed, low power CMOS 16 x 16-bit parallel multiplier ideal for fast, real time digital signal processing applications. The 16-bit X and Y operands may be independently specified as either two’s complement or unsigned magnitude format, thereby, allowing mixed mode multiplication operations. • 16 x 16-Bit Parallel Multiplier with Full 32-Bit Product • High-Speed (45ns) Clocked Multiply Time Additional inputs are provided to accommodate format adjustment and rounding of the 32-bit product. The Format Adjust control allows the user to select a 31-bit product with the sign bit replicated in the LSP. The round control provides for rounding the most significant portion of the result by adding one to the most significant bit of the LSP. • Low Power CMOS Operation - ICCSB = 500µA Maximum - ICCOP = 7.0mA Maximum at 1MHz • HMU16/883 is Compatible with the AM29516, LMU16, IDT7216, and the CY7C516 Two 16-bit Output Registers (MSP and LSP) are provided to hold the most and least significant portions of the result, respectively. These registers may be made transparent for asynchronous operation through the use of the Feedthrough Control (FT). The two halves of the product may be routed to a single 16-bit three-state output port via the output multiplexer control, and in addition, the LSP is connected to the Yinput port through a separate three-state buffer. • Supports Two’s Complement, Unsigned Magnitude and Mixed Mode Multiplication • TTL Compatible Inputs/Outputs • Three-State Outputs Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. NO. HMU16GM-45/883 HMU16GM-60/883 -55 to 125 68 Ld CPGA N68.95 -55 to 125 68 Ld CPGA N68.95 The HMU16/883 utilizes independent clock signals (CLKX, CLKY, CLKL, CLKM) to latch the input operands and output Product Registers. This configuration maximizes throughput and simplifies bus interfacing. All outputs of the HMU16/883 also offer three-state control for multiplexing onto multi-use system busses. Functional Diagram X0-15 TCX REGISTER TCY RND REGISTER Y0-15/P0-15 REGISTER OEL CLKX CLKY MULTIPLIER ARRAY FA FT FORMAT ADJUST MSP REGISTER LSP REGISTER CLKM CLKL MSPSEL MULTIPLEXER OEP P16-31/P0-15 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 3-29 File Number 2804.2 HMU16/883 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input or Output Voltage Applied . . . . . . . . GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Operating Conditions Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) CPGA Package . . . . . . . . . . . . . . . . . . 42.69 10.0 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4500 Gates CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. TABLE 1. HMU16/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested GROUP A SUBGROUPS TEMPERATURE (oC) MIN MAX UNITS VCC = 5.5V 1, 2, 3 -55 ≤ TA ≤ 125 2.2 - V VIL VCC = 4.5V 1, 2, 3 -55 ≤ TA ≤ 125 - 0.8 V Output HIGH Voltage VOH IOH = -400µA VCC = 4.5V (Note 2) 1, 2, 3 -55 ≤ TA ≤ 125 2.6 - V Output LOW Voltage VOL IOL = +4.0mA VCC = 4.5V (Note 2) 1, 2, 3 -55 ≤ TA ≤ 125 - 0.4 V PARAMETER SYMBOL Logical One Input Voltage VIH Logical Zero Input Voltage TEST CONDITIONS Input Leakage Current II VIN = VCC or GND VCC = 5.5V 1, 2, 3 -55 ≤ TA ≤ 125 -10 +10 mA Output or I/O Leakage Current IO VOUT = VCC or GND VCC = 5.5V 1, 2, 3 -55 ≤ TA ≤ 125 -10 +10 mA Standby Power Supply Current ICCSB VIN = VCC or GND, VCC = 5.5V, Outputs Open 1, 2, 3 -55 ≤ TA ≤ 125 - 500 mA Operating Power Supply Current ICCOP f = 1.0MHz, VIN = VCC or GND VCC = 5.5V (Note 3) 1, 2, 3 -55 ≤ TA ≤ 125 - 7.0 mA 7, 8 -55 ≤ TA ≤ 125 - - Functional Test FT (Note 4) NOTES: 2. Interchanging of force and sense conditions is permitted. 3. Operating supply current is proportional to frequency, typical rating is 5mA/MHz. 4. Tested as follows: f = 1MHz, VIH (clock inputs) = 3.0, VIH (all other inputs) = 2.6, VIL = 0.4, VOH ≥ 1.5V, and VOL ≤ 1.5V. 3-30 HMU16/883 TABLE 2. HMU16/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested (NOTE 5) TEST CONDITIONS -45 -60 GROUP A SUBGROUPS TEMPERATURE (oC) MIN MAX MIN MAX UNITS tMUC 9, 10, 11 -55 ≤ TA ≤ 125 - 70 - 90 ns Clocked Multiply Time tMC 9, 10, 11 -55 ≤ TA ≤ 125 - 45 - 60 ns X, Y, RND Setup Time tS 9, 10, 11 -55 ≤ TA ≤ 125 18 - 20 - ns Clock HIGH Pulse Width tPWH 9, 10, 11 -55 ≤ TA ≤ 125 15 - 20 - ns Clock LOW Pulse Width tPWL 9, 10, 11 -55 ≤ TA ≤ 125 15 - 20 - ns tPDSEL 9, 10, 11 -55 ≤ TA ≤ 125 - 25 - 30 ns Output Clock to P tPDP 9, 10, 11 -55 ≤ TA ≤ 125 - 25 - 30 ns Output Clock to Y tPDY 9, 10, 11 -55 ≤ TA ≤ 125 - 25 - 30 ns Three-State Enable Time tENA (Note 6) 9, 10, 11 -55 ≤ TA ≤ 125 - 25 - 30 ns Clock Low Hold Time CLKXY Relative to CLKML tHCL (Note 7) 9, 10, 11 -55 ≤ TA ≤ 125 0 - 0 - ns PARAMETER Unclocked Multiply Time MSPSEL to Product Out SYMBOL NOTES: 5. AC Testing as follows: VCC = 4.5V and 5.5V. Input levels 0V and 3.0V; timing reference levels = 1.5V; output load per test load circuit, with V1 = 4V, R1 = 500Ω and CL = 40pF. 6. Transition is measured at ±200mV from steady state voltage; output loading per test load circuit with V1 = 1.5V, R1 = 500Ω and CL = 40pF. 7. To ensure the correct product is entered in the Output Registers; new data may not be entered into the Input Registers before the Output Registers have been clocked. 3-31 HMU16/883 TABLE 3. HMU16/883 ELECTRICAL PERFORMANCE SPECIFICATIONS -45 PARAMETER Input Capacitance Output Capacitance SYMBOL CONDITIONS NOTES TEMPERATURE (oC) MIN MAX MIN MAX UNITS CIN VCC = Open, f = 1MHz All Measurements are referenced to device GND. 1 TA = 25 - 15 - 15 pF 1 TA = 25 - 10 - 10 pF 1 TA = 25 - 10 - 10 pF COUT I/O Capacitance -60 CI/O X, Y, RND Hold Time tH 1, 2 -55 ≤ TA ≤ 125 3 - 3 - ns Three-State Disable Time tDIS 1, 2, 3 -55 ≤ TA ≤ 125 - 25 - 30 ns Output Rise Time tr From 0.8V to 2.0V 1, 2, 4 -55 ≤ TA ≤ 125 - 10 - 10 ns Output Fall Time tf From 2.0V to 0.8V 1, 2, 4 -55 ≤ TA ≤ 125 - 10 - 10 ns NOTES: 8. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design and after major process and/or design changes. 9. Guaranteed, but not 100% tested. 10. Transition is measured at 1200mV from steady state voltage; output loading per test load circuit with V1 = 1.5V, R1 = 500Ω and CL = 40pF. 11. Loading is as specified in the test load circuit, with V1 = 2.4V, R1 = 500Ω and CL = 40pF. TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS METHOD SUBGROUPS Initial Test 100%/5004 - Interim Test 100%/5004 - PDA 100% 1 Final Test 100% 2, 3, 8A, 8B, 10, 11 - 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Samples/5005 1, 7, 9 Group A Groups C and D 3-32 HMU16/883 Burn-In Circuit 68 LEAD CPGA TOP VIEW 11 X13 X15 RND TCY VCC GND FT OEP X14 CLKX TCX VCC GND MSP SEL FA CLKM N/C 10 X11 X12 9 X9 X10 P30/ P14 P31/ P15 8 X7 X8 P28/ P12 P29/ P13 7 X5 X6 P26/ P10 P27/ P11 6 X3 X4 P24/P8 P25/P9 5 X1 X2 P22/P6 P23/P7 4 OEL X0 P20/P4 P21/P5 3 CLKY CLKL P18/P2 P19/P3 2 N/C Y0/P0 Y2/P2 Y4/P4 Y6/P6 Y8/P8 Y10/ P10 Y12/ P12 Y14/ P14 P16/P0 P17/P1 Y1/P1 Y3/P3 Y5/P5 Y7/P7 Y9/P9 Y11/ P11 Y13/ P13 Y15/ P15 N/C G H J K 1 A CPGA PIN N/C PIN NAME B C D E F CPGA PIN BURN-IN SIGNAL L PIN NAME BURN-IN SIGNAL B6 X4 F6 G1 Y11/P11 F13 A6 X3 F5 H2 Y12/P12 F14 B5 X2 F4 H1 Y13/P13 F15 A5 X1 F3 J2 Y14/P14 F4 B4 X0 F2 J1 Y15/P15 F5 A4 OEL VCC K2 P0/P16 VCC/2 B3 CLKL F0 L2 P1/P17 VCC/2 A3 CLKY F0 K3 P2/P18 VCC/2 B2 Y0/P0 F2 L3 P3/P19 VCC/2 B1 Y1/P1 F3 K4 P4/P20 VCC/2 C2 Y2/P2 F4 L4 P5/P21 VCC/2 C1 Y3/P3 F5 K5 P6/P22 VCC/2 D2 Y4/P4 F6 L5 P7/P23 VCC/2 D1 Y5/P5 F7 K6 P8/P24 VCC/2 E2 Y6/P6 F8 L6 P9/P25 VCC/2 E1 Y7/P7 F9 K7 P10/P26 VCC/2 F2 Y8/P8 F10 L7 P11/P27 VCC/2 F1 Y9/P9 F11 K8 P12/P28 VCC/2 G2 Y10/P10 F12 L8 P13/P29 VCC/2 3-33 HMU16/883 CPGA PIN PIN NAME BURN-IN SIGNAL K9 P14/P30 VCC/2 L9 P15/P31 VCC/2 K10 CLKM F0 K11 OEP F1 J10 FA F14 J11 FT F15 H10 MSPSEL F14 H11 GND GND G10 GND GND G11 VCC VCC F10 VCC VCC F11 TCY F15 E10 TCX F15 E11 RND F1 D10 CLKX F0 D11 X15 F3 C10 X14 F2 C11 X13 F15 B10 X12 F14 A10 X11 F13 B9 X10 F12 A9 X9 F11 B8 X8 F10 A8 X7 F9 B7 X6 F8 A7 X5 F7 A2 N.C. NONE K1 N.C. NONE L10 N.C. NONE B11 N.C. NONE NOTES: 12. VCC = 5.5V +0.5V/-0.0V with 0.1µF decoupling capacitor to GND. 13. F0 = 100kHz, F1 = F0/2, F2 = F1/2, . . . . . . . . . . . . . . . . . . . . . 14. VlH = VCC - 1V ± 0.5V (Min), VIL = 0.8V (Max). 15. 47kΩ Load Resistors used on all pins except VCC and GND (PinGrid identifiers F10, G10, G11 and H11). 3-34 HMU16/883 Die Characteristics DIE DIMENSIONS: 179 x 169 x 19 ± 1mils METALLIZATION: Type: Si - Al or Si-Al-Cu Thickness: 8kÅ GLASSIVATION: Type: Nitrox Thickness: 10kÅ WORST CASE CURRENT DENSITY: 1.2 x 105A/cm2 Metallization Mask Layout HMU16/883 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 3-35