RENESAS M32C83T

REJ09B0034-0131
16/32
M32C/83 Group (M32C/83, M32C/83T)
Hardware Manual
RENESAS 16/32-BIT SINGLE-CHIP MICROCOMPUTER
M16C FAMILY / M32C/80 SERIES
Before using this material, please visit our website to verify that this is the most
current document available.
Rev. 1.31
Revision Date: Jan. 31, 2006
www.renesas.com
Keep safety first in your circuit designs!
1.
Renesas Technology Corp. puts the maximum effort into making semiconductor products
better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.
2.
3.
4.
5.
6.
7.
8.
These materials are intended as a reference to assist our customers in the selection of the
Renesas Technology Corp. product best suited to the customer's application; they do not
convey any license under any intellectual property rights, or any other rights, belonging to
Renesas Technology Corp. or a third party.
Renesas Technology Corp. assumes no responsibility for any damage, or infringement of
any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these
materials, and are subject to change by Renesas Technology Corp. without notice due to
product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other
loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://
www.renesas.com).
When using any or all of the information contained in these materials, including product
data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information
and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.
Renesas Technology Corp. semiconductors are not designed or manufactured for use in a
device or system that is used under circumstances in which human life is potentially at
stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology
Corp. product distributor when considering the use of a product contained herein for any
specific purposes, such as apparatus or systems for transportation, vehicular, medical,
aerospace, nuclear, or undersea repeater use.
The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials.
If these products or technologies are subject to the Japanese export control restrictions,
they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/
or the country of destination is prohibited.
Please contact Renesas Technology Corp. for further details on these materials or the
products contained therein.
How to Use This Manual
1. Introduction
This hardware manual provides detailed information on the M32C/83 Group (M32C/83, M32C/83T) microcomputers. Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers.
2. Register Diagram
The symbols, and descriptions, used for bit function in each register are shown below.
XXX Register
b7
b6
b5
b4
b3
b2
*1
b1
b0
0 0
Symbol
XXX
Address
XXX
After Reset
0016
Bit Name
Bit Symbol
Function
RW
*2
b1 b0
XXX0
XXX bit
XXX1
(b2)
0 0: XXX
0 1: XXX
1 0: Do not set a value
1 1: XXX
RW
Nothing is assigned.
When write, set to "0". When read, its content is indeterminate.
Reserved bit
(b4 - b3)
Set to "0"
*3
WO
*4
XXX5
XXX bit
Function varies depending on mode
of operation
RW
RW
XXX6
XXX7
RW
XXX bit
0: XXX
1: XXX
RO
*1
Blank:Set to "0" or "1" according to the application
0:
Set to "0"
1:
Set to "1"
X:
Nothing is assigned
*2
RW:
RO:
WO:
–:
Read and write
Read only
Write only
Nothing is assigned
*3
• Reserved bit
Reserved bit. Set to specified value.
*4
• Nothing is assigned
Nothing is assigned to the bit concerned. As the bit may be use for future functions,
set to "0" when writing to this bit.
• Do not set a value
The operation is not guaranteed when a value is set.
• Function varies depending on mode of operation
Bit function varies depending on peripheral function mode.
Refer to respective register for each mode.
3. M16C Family Documents
The following documents were prepared for the M16C family. (1)
Document
Contents
Short Sheet
Data Sheet
Hardware Manual
Hardware overview
Hardware overview and electrical characteristics
Hardware specifications (pin assignments, memory maps, peripheral
specifications, electrical characteristics, timing charts)
Software Manual
Detailed description of assembly instructions and microcomputer performance of each instruction
Application Note
• Application examples of peripheral functions
• Sample programs
• Introduction to the basic functions in the M16C family
• Programming method with Assembly and C languages
RENESAS TECHNICAL UPDATE Preliminary report about the specification of a product, a document, etc.
NOTES :
1. Before using this material, please visit the our website to confirm that this is the most current document
available.
Table of Contents
Quick Reference by Address _____________________ B-1
1. Overview _____________________________________ 1
1.1
1.2
1.3
1.4
1.5
1.6
Applications ................................................................................................................ 1
Performance Overview .............................................................................................. 2
Block Diagram ............................................................................................................ 4
Product Information ................................................................................................... 5
Pin Assignment .......................................................................................................... 6
Pin Description ......................................................................................................... 14
2. Central Processing Unit (CPU) __________________ 18
2.1 General Registers .................................................................................................... 19
2.1.1 Data Registers (R0, R1, R2 and R3) ................................................................. 19
2.1.2 Address Registers (A0 and A1) ....................................................................... 19
2.1.3 Static Base Register (SB) ................................................................................. 19
2.1.4 Frame Base Register (FB) ................................................................................ 19
2.1.5 Program Counter (PC) ...................................................................................... 19
2.1.6 Interrupt Table Register (INTB) ........................................................................ 19
2.1.7 User Stack Pointer (USP), Interrupt Stack Pointer (ISP) ............................... 19
2.1.8 Flag Register (FLG) ........................................................................................... 19
2.2 High-Speed Interrupt Registers .............................................................................. 20
2.3 DMAC-Associated Registers ................................................................................... 20
3. Memory _____________________________________ 21
4. Special Function Registers (SFR)________________ 22
5. Reset _______________________________________ 44
5.1 Hardware Reset ........................................................................................................ 44
5.1.1 Reset on a Stable Supply Voltage ................................................................... 44
5.1.2 Power-on Reset ................................................................................................. 44
5.2 Software Reset ......................................................................................................... 46
5.3 Watchdog Timer Reset ............................................................................................ 46
5.4 Internal Space ........................................................................................................... 47
6. Processor Mode ______________________________ 48
6.1 Types of Processor Mode ........................................................................................ 48
6.1.1 Single-chip Mode .............................................................................................. 48
6.1.2 Memory Expansion Mode ................................................................................. 48
6.1.3 Microprocessor Mode ....................................................................................... 48
A-1
6.2 Setting Processor Mode .......................................................................................... 48
6.2.1 Applying VSS to CNVSS Pin ............................................................................ 48
6.2.2 Applying VCC to CNVSS Pin ............................................................................ 48
7. Bus................................................................................... 52
7.1 Bus Settings ............................................................................................................. 52
7.1.1 Selecting External Address Bus ...................................................................... 53
7.1.2 Selecting External Data Bus ............................................................................ 53
7.1.3 Selecting Separate/Multiplexed Bus ............................................................... 53
7.2 Bus Control ............................................................................................................... 55
7.2.1 Address Bus and Data Bus .............................................................................. 55
7.2.2 Chip-Select Signal ............................................................................................ 55
7.2.3 Read and Write Signals ..................................................................................... 57
7.2.4 Bus Timing ......................................................................................................... 58
7.2.5 ALE Signal ......................................................................................................... 62
_______
7.2.6 RDY Signal ......................................................................................................... 62
_________
7.2.7 HOLD Signal ...................................................................................................... 63
7.2.8 External Bus State when Accessing Internal Space...................................... 64
7.2.9 BCLK Output ..................................................................................................... 64
_______ __________ __________
_____
7.2.10 DRAM Control Signals (RAS, CASL, CASH and DW) .................................. 64
8. Clock Generation Circuit _______________________ 65
8.1 Types of Clock Generation Circuits........................................................................ 65
8.1.1 Main Clock ......................................................................................................... 74
8.1.2 Sub Clock .......................................................................................................... 75
8.1.3 On-chip Oscillator Clock .................................................................................. 76
8.1.4 PLL Clock .......................................................................................................... 77
8.2 CPU Clock and BCLK .............................................................................................. 79
8.3 Peripheral Function Clock ....................................................................................... 79
8.3.1 f1, f8, f32 and f2n ......................................................................................................................... 79
8.3.2 fAD .................................................................................................................................................... 79
8.3.3 fC32 .................................................................................................................................................. 80
8.4 Clock Output Function ............................................................................................ 80
8.5 Power Consumption Control .................................................................................. 80
8.5.1 Normal Operation Mode ................................................................................... 81
8.5.2 Wait Mode .......................................................................................................... 82
8.5.3 Stop Mode .......................................................................................................... 84
9. Protection ___________________________________ 88
A-2
10. Interrupts___________________________________ 89
10.1 Types of Interrupts ................................................................................................. 89
10.2 Software Interrupts ................................................................................................ 89
10.2.1 Undefined Instruction Interrupt ..................................................................... 89
10.2.2 Overflow Interrupt ........................................................................................... 89
10.2.3 BRK Interrupt .................................................................................................. 89
10.2.4 BRK2 Interrupt ................................................................................................ 90
10.2.5 INT Instruction Interrupt ................................................................................. 90
10.3 Hardware Interrupts ............................................................................................... 90
10.3.1 Special Interrupts ............................................................................................ 90
10.3.2 Peripheral Function Interrupt ........................................................................ 91
10.4 High-Speed Interrupt ............................................................................................. 91
10.5 Interrupts and Interrupt Vectors ........................................................................... 91
10.5.1 Fixed Vector Tables ........................................................................................ 92
10.5.2 Relocatable Vector Tables .............................................................................. 92
10.6 Interrupt Request Reception ................................................................................. 95
10.6.1 I Flag and IPL ................................................................................................... 95
10.6.2 Interrupt Control Register and RLVL Register ............................................. 95
10.6.3 Interrupt Sequence ......................................................................................... 99
10.6.4 Interrupt Response Time .............................................................................. 100
10.6.5 IPL Change when Interrupt Request is Acknowledged ............................. 101
10.6.6 Saving a Register .......................................................................................... 102
10.6.7 Restoration from Interrupt Routine ............................................................. 102
10.6.8 Interrupt Priority ............................................................................................ 103
10.6.9 Interrupt Priority Level Select Circuit ......................................................... 103
______
10.7 INT Interrupt .......................................................................................................... 105
______
10.8 NMI Interrupt ......................................................................................................... 106
10.9 Key Input Interrupt ............................................................................................... 106
10.10 Address Match Interrupt .................................................................................... 107
10.11 Intelligent I/O Interrupt and CAN Interrupt ....................................................... 108
11. Watchdog Timer ____________________________ 111
12. DMAC_____________________________________ 114
12.1 Transfer Cycles .................................................................................................... 121
12.1.1 Effect of Source and Destination Addresses ............................................. 121
12.1.2 Effect of the DS Register .............................................................................. 121
12.1.3 Effect of Software Wait State ....................................................................... 121
________
12.1.4 Effect of RDY Signal ..................................................................................... 121
A-3
12.2 DMAC Transfer Cycles ......................................................................................... 123
12.3 Channel Priority and DMA Transfer Timing ....................................................... 123
13. DMAC II ___________________________________ 125
13.1 DMAC II Settings .................................................................................................. 125
13.1.1 RLVL Register................................................................................................ 125
13.1.2 DMAC II Index ................................................................................................ 127
13.1.3 Interrupt Control Register for the Peripheral Function ............................. 129
13.1.4 Relocatable Vector Table for the Peripheral Function .............................. 129
13.1.5 IRLT Bit in the IIOiIE Register (i=0 to 11)..................................................... 129
13.2 DMAC II Performance .......................................................................................... 129
13.3 Transfer Data ........................................................................................................ 129
13.3.1 Memory-to-Memory Transfer ....................................................................... 129
13.3.2 Immediate Data Transfer .............................................................................. 130
13.3.3 Calculation Transfer ..................................................................................... 130
13.4 Transfer Modes ..................................................................................................... 130
13.4.1 Single Transfer .............................................................................................. 130
13.4.2 Burst Transfer ............................................................................................... 130
13.4.3 Multiple Transfer ........................................................................................... 130
13.4.4 Chained Transfer........................................................................................... 131
13.4.5 End-of-Transfer Interrupt ............................................................................. 131
13.5 Execution Time ..................................................................................................... 132
14. Timer _____________________________________ 133
14.1 Timer A .................................................................................................................. 135
14.1.1 Timer Mode .................................................................................................... 141
14.1.2 Event Counter Mode ..................................................................................... 143
14.1.3 One-shot Timer Mode ................................................................................... 147
14.1.4 Pulse Width Modulation Mode ..................................................................... 149
14.2 Timer B .................................................................................................................. 152
14.2.1 Timer Mode .................................................................................................... 155
14.2.2 Event Counter Mode ..................................................................................... 156
14.2.3 Pulse Period/Pulse Width Measurement Mode .......................................... 158
15. Three-Phase Motor Control Timer Functions ____ 161
16. Serial I/O __________________________________ 172
16.1 Clock Synchronous Serial I/O Mode .................................................................. 182
16.1.1 Selecting CLK Polarity ................................................................................. 186
16.1.2 Selecting LSB First or MSB First ................................................................. 186
16.1.3 Continuous Receive Mode ........................................................................... 187
16.1.4 Serial Data Logic Inverse ............................................................................. 187
A-4
16.2 Clock Asynchronous Serial I/O (UART) Mode ................................................... 188
16.2.1 Bit Rate .......................................................................................................... 192
16.2.2 Selecting LSB First or MSB First ................................................................. 193
16.2.3 Serial Data Logic Inverse ............................................................................. 193
16.2.4 TxD and RxD I/O Polarity Inverse ................................................................ 194
16.3 Special Mode 1 (I2C Mode) .................................................................................. 195
16.3.1 Detecting Start Condition and Stop Condition .......................................... 200
16.3.2 Start Condition or Stop Condition Output .................................................. 201
16.3.3 Arbitration ...................................................................................................... 202
16.3.4 Transfer Clock ............................................................................................... 202
16.3.5 SDA Output .................................................................................................... 202
16.3.6 SDA Input ....................................................................................................... 203
16.3.7 ACK, NACK .................................................................................................... 203
16.3.8 Transmit and Receive Reset ........................................................................ 203
16.4 Special Mode 2 ..................................................................................................... 204
______
16.4.1 SSi Input Pin Function (i=0 to 4) .................................................................. 207
16.4.2 Clock Phase Setting Function ..................................................................... 208
16.5 Special Mode 3 (GCI Mode) ................................................................................. 210
16.6 Special Mode 4 (IE Mode) .................................................................................... 214
16.7 Special Mode 5 (SIM Mode) ................................................................................. 218
16.7.1 Parity Error Signal ........................................................................................ 222
16.7.2 Format ............................................................................................................ 223
17. A/D Converter ______________________________ 224
17.1 Mode Description ................................................................................................. 234
17.1.1 One-shot Mode .............................................................................................. 234
17.1.2 Repeat Mode .................................................................................................. 234
17.1.3 Single Sweep Mode ...................................................................................... 235
17.1.4 Repeat Sweep Mode 0 .................................................................................. 235
17.1.5 Repeat Sweep Mode 1 .................................................................................. 236
17.2 Function ................................................................................................................ 236
17.2.1 Resolution Select Function .......................................................................... 236
17.2.2 Sample and Hold ........................................................................................... 236
17.2.3 Trigger Select Function ................................................................................ 236
17.2.4 Two-Circuit Simultaneous Start (Software Trigger) ................................... 237
17.2.5 Pin Input Replacement Function ................................................................. 237
17.2.6 Extended Analog Input Pins ........................................................................ 238
17.2.7 External Operation Amplifier (Op-Amp) Connection Mode....................... 238
17.2.8 Power Consumption Reducing Function ................................................... 239
17.2.9 Analog Input Pin and External Sensor Equivalent Circuit ........................ 239
A-5
18.
19.
20.
21.
D/A Converter ______________________________
CRC Calculation ____________________________
X/Y Conversion _____________________________
Intelligent I/O_______________________________
240
243
245
248
21.1 Base Timer ............................................................................................................ 264
21.2 Time Measurement Function (Group 0 and 1) ................................................... 269
21.3 Waveform Generation Function .......................................................................... 274
21.3.1 Single-Phase Waveform Output Mode (Group 0 to 3) ............................... 276
21.3.2 Phase-Delayed Waveform Output Mode (Group 0 to 3) ............................ 278
21.3.3 Set/Reset Waveform Output (SR Waveform Output) Mode (Group 0 to 3) .... 280
21.3.4 Bit Modulation PWM Output Mode (Group 2 and 3) .................................. 283
21.3.5 Real-Time Port (RTP) Output Mode (Group 2 and 3) ................................. 285
21.3.6 Parallel Real-Time Port Output Mode (Group 2 and 3) .............................. 287
21.4 Communication Unit 0 and 1 Communication Function .................................. 289
21.4.1 Clock Synchronous Serial I/O Mode (Groups 0 and 1) .............................. 296
21.4.2 Clock Asynchronous Serial I/O Mode (UART) (Groups 0 and 1) .............. 299
21.4.3 HDLC Data Processing Mode (Group 0 and 1) ........................................... 303
21.5 Group 2 Communication Function ..................................................................... 306
21.5.1 Variable Clock Synchronous Serial I/O Mode (Group 2) ........................... 310
21.5.2 IEBus Mode (Group 2) .................................................................................. 314
21.6 Group 3 Communication Function ..................................................................... 317
21.6.1 8-bit or 16-bit Clock Synchronous Serial I/O Mode (Group 3) .................. 320
22. CAN Module _______________________________ 324
22.1 CAN-Associated Registers .................................................................................. 326
22.1.1 CAN0 Control Register 0 (C0CTLR0 Register) ............................................... 326
22.1.2 CAN0 Control Register 1 (C0CTLR1 Register) ........................................... 329
22.1.3 CAN0 Sleep Control Register (C0SLPR Register) ..................................... 330
22.1.4 CAN0 Status Register (C0STR Register) .................................................... 331
22.1.5 CAN0 Extended ID Register (C0IDR Register) ........................................... 333
22.1.6 CAN0 Configuration Register (C0CONR Register) .................................... 334
22.1.8 CAN0 Transmit Error Count Register (C0TEC Register) ........................... 336
22.1.7 CAN0 Time Stamp Register (C0TSR Register) ........................................... 336
22.1.9 CAN0 Receive Error Count Register (C0REC Register) ............................ 337
22.1.10 CAN0 Baud Rate Prescaler (C0BRP Register) ......................................... 337
22.1.11 CAN0 Slot Interrupt Status Register (C0SISTR Register) ....................... 338
22.1.12 CAN0 Slot Interrupt Mask Register (C0SIMKR Register) ........................ 340
A-6
22.1.13 CAN0 Error Interrupt Mask Register (C0EIMKR Register) ...................... 341
22.1.14 CAN0 Error Interrupt Status Register (C0EISTR Register) ..................... 342
22.1.15 CAN0 Global Mask Register, CAN0 Local Mask Register A and CAN0 Local Mask
Register B (C0GMRj (j=0 to4), C0LMARj and C0LMBRj Registers) .......... 343
22.1.16 CAN0 Message Slot i Control Register (C0MCTLi Register) (i=0 to 15) ... 346
22.1.17 CAN0 Slot Buffer Select Register (C0SBS Register) ............................... 349
22.1.18 Message Slot Buffer ................................................................................... 349
22.1.19 CAN0 Acceptance Filter Support Register (C0AFS Register)................. 354
22.2.2 CAN Transmit Timing ................................................................................... 355
22.2 Timing with CAN-Associated Registers ............................................................. 355
22.2.1 CAN Module Reset Timing ........................................................................... 355
22.2.3 CAN Receive Timing ..................................................................................... 356
22.2.4 CAN Bus Error Timing .................................................................................. 357
22.3 CAN Interrupts ...................................................................................................... 357
23. DRAMC ___________________________________ 359
23.1 DRAMC Multiplexed Address Output ................................................................. 361
23.2 Refresh .................................................................................................................. 361
23.2.1 Refresh ........................................................................................................... 361
23.2.2 Self-Refresh ................................................................................................... 361
24. Programmable I/O Ports _____________________ 366
24.1
24.2
24.3
24.4
24.5
24.6
24.7
24.8
24.9
Port Pi Direction Register (PDi Register, i=0 to 15)........................................... 366
Port Pi Register (Pi Register, i=0 to 15) .............................................................. 366
Function Select Register Aj (PSj Register) (j=0 to 3, 5 to 9) ............................. 366
Function Select Register Bk (PSLk Register) (k=0 to 3) ................................... 366
Function Select Register C (PSC Register) ....................................................... 367
Pull-up Control Register 0 to 4 (PUR0 to PUR4 Registers) .............................. 367
Port Control Register (PCR Register) ................................................................ 367
Input Function Select Register (IPS Register) ................................................... 367
Analog Input and Other Peripheral Function Input ........................................... 367
25. Flash Memory Version _______________________ 390
25.1 Memory Map ......................................................................................................... 391
25.1.1 Boot Mode ..................................................................................................... 392
25.2 Functions to Prevent the Flash Memory from Rewriting ................................. 392
25.2.1 ROM Code Protect Function ........................................................................ 392
25.2.2 ID Code Verify Function ............................................................................... 392
A-7
25.3 CPU Rewrite Mode ............................................................................................... 394
25.3.1 Flash Memory Control Register 0 (FMR0 Register) ................................... 395
25.3.2 Status Register.............................................................................................. 397
25.3.3 Data Protect Function ................................................................................... 398
25.3.4 How to Enter and Exit CPU Rewrite Mode .................................................. 399
25.3.5 Software Commands .................................................................................... 400
25.3.6 Full Status Check .......................................................................................... 406
25.3.7 Precautions in CPU Rewrite Mode .............................................................. 408
25.4 Standard Serial I/O Mode ..................................................................................... 409
25.4.1 Pin Function .................................................................................................. 409
25.4.2 ID Code Verify Function ............................................................................... 409
25.4.3 Precautions in Standard Serial I/O Mode .................................................... 414
25.4.4 Circuit Application in Standard Serial I/O Mode ........................................ 414
25.5 Parallel I/O Mode .................................................................................................. 415
25.5.1 Boot ROM Area.............................................................................................. 415
25.5.2 ROM Code Protect Function ........................................................................ 415
25.5.3 Precautions on Parallel I/O Mode ................................................................ 415
26. Electrical Characteristics ____________________ 416
26.1 Electrical Characteristics (M32C/83) .................................................................. 416
26.2 Electrical Characteristics (M32C/83T) ................................................................ 453
27. Precautions ________________________________ 462
27.1 Processor Mode ................................................................................................... 462
27.1.1 Microprocessor Mode ................................................................................... 462
27.2 Bus ........................................................................................................................ 463
__________
27.2.1 HOLD Signal .................................................................................................. 463
27.2.2 External Bus .................................................................................................. 463
27.3 SFR ........................................................................................................................ 464
27.3.1 100-Pin Package ............................................................................................ 464
27.3.2 Register Settings .......................................................................................... 464
27.4 Clock Generation Circuit ..................................................................................... 465
27.4.1 PLL Frequency Synthesizer ......................................................................... 465
27.4.2 Power Consumption Control ....................................................................... 465
27.4.3 Wait Mode ...................................................................................................... 466
27.4.4 Stop Mode ...................................................................................................... 466
27.5 Protection ............................................................................................................. 467
27.6 Interrupts .............................................................................................................. 468
27.6.1 ISP Setting ..................................................................................................... 468
_______
27.6.2 NMI Interrupt .................................................................................................. 468
A-8
______
27.6.3 INT Interrupt .................................................................................................. 468
27.6.4 Watchdog Timer Interrupt ............................................................................ 469
27.6.5 Changing Interrupt Control Register .......................................................... 469
27.6.6 Changing IIOiIR Register (i = 0 to 11) .......................................................... 469
27.6.7 Changing RLVL Register .............................................................................. 469
27.7 DMAC .................................................................................................................... 470
27.8 Timer...................................................................................................................... 471
27.8.1 Timers A and B .............................................................................................. 471
27.8.2 Timer A ........................................................................................................... 471
27.8.3 Timer B ........................................................................................................... 473
27.9 Three-Phase Motor Control Timer Functions .................................................... 474
27.9.1 Changing TAi and TAi1 (i=1, 2, 4) Registers ............................................... 474
27.10 Serial I/O .............................................................................................................. 475
27.10.1 Clock Synchronous Serial I/O Mode ......................................................... 475
27.10.2 UART Mode ................................................................................................. 476
27.10.3 Special Mode 2 ............................................................................................ 476
27.11 A/D Converter .................................................................................................... 477
27.12 Intelligent I/O ...................................................................................................... 479
27.12.1 Register Setting .......................................................................................... 479
27.12.2 BTSR Register Setting ................................................................................ 479
27.13 Programmable I/O Port ...................................................................................... 480
27.14 Flash Memory Version ....................................................................................... 481
27.14.1 Differences Between Flash Memory Version and Masked ROM Version ... 481
27.15 Noise ................................................................................................................... 482
27.16 Low Voltage Operations .................................................................................... 483
Package Dimensions ___________________________ 484
Register Index _________________________________ 486
A-9
Quick Reference by Address
Address
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
Register
Page
Processor Mode Register 0 (PM0)
Processor Mode Register 1 (PM1)
System Clock Control Register 0 (CM0)
System Clock Control Register 1 (CM1)
Wait Control Register 1 (WCR)
Address Match Interrupt Enable Register (AIER)
Protect Register (PRCR)
External Data Bus Width Control Register (DS)
Main Clock Division Register (MCD)
Oscillation Stop Detect Register (CM2)
Watchdog Timer Start Register (WDTS)
Watchdog Timer Control Register (WDC)
49
50
67
68
58
107
88
52
69
70
Address Match Interrupt Register 0 (RMAD0)
107
Address Match Interrupt Register 1 (RMAD1)
107
VDC Control Register for PLL (PLV)
72
Address Match Interrupt Register 2 (RMAD2)
107
VDC Control Register 0 (VDC0)
Address Match Interrupt Register 3 (RMAD3)
112
107
Address
Register
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
004016 DRAM Control Register (DRAMCONT)
004116 DRAM Refresh Interval Set Register (REFCNT)
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716 Flash Memory Control Register 0 (FMR0)
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
Page
360
395
Blank spaces are reserved. No access is allowed.
B-1
Quick Reference by Address
Address
006016
006116
006216
006316
006416
006516
006616
006716
006816
006916
006A16
006B16
006C16
006D16
006E16
006F16
007016
007116
007216
007316
007416
007516
007616
007716
007816
007916
007A16
007B16
007C16
007D16
007E16
007F16
Register
Page
DMA0 Interrupt Control Register (DM0IC)
Timer B5 Interrupt Control Register (TB5IC)
DMA2 Interrupt Control Register (DM2IC)
UART2 Receive /ACK Interrupt Control Register (S2RIC)
Timer A0 Interrupt Control Register (TA0IC)
UART3 Receive /ACK Interrupt Control Register (S3RIC)
Timer A2 Interrupt Control Register (TA2IC)
UART4 Receive /ACK Interrupt Control Register (S4RIC)
Timer A4 Interrupt Control Register (TA4IC)
UART0 Bus Conflict Detect Interrupt Control Register (BCN0IC)/
UART3 Bus Conflict Detect Interrupt Control Register (BCN3IC)
UART0 Receive/ACK Interrupt Control Register (S0RIC)
A/D0 Conversion Interrupt Control Register (AD0IC)
UART1 Receive/ACK Interrupt Control Register (S1RIC)
Intelligent I/O Interrupt Control Register 0 (IIO0IC)
Timer B1 Interrupt Control Register (TB1IC)
Intelligent I/O Interrupt Control Register 2 (IIO2IC)
Timer B3 Interrupt Control Register (TB3IC)
Intelligent I/O Interrupt Control Register 4 (IIO4IC)
INT5 Interrupt Control Register (INT5IC)
Intelligent I/O Interrupt Control Register 6 (IIO6IC)
INT3 Interrupt Control Register (INT3IC)
Intelligent I/O Interrupt Control Register 8 (IIO8IC)
INT1 Interrupt Control Register (INT1IC)
Intelligent I/O Interrupt Control Register 10 (IIO10IC)/
CAN Interrupt 1 Control Register (CAN1IC)
96
97
96
97
96
97
96
008016
Intelligent I/O Interrupt Control Register 11 (IIO11IC)/
008116
CAN Interrupt 2 Control Register (CAN2IC)
008216
008316
008416
008516
008616 A/D1 Conversion Interrupt Control Register (AD1IC)
008716
008816 DMA1 Interrupt Control Register (DM1IC)
008916 UART2 Transmit /NACK Interrupt Control Register (S2TIC)
008A16 DMA3 Interrupt Control Register (DM3IC)
008B16 UART3 Transmit /NACK Interrupt Control Register (S3TIC)
008C16 Timer A1 Interrupt Control Register (TA1IC)
008D16 UART4 Transmit /NACK Interrupt Control Register (S4TIC)
008E16 Timer A3 Interrupt Control Register (TA3IC)
008F16 UART2 Bus Conflict Detect Interrupt Control Register (BCN2IC)
Blank spaces are reserved. No access is allowed.
B-2
96
96
96
Address
Register
Page
009016 UART0 Transmit /NACK Interrupt Control Register (S0TIC)
UART1 Bus Conflict Detect Interrupt Control Register (BCN1IC)/
009116
UART4 Bus Conflict Detect Interrupt Control Register (BCN4IC)
009216 UART1 Transmit/NACK Interrupt Control Register (S1TIC)
009316 Key Input Interrupt Control Register (KUPIC)
009416 Timer B0 Interrupt Control Register (TB0IC)
96
009516 Intelligent I/O Interrupt Control Register 1 (IIO1IC)
009616 Timer B2 Interrupt Control Register (TB2IC)
009716 Intelligent I/O Interrupt Control Register 3 (IIO3IC)
009816 Timer B4 Interrupt Control Register (TB4IC)
009916 Intelligent I/O Interrupt Control Register 5 (IIO5IC)
009A16 INT4 Interrupt Control Register (INT4IC)
97
009B16 Intelligent I/O Interrupt Control Register 7 (IIO7IC) 96
009C16 INT2 Interrupt Control Register (INT2IC)
97
Intelligent I/O Interrupt Control Register 9 (IIO9IC)/
009D16
96
CAN Interrupt 0 Control Register (CAN0IC)
009E16 INT0 Interrupt Control Register (INT0IC)
97
009F16
00A016
00A116
00A216
00A316
00A416
00A516
00A616
00A716
00A816
00A916
00AA16
00AB16
00AC16
00AD16
00AE16
00AF16
00B016
00B116
00B216
00B316
00B416
00B516
00B616
00B716
00B816
00B916
00BA16
00BB16
00BC16
00BD16
00BE16
00BF16
Exit Priority Control Register (RLVL)
Interrupt Request Register 0 (IIO0IR)
Interrupt Request Register 1 (IIO1IR)
Interrupt Request Register 2 (IIO2IR)
Interrupt Request Register 3 (IIO3IR)
Interrupt Request Register 4 (IIO4IR)
Interrupt Request Register 5 (IIO5IR)
Interrupt Request Register 6 (IIO6IR)
Interrupt Request Register 7 (IIO7IR)
Interrupt Request Register 8 (IIO8IR)
Interrupt Request Register 9 (IIO9IR)
Interrupt Request Register 10 (IIO10IR)
Interrupt Request Register 11 (IIO11IR)
98
109
Interrupt Enable Register 0 (IIO0IE)
Interrupt Enable Register 1 (IIO1IE)
Interrupt Enable Register 2 (IIO2IE)
Interrupt Enable Register 3 (IIO3IE)
Interrupt Enable Register 4 (IIO4IE)
Interrupt Enable Register 5 (IIO5IE)
Interrupt Enable Register 6 (IIO6IE)
Interrupt Enable Register 7 (IIO7IE)
Interrupt Enable Register 8 (IIO8IE)
Interrupt Enable Register 9 (IIO9IE)
Interrupt Enable Register 10 (IIO10IE)
Interrupt Enable Register 11 (IIO11IE)
110
Quick Reference by Address
Address
00C016
00C116
00C216
00C316
00C416
00C516
00C616
00C716
00C816
00C916
00CA16
00CB16
00CC16
00CD16
00CE16
00CF16
00D016
00D116
00D216
00D316
00D416
00D516
00D616
00D716
00D816
00D916
00DA16
00DB16
00DC16
00DD16
00DE16
00DF16
00E016
00E116
00E216
00E316
00E416
00E516
Register
Page
Group 0 Time Measurement Register 0 (G0TM0)/
Group 0 Waveform Generation Register 0 (G0PO0)
Group 0 Time Measurement Register 1 (G0TM1)/
Group 0 Waveform Generation Register 1 (G0PO1)
Group 0 Time Measurement Register 2 (G0TM2)/
Group 0 Waveform Generation Register 2 (G0PO2)
Group 0 Time Measurement Register 3 (G0TM3)/
Group 0 Waveform Generation Register 3 (G0PO3)
259/
Group 0 Time Measurement Register 4 (G0TM4)/
261
Group 0 Waveform Generation Register 4 (G0PO4)
Group 0 Time Measurement Register 5 (G0TM5)/
Group 0 Waveform Generation Register 5 (G0PO5)
Group 0 Time Measurement Register 6 (G0TM6)/
Group 0 Waveform Generation Register 6 (G0PO6)
Group 0 Time Measurement Register 7 (G0TM7)/
Group 0 Waveform Generation Register 7 (G0PO7)
Group 0 Waveform Generation Control Register 0 (G0POCR0)
Group 0 Waveform Generation Control Register 1 (G0POCR1)
Group 0 Waveform Generation Control Register 2 (G0POCR2)
Group 0 Waveform Generation Control Register 3 (G0POCR3)
259
Group 0 Waveform Generation Control Register 4 (G0POCR4)
Group 0 Waveform Generation Control Register 5 (G0POCR5)
Group 0 Waveform Generation Control Register 6 (G0POCR6)
Group 0 Waveform Generation Control Register 7 (G0POCR7)
Group 0 Time Measurement Control Register 0 (G0TMCR0)
Group 0 Time Measurement Control Register 1 (G0TMCR1)
Group 0 Time Measurement Control Register 2 (G0TMCR2)
Group 0 Time Measurement Control Register 3 (G0TMCR3)
258
Group 0 Time Measurement Control Register 4 (G0TMCR4)
Group 0 Time Measurement Control Register 5 (G0TMCR5)
Group 0 Time Measurement Control Register 6 (G0TMCR6)
Group 0 Time Measurement Control Register 7 (G0TMCR7)
00E616
00E716
00E816
00E916
00EA16
00EB16
00EC16
00ED16
00EE16
00EF16
Group 0 Function Enable Register (G0FE)
Group 0 Function Select Register (G0FS)
262
Group 0 SI/O Receive Buffer Register (G0RB)
291
Group 0 Transmit Buffer/Receive Data Register (G0TB/G0DR)
294
Group 0 Receive Input Register (G0RI)
Group 0 SI/O Communication Mode Register (G0MR)
Group 0 Transmit Output Register (G0TO)
Group 0 SI/O Communication Control Register (G0CR)
289
291
289
290
Group 0 Base Timer Register (G0BT)
Group 0 Base Timer Control Register 0 (G0BCR0)
Group 0 Base Timer Control Register 1 (G0BCR1)
Group 0 Time Measurement Prescaler Register 6 (G0TPR6)
Group 0 Time Measurement Prescaler Register 7 (G0TPR7)
253
254
258
Address
00F016
00F116
00F216
00F316
00F416
00F516
00F616
00F716
00F816
00F916
00FA16
00FB16
00FC16
00FD16
00FE16
00FF16
010016
010116
010216
010316
010416
010516
010616
010716
010816
010916
010A16
010B16
010C16
010D16
010E16
010F16
011016
011116
011216
011316
011416
011516
011616
011716
011816
011916
011A16
011B16
011C16
011D16
011E16
011F16
Register
Group 0 Data Compare Register 0 (G0CMP0)
Group 0 Data Compare Register 1 (G0CMP1)
Group 0 Data Compare Register 2 (G0CMP2)
Group 0 Data Compare Register 3 (G0CMP3)
Group 0 Data Mask Register 0 (G0MSK0)
Group 0 Data Mask Register 1 (G0MSK1)
Page
295
Group 0 Receive CRC Code Register (G0RCRC)
295
Group 0 Transmit CRC Code Register (G0TCRC)
Group 0 SI/O Extended Mode Register (G0EMR)
Group 0 SI/O Extended Receive Control Register (G0ERC)
Group 0 SI/O Special Communication Interrupt Detect Register (G0IRF)
Group 0 SI/O Extended Transmit Control Register (G0ETC)
Group 1 Time Measurement Register 0 (G1TM0)/
Group 1 Waveform Generation Register 0 (G1PO0)
Group 1 Time Measurement Register 1 (G1TM1)/
Group 1 Waveform Generation Register 1 (G1PO1)
Group 1 Time Measurement Register 2 (G1TM2)/
Group 1 Waveform Generation Register 2 (G1PO2)
Group 1 Time Measurement Register 3 (G1TM3)/
Group 1 Waveform Generation Register 3 (G1PO3)
Group 1 Time Measurement Register 4 (G1TM4)/
Group 1 Waveform Generation Register 4 (G1PO4)
Group 1 Time Measurement Register 5 (G1TM5)/
Group 1 Waveform Generation Register 5 (G1PO5)
Group 1 Time Measurement Register 6 (G1TM6)/
Group 1 Waveform Generation Register 6 (G1PO6)
Group 1 Time Measurement Register 7 (G1TM7)/
Group 1 Waveform Generation Register 7 (G1PO7)
Group 1 Waveform Generation Control Register 0 (G1POCR0)
Group 1 Waveform Generation Control Register 1 (G1POCR1)
Group 1 Waveform Generation Control Register 2 (G1POCR2)
Group 1 Waveform Generation Control Register 3 (G1POCR3)
Group 1 Waveform Generation Control Register 4 (G1POCR4)
Group 1 Waveform Generation Control Register 5 (G1POCR5)
Group 1 Waveform Generation Control Register 6 (G1POCR6)
Group 1 Waveform Generation Control Register 7 (G1POCR7)
Group 1 Time Measurement Control Register 0 (G1TMCR0)
Group 1 Time Measurement Control Register 1 (G1TMCR1)
Group 1 Time Measurement Control Register 2 (G1TMCR2)
Group 1 Time Measurement Control Register 3 (G1TMCR3)
Group 1 Time Measurement Control Register 4 (G1TMCR4)
Group 1 Time Measurement Control Register 5 (G1TMCR5)
Group 1 Time Measurement Control Register 6 (G1TMCR6)
Group 1 Time Measurement Control Register 7 (G1TMCR7)
292
293
294
292
259/
261
259
258
Blank spaces are reserved. No access is allowed.
B-3
Quick Reference by Address
Address
012016
012116
012216
012316
012416
012516
012616
012716
012816
012916
012A16
012B16
012C16
012D16
012E16
012F16
013016
013116
013216
013316
013416
013516
013616
013716
013816
013916
013A16
013B16
013C16
013D16
013E16
013F16
014016
014116
014216
014316
014416
014516
014616
014716
014816
014916
014A16
014B16
014C16
014D16
014E16
014F16
Register
Group 1 Base Timer Register (G1BT)
Group 1 Base Timer Control Register 0 (G1BCR0)
Group 1 Base Timer Control Register 1 (G1BCR1)
Group 1 Time Measurement Prescaler Register 6 (G1TPR6)
Group 1 Time Measurement Prescaler Register 7 (G1TPR7)
Group 1 Function Enable Register (G1FE)
Group 1 Function Select Register (G1FS)
253
254
258
262
Group 1 SI/O Receive Buffer Register (G1RB)
291
Group 1 Transmit Buffer/Receive Data Register (G1TB/G1DR)
294
Group 1 Receive Input Register (G1RI)
Group 1 SI/O Communication Mode Register (G1MR)
Group 1 Transmit Output Register (G1TO)
Group 1 SI/O Communication Control Register (G1CR)
Group 1 Data Compare Register 0 (G1CMP0)
289
291
289
290
Group 1 Data Compare Register 1 (G1CMP1)
Group 1 Data Compare Register 2 (G1CMP2)
Group 1 Data Compare Register 3 (G1CMP3)
Group 1 Data Mask Register 0 (G1MSK0)
Group 1 Data Mask Register 1 (G1MSK1)
295
Group 1 Receive CRC Code Register (G1RCRC)
295
Group 1 Transmit CRC Code Register (G1TCRC)
Group 1 SI/O Extended Mode Register (G1EMR)
Group 1 SI/O Extended Receive Control Register (G1ERC)
Group 1 SI/O Special Communication Interrupt Detect Register (G1IRF)
Group 1 SI/O Extended Transmit Control Register (G1ETC)
292
293
294
292
Group 2 Waveform Generation Register 0 (G2PO0)
Group 2 Waveform Generation Register 1 (G2PO1)
Group 2 Waveform Generation Register 2 (G2PO2)
Group 2 Waveform Generation Register 3 (G2PO3)
261
Group 2 Waveform Generation Register 4 (G2PO4)
Group 2 Waveform Generation Register 5 (G2PO5)
Group 2 Waveform Generation Register 6 (G2PO6)
Group 2 Waveform Generation Register 7 (G2PO7)
Blank spaces are reserved. No access is allowed.
B-4
Page
Address
015016
015116
015216
015316
015416
015516
015616
015716
015816
015916
015A16
015B16
015C16
015D16
015E16
015F16
016016
016116
016216
016316
016416
016516
016616
016716
016816
016916
016A16
016B16
016C16
016D16
016E16
016F16
017016
017116
017216
017316
017416
017516
017616
017716
017816
017916
017A16
017B16
017C16
017D16
017E16
017F16
Register
Page
Group 2 Waveform Generation Control Register 0 (G2POCR0)
Group 2 Waveform Generation Control Register 1 (G2POCR1)
Group 2 Waveform Generation Control Register 2 (G2POCR2)
Group 2 Waveform Generation Control Register 3 (G2POCR3) 260
Group 2 Waveform Generation Control Register 4 (G2POCR4)
Group 2 Waveform Generation Control Register 5 (G2POCR5)
Group 2 Waveform Generation Control Register 6 (G2POCR6)
Group 2 Waveform Generation Control Register 7 (G2POCR7)
Group 2 Base Timer Register (G2BT)
253
Group 2 Base Timer Control Register 0 (G2BCR0)
Group 2 Base Timer Control Register 1 (G2BCR1)
Base Timer Start Register (BTSR)
255
257
Group 2 Function Enable Register (G2FE)
Group 2 RTP Output Buffer Register (G2RTP)
262
263
Group 2 SI/O Communication Mode Register (G2MR)
Group 2 SI/O Communication Control Register (G2CR)
307
Group 2 SI/O Transmit Buffer Register (G2TB)
306
Group 2 SI/O Receive Buffer Register (G2RB)
Group 2 IEBus Address Register (IEAR)
308
Group 2 IEBus Control Register (IECR)
Group 2 IEBus Transmit Interrupt Cause Detect Register (IETIF)
Group 2 IEBus Receive Interrupt Cause Detect Register (IERIF)
309
Input Function Select Register (IPS)
383
Group 3 SI/O Communication Mode Register (G3MR)
Group 3 SI/O Communication Control Register (G3CR)
318
Group 3 SI/O Transmit Buffer Register (G3TB)
317
Group 3 SI/O Receive Buffer Register (G3RB)
Quick Reference by Address
Address
018016
018116
018216
018316
018416
018516
018616
018716
018816
018916
018A16
018B16
018C16
018D16
018E16
018F16
019016
019116
019216
019316
019416
019516
019616
019716
019816
019916
019A16
019B16
019C16
019D16
019E16
019F16
01A016
01A116
01A216
01A316
01A416
01A516
01A616
01A716
01A816
01A916
01AA16
01AB16
01AC16
01AD16
01AE16
01AF16
Register
Page
Group 3 Waveform Generation Register 0 (G3PO0)
Group 3 Waveform Generation Register 1 (G3PO1)
Group 3 Waveform Generation Register 2 (G3PO2)
Group 3 Waveform Generation Register 3 (G3PO3)
261
Group 3 Waveform Generation Register 4 (G3PO4)
Group 3 Waveform Generation Register 5 (G3PO5)
Group 3 Waveform Generation Register 6 (G3PO6)
Group 3 Waveform Generation Register 7 (G3PO7)
Group 3 Waveform Generation Control Register 0 (G3POCR0)
Group 3 Waveform Generation Control Register 1 (G3POCR1)
Group 3 Waveform Generation Control Register 2 (G3POCR2)
Group 3 Waveform Generation Control Register 3 (G3POCR3)
Group 3 Waveform Generation Control Register 4 (G3POCR4)
Group 3 Waveform Generation Control Register 5 (G3POCR5)
Group 3 Waveform Generation Control Register 6 (G3POCR6)
Group 3 Waveform Generation Control Register 7 (G3POCR7)
260
Group 3 Waveform Generation Mask Register 4 (G3MK4)
Group 3 Waveform Generation Mask Register 5 (G3MK5)
261
Group 3 Waveform Generation Mask Register 6 (G3MK6)
Group 3 Waveform Generation Mask Register 7 (G3MK7)
Group 3 Base Timer Register (G3BT)
Group 3 Base Timer Control Register 0 (G3BCR0)
Group 3 Base Timer Control Register 1 (G3BCR1)
253
256
Group 3 Function Enable Register 1 (G3FE)
Group 3 RTP Output Buffer Register 1 (G3RTP)
262
263
Group 3 SI/O Communication Flag Register (G3FLG)
319
Address
01B016
01B116
01B216
01B316
01B416
01B516
01B616
01B716
01B816
01B916
01BA16
01BB16
01BC16
01BD16
01BE16
01BF16
01C016
01C116
01C216
01C316
01C416
01C516
01C616
01C716
01C816
01C916
01CA16
01CB16
01CC16
01CD16
01CE16
01CF16
01D016
01D116
01D216
01D316
01D416
01D516
01D616
01D716
01D816
01D916
01DA16
01DB16
01DC16
01DD16
01DE16
01DF16
Register
Page
A/D1 Register 0 (AD10)
A/D1 Register 1 (AD11)
A/D1 Register 2 (AD12)
A/D1 Register 3 (AD13)
233
A/D1 Register 4 (AD14)
A/D1 Register 5 (AD15)
A/D1 Register 6 (AD16)
A/D1 Register 7 (AD17)
A/D1 Control Register 2 (AD1CON2)
233
A/D1 Control Register 0 (AD1CON0)
A/D1 Control Register 1 (AD1CON1)
231
232
Blank spaces are reserved. No access is allowed.
B-5
Quick Reference by Address
Address
01E016
01E116
01E216
01E316
01E416
01E516
01E616
01E716
01E816
01E916
01EA16
01EB16
01EC16
01ED16
01EE16
01EF16
01F016
01F116
01F216
01F316
01F416
01F516
01F616
01F716
01F816
01F916
01FA16
01FB16
01FC16
01FD16
01FE16
01FF16
020016
020116
020216
020316
020416
020516
020616
020716
020816
020916
020A16
020B16
020C16
020D16
020E16
020F16
Register
Page
CAN0 Message Slot Buffer 0 Standard ID0 (C0SLOT0_0)
350
CAN0 Message Slot Buffer 0 Standard ID1 (C0SLOT0_1)
CAN0 Message Slot Buffer 0 Extended ID0 (C0SLOT0_2)
351
CAN0 Message Slot Buffer 0 Extended ID1 (C0SLOT0_3)
CAN0 Message Slot Buffer 0 Extended ID2 (C0SLOT0_4)
352
CAN0 Message Slot Buffer 0 Data Length Code (C0SLOT0_5)
CAN0 Message Slot Buffer 0 Data 0 (C0SLOT0_6)
CAN0 Message Slot Buffer 0 Data 1 (C0SLOT0_7)
CAN0 Message Slot Buffer 0 Data 2 (C0SLOT0_8)
CAN0 Message Slot Buffer 0 Data 3 (C0SLOT0_9)
CAN0 Message Slot Buffer 0 Data 4 (C0SLOT0_10)
353
CAN0 Message Slot Buffer 0 Data 5 (C0SLOT0_11)
CAN0 Message Slot Buffer 0 Data 6 (C0SLOT0_12)
CAN0 Message Slot Buffer 0 Data 7 (C0SLOT0_13)
CAN0 Message Slot Buffer 0 Time Stamp High-Order (C0SLOT0_14)
CAN0 Message Slot Buffer 0 Time Stamp Low-Order (C0SLOT0_15)
CAN0 Message Slot Buffer 1 Standard ID0 (C0SLOT1_0)
350
CAN0 Message Slot Buffer 1 Standard ID1 (C0SLOT1_1)
CAN0 Message Slot Buffer 1 Extended ID0 (C0SLOT1_2)
351
CAN0 Message Slot Buffer 1 Extended ID1 (C0SLOT1_3)
CAN0 Message Slot Buffer 1 Extended ID2 (C0SLOT1_4)
352
CAN0 Message Slot Buffer 1 Data Length Code (C0SLOT1_5)
CAN0 Message Slot Buffer 1 Data 0 (C0SLOT1_6)
CAN0 Message Slot Buffer 1 Data 1 (C0SLOT1_7)
CAN0 Message Slot Buffer 1 Data 2 (C0SLOT1_8)
CAN0 Message Slot Buffer 1 Data 3 (C0SLOT1_9)
CAN0 Message Slot Buffer 1 Data 4 (C0SLOT1_10)
353
CAN0 Message Slot Buffer 1 Data 5 (C0SLOT1_11)
CAN0 Message Slot Buffer 1 Data 6 (C0SLOT1_12)
CAN0 Message Slot Buffer 1 Data 7 (C0SLOT1_13)
CAN0 Message Slot Buffer 1 Time Stamp High-Order (C0SLOT1_14)
CAN0 Message Slot Buffer 1 Time Stamp Low-Order (C0SLOT1_15)
Address
021016
021116
021216
021316
021416
021516
021616
021716
021816
021916
021A16
021B16
021C16
021D16
021E16
021F16
022016
022116
022216
022316
022416
022516
022616
022716
022816
022916
022A16
022B16
022C16
022D16
022E16
022F16
CAN0 Control Register0 (C0CTLR0)
326
023016
CAN0 Status Register (C0STR)
331
023116
CAN0 Extended ID Register (C0IDR)
333
023216
CAN0 Configuration Register (C0CONR)
334
023316
CAN0 Time Stamp Register (C0TSR)
CAN0 Transmit Error Count Register (C0TEC)
CAN0 Receive Error Count Register (C0REC)
337
CAN0 Slot Interrupt Status Register (C0SISTR)
338
Blank spaces are reserved. No access is allowed.
B-6
336
023416
023516
023616
023716
023816
Register
Page
CAN0 Slot Interrupt Mask Register (C0SIMKR)
340
CAN0 Error Interrupt Mask Register (C0EIMKR)
CAN0 Error Interrupt Status Register (C0EISTR)
341
342
CAN0 Baud Rate Prescaler (C0BPR)
337
CAN0 Global Mask Register Standard ID0 (C0GMR0)
CAN0 Global Mask Register Standard ID1 (C0GMR1)
CAN0 Global Mask Register Extended ID0 (C0GMR2)
CAN0 Global Mask Register Extended ID1 (C0GMR3)
CAN0 Global Mask Register Extended ID2 (C0GMR4)
343
CAN0 Message Slot 0 Control Register (C0MCTL0)/
CAN0 Local Mask Register A Standard ID0 (C0LMAR0)
CAN0 Message Slot 1 Control Register (C0MCTL1)/
CAN0 Local Mask Register A Standard ID1 (C0LMAR1)
CAN0 Message Slot 2 Control Register (C0MCTL2)/
CAN0 Local Mask Register A Extended ID0 (C0LMAR2)
CAN0 Message Slot 3 Control Register (C0MCTL3)/
CAN0 Local Mask Register A Extended ID1 (C0LMAR3)
CAN0 Message Slot 4 Control Register (C0MCTL4)/
CAN0 Local Mask Register A Extended ID2 (C0LMAR4)
CAN0 Message Slot 5 Control Register (C0MCTL5)
CAN0 Message Slot 6 Control Register (C0MCTL6)
CAN0 Message Slot 7 Control Register (C0MCTL7)
CAN0 Message Slot 8 Control Register (C0MCTL8)/
CAN0 Local Mask Register B Standard ID0 (C0LMBR0)
346/
343
344
345
344/
346/
345
346/
346
346/
343
Quick Reference by Address
Address
023916
023A16
023B16
023C16
Register
Page
CAN0 Message Slot 9 Control Register (C0MCTL9)/
CAN0 Local Mask Register B Standard ID1 (C0LMBR1) 344
CAN0 Message Slot 10 Control Register (C0MCTL10)/ 346/
CAN0 Local Mask Register B Extended ID0 (C0LMBR2)
CAN0 Message Slot 11 Control Register (C0MCTL11)/
CAN0 Local Mask Register B Extended ID1 (C0LMBR3) 345
CAN0 Message Slot 12 Control Register (C0MCTL12)/ 346/
CAN0 Local Mask Register B Extended ID2 (C0LMBR4)
CAN0 Message Slot 13 Control Register (C0MCTL13)
CAN0 Message Slot 14 Control Register (C0MCTL14) 346
CAN0 Message Slot 15 Control Register(C0MCTL15)
CAN0 Slot Buffer Select Register (C0SBS)
349
CAN0 Control Register 1 (C0CTLR1)
329
CAN0 Sleep Control Register (C0SLPR)
330
023D16
023E16
023F16
024016
024116
024216
024316
024416
CAN0 Acceptance Filter Support Register (C0AFS)
024516
354
Address
02C016
02C116
02C216
02C316
02C416
02C516
02C616
02C716
02C816
02C916
02CA16
02CB16
02CC16
02CD16
02CE16
02CF16
02D016
02D116
02D216
02D316
02D416
02D516
02D616
02D716
02D816
02D916
02DA16
02DB16
02DC16
02DD16
02DE16
02DF16
02E016
02E116
02E216
02E316
02E416
02E516
02E616
02E716
02E816
02E916
02EA16
02EB16
02EC16
02ED16
02EE16
02EF16
Register
Page
X0 Register Y0 Register (X0R,Y0R)
X1 Register Y1 Register (X1R,Y1R)
X2 Register Y2 Register (X2R,Y2R)
X3 Register Y3 Register (X3R,Y3R)
X4 Register Y4 Register (X4R,Y4R)
X5 Register Y5 Register (X5R,Y5R)
X6 Register Y6 Register (X6R,Y6R)
X7 Register Y7 Register (X7R,Y7R)
246
X8 Register Y8 Register (X8R,Y8R)
X9 Register Y9 Register (X9R,Y9R)
X10 Register Y10 Register (X10R,Y10R)
X11 Register Y11 Register (X11R,Y11R)
X12 Register Y12 Register (X12R,Y12R)
X13 Register Y13 Register (X13R,Y13R)
X14 Register Y14 Register (X14R,Y14R)
X15 Register Y15 Register (X15R,Y15R)
XY Control Register (XYC)
245
UART1 Special Mode Register 4 (U1SMR4)
UART1 Special Mode Register 3 (U1SMR3)
UART1 Special Mode Register 2 (U1SMR2)
UART1 Special Mode Register (U1SMR)
UART1 Transmit/Receive Mode Register (U1MR)
UART1 Baud Rate Register (U1BRG)
180
179
178
177
175
UART1 Transmit Buffer Register (U1TB)
174
UART1 Transmit/Receive Control Register 0 (U1C0)
UART1 Transmit/Receive Control Register 1 (U1C1)
176
177
UART1 Receive Buffer Register (U1RB)
174
Blank spaces are reserved. No access is allowed.
B-7
Quick Reference by Address
Address
02F016
02F116
02F216
02F316
02F416
02F516
02F616
02F716
02F816
02F916
02FA16
02FB16
02FC16
02FD16
02FE16
02FF16
030016
030116
030216
030316
030416
030516
030616
030716
030816
030916
030A16
030B16
030C16
030D16
030E16
030F16
031016
031116
031216
031316
031416
031516
031616
031716
031816
031916
031A16
031B16
031C16
031D16
031E16
031F16
Register
Page
UART4 Special Mode Register 4 (U4SMR4)
UART4 Special Mode Register 3 (U4SMR3)
UART4 Special Mode Register 2 (U4SMR2)
UART4 Special Mode Register (U4SMR)
UART4 Transmit/Receive Mode Register (U4MR)
UART4 Baud Rate Register (U4BRG)
180
179
178
177
UART4 Transmit Buffer Register (U4TB)
174
UART4 Transmit/Receive Control Register 0 (U4C0)
UART4 Transmit/Receive Control Register 1 (U4C1)
176
177
UART4 Receive Buffer Register (U4RB)
174
Timer B3,B4,B5 Count Start Flag (TBSR)
154
Timer A1-1 Register (TA11)
Timer A2-1 Register (TA21)
167
Timer A4-1 Register (TA41)
Three-Phase PWM Control Register 0 (INVC0)
Three-Phase PWM Control Register 1 (INVC1)
Three-Phase Output Buffer Register 0 (IDB0)
Three-Phase Output Buffer Register 1 (IDB1)
Dead Time Timer (DTT)
Timer B2 Interrupt Generation Frequency Set Counter (ICTB2)
164
165
166
167
Timer B3 Register (TB3)
Timer B4 Register (TB4)
152
Timer B5 Register (TB5)
Timer B3 Mode Register (TB3MR)
Timer B4 Mode Register (TB4MR)
Timer B5 Mode Register (TB5MR)
153
External Interrupt Cause Select Register (IFSR)
105
Blank spaces are reserved. No access is allowed.
B-8
175
Address
032016
032116
032216
032316
032416
032516
032616
032716
032816
032916
032A16
032B16
032C16
032D16
032E16
032F16
033016
033116
033216
033316
033416
033516
033616
033716
033816
033916
033A16
033B16
033C16
033D16
033E16
033F16
034016
034116
034216
034316
034416
034516
034616
034716
034816
034916
034A16
034B16
034C16
034D16
034E16
034F16
Register
Page
UART3 Special Mode Register 4 (U3SMR4)
UART3 Special Mode Register 3 (U3SMR3)
UART3 Special Mode Register 2 (U3SMR2)
UART3 Special Mode Register (U3SMR)
UART3 Transmit/Receive Mode Register (U3MR)
UART3 Baud Rate Register (U3BRG)
180
179
178
177
175
UART3 Transmit Buffer Register (U3TB)
174
UART3 Transmit/Receive Control Register 0 (U3C0)
UART3 Transmit/Receive Control Register 1 (U3C1)
176
177
UART3 Receive Buffer Register (U3RB)
174
UART2 Special Mode Register 4 (U2SMR4)
UART2 Special Mode Register 3 (U2SMR3)
UART2 Special Mode Register 2 (U2SMR2)
UART2 Special Mode Register (U2SMR)
UART2 Transmit/Receive Mode Register (U2MR)
UART2 Baud Rate Register (U2BRG)
180
179
178
177
175
UART2 Transmit Buffer Register (U2TB)
174
UART2 Transmit/Receive Control Register 0 (U2C0)
UART2 Transmit/Receive Control Register 1 (U2C1)
176
177
UART2 Receive Buffer Register (U2RB)
174
Count Start Flag (TABSR)
Clock Prescaler Reset Flag (CPSRF)
One-Shot Start Flag (ONSF)
Trigger Select Register (TRGSR)
Up-Down Flag (UDF)
137
71
138
139
138
Timer A0 Register (TA0)
Timer A1 Register (TA1)
Timer A2 Register (TA2)
Timer A3 Register (TA3)
Timer A4 Register (TA4)
136
Quick Reference by Address
Address
035016
035116
035216
035316
035416
035516
035616
035716
035816
035916
035A16
035B16
035C16
035D16
035E16
035F16
036016
036116
036216
036316
036416
036516
036616
036716
036816
036916
036A16
036B16
036C16
036D16
036E16
036F16
037016
037116
037216
037316
037416
037516
037616
037716
037816
037916
037A16
037B16
037C16
037D16
037E16
037F16
Register
Page
Timer B0 Register (TB0)
Timer B1 Register (TB1)
152
Timer B2 Register (TB2)
Timer A0 Mode Register (TA0MR)
Timer A1 Mode Register (TA1MR)
Timer A2 Mode Register (TA2MR)
Timer A3 Mode Register (TA3MR)
Timer A4 Mode Register (TA4MR)
Timer B0 Mode Register (TB0MR)
Timer B1 Mode Register (TB1MR)
Timer B2 Mode Register (TB2MR)
Timer B2 Special Mode Register (TB2SC)
Count Source Prescaler Register (TCSPR)
UART0 Special Mode Register 4 (U0SMR4)
UART0 Special Mode Register 3 (U0SMR3)
UART0 Special Mode Register 2 (U0SMR2)
UART0 Special Mode Register (U0SMR)
UART0 Transmit/Receive Mode Register (U0MR)
UART0 Baud Rate Register (U0BRG)
137
153
167
71
180
179
178
177
175
UART0 Transmit Buffer Register (U0TB)
174
UART0 Transmit/Receive Control Register 0 (U0C0)
UART0 Transmit/Receive Control Register 1 (U0C1)
176
177
UART0 Receive Buffer Register (U0RB)
174
PLL Control Register 0 (PLC0)
PLL Control Register 1 (PLC1)
DMA0 Cause Select Register (DM0SL)
DMA1 Cause Select Register (DM1SL)
DMA2 Cause Select Register (DM2SL)
DMA3 Cause Select Register (DM3SL)
72
73
CRC Data Register (CRCD)
Address
038016
038116
038216
038316
038416
038516
038616
038716
038816
038916
038A16
038B16
038C16
038D16
038E16
038F16
039016
039116
039216
039316
039416
039516
039616
039716
039816
039916
039A16
039B16
039C16
039D16
039E16
039F16
Register
Page
A/D0 Register0 (AD00)
A/D0 Register1 (AD01)
A/D0 Register2 (AD02)
A/D0 Register3 (AD03)
230
A/D0 Register4 (AD04)
A/D0 Register5 (AD05)
A/D0 Register6 (AD06)
A/D0 Register7 (AD07)
A/D0 Control Register 2 (AD0CON2)
230
A/D0 Control Register 0 (AD0CON0)
A/D0 Control Register 1 (AD0CON1)
D/A Register 0 (DA0)
228
229
242
D/A Register 1 (DA1)
242
D/A Control Register (DACON)
242
116
243
CRC Input Register (CRCIN)
Blank spaces are reserved. No access is allowed.
B-9
Quick Reference by Address
Address
03A016
03A116
03A216
03A316
03A416
03A516
03A616
03A716
03A816
03A916
03AA16
03AB16
03AC16
03AD16
03AE16
03AF16
03B016
Register
Function Select Register A8 (PS8)
Function Select Register A9 (PS9)
03B116
03B216
03B316
03B416
03B516
03B616
03B716
03B816
03B916
03BA16
03BB16
03BC16
03BD16
03BE16
03BF16
03C016
03C116
03C216
03C316
03C416
03C516
03C616
03C716
03C816
03C916
03CA16
03CB16
03CC16
03CD16
03CE16
03CF16
Function Select Register A1 (PS1)
Function Select Register B0 (PSL0)
Function Select Register B1 (PSL1)
Function Select Register A2 (PS2)
Function Select Register A3 (PS3)
Function Select Register B2 (PSL2)
Function Select Register B3 (PSL3)
Function Select Register C (PSC)
Function Select Register A0 (PS0)
Function Select Register A5 (PS5)
Function Select Register A6 (PS6)
Function Select Register A7 (PS7)
Port P6 Register (P6)
Port P7 Register (P7)
Port P6 Direction Register (PD6)
Port P7 Direction Register (PD7)
Port P8 Register (P8)
Port P9 Register (P9)
Port P8 Direction Register (PD8)
Port P9 Direction Register (PD9)
Port P10 Register (P10)
Port P11 Register (P11)
Port P10 Direction Register (PD10)
Port P11 Direction Register(PD11)
Port P12 Register (P12)
Port P13 rRegister (P13)
Port P12 Direction Register (PD12)
Port P13 Direction Register (PD13)
Blank spaces are reserved. No access is allowed.
B-10
Page
376
377
380
373
378
374
379
375
375
376
372
371
372
371
372
371
372
371
Address
03D016
03D116
03D216
03D316
03D416
03D516
03D616
03D716
03D816
03D916
03DA16
03DB16
03DC16
03DD16
03DE16
03DF16
03E016
Register
Port P14 Register (P14)
Port P15 Register (P15)
Port P14 Direction Register (PD14)
Port P15 Direction Register (PD15)
Page
Pull-Up Control Register 2 (PUR2)
Pull-Up Control Register 3 (PUR3)
Pull-Up Control Register 4 (PUR4)
381
03E116
03E216
03E316
03E416
03E516
03E616
03E716
03E816
03E916
03EA16
03EB16
03EC16
03ED16
03EE16
03EF16
03F016
03F116
03F216
03F316
03F416
03F516
03F616
03F716
03F816
03F916
03FA16
03FB16
03FC16
03FD16
03FE16
03FF16
Port P14 Register (P1)
Port P14 Direction Register (PD0)
Port P14 Direction Register (PD1)
Port P14 Register (P2)
Port P14 Register (P3)
Port P14 Direction Register (PD2)
Port P14 Direction Register (PD3)
Port P14 Register (P4)
Port P14 Register (P5)
Port P14 Direction Register (PD4)
Port P14 Direction Register (PD5)
Port P14 Register (P0)
372
371
382
372
371
372
371
372
371
Pull-Up Control Register 0 (PUR0)
Pull-Up Control Register 1 (PUR1)
381
Port Control Register (PCR)
383
M32C/83 Group (M32C/83, M32C/83T)
SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER
1. Overview
The M32C/83 Group (M32C/83, M32C/83T) microcomputer is a single-chip control unit that utilizes highperformance silicon gate CMOS technology with the M32C/80 Series CPU core. The M32C/83 Group
(M32C/83, M32C/83T) is available in 144-pin and 100-pin plastic molded LQFP/QFP packages.
With a 16-Mbyte address space, this microcomputer combines advanced instruction manipulation capabilities to process complex instructions by less bytes and execute instructions at higher speed.
It includes a multiplier and DMAC adequate for office automation, communication devices and industrial
equipments, and other high-speed processing applications.
1.1 Applications
Automobiles, audio, cameras, office equipment, communications equipment, portable equipment, etc.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 1
of 488
1. Overview
M32C/83 Group (M32C/83, M32C/83T)
1.2 Performance Overview
Tables 1.1 and 1.2 list performance overview of the M32C/83 Group (M32C/83, M32C/83T).
Table 1.1 M32C/83 Group (M32C/83, M32C/83T) Performance (144-Pin Package)
Characteristic
CPU
Basic Instructions
Performance
M32C/83
108 instructions
M32C/83T
Minimum Instruction Execution Time 31.3 ns (f(BCLK)=32 MHz, VCC=4.2 to 5.5 V)(3) 31.3 ns (f(BCLK)=32 MHz, VCC=4.2 to 5.5 V)(3)
50 ns (f(BCLK)=20 MHz, VCC=3.0 to 5.5 V)
Operating Mode
Address Space
Memory Capacity
Peripheral I/O Port
Function Multifunction Timer
Intelligent I/O
Serial I/O
CAN Module
A/D Converter
D/A Converter
DMAC
DMAC II
DRAM
CRC Calculation Circuit
X/Y Converter
Watchdog Timer
Interrupt
Clock Generation Circuit
Oscillation Stop Detect Function
Electrical Supply Voltage
Characteristics
Power Consumption
Flash
Program/Erase Supply Voltage
Memory Program and Erase Endurance
Operating Ambient Temperature
Package
Single-chip mode, Memory expansion
Single-chip mode
mode and Microprocessor mode
16 Mbytes
See Table 1.3
123 I/O pins and 1 input pin
Timer A: 16 bits x 5 channels, Timer B: 16 bits x 6 channels
Three-phase motor control circuit
Time measurement function: 16 bits x 12 channels
Waveform generating function: 16 bits x 28 channels
Communication function (Clock synchronous serial I/O, Clock asynchronous serial I/O, HDLC data processing, Clock synchronous variable length serial I/O,
IEBus(1), 8-bit or 16-bit Clock synchronous serial I/O)
5 Channels
Clock synchronous serial I/O, Clock asynchronous serial I/O, IEBus(1), I2C bus(2)
1 channel Supporting CAN 2.0B specification
10-bit A/D converter: 2 circuit, 34 channels
8 bits x 2 channels
4 channels
Can be activated by all peripheral function interrupt sources
Immediate transfer, Calculation transfer and Chain transfer functions
CAS before RAS refresh, Self-reflesh, EDO, EP
CRC-CCITT
16 bits x 16 bits
15 bits x 1 channel (with prescaler)
42 internal and 8 external sources, 5 software sources, Interrupt priority level: 7
4 circuits
Main clock oscillation circuit(*), Sub clock oscillation circuit(*), On-chip oscillator,
PLL frequency synthesizer
(*)Equipped with a built-in feedback resistor. Ceramic resonator or crystal oscillator must be connected externally
Main clock oscillation stop detect function
4.2 to 5.5 V (f(BCLK)=32 MHz)
4.2 to 5.5 V (f(BCLK)=32 MHz)
3.0 to 5.5 V (f(BCLK)=20 MHz, through VDC)
3.0 to 3.6 V (f(BCLK)=20 MHz,
not through VDC)
41 mA (VCC=5 V, f(BCLK)=32 MHz)
41 mA (VCC=5 V, f(BCLK)=32 MHz)
38 mA (VCC=5 V, f(BCLK)=30 MHz)
38 mA (VCC=5 V, Vf(BCLK)=30 MHz)
26 mA (VCC=3.3 V, f(BCLK)=20 MHz)
470 µA (VCC=5 V, f(XCIN)=32 kHz,
470 µA (VCC=5 V, f(XCIN)=32 kHz,
in wait mode)
in wait mode)
0.4 µA (VCC=5 V, stop mode)
340 µA (VCC=3.3 V, f(XCIN)=32 kHz,
through VDC, in wait mode)
5.0 µA (VCC=3.3 V, f(XCIN)=32 kHz,
not through VDC, in wait mode)
0.4 µA (VCC=5 V, stop mode)
0.4 µA (VCC=3.3 V, stop mode)
3.3 ± 0.3 V or 5.0 ± 0.5 V
5.0 ± 0.5 V
100 times
–20 to 85oC, –40 to 85oC (optional)
–40 to 85oC (T version)
144-pin plastic molded LQFP
NOTES:
1. IEBus is a trademark of NEC Electronics Corporation.
2. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
3. Contact our sales office if 30-MHz or higher frequency is required.
All options are on a request basis.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 2 of 488
1. Overview
M32C/83 Group (M32C/83, M32C/83T)
Table 1.2 M32C/83 Group (M32C/83, M32C/83T) Performance (100-Pin Package)
Characteristic
Performance
M32C/83
CPU
Basic Instructions
Minimum Instruction Execution Time
Operating Mode
Peripheral
Function
Address Space
Memory Capacity
I/O Port
Multifunction Timer
Intelligent I/O
Serial I/O
CAN Module
A/D Converter
D/A Converter
DMAC
DMAC II
CRC Calculation Circuit
X/Y Converter
Watchdog Timer
Interrupt
Clock Generation Circuit
Oscillation Stop Detect Function
Electrical Supply Voltage
Characteristics
Power Consumption
Flash
Program/Erase Supply Voltage
Memory Program and Erase Endurance
Operating Ambient Temperature
Package
M32C/83T
108 instructions
31.3 ns (f(BCLK) = 32 MHz, VCC = 4.2 to 5.5 V)
31.3 ns (f(BCLK) = 32 MHz, V CC=4.2 to 5.5 V)
50 ns (f(BCLK) = 20 MHz, VCC = 3.0 to 5.5 V)
Single-chip mode, Memory expansion
Single-chip mode
mode and Microprocessor mode
16 Mbytes
See Table 1.3
87 I/O pins and 1 input pin
Timer A: 16 bits x 5 channels, Timer B: 16 bits x 6 channels
Three-phase motor control circuit
Time measurement function: 16 bits x 5 channels
Waveform generating function: 16 bits x 10 channels
Communication function (Clock synchronous serial I/O, Clock asynchronous serial I/O, HDLC data processing, Clock synchronous variable length serial I/O,
IEBus(1))
5 Channels
Clock synchronous serial I/O, Clock asynchronous serial I/O, IEBus(1), I2C bus(2)
1 channel Supporting CAN 2.0B specification
10-bit A/D converter: 2 circuits, 26 channels
8 bits x 2 channels
4 channels
Can be activated by all peripheral function interrupt sources
Immediate transfer, Calculation transfer and Chain transfer functions
CRC-CCITT
16 bits x 16 bits
15 bits x 1 channel (with prescaler)
42 internal and 8 external sources, 5 software sources
Interrupt priority level: 7
4 circuits
Main clock oscillation circuit(*), Sub clock oscillation circuit(*), On-chip oscillator,
PLL frequency synthesizer
(*)Equipped with a built-in feedback resistor. Ceramic resonator or crystal oscillator
must be connected externally
Main clock oscillation stop detect function
4.2 to 5.5 V (f(BCLK)=32 MHz)
4.2 to 5.5 V (f(BCLK)=32 MHz)
3.0 to 5.5 V (f(BCLK)=20 MHz, through VDC)
3.0 to 3.6 V (f(BCLK)=20 MHz, not through VDC)
41 mA (VCC=5 V, f(BCLK)=32 MHz)
41 mA (VCC=5 V, f(BCLK)=32 MHz)
38 mA (VCC=5 V, f(BCLK)=30 MHz)
38 mA (VCC=5 V, Vf(BCLK)=30 MHz)
26 mA (VCC=3.3 V, f(BCLK)=20 MHz)
470 µA (VCC=5 V, f(XCIN)=32 kHz,
in wait mode)
470 µA (VCC=5 V, f(XCIN)=32 kHz,
in wait mode)
0.4 µA (VCC=5 V, stop mode)
340 µA (VCC=3.3 V, f(XCIN)=32 kHz,
through VDC, in wait mode)
5.0 µA (VCC=3.3 V, f(XCIN)=32 kHz,
not through VDC, in wait mode)
0.4 µA (VCC=5 V, stop mode)
0.4 µA (VCC=3.3 V, stop mode)
3.3 ± 0.3 V or 5.0 ± 0.5 V
5.0 ± 0.5 V
100 times
–20 to 85oC, –40 to 85oC (optional)
–40 to 85oC (T version)
100-pin plastic molded LQFP/QFP
NOTES:
1. IEBus is a trademark of NEC Electronics Corporation.
2. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
3. Contact our sales office if 30-MHz or higher frequency is required.
All options are on a request basis.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 3 of 488
1. Overview
M32C/83 Group (M32C/83, M32C/83T)
1.3 Block Diagram
Figure 1.1 shows a block diagram of the M32C/83 Group (M32C/83, M32C/83T) microcomputer.
8
8
8
8
8
8
8
8
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Port P7
Peripheral Functions
A/D Converter:
2 circuits
Standard: 18 inputs(2)
Maximum: 34 inputs(2)
Timer (16 bits)
Timer A: 5 channels
Timer B: 6 channels
Clock Generation Circuit
XIN - XOUT
XCIN - XCOUT
On-chip Oscillator
PLL Frequency Synthesizer
Three-phase Motor Control Circuit
UART/Clock Synchronous Serial I/O:
5 channels
DMAC
Watchdog Timer (15 bits)
X/Y Converter:
16 bits x 16 bits
DMACII
D/A Converter
(8 bits x 2 channels)
CRC Calculation Circuit (CCITT):
X16+X12+X5+1
Intelligent I/O
( 4 Groups )
Time Measurement: 12 channels(2)
Wave Generating: 28 channels(2)
Communication Functions:
Clock Synchronous Serial I/O, UART,
IEBus, HDLC Data Processing, 8-bit or
16-bit Clock Synchronous Serial I/O(3)
M32C/80 Series CPU Core
R0H
R0L
R1H
R1L
8
Port P14
7
Port P13
8
Port P12
ISP
R3
USP
SVF
FB
SVP
SB
VCT
Port P11
8
5
Port P10
8
NOTES:
1. Ports P11 to P15 are provided only in the 144-pin package.
2. Included only in the 144-pin package.
3. Can be used only in the 144-pin package.
Figure 1.1 M32C/83 Group (M32C/83, M32C/83T) Block Diagram
Page 4 of 488
RAM
PC
(Note1)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
ROM
INTB
A1
CAN Module
Memory
FLG
R2
A0
Port P15
DRAMC
Multiplier
Port P9
8
P85
Port P8
7
1. Overview
M32C/83 Group (M32C/83, M32C/83T)
1.4 Product Information
Table 1.3 lists the product information. Figure 1.2 shows the product numbering system.
Table 1.3 M32C/83 Group (1) (M32C/83)
Type Number
Package Type
M30835FJGP
PLQP0144KA-A (144P6Q-A)
M30833FJGP
PLQP0100KB-A (100P6Q-A)
M30833FJFP
PRQP0100JB-A (100P6S-A)
As of January, 2006
ROM
Capacity
RAM
Capacity
Remarks
512K
31K
Flash Memory
Table 1.3 M32C/83 Group (2) (T Version, M32C/83T)
Type Number
Package Type
M30833FJTGP
As of January, 2006
ROM
Capacity
PLQP0100KB-A (100P6Q-A)
RAM
Capacity
Remarks
31K
Flash Memory
T Version
(High-reliability
85oC Version)
512K
Please contact our sales office for V version information.
M30 83 3 F J
GP
Package Type:
FP = Package PRQP0100JB-A (100P6S-A)
GP = Package PLQP0100KB-A (100P6Q-A)
Package PLQP0144KA-A (144P6Q-A)
Classification:
Blank = General Industrial Use
T = T Version
ROM Capacity:
J = 512 Kbytes
Memory Type:
F = Flash Memory Version
RAM Capacity, Pin Count, etc.
(Value itself has no specific meaning)
M32C/83 Group
M16C Family
Figure 1.2 Product Numbering System
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 5 of 488
1. Overview
M32C/83 Group (M32C/83, M32C/83T)
1.5 Pin Assignment
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
109
72
110
71
111
70
112
69
113
68
114
67
115
66
116
65
117
64
118
63
119
62
120
61
121
60
122
59
123
58
M32C/83 GROUP
(M32C/83, M32C/83T)
124
125
126
127
57
56
55
54
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
P44 / CS3 / A20 (MA12)
P45 / CS2 / A21
P46 / CS1 / A22
P47 / CS0 / A23
P125 / OUTC35
P126 / OUTC36
P127 / OUTC37
P50 / WRL / WR / CASL
P51 / WRH / BHE / CASH
P52 / RD / DW
P53 / CLKOUT / BCLK / ALE
P130 / OUTC24
P131 / OUTC25
Vcc
P132 / OUTC26
Vss
P133 / OUTC23
P54 / HLDA / ALE
P55 / HOLD
P56 / ALE / RAS
P57 / RDY
P134 / OUTC20 / ISTxD2 / IEOUT
P135 / OUTC22 / ISRxD2 / IEIN
P136 / OUTC21 / ISCLK2
P137 / OUTC27
P60 / CTS0 / RTS0 / SS0
P61 / CLK0
P62 / RxD0 / SCL0 / STxD0
P63 / TxD0 / SDA0 / SRxD0
P64(1)
P65 / CLK1
Vss
P66 / RxD1 / SCL1 / STxD1
Vcc
P67 / TxD1 / SDA1 / SRxD1
P70(2, 3)
SRxD4 / SDA4 / TxD4 / ANEX1 / P96
CLK4 / ANEX0 / P95
SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94
SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93
IEOUT / ISTxD2 / OUTC20 / SRxD3 / SDA3 / TxD3 / TB2IN / P92
IEIN / ISRxD2 / STxD3 / SCL3 / RxD3 / TB1IN / P91
CLK3 / TB0IN / P90
P146
P145
P144
OUTC17 / INPC17 / P143
OUTC16 / INPC16 / P142
OUTC15 / P141
OUTC14 / P140
BYTE
CNVss
VCONT / XCIN / P87
XCOUT / P86
RESET
XOUT
Vss
XIN
Vcc
NMI / P85
INT2 / P84
CANIN / INT1 / P83
ISRxD3 / OUTC32 / CANOUT / INT0 / P82
ISTxD3 / OUTC30 / U / TA4IN / P81
BE0IN / ISRxD0 / INPC02 / U / TA4OUT / P80
CANIN / ISCLK0 / OUTC01 / INPC01 / TA3IN / P77
CANOUT / BE0OUT / ISTxD0 / OUTC00 / INPC00 / TA3OUT / P76
BE1IN / ISRxD1 / OUTC12 / INPC12 / W / TA2IN / P75
ISCLK1 / OUTC11 / INPC11 / W / TA2OUT / P74
BE1OUT / ISTxD1 / OUTC10 / SS2 / RTS2 / CTS2 / V / TA1IN / P73
CLK2 / V / TA1OUT / P72
(3)
IEIN / ISRxD2 / OUTC22 / STxD2 / SCL2 / RxD2 / TA0IN / TB5IN / P71
19
37
18
38
144
17
39
143
16
40
142
15
41
141
14
42
140
13
43
139
12
44
138
11
45
137
10
46
136
9
47
135
8
48
134
7
49
133
6
50
132
5
51
131
4
52
130
3
53
129
2
128
1
D8 / P10
AN07 / D7 / P07
AN06 / D6 / P06
AN05 / D5 / P05
AN04 / D4 / P04
P114
OUTC13 / P113
BE1IN / ISRxD1 / OUTC12 / INPC12 / P112
ISCLK1 / OUTC11 / INPC11 / P111
BE1OUT / ISTxD1 / OUTC10 / P110
AN03 / D3 / P03
AN02 / D2 / P02
AN01 / D1 / P01
AN00 / D0 / P00
INPC07 / AN157 / P157
INPC06 / AN156 / P156
OUTC05 / INPC05 / AN155 / P155
OUTC04 / INPC04 / AN154 / P154
INPC03 / AN153 / P153
BE0IN / ISRxD0 / INPC02 / AN152 / P152
ISCLK0 / OUTC01 / INPC01 / AN151 / P151
Vss
BE0OUT / ISTxD0 / OUTC00 / INPC00 / AN150 / P150
Vcc
KI3 / AN7 / P107
KI2 / AN6 / P106
KI1 / AN5 / P105
KI0 / AN4 / P104
AN3 / P103
AN2 / P102
AN1 / P101
AVss
AN0 / P100
VREF
AVcc
STxD4 / SCL4 / RxD4 / ADTRG / P97
107
108
P11 / D9
P12 / D10
P13 / D11
P14 / D12
P15 / D13 / INT3
P16 / D14 / INT4
P17 / D15 / INT5
P20 / A0 ( / D0 ) / AN20
P21 / A1 ( / D1 ) / AN21
P22 / A2 ( / D2 ) / AN22
P23 / A3 ( / D3 ) / AN23
P24 / A4 ( / D4 ) / AN24
P25 / A5 ( / D5 ) / AN25
P26 / A6 ( / D6 ) / AN26
P27 / A7 ( / D7 ) / AN27
Vss
P30 / A8 ( MA0 ) ( / D8 )
Vcc
P120 / OUTC30 / ISTxD3
P121 / OUTC31 / ISCLK3
P122 / OUTC32 / ISRxD3
P123 / OUTC33
P124 / OUTC34
P31 / A9 ( MA1 ) ( / D9 )
P32 / A10 ( MA2 ) ( / D10 )
P33 / A11 ( MA3 ) ( / D11 )
P34 / A12 ( MA4 ) ( / D12 )
P35 / A13 ( MA5 ) ( / D13 )
P36 / A14 ( MA6 ) ( / D14 )
P37 / A15 ( MA7 ) ( / D15 )
P40 / A16 ( MA8 )
P41 / A17 ( MA9 )
Vss
P42 / A18 ( MA10 )
Vcc
P43 / A19 ( MA11 )
Figures 1.3 to 1.5 show pin assignments (top view).
NOTES:
1. P64 / CTS1 / RTS1 / SS1 / OUTC21 / ISCLK2
2. P70 / TA0OUT / TxD2 / SDA2 / SRxD2 / OUTC20 / ISTxD2 / IEOUT
3. P70 and P71 are ports for the N-channel open drain output.
Figure 1.3 Pin Assignment for 144-Pin Package
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 6 of 488
PLQP0144KA-A
(144P6Q-A)
1. Overview
M32C/83 Group (M32C/83, M32C/83T)
Table 1.4 Pin Characteristics for 144-Pin Package
Pin
No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Control
Pin
Port
Interrupt
Timer Pin
Pin
P96
P95
P94
TB4IN
P93
TB3IN
P92
P91
TB2IN
TB1IN
P90
TB0IN
UART/CAN Pin
TxD4/SDA4/SRxD4
CLK4
CTS4/RTS4/SS4
CTS3/RTS3/SS3
TxD3/SDA3/SRxD3
RxD3/SCL3/STxD3
CLK3
Intelligent I/O Pin
ANEX1
ANEX0
DA1
DA0
OUTC20/IEOUT/ISTxD2
IEIN/ISRxD2
P146
P145
P144
P143
INPC17/OUTC17
P142
P141
INPC16/OUTC16
P140
OUTC14
OUTC15
BYTE
CNVSS
XCIN/VCONT
XCOUT
P87
P86
RESET
XOUT
VSS
XIN
VCC
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39 VCC
40
41 VSS
42
43
44
45
P85
P84
P83
P82
P81
NMI
INT2
INT1
INT0
CANIN
CANOUT
OUTC32/ISRxD3
OUTC30/ISTxD3
INPC02/ISRxD0/BE0IN
P80
TA4IN/U
TA4OUT/U
P77
TA3IN
CANIN
INPC01/OUTC01/ISCLK0
P76
P75
P74
TA3OUT
TA2IN/W
TA2OUT/W
CANOUT
INPC00/OUTC00/ISTxD0/BE0OUT
INPC12/OUTC12/ISRxD1/BE1IN
P73
TA1IN/V
TA1OUT/V
P67
CTS2/RTS2/SS2
CLK2
RxD2/SCL2/STxD2
TxD2/SDA2/SRxD2
TxD1/SDA1/SRxD1
P66
RxD1/SCL1/STxD1
P65
P64
P63
P62
CLK1
CTS1/RTS1/SS1
TxD0/SDA0/SRxD0
RxD0/SCL0/STxD0
CLK0
CTS0/RTS0/SS0
P72
P71
P70
TB5IN/TA0IN
TA0OUT
P61
46
P60
47
P137
48
NOTES:
1. Bus control pins in M32C/83T cannot be used.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 7 of 488
Analog
Pin
INPC11/OUTC11/ISCLK1
OUTC10/ISTxD1/BE1OUT
OUTC22/ISRxD2/IEIN
OUTC20/ISTxD2/IEOUT
OUTC21/ISCLK2
OUTC27
Bus Control Pin(1)
1. Overview
M32C/83 Group (M32C/83, M32C/83T)
Table 1.4 Pin Characteristics for 144-Pin Package (Continued)
Pin
No
Control
Pin
Port
Interrupt
Pin
Timer Pin
UART/CAN Pin
49
P136
P135
50
P134
51
P57
52
P56
53
P55
54
P54
55
P133
56
57 VSS
P132
58
59 VCC
P131
60
P130
61
P53
62
P52
63
P51
64
P50
65
P127
66
P126
67
P125
68
P47
69
P46
70
P45
71
P44
72
P43
73
74 VCC
P42
75
76 VSS
P41
77
P40
78
P37
79
P36
80
P35
81
P34
82
P33
83
P32
84
P31
85
P124
86
P123
87
P122
88
P121
89
P120
90
91 VCC
P30
92
93 VSS
P27
94
P26
95
P25
96
NOTES:
1. Bus control pins in M32C/83T cannot be used.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 8 of 488
Intelligent I/O Pin
Analog
Pin
Bus Control Pin(1)
OUTC21/ISCLK2
OUTC22/ISRxD2/IEIN
OUTC20/ISTxD2/IEOUT
RDY
ALE/RAS
HOLD
HLDA/ALE
OUTC23
OUTC26
OUTC25
OUTC24
CLKOUT/BCLK/ALE
RD/DW
WRH/BHE/CASH
WRL/WR/CASL
OUTC37
OUTC36
OUTC35
CS0/A23
CS1/A22
CS2/A21
CS3/A20(MA12)
A19(MA11)
A18(MA10)
A17(MA9)
A16(MA8)
A15(MA7)(/D15)
A14(MA6)(/D14)
A13(MA5)(/D13)
A12(MA4)(/D12)
A11(MA3)(/D11)
A10(MA2)(/D10)
A9(MA1)(/D9)
OUTC34
OUTC33
OUTC32/ISRxD3
OUTC31/ISCLK3
OUTC30/ISTxD3
A8(MA0)(/D8)
AN27
AN26
AN25
A7(/D7)
A6(/D6)
A5(/D5)
1. Overview
M32C/83 Group (M32C/83, M32C/83T)
Table 1.4 Pin Characteristics for 144-Pin Package (Continued)
Pin
No
Control
Pin
97
98
99
100
101
Analog
Pin
Bus Control Pin(1)
P24
AN24
P23
P22
P21
AN23
AN22
AN21
A4(/D4)
A3(/D3)
Port
Interrupt
Pin
Timer Pin
UART/CAN Pin
Intelligent I/O Pin
P20
AN20
A2(/D2)
A1(/D1)
A0(/D0)
102
103
104
105
P17
P16
P15
P14
D12
106
107
108
P13
P12
D11
D10
P11
P10
D9
D8
109
110
111
112
D15
INT5
INT4
D14
D13
INT3
P07
P06
P05
AN07
AN06
AN05
D7
D6
D5
113
114
115
P04
AN04
D4
P114
P113
OUTC13
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130 VSS
131
132 VCC
133
P112
P111
P110
INPC12/OUTC12/ISRxD1/BE1IN
INPC11/OUTC11/ISCLK1
OUTC10/ISTxD1/BE1OUT
P03
P02
AN03
AN02
D3
D2
P01
P00
P157
P156
P155
P154
P153
P152
D1
D0
INPC07
INPC06
INPC05/OUTC05
INPC04/OUTC04
INPC03
INPC02/ISRxD0/BE0IN
AN01
AN00
AN157
AN156
AN155
AN154
AN153
AN152
P151
INPC01/OUTC01/ISCLK0
AN151
P150
INPC00/OUTC00/ISTxD0/BE0OUT
AN150
134
135
136
137
138
139
P107
P106
KI3
KI2
AN7
AN6
P105
P104
KI1
KI0
AN5
AN4
P103
P102
AN3
AN2
P101
140 AVSS
141
P100
142 VREF
143 AVCC
RxD4/SCL4/STxD4
144
P97
NOTES:
1. Bus control pins in M32C/83T cannot be used.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 9 of 488
AN1
AN0
ADTRG
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
NOTES:
1. P64 / CTS1 / RTS1 / SS1 / OUTC21 / ISCLK2
2. P97 / ADTRG / RxD4 / STxD4 / SCL4
3. P70 and P71 are ports for the N-channel open drain output.
Figure 1.4 Pin Assignment for 100-Pin Package
Page 10 of 488
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93
IEOUT / ISTxD2 / OUTC20 / SRxD3 / SDA3 / TxD3 / TB2IN / P92
IEIN / ISRxD2 / STxD3 / SCL3 / RxD3 / TB1IN / P91
CLK3 / TB0IN / P90
BYTE
CNVss
VCONT / XCIN / P87
XCOUT / P86
RESET
XOUT
Vss
XIN
Vcc
NMI / P85
INT2 / P84
CANIN / INT1 / P83
ISRxD3 / OUTC32 / CANOUT / INT0 / P82
ISTxD3 / OUTC30 / U / TA4IN / P81
BE0IN / ISRxD0 /INPC02 / U / TA4OUT / P80
CANIN / ISCLK0 / OUTC01 / INPC01 / TA3IN / P77
CANOUT / BE0OUT / ISTxD0 / OUTC00 / INPC00 / TA3OUT / P76
BE1IN / ISRxD1 / OUTC12 / INPC12 / W / TA2IN / P75
ISCLK1 / OUTC11 / INPC11 / W / TA2OUT / P74
BE1OUT / ISTxD1 / OUTC10 / SS2 / RTS2 / CTS2 / V / TA1IN / P73
CLK2 / V / TA1OUT / P72
(3)IEOUT
/ ISTxD2 / OUTC20 / SRxD2 / SDA2 / TxD2 / TA0OUT / P70
30
29
3
SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94
/ ISRxD2 / OUTC22 / STxD2 / SCL2 / RxD2 / TA0IN / TB5IN / P71
2
CLK4 / ANEX0 / P95
(3)IEIN
1
SRxD4 / SDA4 / TxD4 / ANEX1 / P96
P30 / A8 ( MA0 ) ( / D8 )
Vcc
P31 / A9 ( MA1 ) ( / D9 )
P32 / A10 ( MA2 ) ( / D10 )
P33 / A11 ( MA3 ) ( / D11 )
63
62
61
60
59
P40 / A16 ( MA8 )
P41 / A17 ( MA9 )
P42 / A18 ( MA10 )
P43 / A19 ( MA11 )
54
53
52
51
P37 / A15 ( MA7 ) ( / D15 )
Vss
64
P36 / A14 ( MA6 ) ( / D14 )
P27 / A7 ( / D7 ) / AN27
65
55
P26 / A6 ( / D6 ) / AN26
66
56
P25 / A5 ( / D5 ) / AN25
67
P34 / A12 ( MA4 ) ( / D12 )
P24 / A4 ( / D4 ) / AN24
68
P35 / A13 ( MA5 ) ( / D13 )
P23 / A3 ( / D3 ) / AN23
69
57
P22 / A2 ( / D2 ) / AN22
70
58
P20 / A0 ( / D0 ) / AN20
P21 / A1 ( / D1 ) / AN21
71
P17 / D15 / INT5
72
73
P14 / D12
76
P15 / D13 / INT3
P13 / D11
77
P16 / D14 / INT4
P12 / D10
78
74
P11 / D9
79
75
P10 / D8
80
M32C/83 Group (M32C/83, M32C/83T)
1. Overview
D7 / AN07 / P07
81
50
P44 / CS3 / A20 (MA12)
D6 / AN06 / P06
82
49
P45 / CS2 / A21
D5 / AN05 / P05
83
48
P46 / CS1 / A22
D4 / AN04 / P04
84
47
P47 / CS0 / A23
D3 / AN03 / P03
85
46
P50 / WRL / WR / CASL
D2 / AN02 / P02
86
45
P51 / WRH / BHE / CASH
D1 / AN01 / P01
87
44
P52 / RD / DW
D0 / AN00 / P00
88
43
P53 / CLKOUT / BCLK / ALE
KI3 / AN7 / P107
89
42
P54 / HLDA / ALE
KI2 / AN6 / P106
90
41
P55 / HOLD
KI1 / AN5 / P105
91
40
P56 / ALE / RAS
KI0 / AN4 / P104
92
39
P57 / RDY
AN3 / P103
93
38
P60 / CTS0 / RTS0 / SS0
AN2 / P102
94
37
P61 / CLK0
AN1 / P101
95
36
P62 / RxD0 / SCL0 / STxD0
AVss
96
35
P63 / TxD0 / SDA0 / SRxD0
AN0 / P100
97
34
P64(1)
VREF
98
33
P65 / CLK1
AVcc
99
32
P66 / RxD1 / SCL1 / STxD1
(2)P97
100
31
P67 / TxD1 / SDA1 / SRxD1
M32C/83 GROUP
(M32C/83, M32C/83T)
PRQP0100JB-A
(100P6S-A)
1. Overview
P33 / A11 ( MA3 ) ( / D11 )
57
P40 / A16 ( MA8 )
P32 / A10 ( MA2 ) ( / D10 )
58
P41 / A17 ( MA9 )
P31 / A9 ( MA1 ) ( / D9 )
59
51
Vcc
60
P37 / A15 ( MA7 ) ( / D15 )
P30 / A8 ( MA0 ) ( / D8 )
61
52
Vss
62
P36 / A14 ( MA6 ) ( / D14 )
P27 / A7 ( / D7 ) / AN27
63
53
P26 / A6 ( / D6 ) / AN26
64
54
P25 / A5 ( / D5 ) / AN25
65
P34 / A12 ( MA4 ) ( / D12 )
P24 / A4 ( / D4 ) / AN24
66
P35 / A13 ( MA5 ) ( / D13 )
P23 / A3 ( / D3 ) / AN23
67
55
P22 / A2 ( / D2 ) / AN22
68
56
P20 / A0 ( / D0 ) / AN20
P21 / A1 ( / D1 ) / AN21
69
P17 / D15 / INT5
71
70
P15 / D13 / INT3
P16 / D14 / INT4
72
P14 / D12
74
73
P13 / D11
75
M32C/83 Group (M32C/83, M32C/83T)
D10 / P12
76
50
D9 / P11
77
49
P43 / A19 ( MA11 )
D8 / P10
78
48
P44 / CS3 / A20 (MA12)
D7 / AN07 / P07
79
47
P45 / CS2 / A21
D6 / AN06 / P06
80
46
P46 / CS1 / A22
D5 / AN05 / P05
81
45
P47 / CS0 / A23
D4 / AN04 / P04
82
44
P50 / WRL / WR / CASL
D3 / AN03 / P03
83
43
P51 / WRH / BHE / CASH
D2 / AN02 / P02
84
42
P52 / RD / DW
D1 / AN01 / P01
85
41
P53 / CLKOUT / BCLK / ALE
D0 / AN00 / P00
86
40
P54 / HLDA / ALE
KI3 / AN37 / P107
87
39
P55 / HOLD
KI2 / AN36 / P106
88
38
P56 / ALE / RAS
KI1 / AN35 / P105
89
37
P57 / RDY
KI0 / AN34 / P104
90
36
P60 / CTS0 / RTS0 / SS0
AN33 / P103
91
35
P61 / CLK0
AN32 / P102
92
34
P62 / RxD0 / SCL0 / STxD0
AN31 / P101
93
33
P63 / TxD0 / SDA0 / SRxD0
AVss
94
32
P64(1)
AN30 / P100
95
31
P65 / CLK1
VREF
96
30
P66 / RxD1 / SCL1 / STxD1
M32C/83 GROUP
(M32C/83, M32C/83T)
P42 / A18 ( MA10 )
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
CNVss
VCONT / XCIN / P87
XCOUT / P86
RESET
XOUT
Vss
XIN
Vcc
NMI / P85
INT2 / P84
CANIN / INT1 / P83
ISRxD3 / OUTC32 / CANOUT / INT0 / P82
ISTxD3 / OUTC30 / U / TA4IN / P81
BE0IN / ISRxD0 /INPC02 / U / TA4OUT / P80
CANIN / ISCLK0 / OUTC01 / INPC01 / TA3IN / P77
CANOUT / BE0OUT / ISTxD0 / OUTC00 / INPC00 / TA3OUT / P76
BE1IN / ISRxD1 / OUTC12 / INPC12 / W / TA2IN / P75
ISCLK1 / OUTC11 / INPC11 / W / TA2OUT / P74
BE1OUT / ISTxD1 / OUTC10 / SS2 / RTS2 / CTS2 / V / TA1IN / P73
P72 / TA1OUT / V / CLK2
BYTE
26
CLK3 / TB0IN / P90
100
4
P71(3, 4)
CLK4 / ANEX0 / P95
IEIN/ ISRxD2 / STxD3 / SCL3 / RxD3 / TB1IN / P91
27
3
99
IEOUT/ ISTxD2 / OUTC20 / SRxD3 / SDA3 / TxD3 / TB2IN / P92
P70(2, 4)
SRxD4 / SDA4 / TxD4 / ANEX1 / P96
2
P67 / TxD1 / SDA1 / SRxD1
28
1
29
98
SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93
97
SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94
AVcc
STxD4 / SCL4 / RxD4 / ADTRG / P97
NOTES:
1. P64 / CTS1 / RTS1 / SS1 / OUTC21 / ISCLK2
2. P70 / TA0OUT / TxD2 / SDA2 / SRxD2 / OUTC20 / ISTxD2 / IEOUT
3. P71 / TA0IN / TB5IN / RxD2 / SCL2 / STxD2 / OUTC22 / ISRxD2 / IEIN
4. P70 and P71 are ports for the N-channel open drain output.
Figure 1.5 Pin Assignment for 100-Pin Package
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 11 of 488
PLQP0100KB-A
(100P6Q-A)
1. Overview
M32C/83 Group (M32C/83, M32C/83T)
Table 1.5 Pin Characteristics for 100-Pin Package
Package
Pin No
FP GP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Control
Pin
Port
Interrupt
Pin
Timer Pin
UART/CAN Pin
99
P96
TxD4/SDA4/SRxD4
100
1
2
3
P95
CLK4
CTS4/RTS4/SS4
4
5
6 BYTE
7 CNVSS
8 XCIN/VCONT
9 XCOUT
10 RESET
11 XOUT
12 VSS
13 XIN
14 VCC
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
P94
P93
TB4IN
TB3IN
P92
TB2IN
P91
P90
TB1IN
TB0IN
ANEX1
ANEX0
DA1
DA0
OUTC20/IEOUT/ISTxD2
IEIN/ISRxD2
P86
P85
P84
P83
P82
P81
P80
NMI
INT2
INT1
INT0
CANIN
CANOUT
P77
TA4IN/U
TA4OUT/U
TA3IN
P76
TA3OUT
P75
P74
P73
P72
TA2IN/W
TA2OUT/W
TA1IN/V
TA1OUT/V
P71
P70
TB5IN/TA0IN
TA0OUT
P67
P66
P65
P64
P63
P62
P61
39
40
P55
45
46
47
48
Analog Bus Control Pin(1)
Pin
P87
34
35
36
37
38
41
42
43
44
CTS3/RTS3/SS3
TxD3/SDA3/SRxD3
RxD3/SCL3/STxD3
CLK3
Intelligent I/O Pin
P60
P57
P56
OUTC32/ISRxD3
OUTC30/ISTxD3
INPC02/ISRxD0/BE0IN
CANIN
CANOUT
CTS2/RTS2/SS2
CLK2
RxD2/SCL2/STxD2
TxD2/SDA2/SRxD2
TxD1/SDA1/SRxD1
RxD1/SCL1/STxD1
CLK1
CTS1/RTS1/SS1
TxD0/SDA0/SRxD0
RxD0/SCL0/STxD0
CLK0
CTS0/RTS0/SS0
INPC01/OUTC01/ISCLK0
INPC00/OUTC00/ISTxD0/BE0OUT
INPC12/OUTC12/ISRxD1/BE1IN
INPC11/OUTC11/ISCLK1
OUTC10/ISTxD1/BE1OUT
OUTC22/ISRxD2/IEIN
OUTC20/ISTxD2/IEOUT
OUTC21/ISCLK2
RDY
ALE/RAS
HOLD
HLDA/ALE
P54
P53
CLKOUT/BCLK/ALE
P52
P51
P50
RD/DW
WRH/BHE/CASH
P47
P46
WRL/WR/CASL
CS0/A23
CS1/A22
P45
CS2/A21
P44
CS3/A20(MA12)
NOTES:
1. Bus control pins in M32C/83T cannot be used.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 12 of 488
1. Overview
M32C/83 Group (M32C/83, M32C/83T)
Table 1.5 Pin Characteristics for 100-Pin Package (Continued)
Package
Pin No
Control
Pin
Port
Interrupt
Pin
Timer Pin
UART/CAN Pin
Intelligent I/O Pin
Analog
Pin
Bus Control Pin(1)
FP GP
51
52
53
54
55
56
57
58
59
60
61
62
63
64
49
50
51
52
53
54
55
56
57
58
59
60
61
62
65
66
67
68
69
70
71
72
73
74
75
76
77
63
64
65
66
67
68
69
70
71
72
73
74
75
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
P43
P42
P41
P40
P37
P36
P35
P34
P33
P32
P31
A19(MA11)
A18(MA10)
A17(MA9)
A16(MA8)
A15(MA7)(/D15)
A14(MA6)(/D14)
A13(MA5)(/D13)
A12(MA4)(/D12)
A11(MA3)(/D11)
A10(MA2)(/D10)
A9(MA1)(/D9)
P30
A8(MA0)(/D8)
VCC
VSS
P27
P26
P25
P24
P23
P22
P21
P20
P17
P16
P15
P14
P13
P12
P11
P10
P07
P06
P05
P04
P03
P02
P01
P00
P107
P106
P105
P104
P103
P102
P101
AN27
AN26
AN25
AN24
AN23
AN22
AN21
AN20
INT5
INT4
INT3
AN07
AN06
AN05
AN04
AN03
AN02
AN01
AN00
AN7
AN6
AN5
AN4
AN3
AN2
AN1
KI3
KI2
KI1
KI0
AVSS
P100
AN0
VREF
AVCC
P97
RxD4/SCL4/STxD4
NOTES:
1. Bus control pins in M32C/83T cannot be used.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 13 of 488
ADTRG
A7(/D7)
A6(/D6)
A5(/D5)
A4(/D4)
A3(/D3)
A2(/D2)
A1(/D1)
A0(/D0)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1. Overview
M32C/83 Group (M32C/83, M32C/83T)
1.6 Pin Description
Table 1.6 Pin Description (100-Pin and 144-Pin Packages)
Classsfication
Symbol
I/O Type
Function
Power Supply
VCC
I
Apply 3.0 to 5.5V to both VCC pin.
Apply 0V to the VSS pin. (1)
Analog Power
VSS
AVCC
I
Supply
Reset Input
AVSS
____________
RESET
Supplies power to the A/D converter. Connect the AVCC pin to VCC and the
AVSS pin to VSS
I
CNVSS
CNVSS
I
The microcomputer is in a reset state when "L" is applied to the RESET pin
Switches processor mode. Connect the CNVSS pin to VSS to start up in single-
I
chip mode or to VCC to start up in microprocessor mode
Switches data bus width in external memory space 3. The data bus is 16
___________
Input to Switch BYTE
External Data Bus
bits wide when the BYTE pin is held "L" and 8 bits wide when it is held "H".
Set to either. Connect the BYTE pin to VSS to use the microcomputer in
Width(2)
Bus Control
Pins(2)
I/O
single-chip mode
Inputs and outputs data (D0 to D7) while accessing an external memory
D8 to D15
I/O
space with separate bus
Inputs and outputs data (D8 to D15) while accessing an external memory
A0 to A22
______
A23
O
O
A0/D0 to
A7/D7
I/O
A8/D8 to
I/O
Inputs and outputs data (D8 to D15) and outputs 8 middle-order address bits
(A8 to A15) by time-sharing while accessing an external memory space with
16-bit multiplexed bus
O
O
Outputs CS0 to CS3 that are chip-select signals specifying an external space
D0 to D7
Outputs inversed address bit A23
Inputs and outputs data (D0 to D7) and outputs 8 low-order address bits (A0
to A7) by time-sharing while accessing an external memory space with
multiplexed bus
A15/D15
______
space with 16-bit separate bus
Outputs address bits A0 to A22
_______
______
CS0 to CS3
______
________
WRL / WR
_________
________
WRH / BHE
_____
RD
_______
________
_________
______
________
_____
________
_________
Outputs WRL, WRH, (WR, BHE) and RD signals. WRL and WRH can be
______
_______
switched with WR and BHE by program
________ _________
_____
WRL, WRH and RD selected:
If external data bus is 16 bits wide, data is written to an even address in
________
external memory space when WRL is held "L".
_________
Data is written to an odd address when WRH is held "L".
_____
Data is read when RD is held "L".
______
________
_____
WR, BHE and RD selected:
______
Data is written to external memory space when WR is held "L".
_____
Data in an external memory space is read when RD is held "L".
________
An odd address is accessed when BHE is held "L".
______
ALE
________
_____
O
Select WR, BHE and RD for external 8-bit data bus.
ALE is a signal latching the address
I
O
The microcomputer is placed in a hold state while the HOLD pin is held "L"
Outputs an "L" signal while the microcomputer is placed in a hold state
I
O
Bus is placed in a wait state while the RDY pin is held "L"
When DRAM area is accessed, outputs column and row addresses by time-sharing.
O
The DW signal becomes "L" when data is written to the DRAM area. CASL and CASH are
__________
signals indicating the timing to latch column addresses. The CASL signal becomes "L" when
__________
__________
HOLD
__________
HLDA
________
________
DRAM Bus
Control Pin(2)
RDY
MA0 to MA12
______
______
DW
CASL
__________
__________
__________
__________
an even address is accessed. The CASH signal becomes "L" when an odd address is
________
accessed. RAS is a signal latching row addresses.
CASH
RAS
________
I : Input
O : Output
I/O : Input and output
NOTES:
1. Apply 4.2 to 5.5V to the VCC pin when using M32C/83T.
2. Bus control pins in M32C/83T cannot be used.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
__________
Page 14 of 488
1. Overview
M32C/83 Group (M32C/83, M32C/83T)
Table 1.6 Pin Description (100-Pin and 144-Pin Packages) (Continued)
Classsfication
Symbol
Main Clock Input XIN
I/O Type
Function
I/O pins for the main clock oscillation circuit. Connect a ceramic resonator
I
Main Clock Output XOUT
O
Sub Clock Input XCIN
I
Sub Clock Output XCOUT
O
Low-Pass Filter
or crystal oscillator between XIN and XOUT. To apply external clock, apply it
to XIN and leave XOUT open
I/O pins for the sub clock oscillation circuit. Connect a crystal oscillator
between XCIN and XCOUT. To apply external clock, apply it to XCIN and
leave XCOUT open
Connects the low-pass filter to the VCONT pin when using the PLL frequency synthesizer. Connect P86 to VSS to stabilize the PLL frequency.
VCONT
Connect
Pin for PLL
Frequency
Synthesizer Pin
BCLK Output (1) BCLK
Clock Output
CLKOUT
______
________
O
O
________
INT Interrupt Input INT0 to INT5
_______
_______
NMI Interrupt Input NMI
_____
_____
Key Input Interrupt KI0 to KI3
Timer A
TA0OUT to
Timer B
I
I
I
I/O
Outputs BCLK signal
Outputs the clock having the same frequency as fC, f8 or f32
______
Input pins for the INT interrupt
_______
Input pin for the NMI interrupt
Input pins for the key input interrupt
I/O pins for the timer A0 to A4
(TA0OUT is a pin for the N-channel open drain output.)
TA4OUT
TA0IN to
I
Input pins for the timer A0 to A4
TA4IN
TB0IN to
I
Input pins for the timer B0 to B5
O
Output pins for the three-phase motor control timer
I
Input pins for data transmission control
Output pins for data reception control
TB5IN
___
___
Three-phase Motor U, U, V, V,
___
Control Timer Output W, W
_________
________
Serial I/O
CTS0 to CTS4
_________
I2C Mode
_________
RTS0 to RTS4
CLK0 to CLK4
O
I/O
RxD0 to RxD4
TxD0 to TxD4
I
O
SDA0 to
I/O
SDA4
SCL0 to
O : Output
Outputs serial data
(TxD2 is a pin for the N-channel open drain output.)
Inputs and outputs serial data
(SDA2 is a pin for the N-channel open drain output.)
Inputs and outputs the transfer clock
(SCL2 is a pin for the N-channel open drain output.)
SCL4
I : Input
NOTE:
Inputs and outputs the transfer clock
Inputs serial data
I/O : Input and output
1. Bus control pins in M32C/83T cannot be used.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 15 of 488
1. Overview
M32C/83 Group (M32C/83, M32C/83T)
Table 1.6 Pin Description (100-Pin and 144-Pin Packages) (Continued)
Classsfication
Symbol
STxD0 to
Serial I/O
Special Function STxD4
SRxD0 to
Reference
Voltage Input
A/D Converter
I/O Type
Function
O
Outputs serial data when slave mode is selected
I
Inputs serial data when slave mode is selected
SRxD4
_______
_______
SS0 to SS4
I
Input pins to control serial I/O special function
VREF
I
Applies reference voltage to the A/D converter and D/A converter
AN0 to AN7
AN00 to AN07
I
Analog input pins for the A/D converter
AN20 to AN27
AN150 to AN157
___________
D/A Converter
Intelligent I/O
ADTRG
ANEX0
I
I/O
ANEX1
I
op-amp connection mode
Extended analog input pin for the A/D converter
DA0, DA1
INPC00 to INPC02
O
I
Output pin for the D/A converter
Input pins for the time measurement function
O
Output pins for the waveform generating function
Input pin for an external A/D trigger
Extended analog input pin for the A/D converter and output pin in external
INPC03 to
INPC07(1)
INPC11 to INPC12
INPC16 to
INPC17(1)
OUTC00 to OUTC02
OUTC04 to
OUTC05(1)
(OUTC20 and OUTC22 assigned to P70 and P71 are pins for the N-channel open drain output.)
OUTC10 to OUTC12
OUTC13 to
OUTC17(1)
OUTC20 to OUTC22
OUTC23 to
OUTC27(1)
OUTC30 to OUTC32
OUTC31, OUTC33
CAN
I : Input
to OUTC37(1)
ISCLK0 to ISCLK2
I/O
ISCLK3(1)
ISRXD0 to ISRXD3
I
Inputs data for the intelligent I/O communication function
ISTXD0 to ISTXD3
BE0IN, BE1IN
O
I
Outputs data for the intelligent I/O communication function
Inputs data for the intelligent I/O communication function
BE0OUT, BE1OUT
IEIN
O
I
Outputs data for the intelligent I/O communication function
Inputs data for the intelligent I/O communication function
IEOUT
CANIN
O
I
Outputs data for the intelligent I/O communication function
Input pin for the CAN communication function
CANOUT
O
Output pin for the CAN communication function
O : Output
Inputs and outputs the clock for the intelligent I/O communication function
I/O : Input and output
NOTE:
1. Available in the 144-pin package only.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 16 of 488
1. Overview
M32C/83 Group (M32C/83, M32C/83T)
Table 1.6 Pin Description (144-Pin Package only) (Continued)
Classsfication
I/O Ports
Symbol
I/O Type
P00 to P07
P10 to P17
I/O
Function
8-bit I/O ports for CMOS. Each port can be programmed for input or output
under the control of the direction register. An input port can be set, by
program, for a pull-up resistor available or for no pull-up resister available in
P20 to P27
P30 to P37
4-bit units
(P70 and P71 are ports for the N-channel open drain output.)
P40 to P47
P50 to P57
P60 to P67
P70 to P77
P90 to P97
P100 to P107
P110 to P114
P120 to P127
I/O
I/O ports having equivalent functions to P0
I/O
I/O ports having equivalent functions to P0
P130 to P137
P140 to P146
P150 to P157
(1)
P80 to P84
P86, P87
_______
Input Port
I : Input
P85
O : Output
I
I/O : Input and output
NOTE:
1. Available in the 144-pin package only.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 17 of 488
_______
Shares a pin with NMI. NMI input state can be got by reading P8 5
2. Central Processing Unit (CPU)
M32C/83 Group (M32C/83, M32C/83T)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers.
A register bank comprises 8 registers (R0, R1, R2, R3, A0, A1, SB and FB) out of 28 CPU registers. Two
sets of register banks are provided.
b31
b15
General Register
b0
R2
R0H
R3
R1H
R0L
R1L
Data Register(1)
R2
R3
b23
A0
Address Register(1)
A1
SB
Static Base Register(1)
FB
Frame Base Register(1)
USP
User Stack Pointer
ISP
Interrupt Stack Pointer
INTB
Interrupt Table Register
Program Counter
PC
FLG
b15
Flag Register
b8 b7
IPL
b0
U I O B S Z D C
Carry Flag
Debug Flag
Zero Flag
Sign Flag
Register Bank Flag
Overflow Flag
Interrupt Enable Flag
Stack Pointer Select Flag
Reserved Space
Processor Interrupt Priority Level
Reserved space
b15
High-Speed Interrupt Register
b0
SVF
b23
Flag Save Register
SVP
PC Save Register
VCT
Vector Register
b7
DMAC Associated Register
b0
DMD0
DMD1
b15
DCT0
DCT1
DMA Mode Register
DMA Transfer Count Register
DRC0
DRC1
b23
DMA Transfer Count Reload Register
DMA0
DMA1
DMA Memory Address Register
DRA0
DRA1
DMA Memory Address Reload Register
DSA0
DSA1
DMA SFR Address Register
NOTES:
1. A register bank comprises these registers. Two sets of register banks are provided.
Figure 2.1 CPU Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 18 of 488
M32C/83 Group (M32C/83, M32C/83T)
2. Central Processing Unit (CPU)
2.1 General Registers
2.1.1 Data Registers (R0, R1, R2 and R3)
R0, R1, R2 and R3 are 16-bit registers for transfer, arithmetic and logic operations. R0 and R1 can be
split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers.
R0 can be combined with R2 to be used as a 32-bit data register (R2R0). The same applies to R1 and
R3.
2.1.2 Address Registers (A0 and A1)
A0 and A1 are 24-bit registers for A0-/A1-indirect addressing, A0-/A1-relative addressing, transfer, arithmetic and logic operations.
2.1.3 Static Base Register (SB)
SB is a 24-bit register for SB-relative addressing.
2.1.4 Frame Base Register (FB)
FB is a 24-bit register for FB-relative addressing.
2.1.5 Program Counter (PC)
PC, 24 bits wide, indicates the address of an instruction to be executed.
2.1.6 Interrupt Table Register (INTB)
INTB is a 24-bit register indicating the starting address of an interrupt vector table.
2.1.7 User Stack Pointer (USP), Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP and ISP, are 24 bits wide each. The U flag is used to switch between USP
and ISP. Refer to "2.1.8 Flag Register (FLG)" for details on the U flag. Set USP and ISP to even
addresses to execute an interrupt sequence efficiently.
2.1.8 Flag Register (FLG)
FLG is a 16-bit register indicating a CPU state.
2.1.8.1 Carry Flag (C)
The C flag indicates whether carry or borrow has occurred after executing an instruction.
2.1.8.2 Debug Flag (D)
The D flag is for debug only. Set to "0".
2.1.8.3 Zero Flag (Z)
The Z flag is set to "1" when the value of zero is obtained from an arithmetic calculation; otherwise "0".
2.1.8.4 Sign Flag (S)
The S flag is set to "1" when a negative value is obtained from an arithmetic calculation; otherwise "0".
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 19 of 488
M32C/83 Group (M32C/83, M32C/83T)
2. Central Processing Unit (CPU)
2.1.8.5 Register Bank Select Flag (B)
The register bank 0 is selected when the B flag is set to "0". The register bank 1 is selected when this
flag is set to "1".
2.1.8.6 Overflow Flag (O)
The O flag is set to "1" when the result of an arithmetic operation overflows; otherwise "0".
2.1.8.7 Interrupt Enable Flag (I)
The I flag enables a maskable interrupt.
An interrupt is disabled when the I flag is set to "0" and enabled when the I flag is set to "1". The I flag
is set to "0" when an interrupt is acknowledged.
2.1.8.8 Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to "0". USP is selected when this flag is set to "1".
The U flag is set to "0" when a hardware interrupt is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.1.8.9 Processor Interrupt Priority Level (IPL)
IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has greater priority than IPL, the interrupt is enabled.
2.1.8.10 Reserved Space
When writing to a reserved space, set to "0". When read, its content is indeterminate.
2.2 High-Speed Interrupt Registers
Registers associated with the high-speed interrupt are as follows. Refer to 10.4 High-Speed Interrupt for
details.
- Flag save register (SVF)
- PC save register (SVP)
- Vector register (VCT)
2.3 DMAC-Associated Registers
Registers associated with DMAC are as follows. Refer to 12. DMAC for details.
- DMA mode register (DMD0, DMD1)
- DMA transfer count register (DCT0, DCT1)
- DMA transfer count reload register (DRC0, DRC1)
- DMA memory address register (DMA0, DMA1)
- DMA SFR address register (DSA0, DSA1)
- DMA memory address reload register (DRA0, DRA1)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 20 of 488
3. Memory
M32C/83 Group (M32C/83, M32C/83T)
3. Memory
Figure 3.1 shows a memory map of the M32C/83 group (M32C/83, M32C/83T).
M32C/83 group (M32C/83, M32C/83T) provides 16-Mbyte address space from addresses 00000016 to
FFFFFF16.
The internal ROM is allocated lower addresses beginning with address FFFFFF16. For example, a 64Kbyte internal ROM is allocated addresses FF000016 to FFFFFF16.
The fixed interrupt vectors are allocated addresses FFFFDC16 to FFFFFF16. It stores the starting address
of each interrupt routine. Refer to 10. Interrupts for details.
The internal RAM is allocated higher addresses beginning with address 00040016. For example, a 10Kbyte internal RAM is allocated addresses 00040016 to 002BFF16. Besides storing data, it becomes stacks
when the subroutine is called or an interrupt is acknowledged.
SFR, consisting of control registers for peripheral functions such as I/O port, A/D conversion, serial I/O, and
timers, is allocated addresses 00000016 to 0003FF16. All addresses, which have nothing allocated within
SFR, are reserved space and cannot be accessed by users.
The special page vectors are allocated addresses FFFE0016 to FFFFDB16. It is used for the JMPS instruction and JSRS instruction. Refer to the Renesas publication Software Manual for details.
In memory expansion mode and microprocessor mode, some space are reserved and cannot be accessed
by users.
00000016
SFR
00040016
Internal RAM
007FFF16
Reserved Space
FFFE00 16
00800016
Special Page
Vector Table
External Space(1)
FFFFDC 16
Undefined Instruction
Overflow
BRK Instruction
Address Match
F0000016
Reserved Space(2)
Watchdog Timer(4)
F8000016
Internal ROM(3)
FFFFFF16
FFFFFF 16
NMI
Reset
NOTES:
1. In memory expansion and microprocessor modes
2. In memory expansion mode. This space becomes external space in microprocessor mode.
3. This space can be used in single-chip mode and memory expansion mode. This space becomes external
space in microprocessor mode.
4. Watchdog timer interrupt, oscillation stop detection interrupt, and low voltage detection interrupt share vectors.
Figure 3.1 Memory Map
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 21 of 488
4. Special Function Registers (SFR)
M32C/83 Group (M32C/83, M32C/83T)
4. Special Function Registers (SFR)
Address
000016
000116
000216
000316
Register
Symbol
Value after RESET
1000 00002 (CNVss pin ="L")
000416
Processor Mode Register 0(1)
PM0
000516
000616
000716
000816
000916
000A16
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
Wait Control Register(2)
Address Match Interrupt Enable Register
Protect Register
PM1
CM0
CM1
WCR
AIER
PRCR
000B16
External Data Bus Width Control Register(2)
DS
000C16
000D16
000E16
Main Clock Division Register
Oscillation Stop Detection Register
Watchdog Timer Start Register
MCD
CM2
WDTS
000F16
001016
001116
Watchdog Timer Control Register
WDC
000X XXXX2
Address Match Interrupt Register 0
RMAD0
00 00 0016
Address Match Interrupt Register 1
RMAD1
00 00 0016
VDC Control Register for PLL
PLV
XXXX XX012
Address Match Interrupt Register 2
RMAD2
00 00 0016
VDC Control Register 0
VDC0
0016
Address Match Interrupt Register 3
RMAD3
00 00 0016
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
0000 00112 (CNVss pin ="H")
0X00 00002
0000 X0002
0010 00002
1111 11112
XXXX 00002
XXXX 00002
XXXX 10002 (BYTE pin ="L")
XXXX 00002 (BYTE pin ="H")
XXX0 10002
0016
XX16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
NOTES:
1. The PM00 and PM01 bits in the PM1 register maintain values set before reset even if software reset or watchdog timer reset is performed.
2. These registers in M32C/83T cannot be used.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 22 of 488
4. Special Function Registers (SFR)
M32C/83 Group (M32C/83, M32C/83T)
Address
Register
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
004016 DRAM Control Register (1)
004116 DRAM Refresh Interval Set Register (1)
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
Flash Memory Control Register 0
X: Indeterminate
Blank spaces are reserved. No access is allowed.
NOTES:
1. These registers in M32C/83T cannot be used.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 23 of 488
Symbol
Value after RESET
DRAMCONT
REFCNT
XX16
XX16
FMR0
XX00 00012
4. Special Function Registers (SFR)
M32C/83 Group (M32C/83, M32C/83T)
Address
006016
006116
006216
006316
006416
006516
006616
006716
006816
006916
006A16
006B16
006C16
006D16
006E16
006F16
007016
007116
007216
007316
007416
007516
007616
007716
007816
007916
007A16
007B16
007C16
007D16
007E16
007F16
Register
Symbol
Value after RESET
DMA0 Interrupt Control Register
Timer B5 Interrupt Control Register
DMA2 Interrupt Control Register
UART2 Receive /ACK Interrupt Control Register
Timer A0 Interrupt Control Register
UART3 Receive /ACK Interrupt Control Register
Timer A2 Interrupt Control Register
UART4 Receive /ACK Interrupt Control Register
Timer A4 Interrupt Control Register
UART0/UART3 Bus Conflict Detect Interrupt Control Register
DM0IC
TB5IC
DM2IC
S2RIC
TA0IC
S3RIC
TA2IC
S4RIC
TA4IC
BCN0IC/BCN3IC
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
UART0 Receive/ACK Interrupt Control Register
A/D0 Conversion Interrupt Control Register
UART1 Receive/ACK Interrupt Control Register
Intelligent I/O Interrupt Control Register 0
Timer B1 Interrupt Control Register
Intelligent I/O Interrupt Control Register 2
Timer B3 Interrupt Control Register
Intelligent I/O Interrupt Control Register 4
INT5 Interrupt Control Register
Intelligent I/O Interrupt Control Register 6
INT3 Interrupt Control Register
Intelligent I/O Interrupt Control Register 8
INT1 Interrupt Control Register
Intelligent I/O Interrupt Control Register 10/
S0RIC
AD0IC
S1RIC
IIO0IC
TB1IC
IIO2IC
TB3IC
IIO4IC
INT5IC
IIO6IC
INT3IC
IIO8IC
INT1IC
IIO10IC
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XX00 X0002
XXXX X0002
XX00 X0002
XXXX X0002
XX00 X0002
CAN Interrupt 1 Control Register
CAN1IC
Intelligent I/O Interrupt Control Register 11/
IIO11IC
CAN Interrupt 2 Control Register
CAN2IC
A/D1 Conversion Interrupt Control Register
AD1IC
XXXX X0002
DMA1 Interrupt Control Register
UART2 Transmit /NACK Interrupt Control Register
DMA3 Interrupt Control Register
UART3 Transmit /NACK Interrupt Control Register
Timer A1 Interrupt Control Register
UART4 Transmit /NACK Interrupt Control Register
Timer A3 Interrupt Control Register
UART2 Bus Conflict Detect Interrupt Control Register
DM1IC
S2TIC
DM3IC
S3TIC
TA1IC
S4TIC
TA3IC
BCN2IC
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
008016
008116
008216
008316
008416
008516
008616
008716
008816
008916
008A16
008B16
008C16
008D16
008E16
008F16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 24 of 488
XXXX X0002
M32C/83 Group (M32C/83, M32C/83T)
Address
009016
009116
009216
009316
009416
009516
009616
009716
009816
009916
009A16
009B16
009C16
009D16
009E16
009F16
00A016
00A116
00A216
00A316
00A416
00A516
00A616
00A716
00A816
00A916
00AA16
00AB16
00AC16
00AD16
00AE16
00AF16
00B016
00B116
00B216
00B316
00B416
00B516
00B616
00B716
00B816
00B916
00BA16
00BB16
00BC16
00BD16
00BE16
00BF16
4. Special Function Registers (SFR)
Register
UART0 Transmit /NACK Interrupt Control Register
UART1/UART4 Bus Conflict Detect Interrupt Control Register
UART1 Transmit/NACK Interrupt Control Register
Key Input Interrupt Control Register
Timer B0 Interrupt Control Register
Intelligent I/O Interrupt Control Register 1
Timer B2 Interrupt Control Register
Intelligent I/O Interrupt Control Register 3
Timer B4 Interrupt Control Register
Intelligent I/O Interrupt Control Register 5
INT4 Interrupt Control Register
Intelligent I/O Interrupt Control Register 7
INT2 Interrupt Control Register
Intelligent I/O Interrupt Control Register 9/
Symbol
S0TIC
BCN1IC/BCN4IC
S1TIC
KUPIC
TB0IC
IIO1IC
TB2IC
IIO3IC
TB4IC
IIO5IC
INT4IC
IIO7IC
INT2IC
IIO9IC
CAN Interrupt 0 Control Register
INT0 Interrupt Control Register
Exit Priority Control Register
Interrupt Request Register 0
Interrupt Request Register 1
CAN0IC
INT0IC
RLVL
IIO0IR
IIO1IR
XX00 X0002
XXXX 00002
0000 000X2
0000 000X2
Interrupt Request Register 2
Interrupt Request Register 3
Interrupt Request Register 4
Interrupt Request Register 5
Interrupt Request Register 6
Interrupt Request Register 7
Interrupt Request Register 8
Interrupt Request Register 9
Interrupt Request Register 10
Interrupt Request Register 11
IIO2IR
IIO3IR
IIO4IR
IIO5IR
IIO6IR
IIO7IR
IIO8IR
IIO9IR
IIO10IR
IIO11IR
0000 000X2
0000 000X2
0000 000X2
0000 000X2
0000 000X2
0000 000X2
0000 000X2
0000 000X2
0000 000X2
0000 000X2
Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Enable Register 2
Interrupt Enable Register 3
Interrupt Enable Register 4
Interrupt Enable Register 5
Interrupt Enable Register 6
Interrupt Enable Register 7
Interrupt Enable Register 8
Interrupt Enable Register 9
Interrupt Enable Register 10
Interrupt Enable Register 11
IIO0IE
IIO1IE
IIO2IE
IIO3IE
IIO4IE
IIO5IE
IIO6IE
IIO7IE
IIO8IE
IIO9IE
IIO10IE
IIO11IE
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 25 of 488
Value after RESET
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XX00 X0002
XXXX X0002
XX00 X0002
XXXX X0002
4. Special Function Registers (SFR)
M32C/83 Group (M32C/83, M32C/83T)
Address
00C016
00C116
00C216
00C316
00C416
00C516
00C616
00C716
00C816
00C916
00CA16
00CB16
00CC16
00CD16
00CE16
00CF16
00D016
00D116
00D216
00D316
00D416
00D516
00D616
00D716
00D816
00D916
00DA16
00DB16
00DC16
00DD16
00DE16
00DF16
00E016
00E116
00E216
00E316
00E416
00E516
00E616
00E716
00E816
00E916
00EA16
00EB16
00EC16
00ED16
00EE16
00EF16
Register
Symbol
Value after RESET
XX16
Group 0 Time Measurement/Waveform Generating Register 0
G0TM0/G0PO0
Group 0 Time Measurement/Waveform Generating Register 1
G0TM1/G0PO1
Group 0 Time Measurement/Waveform Generating Register 2
G0TM2/G0PO2
Group 0 Time Measurement/Waveform Generating Register 3
G0TM3/G0PO3
Group 0 Time Measurement/Waveform Generating Register 4
G0TM4/G0PO4
Group 0 Time Measurement/Waveform Generating Register 5
G0TM5/G0PO5
Group 0 Time Measurement/Waveform Generating Register 6
G0TM6/G0PO6
Group 0 Time Measurement/Waveform Generating Register 7
G0TM7/G0PO7
Group 0 Waveform Generating Control Register 0
Group 0 Waveform Generating Control Register 1
Group 0 Waveform Generating Control Register 2
Group 0 Waveform Generating Control Register 3
Group 0 Waveform Generating Control Register 4
Group 0 Waveform Generating Control Register 5
Group 0 Waveform Generating Control Register 6
Group 0 Waveform Generating Control Register 7
Group 0 Time Measurement Control Register 0
Group 0 Time Measurement Control Register 1
Group 0 Time Measurement Control Register 2
Group 0 Time Measurement Control Register 3
Group 0 Time Measurement Control Register 4
Group 0 Time Measurement Control Register 5
Group 0 Time Measurement Control Register 6
Group 0 Time Measurement Control Register 7
G0POCR0
G0POCR1
G0POCR2
G0POCR3
G0POCR4
G0POCR5
G0POCR6
G0POCR7
G0TMCR0
G0TMCR1
G0TMCR2
G0TMCR3
G0TMCR4
G0TMCR5
G0TMCR6
G0TMCR7
Group 0 Base Timer Register
G0BT
Group 0 Base Timer Control Register 0
Group 0 Base Timer Control Register 1
Group 0 Time Measurement Prescaler Register 6
Group 0 Time Measurement Prescaler Register 7
Group 0 Function Enable Register
Group 0 Function Select Register
G0BCR0
G0BCR1
G0TPR6
G0TPR7
G0FE
G0FS
Group 0 SI/O Receive Buffer Register
G0RB
Group 0 Transmit Buffer/Receive Data Register
G0TB/G0DR
XX00 XXXX2
XX16
Group 0 Receive Input Register
Group 0 SI/O Communication Mode Register
Group 0 Transmit Output Register
Group 0 SI/O Communication Control Register
G0RI
G0MR
G0TO
G0CR
XX16
0016
XX16
0000 X0002
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 26 of 488
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
0X00 X0002
0X00 X0002
0X00 X0002
0X00 X0002
0X00 X0002
0X00 X0002
0X00 X0002
0X00 X0002
0016
0016
0016
0016
0016
0016
0016
0016
XX16
XX16
0016
0016
0016
0016
0016
0016
XXXX XXXX2
M32C/83 Group (M32C/83, M32C/83T)
Address
00F016
00F116
00F216
00F316
00F416
00F516
00F616
00F716
00F816
00F916
00FA16
00FB16
00FC16
00FD16
00FE16
00FF16
010016
010116
010216
010316
010416
010516
010616
010716
010816
010916
010A16
010B16
010C16
010D16
010E16
010F16
011016
011116
011216
011316
011416
011516
011616
011716
011816
011916
011A16
011B16
011C16
011D16
011E16
011F16
4. Special Function Registers (SFR)
Register
Group 0 Data Compare Register 0
Group 0 Data Compare Register 1
Group 0 Data Compare Register 2
Group 0 Data Compare Register 3
Group 0 Data Mask Register 0
Group 0 Data Mask Register 1
Symbol
G0CMP0
G0CMP1
G0CMP2
G0CMP3
G0MSK0
G0MSK1
Group 0 Receive CRC Code Register
G0RCRC
Group 0 Transmit CRC Code Register
G0TCRC
Group 0 SI/O Extended Mode Register
Group 0 SI/O Extended Receive Control Register
Group 0 SI/O Special Communication Interrupt Detect Register
Group 0 SI/O Extended Transmit Control Register
G0EMR
G0ERC
G0IRF
G0ETC
Group 1 Time Measurement/Waveform Generating Register 0
G1TM0/G1PO0
Group 1 Time Measurement/Waveform Generating Register 1
G1TM1/G1PO1
Group 1 Time Measurement/Waveform Generating Register 2
G1TM2/G1PO2
Group 1 Time Measurement/Waveform Generating Register 3
G1TM3/G1PO3
Group 1 Time Measurement/Waveform Generating Register 4
G1TM4/G1PO4
Group 1 Time Measurement/Waveform Generating Register 5
G1TM5/G1PO5
Group 1 Time Measurement/Waveform Generating Register 6
G1TM6/G1PO6
Group 1 Time Measurement/Waveform Generating Register 7
G1TM7/G1PO7
Group 1 Waveform Generating Control Register 0
Group 1 Waveform Generating Control Register 1
Group 1 Waveform Generating Control Register 2
Group 1 Waveform Generating Control Register 3
Group 1 Waveform Generating Control Register 4
Group 1 Waveform Generating Control Register 5
Group 1 Waveform Generating Control Register 6
Group 1 Waveform Generating Control Register 7
Group 1 Time Measurement Control Register 0
Group 1 Time Measurement Control Register 1
Group 1 Time Measurement Control Register 2
Group 1 Time Measurement Control Register 3
Group 1 Time Measurement Control Register 4
Group 1 Time Measurement Control Register 5
Group 1 Time Measurement Control Register 6
Group 1 Time Measurement Control Register 7
G1POCR0
G1POCR1
G1POCR2
G1POCR3
G1POCR4
G1POCR5
G1POCR6
G1POCR7
G1TMCR0
G1TMCR1
G1TMCR2
G1TMCR3
G1TMCR4
G1TMCR5
G1TMCR6
G1TMCR7
Value after RESET
XX16
XX16
XX16
XX16
XX16
XX16
XX16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 27 of 488
XX16
0016
0016
0016
0016
0000 00XX2
0000 0XXX2
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
0X00 X0002
0X00 X0002
0X00 X0002
0X00 X0002
0X00 X0002
0X00 X0002
0X00 X0002
0X00 X0002
0016
0016
0016
0016
0016
0016
0016
0016
4. Special Function Registers (SFR)
M32C/83 Group (M32C/83, M32C/83T)
Address
012016
012116
012216
012316
012416
012516
012616
012716
012816
012916
012A16
012B16
012C16
012D16
012E16
012F16
013016
013116
013216
013316
013416
013516
013616
013716
013816
013916
013A16
013B16
013C16
013D16
013E16
013F16
014016
014116
014216
014316
014416
014516
014616
014716
014816
014916
014A16
014B16
014C16
014D16
014E16
014F16
Register
Symbol
Value after RESET
XX16
Group 1 Base Timer Register
G1BT
Group 1 Base Timer Control Register 0
Group 1 Base Timer Control Register 1
Group 1 Time Measurement Prescaler Register 6
Group 1 Time Measurement Prescaler Register 7
Group 1 Function Enable Register
Group 1 Function Select Register
G1BCR0
G1BCR1
G1TPR6
G1TPR7
G1FE
G1FS
Group 1 SI/O Receive Buffer Register
G1RB
Group 1 Transmit Buffer/Receive Data Register
G1TB/G1DR
XX00 XXXX2
XX16
Group 1 Receive Input Register
Group 1 SI/O Communication Mode Register
Group 1 Transmit Output Register
Group 1 SI/O Communication Control Register
Group 1 Data Compare Register 0
Group 1 Data Compare Register 1
Group 1 Data Compare Register 2
Group 1 Data Compare Register 3
Group 1 Data Mask Register 0
Group 1 Data Mask Register 1
G1RI
G1MR
G1TO
G1CR
G1CMP0
G1CMP1
G1CMP2
G1CMP3
G1MSK0
G1MSK1
XX16
0016
XX16
0000 X0002
XX16
XX16
XX16
XX16
XX16
XX16
Group 1 Receive CRC Code Register
G1RCRC
Group 1 Transmit CRC Code Register
G1TCRC
Group 1 SI/O Extended Mode Register
Group 1 SI/O Extended Receive Control Register
Group 1 SI/O Special Communication Interrupt Detect Register
Group 1 SI/O Extended Transmit Control Register
G1EMR
G1ERC
G1IRF
G1ETC
Group 2 Waveform Generating Register 0
G2PO0
Group 2 Waveform Generating Register 1
G2PO1
Group 2 Waveform Generating Register 2
G2PO2
Group 2 Waveform Generating Register 3
G2PO3
Group 2 Waveform Generating Register 4
G2PO4
Group 2 Waveform Generating Register 5
G2PO5
Group 2 Waveform Generating Register 6
G2PO6
Group 2 Waveform Generating Register 7
G2PO7
XX16
0016
0016
0016
0016
0016
0016
XXXX XXXX2
XX16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 28 of 488
XX16
0016
0016
0016
0016
0000 00XX2
0000 0XXX2
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
4. Special Function Registers (SFR)
M32C/83 Group (M32C/83, M32C/83T)
Address
015016
015116
015216
015316
015416
015516
015616
015716
015816
015916
015A16
015B16
015C16
015D16
015E16
015F16
016016
016116
016216
016316
016416
016516
016616
016716
016816
016916
016A16
016B16
016C16
016D16
016E16
016F16
017016
017116
017216
017316
017416
017516
017616
017716
017816
017916
017A16
017B16
017C16
017D16
017E16
017F16
Register
Group 2 Waveform Generating Control Register 0
Group 2 Waveform Generating Control Register 1
Group 2 Waveform Generating Control Register 2
Group 2 Waveform Generating Control Register 3
Group 2 Waveform Generating Control Register 4
Group 2 Waveform Generating Control Register 5
Group 2 Waveform Generating Control Register 6
Group 2 Waveform Generating Control Register 7
Symbol
G2POCR0
G2POCR1
G2POCR2
G2POCR3
G2POCR4
G2POCR5
G2POCR6
G2POCR7
Value after RESET
0016
0016
0016
0016
0016
0016
0016
0016
Group 2 Base Timer Register
G2BT
Group 2 Base Timer Control Register 0
Group 2 Base Timer Control Register 1
Base Timer Start Register
G2BCR0
G2BCR1
BTSR
XX16
0016
0016
XXXX 00002
Group 2 Function Enable Register
Group 2 RTP Output Buffer Register
G2FE
G2RTP
0016
0016
Group 2 SI/O Communication Mode Register
Group 2 SI/O Communication Control Register
G2MR
G2CR
00XX X0002
0000 X0002
XX16
Group 2 SI/O Transmit Buffer Register
G2TB
Group 2 SI/O Receive Buffer Register
G2RB
Group 2 IEBus Address Register
IEAR
Group 2 IEBus Control Register
Group 2 IEBus Transmit Interrupt Cause Detect Register
Group 2 IEBus Receive Interrupt Cause Detect Register
IECR
IETIF
IERIF
XX16
00XX X0002
XXX0 00002
XXX0 00002
Input Function Select Register
IPS
0016
Group 3 SI/O Communication Mode Register
Group 3 SI/O Communication Control Register
G3MR
G3CR
00XX 00002
0000 X0002
XX16
Group 3 SI/O Transmit Buffer Register
G3TB
Group 3 SI/O Receive Buffer Register
G3RB
XX16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 29 of 488
XX16
XX16
XX16
XX16
XX16
XX16
XX16
4. Special Function Registers (SFR)
M32C/83 Group (M32C/83, M32C/83T)
Address
018016
018116
018216
018316
018416
018516
018616
018716
018816
018916
018A16
018B16
018C16
018D16
018E16
018F16
019016
019116
019216
019316
019416
019516
019616
019716
019816
019916
019A16
019B16
019C16
019D16
019E16
019F16
01A016
01A116
01A216
01A316
01A416
01A516
01A616
01A716
01A816
01A916
01AA16
01AB16
01AC16
01AD16
01AE16
01AF16
Register
Symbol
Value after RESET
XX16
Group 3 Waveform Generating Register 0
G3PO0
Group 3 Waveform Generating Register 1
G3PO1
Group 3 Waveform Generating Register 2
G3PO2
Group 3 Waveform Generating Register 3
G3PO3
Group 3 Waveform Generating Register 4
G3PO4
Group 3 Waveform Generating Register 5
G3PO5
Group 3 Waveform Generating Register 6
G3PO6
Group 3 Waveform Generating Register 7
G3PO7
Group 3 Waveform Generating Control Register 0
Group 3 Waveform Generating Control Register 1
Group 3 Waveform Generating Control Register 2
Group 3 Waveform Generating Control Register 3
Group 3 Waveform Generating Control Register 4
Group 3 Waveform Generating Control Register 5
Group 3 Waveform Generating Control Register 6
Group 3 Waveform Generating Control Register 7
G3POCR0
G3POCR1
G3POCR2
G3POCR3
G3POCR4
G3POCR5
G3POCR6
G3POCR7
Group 3 Waveform Generating Mask Register 4
G3MK4
Group 3 Waveform Generating Mask Register 5
G3MK5
Group 3 Waveform Generating Mask Register 6
G3MK6
Group 3 Waveform Generating Mask Register 7
G3MK7
Group 3 Base Timer Register
G3BT
Group 3 Base Timer Control Register 0
Group 3 Base Timer Control Register 1
G3BCR0
G3BCR1
XX16
0016
0016
Group 3 Function Enable Register
Group 3 RTP Output Buffer Register
G3FE
G3RTP
0016
0016
Group 3 SI/O Communication Flag Register
G3FLG
XXXX XXX02
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 30 of 488
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
0016
0016
0016
0016
0016
0016
0016
0016
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
4. Special Function Registers (SFR)
M32C/83 Group (M32C/83, M32C/83T)
Address
01B016
01B116
01B216
01B316
01B416
01B516
01B616
01B716
01B816
01B916
01BA16
01BB16
01BC16
01BD16
01BE16
01BF16
01C016
01C116
01C216
01C316
01C416
01C516
01C616
01C716
01C816
01C916
01CA16
01CB16
01CC16
01CD16
01CE16
01CF16
01D016
01D116
01D216
01D316
01D416
01D516
01D616
01D716
01D816
01D916
01DA16
01DB16
01DC16
01DD16
01DE16
01DF16
Register
Symbol
Value after RESET
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
A/D1 Register 0
AD10
A/D1 Register 1
AD11
A/D1 Register 2
AD12
A/D1 Register 3
AD13
A/D1 Register 4
AD14
A/D1 Register 5
AD15
A/D1 Register 6
AD16
A/D1 Register 7
AD17
A/D1 Control Register 2
AD1CON2
X00X X0002
A/D1 Control Register 0
A/D1 Control Register 1
AD1CON0
AD1CON1
0016
XX00 00002
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 31 of 488
4. Special Function Registers (SFR)
M32C/83 Group (M32C/83, M32C/83T)
Address
01E016
01E116
01E216
01E316
01E416
01E516
01E616
01E716
01E816
01E916
01EA16
01EB16
01EC16
01ED16
01EE16
01EF16
01F016
01F116
01F216
01F316
01F416
01F516
01F616
01F716
01F816
01F916
01FA16
01FB16
01FC16
01FD16
01FE16
01FF16
020016
020116
020216
020316
020416
020516
020616
020716
020816
020916
020A16
020B16
020C16
020D16
020E16
020F16
Register
CAN0 Message Slot Buffer 0 Standard ID0
CAN0 Message Slot Buffer 0 Standard ID1
CAN0 Message Slot Buffer 0 Extended ID0
CAN0 Message Slot Buffer 0 Extended ID1
CAN0 Message Slot Buffer 0 Extended ID2
CAN0 Message Slot Buffer 0 Data Length Code
CAN0 Message Slot Buffer 0 Data 0
CAN0 Message Slot Buffer 0 Data 1
CAN0 Message Slot Buffer 0 Data 2
CAN0 Message Slot Buffer 0 Data 3
CAN0 Message Slot Buffer 0 Data 4
CAN0 Message Slot Buffer 0 Data 5
CAN0 Message Slot Buffer 0 Data 6
CAN0 Message Slot Buffer 0 Data 7
CAN0 Message Slot Buffer 0 Time Stamp High-Order
CAN0 Message Slot Buffer 0 Time Stamp Low-Order
CAN0 Message Slot Buffer 1 Standard ID0
CAN0 Message Slot Buffer 1 Standard ID1
CAN0 Message Slot Buffer 1 Extended ID0
CAN0 Message Slot Buffer 1 Extended ID1
CAN0 Message Slot Buffer 1 Extended ID2
CAN0 Message Slot Buffer 1 Data Length Code
CAN0 Message Slot Buffer 1 Data 0
CAN0 Message Slot Buffer 1 Data 1
CAN0 Message Slot Buffer 1 Data 2
CAN0 Message Slot Buffer 1 Data 3
CAN0 Message Slot Buffer 1 Data 4
CAN0 Message Slot Buffer 1 Data 5
CAN0 Message Slot Buffer 1 Data 6
CAN0 Message Slot Buffer 1 Data 7
CAN0 Message Slot Buffer 1 Time Stamp High-Order
CAN0 Message Slot Buffer 1 Time Stamp Low-Order
Symbol
C0SLOT0_0
C0SLOT0_1
C0SLOT0_2
C0SLOT0_3
C0SLOT0_4
C0SLOT0_5
C0SLOT0_6
C0SLOT0_7
C0SLOT0_8
C0SLOT0_9
C0SLOT0_10
C0SLOT0_11
C0SLOT0_12
C0SLOT0_13
C0SLOT0_14
C0SLOT0_15
C0SLOT1_0
C0SLOT1_1
C0SLOT1_2
C0SLOT1_3
C0SLOT1_4
C0SLOT1_5
C0SLOT1_6
C0SLOT1_7
C0SLOT1_8
C0SLOT1_9
C0SLOT1_10
C0SLOT1_11
C0SLOT1_12
C0SLOT1_13
C0SLOT1_14
C0SLOT1_15
Value after RESET
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX01 0X012(1)
CAN0 Control Register 0
C0CTLR0
CAN0 Status Register
C0STR
CAN0 Extended ID Register
C0IDR
CAN0 Configuration Register
C0CONR
CAN0 Time Stamp Register
C0TSR
CAN0 Transmit Error Count Register
CAN0 Receive Error Count Register
C0TEC
C0REC
CAN0 Slot Interrupt Status Register
C0SISTR
XXXX 00002(1)
0000 00002(1)
X000 0X012(1)
0016(1)
0016(1)
0000 XXXX2(1)
0000 00002(1)
00161)
0016(1)
0016(1)
0016(1)
0016(1)
0016(1)
X: Indeterminate
Blank spaces are reserved. No access is allowed.
NOTES:
1. Values are obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying a
clock to the CAN module after reset.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 32 of 488
4. Special Function Registers (SFR)
M32C/83 Group (M32C/83, M32C/83T)
Address
021016
021116
021216
021316
021416
021516
021616
021716
021816
021916
021A16
021B16
021C16
021D16
021E16
021F16
022016
022116
022216
022316
022416
022516
022616
022716
022816
022916
022A16
022B16
022C16
022D16
022E16
022F16
023016
023116
023216
023316
023416
023516
023616
023716
023816
Register
Symbol
Value after RESET
0016(2)
0016(2)
CAN0 Slot Interrupt Mask Register
C0SIMKR
CAN0 Error Interrupt Mask Register
CAN0 Error Interrupt Status Register
C0EIMKR
C0EISTR
XXXX X0002(2)
XXXX X0002(2)
CAN0 Baud Rate Prescaler
C0BRP
0000 00012(2)
CAN0 Global Mask Register Standard ID0
CAN0 Global Mask Register Standard ID1
CAN0 Global Mask Register Extended ID0
CAN0 Global Mask Register Extended ID1
CAN0 Global Mask Register Extended ID2
C0GMR0
C0GMR1
C0GMR2
C0GMR3
C0GMR4
XXX0 00002(2)
XX00 00002(2)
XXXX 00002(2)
0016(2)
XX00 00002(2)
(Note 1)
CAN0 Message Slot 0 Control Register /
CAN0 Local Mask Register A Standard ID0
CAN0 Message Slot 1 Control Register /
CAN0 Local Mask Register A Standard ID1
CAN0 Message Slot 2 Control Register /
CAN0 Local Mask Register A Extended ID0
CAN0 Message Slot 3 Control Register /
CAN0 Local Mask Register A Extended ID1
CAN0 Message Slot 4 Control Register /
CAN0 Local Mask Register A Extended ID2
CAN0 Message Slot 5 Control Register
CAN0 Message Slot 6 Control Register
CAN0 Message Slot 7 Control Register
CAN0 Message Slot 8 Control Register /
CAN0 Local Mask Register B Standard ID0
C0MCTL0/
C0LMAR0
C0MCTL1/
C0LMAR1
C0MCTL2/
C0LMAR2
C0MCTL3/
C0LMAR3
C0MCTL4/
C0LMAR4
C0MCTL5
C0MCTL6
C0MCTL7
C0MCTL8/
C0LMBR0
00002(2)
0000
XXX0 00002(2)
0000 0000 2(2)
XX00 00002(2)
0000 00002(2)
XXXX 00002(2)
0016(2)
0016(2)
0000 0000 2(2)
XX00 00002(2)
0016(2)
0016(2)
0016(2)
0000 0000 2(2)
XXX0 00002(2)
X: Indeterminate
Blank spaces are reserved. No access is allowed.
NOTES:
1. The BANKSEL bit in the C0CTLR1 register switches functions for addresses 022016 to 023F16.
2. Values are obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying a
clock to the CAN module after reset.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 33 of 488
4. Special Function Registers (SFR)
M32C/83 Group (M32C/83, M32C/83T)
Address
023916
023A16
023B16
023C16
023D16
023E16
023F16
024016
024116
024216
024316
024416
024516
024616
024716
024816
024916
024A16
024B16
024C16
024D16
024E16
024F16
025016
025116
025216
025316
025416
025516
025616
025716
025816
025916
025A16
025B16
025C16
025D16
025E16
025F16
026016
026116
to
02BF16
Register
CAN0 Message Slot 9 Control Register /
CAN0 Local Mask Register B Standard ID1
CAN0 Message Slot 10 Control Register /
CAN0 Local Mask Register B Extended ID0
CAN0 Message Slot 11 Control Register /
CAN0 Local Mask Register B Extended ID1
CAN0 Message Slot 12 Control Register /
CAN0 Local Mask Register B Extended ID2
CAN0 Message Slot 13 Control Register
CAN0 Message Slot 14 Control Register
CAN0 Message Slot 15 Control Register
CAN0 Slot Buffer Select Register
CAN0 Control Register 1
CAN0 Sleep Control Register
Symbol
C0MCTL9/
C0LMBR1
C0MCTL10/
C0LMBR2
C0MCTL11/
C0LMBR3
C0MCTL12/
C0LMBR4
C0MCTL13
C0MCTL14
C0MCTL15
C0SBS
C0CTLR1
C0SLPR
Value after RESET
0000 00002(2)
XX00 00002(2)
0000 00002(2)
XXXX 00002(2)
0016(2)
0016(2)
0000 00002(2)
XX00 00002(2)
0016(2)
0016(2)
0016(2)
0016(2)
XX00 00XX2(2)
XXXX XXX02
CAN0 Acceptance Filter Support Register
C0AFS
0016(2)
0116(2)
(Note 1)
X: Indeterminate
Blank spaces are reserved. No access is allowed.
NOTES:
1. The BANKSEL bit in the C0CTLR1 register switches functions for addresses 022016 to 023F16.
2. Values are obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying a
clock to the CAN module after reset.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 34 of 488
4. Special Function Registers (SFR)
M32C/83 Group (M32C/83, M32C/83T)
Address
02C016
02C116
02C216
02C316
02C416
02C516
02C616
02C716
02C816
02C916
02CA16
02CB16
02CC16
02CD16
02CE16
02CF16
02D016
02D116
02D216
02D316
02D416
02D516
02D616
02D716
02D816
02D916
02DA16
02DB16
02DC16
02DD16
02DE16
02DF16
02E016
02E116
02E216
02E316
02E416
02E516
02E616
02E716
02E816
02E916
02EA16
02EB16
02EC16
02ED16
02EE16
02EF16
Register
Symbol
X0 Register Y0 Register
X0R,Y0R
X1 Register Y1 Register
X1R,Y1R
X2 Register Y2 Register
X2R,Y2R
X3 Register Y3 Register
X3R,Y3R
X4 Register Y4 Register
X4R,Y4R
X5 Register Y5 Register
X5R,Y5R
X6 Register Y6 Register
X6R,Y6R
X7 Register Y7 Register
X7R,Y7R
X8 Register Y8 Register
X8R,Y8R
X9 Register Y9 Register
X9R,Y9R
X10 Register Y10 Register
X10R,Y10R
X11 Register Y11 Register
X11R,Y11R
X12 Register Y12 Register
X12R,Y12R
X13 Register Y13 Register
X13R,Y13R
X14 Register Y14 Register
X14R,Y14R
X15 Register Y15 Register
X15R,Y15R
XY Control Register
XYC
UART1 Special Mode Register 4
UART1 Special Mode Register 3
UART1 Special Mode Register 2
UART1 Special Mode Register
UART1 Transmit/Receive Mode Register
UART1 Baud Rate Register
U1SMR4
U1SMR3
U1SMR2
U1SMR
U1MR
U1BRG
UART1 Transmit Buffer Register
U1TB
UART1 Transmit/Receive Control Register 0
UART1 Transmit/Receive Control Register 1
U1C0
U1C1
UART1 Receive Buffer Register
U1RB
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 35 of 488
Value after RESET
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XXXX XX002
0016
0016
0016
0016
0016
XX16
XX16
XX16
0000 10002
0000 00102
XX16
XX16
4. Special Function Registers (SFR)
M32C/83 Group (M32C/83, M32C/83T)
Address
02F016
02F116
02F216
02F316
02F416
02F516
02F616
02F716
02F816
02F916
02FA16
02FB16
02FC16
02FD16
02FE16
02FF16
030016
030116
030216
030316
030416
030516
030616
030716
030816
030916
030A16
030B16
030C16
030D16
030E16
030F16
031016
031116
031216
031316
031416
031516
031616
031716
031816
031916
031A16
031B16
031C16
031D16
031E16
031F16
Register
Symbol
Value after RESET
UART4 Special Mode Register 4
UART4 Special Mode Register 3
UART4 Special Mode Register 2
UART4 Special Mode Register
UART4 Transmit/Receive Mode Register
UART4 Baud Rate Register
U4SMR4
U4SMR3
U4SMR2
U4SMR
U4MR
U4BRG
0016
0016
0016
0016
0016
XX16
XX16
XX16
0000 10002
0000 00102
XX16
XX16
000X XXXX2
UART4 Transmit Buffer Register
U4TB
UART4 Transmit/Receive Control Register 0
UART4 Transmit/Receive Control Register 1
U4C0
U4C1
UART4 Receive Buffer Register
U4RB
Timer B3, B4, B5 Count Start Flag
TBSR
Timer A1-1 Register
TA11
Timer A2-1 Register
TA21
Timer A4-1 Register
TA41
Three-Phase PWM Control Register 0
Three-Phase PWM Control Register 1
Three-Phase output Buffer Register 0
Three-Phase output Buffer Register 1
Dead Time Timer
Timer B2 Interrupt Generating Frequency Set Counter
INVC0
INVC1
IDB0
IDB1
DTT
ICTB2
Timer B3 Register
TB3
Timer B4 Register
TB4
Timer B5 Register
TB5
Timer B3 Mode Register
Timer B4 Mode Register
Timer B5 Mode Register
TB3MR
TB4MR
TB5MR
00XX 00002
00XX 00002
00XX 00002
External Interrupt Cause Select Register
IFSR
0016
XX16
XX16
XX16
XX16
XX16
XX16
0016
0016
XX11 11112
XX11 11112
XX16
XX16
XX16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 36 of 488
XX16
XX16
XX16
XX16
XX16
4. Special Function Registers (SFR)
M32C/83 Group (M32C/83, M32C/83T)
Address
Register
032016
032116
032216
032316
032416 UART3 Special Mode Register 4
032516
032616
032716
032816
032916
032A16
032B16
032C16
032D16
032E16
032F16
033016
033116
033216
033316
033416
033516
033616
033716
033816
033916
033A16
033B16
033C16
033D16
033E16
033F16
034016
034116
034216
034316
034416
034516
034616
034716
034816
034916
034A16
034B16
034C16
034D16
034E16
034F16
Symbol
Value after RESET
U3SMR4
0016
UART3 Special Mode Register 3
UART3 Special Mode Register 2
UART3 Special Mode Register
UART3 Transmit/Receive Mode Register
UART3 Baud Rate Register
U3SMR3
U3SMR2
U3SMR
U3MR
U3BRG
UART3 Transmit Buffer Register
U3TB
UART3 Transmit/Receive Control Register 0
UART3 Transmit/Receive Control Register 1
U3C0
U3C1
UART3 Receive Buffer Register
U3RB
0016
0016
0016
0016
XX16
XX16
XX16
0000 10002
0000 00102
XX16
XX16
UART2 Special Mode Register 4
UART2 Special Mode Register 3
UART2 Special Mode Register 2
UART2 Special Mode Register
UART2 Transmit/Receive Mode Register
UART2 Baud Rate Register
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
U2BRG
UART2 Transmit Buffer Register
U2TB
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
U2C0
U2C1
UART2 Receive Buffer Register
U2RB
Count Start Flag
Clock Prescaler Reset Flag
One-Shot Start Flag
Trigger Select Register
Up-Down Flag
TABSR
CPSRF
ONSF
TRGSR
UDF
Timer A0 Register
TA0
Timer A1 Register
TA1
Timer A2 Register
TA2
Timer A3 Register
TA3
Timer A4 Register
TA4
0016
0016
0016
0016
0016
XX16
XX16
XX16
0000 10002
0000 00102
XX16
XX16
0016
0XXX XXXX2
0016
0016
0016
XX16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 37 of 488
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
4. Special Function Registers (SFR)
M32C/83 Group (M32C/83, M32C/83T)
Address
Register
035016
Timer B0 Register
035116
035216
Timer B1 Register
035316
035416
Timer B2 Register
035516
035616 Timer A0 Mode Register
035716 Timer A1 Mode Register
035816 Timer A2 Mode Register
035916 Timer A3 Mode Register
035A16 Timer A4 Mode Register
035B16 Timer B0 Mode Register
035C16 Timer B1 Mode register
035D16 Timer B2 Mode Register
035E16 Timer B2 Special Mode Register
035F16 Count Source Prescaler Register(1)
036016
036116
036216
036316
036416 UART0 Special Mode Register 4
036516 UART0 Special Mode Register 3
036616 UART0 Special Mode Register 2
036716 UART0 Special Mode Register
036816 UART0 Transmit/Receive Mode Register
036916 UART0 Baud Rate Register
036A16
UART0 Transmit Buffer Register
036B16
036C16 UART0 Transmit/Receive Control Register 0
036D16 UART0 Transmit/Receive Control Register 1
036E16
UART0 Receive Buffer Register
036F16
037016
037116
037216
037316
037416
037516
037616 PLL Control Register 0
037716 PLL Control Register 1
037816 DMA0 Cause Select Register
037916 DMA1 Cause Select Register
037A16 DMA2 Cause Select Register
037B16 DMA3 Cause Select Register
037C16
CRC Data Register
037D16
037E16 CRC Input Register
037F16
Symbol
TB0
TB1
TB2
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
TB2SC
TCSPR
U0SMR4
U0SMR3
U0SMR2
U0SMR
U0MR
U0BRG
U0TB
U0C0
U0C1
U0RB
PLC0
PLC1
DM0SL
DM1SL
DM2SL
DM3SL
CRCD
CRCIN
Value after RESET
XX16
XX16
XX16
XX16
XX16
XX16
0000 0X002
0000 0X002
0000 0X002
0000 0X002
0000 0X002
00XX 00002
00XX 00002
00XX 00002
XXXX XXX02
0XXX 00002
0016
0016
0016
0016
0016
XX16
XX16
XX16
0000 10002
0000 00102
XX16
XX16
0011 X1002
XXXX 00002
0X00 00002
0X00 00002
0X00 00002
0X00 00002
XX16
XX16
XX16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
NOTES:
1. The TCSPR register maintains the values set before reset even if software reset or watchdog timer reset
is performed.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 38 of 488
4. Special Function Registers (SFR)
M32C/83 Group (M32C/83, M32C/83T)
Address
038016
038116
038216
038316
038416
038516
038616
038716
038816
038916
038A16
038B16
038C16
038D16
038E16
038F16
039016
039116
039216
039316
039416
039516
039616
039716
039816
039916
039A16
039B16
039C16
039D16
039E16
039F16
Register
Symbol
Value after RESET
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
A/D0 Register 0
AD00
A/D0 Register 1
AD01
A/D0 Register 2
AD02
A/D0 Register 3
AD03
A/D0 Register 4
AD04
A/D0 Register 5
AD05
A/D0 Register 6
AD06
A/D0 Register 7
AD07
A/D0 Control Register 2
AD0CON2
X000 00002
A/D0 Control Register 0
A/D0 Control Register 1
D/A Register 0
AD0CON0
AD0CON1
DA0
0016
0016
XX16
D/A Register 1
DA1
XX16
D/A Control Register
DACON
XXXX XX002
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 39 of 488
4. Special Function Registers (SFR)
M32C/83 Group (M32C/83, M32C/83T)
<144-pin package>
Address
03A016
03A116
03A216
03A316
03A416
03A516
03A616
03A716
03A816
03A916
03AA16
03AB16
03AC16
03AD16
03AE16
03AF16
03B016
03B116
03B216
03B316
03B416
03B516
03B616
03B716
03B816
03B916
03BA16
03BB16
03BC16
03BD16
03BE16
03BF16
03C016
03C116
03C216
03C316
03C416
03C516
03C616
03C716
03C816
03C916
03CA16
03CB16
03CC16
03CD16
03CE16
03CF16
Register
Function Select Register A8
Function Select Register A9
Symbol
PS8
PS9
Value after RESET
X000 00002
0016
Function Select Register C
Function Select Register A0
Function Select Register A1
Function Select Register B0
Function Select Register B1
Function Select Register A2
Function Select Register A3
Function Select Register B2
Function Select Register B3
PSC
PS0
PS1
PSL0
PSL1
PS2
PS3
PSL2
PSL3
00X0 00002
0016
0016
0016
0016
00X0 00002
0016
00X0 00002
0016
Function Select Register A5
PS5
XXX0 00002
Function Select Register A6
Function Select Register A7
PS6
PS7
0016
0016
Port P6 Register
Port P7 Register
Port P6 Direction Register
Port P7 Direction Register
Port P8 Register
Port P9 Register
Port P8 Direction Register
Port P9 Direction Register
Port P10 Register
Port P11 Register
Port P10 Direction Register
Port P11 Direction Register
Port P12 Register
Port P13 Register
Port P12 Direction Register
Port P13 Direction Register
P6
P7
PD6
PD7
P8
P9
PD8
PD9
P10
P11
PD10
PD11
P12
P13
PD12
PD13
XX16
XX16
0016
0016
XX16
XX16
00X0 00002
0016
XX16
XX16
0016
XXX0 00002
XX16
XX16
0016
0016
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 40 of 488
4. Special Function Registers (SFR)
M32C/83 Group (M32C/83, M32C/83T)
<144-pin package>
Address
03D016
03D116
03D216
03D316
03D416
03D516
03D616
03D716
03D816
03D916
03DA16
03DB16
03DC16
03DD16
03DE16
03DF16
03E016
03E116
03E216
03E316
03E416
03E516
03E616
03E716
03E816
03E916
03EA16
03EB16
03EC16
03ED16
03EE16
03EF16
03F016
03F116
03F216
03F316
03F416
03F516
03F616
03F716
03F816
03F916
03FA16
03FB16
03FC16
03FD16
03FE16
03FF16
Register
Port P14 Register
Port P15 Register
Port P14 Direction Register
Port P15 Direction Register
Symbol
P14
P15
PD14
PD15
Value after RESET
XX16
XX16
X000 00002
0016
Pull-Up Control Register 2
Pull-Up Control Register 3
Pull-Up Control Register 4
PUR2
PUR3
PUR4
0016
0016
XXXX 00002
Port P0 Register
Port P1 Register
Port P0 Direction Register
Port P1 Direction Register
Port P2 Register
Port P3 Register
Port P2 Direction Register
Port P3 Direction Register
Port P4 Register
Port P5 Register
Port P4 Direction Register
Port P5 Direction Register
P0
P1
PD0
PD1
P2
P3
PD2
PD3
P4
P5
PD4
PD5
XX16
XX16
0016
0016
XX16
XX16
0016
0016
XX16
XX16
0016
0016
Pull-Up Control Register 0
Pull-Up Control Register 1
PUR0
PUR1
0016
XXXX 00002
Port Control Register
PCR
XXXX XXX02
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 41 of 488
M32C/83 Group (M32C/83, M32C/83T)
4. Special Function Registers (SFR)
<100-pin package>
12345678901234567890123456789012123456789012345678901234
12345678901234567890123456789012123456789012345678901234
12345678901234567890123456789012123456789012345678901234
12345678901234567890123456789012123456789012345678901234
Address
Register
Symbol
Value after RESET
03A016
(Note 2)
03A116
03A216
03A316
03A416
03A516
03A616
03A716
03A816
03A916
03AA16
03AB16
03AC16
03AD16
03AE16
03AF16 Function Select Register C
PSC
0X00 00002
03B016 Function Select Register A0
PS0
0016
03B116 Function Select Register A1
PS1
0016
03B216 Function Select Register B0
PSL0
0016
03B316 Function Select Register B1
PSL1
0016
03B416 Function Select Register A2
PS2
00X0 00002
03B516 Function Select Register A3
PS3
0016
03B616 Function Select Register B2
PSL2
00X0 00002
03B716 Function Select Register B3
PSL3
0016
03B816
(Note 2)
03B916
03BA16
03BB16
03BC16
(Note 2)
03BD16
03BE16
03BF16
03C016 Port P6 Register
P6
XX16
03C116 Port P7 Register
P7
XX16
03C216 Port P6 Direction Register
PD6
0016
03C316 Port P7 Direction Register
PD7
0016
03C416 Port P8 Register
P8
XX16
03C516 Port P9 Register
P9
XX16
03C616 Port P8 Direction Register
PD8
00X0 00002
03C716 Port P9 Direction Register
PD9
0016
03C816 Port P10 Register
P10
XX16
(Note 2)
03C916
03CA16 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901
Port P10 Direction Register
PD10
0016
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901
(Note 1)
03CB16 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901
03CC16
(Note 2)
03CD16 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901
03CE16 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901
(Note 1)
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901
03CF16 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901
12345678901234567890123456789012123456789012345678901234
12345678901234567890123456789012123456789012345678901234
12345678901234567890123456789012123456789012345678901234
12345678901234567890123456789012123456789012345678901234
12345678901234567890123456789012123456789012345678901234
12345678901234567890123456789012123456789012345678901234
12345678901234567890123456789012123456789012345678901234
12345678901234567890123456789012123456789012345678901234
12345678901234567890123456789012123456789012345678901234
12345678901234567890123456789012123456789012345678901234
12345678901234567890123456789012123456789012345678901234
12345678901234567890123456789012123456789012345678901234
12345678901234567890123456789012123456789012345678901234
12345678901234567890123456789012123456789012345678901234
X: Indeterminate
Blank spaces are reserved. No access is allowed.
NOTES:
123456
123456
123456 Set address spaces 03CB16, 03CE16 and 03CF16 to "FF16" in the 100-pin package.
1234
1234 Address spaces 03A016, 03A116, 03B916, 03BC16, 03BD16, 03C916, 03CC16 and 03CD16 are not provided
1.
2.
in the 100-pin package.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 42 of 488
M32C/83 Group (M32C/83, M32C/83T)
4. Special Function Registers (SFR)
<100-pin package>
12345678901234567890123456789012123456789012345678901234
12345678901234567890123456789012123456789012345678901234
12345678901234567890123456789012123456789012345678901234
12345678901234567890123456789012123456789012345678901234
Address
Register
Symbol
Value after RESET
03D016
(Note 3)
03D116 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901
03D216 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901(Note 1)
03D316 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901
03D416
03D516
03D616
03D716
03D816
03D916
03DA16 Pull-up Control Register 2
PUR2
0016
03DB16 123456789012345678901234567890121234567890123456789012345678901212345678901234567
Pull-up Control Register 3
PUR3
0016
123456789012345678901234567890121234567890123456789012345678901212345678901234567
03DC16 123456789012345678901234567890121234567890123456789012345678901212345678901234567(Note 2)
03DD16
03DE16
03DF16
03E016 Port P0 Register
P0
XX16
03E116 Port P1 Register
P1
XX16
03E216 Port P0 Direction Register
PD0
0016
03E316 Port P1 Direction Register
PD1
0016
03E416 Port P2 Register
P2
XX16
03E516 Port P3 Register
P3
XX16
03E616 Port P2 Direction Register
PD2
0016
03E716 Port P3 Direction Register
PD3
0016
03E816 Port P4 Register
P4
XX16
03E916 Port P5 Register
P5
XX16
03EA16 Port P4 Direction Register
PD4
0016
03EB16 Port P5 Direction Register
PD5
0016
03EC16
03ED16
03EE16
03EF16
03F016 Pull-Up Control Register 0
PUR0
0016
03F116 Pull-Up Control Register 1
PUR1
XXXX 00002
03F216
03F316
03F416
03F516
03F616
03F716
03F816
03F916
03FA16
03FB16
03FC16
03FD16
03FE16
03FF16 Port Control Register
PCR
XXXX XXX02
X: Indeterminate
Blank spaces are reserved. No access is allowed.
NOTES:
123456
123456 Set address spaces 03D216 and 03D316 to "FF16" in the 100-pin package.
1. 123456
12345
12345
2.
Set address spaces 03DC16 to "0016" in the 100-pin package.
1234
1234Address spaces 03D016 and 03D116 are not provided in the 100-pin package.
3.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 43 of 488
5. Reset
M32C/83 Group (M32C/83, M32C/83T)
5. Reset
Hardware reset, software reset, and watchdog timer reset are available to reset the microcomputer.
5.1 Hardware Reset
5.1.1 Reset on a Stable Supply Voltage
The microcomputer resets pins, the CPU and SFR when the supply voltage meets the recommended
___________
performance conditions while an "L" signal is applied to the RESET pin (see Table 5.1). Apply an "H"
____________
signal to the RESET pin again after 20 or more clock cycles are input to the XIN pin while applying an "L"
____________
to the RESET pin. The CPU and SFR are reset and programs run from the address indicated by the reset
vector.
____________
The internal RAM is not reset. When the RESET pin becomes "L" while writing data to the internal RAM,
the internal RAM is in an indeterminate state.
5.1.2 Power-on Reset
The microcomputer resets pins, the CPU and SFR when the supply voltage applied to the VCC pin meets
___________
the recommended performance conditions while an "L" signal is applied to the RESET pin. (See Table
5.1.)
____________
The CPU and SFR are reset when the signal applied to the RESET pin changes low ("L") to high ("H")
after the main clock oscillation stabilizes and 20 or more clock cycles are applied to the XIN pin. Programs
run from the address indicated by the reset vector. The internal RAM is in a indeterminate state
Figure 5.1 shows a reset circuit. Figure 5.2 shows a reset sequence. Figure 5.3 shows CPU register condi____________
tions after reset. Table 5.1 lists pin states while the RESET pin is held "L". Refer to 4. SFR for SFR states
after reset.
5V
VCC
RESET
Recommended
Operation Voltage
0V
5V
VCC
RESET
0.2VCC or below
0V
The above applies to VCC = 5V
Figure 5.1 Reset Circuit
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 44 of 488
Supply a clock with 20 or more cycles to
the XIN pin
5. Reset
M32C/83 Group (M32C/83, M32C/83T)
XIN
Microprocessor
(2)
mode BYTE = “H”
20 or more XIN cycles
required
40 to 45 BCLK cycles
RESET
BCLK
Content of reset vector
FFFFFC16
Address
FFFFFD16
FFFFFE16
RD
WR
CS0
Microprocessor
mode BYTE = “L”(2)
Content of reset vector
FFFFFC16
Address
FFFFFE16
RD
WR
CS0
Single-chip
mode
FFFFFC16 Content of reset vector
Address(1)
FFFFFE16
NOTES:
1. Addresses cannot be output from pins, in single-chip mode.
2. M32C/83T cannot be used in memory expansion mode and microprocessor mode.
Figure 5.2 Reset Sequence
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 45 of 488
5. Reset
M32C/83 Group (M32C/83, M32C/83T)
____________
Table 5.1 Pin States while RESET Pin is Held "L"
Pin States
Pin Name
CNVSS = VCC
CNVSS = VSS
BYTE = VSS
BYTE = VCC
P0
Input port (high-impedance) Data input (high-impedance)
P1
Input port (high-impedance) Data input (high-impedance)
P2, P3, P4
Input port (high-impedance) Address output (indeterminate)
P50
Input port (high-impedance) WR output (output "H")
P51
Input port (high-impedance) BHE output (indeterminate)
P52
Input port (high-impedance) RD output (output "H")
P53
Input port (high-impedance) BCLK output
P54
Input port (high-impedance) HLDA output (output value depends on an input to HOLD pin)
P55
Input port (high-impedance) HOLD input (high-impedance)
P56
Input port (high-impedance) RAS output
P57
P6 to P15
Input port (high-impedance)
Input port (high-impedance) RDY input (high-impedance)
(1)
Input port (high-impedance) Input port (high-impedance)
NOTES:
1. Ports P11 to P15 are provided in the 144-pin package.
5.2 Software Reset
When the PM03 bit in the PM0 register is set to "1" (microcomputer reset), pins, the CPU and SFR are
reset. Then the microcomputer executes the program from an address determined by the reset vector.
When software reset is performed, some registers in the SFR are not reset. Refer to 4. SFR for details.
Set the PM03 bit to "1" while the main clock is selected as the CPU clock and the main clock oscillation is
stable.
5.3 Watchdog Timer Reset
The microcomputer resets pins, the CPU and the SFR when the watchdog timer underflows while the
CM06 bit in the CM0 register is set to "1" (reset). Then the microcomputer executes the program from an
address indicated by the reset vector.
When watchdog timer reset is performed, some registers in the SFR are not reset. Refer to 4. SFR for
details. Because the PM01 to PM00 bits in the PM0 register are not reset, the processor mode remains
unchanged.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 46 of 488
5. Reset
M32C/83 Group (M32C/83, M32C/83T)
5.4 Internal Space
Figure 5.3 shows CPU register states after reset. Refer to 4. SFR for SFR states after reset.
0 : "0" after reset
X : Indeterminate after reset
General Register
High-Speed Interrupt Register
b15
Flag Register (FLG)
000016
b15
b15
b0
b8 b7
b0
X 0 0 0 X X X X 0 0 0 0 0 0 0 0
IPL
U I O B S Z D C
b0
XXXX16
b23
Save Flag Register (SVF)
XXXXXX16
Save PC Register (SVP)
XXXXXX16
Vector Register (VCT)
DMAC-Associated Register
b0
b7
0016
0016
Data Register (R0H/R0L)
0016
0016
Data Register (R1H/R1L)
b15
b0
0016
DMA Mode Register (DMD0)
0016
DMA Mode Register (DMD1)
000016
Data Register (R2)
XXXX16
DMA Transfer Count Register (DCT0)
000016
Data Register (R3)
XXXX16
DMA Transfer Count Register (DCT1)
00000016
Address Register (A0)
XXXX16
DMA Transfer Count Reload Register (DRC0)
00000016
Address Register (A1)
XXXX16
DMA Transfer Count Reload Register (DRC1)
00000016
Static Base Register (SB)
XXXXXX16
DMA Memory Address Register (DMA0)
00000016
Frame Base Register (FB)
XXXXXX16
DMA Memory Address Register (DMA1)
00000016
User Stack Pointer (USP)
XXXXXX16
DMA Memory Address Reload Register (DRA0)
00000016
Interrupt Stack Pointer (ISP)
XXXXXX16
DMA Memory Address Reload Register (DRA1)
00000016
Interrupt Table Register (INTB)
XXXXXX16
DMA SFR Address Register (DSA0)
XXXXXX16
DMA SFR Address Register (DSA1)
b23
Contents of addresses
Program Counter (PC)
FFFFFE16 to FFFFFC16
Figure 5.3 CPU Register after Reset
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 47 of 488
b23
M32C/83 Group (M32C/83, M32C/83T)
6. Processor Mode
6. Processor Mode
NOTE
M32C/83T can be used in single-chip mode.
M32C/83T cannot be used in memory expansion mode and microprocessor mode.
6.1 Types of Processor Mode
Single-chip mode, memory expansion mode, or microprocessor mode can be selected as processor mode.
Pin functions, memory map and accessible space vary depending on the selected processor mode.
6.1.1 Single-chip Mode
In single-chip mode, internal memory space (the SFR, internal RAM and internal ROM) can be accessed.
All I/O ports can be used.
6.1.2 Memory Expansion Mode
In memory expansion mode, both external memory space and internal memory space can be accessed .
Some pins function as pins for bus control signals. The BYTE pin and register settings determine how
many pins are assigned for these pin functions. Refer to 7. Bus for details.
6.1.3 Microprocessor Mode
In microprocessor mode, SFR, internal RAM and external memory space can be accessed. Internal ROM
cannot be accessed.
Some pins function as pins for bus control signals. The BYTE pin and register settings determine how
many pins are assigned for these pin functions. (Refer to 7. Bus for details.)
6.2 Setting Processor Mode
The processor mode is set by the combination of CNVSS pin and the PM01 to PM00 bit settings in the PM0
register. Do not set the PM01 to PM00 bits to "102".
If the PM01 to PM00 bits are rewritten, the mode corresponding to the PM01 to PM00 bits is selected
regardless of CNVSS pin level.
Do not change the PM01 to PM00 bits when the PM02 to PM07 bits in the PM0 register are being rewritten.
Do not enter microprocessor mode while the CPU is executing a program in the internal ROM . Do not enter
single-chip mode while the CPU is executing a program in an external memory space.
Figures 6.1 and 6.2 show the PM0 register and PM1 register. Figure 6.3 shows a memory map in each
processor mode.
6.2.1 Applying VSS to CNVSS Pin
The microcomputer enters single-chip mode after reset. Set the PM01 to PM00 bits to "012" (memory
expansion mode) to switch to memory expansion mode after the microcomputer starts operating.
6.2.2 Applying VCC to CNVSS Pin
The microcomputer enters microprocessor mode after reset.
When using the flash memory version, apply VCC to P55 (HOLD) as well as to the CNVSS.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 48 of 488
6. Processor Mode
M32C/83 Group (M32C/83, M32C/83T)
Processor Mode Register 0(1)
b7
b6
b5
b4
b3
b2
b1
Symbol
PM0
b0
0
Bit
Symbol
Address
000416
After Reset
1000 00002 (CNVss = "L")
0000 00112 (CNVss = "H")
Bit Name
Function
RW
b1 b0
PM00
Processor Mode
Bit(2, 3)
PM01
0 0: Single-chip mode
0 1: Memory expansion mode(9)
1 0: Do not set to this value
1 1: Microprocessor mode(9)
RW
RW
PM02
R/W Mode Select Bit(4)
0: RD / BHE / WR
1: RD / WRH / WRL
RW
PM03
Software Reset Bit
The microcomputer is reset when
this bit is set to "1". When read, its
content is "0".
RW
b5 b4
PM04
Multiplexed Bus Space
Select Bit(5)
RW
0 0 : Multiplexed bus is not used
0 1 : Access the CS2 area with the bus
0 1 : Access the CS1 area with the bus
RW
1 1 : Access all CS areas with the bus(6)
Reserved Bit
Set to "0"
PM05
RW
(b6)
PM07
BCLK Output
Disable Bit(7)
0 : BCLK is output(8)
1 : BCLK is not output
RW
The CM01 and CM00 bits in the
CM0 register determine pin functions.
NOTES:
1. Rewrite the PM0 register after the PRC1 bit in the PRCR register is set to "1" (write enable).
2. Processor mode is not changed even if the PM03 bit is set to "1" (software reset).
3. Set the PM01 to PM00 bits to "012" or "112" separately. Rewrite other bits before rewriting the PM01 to
PM00 bits.
4. When using the 16-bit data bus in the DRAMC, set the PM02 bit to "1".
5. The PM05 to PM04 bits are available in memory expansion mode or microprocessor mode.
• Set the PM05 to PM04 bits to "002" in mode 0.
• Do not set the PM05 to PM04 bits to "012" in mode 2.
6. The PM05 to PM04 bits cannot be set to "112" in microprocessor mode because the microcomputer
starts operation using the separate bus after reset.
When the PM05 to PM04 bits are set to "112" in memory expansion mode, the microcomputer can
access each 64-Kbyte chip-select-assigned address space. The multiplexed bus is not available in
mode 0. The microcomputer accesses CS0 to CS2 in mode 1, CS0 and CS1 in mode 2 and CS0 to
CS3 in mode 3.
7. No BCLK is output in single-chip mode even if the PM07 bit is set to "0". When a clock output is
terminated in microprocessor mode or memory expansion mode, set the PM07 bit to "1" and the
CM01 to CM00 bits in the CM0 register to "002" (I/O port P53). P53 outputs "L" .
8. When the PM07 bit is set to "0" (BCLK output), set the CM01 and CM00 bits to "002".
9. M32C/83T cannot be used in memory expansion mode and microprocessor mode.
Figure 6.1 PM0 Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 49 of 488
6. Processor Mode
M32C/83 Group (M32C/83, M32C/83T)
Processor Mode Register 1(1)
b7
b6
b5
b4
b3
b2
b1
Symbol
PM1
b0
0
Bit
Symbol
After Reset
0X00 00002
Address
000516
Bit Name
Function
RW
b1 b0
PM10
PM11
0 0 : Mode 0 (A20 to A23 for P44 to P47)
RW
0 1 : Mode 1 (A20 for P44,
CS2
to
CS0
for
P4
5 to P47)
External Memory Space
1 0 : Mode 2 (A20, A21 for P44, P45,
Mode Bit(2, 6)
CS1, CS0 for P46, P47)
RW
1 1 : Mode 3(3)
(CS3 to CS0 for P44 to P47)
PM12
Internal Memory Wait Bit
0 : No wait state
1 : Wait state
RW
PM13
SFR Area Wait Bit 0
0 : 1 wait state
1 : 2 wait states(4)
RW
b5 b4
PM14
ALE Pin Select
PM15
(b6)
(b7)
Bit(2, 6)
0 0 : No ALE
0 1 : P53/BCLK(5)
1 0 : P56/RAS
1 1 : P54/HLDA
RW
RW
Nothing is assigned.
When read, its content is indeterminate.
Reserved Bit
Set to "0"
RW
NOTES:
1. Rewrite the PM1 register after the PRC1 bit in the PRCR register is set to "1" (write enable).
2. The PM10 and PM11 bits are available in memory expansion mode or microprocessor mode.
3. The DRAMC is not available when the PM11 and PM10 bits are set to "112" (mode 3).
4. Set the PM13 bit to "1" (2 wait states) to access CAN-associated registers (addresses 01E016 to
024516).
5. Set the CM01 and CM00 bits in the CM0 register to "002" (I/O port P53) when the PM15 and PM14
bits are set to "012" (P53/BCLK select).
6. M32C/83T cannot be used in memory expansion mode and microprocessor mode.
Figure 6.2 PM1 Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 50 of 488
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 51 of 488
Figure 6.3 Memory Map in Each Processor Mode
FFFFFF16
F0000016
E0000016
E0000016
C0000016
40000016
30000016
20000016
10000016
00080016
00040016
00000016
Reserved Space
Internal ROM
External Space 3
(External Space 2)
(External Space 2)
Reserved Space
Internal ROM
Not Used
CS0
2M bytes
External Space 3
DRAMConnectable
Space 0,
0.5 to 8M bytes (
Remaining space
cannot be used if
empty space is
less than 8M
bytes)
CS2
2M bytes
External Space 1
CS1
2M bytes (1)
External Space 0
SFR
Internal RAM
Reserved Space
Mode 1
DRAMConnectable
Space 0,
0.5 to 8M byte
(Available as
external space
when DRAM is not
used)
External Space 1
External Space 0
SFR
Internal RAM
Reserved Space
Mode 0
Memory Expansion Mode
Reserved Space
Internal ROM
CS0
3M bytes
External Space 3
(External Space 2)
DRAMConnectable
Space 0,
0.5 to 8M bytes(
Remaining space
cannot be used if
empty space is
less than 8M
bytes)
CS1
4M bytes (2)
External Space 0
SFR
Internal RAM
Reserved Space
Mode 2
The WCR register determines how many wait states are inserted for each space CS0 to CS3.
Internal ROM
Not Used
SFR
Internal RAM
Single-Chip
Mode
External Space 3
(External Space 2)
DRAMConnectable
Space 0,
0.5 to 8M bytes(
Available as
external space
when DRAM is not
used)
External Space 1
External Space 0
SFR
Internal RAM
Reserved Space
Mode 0
CS0
2M bytes
External Space 3
Not Used
(External Space 2)
DRAMConnectable
Space 0,
0.5 to 8M bytes(
Remaining space
cannot be used if
empty space is
less than 8M
bytes)
CS2
2M bytes
External Space 1
CS1
2M bytes (1)
External Space 0
SFR
Internal RAM
Reserved Space
Mode 1
Microprocessor Mode
CS0
4M bytes
External Space 3
(External Space 2)
DRAMConnectable
Space 0,
0.5 to 8M bytes
(Remaining space
cannot be used if
empty space is
less than 8M
bytes)
CS1
4M bytes (2)
External Space 0
SFR
Internal RAM
Reserved Space
Mode 2
NOTES:
1. 20000016–00800016=2016K bytes. 32K bytes less than 2M bytes.
2. 40000016–00800016=4064K bytes. 32K bytes less than 4M bytes.
Reserved Space
Internal ROM
CS0, 1M byte
External Space 3
Not Used
CS3, 1M byte
External Space 2
(Cannot be used
as DRAMconnectable
space or external
space)
Not Used
Not Used
CS1, 1M byte
External Space 0
CS2, 1M byte
External Space 1
Not Used
SFR
Internal RAM
Reserved Space
Mode 3
CS0, 1M byte
External Space 3
Not Used
CS3, 1M byte
External Space 2
(Cannot be used
as DRAMconnectable
space or external
space)
Not Used
Not Used
CS1, 1M byte
External Space 0
CS2, 1M byte
External Space 1
Not Used
SFR
Internal RAM
Reserved Space
Mode 3
M32C/83 Group (M32C/83, M32C/83T)
6. Processor Mode
7. Bus
M32C/83 Group (M32C/83, M32C/83T)
7. Bus
In memory expansion mode or microprocessor mode, some pins function as bus control pins to input and
______
_______
_______ ________ ______ _________
output data from external devices. A0 to A22, A23, D0 to D15, MA0 to MA12, CS0 to CS3, WRL/WR/CASL,
_________ _______ __________ _____ ______
_________
_________
_______
_______
WRH/BHE/CASH, RD/DW, BCLK/ALE, HLDA/ALE, HOLD, ALE/RAS, and RDY are used as bus control
pins.
NOTE
Bus control pins in M32C/83T cannot be used.
7.1 Bus Settings
The BYTE pin, the DS register, the PM05 to PM04 bits in the PM0 register and the PM11 to PM10 bits in
the PM1 register determine bus settings.
Table 7.1 lists how to change a bus setting. Figure 7.1 shows the DS register.
Table 7.1 Bus Settings
Bus Setting
Selecting external address bus width
Setting bus width after reset
Switching between separate bus or multiplexed bus
Number of chip-select
Changed By
DS register
BYTE pin (external space 3 only)
PM05 to PM04 bits in PM0 register
PM11 to PM10 bits in PM1 register
External Data Bus Width Control Register(2)
b7
b6
b5
b4
b3
b2
b1
Symbol
DS
b0
Bit
Symbol
Address
000B16
Bit Name
After Reset
XXXX 10002 (BYTE pin = "L")
XXXX 00002 (BYTE pin = "H")
Function
RW
DS0
External Space 0 Data
Bus Width Select Bit
0 : 8 bits wide
1 : 16 bits wide
RW
DS1
External Space 1 Data
Bus Width Select Bit
0 : 8 bits wide
1 : 16 bits wide
RW
DS2
External Space 2 Data
Bus Width Select Bit
0 : 8 bits wide
1 : 16 bits wide
RW
DS3
External Space 3 Data
Bus Width Select Bit(1)
0 : 8 bits wide
1 : 16 bits wide
RW
(b7 - b4)
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
NOTES:
1. After reset, the DS3 bit is set to "1" when the BYTE pin is held "L". It is set to "0" when the BYTE pin
is held "H".
2. The DS register in the M32C/83T cannot be used.
Figure 7.1 DS Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 52 of 488
M32C/83 Group (M32C/83, M32C/83T)
7. Bus
7.1.1 Selecting External Address Bus
The number of externally-output address bus, chip-select signals and chip-select-assigned address
_____
space (CS area) varies depending on each external space mode. The PM11 to PM10 bits in the PM1
register determine the external space mode.
When using the DRAMC, row addresses and column addresses are multiplexed to output in the DRAM
area.
7.1.2 Selecting External Data Bus
The DS register selects either external 8-bit or 16-bit data bus per external space. The data bus in the
external space 3, after reset, becomes 16 bits wide when an "L" signal is applied to the BYTE pin and 8
bits wide when an "H" signal is applied. Do not change the BYTE pin level while the microcomputer is
operating. The internal bus is always 16 bits wide.
7.1.3 Selecting Separate/Multiplexed Bus
The PM05 to PM04 bits in the PM0 register determine either a separate or multiplexed bus as bus format .
7.1.3.1 Separate Bus
The separate bus is a bus format which allows the microcomputer to input and output data and address using separate buses. The DS register selects 8-bit or 16-bit data bus as the external data bus
per external space. If all DSi bits in the DS register (i=0 to 3) are set to "0" (8-bit data bus), port P0
becomes the data bus and port P1 becomes the programmable I/O port. If one of the DSi bits is set to
"1" (16-bit data bus), ports P0 and P1 become the data bus. When the microcomputer accesses a
space while the DSi bit set to "0", port P1 is indeterminate.
If the microcomputer accesses a space with the separate bus, the WCR register determines the number of software wait states inserted.
7.1.3.2 Multiplexed Bus
The multiplexed bus is a bus format which allows the microcomputer to input and output data and
address via bus by timesharing. D0 to D7 are multiplexed with A0 to A7 in space accessed by the 8-bit
data bus. D0 to D15 are multiplexed with A0 to A15 in space accessed by the 16-bit data bus. If the
microcomputer accesses a space with the multiplexed bus, the WCR register can be set to either two
wait states or three wait states. Two-wait-state access is automatically selected if the WCR register is
set to no wait state or one wait state. Refer to 7.2.4 Bus Timing for details.
The microcomputer starts operation using the separate bus after reset. Therefore, the multiplexed bus
_______
_______
_____
can be assigned to access the CS1 area, the CS2 area, or all CS areas. However, the multiplexed bus
_____
cannot be assigned to access all CS areas in microprocessor mode. When the PM05 and PM04 bits
_____
in the PM0 register are set to "112" (access all CS areas with the bus), only 16 low-order bits, from A0
to A15, of an address are output. See Table 7.2 for details.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 53 of 488
7. Bus
M32C/83 Group (M32C/83, M32C/83T)
Table 7.2 Processor Mode and Port Function
Processor
Mode
SingleChip Mode
PM05 to
PM04 Bits in
PM0 Register
Memory Expansion Mode/ Microprocessor Mode
Memory Expansion Mode
"112"(1)
"012", "102"
"002"
Access CS1 or CS2 using
the Multiplexed Bus
Access All Other CS Areas using
the Separate Bus
Access all CS Areas using
the Separate Bus
Access all CS Areas using
the Multiplexed Bus
Access all
Access one or more
Access all
Access one or more
Access all
Access one or more
external space with external space with external space with external space with external space with external space with
8-bit data bus
16-bit data bus
8-bit data bus
16-bit data bus
8-bit data bus
16-bit data bus
Data Bus Width
Data bus
Data bus
Data bus
Data bus
D0 to D7
D0 to D7
D0 to D7
D0 to D7
I/O port
I/O port
I/O port
Data bus
I/O port
Data bus
I/O port
I/O port
P00 to P07
I/O port
P10 to P17
I/O port
P20 to P27
I/O port
Address bus/
Data bus(2)
A0/D0 to A7/D7
P30 to P37
I/O port
P40 to P43
I/O port
P44 to P46
I/O port
CS (Chip-select signal) or Address bus (A20 to A22)
(Refer to 7.2 Bus Control for details)(4)
P47
I/O port
CS (Chip-select signal) or Address bus (A23)
(Refer to 7.2 Bus Control for details)(4)
P50 to P53
I/O port
Outputs RD, WRL, WRH and BCLK or outputs RD, BHE, WR and BCLK
(Refer to 7.2 Bus Control for details)(3)
P54
I/O port
HLDA (3)
HLDA (3)
HLDA (3)
HLDA (3)
HLDA (3)
HLDA (3)
P55
I/O port
HOLD
HOLD
HOLD
HOLD
HOLD
HOLD
P56
I/O port
RAS (3)
RAS (3)
RAS (3)
RAS (3)
RAS (3)
RAS (3)
P57
I/O port
RDY
RDY
RDY
RDY
RDY
RDY
D8 to D15
D8 to D15
Address bus/
Data bus(2)
A0/D0 to A7/D7
Address bus
A0 to A7
Address bus
A0 to A7
Address bus/
Data bus
A0/D0 to A7/D7
Address bus/
Data bus
A0/D0 to A7/D7
Address bus
A8 to A15
Address bus/
Data bus(2)
A8/D8 to A15/D15
Address bus
A8 to A15
Address bus
A8 to A15
Address bus
A8 to A15
Address bus/
Data bus
A8/D8 to A15/D15
Address bus
A16 to A19
Address bus
A16 to A19
Address bus
A16 to A19
Address bus
A16 to A19
I/O port
NOTES:
1. The PM05 to PM04 bits cannot be set to "112" (access all CS areas using multiplexed bus) in
microprocessor mode because the microcomputer starts operation using the separate bus after reset.
When the PM05 to PM04 bits are set to "112" in memory expansion mode, the microcomputer accesses
64K-byte memory space per chip select using the address bus .
2. These ports become address buses when accessing space using the separate bus.
3. The PM15 to PM14 bits in the PM1 register determine which pin outputs the ALE signal. The PM02 bit in
the PM0 register selects either "WRL,WRH" or "BHE,WR" combination. P56 provides an indeterminate
output when the PM15 and PM14 bits to "002" (no ALE). It cannot be used as an I/O port.
4. When DRAMC is selected to access DRAM area, CASL, CASH, DW, BCLK become output pins.
5. The PM11 to PM10 bits in the PM1 register determine the CS signal and address bus.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 54 of 488
I/O port
7. Bus
M32C/83 Group (M32C/83, M32C/83T)
7.2 Bus Control
Signals required to access external devices are provided and software wait states are inserted as follows.
The signals are available in memory expansion mode and microprocessor mode only.
7.2.1 Address Bus and Data Bus
______
______
The address bus is a signal accessing 16M-byte space and uses 24 control pins; A0 to A22 and A23. A23
is the inversed output signal of the highest-order address bit.
The data bus is a signal which inputs and outputs data. The DS register selects the 8-bit data bus from D0
to D7 or the 16-bit data bus from D0 to D15 for each external space. When applying an "H" signal to the
BYTE pin, the data bus accessing the external memory space 3 becomes the 8-bit data bus after reset.
When applying an "L" signal to the BYTE pin, the data bus accessing the external memory space 3
becomes the 16-bit data bus.
When changing single-chip mode to memory expansion mode, the address bus is in an indeterminate
state until the microcomputer accesses an external memory space.
When using the DRAMC to access DRAM area, row addresses and column addresses are multiplexed
and output via A8 to A20.
7.2.2 Chip-Select Signal
_____
The chip-select signal shares ports with A0 to A22 and A23. The PM11 to PM10 bits in the PM1 register
_____
determine which CS area is accessed and how many chip-select signals are output. A maximum of four
chip-select signals can be output.
_____
In microprocessor mode, the chip-select signal is not output after reset. A23, however, can perform as the
chip-signal signal.
______
The chip-select signal becomes "L" while the microcomputer accesses the external CSi area (i=0 to 3). It
becomes high ("H") when the microcomputer accesses another external memory space or an internal
memory space. Figure 7.2 shows an example of the address bus and chip-select signal output.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 55 of 488
7. Bus
M32C/83 Group (M32C/83, M32C/83T)
Example 2:
Example 1:
When the microcomputer accesses the external
space j specified by another chip-select signal in the
next cycle after having accessed the external space i,
both address bus and chip-select signal change.
Access
External
Space i
Data Bus
Address Bus
When the microcomputer accesses the SFR or the
internal ROM/RAM area in the next cycle after
having accessed an external space, the chip-select
signal changes but the address bus does not.
Access
External
Space
Access
External
Space j
Data
Data
Data Bus
Data
Address Bus
Address
Chip-Select Signal
CSk
Access SFR,
Internal
ROM/RAM
Area
Address
Chip-Select Signal
CSk
Chip-Select Signal
CSp
i = 0 to 3
k = 0 to 3
j = 0 to 3, excluding i
p= 0 to 3, excluding k
(See Figure 6.3 for i, j and p, k)
Example 3:
Example 4:
When the microcomputer accesses the space i
specified by the same chip-select signal in the next
cycle after having accessed the external space i,
the address bus changes but the chip-select signal
does not.
Access
External
Space i
Data Bus
Address Bus
k = 0 to 3
When the microcomputer does not access any
space in the next cycle after having accessed an
external space (no pre-fetch of an instruction is
generated), neither address bus nor chip-select
signal changes.
Access
External
Space i
Data
Address
Chip-Select Signal
CSk
Data
Access
External
No Access
Space
Data
Data Bus
Address Bus
Address
Chip-Select Signal
CSk
i = 0 to 3
k = 0 to 3
k = 0 to 3
(See Figure 6.3 for i and k)
NOTES:
1. The above applies to the address bus and chip-select signal in two consecutive cycles.
By combining these examples, a chip-select signal extended by two or more cycles may be output.
Figure 7.2 Address Bus and Chip-Select Signal Outputs (Separate bus)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 56 of 488
7. Bus
M32C/83 Group (M32C/83, M32C/83T)
7.2.3 Read and Write Signals
_____
______
When set to the 16-bit data bus, the PM02 bit in the PM0 register selects a combination of the RD, WR
________
_____ ________
_________
and BHE signals or the RD, WRL and WRH signals to determine the read or write signal. When the DS3
_____ ______ ________
to DS0 bits in the DS register are set to "0" (8-bit data bus), set the PM02 bit to "0" (RD/WR/BHE). If any
of the DS3 to DS0 bits are set to "1" (16-bit data bus) when accessing an 8-bit space, the combination of
_____ ______
________
RD, WR and BHE is automatically selected regardless of the PM02 bit setting. Tables 7.3 and 7.4 list
each signal operations.
_____ ______
________
The RD, WR and BHE signals are combined for the read or write signal after reset.
_____ ________
_________
When changing the combination to RD, WRL and WRH, set the PM02 bit before writing data to an
external memory.
_____ ________
When using the DRAMC to access the DRAM with the 16-bit bus, set the PM02 bit to "1" (RD/ WRL/
_________
WRH).
_____
________
_________
Table 7.3 RD, WRL and WRH Signals
Data Bus
RD
WRL
WRH
L
H
H
H
L
H
16 Bits
H
H
L
H
L
L
L(1)
H
Not used
8 Bits
H(1)
L
Not used
NOTES:
______
________
1. The WR signal is used instead of the WRL signal.
_____
______
Status of External Data Bus
Read data
Write 1-byte data to even address
Write 1-byte data to odd address
Write data to both even and odd addresses
Write 1-byte data
Read 1-byte data
________
Table 7.4 RD, WR and BHE Signals
Data Bus
16 Bits
8 Bits
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
RD
H
L
H
L
H
L
H
L
WR
L
H
L
H
L
H
L
H
Page 57 of 488
BHE
L
L
H
H
L
L
Not used
Not used
A0
H
H
L
L
L
L
H/L
H/L
Status of External Data Bus
Write 1-byte data to odd address
Read 1-byte data from odd address
Write 1-byte data to even address
Read 1-byte data from even address
Write data to both even and odd addresses
Read data from both even and odd addresses
Write 1-byte data
Read 1-byte data
7. Bus
M32C/83 Group (M32C/83, M32C/83T)
7.2.4 Bus Timing
Bus cycle for the internal ROM and internal RAM are basically one BCLK cycle. When the PM12 bit in the
PM1 register is set to "1" (wait state), the bus cycles are two BCLK cycles.
Bus cycles for the SFR are basically two BCLK cycles. When the PM13 bit in the PM1 register is set to "1"
(2 wait states), the bus cycles are three BCLK cycles. To access CAN-associated registers (addresses
01E016 to 024516), set the PM13 bit to "1".
Bus cycle for an external space is basically one BCLK cycle for a read operation and two BCLK cycles for
a write operation. The WCR register inserts wait states equivalent to one to three BCLK cycles into an
external space. Bus cycles are two BCLK cycles if selecting one wait state. Bus cycles are four BCLK
cycles if selecting three wait states.
If applicable to the followings, bus cycles vary from those selected by the WCR register. Figure 7.5
shows each bit status and bus cycle.
• Write cycle with the separate bus and no wait state
• Read cycle and write cycle with the multiplexed bus and no wait state.
• Read cycle and write cycle with the multiplexed bus and one wait state.
Figure 7.3 shows the WCR register. Figures 7.4 and 7.5 show bus timing in an external space.
Wait Control Register(1, 2, 3)
b7
b6
b5
b4
b3
b2
b1
Symbol
WCR
b0
Bit
Symbol
Address
000816
After Reset
1111 11112
Bit Name
Function
RW
b1 b0
WCR0
External Space 0
Wait Bit
WCR1
0 0: No wait state
0 1: 1 wait state
1 0: 2 wait states
1 1: 3 wait states
RW
RW
b3 b2
WCR2
External Space 1
Wait Bit
WCR3
0 0: No wait state
0 1: 1 wait state
1 0: 2 wait states
1 1: 3 wait states
RW
RW
b5 b4
WCR4
External Space 2
Wait Bit
WCR5
0 0: No wait state
0 1: 1 wait state
1 0: 2 wait states
1 1: 3 wait states
RW
RW
b7 b6
WCR6
External Space 3
Wait Bit
WCR7
0 0: No wait state
0 1: 1 wait state
1 0: 2 wait states
1 1: 3 wait states
RW
RW
NOTES:
1. When using the multiplexed bus, "2 waits" is selected even if the WCR register is set to "002" (no
wait state) or "012" (1 wait state). "102" (2 wait states) and "112" (3 wait states) can be selected.
2. When using the separate bus, the read bus runs one BCLK cycle and the write bus runs two
BCLK cycles (1 wait state) if the WCR register is set to "002".
3.The WCR register cannot be used in M32C/83T.
Figure 7.3 WCR Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 58 of 488
7. Bus
M32C/83 Group (M32C/83, M32C/83T)
Table 7.5 Software Wait State and Bus Cycle
Space
External
Bus Status
PM1 Register
PM13 Bit
WCR Register
PM12 Bit
WCRj to WCRi Bits
2 BCLK cycles
0
SFR
0
3 BCLK cycles
1 BCLK cycle
1
2 BCLK cycles
1
Internal
ROM/RAM
Separate Bus
External
Memory
Multiplexed Bus
i = 0, 2, 4, 6 j = i + 1
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 59 of 488
Bus Cycle
002
Read :1 BCLK cycle
Write : 2 BCLK cycles
012
2 BCLK cycles
102
3 BCLK cycles
112
4 BCLK cycles
002
3 BCLK cycle
012
3 BCLK cycles
102
3 BCLK cycles
112
4 BCLK cycles
7. Bus
M32C/83 Group (M32C/83, M32C/83T)
(1) Separate Bus with No Wait State
Bus cycle(1)
Bus cycle(1)
BCLK
Write Signal
Read Signal
Data Bus
Output
Address Bus(2)
Address
Input
Address
Chip-Select Signal(2, 3)
(2) Separate Bus with 1 Wait State
Bus cycle(1)
Bus cycle(1)
BCLK
Write Signal
Read Signal
Output
Data Bus
Address Bus(2)
Address
Input
Address
Chip-Select Signal(2, 3)
(3) Separate Bus with 2 Wait States
Bus cycle(1)
Bus cycle(1)
BCLK
Write Signal
Read Signal
Data Bus
Data Output
Address Bus(2)
Address
Input
Address
Chip-Select Signal(2, 3)
NOTES:
1. This example illustrates bus cycle length. Read cycle and write cycle may occur consecutively.
2. The address bus and chip-select signal may be extended depending on CPU state such as an
instruction queue buffer.
3. When the microcomputer continuously accesses the same external space (same CS area), the chipselect signal may be output continuously.
Figure 7.4 External Bus Operation with Software Wait State (1)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 60 of 488
7. Bus
M32C/83 Group (M32C/83, M32C/83T)
(1) Separate Bus with 3 Wait States
Bus cycle(1)
Bus cycle(1)
BCLK
Write Signal
Read Signal
Data output
Data Bus
Address Bus(2)
Input
Address
Address
Chip-Select
Signal(2, 3)
(2) Multiplexed Bus with 2 Wait States
Bus cycle(1)
Bus cycle(1)
BCLK
Write Signal
Read Signal
ALE
Address Bus
Address
Address Bus/Data Bus(2)
Address
Data output
Address
Address
Input
Chip-Select Signal(2, 3)
(3) Multiplexed Bus with 3 Wait States
Bus cycle(1)
Bus cycle(1)
BCLK
Write Signal
Read Signal
Address Bus
Address
Address Bus/
Data Bus(2)
Address
Data output
Address
Address
Input
ALE
Chip-Select
Signal(2, 3)
NOTES:
1. This example illustrates bus cycle length. Read cycle and write cycle may occur consecutively.
2. The address bus and chip-select signal may be extended depending on CPU state such as an
instruction queue buffer.
3. When the microcomputer continuously accesses the same external space (same CS area), the chipselect signal may be output continuously.
Figure 7.5 External Bus Operation with Software Wait State (2)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 61 of 488
7. Bus
M32C/83 Group (M32C/83, M32C/83T)
7.2.5 ALE Signal
The ALE signal latches an address of the multiplexed bus. Latch an address on the falling edge of the
ALE signal. The PM15 to PM14 bits in the PM1 register determine the output pin for the ALE signal.
The ALE signal is output to an internal space and external space.
(2) 16-Bit Data Bus
(1) 8-Bit Data Bus
ALE
ALE
D0/A0 to D7/A7
Address
Data
A8 to A15
Address
A16 to A19
Address
A20/CS3
A21/CS2
A22/CS1
A23/CS0
(1)
(2)
Address or CS
D0/A0 to D15/A15
A16 to A19
A20/CS3
A21/CS2
A22/CS1
A23/CS0
Address
(1)
Data
Address (2)
Address or CS
NOTES:
1. D0/A0 to D7/A7 are placed in high-impedance state when read.
2. When the multiplexed bus is selected for all CS areas, the address bus becomes an I/O port.
Figure 7.6 ALE Signal and Address/Data Bus
_______
7.2.6 RDY Signal
_______
The RDY signal facilitates access to external devices which need longer access time. When an "L" signal
________
is applied to the RDY pin on the falling edge of last BCLK of the bus cycle, wait states are inserted into the
________
bus cycle. When an "H" signal is applied to the RDY pin on the falling edge of the BCLK, the bus cycle
starts running again.
________
Table 7.6 lists microcomputer states when the RDY signal inserts wait states into the bus cycle. Figure
_____
________
7.7 shows an example of the RD signal extended by the RDY signal.
Table 7.6 Microcomputer States in a Wait State(1)
Item
State
Oscillation
On
_____
_____
_____
________
RD Signal, WR Signal, Address Bus, CSi (i=0 to 3),
Maintains the same state as when RDY signal
__________
Data Bus, ALE Signal, HLDA, Programmable I/O Ports
was received
Internal Peripheral Circuits
On
NOTES:
________
1. The RDY signal cannot be accepted immediately before software wait states are inserted.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 62 of 488
7. Bus
M32C/83 Group (M32C/83, M32C/83T)
(1) Separate Bus with 2 Wait States
1st cycle
2nd cycle
3rd cycle
4th cycle
BCLK
AAAAAAA
RD
CSi
(1)
(i=0 to 3)
RDY
tsu(RDY - BCLK)
Timing to receive RDY
(2) Multiplexed Bus with 2 Wait States
1st cycle
2nd cycle
3rd cycle
4th cycle
BCLK
AAAAAA
AAAAAA
RD
CSi
(1)
(i=0 to 3)
RDY
tsu(RDY - BCLK)
Timing to receive RDY
AA
: Wait states inserted by RDY
: Wait states inserted by program
tsu(RDY-BCLK): Setup time for RDY input
Timing to receive RDY for j wait(s): j+1 cycles (j = 1 to 3)
NOTES:
1. The chip-select signal (CSi) may be extended depending on CPU state such as the instruction
queue buffer.
_____
________
Figure 7.7 RD Signal Output Extended by RDY Signal
_________
7.2.7 HOLD Signal
__________
The HOLD signal transfers bus privileges from the CPU to external circuits. When an "L" signal is applied
__________
__________
to the HOLD pin , the microcomputer enters a hold state after bus access is completed. While the HOLD
_________
pin is held "L", the microcomputer is in a hold state and the HLDA pin outputs an "L" signal. Table 7.7
shows the microcomputer status in a hold state.
__________
Bus is used in the following order of priority: HOLD, DMAC, CPU.
__________
HOLD > DMAC > CPU
Figure 7.8 Order of Bus Priority
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 63 of 488
7. Bus
M32C/83 Group (M32C/83, M32C/83T)
Table 7.7 Microcomputer Status in a Hold State
Item
Status
Oscillation
_____
_____
_______
RD Signal, WR Signal, Address Bus, Data Bus, BHE,
_______
_______
CS0 to CS3
Programmable I/O Ports: P0 to P15
On
High-impedance
__________
Maintains the same state as when HOLD signal
is received
Output "L"
On (excluding the watchdog timer)
Output "L"
__________
HLDA
Internal Peripheral Circuits
ALE Signal
7.2.8 External Bus State when Accessing Internal Space
Table 7.8 shows external bus states when an internal space is accessed.
Table 7.8 External Bus State when Accessing Internal Space
Item
Address bus
Data Bus
When Read
When Write
_____ ______ ________ _________
RD, WR, WRL, WRH
________
BHE
_______
_______
CS0 to CS3
ALE
State when accessing SFR, internal ROM and internal RAM
Holds an address of an external space accessed just before
High-impedance
High-impedance
Output "H"
Holds state of external space last accessed
Output "H"
Output ALE
7.2.9 BCLK Output
The CPU clock operates the CPU. When combining the PM07 bit in the PM0 register set to "0" (BCLK
output) and the CM01 to CM00 bits in the CM0 register set to "002", the CPU clock signal is output from
P53 as BCLK.
No BCLK is output in single-chip mode. Refer to 8. Clock Generating Circuit for details.
_______
__________
__________
_____
7.2.10 DRAM Control Signals (RAS, CASL, CASH and DW)
The DRAM control signals control the DRAM. The DRAM control signals are output when the DRAM
area, determined by the AR0 to AR2 bits in the DRAMCONT register, is output. Table 7.9 lists each
signal operation.
_______
__________
__________
_____
Table 7.9 RAS, CASL, CASH and DW Signals
Data Bus Width
16 bits
8 bits
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
RAS
L
L
L
L
L
L
L
L
CASL
L
L
H
L
L
H
L
L
Page 64 of 488
CASH
L
H
L
L
H
L
Not used
Not used
DW
H
H
H
L
L
L
H
L
Data Bus State
Read data from both even and odd addresses
Read 1-byte data from even address
Read 1-byte data from odd address
Write data to both even and odd addresses
Write 1-byte data to even address
Write 1-byte data to odd address
Read 1-byte data
Write 1-byte data
8. Clock Generation Circuit
M32C/83 Group (M32C/83, M32C/83T)
8. Clock Generation Circuit
8.1 Types of Clock Generation Circuits
Four circuits are incorporated to generate the system clock signal :
• Main clock oscillation circuit
• Sub clock oscillation circuit
• On-chip oscillator
• PLL frequency synthesizer
Table 8.1 lists specifications of the clock generation circuit. Figure 8.1 shows a block diagram of the clock
generation circuit. Figures 8.2 to 8.8 show registers controlling the clock.
Table 8.1 Clock Generation Circuit Specifications
Item
Main Clock
Oscillation Circuit
Sub Clock
Oscillation Circuit
On-chip Oscillator
PLL Frequency
Synthesizer
• CPU clock source
• Peripheral function
clock source
Use
• CPU clock source • CPU clock source • CPU clock source
• Peripheral function • Timer A and B
• Peripheral function
clock source
clock source
clock source
Clock Frequency
Up to 32 MHz
Connectable
Oscillator or
Additional Circuit
Pins for
Oscillator or for
Additional Circuit
Oscillation Stop/
Restart Function
• Ceramic resonator • Crystal oscillator
• Crystal oscillator
• Low pass filter
XIN, XOUT
XCIN, XCOUT
Available
Available
Available
VCOUT (connect to
low pass filter)
P86 (connect to Vss)
Available
Oscillator State
After Reset
Oscillating
Stopped
Stopped
Stopped
Other
External clock can
be input
External clock can
be input. The PLL
frequency
synthesizer cannot
be used when using
the sub clock
oscillation circuit.
When the main clock stops
oscillating, the on-chip
oscillator starts oscillating
automatically and
becomes the clock source
for the CPU and peripheral
functions
The sub clock
cannot be used
when using the PLL
frequency
synthesizer
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 65 of 488
32.768 kHz
Approximatly 1 MHz
20 MHz to 32 MHz (
See Table 8.2)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Figure 8.1 Clock Generation Circuit
Page 66 of 488
Clock Edge Detect
/Charge and
Discharge
Circuit Control
Charge and
Discharge
Circuit
CM0i : Bit in CM0 register
CM1i : Bit in CM1 register
CM2i : Bit in CM2 register
CM10 = 1 (stop mode)
S Q
R
S Q
R
CM02
CLKOUT
CM04
CM05
On-chip Oscillator
Watchdog Timer
Interrupt Request
Circuit to Generate
Oscillation Stop
Detect Interrupt
Request
XOUT
On-chip Oscillator
XCOUT
Sub Clock
CM17
0
0
1
CM21
fC
1/32
1
0
fC32
Divider
Reset
CPSR=1
1/2
1/2n
(Note 2)
1/m
CST
1/2
1/2
CM07
1/2
1/2
fAD
BCLK
CPU Clock
f2n(1)
f8
f32
f1
b
CM21 Switch
Signal
On-chip
Oscillator
Clock
Interrupt
Request Signal
c
Phase
Comparator
PLC07 : Bit in PLC0 register
PLC11, PLC12 : Bits in PLC1 register
Reference
Frequency Counter
Programmable
Counter
PLL Frequency Synthesizer
Charge
Pump
PLC07
Voltage
Controlled
Oscillator
(VCO)
1/3
1/2
VCONT
PLC12
PLC11
PLL Clock
e
NOTES:
1. The CNT3 to CNT0 bits in the TCSRR register select no division (n=0) or divide-by-2n (n=1 to 15).
2. The MCD4 to MCD0 bits in the MCD register select divide-by-m (m=1,2,3,4,6,8,10,12,14,16 ).
XCIN
b
1
e
Main Clock
c PLL Frequency
Synthesizer
a
Sub Clock Oscillation Circuit
XIN
Main Clock Oscillation Circuit
CST : Bit in TCSPR register
CPSR : Bit in CPSRF register
CM01 to CM00
11
Output to determine an
interrupt request level
NMI
RESET
Software Reset
On-chip Oscillator
a
01
10
WAIT Instruction (wait mode)
Port P53
fC
f8
f32
00
Peripheral Function Clock
M32C/83 Group (M32C/83, M32C/83T)
8. Clock Generation Circuit
8. Clock Generation Circuit
M32C/83 Group (M32C/83, M32C/83T)
System Clock Control Register 0(1)
b7
b6
b5
b4
b3
b2
b1
b0
1
Symbol
Address
After Reset
CM0
000616
0000 X0002
Bit
Symbol
Bit Name
Function
b1 b0
CM00
Clock Output Function
Select Bit(2)
CM01
0 0 : I/O port P53
0 1 : Outputs fC
1 0 : Outputs f8
1 1 : Outputs f32
RW
RW
RW
In Wait Mode,
Peripheral
Function Clock Stop Bit
0 : Peripheral clock does not stop in
wait mode
RW
1 : Peripheral clock stops in wait
mode(3)
Reserved Bit
Set to "1"
CM04
Port XC Switch Bit
0 : I/O port function
RW
1 : XCIN-XCOUT oscillation function(4)
CM05
Main Clock (XIN-XOUT)
Stop Bit(5)
0 : Main clock oscillates
1 : Main clock stops(6)
RW
CM06
Watchdog Timer
Function Select Bit
0 : Watchdog timer interrupt
1 : Reset(7)
RW
CM07
System Clock Select Bit(8)
0: Clock selected by the CM21 bit
divided by MCD register setting
1: Sub clock
CM02
(b3)
RW
RW
NOTES:
1. Rewrite the CM0 register after the PRC0 bit in the PRCR register is set to "1" (write enable).
2. When the PM07 bit in the PM0 register is set to "0" (BCLK output), set the CM01 to CM00 bits to
"002". When the PM15 to PM14 bits in the PM1 register is set to "012" (ALE output to P53), set the
CM01 to CM00 bits to "002". When the PM07 bit is set to "1" (function selected in the CM01 to CM00
bits) in microprocessor or memory expansion mode, and the CM01 to CM00 bits are set to "002", an
"L" signal is output from port P53 (port P53 does not function as an I/O port).
3. fc32 does not stop. When the CM02 bit is set to "1", the PLL clock cannot be used in wait mode.
4. When setting the CM04 bit to "1" (XCIN-XCOUT oscillation), set the PD8_7 to PD8_6 bits to "002" (with
port P87 and P86 input mode) and the PU25 bit in the PUR2 register to "0" (no pull-up).
5. When entering the low-power consumption mode or on-chip oscillator low-power consumption mode,
the CM05 bit stops the main clock. The CM05 bit cannot detect whether the main clock stops or not.
To stop the main clock, set the CM05 bit to "1" after the CM07 bit is set to "1" with a stable sub clock
oscillation or after the CM21 bit in the CM2 register is set to "1" (on-chip oscillator clock). When the
CM05 bit is set to "1", XOUT becomes "H". The built-in feedback resistor remains on. XIN is pulled up
to XOUT ("H" level) via the feedback resistor.
6. When the CM05 bit is set to "1", the MCD register is set to "0816" (divide-by-8 mode). In on-chip
oscillation mode, the MCD register is not divided by eight even if the CM05 bit terminates XIN-XOUT.
7. Once the CM06 bit is set to "1", it cannot be set "0" by program.
8. After the CM04 bit is set to "1" with a stable sub clock oscillation, set the CM07 bit to "1" from "0".
After the CM05 bit is set to "0" with a stable main clock oscillation, set the CM07 bit to "0" from "1".
Do not set the CM07 bit and CM04 or CM05 bits simultaneously.
Figure 8.2 CM0 Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 67 of 488
8. Clock Generation Circuit
M32C/83 Group (M32C/83, M32C/83T)
System Clock Control Register 1(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
CM1
0 1 0 0 0 0
Bit
Symbol
CM10
(b4 - b1)
Address
000716
After Reset
0010 00002
Bit Name
Function
All Clock Stop
Control Bit(2)
0 : Clock oscillates
1 : All clocks stop (stop mode)(3)
RW
Reserved Bit
Set to "0"
RW
Reserved Bit
Set to "1"
RW
Reserved Bit
Set to "0"
RW
CPU Clock Select
Bit 2(4)
0 : Main clock
1 : PLL clock
RW
(b5)
(b6)
CM17
RW
NOTES:
1. Rewrite the CM1 register after the PRC0 bit in the PRCR register is set to "1" (write enable).
2. When the CM10 bit is set to "1", XOUT becomes "H" and the internal feedback resistance is disabled.
XIN, XCIN and XCOUT are placed in high-impedance states.
3. When the CM10 bit is set to "1", the MCD register is set to "0816" (divide-by-8 mode). When the
CM20 bit is set to "1" (oscillation stop detect function enabled) or the CM21 bit to "1" (on-chip
oscillator selected), do not set the CM10 bit to "1".
4. CM17 bit is enabled only when the CM21 bit in the CM2 register is set to "0". Use the procedure
shown in Figure 8.13 to set the CM17 bit to "1".
Figure 8.3 CM1 Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 68 of 488
8. Clock Generation Circuit
M32C/83 Group (M32C/83, M32C/83T)
Main Clock Division Register(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
MCD
Bit
Symbol
Address
000C16
After Reset
XXX010002
Bit Name
Function
RW
b4 b3 b2 b1 b0
MCD0
MCD1
MCD2
MCD3
MCD4
(b7 - b5)
Main Clock Division
Select Bit(2, 4)
1 0 0 1 0 : Divide-by-1(no division)
mode
0 0 0 1 0 : Divide-by-2 mode
0 0 0 1 1 : Divide-by-3 mode
0 0 1 0 0 : Divide-by-4 mode
0 0 1 1 0 : Divide-by-6 mode
0 1 0 0 0 : Divide-by-8 mode
0 1 0 1 0 : Divide-by-10 mode
0 1 1 0 0 : Divide-by-12 mode
0 1 1 1 0 : Divide-by-14 mode
0 0 0 0 0 : Divide-by-16 mode
(Note 3)
RW
RW
RW
RW
RW
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
NOTES:
1. Rewrite the MCD register after the PRC0 bit in the PRCR register is set to "1" (write enable).
2. While the microcomputer is in stop mode or low-power consumption mode, the MCD register is set to
"0816" (divide-by-8 mode).
In on-chip oscillator mode, divide-by-8 mode cannot be entered even if the CM05 bit in the CM0
register is set to "1"(XIN-XOUT stopped).
3. Do not set to bit combinations not listed above.
4. Access CAN-associated register addresses (addresses 01E016 to 024516) after setting the MCD
register to "1216" (no division mode).
Figure 8.4 MCD Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 69 of 488
8. Clock Generation Circuit
M32C/83 Group (M32C/83, M32C/83T)
Oscillation Stop Detect Register(1)
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0
Symbol
Address
CM2
000D16
After Reset
0016
Bit
Symbol
Bit Name
CM20
Oscillation Stop Detect
Enable Bit
0: Disables oscillation stop detect function
RW
1: Enables oscillation stop detect function
CM21
CPU Clock Select Bit(2, 3)
0: Clock selected by the CM17 bit
1: On-chip oscillator clock
RW
CM22
Oscillation Stop Detect
Flag(4)
0: Main clock does not stop
1: Detects main clock stop
RW
CM23
XIN Clock Monitor Flag(5)
0: Main clock oscillates
1: Main clock stops
RO
Reserved Bit
Set to "0"
RW
(b7 - b4)
Function
RW
NOTES:
1. Rewrite the CM2 register after the PRC0 bit in the PRCR register is set to "1" (write enable).
2. When the main clock oscillation stop is detected while the CM20 bit is set to "1" (oscillation stop
detect function enabled), the CM21 bit is set to "1". Although the main clock starts oscillating, the
CM21 bit is not set to "0". When the main clock is used as a CPU clock source after the main clock
resumes oscillation, set the CM21 bit to "0" by program.
3. When the CM20 bit is set to "1" (oscillation stop detect function enabled) and the CM22 bit is set to "1", do
not set the CM21 bit to "0".
4. When a main clock stop is detected, the CM22 bit is set to "1". The CM22 bit can only be set to "0",
not "1", by program.
If the CM22 bit is set to "0" by program while the main clock is stopped, the CM22 bit cannot be set to
"1" until the next main clock stop is detected.
5. Determine the main clock state by reading the CM23 bit several times after the oscillation stop
interrupt is generated.
Figure 8.5 CM2 Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 70 of 488
8. Clock Generation Circuit
M32C/83 Group (M32C/83, M32C/83T)
Count Source Prescaler Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
After Reset(2)
TCSPR
035F16
0XXX 00002
Bit
Symbol
Bit Name
Function
CNT0
RW
CNT1
CNT2
RW
Division Rate
Select Bit(1)
If setting value is n, f2n is divided
the main clock, on-chip oscillator
clock or PLL clock by 2n.
When n is set to "0", no division is
selected.
CNT3
RW
RW
RW
Nothing is assigned. When write, set to "0".
(b6 - b4) When read, its content is indeterminate.
CST
Operation Enable Bit
0: Divider stops
1: Divider starts
RW
NOTES:
1. Rewrite the CNT3 to CNT0 bits after the CST bit is set to "1".
2. Value of the TCSPR register is not reset by software reset or watchdog timer reset.
Clock Prescaler Reset Flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
CPSRF
Bit
Symbol
Address
034116
Bit Name
After Reset
0XXX XXXX2
Function
RW
Nothing is assigned. When write, set to "0".
(b6 - b0) When read, its content is indeterminate.
CPSR
Clock Prescaler Reset
Flag
Figure 8.6 TCSPR and CPSRF Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 71 of 488
When the CPSR bit is set to "1", fC
divided by 32 is reset.
When read, its content is "0".
RW
8. Clock Generation Circuit
M32C/83 Group (M32C/83, M32C/83T)
PLL Control Register 0(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PLC0
0 0 1
Bit
Symbol
Address
037616
After Reset
0011 X1002
Function
Bit Name
PLC00
PLC01
RW
Programmable Counter
Select Bit(2)
See Table 8.2
RW
PLC02
(b3)
(b4)
(b5)
(b6)
PLC07
RW
RW
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Reserved Bit(2)
Set to "1"
RW
Reserved Bit(2)
Set to "0"
RW
Reserved Bit
Set to "0"
RW
Operation Enable Bit(3, 4)
0: PLL is Off
1: PLL is On
RW
NOTES:
1. Rewrite the PLC0 register after the PRC0 bit in the PRCR register is set to "1" (write enable).
2. Set these bits when the PLC07 bit is set to "0". Once these bits are set, they cannot be changed.
3. To use the PLL function, the PD8_7 bit in the PD8 register is set to "0" (input) and the CM04 bit in the
CM0 register is set to "0" (I/O port). Set the PD8_6 bit in the PD8 register to "0" (input) before
connecting P86 to Vss.
4. Before the microcomputer enters wait or stop mode, set the CM17 bit to "0" (main clock as CPU clock
source), the PLC07 bit to "0" and PLV00 bit to "0" (cut off power to PLL) in this order.
VDC Control Register for PLL(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PLV
0
Bit
Symbol
PLV00
(b1)
Address
001716
After Reset
XXXX XX012
Bit Name
Function
RW
PLL VDC Enable Bit(2)
0 : Cut off power to PLL
1 : Power to PLL
RW
Reserved Bit
Set to "0"
RW
Nothing is assigned. When write, set to "0".
(b7 - b2) When read, its content is indeterminate.
NOTES:
1. Rewrite the PLV register after the PRC3 bit in the PRCR register is set to "1" (write enable).
2. Before the microcomputer enters wait or stop mode, set the CM17 bit to "0" (main clock as CPU
clock source), the PLC07 bit to "0" (PLL off) and PLV00 bit to "0" (cut off power to PLL) in this order.
Figure 8.7 PLC0 and PLV Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 72 of 488
8. Clock Generation Circuit
M32C/83 Group (M32C/83, M32C/83T)
PLL Control Register 1(1, 2)
b7
b6
b5
b4
b3
b2
b1
0
b0
Symbol
PLC1
0
Bit
Symbol
Address
037716
After Reset
XXXX 00002
Bit Name
Function
RW
Reserved Bit
Set to "0"
PLC11
PLL Clock Division
Enable Bit(3)
0 : Disables the PLL clock to be divided
RW
1 : Enables the PLL clock to be divided
PLC12
PLL Clock Division
Switch Bit(4)
0 : Divide-by-2
1 : Divide-by-3
RW
Reserved Bit
Set to "0"
RW
(b0)
(b3)
RW
Nothing is assigned. When write, set to "0".
(b7 - b4) When read, its content is indeterminate.
NOTES:
1. Rewrite the PLC1 register after the PRC0 bit in the PRCR register is set to "1" (write enable).
2. Rewrite the PLC1 register after the CM17 bit in the CM1 register is set to "0" (main clock) .
3. When the CM21 bit in the CM2 register is set to "0" (clock selected by the CM17 bit), if the PLC11 bit
is set to "1" before the CM17 bit is set to "1" (PLL clock as CPU clock source), the PLL clock dividedby-2 or divided-by-3 becomes the clock source of the CPU clock and peripheral function clock.
4. Do not rewrite the PLC12 bit if the PLL clock is the CPU clock source.
Figure 8.8 PLC1 Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 73 of 488
8. Clock Generation Circuit
M32C/83 Group (M32C/83, M32C/83T)
8.1.1 Main Clock
Main clock oscillation circuit generates the main clock. The main clock becomes a clock source for the
CPU clock and peripheral function clock.
The main clock oscillation circuit is configured by connecting an oscillator or resonator between the XIN
and XOUT pins. The circuit has a built-in feedback resistor. The feedback resistor is separated from the
oscillation circuit in stop mode to reduce power consumption. The externally generated clock can be input
to the XIN pin in the main clock oscillation circuit. Figure 8.9 shows an example of a main clock circuit
connection. Circuit constants vary with each oscillator. Use the circuit constant recommended by each
oscillator manufacturer.
The main clock divided-by-eight becomes the CPU clock after reset.
To reduce power consumption, set the CM05 bit in the CM0 register to "1" (main clock stopped) after
switching the CPU clock source to the sub clock or on-chip oscillator clock. In this case, XOUT becomes
"H". XIN is pulled up by XOUT via the feedback resistor which remains on. When an externally generated
clock is input to the XIN pin, the main clock does not stop even if the CM05 bit is set to "1". Terminate main
clock operation externally if necessary.
All clocks, including the main clock, stop in stop mode. Refer to 8.5 Power Consumption Control for details.
Microcomputer
(Built-in Feedback Resistor)
Microcomputer
(Built-in Feedback Resistor)
CIN
XIN
External Clock
XIN
VCC
VSS
Oscillator
XOUT
Rd(1)
COUT
VSS
XOUT
Open
NOTE:
1. Place a damping resistor if required. Resistance values vary depending on the oscillator setting.
Use values recommended by each oscillator manufacturer.
Place a feedback resistor between XIN and XOUT if the oscillator manufacturer recommends
placing the resistor externally.
Figure 8.9 Main Clock Circuit Connection
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 74 of 488
8. Clock Generation Circuit
M32C/83 Group (M32C/83, M32C/83T)
8.1.2 Sub Clock
Sub clock oscillation circuit generates the sub clock. The sub clock becomes a clock source for the CPU
clock and a count source for the timers A and B. The same frequency, fc, as the sub clock can be output from
the CLKOUT pin.
The sub clock oscillation circuit is configured by connecting a crystal oscillator between the XCIN and
XCOUT pins. The circuit has a built-in feedback resistor. The feedback resistor is separated from the
oscillation circuit in stop mode to reduce power consumption. The externally generated clock can be
applied to the XCIN pin. Figure 8.10 shows an example of a sub clock circuit connection. Circuit constants
vary with each oscillator. Use the circuit constant recommended by each oscillation manufacturer.
The sub clock stops after reset. The feedback resistor is separated from the oscillation circuit. When the
PD8_6 and PD8_7 bits in the PD8 register are set to "0" (input mode) and the PU25 bit in the PUR2
register is set to "0" (no pull-up), set the CM04 bit in the CM0 register to "1" (XCIN-XCOUT oscillation
function). The sub clock oscillation circuit starts oscillating. To apply the external clock to the XCIN pin, set
the CM04 bit to "1" when the PD8_6 bit is set to "0" and the PU25 bit to "0". The clock applied to the XCIN
pin becomes the clock source for the sub clock.
When the CM07 bit in the CM0 register is set to "1" (sub clock) after the sub clock oscillation has stabilized, the sub clock becomes the CPU clock.
All clocks, including the sub clock, stop in stop mode. Refer to 8.5 Power Consumption Control for
details.
XCIN shares pins with VCONT and XCOUT shares pins with P86. The sub clock and PLL frequency synthesizer cannot be used simultaneously.
Microcomputer
(Built-in Feedback Resistor)
Microcomputer
(Built-in Feedback Resistor)
CCIN
XCIN
External Clock
XCIN
VCC
VSS
Oscillator
XCOUT
RCd(1)
CCOUT
VSS
XCOUT
Open
NOTE:
1. Place a damping resistor if required. Resistance values vary depending on the oscillator setting.
Use values recommended by each oscillator manufacturer.
Place a feedback resistor between XCIN and XCOUT if the oscillator manufacturer recommends
placing the resistor externally.
Figure 8.10 Sub Clock Connection Circuit
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 75 of 488
M32C/83 Group (M32C/83, M32C/83T)
8. Clock Generation Circuit
8.1.3 On-chip Oscillator Clock
On-chip oscillator generates the on-chip oscillator clock. The 1MHz on-chip oscillator clock becomes a
clock source for the CPU clock and peripheral function clock.
The on-chip oscillator clock stops after reset. When the CM21 bit in the CM2 register is set to "1" (on-chip
oscillator clock), the on-chip oscillator starts oscillating. Instead of the main clock, the on-chip oscillator
clock becomes the clock source for the CPU clock and peripheral function clock.
8.1.3.1 Oscillation Stop Detect Function
When the main clock is terminated by external factors, the on-chip oscillator automatically starts oscillating to generate another clock.
When the CM 20 bit is set to "1" (oscillation stop detect function enabled), the oscillation stop detect
interrupt request is generated as soon as the main clock stops. Simultaneously, the on-chip oscillator
starts oscillating. The on-chip oscillator clock takes place of the main clock as the clock source for the
CPU clock and peripheral function clock. Associated bits are set as follows:
• CM21 bit = 1 (on-chip oscillator clock becomes the clock source of the CPU clock.)
• CM22 bit = 1 (main clock stop is detected.)
• CM23 bit = 1 (main clock stops) (See Figure 8.15)
8.1.3.2 How to Use Oscillation Stop Detect Function
• The oscillation stop detect interrupt shares vectors with the watchdog timer interrupt. When both
oscillation stop detect interrupt and watchdog timer interrupt are used, read the CM22 bit with an
interrupt service routine to determine which interrupt request has been generated.
• When the main clock resumes running after an oscillation stop is detected, set the main clock as the
clock source for the CPU clock and peripheral function clock. Figure 8.11 shows the procedure to
switch the on-chip oscillator clock to the main clock.
• In low-speed mode, when the main clock is stopped by setting the CM20 bit to "1", the oscillation
stop detect interrupt request is generated. Simultaneously, the on-chip oscillator starts oscillating.
The sub clock remains the CPU clock. The on-chip oscillator clock becomes the clock source for
the peripheral function clock.
• To enter wait mode while the oscillation stop detect interrupt function is in use, set the CM02 bit to
"0" (peripheral function clock does not stop in wait mode).
• When the oscillation stop detect interrupt request is generated in wait mode, wait mode cannot be
exited by the oscillation stop detect interrupt. After the microcomputer exits wait mode, the oscillation stop detect interrupt is acknowledged first, followed by the interrupt used to exit wait mode.
• The oscillation stop detect function is provided to handle main clock stop caused by external factors. Set the CM20 bit to "0" (oscillation stop detect function disabled) when the main clock is
terminated by program, i.e., entering stop mode or setting the CM05 bit is set to "1" (main clock
oscillation stop).
• When the main clock frequency is 2MHz or less, the oscillation stop detect function is not available.
Set the CM20 bit to "0".
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 76 of 488
8. Clock Generation Circuit
M32C/83 Group (M32C/83, M32C/83T)
Switch to the
main clock
No
Determine several times whether
the CM23 bit is set to "0"
(main clock oscillates)
Yes
Set the MCD register to "0816"
(divide-by-8)
Set the CM22 bit to "0"
(main clock does not stop)
Set the CM21 bit to "0"
(main clock as CPU clock source)
End
CM21 to CM23 bits : Bits in CM2 register
Figure 8.11 Switching Procedure from On-chip Oscillator Clock to Main Clock
8.1.4 PLL Clock
The PLL frequency synthesizer generates the PLL clock based on the main clock. The PLL clock can be
used as a clock source for the CPU clock or peripheral function clock.
Connect a resistor and capacitor to the VCONT pin when using the PLL frequency synthesizer.
Set the PD8_6 and PD8_7 bits in the PD8 register to "0" (input mode) and the CM04 bit to "0" (the XCIN
and XCOUT pins as ports). After that, connect the VCONT pin, the P86 pin, and the VSS pin to the circuit as
is shown in Figure 8.12. Set the PLV00 bit in the PLV register to "1" (power to PLL).
The PLL frequency synthesizer stops after reset. When the PLC07 bit is set to "1" (PLL on), the PLL
frequency synthesizer starts operating. Wait 20 ms (5 V operation) to 50 ms (3.3 V operation) for the PLL
clock to stabilize.
The PLL clock can either be the clock output from the voltage controlled oscillator (VCO) divided-by-2 or
divided-by-3.
When the PLL clock is used as a clock source for the CPU clock or peripheral function clock, set each bit
as is shown in Table 8.2. Figure 8.13 shows the procedure for using the PLL clock as the CPU clock
source.
To enter wait or stop mode, set the CM17 bit to "0" (main clock as CPU clock source). Set the PLC07 bit
in the PLC0 register to "0" (PLL off) and the PLV00 bit to "0" (no power to PLL) before the microcomputer
enters wait or stop mode.
The VCONT and P86 pins share pins with XCIN and XCOUT pins. When the PLL frequency synthesizer is
being used, the sub clock cannot be used.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 77 of 488
8. Clock Generation Circuit
M32C/83 Group (M32C/83, M32C/83T)
Microcomputer
R1
NOTES:
1. Connect VSS to GND via C1 and C2 with shortest possible
wiring. Ground pattern must be formed around the circuit.
C2
2. Optimal values of the low pass filter circuit element,
connected to the VCONT pin, varies with environment
(e.g.noise). Evaluate not only with these optimal values, but
also with other values, to determine the values most
appropriate for your system.
Use capacitors for temperature compensation.
VCONT
C1
P86
VSS
C1=220pF, C2=0.1 µF, R1=1 kΩ(2)
Figure 8.12 External Circuit with PLL Frequency Synthesizer
Table 8.2 Bit Settings to Use PLL Clock as CPU Clock Source
PLC0 Register
PLC1 Register
f(XIN)
PLL Clock
PLC02
PLC01
PLC00
PLC12
0
30 MHz
10MHz
0
1
1
1
20 MHz
0
32MHz
8MHz
1
0
0
1
21.3MHz
Use PLL clock as CPU clock source
Set the PLC11 bit to "1"
(PLL clock division enabled)
Set the PLC02 to PLC00 bits
and the PLC12 bit
Set the PLC07 bit to "1"
(PLL on)
Wait 20 to 50ms
Set the CM17 bit to "1"
(PLL clock as CPU clock source)
End
PLC11 and PLC12 bits : Bit in PLC1 register
PLC00 to PLC02 bits, PLC07 bit : Bits in PLC0 register
CM17 bit : Bit in CM1 register
Figure 8.13 Procedure to Use PLL Clock as CPU Clock Source
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 78 of 488
8. Clock Generation Circuit
M32C/83 Group (M32C/83, M32C/83T)
8.2 CPU Clock and BCLK
The CPU operation clock is referred to as the CPU clock. The CPU clock is also the count source for the
watchdog timer. After reset, the CPU clock is the main clock divided-by-8. In memory expansion or microprocessor mode, the clock having the same frequency as the CPU clock can be output from the BCLK pin
as BCLK. Refer to 8.4 Clock Output Function for details.
The main clock, sub clock, on-chip oscillator clock or PLL clock can be selected as a clock source for the
CPU clock. Table 8.3 shows CPU clock source and bit settings.
When the main clock, on-chip oscillator clock or PLL clock is selected as a clock source of the CPU clock,
the selected clock divided-by-1 (no division), -2, -3, -4, -6, -8, -10, -12, -14 or -16 becomes the CPU clock.
The MCD register selects the clock division.
When the microcomputer enters stop mode or low-power consumption mode (except when the on-chip
oscillator clock is the CPU clock), the MCD register is set to "0816" (divide-by-8 mode). Therefore, when the
main clock starts running, the CPU clock enters middle-speed mode (divide-by-8).
Table 8.3 CPU Clock Source and Bit Settings
CM0 Register
CPU Clock Source
CM07
CM2 Register
CM1 Register
CM21
CM17
Main Clock
0
0
0
Sub Clock
1
0
0
On-chip Oscillator Clock
0
1
0
PLL Clock
0
0
1
8.3 Peripheral Function Clock
The peripheral function clock becomes the operation clock or count source for peripheral functions excluding the watchdog timer.
8.3.1 f1, f8, f32 and f2n
f1, f8, f32 and f2n are the main clock(1) or on-chip oscillator clock divided-by-1, -8, -32 ,or -2n (n=1 to 15. No
division when n=0). The CM21 bit determines which clock is selected.
When the CM02 bit is set to "1" (peripheral function stops in wait mode) when entering wait mode, f1, f8,
f32 and f2n stop running. These clocks also stop in low-power consumption mode.
f1, f8 and f2n are used as the operation clock for the serial I/O and the count source for timers A and B.
The CNT3 to CNT0 bits in the TCSPR register selects a f2n division. f1 is also used as the operation clock
for the intelligent I/O.
The CLKOUT pin outputs f8 and f32 . Refer to 8.4 Clock Output Function for details.
8.3.2 fAD
fAD is the operation clock for the A/D convertor and has the same frequency as the main clock(1) and onchip oscillator clock. The CM21 bit determines which clock is selected.
When the CM02 bit is set to "1" (peripheral function stop in wait mode) when entering wait mode, fAD
stops. fAD also stops in low-power consumption mode.
NOTES:
1. When the CM17 bit is set to "1" (PLL clock as CPU clock source), the PLL clock is the main clock.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 79 of 488
8. Clock Generation Circuit
M32C/83 Group (M32C/83, M32C/83T)
8.3.3 fC32
fC32 is the sub clock divided by 32. fC32 is used for as a count source for the timers A and B. fC32 is
available when the sub clock is running.
8.4 Clock Output Function
The CLKOUT pin outputs fC, f8 or f32.
In memory expansion and microprocessor modes, a clock having the same frequency as the CPU clock
can be output from the BCLK pin as BCLK.
Table 8.4 lists CLKOUT pin function in single-chip mode. Table 8.5 lists CLKOUT pin functions in memory
expansion and microprocessor modes.
Table 8.4 CLKOUT Pin in Single-Chip Mode
PM0 Register (1)
CM0 Register (2)
PM07
CLKOUT Pin Function
CM01
0
CM00
0
1
0
1
Outputs fc
1
1
0
Outputs f8
1
1
1
Outputs f32
P53 I/O port
- : Can be set to either "0" or "1"
NOTES:
1. Rewrite the PM0 register after the PRC1 bit in the PRCR register is set to "1" (write enable)
2. Rewrite the CM0 register after the PRC0 bit in the PRCR register is set to "1" (write enable)
Table 8.5 BLCK/CLKOUT Pin in Memory Expansion Mode and Microprocessor Mode(4)
PM1 Register(1)
PM15
PM14
002, 102, 112,
0
PM0 Register(1)
PM07
0
CM0 Register(2)
CLKOUT Pin Function
CM01
0 (3)
CM00
0 (3)
Outputs BCLK
1
0
0
Outputs "L" (not P53)
1
0
1
Outputs fc
1
1
0
Outputs f8
1
1
1
Outputs f32
0 (3)
0 (3)
Outputs ALE
1
- : Can be set to either "0" or "1"
NOTES:
1. Rewrite the PM0 and PM1 register after the PRC1 bit in the PRCR register is set to "1" (write enable)
2. Rewrite the CM0 register after the PRC0 bit in the PRCR register is set to "1" (write enable)
3. When the PM07 bit is set to "0" (selected in the CM01 to CM00 bits) or the PM15 to PM14 bits are set
to "012" (P53/BCLK), set the CM01 to CM00 bits to "002" (I/O port P53)
4. M32C/83T cannot be used in memory expansion mode and microprocessor mode.
8.5 Power Consumption Control
Normal operation mode, wait mode and stop mode are provided as the power consumption control.
All mode states, except wait mode and stop mode, are called normal operation mode in this document.
Figure 8.14 shows a block diagram of status transition in wait mode and stop mode. Figure 8.15 shows a
block diagram of status transition in all modes.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 80 of 488
M32C/83 Group (M32C/83, M32C/83T)
8. Clock Generation Circuit
8.5.1 Normal Operation Mode
The normal operation mode is further separated into six modes.
In normal operation mode, the CPU clock and peripheral function clock are supplied to operate the CPU
and peripheral function. The power consumption control is enabled by controlling the CPU clock frequency. The higher the CPU clock frequency, the more processing power increases. The lower the CPU
clock frequency, the more power consumption decreases. When unnecessary oscillation circuits stop,
power consumption is further reduced.
8.5.1.1 High-Speed Mode
The main clock(1) becomes the CPU clock and the clock source for the peripheral function clock.
When the sub clock runs, fC32 can be used as a count source for the timers A and B.
8.5.1.2 Medium-Speed Mode
The main clock divided-by-2, -3, -4, -6, -8, -10, -12, -14, or -16 becomes the CPU clock. The main
clock is the clock source for the peripheral function clock. When the sub clock runs, fC32 can be used
as the count source for the timers A and B.
8.5.1.3 Low-Speed Mode
The sub clock becomes the CPU clock. The main clock is the count source for the peripheral function
clock. fC32 can be used as the count source for the timers A and B.
8.5.1.4 Low-Power Consumption Mode
The microcomputer enters low-power consumption mode when the main clock stops in low-speed
mode. The sub clock becomes the CPU clock. fC32 can be used as the count source for timers A and
B. Only fC32 can be used as the peripheral function clock. In low-power consumption mode, the MCD
register is set to "0816" (divide-by-8 mode). Therefore, when the main clock resumes running, the
microcomputer is in middle-speed mode (divide-by-8 mode).
8.5.1.5 On-chip Oscillator Mode
The on-chip oscillator clock divided-by-1(no division), -2, -3, -4, -6, -8, -10, -12, -14, or -16 becomes
the CPU clock. The on-chip oscillator clock is the clock source for the peripheral function clock. When
the sub clock runs, fC32 can be used as the count source for the timers A and B.
8.5.1.6 On-chip Oscillator Low-Power Consumption Mode
The microcomputer enters on-chip oscillator low-power consumption mode when the main clock stops
in on-chip oscillator mode. The on-chip oscillator clock divided-by-1(no division), -2, -3, -4, -6, -8, -10, 12, -14, or -16 becomes the CPU clock. The on-chip oscillator clock is the clock source for the peripheral
function clock. When the sub clock runs, fC32 can be used as the count source for the timers A and B.
Switch the CPU clock after the clock to be switched to stabilizes. Sub clock oscillation will take longer(2)
to stabilize. Wait, by program, until the clock stabilizes directly after running the microcomputer on or
exiting stop mode.
To switch the on-chip oscillator to the main clock, enter medium-speed mode (divide-by-8) after the main
clock is divided by eight in on-chip oscillator mode (MCD register=0816).
Do not enter on-chip oscillator mode or on-chip oscillator low-power consumption mode from low-speed
mode or low-power consumption mode and vice versa.
NOTES:
1. When the CM17 bit is set to "1" (PLL clock as CPU clock source), the PLL clock is the main clock .
2. Contact your oscillator manufacturer for oscillation stabilization time.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 81 of 488
M32C/83 Group (M32C/83, M32C/83T)
8. Clock Generation Circuit
8.5.2 Wait Mode
In wait mode, the CPU clock stops running. The CPU and watchdog timer, operated by the CPU clock,
also stop. Because the main clock, sub clock and on-chip oscillator clock continue running, peripheral
functions using these clocks also continue operating.
8.5.2.1 Peripheral Function Clock Stop Function
If the CM02 bit is set to "1" (peripheral function clock stops in wait mode), f1, f8, f32, f2n and fAD stop in
wait mode. Power consumption can be reduced because the peripheral function that has f1, f8, f32, f2n,
or fAD as a count source stops. fC32 does not stop running.
8.5.2.2 Entering Wait Mode
Follow the procedure below to enter wait mode.
• Initial Setting
Set each interrupt priority level after setting the exit priority level required to exit wait mode, controlled by the RLVL2 to RLVL0 bits in the RLVL register, to "7".
• Before Entering Wait Mode
(1) Set the I flag to "0"
(2) Set the interrupt priority level of the interrupt being used to exit wait mode
(3) Set the interrupt priority levels of the interrupts, not being used to exit wait mode, to "0"
(4) Set the IPL in the FLG register. Then set the exit priority level to the same level as IPL
(Interrupt priority level of the interrupt used to exit wait mode > exit priority level ≥ interrupt
priority level of the interrupts not used to exit wait mode)
(5) Set the PRC0 bit in the PRCR register to "1" (write enable)
(6) If the CPU clock source is the PLL clock, set the CM17 bit in the CM1 register to "0" (main clock),
the PLC07 bit in the PLC0 register to "0" (PLL off), and the PLV00 bit in the PLV register to
"0"(cut off power to PLL)
(7) Set the I flag to "1"
(8) Execute the WAIT instruction
• After Exiting Wait Mode
Set the interrupt priority level required to exit wait mode to "7" immediately after exiting wait mode.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 82 of 488
8. Clock Generation Circuit
M32C/83 Group (M32C/83, M32C/83T)
8.5.2.3 Pin Status in Wait Mode
Table 8.6 lists pin states in wait mode.
Table 8.6 Pin Status in Wait Mode
Pin
Memory Expansion Mode
Single-Chip Mode
Microprocessor Mode
_______
_______
Address Bus, Data Bus, CS0 to CS3,
Maintains state immediately
________
BHE
_____
______
before entering wait mode
________
_________
______
_________
________
RD, WR, WRL, WRH, DW, CASL, CASH
________
"H" (1)
"H" (1)
RAS
__________
HLDA, BCLK
"H"
ALE
"L"
Port
Maintains state immediately before entering wait mode
CLKOUT
When fC is selected
Outputs clock
When f8, f32 are selected
The clock is output when the CM02 bit in the CM0 register is set to
"0" (peripheral function clock not stop in wait mode).
Maintains state immediately before entering wait mode when the
CM02 bit is set to "1" (peripheral function clock stopped in wait
mode).
NOTES:
________
________
1. When performing a self-refresh operation using the DRAMC, CAS and RAS become low ("L").
2. M32C/83T cannot be used in memory expansion mode and microprocessor mode.
8.5.2.4 Exiting Wait Mode
_______
Wait mode is exited by the hardware reset, NMI interrupt or peripheral function interrupts.
_______
When the hardware reset or NMI interrupt, but not the peripheral function interrupts, is used to exit wait
mode, set the ILVL2 to ILVL0 bits for the peripheral function interrupts to "0002" (interrupt disabled)
before executing the WAIT instruction.
The CM02 bit affects the peripheral function interrupts. When the CM02 bit is set to "0" (peripheral
function clock does not stop in wait mode), all peripheral function interrupts can be used to exit wait
mode. When the CM02 bit is set to "1" (peripheral function clock stops in wait mode), peripheral
functions using the peripheral function clock stop. Therefore, the peripheral function interrupts cannot
be used to exit wait mode. However, peripheral function interrupts caused by an external signal can
be used to exit wait mode.
_______
The CPU clock used when exiting wait mode by the peripheral function interrupts or NMI interrupt is
the same CPU clock used when WAIT instructions are executed.
Table 8.7 shows interrupts to be used to exit wait mode and usage conditions.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 83 of 488
8. Clock Generation Circuit
M32C/83 Group (M32C/83, M32C/83T)
Table 8.7 Interrupts to Exit Wait Mode
Interrupt
When CM02=0
When CM02=1
_______
NMI Interrupt
Available
Available
Serial I/O Interrupt
Available when the internal and external
Available only when the external clock is used
clocks are used
Key Input Interrupt
Available
Available
A/D Conversion Interrupt Available in single or single-sweep mode Do not use
Timer A Interrupt
Available in all modes
Timer B Interrupt
Available in event counter mode or when
the count source is fC32
______
INT Interrupt
Available
Available
CAN Interrupt
Available
Do not use
Intelligent I/O Interrupt
Available
Do not use
8.5.3 Stop Mode
In stop mode, all oscillators and resonators stop. The CPU clock and peripheral function clock, as well as
the CPU and peripheral functions operated by these clocks, also stop. The least power required to
operate the microcomputer is in stop mode. The internal RAM holds its data if the voltage applied to the
Vcc pin is 2.5V or more.
______
______
Interrupts used to exit stop mode are NMI interrupt, key input interrupt, and INT interrupt.
8.5.3.1 Entering Stop Mode
Stop mode is entered when setting the CM10 bit in the CM1 register to "1" (all clocks stops). The
MCD4 to MCD0 bits in the MCD register become set to "010002" (divide-by-8 mode).
Enter stop mode after setting the followings.
• Initial Setting
Set each interrupt priority level after setting the minimum interrupt priority level required to exit stop
or wait mode, controlled by the RLVL2 to RLVL0 bits in the RLVL register, to "7".
• Before Entering Stop Mode
(1) Set the I flag to "0"
(2) Set the interrupt priority level of the interrupt being used to exit stop mode
(3) Set the interrupt priority levels of the interrupts, not being used to exit stop mode, to "0"
(4) Set IPL in the FLG register. Then set the exit priority level to the same level as IPL
(Interrupt priority level of the interrupt used to exit stop mode > interrupt priority level to exit stop
mode ≥ interrupt priority level of the interrupts not used to exit stop mode)
(5) Set the PRC0 bit in the PRCR register to "1" (write enabled)
(6) Select the main clock as the CPU clock
• When the CPU clock source is the sub clock,
Set the CM05 bit in the CM0 register to "0" (main clock oscillates) and CM07 bit in the CM0
register to "0" (clock selected by the CM21 bit divided by MCD register setting)
• When the CPU clock source is the PLL clock,
Set the CM17 bit in the CM1 register to "0" (main clock) and the PLC07 bit in the PLC0 register to
"0" (PLL off)
• When the CPU clock source is the on-chip oscillator clock,
Set the MCD4 to MCD0 bits to "010002" (divide-by-8 mode), the CM05 bit to "0" (main clock
oscillates), and the CM21 it in the CM2 register to "0" (clock selected by the CM17 bit)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 84 of 488
8. Clock Generation Circuit
M32C/83 Group (M32C/83, M32C/83T)
(7) The oscillation stop detect function is used, set the CM20 bit in the CM2 register to "0" (oscilla
tion stop detect function disabled)
(8) Set the I flag to "1"
(9) Set the CM10 bit to "1" (all clocks stops)
• After Exiting Stop Mode
Set the interrupt priority level required to exit stop mode to "7" immediately after exiting stop mode.
8.5.3.2 Exiting Stop Mode
_______
Stop mode is exited by the hardware reset, NMI interrupt, or peripheral function interrupts (key input
______
interrupt and INT interrupt).
_______
When the hardware reset or NMI interrupt, but not the peripheral function interrupts, is used to exit wait
mode, set all ILVL2 to ILVL0 bits in the interrupt control registers for the peripheral function interrupt to
"0002" (interrupt disabled) before setting the CM10 bit to "1" (all clocks stops).
8.5.3.3 Pin Status in Stop Mode
Table 8.8 lists pin status in stop mode.
Table 8.8 Pin Status in Stop Mode
Pin
Memory Expansion Mode
Microprocessor Mode(2)
_______
_______
Single-Chip Mode
_______
Address Bus, Data Bus, CS0 to CS3, BHE
Maintains state immediately before
entering stop mode
_____
______
________
_________
______
_________
________
RD, WR, WRL, WRH, DW, CASL, CASH
________
"H" (1)
"H" (1)
RAS
__________
HLDA, BCLK
"H"
ALE
"H"
Port
Maintains state immediately before entering stop mode
CLKOUT
When fC selected
"H"
When f8, f32 selected
Maintains state immediately before entering stop mode
XIN
High-impedance
XOUT
"H"
XCIN, XCOUT
High-impedance
NOTES:
________
________
1. When performing a self-refresh operation using DRAMC, CAS and RAS become low ("L").
2. M32C/83T cannot be used in memory expansion mode and microprocessor mode.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 85 of 488
8. Clock Generation Circuit
M32C/83 Group (M32C/83, M32C/83T)
Reset
All oscillation is stopped
CPU operation is stopped
CM10=1
(Note 2)
Stop mode
Interrupt
Inter
Stop mode
rupt
CM10=1
Middle-speed mode
(divide-by-8 mode)
(Note 2)
WAIT instruction
Interrupt
Wait mode
(Note 1)
(Note 2)
High-speed /
middle-speed mode
(Note 2)
WAIT instruction
Wait mode
Interrupt
(Note 1)
Low-speed/ low-power
consumption mode
WAIT instruction
Wait mode
Interrupt
(Note 3)
On-chip oscillator /
On-chip oscillator lowpower consumption
WAIT instruction
Interrupt
Wait mode
Normal operation mode
NOTES:
1. See Figure 8.15.
2. When the CM17 bit is set to "1" (PLL clock as CPU clock source), set the CM17 bit to "0"(main clock as CPU clock
source) before the PLC07 bit is set to "0" (PLL off). Set the PLV00 bit to "0" (no power to PLL) before the
microcomputer enters wait mode or stop mode.
3. When the PLL frequency synthesizer is used, the microcomputer cannot enter low-speed and low-power consumption
mode.
Figure 8.14 Status Transition in Wait Mode and Stop Mode
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 86 of 488
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Figure 8.15 Status Transition
Page 87 of 488
Middle-speed mode
CPU clock: f(XPLL)/n
(n=2,3,4,6,8,10,12,14,16)
CM07=0 MCD=XX16 CM21=0
CM05=0 CM04=0 PLC07=1
PLC11=1 CM17=1
PLC07=0
(Note 4, 5)
Main clock stop
is detected when
CM20=1
Middle-speed mode
CPU clock: f(XIN)/n
(n=2,3,4,6,8,10,12,14,16)
CM07=0 MCD=XX16 CM21=0
CM05=0 CM04=0 PLC07=1
PLC11=0 CM17=0
PLC07=1
CM04=0
Main clock stop
Sub clock stop
On-chip oscillator clock oscillation
PLL clock stop
CPU clock: On-chip oscillator clock/n
(n=1,2,3,4,6,8,10,12,14,16)
CM07=0 MCD=XX16 CM21=1
CM05=1 CM04=0 PLC07=0
PLC11=0 CM17=0
On-chip oscillator low power
consumption mode
CM05=0
Main clock oscillation
Sub clock stop
On-chip oscillator clock oscillation
PLL clock stop
CPU clock: On-chip oscillator clock/ n
(n=1,2,3,4,6,8,10,12,14,16)
CM07=0 MCD=XX16 CM21=1
CM05=0 CM04=0 PLC07=0
PLC11=0 CM17=0
On-chip oscillator mode
(Note 1) CM21=0
Middle-speed mode
CPU clock: f(XIN)/n
(n=2,3,4,6,8,10,12,14,16)
CM07=0 MCD=XX16 CM21=0
CM05=0 CM04=0 PLC07=0
PLC11=0 CM17=0
CM04=1
CM04=0
CM05=1
CM04=1
CM04=0
CM21=1
CM04=1
(Note 5)
CM05=1
CM21=1
CM07=1 (Note 2)
CM07=0 (Note 1)
Middle-speed mode
CPU clock: f(XIN)/n
(n=2,3,4,6,8,10,12,14,16)
CM07=0 MCD=XX16 CM21=0
CM05=0 CM04=1 PLC07=1
PLC11=0 CM17=0
CM21=0
CM05=0
(Note 3)
Main clock stop
Sub clock oscillation
On-chip oscillator clock oscillation
PLL clock stop
CPU clock: f(XCIN)
CM07=1 MCD=0816 CM21=1
CM05=1 CM04=1 PLC07=0
PLC11=0 CM17=0
CM05=0
Main clock stop
Sub clock oscillation
On-chip oscillator clock stop
PLL clock stop
CPU clock: f(XCIN)
CM07=1 MCD=0816 CM21=0
CM05=1 CM04=1 PLC07=0
PLC11=0 CM17=0
Low power consumption mode
CM05=1
CM21=1
(Note 1)
Main clock oscillation
Sub clock oscillation
On-chip oscillator clock stop
PLL clock stop
CPU clock: f(XCIN)
CM07=1 CM21=0 CM05=0
CM04=1 PLC07=0
PLC11=0 CM17=0
(Note 3)
CM05=1
Middle-speed mode
CPU clock: f(XPLL)/n
(n=2,3,4,6,8,10,12,14,16)
CM07=0 MCD=XX16 CM21=0
CM05=0 CM04=1 PLC07=1
PLC11=1 CM17=1
Low-speed mode
PLC11=1
CM17=1
(Note 6)
Main clock oscillation
Sub clock oscillation
On-chip oscillator clock oscillation
PLL clock stop
CPU clock: f(XCIN)
CM07=1 CM21=1 CM05=0
CM04=1 PLC07=0
PLC11=0 CM17=0
Low power consumption mode
CM07=1
(Note 2)
CM07=0
Low-speed mode
Main clock stop
is detected when
CM20=1
PLC07=1
PLC07=0
CPU clock: f(XPLL)
CM07=0 MCD=1216 CM21=0
CM05=0 CM04=1 PLC07=1
PLC11=1 CM17=1
High-speed mode
PLC11=0
CM17=0
High-speed mode
CPU clock: f(XIN)
CM07=0 MCD=1216 CM21=0
CM05=0 CM04=1 PLC07=1
PLC11=0 CM17=0
Main clock oscillation
Sub clock oscillation
On-chip oscillator clock stop
PLL clock oscillation
Main clock oscillation
Sub clock oscillation
On-chip oscillator clock stop
PLL clock oscillation
5. The CM05 bit is not set to "1" when the microcomputer detects a main clock oscillation stop through the
oscillation stop detect circuit .
6. To select the PLL clock, set the PLC07 bit to "1" (PLL on) after the PLC11 bit is set to "1" (division enabled).
To select the main clock, set the PLC11 bit to "0" (division disabled) after the PLC07 bit is set to "0" (PLL off).
Switch the PLL clock after a PLL clock oscillation is fully stabilized.
Main clock stop
Sub clock oscillation
On-chip oscillator clock oscillation
PLL clock stop
CPU clock: On-chip oscillator clock/n
(n=1,2,3,4,6,8,10,12,14,16)
CM07=0 MCD=XX16 CM21=1
CM05=1 CM04=1 PLC07=0
PLC11=0 CM17=0
CM05=0
On-chip oscillator low power
consumption mode
Main clock oscillation
Sub clock oscillation
On-chip oscillator clock oscillation
PLL clock stop
CPU clock: On-chip oscillator clock/n
(n=1,2,3,4,6,8,10,12,14,16)
CM07=0 MCD=XX16 CM21=1
CM05=0 CM04=1 PLC07=0
PLC11=0 CM17=0
On-chip oscillator mode
(Note 1) CM21=0
Middle-speed mode
CPU clock: f(XIN)/n
(n=2,3,4,6,8,10,12,14,16)
CM07=0 MCD=XX16 CM21=0
CM05=0 CM04=1 PLC07=0
PLC11=0 CM17=0
CPU clock: f(XIN)
CM07=0 MCD=1216 CM21=0
CM05=0 CM04=1 PLC07=0
PLC11=0 CM17=0
High-speed mode
CPU clock: f(XIN)
CM07=0 MCD=1216 CM21=0
CM05=0 CM04=0 PLC07=0
PLC11=0 CM17=0
High-speed mode
CM04=1 (Note 1)
Main clock oscillation
Sub clock oscillation
On-chip oscillator clock stop
PLL clock stop
Main clock oscillation
Sub clock stop
On-chip oscillator clock stop
PLL clock stop
: Arrow shows mode can be changed. Do not change mode to another mode when no arrow is shown.
MCD=XX16: Desired division must be set in the MCD register.
NOTES:
1. Switch clock after main clock oscillation is fully stabilized.
2. Switch clock after sub clock oscillation is fully stabilized.
3. The MCD register is set to "0816" (divide-by-8 mode) automatically.
4. When the CM20 bit is set to "1" (oscillation stop detect function enabled), the microcomputer detects
a main clock oscillation stop. If the microcomputer then enters on-chip oscillator low power consumption mode,
the CM05 bit is set to "1" (main clock stopped). See Figure 1.8.10 about the follow-up handling.
PLC11=0
CM17=0
(Note 6)
CPU clock: f(XIN)
CM07=0 MCD=1216 CM21=0
CM05=0 CM04=0 PLC07=1
PLC11=0 CM17=0
High-speed mode
PLC11=1
CM17=1
High-speed mode
CPU clock: f(XPLL)
CM07=0 MCD=1216 CM21=0
CM05=0 CM04=0 PLC07=1
PLC11=1 CM17=1
Main clock oscillation
Sub clock stop
On-chip oscillator clock stop
PLL clock oscillation
Main clock oscillation
Sub clock stop
On-chip oscillator clock stop
PLL clock oscillation
MCD=XX16 (Note 1)
After reset,
middle-speed mode ( divide-by-8)
Main clock oscillation
Sub clock stop
On-chip oscillator clock stop
PLL clock stop
CPU clock: f(XIN)/8
CM07=0 MCD=0816 CM21=0
CM05=0 CM04=0 PLC07=0
PLC11=0 CM17=0
M32C/83 Group (M32C/83, M32C/83T)
8. Clock Generation Circuit
9. Protection
M32C/83 Group (M32C/83, M32C/83T)
9. Protection
The protection function protects important registers from being easily overwritten when a program runs out of
control.
Figure 9.1 shows the PRCR register. Each bit in the PRCR register protects the following registers:
• The PRC0 bit protects the CM0, CM1, CM2, MCD, PLC0 and PLC1 registers;
• The PRC1 bit protects the PM0, PM1, PM2, INVC0 and INVC1 registers;
• The PRC2 bit protects the PD9 and PS3 registers;
• The PRC3 bit protects the PLV and VDC0 registers.
The PRC2 bit is set to "0" (write disable) when data is written to a desired address after setting the PRC2 bit
to "1" (write enable). Set the PD9 and PS3 registers immediately after setting the PRC2 bit in the PRCR
register to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set
to the PRC2 bit to "1" and the following instruction. The PRC0, PRC1 and PRC3 bits are not set to "0" even
if data is written to desired addresses. Set the PRC0, PRC1 and PRC3 bits to "0" by program.
Protect Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PRCR
Bit
Symbol
Address
000A16
Bit Name
After Reset
XXXX 00002
Function
PRC0
Protect Bit 0
Enables writing to CM0, CM1, CM2,
MCD, PLC0, PLC1 registers
0 : Write disable
1 : Write enable
RW
PRC1
Protect Bit 1
Enables writing to PM0, PM1, INVC0,
INVC1 registers
0 : Write disable
1 : Write enable
RW
PRC2
Protect Bit 2(1)
Enables writing to PD9, PS3 registers
0 : Write disable
1 : Write enable
RW
Protect Bit 3
Enables writing to PLV, VDC0 and
VDC1 registers
0 : Write disable
1 : Write enable
PRC3
Nothing is assigned. When write, set to "0".
(b7 - b4) When read, its content is indeterminate.
NOTES:
1. The PRC2 bit can be set to "0" by writing to a desired address after the PRC2 bit is set to "1".
The PRC0, PRC1 and PRC3 bits are not automatically set to "0". Set to"0" by program.
Figure 9.1 PRCR Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
RW
Page 88 of 488
RW
10. Interrupts
M32C/83 Group (M32C/83, M32C/83T)
10. Interrupts
10.1 Types of Interrupts
Figure 10.1 shows types of interrupts.










Hardware
Special
(Non-Maskable Interrupt)















Interrupt
Software
(Non-Maskable Interrupt)
Undefined Instruction (UND Instruction)
Overflow (INTO Instruction)
BRK Instruction
BRK2 Instruction(2)
INT Instruction
_______
NMI
Watchdog Timer
Oscillation Stop Detect
Single-Step(2)
Address Match
DMACII
Peripheral Function(1)
(Maskable Interrupt)
NOTES:
1. The peripheral functions in the microcomputer are used to generate the peripheral interrupt.
2. Do not use this interrupt. For development support tools only.
Figure 10.1 Interrupts
• Maskable Interrupt
The I flag enables or disables an interrupt.
The interrupt priority order based on interrupt priority level can be changed.
• Non-maskable Interrupt
The I flag does not enable nor disable an interrupt .
The interrupt priority order based on interrupt priority level cannot be changed.
10.2 Software Interrupts
Software interrupt occurs when an instruction is executed. The software interrupts are non-maskable interrupts.
10.2.1 Undefined Instruction Interrupt
The undefined instruction interrupt occurs when the UND instruction is executed.
10.2.2 Overflow Interrupt
The overflow interrupt occurs when the O flag in the FLG register is set to "1" (overflow of arithmetic
operation) and the INTO instruction is executed.
Instructions to set the O flag are :
ABS, ADC, ADCF, ADD, ADDX, CMP, CMPX, DIV, DIVU, DIVX, NEG, RMPA, SBB, SCMPU, SHA, SUB, SUBX
10.2.3 BRK Interrupt
The BRK interrupt occurs when the BRK instruction is executed.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 89 of 488
M32C/83 Group (M32C/83, M32C/83T)
10. Interrupts
10.2.4 BRK2 Interrupt
The BRK2 interrupt occurs when the BRK2 instruction is executed.
Do not use this interrupt. For development support tools only.
10.2.5 INT Instruction Interrupt
The INT instruction interrupt occurs when the INT instruction is executed. The INT instruction can select
software interrupt numbers 0 to 63. Software interrupt numbers 7 to 54, and 57 are assigned to the vector
table used for the peripheral function interrupt. Therefore, the microcomputer executes the same service
routine when the INT instruction is executed as when a peripheral function interrupt occurs.
When the INT instruction is executed, the FLG register and PC are saved to the stack. PC also stores the
relocatable vector of the specified software interrupt number. Where the stack is saved varies, depending on the software interrupt number. ISP is selected as the stack for the software interrupt numbers 0 to
31 (the U flag is set to "0"). SP, which is set before the INT instruction is executed, is selected as the stack
for the software interrupt numbers 32 to 63 (the U flag is not changed).
With the peripheral function interrupt, the FLG register is saved and the U flag is set to "0" (ISP select)
when an interrupt request is acknowledged. With software interrupt numbers 32 to 54 and 57, the SP to
be used varies, depending on whether the interrupt is generated by the peripheral function interrupt
request or by the INT instruction.
10.3 Hardware Interrupts
Special interrupts and peripheral function interrupts are available as hardware interrupts.
10.3.1 Special Interrupts
Special interrupts are non-maskable interrupts.
______
10.3.1.1 NMI Interrupt
______
______
The NMI interrupt occurs when a signal applied to the NMI pin changes from an "H" signal to an "L"
______
signal. Refer to 10.8 NMI Interrupt for details.
10.3.1.2 Watchdog Timer Interrupt
The watchdog timer interrupt occurs when the count source of the watchdog timer underflows. Refer
to 11. Watchdog Timer for details.
10.3.1.3 Oscillation Stop Detection Interrupt
The oscillation stop detection interrupt occurs when the microcomputer detects a main clock oscillation stop. Refer to 8. Clock Generating Circuit for details.
10.3.1.4 Single-Step Interrupt
Do not use the single-step interrupt. For development support tool only.
10.3.1.5 Address Match Interrupt
The address match interrupt occurs immediately before executing an instruction that is stored into an
address indicated by the RMADi register (i=0 to 3) when the AIERi bit in the AIER register is set to "1"
(address match interrupt enabled). Set the starting address of the instruction in the RMADi register.
The address match interrupt does not occur when a table data or addresses of the instruction other
than the starting address, if the instruction has multiple addresses, is set. Refer to 10.10 Address
Match Interrupt for details.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 90 of 488
10. Interrupts
M32C/83 Group (M32C/83, M32C/83T)
10.3.2 Peripheral Function Interrupt
The peripheral function interrupt occurs when a request from the peripheral functions in the microcomputer is acknowledged. The peripheral function interrupts and software interrupt numbers 7 to 54 and
57 for the INT instruction use the same interrupt vector table. The peripheral function interrupt is a
maskable interrupt.
See Table 10.2 about how the peripheral function interrupt occurs. Refer to the descriptions of each
function for details.
10.4 High-Speed Interrupt
The high-speed interrupt executes an interrupt sequence in five cycles and returns from the interrupt in 3
cycles.
When the FSIT bit in the RLVL register is set to "1" (interrupt priority level 7 available for the high-speed
interrupt), the ILVL2 to ILVL0 bits in the interrupt control registers can be set to "1112" (level 7) to use the
high-speed interrupt.
Only one interrupt can be set as the high-speed interrupt. When using the high-speed interrupt, do not set
multiple interrupts to interrupt priority level 7. Set the DMAII bit in the RLVL register to "0" (interrupt priority
level 7 available for interrupts).
Set the starting address of the high-speed interrupt service routine in the VCT register.
When the high-speed interrupt is acknowledged, the FLG register is saved to the SVF register and PC is
saved to the SVP registers. The program is executed from an address indicated by the VCT register.
Execute the FREIT instruction to return from the high-speed interrupt service routine.
The values saved to the SVF and SVP registers are restored to the FLG register and PC by executing the
FREIT instruction.
The high-speed interrupt and the DMA2 and DMA3 use the same register. When using the high-speed
interrupt, neither DMA2 nor DMA3 is available. DMA0 and DMA1 can be used.
10.5 Interrupts and Interrupt Vectors
There are four bytes in one vector. Set the starting address of interrupt service routine in each vector table.
When an interrupt request is acknowledged, the interrupt service routine is executed from the address set
in the interrupt vectors. Figure 10.2 shows the interrupt vector.
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
MSB
Vector Address + 0
Low-order bits of an address
Vector Address + 1
Middle-order bits of an address
Vector Address + 2
High-order bits of an address
Vector Address + 3
0 0 16
Figure 10.2 Interrupt Vector
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
LSB
Page 91 of 488
10. Interrupts
M32C/83 Group (M32C/83, M32C/83T)
10.5.1 Fixed Vector Tables
The fixed vector tables are allocated addresses FFFFDC16 to FFFFFF16. Table 10.1 lists the fixed vector
tables. Refer to 25.2 Functions to Prevent Flash Memory from Rewriting for fixed vectors of the flash
memory.
Table 10.1 Fixed Vector Table
Interrupt
Generated by
Vector Addresses
Address (L) to Address (H)
Undefined
Instruction
FFFFDC16 to FFFFDF16
Overflow
FFFFE016 to FFFFE316
BRK Instruction
FFFFE416 to FFFFE716
Address Match
FFFFE816 to FFFFEB16
-
FFFFEC16 to FFFFEF16
Remarks
Reference
M32C/80 series
software manual
If the content of address FFFFE716 is
FF16, the program is executed from the
address stored into software interrupt
number 0 in the relocatable vector table
Reserved space
Watchdog Timer FFFFF016 to FFFFF316
These addresses are used for the
watchdog timer interrupt and the
oscillation stop detect interrupt
-
FFFFF416 to FFFFF716
Reserved space
NMI
FFFFF816 to FFFFFB16
Reset
FFFFFC16 to FFFFFF16
Clock oscillation circuit,
Watchdog timer
Reset
10.5.2 Relocatable Vector Tables
The relocatable vector tables occupy 256 bytes from the starting address set in the INTB register. Table
10.2 lists the relocatable vector tables.
Set an even address as the starting address of the vector table set in the INTB register to increase
interrupt sequence execution rate.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 92 of 488
10. Interrupts
M32C/83 Group (M32C/83, M32C/83T)
Table 10.2 Relocatable Vector Tables
Interrupt Generated by
Vector Table Address
Address(L) to Address(H)(1)
Software
Reference
Interrupt Number
BRK Instruction(2)
+0 to +3 (000016 to 000316)
0
M32C/80 Series
Reserved Space
+4 to +27 (000416 to 001B16)
1 to 6
Software Manual
A/D1
+28 to +31 (001C16 to 001F16)
7
A/D Converter
DMA0
+32 to +35 (002016 to 002316)
8
DMAC
DMA1
+36 to +39 (002416 to 002716)
9
DMA2
+40 to +43 (002816 to 002B16)
10
DMA3
+44 to +47 (002C16 to 002F16)
11
Timer A0
+48 to +51 (003016 to 003316)
12
Timer A1
+52 to +55 (003416 to 003716)
13
Timer A2
+56 to +59 (003816 to 003B16)
14
Timer A3
+60 to +63 (003C16 to 003F16)
15
Timer A4
+64 to +67 (004016 to 004316)
16
+68 to +71 (004416 to 004716)
17
+72 to +75 (004816 to 004B16)
18
+76 to +79 (004C16 to 004F16)
19
+80 to +83 (005016 to 005316)
20
Timer B0
+84 to +87 (005416 to 005716)
21
Timer B1
+88 to +91 (005816 to 005B16)
22
Timer B2
+92 to +95 (005C16 to 005F16)
23
Timer B3
+96 to +99 (006016 to 006316)
24
Timer B4
+100 to +103 (006416 to 006716)
25
UART0 Transmission, NACK(3)
ACK(3)
UART0 Reception,
UART1 Transmission, NACK(3)
UART1 Reception,
ACK (3)
Timer A
Serial I/O
Timer B
________
INT5
+104 to +107 (006816 to 006B16) 26
Interrupt
________
INT4
+108 to +111 (006C16 to 006F16) 27
________
INT3
+112 to +115 (007016 to 007316)
28
+116 to +119 (007416 to 007716)
29
________
INT2
________
INT1
+120 to +123 (007816 to 007B16) 30
_______
INT0
+124 to +127 (007C16 to 007F16) 31
Timer B5
+128 to +131 (008016 to 008316)
32
Timer B
+132 to +135 (008416 to 008716)
33
Serial I/O
UART2 Transmission, NACK(3)
UART2 Reception,
ACK(3)
UART3 Transmission, NACK(3)
UART3 Reception,
ACK(3)
UART4 Transmission, NACK(3)
UART4 Reception,
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
ACK(3)
Page 93 of 488
+136 to +139 (008816 to 008B16) 34
+140 to +143 (008C16 to 008F16) 35
+144 to +147 (009016 to 009316)
36
+148 to +151 (009416 to 009716)
37
+152 to +155 (009816 to 009B16) 38
10. Interrupts
M32C/83 Group (M32C/83, M32C/83T)
Table 10.2 Relocatable Vector Tables (Continued)
Interrupt Generated by
Vector Table Address
Address(L)to Address(H)(1)
Software
Interrupt Number
Bus Conflict Detect, Start Condition Detect, +156 to +159 (009C16 to 009F16) 39
Reference
Serial I/O
Stop Condition Detect, (UART2)(3),
Fault Error(4)
Bus Conflict Detect, Start Condition Detect, +160 to +163 (00A016 to 00A316) 40
Stop Condition Detect,
(UART3/UART0)(5), Fault Error(4)
Bus Conflict Detect, Start Condition Select, +164 to +167 (00A416 to 00A716) 41
Stop Condition Detect,
(UART4/UART1)(5), Fault Error(4)
A/D0
+168 to +171 (00A816 to 00AB16) 42
A/D Converter
Key Input
+172 to +175 (00AC16 to 00AF16) 43
Interrupts
Intelligent I/O Interrupt 0
+176 to +179 (00B016 to 00B316) 44
Intelligent I/O
Intelligent I/O Interrupt 1
+180 to +183 (00B416 to 00B716) 45
CAN
Intelligent I/O Interrupt 2
+184 to +187 (00B816 to 00BB16) 46
Intelligent I/O Interrupt 3
+188 to +191 (00BC16 to 00BF16) 47
Intelligent I/O Interrupt 4
+192 to +195 (00C016 to 00C316) 48
Intelligent I/O Interrupt 5
+196 to +199 (00C416 to 00C716) 49
Intelligent I/O Interrupt 6
+200 to +203(00C816 to 00CB16) 50
Intelligent I/O Interrupt 7
+204 to +207(00CC16 to 00CF16) 51
Intelligent I/O Interrupt 8
+208 to +211(00D016 to 00D316)
Intelligent I/O Interrupt 9, CAN 0
+212 to +215 (00D416 to 00D716) 53
Intelligent I/O Interrupt 10, CAN 1
+216 to +219 (00D816 to 00DB16) 54
Reserved Space
+220 to +227 (00DC16 to 00E316) 55 to 56
Intelligent I/O Interrupt 11, CAN 2
+228 to +231 (00E416 to 00E716) 57
52
Intelligent I/O
CAN
Reserved Space
+232 to +255 (00E816 to 00FF16) 58 to 62
INT Instruction(2)
+0 to +3 (000016 to 000316) to
0 to 63
Interrupts
+252 to +255 (00FC16 to 00FF16)
NOTES:
1. These addresses are relative to those in the INTB register.
2. The I flag does not disable interrupts.
3. In I2C mode, NACK, ACK or start/stop condition detection causes interrupts to be generated.
_____
4. When the SS pin is selected, fault error causes an interrupt to be generated.
5. The IFSR6 bit in the IFSR register determines whether these addresses are used for an interrupt in UART0 or in
UART3.
The IFSR7 bit in the IFSR register determines whether these addresses are used for an interrupt in UART1 or in
UART4.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 94 of 488
10. Interrupts
M32C/83 Group (M32C/83, M32C/83T)
10.6 Interrupt Request Reception
Software interrupts and special interrupts occur when conditions to generate an interrupt are met.
The peripheral function interrupts are acknowledged when all conditions below are met.
• I flag
= "1"
• IR bit
= "1"
• ILVL2 to ILVL0 bits
> IPL
The I flag, IPL, IR bit and ILVL2 to ILVL0 bits are independent of each other. The I flag and IPL are in the
FLG register. The IR bit and ILVL2 to ILVL0 bits are in the interrupt control register.
10.6.1 I Flag and IPL
The I flag enables or disables maskable interrupts. When the I flag is set to "1" (enable), all maskable
interrupts are enabled; when the I flag is set to "0" (disable), they are disabled. The I flag is automatically
set to "0" after reset.
IPL, consisting of three bits, indicates the interrupt priority level from level 0 to level 7.
If a requested interrupt has higher priority than that indicated by IPL, the interrupt is acknowledged.
Table 10.3 lists interrupt priority levels associated with IPL.
Table 10.3 Interrupt Priority Levels
IPL2
IPL1
IPL0
Interrupt Priority Levels
0
0
0
Level 1 and above
0
0
1
Level 2 and above
0
1
0
Level 3 and above
0
1
1
Level 4 and above
1
0
0
Level 5 and above
1
0
1
Level 6 and above
1
1
0
Level 7 and above
1
1
1
All maskable interrupts are disabled
10.6.2 Interrupt Control Register and RLVL Register
The peripheral function interrupts use interrupt control registers to control each interrupt. Figures 10.3
and 10.4 show the interrupt control register. Figure 10.5 shows the RLVL register.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 95 of 488
10. Interrupts
M32C/83 Group (M32C/83, M32C/83T)
Interrupt Control Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TA0IC to TA4IC
TB0IC to TB5IC
Address
006C16, 008C16, 006E16, 008E16, 007016
009416, 007616, 009616, 007816, 009816, 006916
S0TIC to S4TIC
S0RIC to S4RIC
009016, 009216, 008916, 008B16, 008D16
007216, 007416, 006B16, 006D16, 006F16
007116, 009116, 008F16, 007116(1), 009116(2)
BCN0IC to BCN4IC
DM0IC to DM3IC
AD0IC, AD1IC
KUPIC
IIO0IC to IIO5IC
After Reset
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
006816, 008816, 006A16, 008A16
XXXX X0002
007316, 008616
009316
007516, 009516, 007716, 009716, 007916, 009916
XXXX X0002
XXXX X0002
XXXX X0002
IIO6IC to IIO11IC
007B16, 009B16, 007D16, 009D16, 007F16, 008116 XXXX X0002
CAN0IC0 to CAN2IC 009D16, 007F16, 008116(3)
XXXX X0002
Bit
Symbol
Bit Name
Function
RW
b2 b1 b0
ILVL0
ILVL1
Interrupt Priority Level
Select Bit
ILVL2
IR
(b7 - b4)
Interrupt Request Bit
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0 : No interrupt requested
1 : Interrupt requested(4)
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
NOTES:
1. The BCN0IC register shares an address with the BCN3IC register.
2. The BCN1IC register shares an address with the BCN4IC register.
3. The IIO9IC register shares an address with the CAN0IC register.
The IIO10IC register shares an address with the CAN1IC register.
The IIO11IC register shares an address with the CAN2IC register.
4. The IR bit can be set to "0" only (do not set to "1").
Figure 10.3 Interrupt Control Register (1)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 96 of 488
RW
RW
RW
RW
10. Interrupts
M32C/83 Group (M32C/83, M32C/83T)
Interrupt Control Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
INT0IC to INT2IC
INT3IC to INT5IC(1)
Bit
Symbol
Address
009E16, 007E16, 009C16
007C16, 009A16, 007A16
Bit Name
After Reset
XX00 X0002
XX00 X0002
Function
RW
b2 b1 b0
ILVL0
ILVL1
Interrupt Priority Level
Select Bit
ILVL2
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
RW
RW
RW
Interrupt Request Bit
0 : Requests no interrupt
1 : Requests an interrupt(2)
RW
POL
Polarity Switch Bit
0 : Selects falling edge or "L"(3)
1 : Selects rising edge or "H"
RW
LVS
Level Sensitive/Edge
Sensitive Switch Bit
0 : Edge sensitive
1 : Level sensitive(4)
RW
IR
(b7 - b6)
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
NOTES:
1. When the 16-bit data bus is used in microprocessor or memory expansion mode, each pin for the
INT3 to INT5 bits is used as the data bus. Set the ILVL2 to ILVL0 bits in the INT3IC, INT4IC and
INT5IC registers to "0002".
2. The IR bit can be set to "0" only (do not set to "1").
3. Set the POL bit to "0" when a corresponding bit in the IFSR register is set to "1" (both edges).
4. When setting the LVS bit to "1", set a bit corresponding to the IFSR register to "0" (one edge).
Figure 10.4 Interrupt Control Register (2)
10.6.2.1 ILVL2 to ILVL0 Bits
The ILVL2 to ILVL0 bits determines the interrupt priority level. The higher the interrupt priority level,
the higher interrupt priority is.
When an interrupt request is generated, its interrupt priority level is compared to IPL. This interrupt is
acknowledged only when its interrupt priority level is higher than IPL. When the ILVL2 to ILVL0 bits
are set to "0002" (level 0), this interrupt is ignored.
10.6.2.2 IR Bit
The IR bit is automatically set to "1" (interrupt requested) when an interrupt request is generated. The
IR bit is automatically set to "0" (no interrupt requested) after an interrupt request is acknowledged and
the program in the corresponding interrupt vector is executed.
The IR bit can be set to "0" by program. Do not set to "1".
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 97 of 488
10. Interrupts
M32C/83 Group (M32C/83, M32C/83T)
Exit Priority Register
b7
b6
b5
b4
b3
b2
b1
Symbol
RLVL
b0
Bit
Symbol
Address
009F16
Bit Name
Function
b2 b1 b0
RLVL0
RLVL1
After Reset
XXXX 00002
Stop/Wait Mode Exit
Minimum Interrupt Priority
Level Control Bit(1)
RLVL2
0 0 0 : Level 0
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0: Interrupt priority level 7 is used
for normal interrupt
1: Interrupt priority level 7 is used
for high-speed interrupt
FSIT
High-Speed Interrupt
Set Bit(2)
(b4)
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
DMA II
DMAC II Select Bit(4)
0: Interrupt priority level 7 is used
for interrupt
1: Interrupt priority level 7 is used
for DMAC II transfer(3)
RW
RW
RW
RW
RW
RW
Nothing is assigned. When write, set to "0".
(b7 - b6) When read, its content is indeterminate.
NOTES:
1. The microcomputer exits stop or wait mode when the requested interrupt priority level is higher than
the level set in the RLVL2 to RLVL0 bits. Set the RLVL2 to RLVL0 bits to the same value as IPL in
the FLG register.
2. When the FSIT bit is set to "1", interrupt priority level 7 becomes the high-speed interrupt. In this
case, set only one interrupt to interrupt priority level 7 and the DMA II bit to "0".
3. Set the ILVL2 to ILVL0 bits in the interrupt control register after setting the DMAII bit to "1". Do not
change the DMAII bit setting to "0" after setting the DMAII bit to "1". Set the FSIT bit to "0" when the
DMAII bit to "1".
4. After reset, the DMA II bit is indeterminate. When using an interrupt, set the interrupt control register
after setting the DMA II bit to "0".
Figure 10.5 RLVL Register
10.6.2.3 RLVL2 to RLVL0 Bits
When using an interrupt to exit stop or wait mode, refer to 8.5.2 Wait Mode and 8.5.3 Stop Mode for
details.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 98 of 488
M32C/83 Group (M32C/83, M32C/83T)
10. Interrupts
10.6.3 Interrupt Sequence
The interrupt sequence is performed between an interrupt request acknowledgment and interrupt routine
execution.
When an interrupt request is generated while an instruction is executed, the CPU determines its interrupt
priority level after the instruction is completed. The CPU starts the interrupt sequence from the following
cycle. However, in regards to the SCMPU, SIN, SMOVB, SMOVF, SMOVU, SSTR, SOUT or RMPA
instruction, if an interrupt request is generated while executing the instruction, the microcomputer suspends the instruction to start the interrupt sequence.
The interrupt sequence is performed as follows:
(1) The CPU obtains interrupt information (interrupt number and interrupt request level) by reading
address 00000016 (address 00000216 for the high-speed interrupt). Then, the IR bit applicable to
the interrupt information is set to "0" (interrupt requested).
(2) The FLG register, prior to an interrupt sequence, is saved to a temporary register(1) within the CPU.
(3) Each bit in the FLG register is set as follows:
• The I flag is set to "0" (interrupt disabled)
• The D flag is set to "0" (single-step disabled)
• The U flag is set to "0" (ISP selected)
(4) A temporary register within the CPU is saved to the stack; or to the SVF register for the high-speed
interrupt.
(5) PC is saved to the stack; or to the SVP register for the high-speed interrupt.
(6) The interrupt priority level of the acknowledged interrupt is set in IPL .
(7) A relocatable vector corresponding to the acknowledged interrupt is stored into PC.
After the interrupt sequence is completed, an instruction is executed from the starting address of the
interrupt service routine.
NOTES:
1. Temporary register cannot be modified by users.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 99 of 488
10. Interrupts
M32C/83 Group (M32C/83, M32C/83T)
10.6.4 Interrupt Response Time
Figure 10.6 shows an interrupt response time. Interrupt response time is the period between an interrupt
generation and the execution of the first instruction in an interrupt service routine. An interrupt response
time includes the period between an interrupt request generation and the completed execution of an instruction ((a) in Figure 10.6) and the period required to perform an interrupt sequence ((b) in Figure 10.6).
Interrupt request is generated
Interrupt request is acknowledged
Time
Instruction
(a)
Interrupt sequence
Instruction in an
interrupt routine
(b)
Interrupt response time
(a) Period between an interrupt request generation and the completed execution of an instruction.
(b) Period required to perform an interrupt sequence.
Figure 10.6 Interrupt Response Time
Time (a) varies depending on the instruction being executed. The DIV instruction requires the longest
time (a); 40 cycles when an immediate value or register is set as the divisor .
When the divisor is a value in the memory, the following value is added.
• Normal addressing
:2+X
• Index addressing
:3+X
• Indirect addressing
: 5 + X + 2Y
• Indirect index addressing
: 6 + X + 2Y
X is the number of wait states for a divisor space. Y is the number of wait states for the space that stores
indirect addresses. If X and Y are in an odd address or in 8-bit bus space, the X and Y value must be
doubled.
Table 10.4 lists time (b).
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 100 of 488
10. Interrupts
M32C/83 Group (M32C/83, M32C/83T)
Table 10.4 Interrupt Sequence Execution Time
Interrupt
Peripheral Function
16-Bit Bus
Interrupt Vector Address
8-Bit Bus
Even address
14 cycles
16 cycles
Odd address(1)
16 cycles
16 cycles
Even address
12 cycles
14 cycles
Odd address(1)
14 cycles
14 cycles
Even address(2)
13 cycles
15 cycles
Overflow
Even address(2)
14 cycles
16 cycles
BRK Instruction (relocatable vector table)
Even address
17 cycles
19 cycles
Odd address(1)
19 cycles
19 cycles
BRK Instruction (fixed vector table)
Even address(2)
19 cycles
21 cycles
High-Speed Interrupt
Vector table is internal register
5 cycles
INT Instruction
_______
NMI
Watchdog Timer
Undefined Instruction
Address Match
NOTES:
1. Allocate interrupt vectors to even addresses.
2. Vectors are fixed to even addresses.
10.6.5 IPL Change when Interrupt Request is Acknowledged
When a peripheral function interrupt request is acknowledged, IPL sets the priority level for the acknowledged interrupt.
Software interrupts and special interrupts have no interrupt priority level. If an interrupt request that has
no interrupt priority level is acknowledged, the value shown in Table 10.5 is set in IPL as the interrupt
priority level.
Table 10.5 Interrupts without Interrupt Priority Levels and IPL
Interrupt Sources
Level that is Set to IPL
_______
Watchdog Timer, NMI, Oscillation Stop Detect
7
Reset
0
Software, Address Match
Not changed
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 101 of 488
10. Interrupts
M32C/83 Group (M32C/83, M32C/83T)
10.6.6 Saving a Register
In the interrupt sequence, the FLG register and PC are saved to the stack.
After the FLG register is saved to the stack, 16 high-order bits and 16 low-order bits of PC, extended to 32
bits, are saved to the stack. Figure 10.7 shows the stack state before and after an interrupt request is
acknowledged.
Other important registers are saved by program at the beginning of an interrupt service routine. The
PUSHM instruction can save all registers except SP.
Refer to 10.4 High-Speed Interrupt for the high-speed interrupt.
Address
The Stack
MSB
Address
LSB
The Stack
MSB
LSB
PCL
m-6
m-6
m-5
m-5
PCM
m–4
m–4
PCH
m–3
m–3
00 16
m–2
m–2
FLG L
m–1
m–1
m
Content of
previous stack
m+1
Content of
previous stack
[SP]
SP value before
interrupt is
generated
Stack state before an interrupt request is acknowledged
m
m+1
[SP]
New SP value
FLGH
Content of
previous stack
Content of
previous stack
Stack state after an interrupt request is acknowledged
Figure 10.7 Stack States
10.6.7 Restoration from Interrupt Routine
When the REIT instruction is executed at the end of an interrupt service routine, the FLG register and PC,
which have been saved to the stack, are automatically restored. The program, executed before an interrupt
request has been acknowledged, starts running again. Refer to 10.4 High-Speed Interrupt for the highspeed interrupt.
Restore registers saved by program in an interrupt service routine by the POPM instruction or others
before the REIT and FREIT instructions. Register bank is switched back to the bank used prior to the
interrupt sequence by the REIT or FREIT instruction.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 102 of 488
M32C/83 Group (M32C/83, M32C/83T)
10. Interrupts
10.6.8 Interrupt Priority
If two or more interrupt requests are sampled at the same sampling points (a timing to detect whether an
interrupt request is generated or not), the interrupt with the highest priority is acknowledged.
Set the ILVL2 to ILVL0 bits to select the desired priority level for maskable interrupts (peripheral function
interrupt).
Priority levels of special interrupts such as reset (reset has the highest priority) and watchdog timer are
set by hardware. Figure 10.8 shows priority levels of hardware interrupts.
The interrupt priority does not affect software interrupts. The microcomputer jumps to the interrupt routine when the instruction is executed.
_______
Reset > NMI >
Oscillation Stop Detect
> Peripheral Function > Address Match
Watchdog
Figure 10.8 Interrupt Priority
10.6.9 Interrupt Priority Level Select Circuit
The interrupt priority level select circuit selects the highest priority interrupt when two or more interrupt
requests are sampled at the same sampling point.
Figure 10.9 shows the interrupt priority level select circuit.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 103 of 488
10. Interrupts
M32C/83 Group (M32C/83, M32C/83T)
High
Each Interrupt Priority Level
Level 0 (initial value)
A/D1 Converter
DMA0
DMA1
DMA2
Each Interrupt Priority Level
DMA3
Timer A0
A/D0 Converter
Timer A1
Key Input Interrupt
Timer A2
Intelligent I/O Interrupt 0
Timer A3
Intelligent I/O Interrupt 1
Timer A4
Intelligent I/O Interrupt 2
UART0 Transmission/NACK
Intelligent I/O Interrupt 3
UART0 Reception/ACK
Intelligent I/O Interrupt 4
UART1 Transmission/NACK
Intelligent I/O Interrupt 5
UART1 Reception/ACK
Intelligent I/O Interrupt 6
Timer B0
Intelligent I/O Interrupt 7
Timer B1
Intelligent I/O Interrupt 8
Timer B2
Intelligent I/O Interrupt 9
/CAN Interrupt 0
Timer B3
Intelligent I/O Interrupt 10
/CAN Interrupt 1
Timer B4
Intelligent I/O Interrupt 11
/CAN Interrupt 2
INT5
RLVL2 to RLVL0 Bits
INT4
Interrupt
request is
acknowledged.
To CLK
INT3
INT2
IPL
INT1
I Flag
INT0
Timer B5
Address Match
UART2 Transmission/NACK
Watchdog Timer,
Oscillation Stop Detect
UART2 Reception/ACK
NMI
DMAC II
UART3 Transmission/NACK
Reset
UART3 Reception/ACK
UART4 Transmission/
NACK
UART4 Reception/ACK
Bus Conflict/Start, Stop
Condition(UART2)
Bus Conflict/Start, Stop Condition(
UART0,3)
Bus Conflict/Start, Stop
Condition(UART1,4)
Low
Peripheral Function Interrupt Priority
(if priority levels are the same)
Figure 10.9 Interrupt Priority Level Select Circuit
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 104 of 488
Interrupt
request is
acknowledged.
To CPU
10. Interrupts
M32C/83 Group (M32C/83, M32C/83T)
______
10.7 INT Interrupt
______
External input generates the INTi interrupt (i = 0 to 5). The LVS bit in the INTiIC register selects either edge
sensitive triggering to generate an interrupt on any edge or level sensitive triggering to generate an interrupt at an applied signal level. The POL bit in the INTiIC register determines the polarity.
With an edge sensitive triggering, when the IFSRi bit in the IFSR register is set to "1" (both edges), an
interrupt occurs on both rising and falling edges of the external input. If the IFSRi bit is set to "1", set the
POL bit in the corresponding register to "0" (falling edge).
_______
With a level sensitive triggering, set the IFSRi bit to "0" (single edge). When the INTi pin input level reaches
the level set in the POL bit, the IR bit in the INTiIC register is set to "1". The IR bit remains set to "1" even
_______
_______
if the INTi pin level is changed. The IR bit is set to "0" when the INTi interrupt is acknowledged or when "0"
is written by program.
Figure 10.10 shows the IFSR register.
External Interrupt Request Cause Select Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
IFSR
Address
031F16
After Reset
0016
Bit
Symbol
Bit Name
IFSR0
INT0 Interrupt Polarity
Select Bit(1)
0 : One edge
1 : Both edges
RW
IFSR1
INT1 Interrupt Polarity
Select Bit(1)
0 : One edge
1 : Both edges
RW
IFSR2
INT2 Interrupt Polarity
Select Bit(1)
0 : One edge
1 : Both edges
RW
IFSR3
INT3 Interrupt Polarity
Select Bit(1)
0 : One edge
1 : Both edges
RW
IFSR4
INT4 Interrupt Polarity
Select Bit(1)
0 : One edge
1 : Both edges
RW
IFSR5
INT5 Interrupt Polarity
Select Bit(1)
0 : One edge
1 : Both edges
RW
IFSR6
IFSR7
UART0, UART3
Interrupt Cause Select
Bit
Function
0 : UART3 bus conflict, start condition
detect, stop condition detect, fault
error detect
RW
1 : UART0 bus conflict, start condition
detect, stop condition detect, fault
error detect
0 : UART4 bus conflict, start condition
detect, stop condition detect, fault
UART1, UART4
error detect
RW
Interrupt Cause Select 1 : UART1 bus conflict, start condition
detect, stop condition detect, fault
Bit
error detect
NOTES:
1.Set this bit to "0" to select level sensitive.
When setting this bit to "1", set the POL bit in the INTilC register (i = 0 to 5) to "0" (falling edge).
Figure 10.10 IFSR Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 105 of 488
RW
10. Interrupts
M32C/83 Group (M32C/83, M32C/83T)
______
10.8 NMI Interrupt
______
______
The NMI interrupt occurs when the signal applied to the P85/NMI pin changes from an "H" signal to an "L"
______
______
______
signal. The NMI interrupt is a non-maskable interrupt. Although the P85/NMI pin is used as the NMI interrupt input pin, the P8_5 bit in the P85 register indicates input level for this pin.
NOTES:
______
______
______
When the NMI interrupt is not used, connect (pull-up) the NMI pin to Vcc via a resistor. Because the NMI
interrupt cannot be ignored, the pin must be connected.
10.9 Key Input Interrupt
Key input interrupt request is generated when one of the signals applied to the P104 to P107 pins in input
mode is on the falling edge. The key input interrupt can be also used as key-on wake-up function to exit wait
or stop mode. To use the key input interrupt, do not use P104 to P107 as A/D input ports. Figure 10.11
shows a block diagram of the key input interrupt. When an "L" signal is applied to any pins in input mode,
signals applied to other pins are not detected as a request signal for an interrupt.
When the PSC_7 bit in the PSC register(1) is set to "1" (key input interrupt disabled), no key input interrupt
occurs regardless of interrupt control register settings. When the PSC_7 bit is set to "1", no input from a
port pin is available even when in input mode.
NOTES:
1. Refer to 24. Programmable I/O Ports for details on the PSC register.
PU31 bit in PUR3 register
Pull-up
transistor
PD10_7 bit
PSC_7 bit
KUPIC Register
PD10_7 bit
P107/KI3
Pull-up
transistor
PD10_6 bit
Interrupt Control
Circuit
P106/KI2
Pull-up
transistor
PD10_5 bit
P105/KI1
Pull-up
transistor
PD10_4 bit
P104/KI0
Figure 10.11 Key Input Interrupt
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 106 of 488
Key Input Interrupt
Request
10. Interrupts
M32C/83 Group (M32C/83, M32C/83T)
10.10 Address Match Interrupt
The address match interrupt occurs immediately before executing an instruction that is stored into an address indicated by the RMADi register (i=0 to 3). The address match interrupt can be set in four addresses.
The AIERi bit in the AIER register determines whether the interrupt is enabled or disabled. The I flag and
IPL do not affect the address match interrupt.
Figure 10.12 shows registers associated with the address match interrupt.
Set the starting address of an instruction in the RMADi register. The address match interrupt does not
occur when a table data or addresses other than the starting address of the instruction is set.
Address Match Interrupt Enable Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
AIER
000916
Bit
Symbol
After Reset
XXXX 00002
Function
Bit Name
RW
AIER0
Address Match
Interrupt 0 Enable Bit
0 : Disables the interrupt
1 : Enables the interrupt
RW
AIER1
Address Match
Interrupt 1 Enable Bit
0 : Disables the interrupt
1 : Enables the interrupt
RW
AIER2
Address Match
Interrupt 2 Enable Bit
0 : Disables the interrupt
1 : Enables the interrupt
RW
AIER3
Address Match
Interrupt 3 Enable Bit
0 : Disables the interrupt
1 : Enables the interrupt
RW
Nothing is assigned. When write, set to "0".
(b7 - b4) When read, its content is indeterminate.
Address Match Interrupt Register i
b23
b16 b15
b8 b7
b0
Symbol
RMAD0
RMAD1
RMAD2
RMAD3
Address
001216 - 001016
After Reset
00000016
001616 - 001416
001A16 - 001816
001E16 - 001C16
00000016
00000016
00000016
Function
Addressing Register for the Address Match Interrupt
Figure 10.12 AIER Register and RMAD0 to RMAD3 Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 107 of 488
Setting Range
RW
00000016 to FFFFFF16
RW
10. Interrupts
M32C/83 Group (M32C/83, M32C/83T)
10.11 Intelligent I/O Interrupt and CAN Interrupt
The intelligent I/O interrupt and CAN interrupt are assigned to software interrupt numbers 44 to 54, and 57.
Figure 10.13 shows a block diagram of the intelligent I/O interrupt and CAN interrupt. Figure 10.14 shows
the IIOiIR register (i = 0 to 11). Figure 10.15 shows the IIOiIE register.
When using the intelligent I/O interrupt or CAN interrupt, set the IRLT bit in the IIOiIE register to "1" (interrupt request for interrupt used).
Various interrupt requests cause the intelligent I/O interrupt to occur. When an interrupt request is generated with intelligent I/O or CAN functions, the corresponding bit in the IIOiIR register is set to "1" (interrupt
requested). When the corresponding bit in the IIOiIE register is set to "1" (interrupt enabled), the IR bit in
the corresponding IIOiIC register is set to "1" (interrupt requested).
After the IR bit setting changes from "0" to "1", the IR bit remains set to "1" when a bit in the IIOiIR register
is set to "1" by another interrupt request and the corresponding bit in the IIOiIE register is set to "1".
Bits in the IIOiIR register are not set to "0" automatically, even if an interrupt is acknowledged. Set each bit
to "0" by program. If these bits remain set to "1", all generated interrupt requests are ignored.
CAN interrupt uses bit 7 in the IIO9IR to IIO11IR registers and bit 7 in the IIO9IE to IIO11IE registers. IIO9IR
to IIO11IR registers share addresses with the CAN0IC to CAN2IC registers. Refer to 22.3 CAN Interrupt
for details.
IIOiIR Register(2)
IRLT Bit in
IIOiIE Register
0
Bit 1
Interrupt Request(1)
1
Intelligent I/O Interrupt i Request
0
Bit 2
Interrupt Request(1)
1
0
Bit 7
Interrupt Request(1)
1
IIOiIE Register(3)
Bit 1
Bit 2
Bit 7
NOTES:
1. See Figures 10.14 and 10.15 for details on bits 1 to 7 in
the IIOiIR register and bits 1 to 7 in the IIOiIE register.
2. Bits 1 to 7 in the IIOiIR register are not set to "0"
automatically even if an interrupt request is generated.
Set to "0" by program.
3. Do not change the IRLT bit and the interrupt enable bit in
the IIOiIE register simultaneously.
i= 0 to 11
Figure 10.13 Intelligent I/O Interrupt and CAN Interrupt
When using the intelligent I/O interrupt or CAN interrupt to activate DMAC II, set the IRLT bit in the IIOiIE
register to "0" (an interrupt used for DMAC, DMAC II) to enable the interrupt request that the IIOiIE register
requires.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 108 of 488
10. Interrupts
M32C/83 Group (M32C/83, M32C/83T)
Interrupt Request Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
After Reset
IIO0IR to IIO11IR
See below
0000 000X2
Bit
Symbol
Function
RW
Nothing is assigned. When write, set to "0".
(b0)
(Note 1)
(Note 1)
When read, its content is indeterminate.
RW
0 : Requests no interrupt
1 : Requests an interrupt
( Note 2)
RW
(Note 1)
RW
(Note 1)
RW
(Note 1)
RW
(Note 1)
RW
(Note 1)
RW
NOTES:
1. See table below for bit symbols.
2. Only "0" can be set (nothing is changed even if "1" is set).
Bit Symbols for the Interrupt Request Register
Symbol
Address
Bit 7
Bit 6
Bit 5
IIO0IR
00A016
-
-
IIO1IR
00A116
-
-
IIO2IR
00A216
-
IIO3IR
00A316
IIO4IR
00A416
IIO5IR
00A516
IIO6IR
IIO7IR
IIO8IR
Bit 1
Bit 0
PO13R
TM02R
-
PO14R
TM00R/PO00R
-
TM12R/PO12R
-
-
PO10R
TM03R
-
Bit 4
Bit 3
Bit 2
SIO0RR
G0RIR
-
SIO0TR
G0TOR
-
-
SIO1RR
G1RIR
-
-
-
SIO1TR
G1TOR
PO27R
SRT0R
SRT1R
-
BT1R
PO32R
-
-
-
SIO2RR
PO33R
PO21R
TM05R/PO05R
-
00A616
-
-
-
SIO2TR
PO34R
PO20R
TM06R
-
00A716
IE0R
-
-
BT0R
PO35R
PO22R
TM07R
-
00A816
IE1R
IE2R
-
BT2R
PO36R
PO23R
TM11R/PO11R
-
TM17R/PO17R TM04R/PO04R
-
IIO9IR
00A916
CAN0R
-
-
SIO3RR
PO31R
PO24R
PO15R
-
IIO10IR
00AA16
CAN1R
-
-
SIO3TR
PO30R
PO25R
TM16R/PO16R
-
IIO11IR
00AB16
CAN2R
-
-
BT3R
PO37R
PO26R
TM01R/PO01R
-
BTiR
: Intelligent I/O Group i Base Timer Interrupt Request Bit (i=0 to 3)
TMmjR
: Intelligent I/O Group m Time Measurement j Interrupt Request Bit (j=0 to 7)(m=0,1)
POijR
: Intelligent I/O Group i Waveform Generation Function j Interrupt Request Bit
SIOiRR/SIOiTR : Intelligent I/O Group i Communication Function Interrupt Request Bit (RR:receive, TR:transmit)
GmRIR/GmTOR: Intelligent I/O Group m HDLC Data Processing Function Interrupt Request Bit
(RIR:input to receive, TOR:input to transmit)
SRTmR
: Intelligent I/O Group m Special Communication Function Interrupt Request Bit
IEkR
: Intelligent I/O Group 2 IEBus Communication Function Interrupt Request Bit (k = 0 to 2)
CANkR
: CAN Communication Function Interrupt Request Bit
: Reserved bit. Set to "0".
Figure 10.14 IIO0IR to IIO11IR Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 109 of 488
10. Interrupts
M32C/83 Group (M32C/83, M32C/83T)
Interrupt Enable Register
b7
b6
b5
b4
b3
b2
b1
b0
Bit
Symbol
IRLT
After Reset
0016
Address
Symbol
IIO0IE to IIO11IE
See below
Bit Name
Interrupt Request
Select Bit(2)
RW
Function
0 : Interrupt request is used for DMAC, DMAC II
1 : Interrupt request is used for interrupt
RW
(Note 1)
0 : Disables an interrupt by bit 1 in IIOiIR register
RW
1 : Enables an interrupt by bit 1 in IIOiIR register
(Note 1)
0 : Disables an interrupt by bit 2 in IIOiIR register
RW
1 : Enables an interrupt by bit 2 in IIOiIR register
(Note 1)
0 : Disables an interrupt by bit 3 in IIOiIR register
RW
1 : Enables an interrupt by bit 3 in IIOiIR register
(Note 1)
0 : Disables an interrupt by bit 4 in IIOiIR register
RW
1 : Enables an interrupt by bit 4 in IIOiIR register
0 : Disables an interrupt by bit 5 in IIOiIR register
(Note 1)
1 : Enables an interrupt by bit 5 in IIOiIR register
RW
(Note 1)
0 : Disables an interrupt by bit 6 in IIOiIR register
RW
1 : Enables an interrupt by bit 6 in IIOiIR register
(Note 1)
0 : Disables an interrupt by bit 7 in IIOiIR register
RW
1 : Enables an interrupt by bit 7 in IIOiIR register
NOTES:
1. See table below for bit symbols.
2. If an interrupt request is used for interrupt, set bit 1 to 7 to "1" after the IRLT bit is set to "1".
Bit Symbols for the Interrupt Enable Register
Symbol
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IIO0IE
00B016
-
-
SIO0RE
G0RIE
-
PO13E
TM02E
IRLT
IIO1IE
00B116
-
-
SIO0TE
G0TOE
-
PO14E
TM00E/PO00E
IRLT
IIO2IE
00B216
-
-
SIO1RE
G1RIE
-
TM12E/PO12E
-
IRLT
IIO3IE
00B316
-
-
SIO1TE
G1TOE
PO27E
PO10E
TM03E
IRLT
IIO4IE
00B416
SRT0E
SRT1E
-
BT1E
PO32E
IIO5IE
00B516
-
-
-
SIO2RE
PO33E
IIO6IE
00B616
-
-
-
SIO2TE
IIO7IE
00B716
IE0E
-
-
IIO8IE
00B816
IE1E
IE2E
IIO9IE
00B916
CAN0E
IIO10IE
00BA16
IIO11IE
00BB16
BTiE
TMmjE
POijE
SIOiRE/SIOiTE
GmRIE/GmTOE
SRTmE
IEkE
CANkE
-
TM17E/PO17E TM04E/PO04E
IRLT
PO21E
TM05E/PO05E
IRLT
PO34E
PO20E
TM06E
IRLT
BT0E
PO35E
PO22E
TM07E
IRLT
-
BT2E
PO36E
PO23E
TM11E/PO11E
IRLT
-
-
SIO3RE
PO31E
PO24E
PO15E
IRLT
CAN1E
-
-
SIO3TE
PO30E
PO25E
TM16E/PO16E
IRLT
CAN2E
-
-
BT3E
PO37E
PO26E
TM01E/PO01E
IRLT
: Intelligent I/O Group i Base Timer Interrupt Enable Bit (i=0 to 3)
: Intelligent I/O Group m Time Measurement j Interrupt Enable Bit (j=0 to 7)(m=0,1)
: Intelligent I/O Group i Waveform Generation Function j Interrupt Enable Bit
: Intelligent I/O Group i Communication Function Interrupt Enable Bit (RE:receive, TE:transmit)
: Intelligent I/O Group m HDLC Data Processing Function Interrupt Enable Bit
(RIE:input to receive, TOE:input to transmit)
: Intelligent I/O Group m Special Communication Function Interrupt Enable Bit
: Intelligent I/O Group 2 IEBus Communication Function Interrupt Enable Bit (k=0 to 2)
: CAN Communication Function Interrupt Enable Bit
: Reserved bit. Set to "0".
Figure 10.15 IIO0IE to IIO11IE Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 110 of 488
11. Watchdog Timer
M32C/83 Group (M32C/83, M32C/83T)
11. Watchdog Timer
The watchdog timer detects a program which is out of control. The watchdog timer contains a 15-bit counter
which is decremented by the CPU clock that the prescaler divides. The CM06 bit in the CM0 register
determines whether the watchdog timer interrupt request or reset is generated when the watchdog timer
underflows. The CM06 bit can be set to "1" (reset) only. Once the CM06 bit is set to "1", it cannot be
changed to "0" ( watchdog timer interrupt) by program. The CM06 bit is set to "0" only after reset.
When the main clock, on-chip oscillator clock, or the PLL clock runs as the CPU clock, the WDC7 bit in the
WDC register determines whether the prescaler divides by 16 or by 128. When the sub clock runs as the
CPU clock, the prescaler divides by 2 regardless of the WDC7 bit setting. Watchdog timer cycle is calculated as follows. Marginal errors, due to the prescaler, may occur in watchdog timer cycle.
When the main clock, on-chip oscillator clock, or PLL clock is selected as the CPU clock:
Divide by 16 or 128 prescaler x counter value of watchdog timer (32768)
CPU clock
Watchdog timer cycle =
When the sub clock is selected as the CPU clock,
Watchdog timer cycle =
Divided by 2 prescaler x counter value of watchdog timer (32768)
CPU clock
For example, if the CPU clock frequency is 30MHz and the prescaler divides by 16, watchdog timer cycle is
approximately 17.5 ms.
The watchdog timer is reset when the WDTS register is set and when a watchdog timer interrupt request is
generated. The prescaler is reset only when the microcomputer is reset. Both watchdog timer and prescaler
stop after reset. They begin counting when the WDTS register is set.
Write the WDTS register with shorter cycle than the watchdog timer cycle. Set the WDTS register also in the
beginning of the watchdog timer interrupt routine.
The watchdog timer and prescaler stop in stop mode, wait mode and hold state. They resume counting
from the value held when the mode or state is exited.
Figure 11.1 shows a block diagram of the watchdog timer. Figure 11.2 shows registers associated with the
watchdog timer.
Prescaler
1/16
CM07 = 0
WDC7 = 0
0
CPU Clock
1/128
CM07 = 0
WDC7 = 1
HOLD Signal
Watchdog Timer
1
Reset
CM06
CM07 = 1
1/2
Write to WDTS Register
Internal Reset Signal
CM06, CM07 : Bits in CM0 register
WDC7 : Bit in WDC register
Figure 11.1 Watchdog Timer Block Diagram
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Watchdog Timer
Interrupt Request
Page 111 of 488
Set to
7FFF16
11. Watchdog Timer
M32C/83 Group (M32C/83, M32C/83T)
Watchdog Timer Control Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
WDC
0 0
Address
000F16
Bit
Symbol
(b4 - b0)
(b6 - b5)
WDC7
After Reset
000X XXXX2
Bit Name
Function
High-Order Bit of Watchdog Timer
RW
RO
Reserved Bit
Set to "0"
RW
Prescaler Select Bit
0 : Divide-by-16
1 : Divide-by-128
RW
Watchdog Timer Start Register
b7
b0
Symbol
WDTS
Address
000E16
After Reset
Indeterminate
Function
The watchdog timer is reset to start counting by a write instruction to the
WDTS register. Default value of the watchdog timer is always set to
"7FFF16" regardless of the value written.
Figure 11.2 WDC Register and WDTS Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 112 of 488
RW
WO
11. Watchdog Timer
M32C/83 Group (M32C/83, M32C/83T)
System Clock Control Register 0(1)
b7
b6
b5
b4
b3
b2
b1
b0
1
Symbol
Address
CM0
000616
Bit
Symbol
After Reset
0000 X0002
Bit Name
Function
b1 b0
CM00
Clock Output Function
Select Bit(2)
CM01
0 0 : I/O port P53
0 1 : Outputs fC
1 0 : Outputs f8
1 1 : Outputs f32
RW
RW
RW
In Wait Mode,
Peripheral
Function Clock Stop Bit
0 : Peripheral clock does not stop in
wait mode
RW
1 : Peripheral clock stops in wait
(3)
mode
Reserved Bit
Set to "1"
CM04
Port XC Switch Bit
0 : I/O port function
RW
1 : XCIN-XCOUT oscillation function(4)
CM05
Main Clock (XIN-XOUT)
Stop Bit(5)
0 : Main clock oscillates
1 : Main clock stops(6)
RW
CM06
Watchdog Timer
Function Select Bit
0 : Watchdog timer interrupt
1 : Reset(7)
RW
CM07
System Clock Select Bit(8)
0: Clock selected by the CM21 bit
divided by MCD register setting
1: Sub clock
CM02
(b3)
RW
RW
NOTES:
1. Rewrite the CM0 register after the PRC0 bit in the PRCR register is set to "1" (write enable).
2. When the PM07 bit in the PM0 register is set to "0" (BCLK output), set the CM01 to CM00 bits to
"002". When the PM15 to PM14 bits in the PM1 register is set to "012" (ALE output to P53), set the
CM01 to CM00 bits to "002". When the PM07 bit is set to "1" (function selected in the CM01 to CM00
bits) in microprocessor or memory expansion mode, and the CM01 to CM00 bits are set to "002", an
"L" signal is output from port P53 (port P53 does not function as an I/O port).
3. fc32 does not stop. When the CM02 bit is set to "1", the PLL clock cannot be used in wait mode.
4. When setting the CM04 bit to "1" (XCIN-XCOUT oscillation), set the PD8_7 to PD8_6 bits to "002" (with
port P87 and P86 input mode) and the PU25 bit in the PUR2 register to "0" (no pull-up).
5. When entering the low-power consumption mode or on-chip oscillator low-power consumption mode,
the CM05 bit stops the main clock. The CM05 bit cannot detect whether the main clock stops or not.
To stop the main clock, set the CM05 bit to "1" after the CM07 bit is set to "1" with a stable sub clock
oscillation or after the CM21 bit in the CM2 register is set to "1" (on-chip oscillator clock). When the
CM05 bit is set to "1", XOUT becomes "H". The built-in feedback resistor remains on. XIN is pulled up
to XOUT ("H" level) via the feedback resistor.
6. When the CM05 bit is set to "1", the MCD register is set to "0816" (divide-by-8 mode). In on-chip
oscillation mode, the MCD register is not divided by eight even if the CM05 bit terminates XIN-XOUT.
7. Once the CM06 bit is set to "1", it cannot be set "0" by program.
8. After the CM04 bit is set to "1" with a stable sub clock oscillation, set the CM07 bit to "1" from "0".
After the CM05 bit is set to "0" with a stable main clock oscillation, set the CM07 bit to "0" from "1".
Do not set the CM07 bit and CM04 or CM05 bits simultaneously.
Figure 11.3 CM0 Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 113 of 488
12. DMAC
M32C/83 Group (M32C/83, M32C/83T)
12. DMAC
This microcomputer contains four DMAC (direct memory access controller) channels that allow data to be
sent to memory without using the CPU. DMAC transmits a 8- or 16-bit data from a source address to a
destination address whenever a transmit request occurs. DMA0 and DMA1 must be prioritized when using
DMAC. DMAC2 and DMAC3 share registers required for high-speed interrupts. High-speed interrupts
cannot be used when using three or more DMAC channels.
The CPU and DMAC use the same data bus, but DMAC has a higher bus access privilege than the CPU.
The cycle-steal method employed by DMAC enables high-speed operation between a transfer request and
the complete transmission of 16-bit (word) or 8-bit (byte) data. Figure 12.1 shows a mapping of registers to
be used for DMAC. Table 12.1 lists specifications of DMAC. Figures 12.2 to 12.5 show registers associated with DMAC.
Because the registers shown in Figure 12.1 are allocated to the CPU, use the LDC instruction to write to the
registers. To set DCT2, DCT3, DRC2, DRC3, DMA2 and DMA3 registers, set the B flag to "1" (register
bank 1) and set R0 to R3, A0, A1 registers with the MOV instruction.
To set DSA2 and DSA3 registers, set the B flag to "1" and set the SB, FB, SVP, VCT registers with the LDC
instruction. To set the DRA2 and DRA3 registers, set the SVP, VCT registers with the LDC instruction.
DMAC-Associated Registers
DMD0
DMA Mode Register 0
DMD1
DMA Mode Register 1
DCT0
DMA 0 Transfer Count Register
DCT1
DMA 1 Transfer Count Register
DRC0
DMA 0 Transfer Count Reload Register(1)
DRC1
DMA 1 Transfer Count Reload Register(1)
DMA0
DMA 0 Memory Address Register
DMA1
DMA 1 Memory Address Register
DSA0
DMA 0 SFR Address Register
DSA1
DMA 1 SFR Address Register
DRA0
DMA 0 Memory Address Reload Register(1)
DRA1
DMA 1 Memory Address Reload Register(1)
When Three or More DMAC Channels are Used,
the Register Bank 1 is Used as DMAC Registers
When Three or More DMAC Channels are Used,
the High-Speed Interrupt Register is Used as DMAC
Registers
Flag Save Register
DCT2 (R0)
DMA2 Transfer Count Register
SVF
DCT3 (R1)
DMA3 Transfer Count Register
DRA2 (SVP)
DMA2 Memory Address Reload Register(1)
DRC2 (R2)
DMA2 Transfer Count Reload Register(1)
DRA3 (VCT)
DMA3 Memory Address Reload Register(1)
DRC3 (R3)
DMA3 Transfer Count Reload Register(1)
DMA2 (A0)
DMA2 Memory Address Register
DMA3 (A1)
DMA3 Memory Address Register
DSA2 (SB)
DMA2 SFR Address Register
DSA3 (FB)
DMA3 SFR Address Register
NOTES:
1. Registers are used for repeat transter, not for single transfer.
Figure 12.1 Register Mapping for DMAC
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 114 of 488
When using DMA2 and DMA3, use the CPU registers shown in parentheses ().
M32C/83 Group (M32C/83, M32C/83T)
12. DMAC
DMAC starts a data transfer by setting the DSR bit in the DMiSL register (i=0 to 3) or by using an interrupt
request, generated by the functions determined by the DSEL 4 to DSEL0 bits in the DMiSL register, as a
DMA request. Unlike interrupt requests, the I flag and interrupt control register do not affect DMA. Therefore, a DMA request can be acknowledged even if an interrupt is disabled and cannot be acknowledged. In
addition, the IR bit in the interrupt control register does not change when a DMA request is acknowledged.
Table 12.1 DMAC Specifications
Item
Channels
Transfer Memory Space
Maximum Bytes Transferred
DMA Request Factors(1)
Specification
4 channels (cycle-steal method)
• From a desired address in a 16M-byte space to a fixed address in a
16M-byte space
• From a fixed address in a 16M-byte space to a desired address in a
16M-byte space
128K bytes (when a 16-bit data is transferred) or 64K bytes (when an 8bit data is transferred)
________
________
Falling edge or both edges of input signals to the INT0 to INT3 pins
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B5 interrupt requests
UART0 to UART4 transmit and receive interrupt requests
A/D conversion interrupt request
Intelligent I/O interrupt request
CAN interrupt request
Software trigger
Channel Priority
DMA0 > DMA1 > DMA2 > DMA3 (DMA0 has highest priority)
Transfer Unit
8 bits, 16 bits
Destination Address
Forward/fixed (forward and fixed directions cannot be specified when
specifying source and destination addresses simultaneously)
Transfer Mode Single Transfer Transfer is completed when the DCTi register (i = 0 to 3) is set to "000016"
Repeat Transfer When the DCTi register is set to "000016", the value of the DRCi register
is reloaded into the DCTi register and the DMA transfer is continued
DMA Interrupt Request Generation Timing When the DCTi register changes "000116" to "000016"
DMA Startup
Single Transfer DMA starts when a DMA request is generated after the DCTi register is
set to "000116" or more and the MDi1 to MD0 bits in the DMDj register (j
= 0 to 1) are set to "012" (single transfer)
Repeat Transfer DMA starts when a DMA request is generated after the DCTi register is
set to "000116" or more and the MDi1 to MDi0 bits are set to "112" (repeat transfer)
DMA Stop
Single Transfer DMA stops when the MDi1 to MDi0 bits are set to "002" (DMA disabled)
or when the DCTi register is set to "000016" (0 DMA transfer) by DMA
transfer or write
Repeat Transfer DMA stops when the MDi1 to MDi0 bits are set to "002" or when the
DCTi register is set to "000016" and the DRCi register set to "000016"
Reload Timing to the DCTi
When the DCTi register is set to "000016" from "000116" in repeat transor DMAi Register
fer mode
DMA Transfer Cycles
Minimum 3 cycles between SFR and internal RAM
NOTES:
1. The IR bit in the interrupt control register does not change when a DMA request is acknowledged.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 115 of 488
12. DMAC
M32C/83 Group (M32C/83, M32C/83T)
DMAi Request Factor Select Register (i=0 to 3)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
DM0SL to DM3SL 037816, 037916, 037A16, 037B16
Bit
Symbol
Bit Name
After Reset
0X00 00002
Function
DSEL0
RW
DSEL1
RW
DSEL2
DMA Request Cause
Select Bit(1)
See Table 12.2 about DMiSL
register (i = 0 to 3) function
RW
DSEL3
RW
DSEL4
RW
DSR
Software DMA
Request Bit(2)
When a software trigger is selected, a DMA
request is generated by setting this bit to "1"
(When read, its content is always "0")
(b6)
Nothing is assigned. When write, set "0".
When read, its content is indeterminate.
DRQ
DMA Request Bit(2, 3)
0 : Not requested
1 : Requested
NOTES:
1. Change the DSEL4 to DSEL0 bit settings while the MDi1 to MDi0 bits in the DMA0 or DMD1
register are set to "002" (DMA disabled). Also, set the DRQ bit to "1" simultaneously when the
DSEL4 to DSEL0 bit settings are changed.
e.g., MOV.B #083h, DMiSL ; Set timer A0
2. When the DSR bit is set to "1", set the DRQ bit to "1" simultaneously.
e.g., OR.B #0A0h, DMiSL
3. Do not set the DRQ bit to "0".
Figure 12.2 DM0SL to DM3SL Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
RW
Page 116 of 488
RW
RW
12. DMAC
M32C/83 Group (M32C/83, M32C/83T)
Table 12.2 DMiSL Register (i = 0 to 3) Function
Setting Value
DMA Request Cause
b4 b3 b2 b1 b0
DMA1
DMA0
DMA2
DMA3
Software Trigger
0 0 0 0 0
0 0 0 0 1
Falling edge of INT0 Falling edge of INT1 Falling edge of INT2
Falling edge of INT3(1)
(Note 2)
0 0 0 1 0
Both edges of INT0
Both edges of INT3(1)
(Note 2)
Both edges of INT1
Both edges of INT2
0 0 0 1 1
Timer A0 Interrupt Request
0 0 1 0 0
Timer A1 Interrupt Request
0 0 1 0 1
Timer A2 Interrupt Request
0 0 1 1 0
Timer A3 Interrupt Request
0 0 1 1 1
Timer A4 Interrupt Request
0 1 0 0 0
Timer B0 Interrupt Request
0 1 0 0 1
Timer B1 Interrupt Request
0 1 0 1 0
Timer B2 Interrupt Request
0 1 0 1 1
Timer B3 Interrupt Request
0 1 1 0 0
Timer B4 Interrupt Request
0 1 1 0 1
Timer B5 Interrupt Request
0 1 1 1 0
UART0 Transmit Interrupt Request
0 1 1 1 1
UART0 Receive or ACK Interrupt Request(3)
1 0 0 0 0
UART1 Transmit Interrupt Request
1 0 0 0 1
UART1 Receive or ACK Interrupt Request(3)
1 0 0 1 0
UART2 Transmit Interrupt Request
1 0 0 1 1
UART2 Receive or ACK Interrupt Request(3)
1 0 1 0 0
UART3 Transmit Interrupt Request
1 0 1 0 1
UART3 Receive or ACK Interrupt Request(3)
1 0 1 1 0
UART4 Transmit Interrupt Request
1 0 1 1 1
UART4 Receive or ACK Interrupt Request(3)
1 1 0 0 0
A/D0 Interrupt Request A/D1 Interrupt Request A/D0 Interrupt request A/D1 Interrupt Request
1 1 0 0 1
Intelligent I/O
Interrupt 0 Request
Intelligent I/O
Interrupt 7 Request
Intelligent I/O
Interrupt 2 Request
Intelligent I/O
Interrupt 9 Request(4)
1 1 0 1 0
Intelligent I/O
Interrupt 1 Request
Intelligent I/O
Interrupt 8 Request
Intelligent I/O
Interrupt 3 Request
Intelligent I/O
Interrupt 10 Request(5)
1 1 0 1 1
1 1 1 0 0
Intelligent I/O
Intelligent I/O
Intelligent I/O
Intelligent I/O
Interrupt 2 Request
Interrupt 9 Request(4)
Interrupt 4 Request
Interrupt 11 Request(6)
Intelligent I/O
Intelligent I/O
Intelligent I/O
Intelligent I/O
Interrupt 3 Request
Interrupt 10 Request(5)
Interrupt 5 Request
Interrupt 0 Request
1 1 1 0 1
Intelligent I/O
Interrupt 4 Request
Intelligent I/O
Interrupt 11 Request(6)
Intelligent I/O
Interrupt 6 Request
Intelligent I/O
Interrupt 1 Request
1 1 1 1 0
Intelligent I/O
Interrupt 5 Request
Intelligent I/O
Interrupt 0 Request
Intelligent I/O
Interrupt 7 Request
Intelligent I/O
Interrupt 2 Request
1 1 1 1 1
Intelligent I/O
Intelligent I/O
Intelligent I/O
Intelligent I/O
Interrupt 6 Request
Interrupt 1 Request
Interrupt 8 Request
Interrupt 3 Request
NOTES:
1. If the INT3 pin is used as data bus in the memory expansion mode or microprocessor mode, a DMA3 interrupt
request cannot be generated by an input signal to the INT3 pin.
2. The falling edge and both edges of input signal into the INTj pin (j = 0 to 3) cause a DMA request. The INT interrupt
(the POL bit in the INTjlC register, the LVS bit, the IFSR register) is not affected and vice versa.
3. The UkSMR register and UkSMR2 register (k = 0 to 4) switch the UARTj receive to ACK or ACK to UARTk receive.
4. The same setting is used to generate an intelligent I/O interrupt 9 request and a CAN interrupt 0 request.
5. The same setting is used to generate an intelligent I/O interrupt 10 request and a CAN interrupt 1 request.
6. The same setting is used to generate an intelligent I/O interrupt 11 request and a CAN interrupt 2 request.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 117 of 488
12. DMAC
M32C/83 Group (M32C/83, M32C/83T)
DMA Mode Register 0(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
DMD0
Bit
Symbol
Address
CPU Internal Register
Bit Name
After Reset
0016
Function
RW
b1 b0
MD00
Channel 0 Transfer
Mode Select Bit
MD01
0 0 : DMA disabled
0 1 : Single transfer
1 0 : Do not set to this value
1 1 : Repeat transfer
RW
RW
BW0
Channel 0 Transfer
Unit Select Bit
0 : 8 bits
1 : 16 bits
RW0
Channel 0 Transfer
Direction Select Bit
0 : Fixed address to memory (forward direction)
RW
1 : Memory (forward direction) to fixed address
Channel 1 Transfer
Mode Select Bit
0 0 : DMA disabled
0 1 : Single transfer
1 0 : Do not set to this value
1 1 : Repeat transfer
RW
b5 b4
MD10
MD11
RW
RW
BW1
Channel 1 Transfer
Unit Select Bit
0 : 8 bits
1 : 16 bits
RW1
Channel 1 Transfer
Direction Select Bit
0 : Fixed address to memory (forward direction)
RW
1 : Memory (forward direction) to fixed address
RW
NOTES:
1. Use the LDC instruction to set the DMD0 register.
DMA Mode Register 1(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
DMD1
Bit
Symbol
Address
CPU Internal Register
Bit Name
After Reset
0016
Function
RW
b1 b0
MD20
Channel 2 Transfer
Mode Select Bit
MD21
RW
RW
BW2
Channel 2 Transfer
Unit Select Bit
0 : 8 bits
1 : 16 bits
RW2
Channel 2 Transfer
Direction Select Bit
0 : Fixed address to memory (forward direction)
RW
1 : Memory (forward direction) to fixed address
Channel 3 Transfer
Mode Select Bit
0 0 : DMA disabled
0 1 : Single transfer
1 0 : Do not set to this value
1 1 : Repeat transfer
b5 b4
MD30
MD31
RW
RW
RW
BW3
Channel 3 Transfer
Unit Select Bit
0 : 8 bits
1 : 16 bits
RW3
Channel 3 Transfer
Direction Select Bit
0 : Fixed address to memory (forward direction)
RW
1 : Memory (forward direction) to fixed address
NOTES:
1. Use the LDC instruction to set the DMD1 register.
Figure 12.3 DMD0 Register, DMD1 Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
0 0 : DMA disabled
0 1 : Single transfer
1 0 : Do not set to this value
1 1 : Repeat transfer
Page 118 of 488
RW
12. DMAC
M32C/83 Group (M32C/83, M32C/83T)
DMAi Transfer Count Register (i=0 to 3)
b15
b8 b7
b0
Symbol
DCT0(2)
DCT1(2)
DCT2(bank1;R0)(3)
DCT3(bank1;R1)(4)
Address
(CPU Internal Register)
(CPU Internal Register)
(CPU Internal Register)
(CPU Internal Register)
Function
Set the number of transfers
After Reset
XXXX16
XXXX16
000016
000016
Setting Range
RW
000016 to FFFF16(1)
RW
NOTES:
1. When the DCTi register to "000016", no data transfer occurs regardless of a DMA request.
2. Use the LDC instruction to set the DCT0 and DCT1 registers.
3. To set the DCT2 register, set the B flag in the FLG register to "1" (register bank 1) and set R0
register. Use the MOV instruction to set the R0 register.
4. To set the DCT3 register, set the B flag to "1" and set R1 register. Use the MOV instruction to
set the R1 register.
DMAi Transfer Count Reload Register (i=0 to 3)
b15
b8 b7
b0
Symbol
DRC0(1)
DRC1(1)
DRC2(bank1;R2)(2)
DRC3(bank1;R3)(3)
Address
(CPU Internal Register)
(CPU Internal Register)
(CPU Internal Register)
(CPU Internal Register)
Function
Set the number of transfers
After Reset
XXXX16
XXXX16
000016
000016
Setting Range
RW
000016 to FFFF16
RW
NOTES:
1. Use the LDC instruction to set the DRC0 and DRC1 registers.
2. To set the DRC2 register, set the B flag in the FLG register to "1" (register bank 1) and set R2
register. Use the MOV instruction to set the R2 register.
3. To set the DRC3 register, set the B flag to "1" and set R3 register. Use the MOV instruction to set the
R3 register.
Figure 12.4 DCT0 to DCT3 Registers and DRC0 to DRC3 Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 119 of 488
12. DMAC
M32C/83 Group (M32C/83, M32C/83T)
DMAi Memory Address Register (i=0 to 3)
b23
b16 b15
b8 b7
b0
Symbol
DMA0(2)
DMA1(2)
DMA2(bank1;A0)(3)
DMA3(bank1;A1)(4)
Address
(CPU Internal Register)
(CPU Internal Register)
(CPU Internal Register)
(CPU Internal Register)
Function
Set a source memory address or destination
memory address(1)
After Reset
XXXXXX16
XXXXXX16
00000016
00000016
Setting Range
RW
00000016 to FFFFFF16
(16-Mbyte space)
RW
NOTES:
1. When the RWk bit (k=0 to 3) in the DMDj register (j=0, 1)is set to "0" (fixed address to memory), a
destination address is selected. When the RWk bit is set to "1" (memory to fixed address), a source
address is selected.
2. Use the LDC instruction to set the DMA0 and DMA1 registers.
3. To set the DMA2 register, set the B flag in the FLG register to "1" (register bank 1) and set A0
register. Use the MOV instruction to set the A0 register.
4. To set the DMA3 register, set the B flag to "1" and set A1 register. Use the MOV instruction to set the
1 register.
DMAi SFR Address Register (i=0 to 3)
b23
b16 b15
b8 b7
b0
Symbol
DSA0(2)
DSA1(2)
DSA2(bank1;SB)(3)
DSA3(bank1;FB)(4)
Address
(CPU Internal Register)
(CPU Internal Register)
(CPU Internal Register)
(CPU Internal Register)
Function
After Reset
XXXXXX16
XXXXXX16
00000016
00000016
Setting Range
Set a source fixed address or destination fixed
address(1)
00000016 to FFFFFF16
(16-Mbyte space)
RW
RW
NOTES:
1. When the RWk bit (k=0 to 3) in the DMDj register (j=0, 1) is set to "0" (fixed address to memory), a
source address is selected. When the RWk bit is set to "1" (memory to fixed address), a destination
address is selected.
2. Use the LDC instruction to set the DSA0 and DSA1 registers.
3. To set the DSA2 register, set the B flag in the FLG register to "1" (register bank 1) and the set the SB
register. Use the LDC instruction to set the SB register.
4. To set the DSA3 register, set the B flag to "1" and set the FB register. Use the LDC instruction to set
the FB register.
DMAi Memory Address Reload Register(1) (i=0 to 3)
b23
b16 b15
b8 b7
b0
Symbol
DRA0
DRA1
DRA2(SVP)(2)
DRA3(VCT)(3)
Address
(CPU Internal Register)
(CPU Internal Register)
(CPU Internal Register)
(CPU Internal Register)
Function
Set a source memory address or destination
memory address
After Reset
XXXXXX16
XXXXXX16
XXXXXX16
XXXXXX16
Setting Range
00000016 to FFFFFF16
(16-Mbyte space)
RW
RW
NOTES:
1. Use the LDC instruction to set the these registers.
2. To set the DRA2 register, set the SVP register.
3. To set the DRA3 register, set the VCT register.
Figure 12.5 DMA0 to DMA3 Registers, DSA0 to DSA3 Registers and DRA0 to DRA3 Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 120 of 488
12. DMAC
M32C/83 Group (M32C/83, M32C/83T)
12.1 Transfer Cycles
Transfer cycle contains a bus cycle to read data from a memory or the SFR area (source read) and a bus
cycle to write data to a memory space or the SFR area (destination write). The number of read and write
bus cycles depends on source and destination addresses. In memory expansion mode and microprocessor
mode, the number of read and write bus cycles also depends on the DS register. Software wait state
________
insertion and the RDY signal make a bus cycle longer.
12.1.1 Effect of Source and Destination Addresses
When a 16-bit data is transferred with a 16-bit data bus, and the source address starts with an odd
address, source read cycle has one more bus cycle compared to a source address starting with an even
address.
When a 16-bit data is transferred with a 16-bit data bus and the destination address starts with an odd
address, destination write cycle has one more bus cycle compared to a destination address starting with
an even address.
12.1.2 Effect of the DS Register
In an external space in memory expansion or microprocessor mode, transfer cycle varies depending on
the data bus used at the source and destination addresses. See Figure 7.1 for details about the DS
register.
(1) When an 8-bit data bus (the DSi bit in the DS register is set to "0" (i=0 to 3)), accessing both source
address and destination address, is used to transfer a 16-bit data, 8-bit data is transferred twice.
Therefore, two bus cycles are required to read the data and another two bus cycles to write the data.
(2) When an 8-bit data bus (the DSi bit in the DS register is set to "0" (i=0 to 3)), accessing source
address, and a 16-bit data bus, accessing destination address, are used to transfer a 16-bit data, 8bit data is read twice but is written once as 16-bit data. Therefore, two bus cycles are required for
reading and one bus cycle is for writing.
(3) When a 16-bit data bus, accessing source address, and an 8-bit data bus, accessing destination
address, are used to transfer a 16-bit data, 16-bit data is read once and 8-bit data is written twice.
Therefore, one bus cycle is required for reading and two bus cycles is for writing.
12.1.3 Effect of Software Wait State
When the SFR area or memory space with software wait states is accessed, the number of cycles is
incremented by software wait states.
Figure 12.6 shows an example of a transfer cycle for the source-read bus cycle. In Figure 12.6, the
number of source-read bus cycles is illustrated under different conditions, provided that the destination
address is an address of an external space with the destination write bus cycle as two BCLK cycles (=one
bus cycle). In effect, the destination-write bus cycle is also affected by each condition and the transfer
cycles change accordingly. To calculate a transfer cycle, apply respective conditions to both destinationwrite bus cycle and source-read bus cycle. As shown in example (2) of Figure 12.6, when an 8-bit data
bus, accessing both source and destination addresses, is used to transfer a 16-bit data, two bus cycles
each are required for the source-read bus cycle and destination-write bus cycle.
,
________
12.1.4 Effect of RDY Signal
________
In memory expansion or microprocessor mode, the RDY signal affects a bus cycle of source address or
_______
destination address is allocated address in an external space. Refer to 7.2.6 RDY Signal for details.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 121 of 488
12. DMAC
M32C/83 Group (M32C/83, M32C/83T)
(1) When 8-bit data is transferred
or when 16-bit data is transferred from an even source address by a 16-bit data bus
BCLK
Address
Bus
CPU Use
Source
Destination
CPU Use
RD Signal
WR Signal
Data
bus
CPU Use
Destination
Source
CPU Use
(2) When 16-bit data is transferred from an odd source address
or when 16-bit data is transferred from source by an 8-bit data bus
BCLK
CPU Clock
Address
Bus
CPU Use
Source
Source + 1
CPU Use
Destination
RD Signal
WR Signal
Data
Bus
CPU Use
Source
Source + 1
CPU Use
Destination
(3) When one wait state is inserted into the source-read bus cycle under the conditions in (1)
BCLK
Address
Bus
CPU Use
Source
Destination
CPU Use
RD Signal
WR Signal
Data
Bus
CPU Use
Source
CPU Use
Destination
(4) When one wait state is inserted into the source-read bus cycle under the conditions in (2)
BCLK
Address
Bus
CPU Use
Source
Source + 1
Destination
CPU Use
RD Signal
WR Signal
Data
Bus
CPU Use
Source
Source + 1
Destination
CPU Use
NOTES:
1. The above applies when the destination-write bus cycle is 2 BCLK cycles (1 bus cycle).
However, if the destination-write bus cycle is placed under these conditions, it will change to
the same timing as the source-read bus cycle illustrated above.
Figure 12.6 Transfer Cycle Examples with the Source-Read Bus Cycle
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 122 of 488
12. DMAC
M32C/83 Group (M32C/83, M32C/83T)
12.2 DMAC Transfer Cycles
The number of DMAC transfer cycle can be calculated as follows.
Any combination of even or odd transfer read and write addresses are possible. Table 12.3 lists the number
of DMAC transfer cycles. Table 12.4 lists coefficient j, k.
Transfer cycles per transfer = Number of read cycle x j + Number of write cycle x k
Table 12.3 DMAC Transfer Cycles
Single-Chip Mode
Transfer Unit
Bus Width Access Address
16-bit
8-bit transfers
(BWi bit in the DMDp
register = 0)
Even
Odd
Even
Odd
Even
Odd
Even
Odd
8-bit
16-bit
16-bit transfers
(BWi bit = 1)
8-bit
Read
Cycle
1
1
—
—
1
2
—
—
Write
Cycle
1
1
—
—
1
2
—
—
Memory Expansion Mode
Microprocessor Mode
Read
Write
Cycle
Cycle
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
i= 0 to 3, p = 0 to 1
Table 12.4 Coefficient j, k
Internal Space
External Space
Internal ROM or Internal ROM or
Internal RAM
Internal RAM with
with no wait state a wait state
SFR
Area
Separate
Separate Separate
Separate Multiplexed Multiplexed
Bus with no Bus with 1 Bus with 2 Bus with 3 Bus with 2 Bus with 3
wait state
wait state wait states wait states wait states wait states
j=1
k=1
j=2
k=2
j=1
k=2
j=2
k=2
j=2
k=2
j=3
k=3
j=4
k=4
j=3
k=3
j=4
k=4
12.3 Channel Priority and DMA Transfer Timing
When multiple DMA requests are generated in the same sampling period, between the falling edge of the
CPU clock and the next falling edge, the DRQ bit in the DMiSL register (i = 0 to 3) is set to "1" (requested)
simultaneously. Channel priority in this case is : DMA0 > DMA1 > DMA2 > DMA3.
Figure 12.7 shows an example of the DMA transfer by external factors.
In Figure 12.7, the DMA0 request having the highest priority is received first to start a transfer when a DMA0
request and DMA1 request are generated simultaneously. After one DMA0 transfer is completed, the bus
privilege is returned to the CPU. When the CPU has completed one bus access, the DMA1 transfer starts.
After one DMA1 transfer is completed, the privilege is again returned to the CPU.
In addition, DMA requests cannot be counted up since each channel has one DRQ bit. Therefore, when
DMA requests, as DMA1 in Figure 12.7, occur more than once before receiving bus privilege, the DRQ bit
is set to "0" as soon as privilege is acquired. The bus privilege is returned to the CPU when one transfer is
completed.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 123 of 488
12. DMAC
M32C/83 Group (M32C/83, M32C/83T)
When DMA transfer request signals are applied to INT0 and INT1 simultaneously
and a DMA transfer with minimum cycle occurs.
BCLK
AAA
AAA
DMA0
DMA1
CPU
INT0
AAAAAAAA
AA
A
AA
A
DRQ Bit
in DMA0
Register
INT1
DRQ Bit
in DMA1
Register
Figure 12.7 DMA Transfer by External Factors
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 124 of 488
AAA
AAA
AAA AAA
AA
AA
Bus
priviledge
acquired
M32C/83 Group (M32C/83, M32C/83T)
13. DMACII
13. DMAC II
The DMAC II performs memory-to-memory transfer, immediate data transfer and calculation transfer, which
transfers the sum of two data added by an interrupt request from any peripheral functions.
Table 13.1 lists specifications of the DMAC II.
Table 13.1 DMAC II Specifications
Item
DMAC II Request Factor
Specification
Interrupt requests generated by all peripheral functions when the ILVL2 to
ILVL0 bits are set to "1112"
Transfer Data
• Data in memory is transferred to memory (memory-to-memory transfer)
• Immediate data is transferred to memory (immediate data transfer)
• Data in memory (or immediate data) + data in memory are transferred to
memory (calculation transfer)
Transfer Block
8 bits or 16 bits
Transfer Space
64-Kbyte space in addresses 0000016 to 0FFFF16(1, 2)
Transfer Direction
Fixed or forward address
Selected separately for each source address and destination address
Transfer Mode
Single transfer, burst transfer
Chained Transfer Function Parameters (transfer count, transfer address and other information) are
switched when transfer counter reaches zero
End-of-Transfer Interrupt
Interrupt occurs when a transfer counter reaches zero
Multiple Transfer Function Multiple data can be transferred by a generated request for one DMA II transfer
NOTES:
1. When transferring a 16-bit data to destination address 0FFFF16, it is transferred to 0FFFF16 and
1000016. The same transfer occurs when the source address is 0FFFF16.
2. The actual space where transfer can occur is limited due to internal RAM capacity.
13.1 DMAC II Settings
DMAC II can be made available by setting up the following registers and tables.
• RLVL register
• DMAC II Index
• Interrupt control register of the peripheral function causing a DMAC II request
• The relocatable vector table of the peripheral function causing a DMAC II request
• IRLT bit in the IIOiIE register (i = 0 to 11) if using the intelligent I/O or CAN interrupt
Refer to 10. Interrupts for details on the IIOiIE register
13.1.1 RLVL Register
When the DMAII bit is set to "1" (DMAC II transfer) and the FSIT bit to "0" (normal interrupt), the DMAC II
is activated by an interrupt request from any peripheral function with the ILVL2 to ILVL0 bits in the interrupt control register set to "1112" (level 7).
Figure 13.1 shows the RLVL register.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 125 of 488
13. DMACII
M32C/83 Group (M32C/83, M32C/83T)
Exit Priority Register
b7
b6
b5
b4
b3
b2
b1
Symbol
RLVL
b0
Bit
Symbol
Address
009F16
Bit Name
Function
b2 b1 b0
RLVL0
RLVL1
After Reset
XXXX 00002
Stop/Wait Mode Exit
Minimum Interrupt Priority
Level Control Bit(1)
RLVL2
0 0 0 : Level 0
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0: Interrupt priority level 7 is used
for normal interrupt
1: Interrupt priority level 7 is used
for high-speed interrupt
FSIT
High-Speed Interrupt
Set Bit(2)
(b4)
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
DMA II
DMAC II Select
Bit(4)
0: Interrupt priority level 7 is used
for interrupt
1: Interrupt priority level 7 is used
for DMAC II transfer(3)
RW
RW
RW
RW
RW
RW
Nothing is assigned. When write, set to "0".
(b7 - b6) When read, its content is indeterminate.
NOTES:
1. The microcomputer exits stop or wait mode when the requested interrupt priority level is higher than
the level set in the RLVL2 to RLVL0 bits. Set the RLVL2 to RLVL0 bits to the same value as IPL in
the FLG register.
2. When the FSIT bit is set to "1", interrupt priority level 7 becomes the high-speed interrupt. In this
case, set only one interrupt to interrupt priority level 7 and the DMA II bit to "0".
3. Set the ILVL2 to ILVL0 bits in the interrupt control register after setting the DMAII bit to "1". Do not
change the DMAII bit setting to "0" after setting the DMAII bit to "1". Set the FSIT bit to "0" when the
DMAII bit to "1".
4. After reset, the DMA II bit is indeterminate. When using an interrupt, set the interrupt control register
after setting the DMA II bit to "0".
Figure 13.1 RLVL Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 126 of 488
13. DMACII
M32C/83 Group (M32C/83, M32C/83T)
13.1.2 DMAC II Index
The DMAC II index is a data table which comprises 8 to 18 bytes (maximum 32 bytes when the multiple
transfer function is selected). The DMAC II index stores parameters for transfer mode, transfer counter,
source address (or immediate data), operation address as an address to be calculated, destination address, chained transfer address, and end-of-transfer interrupt address.
This DMAC II index must be located on the RAM area.
Figure 13.2 shows a configuration of the DMAC II index. Table 13.2 lists a configuration of the DMAC II
index in transfer mode.
Memory-to-Memory Transfer, Immediate Transfer,
Calculation Transfer
Multiple Transfer
16 bits
DMAC II Index
Starting Address (BASE) Transfer Mode
16 bits
(MOD)
BASE
Transfer Mode
(MOD)
(COUNT)
BASE + 2
Transfer Counter
(COUNT)
Transfer Source Address (or immediate data) (SADR)
BASE + 4
Transfer Source Address
(SADR1)
Operation Address(1)
(OADR)
BASE + 6
Transfer Destination Address
(DADR1)
BASE + 8
Transfer Destination Address
(DADR)
BASE + 8
Transfer Source Address
BASE + 10
Chained Transfer Address(2)
(CADR0)
BASE + 10 Transfer Destination Address
BASE + 12
Chained Transfer Address(2)
(CADR1)
BASE + 14
End-of-Transfer Interrupt Address(3)
(IADR0)
BASE + 28 Transfer Source Address
(SADR7)
BASE + 16
End-of-Transfer Interrupt Address(3)
(IADR1)
BASE + 30 Transfer Destination Address
(DADR7)
BASE + 2
Transfer Counter
BASE + 4
BASE + 6
(SADR2)
(DADR2)
NOTES:
1. This data is not required when not using the calculation transfer function.
2. This data is not required when not using the chained transfer function.
3. This data is not required when not using the end-of-transfer interrupt.
The DMAC II index must be located on the RAM. Necessary data is set front-aligned. For example, if not using a calculation
transfer function, set destination address to BASE+6. (See Table 13.2)
Starting address of the DMAC II index must be set in the interrupt vector for the peripheral function interrupt causing a DMAC II request.
Figure 13.2 DMAC II Index
The followings are details of the DMAC II index. Set these parameters in the specified order listed in
Table 13.2, according to DMAC II transfer mode.
• Transfer mode (MOD)
Two-byte data is required to set transfer mode. Figure 13.3 shows a configuration for transfer mode.
• Transfer counter (COUNT)
Two-byte data is required to set the number of transfer.
• Transfer source address (SADR)
Two-byte data is required to set the source memory address or immediate data.
• Operation address (OADR)
Two-byte data is required to set a memory address to be calculated. Set this data only when using
the calculation transfer function.
• Transfer destination address (DADR)
Two-byte data is required to set the destination memory address.
• Chained transfer address (CADR)
Four-byte data is required to set the starting address of the DMAC II index for the next transfer. Set
this data only when using the chained transfer function.
• End-of-transfer interrupt address (IADR)
Four-byte data is required to set a jump address for end-of-transfer interrupt processing. Set this
data only when using the end-of-transfer interrupt.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 127 of 488
13. DMACII
M32C/83 Group (M32C/83, M32C/83T)
Table 13.2 DMAC II Index Configuration in Transfer Mode
Memory-to-Memory Transfer
/Immediate Data Transfer
Chained Transfer
Not Used
Used
Not Used
Used
Not Used
Used
Not Used
Used
Not Available
Not Used
Used
Used
Not Used
Not Used
Used
Used
Not Available
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
COUNT
COUNT
COUNT
COUNT
COUNT
COUNT
COUNT
COUNT
COUNT
SADR
SADR
SADR
SADR
SADR
SADR
SADR
SADR
SADR1
DADR
DADR
DADR
DADR
OADR
OADR
OADR
OADR
DADR1
CADR0
IADR0
CADR0
DADR
DADR
DADR
DADR
CADR1
IADR1
CADR1
10 bytes
CADR0
IADR0
CADR0
CADR1
IADR1
CADR1
SADRi
IADR0
DADRi
End-of-Transfer Not Used
Interrupt
DMAC II
Index
Multiple Transfer
Calculation Transfer
8 bytes
12 bytes
12 bytes
IADR0
IADR1
14 bytes
14 bytes
IADR1
16 bytes
18 bytes
i=1 to 7
Max 32 bytes
(when i=7)
Transfer Mode (MOD)(1)
b15
b8 b7
b0
Bit
Symbol
Bit Name
Function
(MULT=0)
SIZE
Transfer Unit
Select Bit
0: 8 bits
1: 16 bits
IMM
Transfer Data
Select Bit
0: Immediate data
1: Memory
Function
(MULT=1)
RW
RW
Set to "1"
RW
UPDS
Transfer Source
0: Fixed address
Direction Select Bit 1: Forward address
RW
UPDD
Transfer Destination 0: Fixed address
Direction Select Bit 1: Forward address
RW
OPER/ Calculation Transfer 0: Not used
CNT0(2) Function Select Bit 1: Used
BRST/ Burst Transfer
CNT1(2) Select Bit
0: Single transfer
1: Burst transfer
INTE/ End-of-Transfer
CNT2(2) Interrupt Select Bit
0: Interrupt not used
1: Use interrupt
CHAIN
Chained Transfer
Select Bit
b6 b5 b4
0 0 0: Do not set
to this value
0 0 1: Once
0 1 0: Twice
:
:
1 1 0: 6 times
1 1 1: 7 times
0: Chained transfer not used
Set to "0"
1: Use chained transfer
RW
RW
RW
RW
Nothing is assigned. When write, set to "0".
(b14 - b8) When read, its content is indeterminate.
MULT
Multiple Transfer
Select Bit
0: Multiple
transfer not used
1: Use multiple
transfer
RW
NOTES:
1. MOD must be located on the RAM.
2. When the MULT bit is set to "0" (no multiple transfer), bits 4 to 6 becomes the OPER, BRST, INTE
bits. When the MULT bit is set to "1" (multiple transfer), bits 4 to 6 becomes the CNT0 to CNT2 bits.
Figure 13.3 MOD
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 128 of 488
M32C/83 Group (M32C/83, M32C/83T)
13. DMACII
13.1.3 Interrupt Control Register for the Peripheral Function
For the peripheral function interrupt activating a DMAC II request, set the ILVL2 to ILVL0 bits to "1112"
(level 7).
13.1.4 Relocatable Vector Table for the Peripheral Function
Set the starting address of the DMAC II index in the interrupt vector for the peripheral function interrupt
activating a DMAC II request.
When using the chained transfer, the relocatable vector table must be located in the RAM.
13.1.5 IRLT Bit in the IIOiIE Register (i=0 to 11)
When the intelligent I/O interrupt or CAN interrupt is used to activate DMAC II, set the IRLT bit in the IIOiIE
register of the interrupt to "0".
13.2 DMAC II Performance
The DMAC II function is selected by setting the DMA II bit to "1" (DMAC II transfer). DMAC II request is
activated by all peripheral function interrupts with the ILVL2 to ILVL0 bits set to "1112" (level 7). These
peripheral function interrupt request signals become DMAC II transfer request signals and the peripheral
function interrupt cannot be used.
When an interrupt request is generated by setting the ILVL2 to ILVL0 bits to "1112" (level 7), the DMAC II is
activated regardless of what state the I flag and IPL is in.
13.3 Transfer Data
The DMAC II transfers 8-bit or 16-bit data.
• Memory-to-memory transfer : Data is transferred from a desired memory location in a 64-Kbyte space
(Addresses 0000016 to 0FFFF16) to another desired memory location in the same space.
• Immediate data transfer : Immediate data is transferred to a desired memory location in a 64-Kbyte space.
• Calculation transfer : Two 8-bit or16-bit data are added together and the result is transferred to a desired
memory location in a 64K-byte space.
When a 16-bit data is transferred to the destination address 0FFFF16, it is transferred to 0FFFF16 and
1000016. The same transfer occurs when the source address is 0FFFF16 .
13.3.1 Memory-to-Memory Transfer
Data transfer between any two memory locations can be:
• a transfer from a fixed address to another fixed address
• a transfer from a fixed address to a relocatable address
• a transfer from a relocatable address to a fixed address
• a transfer from a relocatable address to another relocatable address
When a relocatable address is selected, the DMAC II increments address, after a transfer, for the next
transfer. In a 8-bit transfer, the transfer address is incremented by one. In a 16-bit transfer, the transfer
address is incremented by two.
When a source or destination address exceeds address 0FFFF16 as a result of address incrementation,
the source or destination address returns to address 00000016 and continues incrementation. Maintain
source and destination address at address 0FFFF16 or below.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 129 of 488
M32C/83 Group (M32C/83, M32C/83T)
13. DMACII
13.3.2 Immediate Data Transfer
The DMAC II transfers immediate data to a desired memory location. A fixed or relocatable address can
be selected as the destination address. Store the immediate data into SADR. To transfer an 8-bit immediate data, write the data in the low-order byte of SADR (high-order byte is ignored).
13.3.3 Calculation Transfer
After two memory data, or an immediate data and memory data are added together, the calculated result
is transferred to a desired memory location. SADR must have one memory location address to be calculated or immediate data. OADR must have the other memory location address to be calculated. Fixed or
relocatable address can be selected as source and destination addresses when using a memory +
memory calculation transfer. If the transfer source address is relocatable, the operation address also
becomes relocatable. Fixed or relocatable address can be selected as the transfer destination address
when using an immediate data + memory calculation transfer.
13.4 Transfer Modes
In DMAC II, single and burst transfers are available. The BRST bit in MOD selects transfer method, either
the single transfer or burst transfer. COUNT determines how many transfers occur. No transfer occurs
when COUNT is set to "000016". All interrupts are ignored while transfer is in progress.
13.4.1 Single Transfer
For every transfer request factor, the DMAC II transfers one transfer unit of 8-bit or 16-bit data once.
When the source or destination address is relocatable, the DMAC II increments the address, after a
transfer, for the next transfer.
COUNT is decremented every time a transfer occurs. When using the end-of-transfer interrupt, the interrupt is acknowledged when COUNT reaches "0".
13.4.2 Burst Transfer
For every transfer request factor, the DMAC II continuously transfers data the number of times determined by COUNT. The DMAC II decrements COUNT every time a transfer occurs. The burst transfer
ends when COUNT reaches "0". The end-of-transfer interrupt is acknowledged when the burst transfer
ends if using the end-of-transfer interrupt. All interrupts are ignored while the burst transfer is in progress.
13.4.3 Multiple Transfer
The MULT bit in MOD selects the multiple transfer. When using the multiple transfer, select the memoryto-memory transfer. One transfer request factor initiates multiple transfers. The CNT2 to CNT0 bits in
MOD selects the number of transfers from "0012" (once) to "1112" (7 times). Do not set the CNT2 to
CNT0 bits to "0002".
The transfer source and destination addresses for each transfer must be allocated alternately to addresses following MOD and COUNT. When the multiple transfer is selected, the calculation transfer,
burst transfer, end-of-transfer interrupt and chained transfer cannot be used.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 130 of 488
13. DMACII
M32C/83 Group (M32C/83, M32C/83T)
13.4.4 Chained Transfer
The CHAIN bit in MOD selects the chained transfer.
The following process initiates the chained transfer.
(1) Transfer, caused by a transfer request factor, occurs according to the content of the DMAC II index.
The vectors of the request factor indicates the address where the DMAC II index is allocated. For each
request, the BRST bit in MOD selects either single or burst transfer.
(2) When COUNT reaches "0", the contents of CADR1 to CADR0 are written to the vector of the request
factor. When the INTE bit in the MOD is set to "1," the end-of-transfer interrupt is generated simultaneously.
(3) When the next DMAC II transfer request is generated, transfer occurs according to the contents of the
DMAC II index indicated by the vector rewritten in (2).
Figure 13.4 shows the relocatable vector and DMACII index of when the chained transfer is in progress.
For the chained transfer, the relocatable vector table must be located in the RAM.
RAM
INTB
Relocatable vector
Peripheral I/O interrupt vector causing DMAC II request
Default value of DMAC II is BASE(1).
BASE(1)
DMAC II
Index(1)
(CADR1 to
CADR0)
BASE(2)
The above vector is rewritten to BASE(2)
when a transfer is completed.
Starts at BASE(2) when next request conditions
are met.
Transferred according to the DMAC II Index.
BASE(2)
DMAC II
Index(2)
(CADR1 to
CADR0)
BASE(3)
The above vector is rewritten to BASE(3)
when a transfer is completed.
Figure 13.4 Relocatable Vector and DMAC II Index
13.4.5 End-of-Transfer Interrupt
The INTE bit in MOD selects the end-of-transfer interrupt. Set the starting address of the end-of-transfer
interrupt service routine in the IADR1 to IADR0 bits. The end-of-transfer interrupt is generated when
COUNT reaches "0."
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 131 of 488
13. DMACII
M32C/83 Group (M32C/83, M32C/83T)
13.5 Execution Time
DMAC II execution cycle is calculated by the following equations:
Multiple transfers: t = 21 + (11 + b + c) x k cycles
Other than multiple transfers: t = 6 + (26 + a + b + c + d) x m + (4 + e) x n cycles
a: If IMM = 0 (source of transfer is immediate data), a = 0;
if IMM = 1 (source of transfer is memory), a = –1
b: If UPDS = 1 (source transfer address is a relocatable address), b = 0;
if UPDS = 0 (source transfer address is a fixed address), b = 1
c: If UPDD = 1 (destination transfer address is a relocatable address), c = 0;
if UPDD = 0 (destination transfer address is a fixed address), c = 1
d: If OPER = 0 (calculation function is not selected), d = 0;
if OPER = 1 (calculation function is selected) and UPDS = 0 (source of transfer is immediate data or fixed
address memory), d = 7;
if OPER = 1 (calculation function is selected) and UPDS = 1 (source of transfer is relocatable address
memory), d = 8
e: If CHAIN = 0 (chained transfer is not selected), e = 0; if CHAIN = 1 (chained transfer is selected), e = 4
m: BRST = 0 (single transfer), m = 1; BRST = 1 (burst transfer), m = the value set in COUNT
n: If COUNT = 1, n = 0; if COUNT = 2 or more, n = 1
k: Number of transfers set in the CNT2 to CNT0 bits
The equations above are approximations. The number of cycles may change with CPU state, bus wait
state, and DMAC II index allocation.
The first instruction from the end-of-transfer interrupt service routine is executed in the 8th cycle after the
DMAC II transfer is completed.
If the end-of-transfer interrupt (transfer counter = 2) occurs with no chained transfer function
after a memory-to-memory transfer occurs with a relocatable source address, fixed destination address,
single transfer and double transfer:
a=-1
b=0
c=1
d=0
e=0
m=1
First DMAC II transfer
t=6+26x1+4x1=36 cycles
Second DMAC II transfer t=6+26x1+4x0=32 cycles
DMAC II transfer request
Program
DMAC II transfer
(First time)
DMAC II transfer request
Program
36 cycles
Transfer counter = 2
Processing the end-of-transfer
interrupt
DMAC II transfer
(Second time)
32 cycles
7 cycles
Transfer counter = 1
Decrement a transfer counter
Transfer counter = 1
Decrement a transfer counter
Transfer counter = 0
Figure 13.5 Transfer Cycle
When an interrupt request which acts as a DMAC II transfer request factor and another interrupt request
_______
with higher priority (e.g., NMI or watchdog timer) are generated simultaneously, the interrupt with higher
priority takes precedence over the DMAC II transfer. The pending DMAC II transfer starts after the interrupt
sequence has been completed.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 132 of 488
14. Timer
M32C/83 Group (M32C/83, M32C/83T)
14. Timer
The microcomputer has eleven 16-bit timers. Five timers A and six timers B have different functions. Each
timer operates independently. The count source for each timer is the clock for timer operations including
counting and reloading, etc. Figures 14.1 and 14.2 show block diagrams of timer A and timer B configuration.
Clock prescaler
Main clock,
PLL clock or
On-chip
oscillator
clock
f1
CST
fC32
1/32
XCIN
Reset
1/8
f8
1/2n
f2n
Set the CPSR bit
in the CPSRF register to "1"
(Note 1)
f1 f8 f2n fC32
TCK1 to TCK0
00
01
10
11
10
Noise
filter
01
00
TA0IN
00: Timer mode
10: One-shot timer mode
11: PWM mode
TMOD1 to TMOD0
Timer A0 interrupt
Timer A0
01: Event counter mode
11 TA0TGH to TA0TGL
00
01
10
11
TCK1 to TCK0
TMOD1 to TMOD0
10
Noise
filter
TA1IN
00: Timer mode
10: One-shot tiemr mode
11: PWM mode
01
00
Timer A1 interrupt
Timer A1
01: Event counter mode
11 TA1TGH to TA1TGL
00: Timer mode
10: One-shot timer mode
11: PWM mode
TCK1 to TCK0
00
01
10
11
Noise
filter
TA2IN
TMOD1 to TMOD0
10
01
00
Timer A2 interrupt
Timer A2
01: Event counter mode
11 TA2TGH to TA2TGL
TCK1 to TCK0
00
01
10
11
Noise
filter
TA3IN
00: Timer mode
10: One-shot timer mode
11: PWM mode
TMOD1 to TMOD0
10
01
00
Timer A3 interrupt
Timer A3
01: Event counter mode
11 TA3TGH to TA3TGL
00
01
10
11
TA4IN
TCK1 to TCK0
00: Timer mode
10: One-shot timer mode
11: PWM mode
TMOD1 to TMOD0
10
Noise
filter
00
Timer A4 interrupt
Timer A4
01
01: Event counter mode
11 TA4TGH to TA4TGL
Timer B2 overflow
or underflow
CST: Bit in TCSPR register
TCK1 to TCK0, TMOD1 to TMOD0 : Bits in TAiMR register
TAiGH to TAiGL: Bits in ONSF register or TRGSR register (i=1 to 4)
NOTES:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Figure 14.1 Timer A Configuration
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 133 of 488
14. Timer
M32C/83 Group (M32C/83, M32C/83T)
f1
Main clock,
PLL clock or
On-chip clock
CST
1/8
f8
1/2n
f2n
Clock prescaler
Set the CPSR bit in
the CPSRF register to "1"
(Note 1)
f1 f8 f2n fC32
00
01
10
11
Timer B2 overflow or underflow
(to a count source of the timer A)
00: Timer mode
10: Pulse width measurement mode
TMOD1 to TMOD0
Noise
filter
00
01
10
11
0
Timer B0
TCK1
1
01:Event counter mode
TMOD1 to TMOD0
0
TCK1
01:Event counter mode
TCK1 to TCK0
00: Timer mode
10: Pulse width measurement mode
1
TMOD1 to TMOD0
0
01:Event counter mode
TCK1 to TCK0
00: Timer mode
10: Pulse width measurement mode
TMOD1 to TMOD0
Noise
filter
00
01
10
11
00
01
10
11
TB5IN
0
Timer B3
TCK1
TCK1 to TCK0
Timer B3 interrupt
01:Event counter mode
00: Timer mode
10: Pulse width measurement mode
1
Noise
filter
TB4IN
Timer B2 interrupt
Timer B2
1
TB3IN
Timer B1 interrupt
Timer B1
TCK1
00
01
10
11
Timer B0 interrupt
00: Timer mode
10: Pulse width measurement mode
Noise
filter
TB2IN
1
TCK1 to TCK0
Noise
filter
00
01
10
11
Reset
TCK1 to TCK0
TB0IN
TB1IN
fC32
1/32
XCIN
TMOD1 to TMOD0
Timer B4
0
TCK1
TCK1 to TCK0
Timer B4 interrupt
01:Event counter mode
00: Timer mode
10: Pulse width measurement mode
1
Noise
filter
TMOD1 to TMOD0
Timer B5
0
TCK1
Timer B5 interrupt
01:Event counter mode
CST : Bit in TCSPR register
TCK1 to TCK0, TMOD1 to TMOD0 : Bits in TBiMR register (i=0 to 5)
NOTES:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Figure 14.2 Timer B Configuration
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 134 of 488
14. Timer (Timer A)
M32C/83 Group (M32C/83, M32C/83T)
14.1 Timer A
Figure 14.3 shows a block diagram of the timer A. Figures 14.4 to 14.7 show registers associated with the
timer A.
The timer A supports the following four modes. Except in event counter mode, all timers A0 to A4 have the
same function. The TMOD1 to TMOD0 bits in the TAiMR register (i=0 to 4) determine which mode is used.
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts an external pulse or an overflow and underflow of other timers.
• One-shot timer mode: The timer outputs one valid pulse until the counter reaches "000016".
• Pulse width modulation mode: The timer continuously outputs desired pulse widths.
Table 14.1 lists TAiOUT pin settings when used as an output. Table 14.2 lists TAiIN and TAiOUT pin settings
when used as an input.
Select clock
High-Order Bits of Data Bus
Select Count Source
f1
f8
f2n(1)
fC32
00
01
10
11
TCK1 to TCK0 • Timer
:TMOD1 to TMOD0=00, MR2=0
• One-Shot Timer
:TMOD1 to TMOD0=10 TMOD1 to TMOD0,
• Pulse Width Modulation:TMOD1 to TMOD0=11 MR2
• Timer(gate function):TMOD1 to TMOD0=00,
MR2=1
Low-Order Bits of Data Bus
8 loworder
bits
Reload Register
A
A
• Event counter:TMOD1 to TMOD0=01
TAiIN
Polarity
Selector
Counter
Increment / decrement
Always decrement except
in event counter mode
TAiS
00
01
TB2 Overflow(2)
10
TAj Overflow(2)
11
TAk Overflow(2)
Decrement
00
01
11
01
TAiTGH to TAiTGL
TAiUD
TMOD1 to TMOD0
0
1
Pulse Output
MR2
TAiOUT
Toggle Flip Flop
i=0 to 4
j=i-1, except j=4 if i=0
k=i+1, except k=0 if i=4
NOTES:
1. The CNT3 to CNT0 bits in the TCSPR register select
no division (n=0) or divide-by-2n (n=1 to 15).
2. Overflow or underflow
TAi
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Addresses
034716 034616
034916 034816
034B16 034A16
034D16 034C16
034F16 034E16
TCK1 to TCK0, TMOD1 to TMOD0, MR2 to MR1 : Bits in TAiMR register
TAiTGH to TAiTGL: Bits in ONSF register if i=0 or bits in TRGSR register if i=1 to 4
TAiS: Bits in the TABSR register
TAiUD: Bits in the UDF register
Figure 14.3 Timer A Block Diagram
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 135 of 488
8 highorder
bits
TAj
Timer A4
Timer A0
Timer A1
Timer A2
Timer A3
TAk
Timer A1
Timer A2
Timer A3
Timer A4
Timer A0
14. Timer (Timer A)
M32C/83 Group (M32C/83, M32C/83T)
Timer Ai Register (i=0 to 4)(1)
b15
b8 b7
b0
Symbol
TA0 to TA2
TA3, TA4
Address
034716-034616, 034916-034816, 034B16-034A16
After Reset
Indeterminate
034D16-034C16, 034F16-034E16
Indeterminate
Mode
Function
Setting Range
RW
Timer Mode
If setting value is n, count source
is divided by n+1.
000016 to FFFF16 RW
Event Counter
Mode(2)
If setting value is n, count source
is divided by FFFF16 - n+1 when
the counter is incremented
and by n+1 when the counter is
decremented.
000016 to FFFF16 RW
One-Shot Timer
Mode(4)
If setting value is n, count source
is divided by n, then stops.
000016 to FFFF16(3) WO
If count source frequency is fj
Pulse Width
and setting value of the TAi
Modulation Mode(5) register is n,
PWM cycle: (216-1) / fj
(16-Bit PWM)
"H" width of PWM pulse: n / fj
Pulse Width
Modulation Mode(5)
(8-Bit PWM)
If count source frequency is fj,
setting value of high-order bits in
the TAi register is n and setting
value of low-order bits in the TAi
register is m,
PWM cycle: (28-1)x(m+1) / fj
"H" width of PWM pulse: (m+1)n / fj
000016 to FFFE16(3) WO
0016 to FE16(3)
(High-order
address bits)
0016 to FF16(3)
(Low-order
address bits)
WO
fj : f1, f8, f2n, fC32
NOTES:
1. Use 16-bit data for reading and writing.
2. The TAi register counts how many pulses are input externally or how many times another timer
counter overflows and underflows.
3. Use the MOV instruction to set the TAi register.
4. When the TAi register is set to "000016", the counter does not start and the timer Ai interrupt request
is not generated.
5. When the TAi register is set to "000016", the pulse width modulator does not operate and the TAiOUT
pin is held "L". The TAi interrupt request is also not generated. The same situation occurs in 8-bit
pulse width modulator mode if the 8 high-order bits in the TAi register are set to "0016".
Figure 14.4 TA0 to TA4 Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 136 of 488
14. Timer (Timer A)
M32C/83 Group (M32C/83, M32C/83T)
Timer Ai Mode Register (i=0 to 4)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TA0MR0 to TA4MR
Bit
Symbol
Address
035616, 035716, 035816, 035916, 035A16
Bit Name
After Reset
0000 0X002
Function
RW
b1b0
TMOD0
TMOD1
(b2)
Operation Mode
Select Bit
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation
(PWM) mode
RW
RW
Nothing is assigned. When write, set to "0".
MR1
RW
Function varies depending on
operation mode
MR2
MR3
RW
RW
TCK0
Count Source
Select Bit
Function varies depending on
operation mode
TCK1
RW
RW
Count Start Flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TABSR
Bit
Symbol
Address
034016
After Reset
0016
Bit Name
Function
TA0S
Timer A0 Count
Start Flag
0 : Stops counting
1 : Starts counting
RW
TA1S
Timer A1 Count
Start Flag
0 : Stops counting
1 : Starts counting
RW
TA2S
Timer A2 Count
Start Flag
0 : Stops counting
1 : Starts counting
RW
TA3S
Timer A3 Count
Start Flag
0 : Stops counting
1 : Starts counting
RW
TA4S
Timer A4 Count
Start Flag
0 : Stops counting
TB0S
Timer B0 Count
Start Flag
0 : Stops counting
TB1S
Timer B1 Count
Start Flag
0 : Stops counting
TB2S
Timer B2 Count
Start Flag
0 : Stops counting
1 : Starts counting
1 : Starts counting
1 : Starts counting
1 : Starts counting
Figure 14.5 TA0MR to TA4MR Registers and TABSR Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
RW
Page 137 of 488
RW
RW
RW
RW
14. Timer (Timer A)
M32C/83 Group (M32C/83, M32C/83T)
Up/Down Flag(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
UDF
034416
After Reset
0016
Bit
Symbol
Bit Name
TA0UD
Timer A0 Up/Down Flag
0 : Decrement
1 : Increment
(Note 2)
RW
TA1UD
Timer A1 Up/Down Flag
0 : Decrement
1 : Increment
(Note 2)
RW
TA2UD
Timer A2 Up/Down Flag
0 : Decrement
1 : Increment
(Note 2)
RW
TA3UD
Timer A3 Up/Down Flag
0 : Decrement
1 : Increment
(Note 2)
RW
TA4UD
Timer A4 Up/Down Flag
0 : Decrement
1 : Increment
(Note 2)
RW
TA2P
TA3P
Function
RW
0 : Disables two-phase pulse signal
Timer A2 Two-Phase
processing function
Pulse Signal Processing
WO
1 : Enables two-phase pulse signal
Function Select Bit
(Note
3)
processing function
0 : Disables two-phase pulse signal
Timer A3 Two-Phase
processing function
Pulse Signal Processing
WO
1 : Enables two-phase pulse signal
Function Select Bit
(Note 3)
processing function
0 : Disables two-phase pulse signal
Timer A4 Two-Phase
processing function
Pulse Signal Processing
WO
1 : Enables two-phase pulse signal
Function Select Bit
(Note 3)
processing function
TA4P
NOTES:
1. Use the MOV instruction to set the UDF register.
2. This bit is enabled when the MR2 bit in the TAiMR register (i=0 to 4) is set to "0" (the UDF register
causes increment/decrement switching) in event counter mode.
3. Set this bit to "0" when not using the two-phase pulse signal processing function.
One-Shot Start Flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
ONSF
Bit
Symbol
Address
034216
After Reset
0016
Bit Name
RW
Function
TA0OS
Timer A0 One-Shot
Start Flag
0 : In an idle state
1 : Starts the timer
(Note 1) RW
TA1OS
Timer A1 One-Shot
Start Flag
0 : In an idle state
1 : Starts the timer
(Note 1)
RW
TA2OS
Timer A2 One-Shot
Start Flag
0 : In an idle state
1 : Starts the timer
(Note 1)
RW
TA3OS
Timer A3 One-Shot
Start Flag
0 : In an idle state
1 : Starts the timer
(Note 1) RW
TA4OS
Timer A4 One-Shot
Start Flag
0 : In an idle state
1 : Starts the timer
(Note 1)
TAZIE
Z-Phase Input Enable Bit
0 : Disables Z-phase input
1 : Enables Z-phase input
RW
RW
b7 b6
TA0TGL
Timer A0 Event/Trigger
Select Bit
TA0TGH
NOTES:
1. When read, the bit is set to "0".
2. Overflow or underflow.
Figure 14.6 UDF Register and ONSF Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 138 of 488
0 0 : Selects an input to the TA0IN pin RW
0 1 : Selects the TB2 overflows(2)
1 0 : Selects the TA4 overflows(2)
RW
1 1 : Selects the TA1 overflows(2)
14. Timer (Timer A)
M32C/83 Group (M32C/83, M32C/83T)
Trigger Select Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TRGSR
Bit
Symbol
Address
034316
After Reset
0016
Bit Name
Function
RW
b0 b1
TA1TGL
Timer A1 Event/Trigger
Select Bit
TA1TGH
0 0 : Selects an input to the TA1IN pin RW
0 1 : Selects the TB2 overflows(1)
1 0 : Selects the TA0 overflows(1)
RW
1 1 : Selects the TA2 overflows(1)
b3 b2
TA2TGL
Timer A2 Event/Trigger
Select Bit
TA2TGH
0 0 : Selects an input to the TA2IN pin RW
0 1 : Selects the TB2 overflows(1)
1 0 : Selects the TA1 overflows(1)
RW
1 1 : Selects the TA3 overflows(1)
b5 b4
TA3TGL
Timer A3 Event/Trigger
Select Bit
TA3TGH
0 0 : Selects an input to the TA3IN pin RW
0 1 : Selects the TB2 overflows(1)
1 0 : Selects the TA2 overflows(1)
RW
1 1 : Selects the TA4 overflows(1)
b7 b6
TA4TGL
Timer A4 Event/Trigger
Select Bit
TA4TGH
0 0 : Selects an input to the TA4IN pin RW
0 1 : Selects the TB2 overflows(1)
1 0 : Selects the TA3 overflows(1)
RW
1 1 : Selects the TA0 overflows(1)
NOTES:
1. Overflow or underflow.
Count Source Prescaler Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TCSPR
Bit
Symbol
Address
035F16
Bit Name
After Reset (2)
0XXX 00002
Function
RW
RW
CNT0
CNT1
Divide Ratio Select Bit
CNT2
If setting value is n, f2n is the
main clock, PLL clock or on-chip
oscillator clock divided by 2n.
Not divided if n=0.(1)
RW
RW
RW
CNT3
Nothing is assigned. When write, set to "0".
(b6 - b4) When read, its content is indeterminate.
CST
Operation Enable Bit
0 : Stops divider
1 : Starts divider
RW
NOTES:
1. Set the CST bit to "0" before the CNT3 to CNT0 bits are rewritten.
2. The TCSPR register maintains values set before reset, even after software reset or watchdog timer
reset has performed.
Figure 14.7 TRGSR Register and TCSPR Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 139 of 488
14. Timer (Timer A)
M32C/83 Group (M32C/83, M32C/83T)
Table 14.1 Pin Settings for Output from TAiOUT Pin (i=0 to 4)
Pin
Setting
PS1, PS2 Registers
PSL1, PSL2 Registers
PSC Register
P70/TA0OUT(1)
PS1_0= 1
PSL1_0=1
PSC_0= 0
P72/TA1OUT
PS1_2= 1
PSL1_2=1
PSC_2= 0
P74/TA2OUT
PS1_4= 1
PSL1_4=0
PSC_4= 0
P76/TA3OUT
PS1_6= 1
PSL1_6=1
PSC_6= 0
P80/TA4OUT
PS2_0= 1
PSL2_0=0
–
NOTES:
1. P70/TA0OUT is a port for the N-channel open drain output.
Table 14.2 Pin Settings for Input to TAiIN and TAiOUT Pins (i=0 to 4)
Pin
Setting
PS1, PS2 Registers
PD7, PD8 Registers
P70/TA0OUT
PS1_0=0
PD7_0=0
P71/TA0IN
PS1_1=0
PD7_1=0
P72/TA1OUT
PS1_2=0
PD7_2=0
P73/TA1IN
PS1_3=0
PD7_3=0
P74TA2OUT
PS1_4=0
PD7_4=0
P75/TA2IN
PS1_5=0
PD7_5=0
P76TA3OUT
PS1_6=0
PD7_6=0
P77/TA3IN
PS1_7=0
PD7_7=0
P80/TA4OUT
PS2_0=0
PD8_0=0
P81/TA4IN
PS2_1=0
PD8_1=0
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 140 of 488
14. Timer (Timer A)
M32C/83 Group (M32C/83, M32C/83T)
14.1.1 Timer Mode
In timer mode, the timer counts an internally generated count source (see Table 14.3). Figure 14.8 shows
the TAiMR register (i=0 to 4) in timer mode.
Table 14.3 Specifications in Timer Mode
Item
Specification
Count Source
f1, f8, f2n(1), fC32
Counting Operation
• The timer decrements a counter value
When the timer counter underflows, content of the reload register is reloaded into the
count register and counting resumes.
Divide Ratio
1/(n+1)
n: setting value of the TAi register (i=0 to 4)
000016 to FFFF16
Counter Start Condition
The TAiS bit in the TABSR register is set to "1" (starts counting)
Counter Stop Condition
The TAiS bit is set to "0" (stops counting)
Interrupt Request Generation Timing The timer counter underflows
TAiIN Pin Function
Programmable I/O port or gate input
TAiOUT Pin Function
Programmable I/O port or pulse output
Read from Timer
The TAi register indicates counter value
Write to Timer
• When the timer counter stops,
the value written to the TAi register is also written to both reload register and counter
• While counting,
the value written to the TAi register is written to the reload register
(It is transferred to the counter at the next reload timing)
Selectable Function
• Gate function
Input signal to the TAiIN pin determines whether the timer counter starts or stops counting
• Pulse output function
The polarity of the TAiOUT pin is inversed whenever the timer counter underflows
NOTES:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 141 of 488
14. Timer (Timer A)
M32C/83 Group (M32C/83, M32C/83T)
Timer Ai Mode Register (i=0 to 4) (Timer Mode)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TA0MR to TA4MR
0 0
Bit
Symbol
Address
035616, 035716, 035816, 035916, 035A16
Bit Name
Function
TMOD0
RW
RW
Operation Mode
Select Bit
b1 b0
0 0 : Timer mode
TMOD1
(b2)
After Reset
0000 0X002
RW
Nothing is assigned. When write, set to "0".
b4 b3
MR1
Gate Function
Select Bit
MR2
MR3
0 X : Gate function disabled(1)
RW
(TAiIN pin is a programmable I/O pin)
1 0 : Timer counts only while the
TAiIN pin is held "L"
RW
1 1 : Timer counts only while the
TAiIN pin is held "H"
Set to "0" in timer mode
RW
b7 b6
TCK0
Count Source
Select Bit
TCK1
0 0 : f1
0 1 : f8
1 0 : f2n(2)
1 1 : fC32
RW
RW
NOTES:
1. X can be set to either "0" or "1".
2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Figure 14.8 TA0MR to TA4MR Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 142 of 488
14. Timer (Timer A)
M32C/83 Group (M32C/83, M32C/83T)
14.1.2 Event Counter Mode
In event counter mode, the timer counts how many external signals are applied or how many times
another timer overflows and underflows. The timers A2, A3 and A4 can count externally generated twophase signals. Table 14.4 lists specifications in event counter mode (when not handling a two-phase
pulse signal). Table 14.5 lists specifications in event counter mode (when handling a two-phase pulse
signal with the timer A2, A3 and A4). Figure 14.9 shows the TAiMR (i=0 to 4) register in event counter
mode.
Table 14.4 Specifications in Event Counter Mode (when not processing two-phase pulse signal)
Item
Specification
• External signal applied to the TAiIN pin (i = 0 to 4) (valid edge can be selected by
Count Source
program)
• Timer B2 overflow or underflow signal, timer Aj overflow or underflow signal (j=i-1,
except j=4 if i=0) and timer Ak overflow or underflow signal (k=i+1, except k=0 if i=4)
Counting Operation
• External signal and program can determine whether the timer increments or decrements the counter
• When the timer counter underflows or overflows, the content of the reload register is
reloaded into the count register and counting resumes. When the free-running count
function is selected, the timer counter continues running without reloading.
• 1/(FFFF16 - n + 1) for counter increment
Divide Ratio
• 1/(n + 1) for counter decrement
n : setting value of the TAi register 0000 16 to FFFF16
Counter Start Condition
The TAiS bit in the TABSR register is set to "1" (starts counting)
Counter Stop Condition
The TAiS bit is set to "0" (stops counting)
Interrupt Request Generation Timing The timer counter overflows or underflows
TAiIN Pin Function
Programmable I/O port or count source input
TAiOUT Pin Function
Programmable I/O port, pulse output or input selecting a counter increment or decrement
Read from Timer
The TAi register indicates counter value
Write to Timer
• When the timer counter stops,
the value written to the TAi register is also written to both reload register and counter
• While counting,
the value written to the TAi register is written to the reload register
(It is transferred to the counter at the next reload timing)
Selectable Function
• Free-running count function
Content of the reload register is not reloaded even if the timer counter overflows or
underflows
• Pulse output function
The polarity of the TAiOUT pin is inversed whenever the timer counter overflows or
underflows
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 143 of 488
14. Timer (Timer A)
M32C/83 Group (M32C/83, M32C/83T)
Table 14.5 Specifications in Event Counter Mode (when processing two-phase pulse signal on
timer A2, A3 and A4)
Item
Specification
Count Source
Two-phase pulse signal applied to the TAiIN pin, or TAiIN and TAiOUT pin (i = 2 to 4)
Counting Operation
• Two-phase pulse signal determines whether the timer increments or decrements a
counter value
• When the timer counter overflows or underflows, content of the reload register is
reloaded into the count register and counting resumes. With the free-running count
function, the timer counter continues running without reloading.
• 1/ (FFFF16 - n + 1) for counter increment
Divide Ratio
• 1/ (n + 1) for counter decrement
n : setting value of the TAi register
Counter Start Condition
The TAiS bit in the TABSR register is set to "1" (starts counting)
Counter Stop Condition
The TAiS bit is set to "0" (stops counting)
000016 to FFFF16
Interrupt Request Generation Timing The timer counter overflows or underflows
TAiIN Pin Function
Two-phase pulse signal is applied
TAiOUT Pin Function
Two-phase pulse signal is applied
Read from Timer
The TAi register indicates counter value
Write to Timer
• When the timer counter stops,
the value written to the TAi register is also written to both reload register and counter
• While counting,
the value written to the TAi register is written to the reload register
(It is transferred to the counter at the next reload timing)
Selectable Function(1)
• Normal processing operation (the timer A2 and timer A3)
While a high-level ("H") signal is applied to the TAjOUT pin (j = 2 or 3), the timer increments a counter value on the rising edge of the TAjIN pin or decrements a counter
value on the falling edge.
TAjOUT
TAjIN
Increment Increment Increment Decrement Decrement Decrement
• Multiply-by-4 processing operation (the timer A3 and timer A4)
While an "H" signal is applied to the TAkOUT pin (k = 3 or 4) with the rising edge of the
TAkIN pin, the timer counter increments a counter value on the rising and falling edges of
the TAkOUT and TAkIN pins.
While "H" is applied to the TAkOUT pin on the falling edge of the TAkIN pin, the timer
decrements a counter value on the rising and falling edges of the TAkOUT and TAkIN pins.
TAkOUT
TAkIN
Increment on all edges
Decrement on all edges
NOTES:
1. Only timer A3 operation can be selected. The timer A2 is for the normal processing operation. The
timer A4 is for the multiply-by-4 operation.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 144 of 488
14. Timer (Timer A)
M32C/83 Group (M32C/83, M32C/83T)
Timer Ai Mode Register (i=0 to 4) (Event Counter Mode)
b7
b6
b5
b4
0
b3
b2
b1
b0
Symbol
TA0MR to TA4MR
0 1
Address
035616, 035716, 035816, 035916, 035A16
Function
Bit
Symbol
Bit Name
TMOD0
Operation Mode
Select Bit
After Reset
0000 0X0016
Function
(When not using two-phase (When using two-phase
pulse signal processing) pulse signal processing)
RW
b1 b0
0 1 : Event counter mode(1)
TMOD1
(b2)
RW
RW
Nothing is assigned. When write, set to "0".
RW
MR1
Count Polarity
Select Bit(2)
0 : Counts falling edges
of an external signal
Set to "0"
1 : Counts rising edges
of an external signal
RW
MR2
Increment/Decrement 0 : Setting of the UDF
register
Set to "1"
Switching Cause
1 : Input signal to
Select Bit
(3)
TAiOUT pin
RW
MR3
Set to "0" in event counter mode
RW
TCK0
Count Operation
Type Select Bit
RW
TCK1
Two-Phase Pulse
Set to "0"
Signal Processing
Operation Select Bit(4,5)
0 : Reloading
1 : Free running
0 : Normal processing
operation
RW
1 : Multiplied-by-4
processing operation
NOTES:
1. The TAiTGH to TAiTGL bits in the ONSF or TRGSR register determine the count source in the event
counter mode.
2. The MR1 bit is enabled only when counting how many times external signals are applied.
3. The timer decrements a counter value when "L" is applied to the TAiOUT pin and the timer increments
a counter value when "H" is applied to the TAiOUT pin.
4. The TCK1 bit is enabled only in the TA3MR register.
5. For two-phase pulse signal processing, set the TAjP bit in the UDF register (j=2 to 4) to "1" (twophase pulse signal processing function enabled) and the TAiTGH and TAiTGL bits to "002" (input to
the TAjIN pin).
Figure 14.9 TA0MR to TA4MR Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 145 of 488
14. Timer (Timer A)
M32C/83 Group (M32C/83, M32C/83T)
14.1.2.1 Counter Reset by Two-Phase Pulse Signal Processing
The timer counter is reset to "0" by a Z-phase input when processing a two-phase pulse signal.
This function can be used in timer A3 event counter mode, two-phase pulse signal processing, free_______
run type or multiply-by-4 processing. The Z-phase signal is applied to the INT2 pin.
When the TAZIE bit in the ONSF register is set to "1" (Z-phase input enabled), the timer counter can
be reset by a Z-phase input. To reset the timer counter by a Z-phase input, set the TA3 register to
"000016" beforehand.
_______
Z-phase input is enabled when the edge of the signal applied to the INT2 pin is detected. The POL bit
in the INT2IC register can determine edge polarity. The Z-phase must have a pulse width of one timer
A3 count source cycle or more. Figure 14.10 shows two-phase pulses (A-phase and B-phase) and
the Z-phase.
Z-phase input resets the counter in the next count source following Z-phase input. Figure 14.11 shows
the counter reset timing.
Timer A3 interrupt request is generated twice when a timer A3 overflow or underflow, and a counter
_______
reset by INT2 input occur at the same time. Do not use the timer A3 interrupt request when this
function is used.
TA3OUT
(A-phase)
TA3IN
(B-phase)
Count source
INT2 (1)
(Z-phase)
Pulse width of one count source cycle
or more is required
NOTES:
1. When the rising edge of INT2 is selected.
Figure 14.10 Two-phase Pulse (A-phase and B-phase) and Z-phase
TA3OUT
(A-phase)
TA3IN
(B-phase)
Count source
INT2 (1)
(Z-phase)
Counter value
m
m+1
1
Timer counter is reset at this timing
Figure 14.11 Counter Reset Timing
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 146 of 488
2
3
4
5
NOTES:
1. When the rising edge of INT2 is selected.
14. Timer (Timer A)
M32C/83 Group (M32C/83, M32C/83T)
14.1.3 One-shot Timer Mode
In one-shot timer mode, the timer operates only once for each trigger (see Table 14.6). Once a trigger
occurs, the timer starts and continues operating for a desired period. Figure 14.12 shows the TAiMR
register (i=0 to 4) in one-shot timer mode.
Table 14.6 Specifications in One-shot Timer Mode
Item
Specification
Count Source
f1, f8, f2n(1), fC32
Counting Operation
The timer decrements a counter value
• When the timer counter reaches "000016", it stops counting after reloading.
• If a trigger occurs while counting, content of the reload register is reloaded into the
count register and counting resumes.
Divide Ratio
1/n
n : setting value of the TAi register (i=0 to 4) 000016 to FFFF16
Counter Start Condition
The TAiS bit in the TABSR register is set to "1" (starts counting) and following triggers
but the timer counter does not run if n=000016
occur:
• External trigger input
• The timer overflow or underflow signal
• The TAiOS bit in the ONSF register is set to "1" (timer started)
Counter Stop Condition
• After the timer counter has reached "000016" and is reloaded
• When the TAiS bit is set to "0" (timer stopped)
Interrupt Request Generation Timing The timer counter reaches "000016"
TAiIN Pin Function
Programmable I/O port or trigger input
TAiOUT Pin Function
Programmable I/O port or pulse output
Read from Timer
The value in the TAi register is indeterminate when read
Write to Timer
• When the timer counter stops,
the value written to the TAi register is also written to both reload register and counter
• While counting,
the value written to the TAi register is written to the reload register
(It is transferred to the counter at the next reload timing)
NOTES:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 147 of 488
14. Timer (Timer A)
M32C/83 Group (M32C/83, M32C/83T)
Timer Ai Mode Register (i=0 to 4) (One-Shot Timer Mode)
b7
b6
b5
0
b4
b3
b2
b1
b0
1 0
Symbol
Address
TA0MR to TA4MR
035616, 035716, 035816, 035916, 035A16
Bit
Symbol
Bit Name
TMOD0
Operation Mode
Select Bit
After Reset
0000 0X002
Function
b1b0
RW
1 0 : One-shot timer mode
TMOD1
(b2)
RW
RW
Nothing is assigned. When write, set to "0".
MR1
External Trigger Select 0 : Falling edge of input signal to TAiIN pin
RW
Bit(1)
1 : Rising edge of input signal to TAiIN pin
MR2
Trigger Select Bit
MR3
Set to "0" in the one-shot timer mode
0 : The TAiOS bit is enabled
1 : Selected by the TAiTGH and TAiTGL
bits
b7b6
TCK0
Count Source
Select Bit
TCK1
0 0 : f1
0 1 : f8
1 0 : f2n(2)
1 1 : fC32
RW
RW
RW
RW
NOTES:
1. The MR1 bit setting is enabled only when the TAiTGH to TAiTGL bits in the TRGSR register are set
to "002" (input to the TAiIN pin). The MR1 bit can be set to either "0" or "1" when the TAiTGH and
TAiTGL bits are set to "012" (TB2 overflow and underflow), "102" (TAi overflow and underflow) or
"112" (TAi overflow and underflow).
2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Figure 14.12 TA0MR to TA4MR Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 148 of 488
14. Timer (Timer A)
M32C/83 Group (M32C/83, M32C/83T)
14.1.4 Pulse Width Modulation Mode
In pulse width modulation mode, the timer outputs pulse of desired width continuously (see Table 14.7).
The counter functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. Figure 14.13
shows the TAiMR register (i=0 to 4) in pulse width modulation mode. Figures 14.14 and 14.15 show
examples of how a 16-bit pulse width modulator operates and of how an 8-bit pulse width modulator
operates.
Table 14.7 Specifications in Pulse Width Modulation Mode
Item
Specification
Count Source
f1, f8, f2n(1), fC32
Counting Operation
The timer decrements the counter
(The counter functions as an 8-bit or a 16-bit pulse width modulator)
• The timer reloads on the rising edge of PWM pulse and continues counting.
• The timer is not affected by the trigger that is generated during counting.
16-Bit PWM
• "H" width = n / fj
n : setting value of the TAi register
000016 to FFFE16
fj : Count source frequency
• Cycle =
(216-1)
/ fj fixed
• "H" width = n x (m+1) / fj
8-Bit PWM
n : setting value of high-order bit address of the TAi register
• Cycles =
(28-1)
x (m+1) / fj
m : setting value of low-order bit address of the TAi register
Counter Start Condition
0016 to FE16
0016 to FF16
• External trigger is input
• The timer overflows and underflows
• The TAiS bit in the TABSR register is set to "1" (start counting)
Counter Stop Condition
The TAiS bit is set to "0" (stop counting)
Interrupt Request Generation Timing On the falling edge of the PWM pulse
TAiIN Pin Function
Programmable I/O port or trigger input
TAiOUT Pin Function
Pulse output
Read from Timer
The value in the TAi register is indeterminate when read
Write to Timer
• When the timer counter stops,
the value written to the TAi register is also written to both reload register and counter
• While counting,
the value written to the TAi register is written to the reload register
(It is transferred to the counter at the next reload timing)
NOTES:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 149 of 488
14. Timer (Timer A)
M32C/83 Group (M32C/83, M32C/83T)
Timer Ai Mode Register (i=0 to 4) (Pulse Width Modulator Mode)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TA0MR to TA4MR
1 1
Bit
Symbol
Address
035616, 035716, 035816, 035916, 035A16
Bit Name
TMOD0
Operation Mode
Select Bit
TMOD1
After Reset
0000 0X002
Function
b1b0
1 1 : Pulse width modulation (PWM)
mode
RW
RW
RW
Nothing is assigned. When write, set to "0".
(b2)
MR1
External Trigger Select
Bit(1)
0 : Falling edge of input signal to TAiIN pin
RW
1 : Rising edge of input signal to TAiIN pin
MR2
Trigger Select Bit
0 : The TAiS bit is enabled
1 : Selected by the TAiTGH and TAiTGL
bits
MR3
16/8-Bit PWM Mode
Select Bit
0: Functions as a 16-bit pulse width modulator
RW
1: Functions as an 8-bit pulse width modulator
b7 b6
TCK0
Count Source
Select Bit
TCK1
0 0 : f1
0 1 : f8
1 0 : f2n(2)
1 1 : fC32
RW
RW
RW
NOTES:
1. The MR1 bit setting is enabled only when the TAiTGH to TAiTGL bits in the TRGSR register are set
to "002" (input to the TAiIN pin). The MR1 bit can be set to either "0" or "1" when the TAiTGH and
TAiTGL bits are set to "012" (TB2 overflow and underflow), "102" (TAi overflow and underflow) or
"112" (TAi overflow and underflow).
2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Figure 14.13 TA0MR to TA4MR Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 150 of 488
14. Timer (Timer A)
M32C/83 Group (M32C/83, M32C/83T)
When the reload register is set to "000316" and an external
trigger (rising edge of input signal to the TAiIN pin) is selected
1 / fj x (216 – 1)
Count source
“H”
Input signal
to TAiIN pin
“L”
No trigger is generated by this signal
1 / fi x n(1)
“H”
PWM pulse output
from TAiOUT pin
“L”
“1”
IR bit in TAiIC register
“0”
fj : Count source
(f1, f8, f2n(2), fC32)
i=0 to 4
Set to "0" by an interrupt request acknowledgement or by program
NOTES:
1. n = 000016 to FFFE16.
2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Figure 14.14 16-bit Pulse Width Modulator Operation
When 8 high-order bits of the reload register are set to "0216",
8 low-order bits of the reload register are set to "0216" and
an external trigger (falling edge of input signal to the TAiIN pin) is selected
1 / fj x (m + 1) x (28 – 1)
Count source(1)
Input signal to TAiIN pin
“H”
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
“L”
1 / fj x (m + 1) (3)
Underflow signal of
8-bit prescaler(2)
“H”
“L”
1 / fj x (m + 1) x n (3)
PWM pulse output
from TAiOUT pin
“H”
“L”
“1”
IR bit in TAiIC register
“0”
fj : Count source frequency
(f1, f8, f2n(4), fC32)
Set to "0" by an interrupt request
acknowledgement or by program
i=0 to 4
NOTES:
1. 8-bit prescaler counts a count source.
2. 8-bit pulse width modulator counts underflow signals of the 8-bit prescaler.
3. m = 0016 to FF16, n = 0016 to FE16
4. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (
n=1 to 15).
Figure 14.15 8-bit Pulse Width Modulator Operation
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 151 of 488
14. Timer (Timer B)
M32C/83 Group (M32C/83, M32C/83T)
14.2 Timer B
Figure 14.16 shows a block diagram of the timer B. Figures 14.17 to 14.19 show registers associated with
the timer B. The timer B supports the following three modes. The TMOD1 to TMOD0 bits in the TBiMR
register (i=0 to 5) determine which mode is used.
• Timer mode : The timer counts an internal count source.
• Event counter mode : The timer counts pulses from an external source or overflow and underflow of
another timer.
• Pulse period/pulse width measurement mode : The timer measures pulse period or pulse width of an
external signal.
Table 14.18 lists TBiIN pin settings.
High-order Bits of Data Bus
Select Clock Source
00
f1
TCK1 to
TCK0
01
f8
10
(1)
f2n
fc32 11
8 low-order
bits
00: Timer
01: Pulse Period and Pulse
TMOD1 to TMOD0
Width Measurement
TCK1
(Note 2, 3)
TBj Overflow
Low-order Bits of Data Bus
1
8 highorder
bits
Reload Register
Counter
01:
Event Counter
TBiS
0
Polarity Switching
and Edge Pulse
TBiIN
Counter Reset Circuit
i=0 to 5
NOTES:
1. The CNT3 to CNT0 bits in the TCSPR register select no
division (n=0) or divide-by-2n (n=1 to 15).
2. The timer counter overflows or underflows.
3. j=i-1, except j=2 when i=0 j=5 when i=3
TBi
Timer B0
Timer B1
Timer B2
Timer B3
Timer B4
Timer B5
Address
035116 035016
035316 035216
035516 035416
031116 031016
031316 031216
031516 031416
TBj
Timer B2
Timer B0
Timer B1
Timer B5
Timer B3
Timer B4
TCK1 to TCK0, TMOD1 to TMOD0 : Bits in TAiMR register
TBiS : Bits in the TABSR and the TBSR register
Figure 14.16 Timer B Block Diagram
Timer Bi Register(1) (i=0 to 5)
b15
b8 b7
b0
Symbol
TB0 to TB2
TB3 to TB5
Mode
Address
035116 - 035016, 035316 - 035216, 035516 - 035416
031116 - 031016, 031316 - 031216, 031516 - 031416
Function
After Reset
Indeterminate
Indeterminate
Setting Range
Timer Mode
Event Counter
Mode
If setting value is n, a count source 000016 to FFFF16 RW
is divided by n+1(2)
Pulse Period/Pulse A count source is incremented
Width Measurement between one valid edge and
Mode
another valid edge of TBiIN pulse
NOTES:
1. Use 16-bit data for read and write operations.
2. The TBi register counts the number of external input pulses or the number of times another
timer counter overflows and underflows.
Figure 14.17 TB0 to TB5 Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
RW
If setting value is n, a count source 000016 to FFFF16 RW
is divided by n+1
Page 152 of 488
RO
14. Timer (Timer B)
M32C/83 Group (M32C/83, M32C/83T)
Timer Bi Mode Register (i=0 to 5)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TB0MR to TB5MR
Bit
Symbol
Address
After Reset
035B16, 035C16, 035D16, 031B16, 031C16, 031D16 00XX 00002
Bit Name
Function
RW
b1b0
TMOD0
Operation Mode
Select Bit
TMOD1
0 0 : Timer mode
RW
0 1 : Event counter mode
1 0 : Pulse period measurement mode,
pulse width measurement mode
RW
1 1 : Do not set to this value
MR0
RW
MR1
Function varies depending on
operation mode (1, 2)
MR2
MR3
RW
RW
RW
TCK0
RW
Count Source
Select Bit
Function varies depending on
operation mode
TCK1
RW
NOTES:
1. Only MR2 bits in the TB0MR and TB3MR registers are enabled.
2. Nothing is assigned in the MR2 bit in the TB1MR, TB2MR, TB4MR and TB5MR registers.
When write, set to "0". When read, its content is indeterminate.
Count Start Flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TABSR
Bit
Symbol
Address
034016
After Reset
0016
Bit Name
Function
TA0S
Timer A0 Count
Start Flag
0 : Stops counting
1 : Starts counting
RW
TA1S
Timer A1 Count
Start Flag
0 : Stops counting
1 : Starts counting
RW
TA2S
Timer A2 Count
Start Flag
0 : Stops counting
TA3S
Timer A3 Count
Start Flag
0 : Stops counting
TA4S
Timer A4 Count
Start Flag
0 : Stops counting
1 : Starts counting
RW
TB0S
Timer B0 Count
Start Flag
0 : Stops counting
1 : Starts counting
RW
TB1S
Timer B1 Count
Start Flag
0 : Stops counting
1 : Starts counting
RW
TB2S
Timer B2 Count
Start Flag
0 : Stops counting
1 : Starts counting
RW
1 : Starts counting
1 : Starts counting
Figure 14.18 TB0MR to TB5MR Registers, TABSR Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
RW
Page 153 of 488
RW
RW
14. Timer (Timer B)
M32C/83 Group (M32C/83, M32C/83T)
Timer B3, B4,B5 Count Start Flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TBSR
Bit
Symbol
Address
030016
After Reset
000X XXXX2
Bit Name
Function
RW
Nothing is assigned. When write, set to "0".
(b4 - b0) When read, its content is indeterminate.
TB3S
Timer B3 Count
Start Flag
0 : Stops counting
1 : Starts counting
RW
TB4S
Timer B4 Count
Start Flag
0 : Stops counting
1 : Starts counting
RW
TB5S
Timer B5 Count
Start Flag
0 : Stops counting
1 : Starts counting
RW
Figure 14.19 TBSR Register
Table 14.8 Settings for the TBiIN Pins (i=0 to 5)
Port Name
Function
Setting
PS1, PS3(1) Registers
PD7, PD9(1) Registers
P90
TB0IN
PS3_0=0
PD9_0=0
P91
TB1IN
PS3_1=0
PD9_1=0
P92
TB2IN
PS3_2=0
PD9_2=0
P93
TB3IN
PS3_3=0
PD9_3=0
P94
TB4IN
PS3_4=0
PD9_4=0
P71
TB5IN
PS1_1=0
PD7_1=0
NOTES:
1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (
write enable). Do not generate an interrupt or a DMA transfer between the instruction to set the
PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 154 of 488
14. Timer (Timer B)
M32C/83 Group (M32C/83, M32C/83T)
14.2.1 Timer Mode
In timer mode, the timer counts an internally generated count source (see Table 14.9). Figure 14.20
shows the TBiMR register (i=0 to 5) in timer mode.
Table 14.9 Specifications in Timer Mode
Item
Specification
Count Source
f1, f8, f2n(1), fC32
Counting Operation
The timer decrements a counter value
• When the timer counter underflows, content of the reload register is reloaded into the
count register and counting resumes
Divide Ratio
1/(n+1)
n: setting value of the TBi register (i=0 to 5)
000016 to FFFF16
Counter Start Condition
The TBiS bits in the TABSR or TBSR registers are set to "1" (starts counting)
Counter Stop Condition
The TBiS bit is set to "0" (stops counting)
Interrupt Request Generation Timing The timer counter underflows
TBiIN Pin Function
Programmable I/O port
Read from Timer
The TBi register indicates counter value
Write to Timer
• When the timer counter stops,
the value written to the TBi register is also written to both reload register and counter
• While counting,
the value written to the TBi register is written to the reload register
(It is transferred to the counter at the next reload timing)
NOTES:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Timer Bi Mode Register (i=0 to 5) (Timer Mode)
b7
b6
b5
b4
0
b3
b2
b1
b0
Symbol
Address
After reset
TB0MR to TB5MR 035B16, 035C16, 035D16, 031B16, 031C16, 031D16 00XX 00002
0 0
Bit
Symbol
Bit Name
TMOD0
Operation Mode
Select Bit
Function
b1b0
MR1
RW
0 0 : Timer mode
TMOD1
MR0
RW
RW
RW
Disabled in timer mode.
Can be set to "0" or "1".
RW
TB0MR, TB3MR registers:
Set to "0" in timer mode
MR2
TB1MR, TB2MR TB4MR, TB5MR registers:
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
MR3
Set to "0" in timer mode
RW
RW
b7 b6
TCK0
Count Source
Select Bit
TCK1
0 0 : f1
0 1 : f8
1 0 : f2n(1)
1 1 : fC32
RW
RW
NOTES:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Figure 14.20 TB0MR to TB5MR Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 155 of 488
14. Timer (Timer B)
M32C/83 Group (M32C/83, M32C/83T)
14.2.2 Event Counter Mode
In event counter mode, the timer counts how many external signals are applied or how many times
another timer overflows and underflows. (See Table 14.10) Figure 14.21 shows the TBiMR register (i=0
to 5) in event counter mode.
Table 14.10 Specifications in Event Counter Mode
Item
Specification
• External signal applied to the TBiIN pin (i = 0 to 5) (valid edge can be selected by
Count Source
program)
• TBj overflows or underflows (j=i-1, except j=2 when i=0, j=5 when i=3)
Counting Operation
• The timer decrements a counter value
When the timer counter underflows, content of the reload register is reloaded into the
count register to continue counting
Divide Ratio
1/(n+1)
n : setting value of the TBi register
000016 to FFFF16
Counter Start Condition
The TBiS bit in the TABSR or TBSR register is set to "1" (starts counting)
Counter Stop Condition
The TBiS bit is set to "0" (stops counting)
Interrupt Request Generation Timing The timer counter underflows
TBiIN Pin Function
Programmable I/O port or count source input
Read from Timer
The TBi register indicates the value of the counter
Write to Timer
• When the timer counter stops,
the value written to the TBi register is also written to both reload register and counter
• While counting,
the value written to the TBi register is written to the reload register
(It is transferred to the counter at the next reload timing)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 156 of 488
14. Timer (Timer B)
M32C/83 Group (M32C/83, M32C/83T)
Timer Bi Mode Register (i=0 to 5) (Event Counter Mode)
b7
b6
b5
b4
0
b3
b2
b1
b0
Symbol
Address
After reset
TB0MR to TB5MR 035B16, 035C16, 035D16, 031B16, 031C16, 031D16 00XX 00002
0 1
Bit
Symbol
TMOD0
TMOD1
Bit Name
Operation Mode
Select Bit
Function
b1 b0
0 1 : Event counter mode
RW
RW
RW
b3 b2
MR0
Count Polarity Select
Bit(1)
MR1
0 0 : Counts falling edges of external signal RW
0 1 : Counts rising edges of external signal
1 0 : Counts falling and rising edges of
external signal
RW
1 1 : Do not set to this value
TB0MR and TB3MR registers:
Set to "0" in event counter mode
MR2
TB1MR, TB2MR, TB4MR and TB5MR registers:
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
MR3
Disabled in event counter mode. When write, set to "0".
When read, its content is indeterminate.
TCK0
Disabled in event counter mode.
Can be set to "0" or "1".
TCK1
RW
Count Source
Select Bit
0 : Input signal from the TBiIN pin
1 : TBj overflows or underflows(2)
RW
RW
NOTES:
1. The MR0 and MR1 bits are enabled when the TCK1 bit is set to "0" (input signal from the TBiIN pin).
The MR1 bit can be set to either "0" or "1", when the TCK1 bit is set to "1" (timer overflow or
underflow).
2. j=i – 1, except j=2 when i=0 and j=5 when i=3.
Figure 14.21 TB0MR to TB5MR Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 157 of 488
14. Timer (Timer B)
M32C/83 Group (M32C/83, M32C/83T)
14.2.3 Pulse Period/Pulse Width Measurement Mode
In pulse period/pulse width measurement mode, the timer measures pulse period or pulse width of an
external signal. (See Table 14.11) Figure 14.22 shows the TBiMR register (i=0 to 5) in pulse period/pulse
width measurement mode. Figure 14.23 shows an example of an operation timing when measuring a
pulse period. Figure 14.24 shows an example of the pulse width measurement.
Table 14.11 Specifications in Pulse Period/Pulse Width Measurement Mode
Item
Specification
Count Source
f1, f8, f2n(3), fC32
Counting Operation
• The timer increments a counter value
Counter value is transferred to the reload register on the valid edge of a pulse to be
measured. It is set to "000016" and the timer continues counting
Counter Start Condition
The TBiS bit (i=0 to 5) in the TABSR or TBSR register is set to "1" (starts counting)
Counter Stop Condition
The TBiS bit is set to "0" (stops counting)
Interrupt Request Generation Timing • On the valid edge of a pulse to be measured(1)
• The timer counter overflows
The MR3 bit in the TBiMR register is set to "1" (overflow) simultaneously. When the
TBiS bit is set to "1" (start counting) and the next count source is counted after setting
the MR3 bit to "1" (overflow), the MR3 bit can be set to "0" (no overflow) by writing to
the TBiMR register.
TBiIN Pin Function
Input for a pulse to be measured
Read from Timer
The TBi register indicates reload register values (measurement results)(2)
Write to Timer
Value written to the TBi register can be written to neither reload register nor counter
NOTES:
1. No interrupt request is generated when the pulse to be measured is on the first valid edge after the
timer has started counting.
2. The TBi register is in an indeterminate state until the pulse to be measured is on the second valid
edge after the timer has started counting.
3. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 158 of 488
14. Timer (Timer B)
M32C/83 Group (M32C/83, M32C/83T)
Timer Bi Mode Register (i=0 to 5)
(Pulse Period / Pulse Width Measurement Mode)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
After reset
TB0MR to TB5MR 035B16, 035C16, 035D16, 031B16, 031C16, 031D16 00XX 00002
1 0
Bit
Symbol
TMOD0
TMOD1
Bit Name
Operation Mode
Select Bit
Function
RW
b1 b0
RW
1 0 : Pulse period measurement mode,
pulse width measurement mode RW
b3 b2
MR0
Measurement Mode
Select Bit
MR1
0 0 : Pulse period measurement 1
RW
0 1 : Pulse period measurement 2
1 0 : Pulse width measurement
RW
1 1 : Do not set to this value (Note 1)
TB0MR, TB3MR registers:
Set to "0" in pulse period/pulse width measurement mode
MR2
MR3
RW
TB1MR, TB2MR TB4MR, TB5MR registers:
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
0 : No overflow
Timer Bi Overflow Flag(2) 1 : Overflow
RO
b7 b6
TCK0
Count Source
Select Bit
TCK1
0 0 : f1
0 1 : f8
1 0 : f2n(3)
1 1 : fC32
RW
RW
NOTES:
1. The MR1 to MR0 bits selects the following measurements.
Pulse period measurement 1 (MR1 to MR0 bits = 002) :
Measures between the falling edge and the next falling edge of a pulse to be measured
Pulse period measurement 2 (MR1 to MR0 bits = 012) :
Measures between the rising edge and the next rising edge of a pulse to be measured
Pulse width measurement (MR1 to MR0 bits = 102) :
Measures between a falling edge and the next rising edge of a pulse to be measured and
between the rising edge and the next falling edge of a pulse to be measured
2. The MR3 bit is indeterminate when reset.
When the timer overflows, the MR3 bit is set to "1" (overflow) simultaneously. When the TBiS bit is
set to "1" (start counting) and the next count source is counted after the MR3 bit is set to "1", the
MR3 bit is set to "0" (no overflow) by writing again.
The MR3 bit cannot be set to "1" by program.
3. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Figure 14.22 TB0MR to TB5MR Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 159 of 488
14. Timer (Timer B)
M32C/83 Group (M32C/83, M32C/83T)
Count source
Pulse to be measured
“H”
“L”
Transferred
(indeterminate value)
Counter to reload register
transfer timing
Transferred
(measured value)
(Note 1)
(Note 1)
(Note 2)
Timing that the counter
reaches "000016"
“1”
TBiS bit in TABSR or
TBSR register
IR bit in TBilC register
“0”
“1”
“0”
Set to "0" by an interrupt request acknowledgement or by program
“1”
MR3 bit in TBiMR
register
“0”
i=0 to 5
NOTES:
1. The counter is reset when a measurement is completed.
2. The timer counter overflows.
Figure 14.23 Pulse Period 1 Measurement
Count source
Pulse to be measured
“H”
“L”
Transferred
(indeterminate
value)
Counter to reload register
transfer timing
(Note 1)
Transferred
(measured value)
(Note 1)
Transferred
(measured
value)
(Note 1)
Transferred
(measured value)
(Note 1)
(Note 2)
Timing that the counter
reaches "000016"
TBiS bit in TABSR or
TBSR register
IR bit in TBilC register
“1”
“0”
“1”
“0”
Set to "0" by an interrupt request acknowledgement or by program.
MR3 bit in TBiMR
register
“1”
“0”
i=0 to 5
NOTES:
1. The counter is reset when a measurement is completed.
2. The timer counter overflows.
Figure 14.24 Pulse Width Measurement
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 160 of 488
15. Three-Phase Motor Control Timer Functions
M32C/83 Group (M32C/83, M32C/83T)
15. Three-Phase Motor Control Timer Functions
Three-phase motor driving waveform can be output by using the timers A1, A2, A4 and B2. Table 15.1 lists
specifications of the three-phase motor control timer functions. Table 15.2 lists pin settings. Figure 15.1
shows a block diagram. Figures 15.2 to 15.7 show registers associated with the three-phase control timer
functions.
Table 15.1 Three-Phase Motor Control Timer Functions Specification
Item
Specification
___
___
___
Three-Phase Waveform Output Pin
Six pins (U, U, V, V, W, W)
Forced Cutoff(1)
Apply a low-level signal ("L") to the NMI pin
Timers to be Used
Timer A4, A1, A2 (used in one-shot timer mode)
_______
___
Timer A4: U- and U-phase waveform control
___
Timer A1: V- and V-phase waveform control
___
Timer A2: W- and W-phase waveform control
Timer B2 (used in timer mode)
Carrier wave cycle control
Dead time timer (three 8-bit timers share reload register)
Dead time control
Output Waveform
Triangular wave modulation, Sawtooth wave modification
Can output a high-level waveform or a low-level waveform for one cycle
Can set positive-phase level and negative-phase level separately
Triangular wave modulation: count source x (m+1) x 2
Carrier Wave Cycle
Sawtooth wave modulation: count source x (m+1)
m: setting value of the TB2 register, 000016 to FFFF16
Count source: f1, f8, f2n(2), fc32
Three-Phase PWM Output Width
Triangular wave modulation: count source x n x 2
Sawtooth wave modulation: count source x n
n : setting value of the TA4, TA1 and TA2 register (of the TA4, TA41, TA1, TA11,
TA2 and TA21 registers when setting the INV11 bit to "1"), 000116 to FFFF16
Count source: f1, f8, f2n(2), fc32
Count source x p, or no dead time
Dead Time
p: setting value of the DTT register, 0116 to FF16
Count source: f1, or f1 divided by 2
Active Level
Selected from a high level ("H") or low level ("L")
Positive and Negative-Phase Con-
Positive and negative-phases concurrent active disable function
current Active Disable Function
Positive and negative-phases concurrent active detect function
Interrupt Frequency
For the timer B2 interrupt, one carrier wave cycle-to-cycle basis through 15
time- carrier wave cycle-to-cycle basis can be selected
NOTES:
_______
1. Forced cutoff by the signal applied to the NMI pin is available when the INV02 bit is set to "1" (threephase motor control timer functions) and the INV03 bit is set to "1" (three-phase motor control timer
output enabled).
2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 161 of 488
15. Three-Phase Motor Control Timer Functions
M32C/83 Group (M32C/83, M32C/83T)
Table 15.2 Pin Settings
Setting
Pin
PS1, PS2 Registers(1)
PSL1, PSL2 Registers
PSC Register
P72/V
PS1_2 =1
PSL1_2 =0
PSC_2 =1
P73/V
PS1_3 =1
PSL1_3 =1
PSC_3 =0
P74/W
PS1_4 =1
PSL1_4 =1
PSC_4 =0
P75/W
PS1_5 =1
PSL1_5 =0
P80/U
PS2_0 =1
PSL2_0 =1
P81/U
PS2_1 =1
PSL2_1 =0
NOTES:
1. Set the PS1_2 to PS1_5 and PS2_0 to PS2_1 bits in the PS1 and PS2 registers to "1" after
the INV02 bit is set to "1".
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 162 of 488
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
(Timer Mode)
Timer B2
Page 163 of 488
TA41 Register
T Q
INV11
(One-Shot Timer Mode)
Timer A4 Counter
Reload
TA11 Register
T Q
INV11
(One-Shot Timer Mode)
Timer A1 Counter
Reload
Figure 15.1 Three-Phase Motor Control Timer Functions Block Diagram
TA21 Register
(One-Shot Timer Mode)
INV11
T Q
Timer A2 Counter
Reload
When setting the TA2S bit to "0", signal is
set to "0"
Trigger
TA2 Register
When setting the TA1S bit to "0", signal is
set to "0"
Trigger
TA1 Register
When setting the TA4S bit to "0", signal is
set to "0"
Trigger
TA4 Register
INV07
INV00
Reload Control Signal for
Timer A4
Start Trigger Signal for
Timers A1, A2, A4
Write Signal
to Timer B2
INV10
Timer B2 Underflow
INV00 to INV07: Bits in INVC0 Register
INV10 to INV15: Bits in INVC1 Register
DUi, DUBi: Bits in IDBi Register (i=0,1)
TA1S to TA4S: Bits in TABSR Register
1/2
0
1
INV06
INV06
Timer A4
One-Shot
Pulse
Transfer
Trigger(1)
INV06
f1
INV12
INV01
INV11
0
1
A
T
Q
T
Q
T
Q
D
T
Q
DUB0
bit
D
DU0
bit
W-Phase Output Signal
W-Phase Output Signal
Dead Time Timer
n = 1 to 255
V-Phase Output Signal
V-Phase Output Signal
Dead Time Timer
n = 1 to 255
U-Phase Output Signal
Three-Phase Output
Shift Register
(U Phase)
U-Phase Output Signal
T
D Q
D Q
T
D Q
T
D Q
T
T
D Q
D Q
T
INV05
INV04
RESET
NMI
Value to be written
to INV03 bit
Write signal to
INV03 bit
R
Inverse
Control
Inverse
Control
Inverse
Control
Inverse
Control
Inverse
Control
Inverse
Control
INV14
INV02
T
D Q
INV03
Switching to P80, P81 and P72 to P75 is not shown in this diagram.
NOTES:
1. Transfer trigger is generated only when the IDB0 and IDB1 registers are set and the first timer B2 underflows,
if the INV06 bit is set to "0" (triangular wave modulation).
W-Phase Output
Control Circuit
Trigger
Trigger
V-Phase Output
Control Circuit
Trigger
Trigger
D
DUB1
bit
D
DU1
bit
Reload Register
n = 1 to 255
ICTB2 Counter
n=1 to 15
Timer B2
Interrupt Request Bit
ICTB2 Register n=1 to 15
Dead Time Timer
n = 1 to 255
U-phase Output
Control Circuit
Trigger
Trigger
INV13
Circuit to set Interrupt
Generation Frequency
W
W
V
V
U
U
M32C/83 Group (M32C/83, M32C/83T)
15. Three-Phase Motor Control Timer Functions
15. Three-Phase Motor Control Timer Functions
M32C/83 Group (M32C/83, M32C/83T)
Three-Phase PWM Control Register 0(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
INVC0
Bit
Symbol
Address
030816
After Reset
0016
Function
RW
Interrupt Enable Output
INV00
Polarity Select Bit(3)
0: The ICTB2 counter is incremented by one on the
rising edge of the timer A1 reload control signal
1: The ICTB2 counter is incremented by one on the
falling edge of the timer A1 reload control signal
RW
Interrupt Enable Output
Specification Bit(2, 3)
0: ICTB2 counter is incremented by one
whenever the timer B2 counter underflows
1: Selected by the INV00 bit
RW
INV01
Bit Name
INV02 Mode Select Bit(4, 5, 6)
0: No three-phase control timer functions
1: Three-phase control timer function
(6, 7)
INV03 Output Control Bit
0: Disables three-phase control timer output
1: Enables three-phase control timer output
RW
Positive and NegativeINV04 Phases Concurrent Active
Disable Function Enable Bit
Positive and NegativeINV05 Phases Concurrent Active
Output Detect Flag(8)
0: Enables concurrent active output
1: Disables concurrent active output
RW
0: Not detected
1: Detected
RW
Modulation Mode
Select(9, 10)
0: Triangular wave modulation mode
1: Sawtooth wave modulation mode
RW
Transfer trigger is generated when the
INV07 bit is set to "1". Trigger to the dead
time timer is also generated when setting the
INV06 bit to "1". Its value is "0" when read.
RW
INV06
INV07 Software Trigger Select
RW
NOTES:
1. Set the INVC0 register after the PRC1 bit in the PRCR register is set to "1" (write enable).
Rewrite the INV00 to INV02 and INV06 bits when the timers A1,A2, A4 and B2 stop.
2. Set the INV01 bit to "1" after setting the ICTB2 register .
3. The INV00 and INV01 bits are enabled only when the INV11 bit is set to "1" (three-phase mode 1). The ICTB2
counter is incremented by one every time the timer B2 counter underflows, regardless of INV00 and INV01 bit
settings, when the INV11 bit is set to "0" (three-phase mode).
When setting the INV01 bit to "1", set the timer A1 count start flag before the first timer B2 counter underflow.
When the INV00 bit is set to "1", the first interrupt is generated when the timer B2 counter underflows n-1 times,
if n is the value set in the ICTB2 counter. Subsequent interrupts are generated every n times the timer B2
counter underflows.
4. Set the INV02 bit to "1" to operate the dead time timer, U-, V-and W-phase output control circuits and the ICTB2
counter.
5. Set pins after the INV02 bit is set to "1". See Table 15.2 for pin settings.
6. When the INV02 bit is set to "1" and the INV03 bit to "0", U, U, V, V, W and W pins, including pins shared with
other output functions, are placed in high-impedance states.
7. The INV03 bit is set to "0" when the followings occurs :
- Reset
- A concurrent active state occurs while INV04 bit is set to "1"
- The INV03 bit is set to "0" by program
- A signal applied to the NMI pin changes "H" to "L"
8. The INV05 bit can not be set to "1" by program. Set the INV04 bit to "0", as well, when setting the INV05 bit to "0".
9. The following table describes how the INV06 bit works.
INV06 = 1
Item
INV06 = 0
Triangular wave modulation mode
Timing to Transfer from the IDB0
Transferred once by generating a
and IDB1 Registers to Three-Phase transfer trigger after setting the IDB0
Output Shift Register
and IDB1 registers
Mode
Sawtooth wave modulation mode
Transferred every time a transfer trigger
is generated
Timing to Trigger the Dead Time
Timer when the INV16 Bit=0
On the falling edge of a one-shot pulse By a transfer trigger, or the falling edge of
a one-shot pulse of the timer A1, A2 or A4
of the timer A1, A2 or A4
INV13 Bit
Enabled when the INV11 bit=1 and the Disabled
INV06 bit=0
Transfer trigger : Timer B2 underflows and write to the INV07 bit, or write to the TB2 register when INV10 = 1
10. When the INV06 bit is set to "1", set the INV11 bit to "0" (three-phase mode 0) and the PWCON bit in the
TB2SC register to "0" (timer B2 counter underflows).
Figure 15.2 INVC0 Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 164 of 488
15. Three-Phase Motor Control Timer Functions
M32C/83 Group (M32C/83, M32C/83T)
Three-Phase PWM Control Register 1(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
INVC1
030916
Bit
Symbol
After Reset
0016
Bit Name
Function
RW
INV10
Timer A1, A2 and A4
Start Trigger Select Bit
0: Timer B2 counter underflows
1: Timer B2 counter underflows
and write to the TB2 register
INV11
Timer A1-1, A2-1, A4-1
Control Bit(2, 3)
0: Three-phase mode 0
1: Three-phase mode 1
INV12
Dead Time Timer
0 : f1
Count Source Select Bit 1 : f1 divided-by-2
INV13
Carrier Wave Detect Flag(4)
0: Timer A1 reload control signal is "0" RO
1: Timer A1 reload control signal is "1"
INV14
Output Polarity Control Bit
0 : Active "L" of an output waveform
1 : Active "H" of an output waveform
RW
INV15
Dead Time Disable Bit
0: Enables dead time
1: Disables dead time
RW
INV16
0: Falling edge of a one-shot pulse of
Dead Time Timer Trigger the timer A1, A2, A4(5)
RW
1: Rising edge of the three-phase output
Select Bit
shift register (U-, V-, W-phase)
Reserved Bit
RW
RW
RW
Set to "0"
RW
(b7)
NOTES:
1. Rewrite the INVC1 register after the PRC1 bit in the PRCR register is set to "1" (write enable).
The timers A1, A2, A4, and B2 must be stopped during rewrite.
2. The following table lists how the INV11 bit works.
Item
Mode
INV11 = 0
Three-phase mode 0
TA11, TA21 and TA41 Registers Not used
INV11 = 1
Three-phase mode 1
Used
INV00 and INV01 Bits
in the INVC0 Register
Disabled. The ICTB2 counter is
incremented whenever the timer B2
counter underflows
Enabled
INV13 Bit
Disabled
Enabled when INV11=1 and INV06=0
3. When the INV06 bit is set to "1" (sawtooth wave modulation mode), set the INV11 bit to "0" (threephase mode 0). Also, when the INV11 bit is set to "0", set the PWCON bit in the TB2SC register to "0"
(timer B2 counter underflows).
4. The INV13 bit is enabled only when the INV06 bit is set to "0" (Triangular wave modulation mode) and
the INV11 bit to "1" (three-phase mode 1).
5. If the following conditions are all met, set the INV16 bit to "1".
• The INV15 bit is set to "0" (dead time timer enabled)
• The Dij bit (i=U, V or W, j=0, 1) and DiBj bit always have different values when the INV03 bit
is set to "1". (The positive-phase and negative-phase always output opposite level signals.)
If above conditions are not met, set the INV16 bit to "0".
Figure 15.3 INVC1 Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 165 of 488
15. Three-Phase Motor Control Timer Functions
M32C/83 Group (M32C/83, M32C/83T)
Three-Phase Output Buffer Register i(1) (i=0, 1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
After Reset
IDB0, IDB1
030A16, 030B16
XX11 11112
Bit
Symbol
DUi
DUBi
DVi
DVBi
DWi
DWBi
Bit Name
Function
RW
U-Phase Output Buffer i Write output level
U-Phase Output Buffer i 0: Active level
1: Inactive level
V-Phase Output Buffer i
RW
V-Phase Output Buffer i
When read, the value of the threeW-Phase Output Buffer i phase shift register is read.
RW
W-Phase Output Buffer i
RW
RW
RW
Nothing is assigned. When write, set to "0".
(b7 - b6) When read, its content is "0."
RW
RO
NOTES:
1. Values of the IDB0 and IDB1 registers are transferred to the three-phase output shift register by a
transfer trigger.
After the transfer trigger occurs, the values written in the IDB0 register determine each phase output
signal first. Then the value written in the IDB1 register on the falling edge of timers A1, A2 and A4 oneshot pulse determines each phase output signal.
Dead Time Timer(1, 2)
b7
b0
Symbol
DTT
Address
030C16
Function
If setting value is n, the timer stops when counting
n times a count source selected by the INV12 bit
after start trigger occurs. Positive or negative
phase, which changes from inactive level to active
level, shifts when the dead time timer stops.
After Reset
Indeterminate
Setting Range
RW
1 to 255
WO
NOTES:
1. Use the MOV instruction to set the DTT register.
2. The DTT register is enabled when the INV15 bit in the INVC1 register is set to "0" (dead time
enabled). No dead time can be set when the INV15 bit is set to "1" (dead time disabled). The INV06
bit in the INVC0 register determines start trigger of the DTT register.
Figure 15.4 IDB0, IDB1 and DTT Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 166 of 488
15. Three-Phase Motor Control Timer Functions
M32C/83 Group (M32C/83, M32C/83T)
Timer B2 Interrupt Generation Frequency Set Counter(1, 2, 3)
b7
b0
Symbol
Address
After Reset
ICTB2
030D16
Indeterminate
Setting Range
Function
When the INV01 bit is set to "0" (the ICTB2 counter
increments whenever the timer B2 counter underflows)
and the setting value is n, the timer B2 interrupt is
generated every nth time timer B2 counter underflow
occurs.
When the INV01 bit is set to "1" (selected by the INV00
bit) and setting value is n, the timer B2 interrupt is
generated every nth time timer B2 counter underflow
meeting the condition selected in the INV00 bit occurs.
1 to 15
RW
WO
Nothing is assigned. When write, set to "0".
NOTES:
1. Use the MOV instruction to set the ICTB2 register.
2. If the INV01 bit in the INVC0 register is set to "1", set the ICTB2 register when the TB2S bit is set to "0" (timer B2
counter stopped).
If the INV01 bit is set to "0" and the TB2S bit to "1" (timer B2 counter start), do not set the ICTB2 register when
the timer B2 counter underflows.
3. If the INV00 bit is set to "1", the first interrupt is generated when the timer B2 counter underflows n-1
times, n being the value set in the ICTB2 counter. Subsequent interrupts are generated every n times
the timer B2 counter underflows.
Timer Ai, Ai-1 Register (i=1, 2, 4)(1, 2, 3, 4, 5, 6, 7)
b15
b8 b7
b0
Symbol
TA1, TA2, TA4
TA11, TA21, TA41
Address
After Reset
034916 - 034816, 034B16 - 034A16, 034F16 - 034E16 Indeterminate
030316 - 030216, 030516 - 030416, 030716 - 030616 Indeterminate
Function
If setting value is n, the timer stops when the nth count
source is counted after a start trigger is generated.
Positive phase changes to negative phase, and vice
versa, when the timers A1, A2 and A4 stop.
Setting Range
RW
000016 to FFFF16
WO
NOTES:
1. Use a 16-bit data for read and write..
2. If the TAi or TAi1 register is set to "000016", no counters start and no timer Ai interrupt is generated.
3. Use the MOV instruction to set the TAi and TAi1 registers.
4. When the INV15 bit in the INVC1 register is set to "0" (dead timer enabled), phase switches from an
inactive level to an active level when the dead time timer stops.
5. When the INV11 bit is set to "0" (three-phase mode 0), the value of the TAi register is transferred to
the reload register by a timer Ai start trigger.
When the INV11 bit is set to "1" (three-phase mode 1), the value of the TAi1 register is first
transferred to the reload register by a timer Ai start trigger. Then, the value of the TAi register is
transferred by the next trigger. The values of the TAi1 and TAi registers are transferred alternately to
the reload register with every timer Ai start trigger.
6. Do not write to these registers when the timer B2 counter underflows.
7. Follow the procedure below to set the TAi1 register.
(1) Write value to the TAi1 register.
(2) Wait one timer Ai count source cycle.
(3) Write the same value as (1) to the TAi1 register.
Timer B2 Special Mode Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
After Reset
TB2SC
035E16
XXXX XXX02
Bit
Symbol
PWCON
Bit Name
Timer B2 Reload Timing
Switching Bit(1)
Function
0 : Timer B2 underflow
1 : Timer A output in odd-number
times
RW
RW
Nothing is assigned. When write, set to "0".
When read, its content is "0."
NOTES:
1. When setting the INV11 bit to "0" (three-phase mode 0) or the INV06 bit to "1" (sawtooth wave
modulation mode), set the PWCON bit to "0".
Figure 15.5 ICTB2 Register, TA1, TA2, TA4, TA11, TA21 and TA41 Registers and TB2SC Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 167 of 488
15. Three-Phase Motor Control Timer Functions
M32C/83 Group (M32C/83, M32C/83T)
Timer B2 Register(1)
b15
b8 b7
b0
Symbol
Address
After Reset
TB2
035516 - 035416
Indeterminate
Setting Range
RW
000016 to FFFF16
RW
Function
If setting value is n, count source is divided by n+1.
The timers A1, A2 and A4 start every time an underflow occurs.
NOTES:
1. Use a 16-bit data for read and write.
Trigger Select Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
After Reset
TRGSR
034316
0016
Bit
Symbol
TA1TGL
TA1TGH
TA2TGL
TA2TGH
Function
Bit Name
RW
Timer A1 Event/Trigger
Select Bit
Set to "012" (TB2 underflow) before using
RW
a V-phase output control circuit
RW
Timer A2 Event/Trigger
Select Bit
Set to "012" (TB2 underflow) before using
a W-phase output control circuit
RW
RW
b5 b4
TA3TGL
Timer A3 Event/Trigger
Select Bit
TA3TGH
TA4TGL
TA4TGH
Timer A4 Event/Trigger
Select Bit
0
0
1
1
0 : Selects an input to the TA3IN pin
1 : Selects TB2 overflow(1)
0 : Selects TA2 overflow(1)
1 : Selects TA4 overflow(1)
Set to "012" (TB2 underflow) before using
a U-phase output control circuit
RW
RW
RW
RW
NOTES:
1. Overflow or underflow
Count Start Flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
After Reset
TABSR
034016
0016
Bit
Symbol
Bit Name
RW
TA0S
Timer A0 Count
Start Flag
0 : Stops counting
1 : Starts counting
RW
TA1S
Timer A1 Count
Start Flag
0 : Stops counting
1 : Starts counting
RW
TA2S
Timer A2 Count
Start Flag
0 : Stops counting
1 : Starts counting
RW
TA3S
Timer A3 Count
Start Flag
0 : Stops counting
1 : Starts counting
RW
TA4S
Timer A4 Count
Start Flag
0 : Stops counting
1 : Starts counting
RW
TB0S
Timer B0 Count
Start Flag
0 : Stops counting
1 : Starts counting
RW
TB1S
Timer B1 Count
Start Flag
0 : Stops counting
1 : Starts counting
RW
TB2S
Timer B2 Count
Start Flag
0 : Stops counting
1 : Starts counting
RW
Figure 15.6 TB2, TRGSR and TABSR Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Function
Page 168 of 488
15. Three-Phase Motor Control Timer Functions
M32C/83 Group (M32C/83, M32C/83T)
Timer Ai Mode Register (i=1, 2, 4)
b7
b6
b5
b4
0
1
b3
b2
b1
b0
Symbol
Address
After Reset
1
0
TA1MR, TA2MR, TA4MR
035716, 035816, 035A16
0000 0X002
Bit
Symbol
Bit Name
TMOD0 Operation Mode
TMOD1 Select Bit
Function
Set to "102" (one-shot timer
mode) with the three-phase motor
control timer function
RW
RW
Nothing is assigned. When write, set to "0".
(b2)
MR1
External Trigger Select Bit
Set to "0" with the three-phase motor
RW
control timer function
MR2
Trigger Select Bit
Set to "1"(selected by the
TRGSR register) with the threephase motor control timer function
MR3
Set to "0" with the three-phase motor control timer function
RW
RW
b7 b6
TCK0
Count Source Select Bit
TCK1
0
0
1
1
RW
0 : f1
1 : f8
0 : f2n(1)
1 : fC32
RW
NOTES:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Timer B2 Mode Register
b7
b6
b5
b4
0
b3
b2
b1
b0
Symbol
Address
After Reset
0
0
TB2MR
035D16
00XX 00002
Bit
Symbol
Bit Name
Function
RW
MR1
Set to "002" (timer mode) when using
Operation Mode
the three-phase motor control timer
RW
Select Bit
function
Disabled when using the three-phase motor control timer function.
When write, set to "0".
When read, its content is indeterminate.
MR2
Set to "0" when using three-phase motor control timer function
RW
MR3
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
RW
TMOD0
TMOD1
MR0
b7 b6
TCK0
Count Source Select Bit
TCK1
0
0
1
1
0 : f1
1 : f8
0 : f2n(1)
1 : fC32
RW
RW
NOTES:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Figure 15.7 TA1MR, TA2MR, TA4MR Registers and TB2MR Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 169 of 488
15. Three-Phase Motor Control Timer Functions
M32C/83 Group (M32C/83, M32C/83T)
The three-phase control timer function is available by setting the INV02 bit in the INVC0 register to "1".
__
The timer B2 is used for carrier wave control and timers A4, A1, A2 for three-phase PWM output (U, U, V,
__
___
V, W, W) control. An exclusive dead time timer controls dead time. Figure 15.8 shows an example of the
triangular modulation waveform. Figure 15.9 shows an example of the sawtooth modulation waveform.
Triangular waveform as a Carrier Wave
Triangular Wave
Signal Wave
TB2S Bit in
TABSR Register
Timer B2
Timer A1
Reload Control Signal(1)
Timer A4
Start Trigger Signal(1)
TA4 Register(2)
m
n
p
q
r
TA41 Register(2)
m
n
p
q
r
Reload Register(2)
m
Timer A4
(1)
One-Shot Pulse
m
m
n
m
n
n
n
p
p
p
n
r
q
q
q
Rewrite the IDB0 and IDB1 registers
U-Phase Output
Signal(1)
Transfer a counter
value to the three-phase
shift register
U-Phase Output
(1)
Signal
INV14 = 0
("L" active)
q
p
U-Phase
U-Phase
Dead time
INV14 = 1
("H" active)
U-Phase
Dead time
U-Phase
INV00, INV01: Bits in the INVC0 register
INV11, INV14: Bits in the INVC1 register
NOTES:
1. Internal signals. See Figure 15.1.
2. Applies only when the INV11 bit is set to "1" (three-phase mode).
The above applies to INVC0 = 00XX11XX2 and INVC1 = 010XXXX02 (X varies depending on each system.)
Examples of PWM output change are
(b) When INV11=0 (three-phase mode 0)
(a) When INV11=1 (three-phase mode 1)
- INV01=0, ICTB2=116 (The timer B2 interrupt is generated
- INV01=0 and ICTB2=216 (The timer B2 interrupt is
whenever the timer B2 underflows)
generated with every second timer B2 underflow) or
- Default value of the timer: TA4=m
INV01=1, INV00=1and ICTB2=116 (The timer B2 interrupt is
The TA4 register is changed whenever the timer B2
generated on the falling edge of the timer A1 reload control
interrupt is generated.
signal)
First time: TA4=m. Second time: TA4=n.
- Default value of the timer: TA41=m, TA4=m
Third time: TA4=n. Fourth time: TA=p.
The TA4 and TA41 registers are changed whenever the
Fifth time: TA4=p.
timer B2 interrupt is generated.
- Default value of the IDB0 and IDB1 registers:
First time: TA41=n, TA4:=n.
DU0=1, DUB0=0, DU1=0, DUB1=1
Second time: TA41=p, TA4=p.
They are changed to DU0=1, DUB0=0, DU1=1, DUB1=0 by
- Default value of the IDB0 and IDB1 registers
the sixth timer B2 interrupt.
DU0=1, DUB0=0, DU1=0, DUB1=1
They are changed to DU0=1, DUB0=0, DU1=1, DUB1=0
by the third timer B2 interrupt.
Figure 15.8 Triangular Wave Modulation Operation
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 170 of 488
15. Three-Phase Motor Control Timer Functions
M32C/83 Group (M32C/83, M32C/83T)
Sawtooth Waveform as a Carrier Wave
Sawtooth Wave
Signal Wave
Timer B2
Timer A4 Start
Trigger Signal(1)
Timer A4 One-Shot
Pulse(1)
Rewrite the IDB0
and IDB1 registers
Transfer the counter to the
three-phase shift register
U-Phase Output
(1)
Signal
U-Phase Output
Signal(1)
U-Phase
INV14 = 0
("L" active)
Dead time
U-Phase
U-Phase
INV14 = 1
("H" active)
Dead time
U-Phase
INV14: Bits in the INVC1 register
NOTES:
1. Internal signals. See Figure 15.1.
The above applies to INVC0 = 01XX110X2 and INVC1 = 010XXX002 (X varies depending on each system.)
The examples of PWM output change are
- Default value of the IDB0 and IDB1 registers: DU0=0, DUB0=1, DU1=1, DUB1=1
They are changed to DU0=1, DUB0=0, DU1=1, DUB1=1 by the timer B2 interrupt.
Figure 15.9 Sawtooth Wave Modulation Operation
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 171 of 488
M32C/83 Group (M32C/83, M32C/83T)
16. Serial I/O
16. Serial I/O
Serial I/O consists of five channels (UART0 to UART4).
Each UARTi (i=0 to 4) has an exclusive timer to generate the transfer clock and operates independently.
Figure 16.1 shows a UARTi block diagram.
UARTi supports the following modes :
- Clock synchronous serial I/O mode
- Clock asynchronous serial I/O mode (UART mode)
- Special mode 1 (I2C mode)
- Special mode 2
- Special mode 3 (Clock-divided synchronous function, GCI mode)
- Special mode 4 (Bus conflict detect function, IE mode)
- Special mode 5 (SIM mode)
Figures 16.2 to 16.9 show registers associated with UARTi.
Refer to the tables listing each mode for register and pin settings.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 172 of 488
16. Serial I/O
M32C/83 Group (M32C/83, M32C/83T)
RxD Polarity
Switching Circuit
RxDi
Selecting Clock Source
00
CKDIR
f1
Inside
01
0
f8
10
f2n(2)
CLK1 to CLK0 1
Outside
UiBRG
Register
Clock Asynchronous
Transmit
1 / (m+1)
CLK
Polarity
Switching
Circuit
CTS/RTS
selected
1
CTSi / RTSi
TxD
Polarity
Switching
Circuit
Receive
Clock
Transmit/
Receive
Unit
TxDi
(Note 1)
Transmit
Clock
1/16
Transmit
010, 100, 101, 110
Control Circuit
Clock Synchronous Type
001
Clock Synchronous Type
(when internal clock is selected)
1/2
0
1
Clock
Synchronous
Clock Synchronous Type
CKDIR
(when internal clock is selected) Type
(when external clock is
selected)
CKPOL
CLKi
Clock Asynchronous
Receive
SMD2 to SMD0
010, 100, 101, 110
1/16
Receive
001
Control Circuit
Clock Synchronous Type
CTS/RTS disabled
CRD
RTSi
CRS 0
CTS/RTS disabled
0 CRD
1
CTSi
m : setting value of UiBRG register
Vss
IOPOL
No inverse
0
RxD Data
Inverse Circuit
RxDi
NOTES:
1. P70 and P71 are ports for the N-channel open drain output, but
not for the CMOS output.
2. The CNT3 to CNT0 bits in the TCSPR register select no division
(n=0) or divide-by-2n (n=1 to 15).
1
Inverse
Clock
Synchronous Type
Clock
Asynchronous
Type (7 bits)
Clock
Clock
Asynchronous
Asynchronous
Type (7 bits)
Type (8 bits)
PRYE
Clock
PAR
disabled Synchronous
Type
0
STPS
1SP
0
SP
SP
UARTi Receive Register
0
0
PAR
Clock
1
Asynchronous
PAR
enabled Type
SMD2 to SMD0
1
2SP
1
Clock
Asynchronous
Type (9 bits)
Clock 1
Synchronous Type
Clock
Asynchronous
Type (8 bits)
Clock
Asynchronous
Type (9 bits)
0
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
UiRB Register
Logic Inverse Circuit + MSB/LSB Conversion Circuit
High-order bits of data bus
Low-order bits of data bus
Logic Inverse Circuit + MSB/LSB Conversion Circuit
D8
D7
D6
D5
D4
D3
D2
D1
D0
UiTB Register
Clock
Asynchronous
Type (8 bits)
PRYE
STPS
Clock
PAR
enabled Asynchronous Type
1
1
2SP
1
SP
SP
SMD2 to SMD0
Clock
Asynchronous
Type (9 bits)
1
Clock
Asynchronous
Type (9 bits)
Clock
Synchronous Type
0
1SP
0
Clock
PAR
Synchronous
disabled Type
0
0
Clock
Asynchronous
Type (7 bits)
Clock
Asynchronous
Type (8 bits)
Clock
Synchronous Type
SP: Stop bit
PAR: Parity bit
i=0 to 4
SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR: Bits in UiMR register
CLK1 to CLK0, CKPOL, CRD, CRS: Bits in UiC0 register
UiERE: Bit in UiC1 register
Figure 16.1 UARTi Block Diagram
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
1
PAR
Page 173 of 488
0 Clock
Asynchronous
Type (7 bits)
UARTi Transmit Register
Error Signal Output
disable
0
Error Signal
Output Circuit
1
Error Signal Output
enable
UiERE
IOPOL
0
1
Inverse
No inverse
TxD Data
Inverse Circuit
TxDi
16. Serial I/O
M32C/83 Group (M32C/83, M32C/83T)
UARTi Transmit Buffer Register (i=0 to 4)(1)
b15
b8 b7
b0
Symbol
Address
U0TB to U2TB 036B16-036A16, 02EB16-02EA16, 033B16-033A16
U3TB, U4TB
032B16-032A16, 02FB16-02FA16
Bit
Symbol
Indeterminate
Indeterminate
RW
Function
(b7 - b0) Transmit data (D7 to D0)
(b8)
After Reset
WO
Transmit data (D8)
WO
Nothing is assigned.
When write, set to "0".
(b15 - b9) When read, its content is indeterminate.
NOTES:
1. Use the MOV instruction to set the UiTB register.
UARTi Receive Buffer Register (i=0 to 4)
b15
b8 b7
b0
Symbol
Address
U0RB to U2RB 036F16 - 036E16, 02EF16 - 02EE16, 033F16 - 033E16
U3RB, U4RB
032F16 - 032E16, 02FF16 - 02FE16
Bit
Symbol
Bit Name
Function
Indeterminate
RW
Received data (D7 to D0)
RO
Received data (D8)
RO
(b7 - b0)
(b8)
After Reset
Indeterminate
Nothing is assigned. When write, set to "0".
(b10 - b9) When read, its content is indeterminate.
ABT
Arbitration Lost
Detect Flag(1)
OER
0: No overrun error occurs
Overrun Error Flag(2) 1: Overrun error occurs
RO
FER
Framing Error
Flag(2, 3)
0: No framing error occurs
1: Framing error occurs
RO
PER
Parity Error Flag(2, 3)
0: No parity error occurs
1: Parity error occurs
RO
SUM
Error Sum Flag(2, 3)
0: No error occurs
1: Error occurs
RO
0: Not detected (win)
1: Detected (lose)
RW
NOTES:
1. The ABT bit can be set to "0" only.
2. When the SMD2 to SMD0 bits in the UiMR register is set to "0002" (serial I/O disable) or the RE bit
in the UiC1 register is set to "0" (receive disable), the OER, FER, PER and SUM bits are set to "0"
(no error occurs).
When all OER, FER and PER bits are set to "0" (no error), the SUM bit is set to "0" (no error).
Also, the FER and PER bits are set to "0" by reading low-order bits in the UiRB register.
3. These error flags are disabled when the SMD2 to SMD0 bits in the UiMR register are set to "0012"
(clock synchronous serial I/O mode, special mode 2, or special mode 3) or to "0102" (I2C mode).
When read, the contents are indeterminate.
Figure 16.2 U0TB to U4TB Registers and U0RB to U4RB Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 174 of 488
16. Serial I/O
M32C/83 Group (M32C/83, M32C/83T)
UARTi Baud Rate Register (i=0 to 4)(1, 2, 3)
b7
Symbol
b0
Address
After Reset
U0BRG to U4BRG 036916, 02E916, 033916, 032916, 02F916
Function
Indeterminate
Setting Range
If the setting value is m, the UiBRG register
divides a count source by m+1
0016 to FF16
RW
WO
NOTES:
1. Use the MOV instruction to set the UiBRG register.
2. Set the UiBRG register data transmit and receive is stopped.
3. Set the UiBRG register after setting the CLK1 and CLK0 bits in the UiC0 register.
UARTi Transmit/Receive Mode Register (i=0 to 4)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
U0MR to U4MR
Bit
Symbol
Address
036816, 02E816, 033816, 032816, 02F816
Bit Name
Function
After Reset
0016
RW
b2 b1 b0
SMD0
SMD1
SMD2
0 0 0: Serial I/O disabled
RW
0 0 1: Clock synchronous serial I/O mode
2
Serial I/O Mode Select 0 1 0: I C mode
RW
1
0
0:
UART
mode, 7-bit transfer data
Bit
1 0 1: UART mode, 8-bit transfer data
1 1 0: UART mode, 9-bit transfer data
RW
Do not set value other than the above
CKDIR
Internal/External Clock 0 : Internal clock
Select Bit
1 : External clock
RW
STPS
Stop Bit Length Select 0 : 1 stop bit
Bit
1 : 2 stop bits
RW
PRY
Odd/Even Parity Select Enables when PRYE = 1
0 : Odd parity
Bit
1 : Even parity
RW
0 : Disables a parity
1 : Enables a parity
PRYE
Parity Enable Bit
IOPOL
TxD,RxD Input/Output 0: Not inversed
Polarity Switch Bit
1: Inverse
Figure 16.3 U0BRG to U4BRG Registers and U0MR to U4MR Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 175 of 488
RW
RW
16. Serial I/O
M32C/83 Group (M32C/83, M32C/83T)
UARTi Transmit/Receive Control Register 0 (i=0 to 4)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
U0C0 to U4C0
Bit
Symbol
Address
036C16, 02EC16, 033C16, 032C16, 02FC16
Bit Name
After Reset
0000 10002
Function
RW
b0 b1
CLK0
CLK1
CRS
0 0: Selects f1
UiBRG Count
0 1: Selects f8
(4)
Source Select Bit
1 0: Selects f2n(2)
1 1: Do not set to this value
CST/RTS Function Enabled when CRD=0
0 : Selects CTS function
Select Bit
1 : Selects RTS function
RW
RW
RW
TXEPT
Transmit Register
Empty Flag
0 : Data in the transmit register
(during transmission)
1 : No data in the transmit register
(transmission is completed)
RO
CRD
CTS/RTS Disable
Bit
0 : Enables CTS/RTS function
1 : Disables CTS/RTS function
RW
NCH
0 : TxDi/SDAi and SCLi are ports for the
Data Output Select
CMOS output
1 : TxDi/SDAi and SCLi are ports for the
Bit(1)
N-channel open drain output
RW
CKPOL
CLK Polarity
Select Bit
0 : Data is transmitted on the falling edge
of the transfer clock and data is
received on the rising edge
RW
1 : Data is transmitted on the rising edge of
the transfer clock and data is received
on the falling edge
UFORM
Transfer Format
Select Bit(3)
0 : LSB first
1 : MSB first
RW
NOTES:
1. P70/TxD2 are ports for the N-channel open drain output, but not for the CMOS output.
2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
3. The UFORM bit is enabled when the SMD2 to SMD0 bits in the UiMR register are set to "0012"
(clock synchronous serial I/O mode), or "1012" (UART mode, 8-bit transfer data).
Set this bit to "1" when the SMD2 to SMD0 bits are set to "0102" (I2C mode), and to "0" when the
SMD2 to SMD0 bits are set to "1002"(UART mode, 7-bit transfer data) or "1102"(UART mode, 9-bit
transfer data).
4. If the CLK1 and CLK0 bits are changed, set the UiBRG register.
Figure 16.4 U0C0 to U4C0 Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 176 of 488
16. Serial I/O
M32C/83 Group (M32C/83, M32C/83T)
UARTi Transmit/Receive Control Register 1 (i=0 to 4)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
U0C1 to U4C1
Bit
Symbol
Address
036D16, 02ED16, 033D16, 032D16, 02FD16
After Reset
0000 00102
Function
Bit Name
RW
0: Transmit disable
1: Transmit enable
TE
Transmit
Enable Bit
TI
Transmit Buffer 0: Data in the UiTB register
1: No data in the UiTB register
Empty Flag
RE
Receive
Enable Bit
0: Receive disable
1: Receive enable
RW
RI
Receive
Complete Flag
0: No data in the UiRB register
1: Data in the UiRB register
RO
RW
RO
UiIRS
UARTi Transmit 0: No data in the UiTB register (TI = 1)
Interrupt Cause
1: Transmission is completed (TXEPT = 1)
Select Bit
UiRRM
UARTi
Continuous
Receive Mode
Enable Bit
0: Disables continuous receive mode to be entered
RW
1: Enables continuous receive mode to be entered
UiLCH
Data Logic
Select Bit
0: Not inversed
1: Inverse
Clock-Divided
Synchronous
SCLKSTPB
Stop Bit /
/UiERE
Error Signal Output
Enable Bit(1)
RW
RW
Clock-divided synchronous stop bit (special mode 3)
0: Stops synchronizing
1: Starts synchronizing
RW
Error signal output enable bit (special mode 5)
0: Not output
1: Output
NOTES:
1. Set the SCLKSTPB/UiERE bit after setting the SMD2 to SMD0 bits in the UiMR register.
2. The UiLCH bit is enabled when the SMD2 to SMD0 bits are set to "0012" (clock synchronous serial
I/O mode), "1002"(UART mode, 7-bit transfer data), or "1012" (UART mode, 8-bit transfer data).
Set this bit to "0" when the SMD2 to SMD0 bits are set to "0102" (I2C mode) or "1102"(UART mode,
9-bit transfer data)
UARTi Special Mode Register (i=0 to 4)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
U0SMR to U4SMR
Bit
Symbol
Address
036716, 02E716, 033716, 032716, 02F716
0016
Function
Bit Name
0: Except I2C mode
1: I2C mode
IICM
I2C Mode Select Bit
ABC
Arbitration Lost Detect 0: Update per bit
Flag Control Bit
1: Update per byte
BBS
Bus Busy Flag
0: Stop condition detected
1: Start condition detected (Busy)
SCLL Sync Output
Enable Bit
0: Disabled
1: Enabled
LSYN
ABSCS
ACSE
SSS
SCLKDIV
RW
RW
RW(1)
RW
RW
Auto Clear Function Select 0: No auto clear function
Bit for Transmit Enable Bit 1: Auto clear at bus conflict
RW
Transmit Start
Condition Select Bit
0: Not related to RxDi
1: Synchronized with RxDi
RW
Clock Divide
Synchronous Bit
(Note 3)
RW
Figure 16.5 U0C1 to U4C1 Registers and U0SMR to U4SMR Registers
Page 177 of 488
RW
Bus Conflict Detect
0: Rising edge of transfer clock
Sampling Clock Select Bit 1: Timer Aj underflow(2)
NOTES:
1. The BBS bit is set to "0" by program. It is unchanged if set to "1".
2. UART0: timer A3 underflow signal, UART1: timer A4 underflow signal,
UART2: timer A0 underflow signal, UART3: timer A3 underflow signal,
UART4: timer A4 underflow signal.
3. Refer to notes for the SU1HIM bit in the UiSMR2 register.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
After Reset
16. Serial I/O
M32C/83 Group (M32C/83, M32C/83T)
UARTi Special Mode Register 2 (i=0 to 4)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
After Reset
U0SMR2 to U4SMR2
036616, 02E616, 033616, 032616, 02F616
0000 00002
Bit
Symbol
Bit Name
IICM2
I2C Mode Select Bit 2
(Note 1)
RW
CSC
Clock Synchronous Bit
0: Disabled
1: Enabled
RW
SWC
SCL Wait Output Bit
0: Disabled
1: Enabled
RW
ALS
SDA Output Stop Bit
0: Output
1: No output
RW
STC
UARTi Initialize Bit
0: Disabled
1: Enabled
RW
SWC2
SCL Wait Output Bit 2
0: Transfer clock
1: 0 output
RW
SDHI
SDA Output Inhibit Bit
0: Output
1: No output (high-impedance)
RW
External Clock
Synchronous Enable Bit
(Note 2)
RW
SU1HIM
Function
NOTES:
1. Refer to 16.3 Special mode 1 (I2C Mode).
2. The external clock synchronous function can be selected by combining the SU1HIM bit and the
SCLKDIV bit in the UiSMR register.
SCLKDIV bit in the
UiSMR Register
SU1HIM bit in the
UiSMR2 Register
0
0
0
1
1
0 or 1
Figure 16.6 U0SMR2 to U4SMR2 Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 178 of 488
External Clock Synchronous Function
Selection
No synchronization
Same division as the external clock
External clock divided by 2
RW
16. Serial I/O
M32C/83 Group (M32C/83, M32C/83T)
UARTi Special Mode Register 3 (i=0 to 4)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
After Reset
U0SMR3 to U4SMR3
036516, 02E516, 033516, 032516, 02F516
0016
Bit
Symbol
Function
RW
SS Pin Function
Enable Bit(1)
0: Disables SS pin function
1: Enables SS pin function
RW
CKPH
Clock-Phase
Set Bit
0: No clock delay
1: Clock delay
RW
DINC
Serial Input Port
Set Bit
0: Selects the TxDi and RxDi pins
(master mode)
1: Selects the STxDi and SRxDi pins
(slave mode)
RW
NODC
Clock Output
Select Bit
0: CMOS output
1: N-channel open drain output
RW
Fault Error Flag(2)
0: No error
1: Error
RW
SSE
ERR
Bit Name
b7 b6 b5
DL0
DL1
SDAi Digital Delay
Time Set Bit(3, 4)
DL2
000 : No delay
001 : 1-to-2 cycles of BRG count source
010 : 2-to-3 cycles of BRG count source
011 : 3-to-4 cycles of BRG count source
100 : 4-to-5 cycles of BRG count source
101 : 5-to-6 cycles of BRG count source
110 : 6-to-7 cycles of BRG count source
111 : 7-to-8 cycles of BRG count source
NOTES:
1. Set the SS pin after the CRD bit in the UiC0 register is set to "1" (CTS/RTS function disabled).
2. The ERR bit is set to "0" by program. It is unchanged if set to "1".
3. Digital delay is generated from a SDAi output by the DL2 to DL0 bits in I2C mode. Set these bits to
"0002" (no delay) except in the I2C mode.
4. When the external clock is selected, approximately 100ns delay is added.
Figure 16.7 U0SMR3 to U4SMR3 Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 179 of 488
RW
RW
RW
16. Serial I/O
M32C/83 Group (M32C/83, M32C/83T)
UARTi Special Mode Register 4 (i=0 to 4)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
U0SMR4 to U4SMR4
Bit
Symbol
Address
036416, 02E416, 033416, 032416, 02F416
Bit Name
After Reset
0016
Function
STAREQ
Start Condition
Generate Bit(1)
0: Clear
1: Start
RW
RSTAREQ
Restart Condition
Generate Bit(1)
0: Clear
1: Start
RW
STPREQ
Stop Condition
Generate Bit(1)
0: Clear
1: Start
RW
STSPSEL
SCL, SDA Output
Select Bit
0: Selects the serial I/O circuit
1: Selects the start/stop condition
generation circuit
RW
ACKD
ACK Data Bit
0: ACK
1: NACK
RW
ACKC
ACK Data Output
Enable Bit
0: Serial I/O data output
1: ACK data output
RW
SCLHI
SCL Output Stop
Enable Bit
0: Disabled
1: Enabled
RW
SWC9
SCL Wait Output
Bit 3
0: SCL "L" hold disabled
1: SCL "L" hold enabled
RW
NOTES:
1. When each condition is generated, the STAREQ, RSTAREQ or STPREQ bit is set to "0".
When a condition generation is incomplete, the bit remains unchanged as "1".
Figure 16.8 U0SMR4 to U4SMR4 Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
RW
Page 180 of 488
16. Serial I/O
M32C/83 Group (M32C/83, M32C/83T)
External Interrupt Request Cause Select Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
IFSR
Address
031F16
After Reset
0016
Bit
Symbol
Bit Name
IFSR0
INT0 Interrupt Polarity
Select Bit(1)
0 : One edge
1 : Both edges
RW
IFSR1
INT1 Interrupt Polarity
Select Bit(1)
0 : One edge
1 : Both edges
RW
IFSR2
INT2 Interrupt Polarity
Select Bit(1)
0 : One edge
1 : Both edges
RW
IFSR3
INT3 Interrupt Polarity
Select Bit(1)
0 : One edge
1 : Both edges
RW
IFSR4
INT4 Interrupt Polarity
Select Bit(1)
0 : One edge
1 : Both edges
RW
IFSR5
INT5 Interrupt Polarity
Select Bit(1)
0 : One edge
1 : Both edges
RW
IFSR6
IFSR7
UART0, UART3
Interrupt Cause Select
Bit
Function
0 : UART3 bus conflict, start condition
detect, stop condition detect, fault
error detect
RW
1 : UART0 bus conflict, start condition
detect, stop condition detect, fault
error detect
0 : UART4 bus conflict, start condition
detect, stop condition detect, fault
UART1, UART4
error detect
RW
Interrupt Cause Select 1 : UART1 bus conflict, start condition
detect, stop condition detect, fault
Bit
error detect
NOTES:
1.Set this bit to "0" to select level sensitive.
When setting this bit to "1", set the POL bit in the INTilC register (i = 0 to 5) to "0" (falling edge).
Figure 16.9 IFSR Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 181 of 488
RW
16. Serial I/O (Clock Synchronous Serial I/O)
M32C/83 Group (M32C/83, M32C/83T)
16.1 Clock Synchronous Serial I/O Mode
In clock synchronous serial I/O mode, data is transmitted and received with the transfer clock. Table 16.1
lists specifications of clock synchronous serial I/O mode. Table 16.2 lists registers to be used and settings.
Tables 16.3 to 16.5 list pin settings. When UARTi (i=0 to 4) operation mode is selected, the TxDi pin outputs
an "H" signal before transfer starts (the TxDi pin is in a high-impedance state when the N-channel open
drain output is selected). Figure 16.10 shows transmit and receive timings in clock synchronous serial I/O
mode.
Table 16.1 Clock Synchronous Serial I/O Mode Specifications
Item
Transfer Data Format
• Transfer data : 8 bits long
Specification
Transfer Clock
• The CKDIR bit in the UiMR register (i=0 to 4) is set to "0" (internal clock selected):
fj
2(m+1)
Transmit/Receive Control
Transmit Start Condition
fj=f1, f8, f2n(1) m :setting value of the UiBRG register 0016 to FF16.
• The CKDIR bit is set to "1" (external clock selected) : an input from the CLKi pin
_______
_______
_______ _______
• Selected from the CTS function, RTS function or CTS/RTS function disabled
• To start transmitting, the following requirements must be met(2):
- Set the TE bit in the UiC1 register to "1" (transmit enable)
- Set the TI bit in the UiC1 register to "0" (data in the UiTB register)
________
_______
- Apply an "L" signal to the CTSi pin when the CTS function is selected
Receive Start Condition
• To start receiving, the following requirements must be met(2):
- Set the RE bit in the UiC1 register to "1" (receive enable)
- Set the TE bit to "1" (transmit enable)
- Set the TI bit to "0" (data in the UiTB register)
Interrupt Request Generation Timing • Transmit interrupt timing can be selected from the followings:
- The UiIRS bit in the UiC1 register is set to "0" (no data in the transmit buffer) :
when data is transferred from the UiTB register to the UARTi transmit register (transfer started)
- The UiIRS bit is set to "1" (transmission completed) :
when a data transfer from the UARTi transmit register is completed
• Receive interrupt timing
When data is transferred from the UARTi receive register to the UiRB register (reception completed)
• Overrun error(3)
Error Detect
This error occurs when the seventh bit of the next received data is read before reading
the UiRB register
Selectable Function
• CLK polarity
Transferred data is output and input on either the rising edge or falling edge of the
transfer clock
• LSB first / MSB first
Data is transmitted or received in either bit 0 or in bit 7
• Continuous receive mode
Data can be received simultaneously by reading the UiRB register
• Serial data logic inverse
This function inverses transmitted or received data logically
NOTES:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
2. To start transmission/reception when selecting the external clock, these conditions must be met after the CKPOL
bit in the UiC0 register is set to "0" (data is transmitted on the falling edge of the transfer clock and data is received
on the rising edge) and the CLKi pin is held high ("H"), or when the CKPOL bit is set to "1" (Data is transmitted on
the rising edge of the transfer clock and data is received on the falling edge) and the CLKi pin is held low ("L").
3. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register does not change to "1"
(interrupt requested).
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 182 of 488
16. Serial I/O (Clock Synchronous Serial I/O)
M32C/83 Group (M32C/83, M32C/83T)
Table 16.2 Registers to be Used and Setting Value in Clock Synchronous Serial I/O Mode
Register
UiTB
UiRB
Bit
Function
0 to 7
Set transmit data
0 to 7
Received data can be read
OER
Overrun error flag
UiBRG
0 to 7
Set bit rate
UiMR
SMD2 to SMD0
Set to "0012"
CKDIR
Select the internal clock or external clock
UiC0
IOPOL
Set to "0"
CLK1 to CLK0
Select count source for the UiBRG register
CRS
Select CTS or RTS when using either
TXEPT
Transmit register empty flag
CRD
Enables or disables the CTS or RTS function
NCH
Select output format of the TxDi pin
_______
_______
_______
UiC1
_______
CKPOL
Select transmit clock polarity
UFORM
Select either LSB first or MSB first
TE
Set to "1" to enable data transmission and reception
TI
Transmit buffer empty flag
RE
Set to "1" to enable data reception
RI
Reception complete flag
UiIRS
Select how the UARTi transmit interrupt is generated
UiRRM
Set to "1" when using continuous receive mode
UiLCH
Set to "1" when using data logic inverse
SCLKSTPB
Set to "0"
UiSMR
UiSMR2
0 to 7
0 to 7
Set to "0016"
Set to "0016"
UiSMR3
0 to 2
Set to "0002"
UiSMR4
NODC
Select clock output format
4 to 7
Set to "00002"
0 to 7
Set to "0016"
i=0 to 4
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 183 of 488
16. Serial I/O (Clock Synchronous Serial I/O)
M32C/83 Group (M32C/83, M32C/83T)
Table 16.3 Pin Settings in Clock Synchronous Serial I/O Mode (1)
Port
Function
Setting
PS0 Register
PSL0 Register
PD6 Register
PS0_0=0
-
PD6_0=0
__________
P60
CTS0 input
__________
P61
P62
P63
RTS0 output
PS0_0=1
-
-
CLK0 input
PS0_1=0
-
PD6_1=0
CLK0 output
PS0_1=1
-
-
RxD0 input
PS0_2=0
-
PD6_2=0
TxD0 output
PS0_3=1
-
-
PS0_4=0
-
PD6_4=0
__________
P64
CTS1 input
_________
P65
RTS1 output
PS0_4=1
PSL0_4=0
-
CLK1 input
PS0_5=0
-
PD6_5=0
CLK1 output
PS0_5=1
-
-
P66
RxD1 input
PS0_6=0
-
PD6_6=0
P67
TxD1 output
PS0_7=1
-
-
Table 16.4 Pin Settings (2)
Port
Function
Setting
P70(1)
TxD2 output
P71(1)
P72
PS1 Register
PSL1 Register
PSC Register
PD7 Register
PS1_0=1
PSL1_0=0
PSC_0=0
-
RxD2 input
PS1_1=0
-
-
PD7_1=0
CLK2 input
PS1_2=0
-
-
PD7_2=0
CLK2 output
PS1_2=1
PSL1_2=0
PSC_2=0
-
PS1_3=0
-
-
PD7_3=0
PS1_3=1
PSL1_3=0
PSC_3=0
-
__________
P73
CTS2 input
__________
RTS2 output
NOTES:
1. P70 and P71 are ports for the N-channel open drain output.
Table 16.5 Pin Settings (3)
Port
Function
Setting
PS3 Register(1)
PSL3 Register
PD9 Register(1)
CLK3 input
PS3_0=0
-
PD9_0=0
CLK3 output
PS3_0=1
-
-
P91
RxD3 input
PS3_1=0
-
PD9_1=0
P92
TxD3 output
PS3_2=1
PSL3_2=0
-
PS3_3=0
PSL3_3=0
PD9_3=0
PS3_3=1
-
-
P90
__________
P93
CTS3 input
__________
RTS3 output
__________
P94
CTS4 input
PS3_4=0
PSL3_4=0
PD9_4=0
RTS4 output
PS3_4=1
-
-
CLK4 input
PS3_5=0
PSL3_5=0
PD9_5=0
CLK4 output
PS3_5=1
-
-
P96
TxD4 output
PS3_6=1
-
-
P97
RxD4 input
PS3_7=0
-
PD9_7=0
__________
P95
NOTES:
1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do
not generate an interrupt or a DMA transfer between the instruction to set the PRC2 bit to "1" and the instruction to
set the PD9 and PS3 registers.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 184 of 488
16. Serial I/O (Clock Synchronous Serial I/O)
M32C/83 Group (M32C/83, M32C/83T)
(1) Transmit Timing (Internal clock selected)
Tc
Transfer Clock
TE bit in UiC1
register
TI bit in UiC1
register
"1"
"0"
Data is set in the UiTB register
"1"
"0"
Data is transferred from the UiTB register to the UARTi transmit register
"H"
CTSi
TCLK
"L"
Pulse stops because CTSi = H
Pulse stops because TE bit = 0
CLKi
TxDi
D0 D 1 D2 D3 D4 D5 D6 D7
TXEPT bit in
UiC0 register
"1"
IR bit in SiTIC
register
"1"
D0 D 1 D2 D3 D4 D5 D 6 D7
D 0 D1 D2 D 3 D 4 D 5 D6 D7
"0"
"0"
Set to "0" by an interrupt request acknowledgement or by program
The above applies to the following settings:
TC=2(m+1)/fj
• The CKDIR bit in the UiMR register is set to "0" (internal clock selected)
fj : Count source frequency set in the UiBRG register (f1, f8, f2n(1))
• The CRD bit in the UiC0 register is set to "0" (RTS/CTS function enabled)
m : Setting value of the UiBRG register
The CRS bit is set to "0" (CTS function selected)
i = 0 to 4
• The CKPOL bit the in UiC0 register is set to "0" (data transmitted on the
NOTES:
falling edge of the transfer clock)
1. The CNT3 to CNT0 bits in the TCSPR register select no division (
• The UiIRS bit in the UiC1 register is set to "0" (no data in the UiTB register)
n=0) or divide-by-2n (n=1 to 15).
(2) Receive Timing (External clock selected)
RE bit in UiC1
register
"1"
TE bit in UiC1
register
"1"
TI bit in UiC1
register
"1"
"0"
Dummy data is set in the UiTB register
"0"
"0"
Data is transferred from the UiTB register to the UARTi transmit register
RTSi
"H"
"L"
1 / fEXT
Becomes "L" when the UiRB register is read
CLKi
Received data is taken in
RxDi
D0
D1
D2
D3
D4
D 5 D6 D7
Data transferred from UARTi register to UiRB register
RI bit in UiC1
register
"1"
IR bit in SiRIC
register
"1"
OER bit in UiRB
register
"1"
D 0 D1 D2 D3 D 4 D 5 D6
D7
D0 D1 D2 D 3 D4 D 5 D6
Read by the UiRB register
"0"
"0"
Set to "0" by an interrupt request acknowledgement or by program
"0"
The above applies to the following settings:
• The CKDIR bit in the UiMR register is set to "1" (external clock selected)
• The CRD bit in the UiC0 register is set to "0" (RTS/CTS function enabled)
The CRS bit is set to "1" (RTS function selected)
• The CKPOL bit in the UiC0 register is set to "0"
(Data is received on the rising edge of the transfer clock)
fEXT: External clock frequency
i=0 to 4
Figure 16.10 Transmit and Receive Operation
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 185 of 488
Meet the following conditions while "H" is applied to the CLKi
pin before receiving data:
• Set the TE bit in the UiC1 register to "1" (transmit enable)
• Set the RE bit in the UiC1 register to "1" (receive enable)
• Write dummy data to the UiTB register
16. Serial I/O (Clock Synchronous Serial I/O)
M32C/83 Group (M32C/83, M32C/83T)
16.1.1 Selecting CLK Polarity
As shown in Figure 16.11, the CKPOL bit in the UiC0 register (i=0 to 4) determines the polarity of the
transfer clock.
(1) When the CKPOL bit in the UiC0 register (i=0 to 4) is set to "0"
(Data is transmitted on the falling edge of the transfer clock and data is received on the rising edge)
CLKi
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
NOTES:
1. The CLKi pin is held high ("H") when no data is transferred.
2. The above applies when the UFORM bit in the UiC0 register is set to "0" (LSB first)
and the UiLCH bit in the UiC1 register is set to "0" (not inversed).
(2) When the CKPOL bit in the UiC0 register is set to "1"
(Data is transmitted on the rising edge of the transfer clock and data is received on the falling edge)
CLKi
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
NOTES:
3. The CLKi pin is held low ("L") when no data is transferred.
4. The above applies when the UFORM bit in the UiC0 register is set to "0" (LSB first)
and the UiLCH bit in the UiC1 register is set to "0" (not inversed).
Figure 16.11 Transfer Clock Polarity
16.1.2 Selecting LSB First or MSB First
As shown in Figure 16.12, the UFORM bit in the UiC0 register (i=0 to 4) determines a data transfer format.
(1) When the UFORM bit in the UiC0 register (i=0 to 4) is set to "0"
(LSB first)
CLKi
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
NOTES:
1. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is
transmitted on the falling edge of the transfer clock and received on the rising
edge) and the UiLCH bit in the UiC1 register is set to "0" (not inversed).
(2) When the UFORM bit in the UiC0 register is set to "1" (MSB first)
CLKi
TXDi
D7
D6
D5
D4
D3
D2
D1
D0
RXDi
D7
D6
D5
D4
D3
D2
D1
D0
NOTES:
2. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is
transmitted on the falling edge of the transfer clock and received on the rising
edge) and the UiLCH bit in the UiC1 register is set to "0" (not inversed).
Figure 16.12 Transfer Format
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 186 of 488
16. Serial I/O (Clock Synchronous Serial I/O)
M32C/83 Group (M32C/83, M32C/83T)
16.1.3 Continuous Receive Mode
When the UiRRM bit in the UiC1 register (i=0 to 4) is set to "1" (continuous receive mode), the TI bit is set
to "0" (data in the UiTB register) by reading the UiRB register. When the UiRRM bit is set to "1", do not set
dummy data in the UiTB register by program.
16.1.4 Serial Data Logic Inverse
When the UiLCH bit in the UiC1 register is set to "1" (inverse), data logic written in the UiTB register is
inversed when transmitted. The inversed receive data logic can be read by reading the UiRB register.
Figure 16.13 shows a switching example of the serial data logic.
(1) When the UiLCH bit in the UiC1 register (i=0 to 4) is set to "0" (not inversed)
Transfer clock
"H"
"L"
TxDi
"H"
(no inverse) "L"
D0
D1
D2
D3
D4
D5
D6
D7
(2) When the UiLCH bit in the UiC1 register is set to "1" (inverse)
Transfer clock
"H"
"L"
TxDi
"H"
(inverse) "L"
D0
D1
D2
D3
D4
D5
D6
D7
NOTES:
1. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is transmitted on
the falling edge) and the UFORM bit in the UiC register is set to "0" (LSB first).
Figure 16.13 Serial Data Logic Inverse
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 187 of 488
M32C/83 Group (M32C/83, M32C/83T)
16. Serial I/O (UART)
16.2 Clock Asynchronous Serial I/O (UART) Mode
In UART mode, data is transmitted and received after setting a desired bit rate and data transfer format.
Table 16.6 lists specifications of UART mode.
Table 16.6 UART Mode Specifications
Item
Transfer Data Format
Specification
• Character bit (transfer data ) : selected from 7 bits, 8 bits, or 9 bits long
• Start bit: 1 bit long
• Parity bit: selected from odd, even, or none
• Stop bit: selected from 1 bit or 2 bits long
• The CKDIR bit in the UiMR register is set to "0" (internal clock selected) :
Transfer Clock
fj/16(m+1) fj = f1, f8, f2n(1) m: setting value of the UiBRG register 0016 to FF16
• The CKDIR bit is set to "1" (external clock selected) :
fEXT/16(m+1)
fEXT: clock applied to the CLKi pin
_______
_______
_______ _______
Transmit/Receive Control • Select from CTS function, RTS function or CTS/RTS function disabled
Transmit Start Condition
• To start transmitting, the following requirements must be met:
- Set the TE bit in the UiC1 register to "1" (transmit enable)
- Set the TI bit in the UiC1 register to "0" (data in the UiTB register)
_______
_______
- Apply an "L" signal to the CTSi pin when the CTS function is selected
Receive Start Condition
Interrupt Request
Generation Timing
• To start receiving, the following requirements must be met:
- Set the RE bit in the UiC1 register to "1" (receive enable)
- The start bit is detected
• Transmit interrupt timing can be selected from the followings:
- The UiIRS bit in the UiC1 register is set to "0" (no data in the transmit buffer) :
when data is transferred from the UiTB register to the UARTi transmit register (transfer started)
- The UiIRS bit is set to "1" (transmission completed) :
when data transmission from the UARTi transfer register is completed
• Receive interrupt timing
Error Detect
when data is transferred from the UARTi receive register to the UiRB register (reception completed)
• Overrun error(2)
This error occurs when the bit before the last stop bit of the next received data is read
prior to reading the UiRB register (the first stop bit when selecting 2 stop bits)
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
When parity is enabled, this error occurs when the number of "1" in parity and character
bits does not match the number of "1" set
• Error sum flag
Selectable Function
This flag is set to "1" when any of an overrun, framing or parity errors occur
• LSB first / MSB first
Data is transmitted or received in either bit 0 or in bit 7
•Serial data logic inverse
Logic values of data to be transmitted or received data are inversed. The start bit and
stop bit are not inversed
•TxD, RxD I/O polarity switching
TxD pin output and RxD pin input are inversed
NOTES:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
2. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register remains unchanged
as "1" (interrupt requested).
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 188 of 488
16. Serial I/O (UART)
M32C/83 Group (M32C/83, M32C/83T)
Table 16.7 lists registers to be used and settings. Tables 16.8 to 16.10 list pin settings. When UARTi (i=0
to 4) operation mode is selected, the TxDi pin outputs an "H" signal before transfer is started (the TxDi pin
is in a high-impedance state when the N-channel open drain output is selected). Figure 16.14 shows an
example of a transmit operation in UART mode. Figure 16.15 shows an example of a receive operation in
UART mode.
Table 16.7 Registers to be Used and Settings in UART
Register
Bit
Function
UiTB
0 to 8
Set transmit data(1)
UiRB
0 to 8
Received data can be read(1)
OER, FER,
Error flags
PER, SUM
UiBRG
0 to 7
Set bit rate
UiMR
SMD2 to SMD0
Set to "1002" when transfer data is 7 bits long
Set to "1012" when transfer data is 8 bits long
Set to "1102" when transfer data is 9 bits long
CKDIR
UiC0
Select the internal clock or external clock
STPS
Select stop bit length
PRY, PRYE
Select parity enable or disable, odd or even
IOPOL
Select TxD / RxD I/O polarity
CLK0, CLK1
Select count source for the UiBRG register
CRS
Select either CTS or RTS when using either
TXEPT
Transfer register empty flag
CRD
Enables or disables the CTS or RTS function
NCH
Select output format of the TxDi pin
_______
_______
________
_______
CKPOL
Set to "0"
UFORM
Select the LSB first or MSB first when a transfer data is 8 bits long
Set to "0" when transfer data is 7 bits or 9 bits long
UiC1
TE
Set to "1" to enable data transmission
TI
Transfer buffer empty flag
RE
Set to "1" to enable data reception
RI
Reception complete flag
UiIRS
Select how the UARTi transmit interrupt is generated
UiRRM
Set to "0"
UiLCH
Select whether or not data logic is inversed when transfer data length is 7 or
UiERE
Set to either "0" or "1"
UiSMR
0 to 7
Set to "0016"
UiSMR2
0 to 7
Set to "0016"
UiSMR3
0 to 7
Set to "0016"
UiSMR4
0 to 7
Set to "0016"
8 bits. Set to "0" when transfer data length is 9 bits.
NOTES:
1. Use bits 0 to 6 when transfer data is 7 bits long, bits 0 to 7 when 8 bits long, bits 0 to 8 when 9 bits long.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 189 of 488
16. Serial I/O (UART)
M32C/83 Group (M32C/83, M32C/83T)
Table 16.8 Pin Settings in UART (1)
Port
Function
Setting
PS0 Register
PSL0 Register
PD6 Register
PS0_0=0
–
PD6_0=0
__________
P60
CTS0 input
__________
RTS0 output
PS0_0=1
–
–
P61
CLK0 input
PS0_1=0
–
PD6_1=0
P62
RxD0 input
PS0_2=0
–
PD6_2=0
P63
TxD0 output
PS0_3=1
–
–
__________
P64
CTS1 input
PS0_4=0
–
PD6_4=0
RTS1 output
PS0_4=1
PSL0_4=0
–
P65
CLK1 input
PS0_5=0
–
PD6_5=0
P66
RxD1 input
PS0_6=0
–
PD6_6=0
P67
TxD1 output
PS0_7=1
–
–
__________
Table 16.9 Pin Settings (2)
Port
Function
Setting
PS1 Register
PSL1 Register
PSC Register
PD7 Register
PS1_0=1
PSL1_0=0
PSC_0=0
–
RxD2 input
PS1_1=0
–
–
PD7_1=0
CLK2 input
PS1_2=0
–
–
PD7_2=0
PS1_3=0
–
–
PD7_3=0
PS1_3=1
PSL1_3=0
PSC_3=0
–
P70(1)
TxD2 output
P71(1)
P72
__________
P73
CTS2 input
__________
RTS2 output
NOTES:
1. P70 and P71 are ports for the N-channel open drain output.
Table 16.10 Pin Settings (3)
Port
Function
Setting
PS3
Register(1)
PSL3 Register
PD9 Register(1)
P90
CLK3 input
PS3_0=0
–
PD9_0=0
P91
RxD3 input
PS3_1=0
–
PD9_1=0
P92
TxD3 output
PS3_2=1
PSL3_2=0
–
PS3_3=0
PSL3_3=0
PD9_3=0
PS3_3=1
–
–
__________
P93
CTS3 input
__________
RTS3 output
__________
P94
CTS4 input
PS3_4=0
PSL3_4=0
PD9_4=0
RTS4 output
PS3_4=1
–
–
P95
CLK4 input
PS3_5=0
PSL3_5=0
PD9_5=0
P96
TxD4 output
PS3_6=1
–
–
P97
RxD4 input
PS3_7=0
–
PD9_7=0
__________
NOTES:
1. Set the PD9 and PS3 registers set immediately after the PRC2 bit in the PRCR register is set to "1" (write enable).
Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the
instruction to set the PD9 and PS3 registers.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 190 of 488
16. Serial I/O (UART)
M32C/83 Group (M32C/83, M32C/83T)
(1) 8-bit Data Transmit Timing (with a parity and 1 stop bit)
Tc
The transfer clock stops momentarily, because an "H" signal is applied to the CTS pin,
when the stop bit state is verified.
The transfer clock resumes running as soon as an "L" signal is applied to the CTS pin
Transfer Clock
TE bit in UiC1
register
"1"
TI bit in UiC1
register
"1"
"0"
Data is set in the UiTB register
"0"
Data is transferred from the UiTB register to the UARTi transmit register
"H"
CTSi
"L"
Parity
bit
Start
bit
ST D0 D1 D2 D3 D4 D5 D6 D7
TxDi
P
Stop
bit
Pulse stops because the TE bit is set to "0"
ST D0 D1 D2 D3 D4 D5 D6 D7
SP
P
ST D0 D1
SP
TXEPT bit in UiC0 "1"
register
"0"
IR bit in SiTIC
register
"1"
"0"
Set to "0" by an interrupt request acknowledgement or by program
i=0 to 4
The above timing applies under the following conditions:
• The PRYE bit in the UiMR register is set to "1" (parity enabled)
• The STPS bit in the UiMR register is set to "0" (1 stop bit)
• The CRD bit in the UiC0 register is set to "0" and the CRS bit is set
to "0" (CTS function selected)
• The UilRS bit in the UiC1 register is set to "1"
(transmission completed)
Tc = 16 (m + 1) / fj or 16 (m + 1) / fEXT
fj: count source frequency set in the UiBRG register (f1, f8, f2n(1))
fEXT: count source frequency set in the UiBRG register (external
clock)
m: setting value of the UiBRG register
NOTE:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0)
or divide-by-2n (n=1 to 15).
(2) 9-bit Data Transmit Timing (with no parity and 2 stop bits)
Tc
Transfer Clock
TE bit in UiC1
register
TI bit in UiC1
register
"1"
Data is set in the UiTB register
"0"
"1"
"0"
Data is transferred from the UiTB register to the UARTi transmit register
Stop
Stop
bit
bit
Start
bit
TxDi
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
ST D0 D1 D2 D3 D4 D5 D6 D7 D8
SP SP
ST D0 D1
"1"
TXEPT bit in UiC0
register
"0"
IR bit in SiTIC
register
"1"
"0"
Set to "0" by an interrupt request acknowledgement or by program
i=0 to 4
The above timing applies under the following conditions:
• The PRYE bit in the UiMR register is set to "0" (parity disabled)
• The STPS bit in the UiMR register is set to "1" (2 stop bits)
• The CRD bit in the UiC0 register is set to "1" (CTS function
disabled)
• The UilRS bit in the UiC1 register is set to "0" (no data in the
transmit buffer)
Figure 16.14 Transmit Operation
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 191 of 488
Tc = 16 (m + 1) / fj or 16 (m + 1) / fEXT
fj: count source frequency set in the UiBRG register (f1, f8, f2n(1))
fEXT: count source frequency set in the UiBRG register (external
clock)
m: setting value of the UiBRG register
NOTE:
1. The CNT3 to CNT0 bits in the TCSPR register select no division
(n=0) or divide-by-2n (n=1 to 15).
16. Serial I/O (UART)
M32C/83 Group (M32C/83, M32C/83T)
8-bit Data Reception Timing (with no parity and 1 stop bit)
Count Source set
in UiBRG register
RE bit in UiC1
register
"1"
"0"
Stop bit
Start bit
RxDi
D1
D0
Determine if it
is "L"
D7
Capture a received data
Transfer Clock
Data is transferred from the URTi receive
Start receiving when the transfer clock is
"1" generated on the falling edge of the start bit register to the UiRB register
RI bit in UiC1
register
"0"
"H"
"L"
RTSi
IR bit in SiRIC
register
Change to "L" by reading the UiRB register
"1"
"0"
Set to "0" by an interrupt request acknowledgement or by program
i=0 to 4
NOTES:
1. The above applies when the PRYE bit in the UiMR register is set to "0" (parity disabled),
the SRPS bit in the UiMR register is set to "0" (1 stop bit) and the CRS bit in the UiC0 register is set
to "1" (RTS function selected).
Figure 16.15 Receive Operation
16.2.1 Bit Rate
In UART mode, bit rate is clock frequency which is divided by a setting value of the UiBRG (i=0 to 4)
register and again divided by 16. Table 16.11 lists an example of bit rate setting.
Table 16.11 Bit Rate
Bit Rate
(bps)
Count
Source
of
UiBRG
Peripheral Function Clock:
16MHz
Setting Value
of UiBRG: n
Actual Bit Rate
(bps)
Peripheral Function Clock:
24MHz
Setting Value
of UiBRG: n
Actual Bit Rate
(bps)
Peripheral Function Clock:
32MHz
Setting Value
of UiBRG: n
Actual Bit Rate
(bps)
1200
f8
103 (67h)
1202
155 (96h)
1202
207 (CFh)
1202
2400
f8
51 (33h)
2404
77 (46h)
2404
103 (67h)
2404
4800
f8
25 (19h)
4808
38 (26h)
4808
51 (33h)
4808
9600
f1
103 (67h)
9615
155 (96h)
9615
207 (CFh)
9615
14400
f1
68 (44h)
14493
103 (67h)
14423
138 (8Ah)
14388
19200
f1
51 (33h)
19231
77 (46h)
19231
103 (67h)
19231
28800
f1
34 (22h)
28571
51 (33h)
28846
68 (44h)
28986
31250
f1
31 (1Fh)
31250
47 (2Fh)
31250
63 (3Fh)
31250
38400
f1
25 (19h)
38462
38 (26h)
38462
51 (33h)
38462
51200
f1
19 (13h)
50000
28 (1Ch)
51724
38 (26h)
51282
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 192 of 488
16. Serial I/O (UART)
M32C/83 Group (M32C/83, M32C/83T)
16.2.2 Selecting LSB First or MSB First
As shown in Figure 16.16, the UFORM bit in the UiC0 register (i=0 to 4) determines data transfer format.
This function is available for 8-bit transfer data.
(1) When the UFORM Bit in the UiC0 Register (i=0 to 4) is set to "0" (LSB first)
CLKi
TxDi
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
RxDi
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
(2) When the UFORM Bit in the UiC0 Register is set to "1" (MSB first)
CLKi
TxDi
ST
D7
D6
D5
D4
D3
D2
D1
D0
P
SP
RxDi
ST
D7
D6
D5
D4
D3
D2
D1
D0
P
SP
NOTES:
1. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is
transmitted on the falling edge of the transfer clock and received on the rising edge)
and the UiLCH bit in the UiC1 register is set to "0" (no inverse).
ST : Start bit
P : Parity bit
SP : Stop bit
Figure 16.16 Transfer Format
16.2.3 Serial Data Logic Inverse
After the UiLCH bit in the UiC1 register is set to "1", data logic is inversed when writing to the UiTB register
(i=0 to 4) and reading from the UiRB register. Figure 16.17 shows a switching example of the serial data
logic.
(1) When the UiLCH bit in the UiC1 register (i=0 to 4) = 0 (no inverse)
Transfer Clock
“H”
“L”
TxDi
“H”
(no inverse)
“L”
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
D5
D6
D7
P
SP
(2) When the UiLCH bit in the UiC1 register = 1 (inverse)
Transfer Clock
“H”
“L”
TxDi
“H”
(inverse) “L”
ST
D0
D1
D2
D3
D4
NOTES:
1. The above applies to when the UFORM bit in the UiC0 register is set to "0" (LSB first),
the STPS bit in the UiMR bit is set to "0" (1 stop bit) and the PRYE bit is set to "1" (parity enabled).
Figure 16.17 Serial Data Logic Inverse
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 193 of 488
16. Serial I/O (UART)
M32C/83 Group (M32C/83, M32C/83T)
16.2.4 TxD and RxD I/O Polarity Inverse
TxD pin output and RxD pin input are inversed. All I/O data level, including the start bit, stop bit and parity
bit, are inversed. Figure 16.18 shows TxD and RxD I/O polarity inverse.
(1) When the IOPOL bit in the UiMR register (i=0 to 4) is set to "0" (no inverse)
Transfer Clock
“H”
“L”
TxDi “H”
(no inverse) “L”
RxDi
“H”
(no inverse) “L”
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
(2) When the IOPOL bit in the UiMR register is set to "1" ( inverse)
Transfer Clock
TxDi
“H”
“L”
“H”
(inverse) “L”
RxDi
“H”
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
(inverse) “L”
NOTES:
1. The above applies when the UFORM bit in the UiC0 register is set to "0" (LSB
first), the STPS bit in the UiMR bit is set to "0" (1 stop bit) and the PRYE bit is set
to "1" (parity enabled).
Figure 16.18 TxD, RxD I/O Polarity Inverse
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 194 of 488
ST : Start bit
P : Even parity
SP : Stop bit
16. Serial I/O (Special Function)
M32C/83 Group (M32C/83, M32C/83T)
16.3 Special Mode 1 (I2C Mode)
I2C mode is a mode to communicate with external devices with a simplified I2C . Table 16.12 lists specifications of I2C mode. Table 16.13 lists registers to be used and settings, Table 16.14 lists each function.
Figure 16.19 shows a block diagram of I2C mode. Figure 16.20 shows timings for transfer to the UiRB
register and interrupts. Tables 16.14 to 16.16 list pin settings.
As shown in Table 16.14, I2C mode is entered when the SMD2 to SMD0 bits in the UiMR register is set to
"0102" and the IICM bit in the UiMR register is set to "1". SDAi output changes after SCLi becomes low ("L")
and stabilizes due to a SDAi output via the delay circuit.
Table 16.12 I2C Mode Specifications
Item
Interrupt
Specifications
Start condition detect, stop condition detect, no acknowledgment detect, acknowledgment
detect
Selectable Function
• Arbitration lost
The update timing of the ABT bit in the UiRB register can be selected.
Refer to 16.3.3 Arbitration.
• SDAi digital delay
Selected from no digital delay or 2 to 8 cycle delay of the count source of BRG.
Refer to 16.3.5 SDA Output.
• Clock phase setting
Selected from clock delay or no clock delay.
Refer to 16.3.4 Transfer Clock.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 195 of 488
16. Serial I/O (Special Function)
M32C/83 Group (M32C/83, M32C/83T)
(Note1)
SDAi
Timer
To DMAi
I/O
UARTi
IICM=0 or IICM2=1
IICM 1
Delay Circuit
0
SDHI
D
IICM=1 and
IICM2=0
To DMAi
Arbitration
T
Noise
Filter
UARTi
ALS
Q
1
0
IICM=0 or
IICM2=1
IICM
Receive Register
UARTi
S
R
Detects Stop Condition
Falling edge
detect
SCLi
Bus
busy
NACK
D Q
T
LSYN bit
D Q
T
R
I/O
Data Register
ACK
9th Pulse
Internal Clock
UARTi
IICM=1
1 IICM
Noise
Filter
Q
Bus Conflict
SWC2 CLK
Detect
Control
UARTi
External Clock
1
0
IICM
0
Noise
Filter
R
S
Falling Edge of 9th Pulse
SWC
Port reading
(Note 1)
UARTi
IICM=0
I/0
CLKi
Timer
i=0 to 4
NOTES:
1. Set the PSj (j=0,1,3), PSLj or PSC register to determine.
IICM : Bit in the UiSMR register
IICM2 : Bit in the UiSMR2 register
Figure 16.19 I2C Mode Block Diagram
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 196 of 488
UARTi Reception
ACK Interrupt Request
DMAi Request
IICM=1 and
IICM2=0
Detects Start Condition
(Note 1)
UARTi Transmission
NACK Interrupt
Request
Transmit Register
* When the IICM bit is set to "1", port pin can be read
regardless of the direction register being set to "1".
Bus Conflict
Start Condition Detect
Stop Condition Detect
Interrupt Request
16. Serial I/O (Special Function)
M32C/83 Group (M32C/83, M32C/83T)
Table 16.13 Registers To Be Used and Settings (I2C Mode)
Register
Bit
Function
Master
UiTB
UiRB
UiBRG
UiMR
UiC0
UiC1
UiSMR
UiSMR2
UiSMR3
UiSMR4
IFSR
i=0 to 4
Slave
0 to 7
0 to 7
8
ABT
OER
0 to 7
SMD2 to SMD0
CKDIR
IOPOL
CLK1 to CLK0
CRS
TXEPT
CRD, NCH
CKPOL
UFORM
TE
TI
RE
RI
UiRRM, UiLCH,
UiERE
IICM
ABC
BBS
3 to 7
IICM2
CSC
SWC
Set transmit data
Received data can be read
ACK or NACK bit can be read
Arbitration lost detect flag
Overrun error flag
Set bit rate
Set to "0102"
Set to "0"
Set to "0"
Select count source of the UiBRG register
Disabled because CRD = 1
Transfer register empty flag
Set to "1"
Set to "0"
Set to "1"
Set to "1" to enable data transmission
Transfer buffer empty flag
Set to "1" to enable data reception
Reception complete flag
Set to "0"
STSPSEL
ACKD
ACKC
SCLHI
Set to "1" when using a condition generating function
Select ACK or NACK
Set to "1" to output ACK data
Set to "1" to enable SCL output stop when
Not used. Set to "0"
SWC9
detecting stop condition
Not used. Set to "0"
IFSR6, IFSR7
Set to "1"
Disabled
Disabled
Set to "1"
Disabled
Set to "1"
Select an arbitration lost detect timing
Disabled
Bus busy flag
Set to "000002"
See Table 16.14
Set to "1" to enable clock synchronization
Set to "0"
Set to "1" to output fixed "L" from the SDAi on the falling edge of the ninth bit of
the transfer clock
ALS
Set to "1" to terminate SDA output when
Not used. Set to "0"
detecting the arbitration lost
STC
Not used. Set to "0"
Set to "1" to reset UARTi
by detecting a start condition
SWC2
Set to "1" to forcibly output an "L" signal from SCL
SDHI
Set to "1" to disable SDA output
SU1HIM
Set to "0"
SSE
Set to "0"
CKPH
See Table 16.14.
DINC, NODC, ERR Set to "0"
DL2 to DL0
Set digital delay value
STAREQ
Set to "1" when generating start condition
Not used. Set to "0"
RSTAREQ
Set to "1" when generating restart condition
STPREQ
Set to "1" when generating stop condition
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 197 of 488
Set to "1" to output fixed "L" from SCLi
on the falling edge of the ninth bit of
the transfer clock
16. Serial I/O (Special Function)
M32C/83 Group (M32C/83, M32C/83T)
Table 16.14 I2C Mode Functions
I2C Mode (SMD2 to SMD0=0102, IICM=1)
Function
Clock Synchronous
Serial I/O Mode
(SMD2 to SMD0=0012,
IICM=0)
IICM2=0
(NACK/ACK interrupt)
IICM2=1
(UART transmit / UART receive interrupt)
CKPH=0
(No clock delay)
CKPH=0
(No clock delay)
CKPH=1
(Clock delay)
CKPH=1
(Clock delay)
Interrupt Numbers 39 to
41 Generated(1)
(See Figure 16.20)
-
Start condition or stop condition detect (See Table 16.17)
Interrupt Number 17, 19,
33, 35 and 37
Generated(1)
(See Figure 16.20)
UARTi Transmission Transmission started or
completed (selected by
the UiIRS register)
No Acknowlegement Detect
(NACK) Rising edge of 9th bit of SCLi
Interrupt Numbers 18, 20,
34, 36 and 38
Generated(1)
(See Figure 16.20)
UARTi Reception Receiving at 8th bit
CKPOL=0(rising edge)
CKPOL=1(falling edge)
Acknowlegement Detect (ACK) - UARTi Reception Rising edge of 9th bit of SCLi
Falling edge of 9th bit of SCLi
Data Transfer Timing from
the UART Receive Shift
Register to the UiRB Register
CKPOL=0(rising edge)
CKPOL=1(falling edge)
Rising edge of 9th bit of SCLi
UARTi Transmit Output
Delay
No delay
Delay
P63, P67, P70, P92, P96
Pin Functions
TxDi output
SDAi input and output
P62, P66, P71, P91, P97
Pin Functions
RxDi input
SCLi input and output
P61, P65, P72, P90, P95
Pin Functions
Select CLKi input or
output
– (Not used in I2C mode)
Noise Filter Width
15ns
200ns
Reading RxDi and SCLi
Pin Levels
Can be read if port
direction bit is set to "0"
Can be read regardless of the port direction bit
Default Value of TxDi,
SDAi Output
CKPOL=0 (H)
CKPOL=1 (L)
Values set in the port register before entering I2C mode(2)
SCLi Default and End
Value
–
H
DMA Generated
(See Figure 16.20)
UARTi reception
Acknowlegement detect
(ACK)
Store Received Data
1st to 8th bits of the
received data are stored
into bits 0 to 7 in the
UiRB register
1st to 8th bits of the received
data are stored into bits 7 to 0
in the UiRB register
Reading Received Data
The UiRB register status is read
L
UARTi
Transmission Rising edge of
9th bit of SCLi
Falling edge of
9th bit of SCLi
H
UARTi Transmission Next falling edge after the
9th bit of SCLi
Falling edge and rising edge
of 9th bit of SCLi
L
UARTi Reception Falling edge of 9 bit of SCLi
1st to 7th bits of the received data are stored
into bits 6 to 0 in the UiRB register. 8th bit is
stored into bit 8 in the UiRB register.
1st to 8th bits are stored into
bits 7 to 0 in the UiRB register(3)
Bits 6 to 0 in the UiRB
registerts(4) are read as bit 7
to 1. Bit 8 in the UiRB
register is read as bit 0
i=0 to 4
NOTES:
1. Follow the procedures below to change how an interrupt is generated.
(a) Disable interrupt of corresponding interrupt number.
(b) Change how an interrupt is generated.
(c) Set the IR bit of a corresponding interrupt number to "0" (no interrupt requested).
(d) Set the ILVL2 to ILVL0 bits of a corresponding interrupt number.
2. Set default value of the SDAi output when the SMD2 to SMD0 bits in the UiMR register are set to "0002"
(serial I/O disabled).
3. Second data transfer to the UiRB register (on the rising edge of the ninth bit of SCLi).
4. First data transfer to the UiRB register (on the falling edge of the ninth bit of SCLi).
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 198 of 488
16. Serial I/O (Special Function)
M32C/83 Group (M32C/83, M32C/83T)
(1) When the IICM2 bit is set to "0" (ACK or NACK interrupt) and the CKPH bit is set to "0" (No clock delay)
1st
bit
2nd
bit
3rd
bit
4th
bit
5th
bit
6th
bit
7th
bit
8th
bit
9th
bit
SCLi
SDAi
D7
D6
D5
D4
D3
D2
D1
D0
D8 (ACK or NACK)
ACK interrupt (DMA
request) or NACK interrupt
b15
Data is transferred to the UiRB register
b9
b8
b7
b0
D8 D7 D 6 D 5 D4 D3 D2 D1 D 0
•••
Contents of the UiRB register
(2) When IICM2 is set to "0" and CKPH is set to "1" (clock delay)
1st
bit
2nd
bit
3rd
bit
4th
bit
5th
bit
6th
bit
7th
bit
8th
bit
9th
bit
SCLi
SDAi
D7
D6
D5
D4
D3
D2
D1
D0
D8 (ACK or NACK)
ACK interrupt (DMA
request) or NACK interrupt
b9
b15
Data is transferred to the UiRB register
•••
b8
b7
b0
D8 D7 D6 D 5 D 4 D3 D2 D1 D0
Contents of the UiRB register
(3) When IICM2 is set to "1" (UART transmit or receive interrupt) and CKPH is set to "0"
1st
bit
2nd
bit
3rd
bit
4th
bit
5th
bit
6th
bit
7th
bit
8th
bit
9th
bit
SCLi
SDAi
D7
D6
D5
D4
D3
D2
D1
D8 (ACK or NACK)
D0
Receive interrupt
(DMA request)
Transmit interrupt
b15
Data is transferred to the UiRB register
b9
2nd
bit
3rd
bit
4th
bit
5th
bit
6th
bit
b7
b0
D 7 D6 D5 D4 D 3 D 2 D 1
Contents of the UiRB register
(4) When IICM2 is set to "1" and CKPH is set to "1"
1st
bit
b8
D0
•••
7th
bit
8th
bit
9th
bit
SCLi
SDAi
D7
D6
D5
D4
D3
D2
D1
D0
D8 (ACK or NACK)
Receive interrupt
(DMA request)
Data is transferred to the UiRB register.
b15
b9
•••
b8
D0
b7
b0
D7 D 6 D 5 D 4 D 3 D 2 D 1
Transmit interrupt
Data is transferred to the UiRB register.
b15
b9
•••
Contents of the UiRB register
i=0 to 4
IICM2 : Bit in the UiSMR2 register
CKPH : Bit in the UiSMR3 regiser
b8
b7
b0
D 8 D7 D6 D5 D 4 D 3 D2 D 1 D0
Contents of the UiRB register
The above timing applies to the following setting :
• CKDIR bit in the UiMR register = 1 (select slave)
Figure 16.20 UiRB Register Transfer and Interrupt Timings
Table 16.15 Pin Settings in I2C Mode (1)
Port
Function
Setting
PSL0 Register
PS0 Register
P62
P63
P66
P67
PD6 Register
SCL0 output
PS0_2=1
PSL0_2=0
-
SCL0 input
PS0_2=0
-
PD6_2=0
SDA0 output
PS0_3=1
-
-
SDA0 input
PS0_3=0
-
PD6_3=0
SCL1 output
PS0_6=1
PSL0_6=0
-
SCL1 input
PS0_6=0
-
PD6_6=0
SDA1 output
PS0_7=1
-
-
SDA1 input
PS0_7=0
-
PD6_7=0
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 199 of 488
16. Serial I/O (Special Function)
M32C/83 Group (M32C/83, M32C/83T)
Table 16.16 Pin Settings (2)
Port
Function
Setting
PSL1 Register
PSC Register
PS1 Register
P70(1)
P71(1)
PD7 Register
SDA2 output
PS1_0=1
PSL1_0=0
PSC_0=0
-
SDA2 input
PS1_0=0
-
-
PD7_0=0
SCL2 output
PS1_1=1
PSL1_1=0
PSC_1=0
SCL2 input
PS1_1=0
-
-
PD7_1=0
NOTES:
1. P70 and P71 are ports for the N-channel open drain output.
Table 16.17 Pin Settings (3)
Port
Function
Setting
PSL3 Register
PS3 Register(1)
P91
P92
P96
P97
PD9 Register(1)
SCL3 output
PS3_1=1
PSL3_1=0
-
SCL3 input
PS3_1=0
-
PD9_1=0
SDA3 output
PS3_2=1
PSL3_2=0
-
SDA3 input
PS3_2=0
-
PD9_2=0
SDA4 output
PS3_6=1
-
-
SDA4 input
PS3_6=0
-
PD9_6=0
SCL4 output
PS3_7=1
PSL3_7=0
-
SCL4 input
PS3_7=0
-
PD9_7=0
NOTES:
1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do
not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction
to set the PD9 and PS3 registers.
16.3.1 Detecting Start Condition and Stop Condition
The microcomputer detects either a start condition or stop condition. The start condition detect interrupt
is generated when the SCLi (i=0 to 4) pin is held high ("H") and the SDAi pin changes high ("H") to low
("L"). The stop condition detect interrupt is generated when the SCLi pin is held high ("H") and the SDAi
pin changes low ("L") to high ("H"). The start condition detect interrupt shares interrupt control registers
and vectors with the stop condition detect interrupt. The BBS bit in the UiSMR register determines which
interrupt is requested.
3 to 6 cycles < setup time(1)
3 to 6 cycles < hold time(1)
Setup time
Hold time
SCLi
SDAi
(Start condition)
SDAi
(Stop condition)
i=0 to 4
NOTES:
1. These cycles are main clock generation frequency cycles (XIN).
Figure 16.21 Start Condition or Stop Condition Detect
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 200 of 488
16. Serial I/O (Special Function)
M32C/83 Group (M32C/83, M32C/83T)
16.3.2 Start Condition or Stop Condition Output
The start condition is generated when the STAREQ bit in the UiSMR4 register (i=0 to 4) is set to "1"
(start). The restart condition is generated when the RSTAREQ bit in the UiSMR4 register is set to "1"
(start). The stop condition is generated when the STPREQ bit in the UiSMR4 is set to "1" (start).
The start condition is output when the STAREQ bit is set to "1" and the STSPSEL bit in the UiSMR4
register is set to "1" (start or stop condition generation circuit selected). The restart condition is output
when the RSTAREQ bit and STSPSEL bit are set to "1". The stop condition is output when the STPREQ
bit and the STSPSEL bit are set to "1".
When the start condition, stop condition or restart condition is output, do not generate an interrupt between the instruction to set the STAREQ bit, STPREQ bit or RSTAREQ bit to "1" and the instruction to set
the STSPSEL bit to "1". When the start condition is output, set the STAREQ bit to "1" before the
STSPSEL bit is set to "1".
Table 16.18 lists function of the STSPSEL bit. Figure 16.22 shows functions of the STSPSEL bit.
Table 16.18 STSPSEL Bit Function
STSPSEL = 0
Function
STSPSEL = 1
Start condition and stop condition
Program with a port determines
The STAREQ bit, RSTAREQ bit and
output
how the start condition or stop
STPREQ bit determine how the start
condition is output
condition or stop condition is output
Timing to generate a start condition
The start condition and stop
Start condition and stop condition
and stop condition interrupt request
condition are detected
generation are completed
(1) In slave mode,
CKDIR is set to "1" (external clock)
STSPSEL is set to "0" (no start condition and stop condition output)
SCLi
SDAi
Start condition detect
interrupt
Stop condition detect
interrupt
(1) In master mode,
CKDIR is set to "0" (internal clock)
STSPSEL is set to "1" (start condition and stop condition output)
Setting value of
the STSPEL bit
0
1
0
1
0
SCLi
SDAi
STAREQ=1
(start)
Start condition detect
interrupt
i=0 to 4
Figure 16.22 STSPSEL Bit Function
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 201 of 488
STPREQ=1
(start)
Stop condition detect
interrupt
M32C/83 Group (M32C/83, M32C/83T)
16. Serial I/O (Special Function)
16.3.3 Arbitration
The ABC bit in the UiSMR register (i=0 to 4) determines an update timing for the ABT bit in the UiRB
register. On the rising edge of SCLi, the microcomputer determines whether a transmit data matches
data input to the SDAi pin.
When the ABC bit is set to "0" (update per bit), the ABT bit is set to "1" as soon as a data discrepancy is
detected. The ABT bit is set to "0" if not detected. When the ABC bit is set to "1", the ABT bit is set to "1"
(detected-arbitration is lost) on the falling edge of the ninth bit of the transfer clock if any discrepancy is
detected. When the ABT bit is updated per byte, set the ABT bit to "0" (not detected-arbitration is won)
between an ACK detection in the first byte data and the next byte data to be transferred. When the ALS
bit in the UiSMR2 register is set to "1" (SDA output stop enabled), the arbitration lost occurs. As soon as
the ABT bit is set to "1", the SDAi pin is placed in a high-impedance state.
16.3.4 Transfer Clock
The transfer clock transmits and receives data as is shown in Figure 16.22
The CSC bit in the UiSMR2 register (i=0 to 4) synchronizes an internally generated clock (internal SCLi)
with the external clock applied to the SCLi pin. When the CSC bit is set to "1" (clock synchronous enabled) and the internal SCLi is held high ("H"), the internal SCLi become low ("L") if signal input to the
SCLi pin is on the falling edge. Value of the UiBRG register is reloaded to start counting for low level. A
counter stops when the SCLi pin is held "L" and then the internal SCLi changes "L" to "H". Counting is
resumed when the SCLi pin become "H". The transfer clock of UARTi is equivalent to the AND for signals
from the internal SCLi and the SCLi pin.
The transfer clock is synchronized between a half cycle before the falling edge of first bit of the internal
SCLi and the rising edge of the ninth bit. Select the internal clock as the transfer clock while the CSC bit
is set to "1".
The SWC bit in the UiSMR2 register determines whether the SCLi pin is fixed to output an "L" signal on
the falling edge of the ninth cycle of the transfer clock or not.
When the SCLHI bit in the UiSMR4 register is set to "1" (enabled), a SCLi output stops when a stop
condition is detected (high-impedance).
When the SWC2 bit in the UiSMR2 register is set to "1" (0 output), the SCLi pin forcibly outputs an "L"
signal while transmitting and receiving. The fixed "L" signal applied to the SCLi pin is cancelled by setting
the SWC2 bit to "0" (transfer clock) and the transfer clock is input to and output from the SCLi pin.
When the CKPH bit in the UiSMR3 register is set to "1" and the SWC9 bit in the UiSMR4 register is set to
"1" (SCL "L" hold enabled), the SCLi pin is fixed to output an "L" signal on the next falling edge after the
ninth bit of the clock. The fixed "L" signal applied to the SCLi pin is cancelled by setting the SWC9 bit to
"0" (SCL "L" hold disabled).
16.3.5 SDA Output
Values in bits 7 to 0 (D7 to D0) in the UiTB register (i=0 to 4) are output in descending order from D7. The
ninth bit (D8) is ACK or NACK.
Set the default value of SDAi transmit output when the IICM bit is set to "1" (I2C mode) and the SMD2 to
SMD0 bits in the UiMR register are set to "0002" (serial I/O disabled).
The DL2 to DL0 bits in the UiSMR3 register determine no delay in the SDAi output or a delay of 2 to 8
UiBRG register count source cycles.
When the SDHI bit in the UiSMR2 register is set to "1" (SDA output disabled), the SDAi pin is forcibly
placed in a high-impedance state. Do not set in the SDHI bit on the rising edge of the URTi transfer clock.
The ABT bit in the UiRB register may be set to "1" (detected).
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 202 of 488
M32C/83 Group (M32C/83, M32C/83T)
16. Serial I/O (Special Function)
16.3.6 SDA Input
When the IICM2 bit in the UiSMR2 register (i=0 to 4) is set to "0", the first eight bits of received data are
stored into bits 7 to 0 (D7 to D0) in the UiRB register. The ninth bit (D8) is ACK or NACK.
When the IICM2 bit is set to "1", the first seven bits (D7 to D1) of received data are stored into bits 6 to 0
in the UiRB register. Store the eighth bit (D0) into bit 8 in the UiRB register.
If the IICM bit in the UiSMR register is set to "1" and the CKPH bit is set to "1", the same data as that of
when setting the IICM2 bit to "0" can be read. To read the data, read the UiRB register after the rising
edge of the ninth bit of the transfer clock.
16.3.7 ACK, NACK
When the STSPSEL bit in the UiSMR4 register (i=0 to 4) is set to "0" (serial I/O circuit selected) and the
ACKC bit in the UiSMR4 register is set to "1" (ACK data output), the SDAi pin outputs the value set in the
ACKD bit.
If the IICM2 bit is set to "0", the NACK interrupt request is generated when the SDAi pin is held high ("H")
on the rising edge of the ninth bit of the transfer clock. The ACK interrupt request is generated when the
SDAi pin is held low ("L") on the rising edge of the ninth bit of the transfer clock.
When ACK is selected to generate a DMA request, the DMA transfer is activated by an ACK detection.
16.3.8 Transmit and Receive Reset
When the STC bit in the UiSMR2 register is set to "1" (UARTi initialization enabled) and a start condition
is detected,
- the transmit shift register is reset and the content of the UiTB register is transferred to the transmit shift
register. The first bit starts transmitting when the next clock is input. UARTi output value remains
unchanged between when clock is input and when data of the first bit is output. The value remains the
same value as when start condition was detected.
- the receive shift register is reset and the first bit starts receiving when the next clock is input.
- the SWC bit is set to "1" (SCL wait output enabled). The SCLi pin becomes low ("L") on the falling edge
of the ninth bit of the transfer clock.
If UARTi transmission and reception are started with this function, the TI bit in the UiC1 register remains
unchanged. Select the external clock as the transfer clock when using this function.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 203 of 488
16. Serial I/O (Special Function)
M32C/83 Group (M32C/83, M32C/83T)
16.4 Special Mode 2
In special mode 2, serial communication between one or multiple masters and multiple slaves is available.
_____
The SSi input pin (i=0 to 4) controls the serial bus communication. Table 16.19 lists specifications of special
mode 2. Table 16.20 lists registers to be used and settings. Tables 16.20 to 16.22 list pin settings.
Table 16.19. Special Mode 2 Specifications
Item
Transfer Data Format
Transfer Clock
Specification
Transfer data : 8 bits long
The CKDIR bit in the UiMR register (i=0 to 4) is set to "0" (internal clock selected) : fj/2(m+1)
fj = f1, f8, f2n(1) m : setting value of the UiBRG register 0016 to FF16
The CKDIR bit to "1" (external clock selected) : input clock from the CLKi pin
______
Transmit/Receive Control SSi input pin function
Transmit Start Condition
•To start transmitting, the following requirements must be met(2) :
- Set the TE bit in the UiC1 register to "1" (transmit enable)
- Set the TI bit in the UiC1 register to "0" (data in the UiTB register)
Receive Start Condition
• To start receiving, the following requirement must be met(2) :
- Set the RE bit in the UiC1 register to "1" (receive enable)
- Set the TE bit to "1" (receive enable)
- Set the TI bit to "0" (data in the UiTB register)
Interrupt Request
• Transmit interrupt timing can be selected from the followings:
Generation Timing
- The UiIRS bit in the UiC1 register is set to "0" (no data in a transmit buffer) :
when data is transferred from the UiTB register to the UARTi transmit register (transmission
started)
- The UiIRS register is set to "1" (transmission completed):
when data transmission from UARTi transfer register is completed
• Receive interrupt timing
When data is transferred from the UARTi receive register to the UiRB register (reception completed)
Error Detection
•Overrun error(3)
This error occurs when the seventh bit of the next received data is read before reading the
UiRB register
•Fault error
______
In master mode, the fault error occurs an "L" signal is applied to the SSi pin
Selectable Function
• CLK polarity
Select from the rising edge or falling edge of the transfer clock when transferred data is output and input
• LSB first / MSB first
Data is transmitted or received in either bit 0 or in bit 7
• Continuous receive mode
Reception is enabled simultaneously by reading the UiRB register
• Serial data logic inverse
This function inverses transmitted or received data logically
• TxD, RxD I/O polarity Inverse
TxD pin output and RxD pin input are inversed. All I/O data levels are also inversed
• Clock phase
Select from one of 4 combinations of transfer data polarity and phases
_____
• SSi input pin function
Output pin is placed in a high-impedance state to avoid data conflict between master and other
masters or slaves
NOTES:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
2. To start transmission/reception when selecting the external clock, these conditions must be met after the CKPOL bit
in the UiC0 register is set to "0" (data is transmitted on the falling edge of the transfer clock and data is received on the
rising edge) and the CLKi pin is held high ("H"), or when the CKPOL bit is set to "1" (Data is transmitted on the rising
edge of the transfer clock and data is received on the falling edge) and the CLKi pin is held low ("L").
3. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register does not change to "1"
(interrupt requested).
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 204 of 488
16. Serial I/O (Special Function)
M32C/83 Group (M32C/83, M32C/83T)
Table 16.20. Registers To Be Used and Settings in Special Mode 2
Register
Bit
Function
UiTB
0 to 7
Set transmit data
UiRB
0 to 7
Received data can be read
OER
Overrun error flag
UiBRG
0 to 7
Set bit rate
UiMR
UiC0
SMD2 to SMD0
Set to "0012"
CKDIR
Set to "0" in master mode or "1" in slave mode
IOPOL
Set to "0"
CLK0, CLK1
Select count source for the UiBRG register
CRS
Disabled since CRD = 1
TXEPT
Transfer register empty flag
CRD
Set to "1"
NCH
Select the output format of the TxDi pin
CKPOL
Clock phase can be set by the combination of the CKPOL bit and the CKPH bit in
the UiSMR3 register
UiC1
UFORM
Select either LSB first or MSB first
TE
Set to "1" to enable data transmission and reception
TI
Transfer buffer empty flag
RE
Set to "1" to enable data reception
RI
Reception complete flag
UiIRS
Select how the UARTi transmit interrupt is generated
UiRRM
Set to "1" to enable continuous receive mode
UiLCH, SCLKSTPB Set to "0"
UiSMR
0 to 7
Set to "0016"
UiSMR2
0 to 7
Set to "0016"
SSE
Set to "1"
CKPH
Clock phase can be set by the combination of the CKPH bit and the CKPOL bit
UiSMR3
in the UiC0 register
DINC
Set to "0" in master mode or "1" in slave mode
NODC
Set to "0"
ERR
Fault error flag
5 to 7
Set to "0002"
UiSMR4
0 to 7
Set to "0016"
IFSR
IFSR6, IFSR7
Select how fault error occurs
i=0 to 4
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 205 of 488
16. Serial I/O (Special Function)
M32C/83 Group (M32C/83, M32C/83T)
Table 16.21 Pin Settings in Special Mode 2 (1)
Port
Function
______
P60
P61
SS0 input
CLK0 input (slave)
CLK0 output (master)
RxD0 input (master)
STxD0 output (slave)
TxD0 output (master)
SRxD0 input (slave)
______
SS1 input
CLK1 input (slave)
CLK1 output (master)
RxD1 input (master)
STxD1 output (slave)
TxD1 output (master)
SRxD1 input (slave)
P62
P63
P64
P65
P66
P67
PS0 Register
PS0_0=0
PS0_1=0
PS0_1=1
PS0_2=0
PS0_2=1
PS0_3=1
PS0_3=0
PS0_4=0
PS0_5=0
PS0_5=1
PS0_6=0
PS0_6=1
PS0_7=1
PS0_7=0
Setting
PSL0 Register
–
–
–
–
PSL0_2=1
–
–
–
–
–
–
PSL0_6=1
–
–
PD6 Register
PD6_0=0
PD6_1=0
–
PD6_2=0
–
–
PD6_3=0
PD6_4=0
PD6_5=0
–
PD6_6=0
–
–
PD6_7=0
Table 16.21 Pin Settings (2)
Port
P70(1)
P71(1)
P72
Function
TxD2 output (master)
SRxD2 input (slave)
RxD2 input (master)
STxD2 output (slave)
CLK2 input (slave)
CLK2 output (master)
______
SS2 input
PS1 Register
PS1_0=1
PS1_0=0
PS1_1=0
PS1_1=1
PS1_2=0
PS1_2=1
PS1_3=0
Setting
PSL1 Register
PSC Register
PSL1_0=0
PSC_0=0
–
–
–
–
PSL1_1=1
PSC_1=0
–
–
PSL1_2=0
PSC_2=0
–
–
P73
NOTES:
1. P70 and P71 are ports for the N-channel open drain output.
PD7 Register
–
PD7_0=0
PD7_1=0
–
PD7_2=0
–
PD7_3=0
Table 16.23 Pin Settings (3)
Port
P90
P91
P92
P93
P94
P95
P96
P97
Function
CLK3 input (slave)
CLK3 output (master)
RxD3 input (master)
STxD3 output (slave)
TxD3 output (master)
SRxD3 input (slave)
______
SS3 input
_______
SS4 input
CLK4 input (slave)
CLK4 output (master)
TxD4 output (master)
SRxD4 input (slave)
RxD4 input (master)
STxD4 output (slave)
PS3 Register(1)
PS3_0=0
PS3_0=1
PS3_1=0
PS3_1=1
PS3_2=1
PS3_2=0
PS3_3=0
PS3_4=0
PS3_5=0
PS3_5=1
PS3_6=1
PS3_6=0
PS3_7=0
PS3_7=1
Setting
PSL3 Register
–
–
–
PSL3_1=1
PSL3_2=0
–
PSL3_3=0
PSL3_4=0
PSL3_5=0
–
–
PSL3_6=0
–
PSL3_7=1
PD9 Register(1)
PD9_0=0
–
PD9_1=0
–
–
PD9_2=0
PD9_3=0
PD9_4=0
PD9_5=0
–
–
PD9_6=0
PD9_7=0
–
NOTES:
1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not
generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to set
the PD9 and PS3 registers.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 206 of 488
16. Serial I/O (Special Function)
M32C/83 Group (M32C/83, M32C/83T)
______
16.4.1 SSi Input Pin Function (i=0 to 4)
____
______
When the SSE bit in the UiSMR3 register is set to "1" (SS function enabled), the SSi input pin function is
selected, activating the pin function.
The DINC bit in the UiSMR3 register determines which microcomputer performs as master or slave.
______
When multiple microcomputers perform as the masters (multi-master system), the SSi pin setting determines which master microcomputer is active and when.
16.4.1.1 When Setting the DINC Bit to "1" (Slave Mode)
_____
When an "H" signal is applied to the SSi pin, the STxDi and SRxDi pins are placed in a high-impedance state and the transfer clock input to the CLKi pin is ignored. When a low-level signal ("L") is
_____
applied to the SSi input pin, the transfer clock input is valid and serial communication is enabled.
16.4.1.2 When Setting the DINC Bit to "0" (Master Mode)
_____
When an "H" signal is applied to the SSi pin, serial communication is available due to transmission
_____
privilege. The master outputs the transfer clock. When an "L" signal is applied to the SSi pin, it indicates that another master is active and TxDi, RxDi and CLKi pins are placed in a high-impedance
state. Moreover, a fault error occurs and the IR bit in the BCNiIC register is set to "1" (interrupt
requested). The ERR bit in the UiSMR3 register indicates whether a fault error occurs.
In master mode, software interrupt numbers 39, 40 and 41 are used for the fault error interrupt. The
fault error interrupt is generated when the ERR bit changes "0" to "1". The fault error interrupt of
UART0 and of UART3 share an interrupt vector. The fault error interrupt of UART1 and of UART4
share an interrupt vector. The IFSR6 and IFSR7 bits in the IFSR register determine which fault error
interrupt is used.
Communication is not terminated even if a fault error is generated while communicating. To stop
communication, the SMD 2 to SMD0 bit in the UiMR register is set to "0002" (serial I/O disabled).
Microcomputer
Microcomputer
P13
P12
P93(SS3)
P93(SS3)
P90(CLK3)
P90(CLK3)
P91(RxD3)
P91(STxD3)
P92(TxD3)
P92(SRxD3)
Master
Slave
Microcomputer
P93(SS3)
P90(CLK3)
P91(STxD3)
P92(SRxD3)
Slave
___
Figure 16.23 Serial Bus Communication Control with SS Pin
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 207 of 488
16. Serial I/O (Special Function)
M32C/83 Group (M32C/83, M32C/83T)
16.4.2 Clock Phase Setting Function
The CKPH bit in the UiSMR3 register (i=0 to 4) and the CKPOL bit in the UiC0 register select one of four
combinations of transfer clock polarity and phases.
The transfer clock phase and polarity must be the same between the master and the slave involved in the
transfer.
16.4.2.1 When setting the DINC Bit to "0" (Master (Internal Clock))
Figure 16.24 shows transmit and receive timing.
16.4.2.2 When Setting the DINC Bit to "1" (Slave (External Clock))
_____
When the CKPH bit is set to "0" (no clock delay) and the SSi input pin is held high ("H"), the STxDi pin
_____
is placed in a high-impedance state. When the SSi input pin becomes low ("L"), conditions to start a
serial transfer are met, but output is indeterminate. The serial transmission is synchronized with the
transfer clock. Figure 16.25 shows the transmit and receive timing.
_____
When the CKPH bit is set to "1" (clock delay) and the SSi input pin is held high ("H"), the STxDi pin is
_____
placed in a high-impedance state. When the SSi pin becomes low ("L"), the first data is output. The
serial transmission is synchronized with the transfer clock. Figure 16.26 shows the transmit and
receive timing.
Input Signal to the
SS Pin in the Master
"H"
"L"
Clock Output
"H"
(CKPOL=0, CKPH=0) "L"
Clock Output
"H"
(CKPOL=1, CKPH=0) "L"
Clock Output
"H"
(CKPOL=0, CKPH=1) "L"
Clock Output
"H"
(CKPOL=1, CKPH=1) "L"
Data Output Timing
"H"
"L"
D0
D1
D2
D3
D4
D5
Data Input Timing
Figure 16.24 Transmit and Receive Timing in Master Mode (Internal Clock)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 208 of 488
D6
D7
16. Serial I/O (Special Function)
M32C/83 Group (M32C/83, M32C/83T)
"H"
Input Signal to the
SS Pin
"L"
"H"
Clock Input
(CKPOL=0, CKPH=0) "L"
"H"
Clock Input
(CKPOL=1, CKPH=0) "L"
Data Output Timing(1)
"H"
"L"
Data Input Timing
D0
D1
D2
D3
D4
D5
D6
D7
Highimpedance
Highimpedance
Indeterminate
NOTES:
1. P70 is a port for the N-channel open drain output and must be pulled up externally for
data output.
Figure 16.25 Transmit and Receive Timing in Slave Mode (External Clock) (CKPH=0)
"H"
Input Signal to the
SS Pin
"L"
"H"
Clock Input
(CKPOL=0, CKPH=1) "L"
"H"
Clock Input
(CKPOL=1, CKPH=1) "L"
Data Output Timing(1) "H"
"L"
D0
Highimpedance
D1
D2
D3
D4
D5
D6
D7
Highimpedance
Data Input Timing
NOTES:
1. P70 is a port for the N-channel open drain output and must be pulled up externally for data output.
Figure 16.26 Transmit and Receive Timing in Slave Mode (External Clock) (CKPH=1)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 209 of 488
16. Serial I/O (Special Function)
M32C/83 Group (M32C/83, M32C/83T)
16.5 Special Mode 3 (GCI Mode)
In GCI mode, the external clock is synchronized with the transfer clock used in the clock synchronous serial
I/O mode.
Table 16.24 lists specifications of GCI mode. Table 16.25 lists registers to be used and settings. Tables
16.25 to 16.27 list pin settings.
Table16.24 GCI Mode Specifications
Item
Specification
Transfer Data Format
Transfer data : 8 bits long
Transfer Clock
The CKDIR bit in the UiMR register (i=0 to 4) is set to "1" (external clock selected):
an input from the CLKi pin
________
Clock Synchronization Function The CTSi pin inputs a trigger
Transmit/Receive Start
When a trigger signal is applied to the CTSi pin under the following conditions:
Conditions
• Set the TE bit in the UiC1 register to "1" (transmit enable)
• Set the RE bit in the UiC1 register to "1" (receive enable)
• Set the TI bit in the UiC1 register to "0" (data in UiTB register)
Interrupt Request
Transmit interrupt timing can be selected from the followings:
Generation Timing
• The UiIRS bit in the UiC1 register is set to "0" (UiTB register empty) :
when data is transferred from the UiTB register to the UARTi transmit register (transmission started)
• The UiIRS bit is set to "1" (transmit completed):
when a data transmission from the UARTi transfer register is completed
Receive interrupt timing
when data is transferred from the UARTi receive register to the UiRB register (reception completed)
Error Detection
Overrun error(1)
This error occurs when the seventh bit of the next received data is read before reading the
UiRB register.
NOTES:
1. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register does not change to
"1" (interrupt requested).
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 210 of 488
16. Serial I/O (Special Function)
M32C/83 Group (M32C/83, M32C/83T)
Table 16.25 Registers To Be Used and Settings in GCI Mode
Register
Bit
Function
UiTB
0 to 7
Set transmit data
UiRB
0 to 7
Received data
OER
Overrun error flag
UiBRG
0 to 7
Set to "0016"
UiMR
UiC0
UiC1
UiSMR
UiSMR2
UiSMR3
UiSMR4
SMD2 to SMD0
Set to "0012"
CKDIR
Set to "1"
IOPOL
Set to "0"
CLK1 to CLK0
Set to "002"
CRS
Disabled because CRD = 1
TXEPT
Transfer register empty flag
CRD
Set to "1"
NCH
Select the output format of the TxDi pin
CKPOL
Set to "0"
UFORM
Set to "0"
TE
Set to "1" to enable data transmission and reception
TI
Transfer buffer empty flag
RE
Set to "1" to enable data reception
RI
Reception complete flag
UiIRS
Select how the UARTi transmit interrupt is generated
UiRRM, UiLCH
Set to "0"
SCLKSTPB
Set to "0"
0 to 6
Set to "00000002"
SCLKDIV
See Table 16.29
0 to 6
Set to "00000002"
SU1HIM
See Table 16.29
0 to 2
Set to "0002"
NODC
Set to "0"
4 to 7
Set to "00002"
0 to 7
Set to "0016"
i=0 to 4
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 211 of 488
16. Serial I/O (Special Function)
M32C/83 Group (M32C/83, M32C/83T)
Table 16.26 Pin Settings in CGI Mode (1)
Port
Function
Setting
PS0 Register
PSL0 Register
PD6 Register
__________
P60
CTS0 input(1)
PS0_0=0
–
PD6_0=0
P61
CLK0 input
PS0_1=0
–
PD6_1=0
P62
RxD0 input
PS0_2=0
–
PD6_2=0
TxD0 output
P63
PS0_3=1
–
–
P64
CTS1 input(1)
PS0_4=0
–
PD6_4=0
P65
CLK1 input
PS0_5=0
–
PD6_5=0
P66
RxD1 input
PS0_6=0
–
PD6_6=0
P67
TxD1 output
PS0_7=1
–
–
__________
NOTES:
_______
1. CTS input is used to input a trigger.
Table 16.27 Pin Settings (2)
Port
Function
Setting
PS1 Register
PSL1 Register
PSC Register
PD7 Register
P70(1)
TxD2 output
PS1_0=1
PSL1_0=0
PSC_0=0
–
P71(1)
RxD2 input
PS1_1=0
–
–
PD7_1=0
CLK2 input
PS1_2=0
–
–
PD7_2=0
PS1_3=0
–
–
PD7_3=0
P72
__________
CTS2 input(2)
P73
NOTES:
1. P70 and P71 are ports for the N-channel open drain output.
_______
2. CTS input is used to input a trigger.
Table 16.28 Pin Settings (3)
Port
Function
Setting
PS3 Register(1)
PD9 Register(1)
PSL3 Register
P90
CLK3 input
PS3_0=0
–
PD9_0=0
P91
RxD3 input
PS3_1=0
–
PD9_1=0
TxD3 output
PS3_2=1
PSL3_2=0
–
PS3_3=0
PSL3_3=0
PD9_3=0
P92
__________
P93
CTS3 input(2)
__________
P94
CTS4 input(2)
PS3_4=0
PSL3_4=0
PD9_4=0
P95
CLK4 input
PS3_5=0
PSL3_5=0
PD9_5=0
P96
TxD4 output
PS3_6=1
–
–
P97
RxD4 input
PS3_7=0
–
PD9_7=0
NOTES:
1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not
generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to set
the PD9 and PS3 registers.
_______
2. CTS input is used to input a trigger.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 212 of 488
16. Serial I/O (Special Function)
M32C/83 Group (M32C/83, M32C/83T)
To generate the internal clock synchronized with the external clock, first set the SU1HIM bit in the
UiSMR2 register (i=0 to 4) and the SCLKDIV bit in the UiSMR register to values shown in Table 16.29.
Then apply a trigger signal to the CTSi pin. Either the same clock cycle as the external clock or external
clock divided by two can be selected as the transfer clock. The SCLKSTPB bit in the UiC1 register
controls the transfer clock. Set the SCLKSTPB bit accordingly, to start or stop the transfer clock during an
external clock operation. Figure 16.27 shows an example of the clock-divided synchronous function.
Table 16.29 Clock-Divided Synchronous Function Select
SCLKDIV Bit in
SU1HIM Bit in
Clock-Divided Synchronous Function
UiSMR Register
UiSMR2 Register
Example of Waveform
0
0
Not synchronized
-
0
1
Same division as the external clock
A in Figure 16.27
1
0 or 1
Same division as the external clock
B in Figure 16.27
divided by 2
i=0 to 4
External Clock
from the CLKi Pin
Trigger Signal
from the CTSi Pin
1
2
3
4
5
6
7
8
Transfer Clock
The SCLKSTPB bit in the UiC1 register
stops the clock
A
TxDi
1
2
3
4
5
6
7
8
Transfer Clock
B
TxDi
1
2
3
i=0 to 4
A, B : See Table 16.29.
Figure 16.27 Clock-Divided Synchronous Function
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 213 of 488
4
5
6
7
8
16. Serial I/O (Special Function)
M32C/83 Group (M32C/83, M32C/83T)
16.6 Special Mode 4 (IE Mode)
In IE mode, devices connected with the IEBus can communicate in UART mode.
Table 16.30 lists registers to be used and settings. Tables 16.30 to 16.32 list pin settings.
Table 16.30. Registers To Be Used and Settings in IE Mode
Register
Bit
Function
UiTB
0 to 8
Set transmit data
UiRB
0 to 8
Received data can be read
OER, FER,
Error flags
PER, SUM
UiBRG
0 to 7
Set bit rate
UiMR
SMD2 to SMD0
Set to "1102"
CKDIR
Select the internal clock or external clock
STPS
Set to "0"
PRY
Disabled because PRYE=0
PRYE
Set to "0"
UiC0
UiC1
IOPOL
Select TxD and RxD I/O polarity
CLK1 to CLK0
Select the count source for the UiBRG register
CRS
Disabled because CRD=1
TXEPT
Transfer register empty flag
CRD
Set to "1"
NCH
Select output format of the TxDi pin
CKPOL
Set to "0"
UFORM
Set to "0"
TE
Set to "1" to enable data transmission
TI
Transfer buffer empty flag
RE
Set to "1" to enable data reception
RI
Reception complete flag
UiIRS
Select how the UARTi transmit interrupt is generated
UiRRM, UiLCH,
Set to "0"
SCLKSTPB
UiSMR
0 to 3
Set to "00002"
ABSCS
Select bus conflict detect sampling timing
ACSE
Set to "1" to automatically clear the transmit enable bit
SSS
Select transmit start condition
SCLKDIV
Set to "0"
UiSMR2
0 to 7
Set to "0016"
UiSMR3
0 to 7
Set to "0016"
UiSMR4
0 to 7
Set to "0016"
IFSR
IFSR6, IFSR7
Select how the bus conflict interrupt occurs
i=0 to 4
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 214 of 488
16. Serial I/O (Special Function)
M32C/83 Group (M32C/83, M32C/83T)
Table 16.31 Pin Settings in IE Mode (1)
Port
Function
Setting
PS0 Register
P61
CLK0 input
PSL0 Register
PD6 Register
PS0_1=0
–
PD6_1=0
CLK0 output
PS0_1=1
–
–
P62
RxD0 input
PS0_2=0
–
PD6_2=0
P63
TxD0 output
PS0_3=1
–
–
P65
CLK1 input
PS0_5=0
–
PD6_5=0
CLK1 output
PS0_5=1
–
–
P66
RxD1 input
PS0_6=0
–
PD6_6=0
P67
TxD1 output
PS0_7=1
–
–
Table 16.32 Pin Settings (2)
Port
Function
Setting
PS1 Register
PSL1 Register
PSC Register
PD7 Register
P70(1)
TxD2 output
PS1_0=1
PSL1_0=0
PSC_0=0
–
P71(1)
RxD2 input
PS1_1=0
–
–
PD7_1=0
P72
CLK2 input
PS1_2=0
–
–
PD7_2=0
CLK2 output
PS1_2=1
PSL1_2=0
PSC_2=0
–
NOTES:
1. P70 and P71 are ports for the N-channel open drain output.
Table 16.33 Pin Settings (3)
Port
Function
Setting
PS3 Register(1)
P90
PD9 Register(1)
PSL3 Register
CLK3 input
PS3_0=0
–
PD9_0=0
CLK3 output
PS3_0=1
–
–
P91
RxD3 input
PS3_1=0
–
PD9_1=0
P92
TxD3 output
PS3_2=1
PSL3_2=0
–
P95
CLK4 input
PS3_5=0
PSL3_5=0
PD9_5=0
CLK4 output
PS3_5=1
–
–
P96
TxD4 output
PS3_6=1
–
–
P97
RxD4 input
PS3_7=0
–
PD9_7=0
NOTES:
1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do
not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to
set the PD9 and PS3 registers.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 215 of 488
M32C/83 Group (M32C/83, M32C/83T)
16. Serial I/O (Special Function)
If the output level of the TxDi pin (i=0 to 4) differs from the input level of the RxDi pin, an interrupt request is
generated.
UART0 and UART3 are assigned software interrupt number 40. UART1 and UART4 are assigned number
41. When using the bus conflict detect function of UART0 or UART3, of UART1 or UART4, set the IFSR6
bit and the IFSR7 bit in the IFSR register accordingly.
When the ABSCS bit in the UiSMR register is set to "0" (rising edge of the transfer clock), it is determined,
on the rising edge of the transfer clock, if the output level of the TxD pin and the input level of the RxD pin
match. When the ABSCS bit is set to "1" (timer Aj underflow), it is determined when the timer Aj (timer A3
in UART0, timer A4 in UART1, timer A0 in UART2, timer A3 in UART3, the timer A4 in UART4) overflows.
Use the timer Aj in one-shot timer mode.
When the ACSE bit in the UiSMR register is set to "1" (automatic clear at bus conflict) and the IR bit in the
BCNiIC register to "1" (discrepancy detected), the TE bit is set to "0" (transmit disable).
When the SSS bit in the UiSMR register is set to "1" (synchronized with RxDi), the TxDi pin starts transmitting data on the falling edge of the RxDi pin. Figure 16.28 shows bits associated with the bus conflict detect
function.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 216 of 488
16. Serial I/O (Special Function)
M32C/83 Group (M32C/83, M32C/83T)
(1) The ABSCS Bit in the UiSMR Register (Bus conflict and sampling clock selected)
(i=0 to 4)
Bus conflict is detected on the rising edge of the transfer clock when ABSCS is set to "0"
Transfer Clock
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
TxDi
RxDi
Trigger signal is applied to the TAjIN pin
Timer Aj
When ABSCS is set to "1", bus conflict is detected when the timer Aj underflows
(in the one-shot mode). An interrupt request is generated.
Timer Aj: timer A3 in UART0 or UART3, timer A4 in UART1 or UART4, timer A0 in UART2
(2) The ACSE Bit in the UiSMR Register (Transmit enable bit is automatically cleared)
Transfer Clock
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
TxDi
RxDi
IR bit in
BCNilC register
TE bit in
UiC1 register
(3) The SSS bit in the UiSMR Register (Transmit start condition selected)
When SSS is set to "0", data is transmitted after one transfer clock cycle if data transmission is enabled.
Transfer Clock
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
D6
D7
D8
SP
TxDi
transmit enable conditons are met
When SSS is set to "1", data is transmitted on the rising edge of RxDi(1)
CLKi
ST
TxDi
D0
D1
D2
D3
D4
(Note 2)
RxDi
NOTES:
1. Data is transmitted on the falling edge of RxDi when IOPOL is set to "0".
Data is transmitted on the rising edge of RxDi when IOPOL is set to "1".
2. Data transmission condition must be met before the falling edge of RxD.
Figure 16.28 Bit Function Related Bus Conflict Detection
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 217 of 488
D5
16. Serial I/O (Special Function)
M32C/83 Group (M32C/83, M32C/83T)
16.7 Special Mode 5 (SIM Mode)
In SIM mode, SIM interface devices can communicate in UART mode. Both direct and inverse formats are
available and the TxDi pin (i=0 to 4) can output an "L" signal when a parity error is detected.
Table 16.34 lists specifications of SIM mode. Table 16.35 lists registers to be used and register settings in
SIM mode. Tables 16.36 to 16.38 list the pin settings.
Table16.34 SIM Mode Specifications
Item
Transfer Data Format
Specification
• Transfer data: 8-bit UART mode
• One stop bit
• In direct format
Parity:
Even
Data logic:
Direct
Transfer format: LSB first
• In inverse format
Parity:
Odd
Data logic:
Inverse
Transfer format: MSB first
Transfer Clock
The CKDIR bit in the UiMR register (i=0 to 4) is "0" (internal clock selected):
fj/16(m+1)(1) fj = f1, f8, f2n(2) m : setting value of the UiBRG register 0016 to FF16
Do not set the CKDIR bit to "1" (external clock selected)
Transmit/Receive Control The CRD bit in the UiC0 register is set to "1" (CTS, RTS function disabled)
Other Setting Items
The UiIRS bit in the UiC1 register is set to "1" (transmission completed)
Transmit Start Condition To start transmitting, the following requirements must be met:
• Set the TE bit in the UiC1 register to "1" (transmit enable)
• Set the TI bit in the UiC1 register to "0" (data being in the UiTB register)
Receive Start Condition To start receiving, the following requirements must be met:
• Set the RE bit in the UiC1 register to "1" (receive enable)
• Detect the start bit
Interrupt Request
Transmit interrupt timing
Generation Timing
• The UiIRS bit is set to "1" (transmission is completed):
when data transmission from the UARTi transfer register is completed
Receive interrupt timing
when data is transferred from the UARTi receive register to the UiRB register (reception completed)
Error Detection
• Overrun error(1)
This error occurs when the eighth bit of the next data is received before reading the UiRB register
• Framing error
This error occurs when the number of the stop bit set is not detected
• Parity error
This error occurs when the number of "1" in parity bit and character bits differ from
the number set.
• Error sum flag
The SUM bit is set to "1" when an overrun error, framing error or parity error occurs.
NOTES:
1. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register does not change to
"1" (interrupt requested).
2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 218 of 488
16. Serial I/O (Special Function)
M32C/83 Group (M32C/83, M32C/83T)
Table 16.35 Registers To Be Used and Settings
Register
UiTB
UiRB
Bit
Function
0 to 7
Set transmit data
0 to 7
Received data can be read
OER, FER,
Error flags
PER, SUM
UiBRG
UiMR
UiC0
UiC1
0 to 7
Set bit rate
SMD2 to SMD0
Set to "1012"
CKDIR
Set to "0"
STPS
Set to "0"
PRY
Set to "1" for direct format or "0" for inverse format
PRYE
Set to "1"
IOPOL
Set to "0"
CLK1 to CLK0
Select count source for the UiBRG register
CRS
Disabled because CRD=1
TXEPT
Transfer register empty flag
CRD
Set to "1"
NCH
Set to "1"
CKPOL
Set to "0"
UFORM
Set to "0" for direct format or "1" for inverse format
TE
Set to "1" to enable data transmission
TI
Transfer buffer empty flag
RE
Set to "1" to enable data reception
RI
Reception complete flag
UiIRS
Set to "1"
UiRRM
Set to "0"
UiLCH
Set to "0" for direct format or "1" for inverse format
UiERE
Set to "1"
UiSMR
0 to 3
Set to "0016"
UiSMR2
0 to 7
Set to "0016"
UiSMR3
0 to 7
Set to "0016"
UiSMR4
0 to 7
Set to "0016"
i=0 to 4
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 219 of 488
16. Serial I/O (Special Function)
M32C/83 Group (M32C/83, M32C/83T)
Table 16.36 Pin Settings in SIM Mode (1)
Port
Function
Setting
PS0 Register
PSL0 Register
PD6 Register
P62
RxD0 input
PS0_2=0
–
PD6_2=0
P63
TxD0 output
PS0_3=1
–
–
P66
RxD1 input
PS0_6=0
–
PD6_6=0
P67
TxD1 output
PS0_7=1
–
–
Table 16.37 Pin Settings (2)
Port
Function
Setting
PS1 Register
PSL1 Register
PSC Register
PD7 Register
P70(1)
TxD2 output
PS1_0=1
PSL1_0=0
PSC_0=0
–
P71(1)
RxD2 input
PS1_1=0
–
–
PD7_1=0
NOTES:
1. P70 and P71 are ports for the N-channel open drain output.
Table 16.38 Pin Settings (3)
Port
Function
Setting
PS3
Register(1)
P91
RxD3 input
PS3_1=0
P92
TxD3 output
P96
TxD4 output
P97
RxD4 input
PS3_7=0
PD9 Register(1)
PSL3 Register
–
PD9_1=0
PS3_2=1
PSL3_2=0
–
PS3_6=1
–
–
–
PD9_7=0
NOTES:
1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do
not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to
set the PD9 and PS3 registers.
Figure 16.29 shows an example of a SIM interface operation. Figure 16.30 shows an example of a SIM
interface connection. Connect TxDi to RxDi for a pull-up.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 220 of 488
16. Serial I/O (Special Function)
M32C/83 Group (M32C/83, M32C/83T)
(1) Transmit Timing
Tc
Transfer Clock
TE bit in the UiC1
register
TI bit in the UiC1
register
"1"
Data is written to
the UiTB register
"0"
"0"
Parity Stop
bit
bit
Start
bit
TxDi
ST D0 D1
D2 D3 D4 D5 D6 D7
P
Data is transferred from the UiTB
register to the UARTi transmit register
ST D0 D1 D2 D3 D4 D5 D6 D7
SP
Parity Error Signal
returned from
Receiving End
P
SP
An "L" signal is applied from the SIM
card due to a parity error
Signal Line Level(2)
TXEPT bit in the
UiC0 register
(Note 1)
"1"
ST D0 D1 D2 D3 D4 D5 D6 D7
P
ST D0 D1 D2 D3 D4 D5 D6 D7
SP
An interrupt routine
detects "H" or "L"
"1"
SP
P
An interrupt routine detects
"H" or "L"
"0"
IR bit in the SiTIC
register
"1"
"0"
Set to "0" by an interrupt request acknowledgement or by program
i=0 to 4
The above applies under the following conditions:
• The PRYE bit in the UiMR register is set to "1" (parity enabled)
• The STPS bit in the UiMR register is set to "0" (1 stop bit)
• The UiIRS bit in the UiC1 register is set to "1" (interrupt request generated
when transmission completed)
Tc = 16(m+1) / fj
fj: count source frequency of the UiBRG register (f1, f8, f2n(4))
m: setting value of the UiBRG register
(2) Receive Timing
Transfer Clock
RE bit in the UiC1
register
"1"
"0"
Start
bit
Transmit Waveform
from the
Transmitting End
ST D0 D1 D2 D3 D4 D5 D6 D7
Parity Stop
bit
bit
P SP
TxDi
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
TxDi outputs "L" due to
a parity error
Signal Line Level(3)
ST D0 D1 D2 D3 D4 D5 D6 D7
RI bit in the UiC1
register
"1"
IR bit in the
SiRIC register
"1"
P SP
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
"0"
Read the UiRB register
"0"
Set to "0" by an interrupt request acknowledgement or by program
i=0 to 4
The above applies under the following conditions:
• The PRYE bit in the UiMR register is set to "1" (parity enabled)
• The STPS bit in the UiMR register is set to "0" (1 stop bit)
Tc = 16(m+1) / fj
fj: count source frequency of the UiBRG register (f1, f8, f2n(4))
m: setting value of the UiBRG register
NOTES:
1. Data transmission starts when BRG overflows after a value is set to the UiTB register on the rising edge of the TI bit.
2. Because the TxDi and RxDi pins are connected, a composite waveform, consisting of transmit waveform from the TxDi
pin and parity error signal from the receiving end, is generated.
3. Because the TxDi and RxDi pins are connected, a composite waveform, consisting of transmit waveform from the
transmitting end and parity error signal from the TxDi pin, is generated.
4. The CNT3 to CNT0 bits in the TCSPR register selects no division (n=0) or divide-by-2n (n=1 to 15).
Figure 16.29 SIM Interface Operation
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 221 of 488
16. Serial I/O (Special Function)
M32C/83 Group (M32C/83, M32C/83T)
Microcomputer
SIM card
TxDi
RxDi
i=0 to 4
Figure 16.30 SIM Interface Connection
16.7.1 Parity Error Signal
16.7.1.1 Parity Error Signal Output Function
When the UiERE bit in the UiC1 register (i=0 to 4) is set to "1", the parity error signal can be output.
The parity error signal is output when a parity error is detected upon receiving data. TxDi outputs an
"L" signal in the timing shown in Figure 16.31. When reading the UiRB register during a parity error
output, the PER bit in the UiRB register is set to "0" and TxDi again outputs an "H" signal simultaneously.
16.7.1.2 Parity Error Signal
To determine whether the parity error signal is output, the port that shares a pin with RxDi is read by
using a transmit complete interrupt routine.
RxDi
TxDi
"H"
"L"
ST
"H"
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
Hi-Z
"L"
Recieve
Complete Flag
"1"
"0"
NOTES:
1. The above applies to direct format conditions (PRY=1, UFORM=0, UiLCH=0).
Figure 16.31 Parity Error Signal Output Timing (LSB First)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 222 of 488
ST : Start bit
P : Even parity
SP : Stop bit
i=0 to 4
16. Serial I/O (Special Function)
M32C/83 Group (M32C/83, M32C/83T)
16.7.2 Format
16.7.2.1 Direct Format
Set the PRYE bit in the UiMR register (i=0 to 4) to "1", the PRY bit to "1", the UFORM bit in the UiC0
register to "0" and the UiLCH bit in the UiC1 register to "0". When data are transmitted, data set in
UiTB register are transmitted with the even-numbered parity, starting from D0. When data are received, received data are stored in the UiRB register, starting from D0. The even-numbered parity
determines whether a parity error occurs.
16.7.2.2 Inverse Format
Set the PRYE bit to "1", the PRY bit to "0", the UFORM bit to "1" and the UiLCH bit to "1". When data
are transmitted, values set in the UiTB register are logically inversed and are transmitted with the
odd-numbered parity, starting from D7. When data are received, received data are logically inversed
to be stored in the UiRB register, starting from D7. The odd-numbered parity determines whether a
parity error occurs.
(1) Direct Format
Transfer Clock
"H"
"L"
TxDi
"H"
D0
D1
D2
D3
D4
D5
D6
D7
P
P : Even parity
D7
D6
D5
D4
D3
D2
D1
D0
P
P : Odd parity
"L"
(2) Inverse Format
Transfer Clock
TxDi
"H"
"L"
"H"
"L"
i=0 to 4
Figure 16.32 SIM Interface Format
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 223 of 488
M32C/83 Group (M32C/83, M32C/83T)
17. A/D Converter
17. A/D Converter
The A/D converter consists of two 10-bit successive approximation A/D converters, each with a capacitive
coupling amplifier.
The result of an A/D conversion is stored into the A/D register corresponding to selected pins.
Table 17.1 lists specifications of the A/D converter. Figure 17.1 shows a block diagram of the
A/D converter. Table 17.2 lists the differences between A/D0 and A/D1 conversions, which share the same
conversion method. A/D0 and A/D1 can perform conversions simultaneously. Table 17.3 lists settings of
the following pins; AN0 to AN7, AN00 to AN07, AN20 to AN27, AN150 to AN157, ANEX0, ANEX1 and
__________
ADTRG. Figures 17.2 to 17.7 show registers associated with the A/D converter.
NOTE
In this section, the 144-pin package is given as the example.
The AN150 to AN157 pins are not included in the 100-pin package.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 224 of 488
17. A/D Converter
M32C/83 Group (M32C/83, M32C/83T)
Table 17.1 A/D Converter Specifications
Item
Specification
A/D Conversion Method
Analog Input
Voltage(1)
Successive approximation (with a capacitive coupling amplifier)
0V to AVCC (VCC)
Operating Clock, ØAD(2)
fAD, fAD/2, fAD/3, fAD/4
Resolution
Select from 8 bits or 10 bits
Operating Mode
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,
repeat sweep mode 1
Analog Input Pins(3)
34 pins
8 pins each for AN (AN0 to AN7), AN0 (AN00 to AN07), AN2 (AN20 to AN27),
AN15 (AN150 to AN157)
2 extended input pins (ANEX0 and ANEX1)
A/D Conversion Start Condition
Software trigger
• The ADST bit in the ADiCON0 (i=0, 1) register is set to "1" (A/D conversion
started) by program
• The PST bit in the AD0CON2 register is set to "1" (A/D0 and A/D1 start a
conversion simultaneously) by program
External trigger (re-trigger is enabled)
__________
When a falling edge is applied to the AD TRG pin after the ADST bit is set to "1" by
program
Hardware trigger (re-trigger is enabled)
One of the following interrupt requests is generated after the ADST bit is set to
"1" by program:
• The timer B2 interrupt request of the three-phase motor control timer functions
(after the ICTB2 counter completes counting)
• The intelligent I/O interrupt request
Channel 1 in the group 2 (A/D0), channel 1 in the group 3 (A/D1)
Conversion Rate Per Pin
• Without the sample and hold function
8-bit resolution : 49 ØAD cycles
10-bit resolution : 59 ØAD cycles
• With the sample and hold function
8-bit resolution : 28 ØAD cycles
10-bit resolution : 33 ØAD cycles
NOTES:
1. Analog input voltage is not affected by the sample and hold function status.
2. ØAD frequency must be under 16 MHz when VCC=5V.
ØAD frequency must be under 10 MHz when VCC=3.3V.
Without the sample and hold function, the ØAD frequency must be 250 kHz or more.
With the sample and hold function, the ØAD frequency must be 1 MHz or more.
3. AVCC = VREF = VCC, A/D input voltage (for AN0 to AN7, AN00 to AN07, AN20 to AN27, AN150 to AN157, ANEX0
and ANEX1) ≤ VCC.
Table 19.2 Difference between A/D0 and A/D1
Item
A/D0
Pins(1)
A/D1
AN (AN0 to AN7)
Select from AN0 (AN00 to AN07),
Extended Analog Input Pins
ANEX0, ANEX1
Not provided
External Op-Amp(1)
Enabled
Disabled
Intelligent I/O used as a Trigger
Channel 1 in group 2
Channel 1 in group 3
Analog Input
AN2 (AN20 to AN27) or AN15 (AN150 to AN157)
NOTES:
1. When the ADS bit in the AD0CON2 register is set to "0" (channel replacement disabled)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 225 of 488
17. A/D Converter
M32C/83 Group (M32C/83, M32C/83T)
000
AN20
001
AN21
010
AN22
011
AN23
100
AN24
101
AN25
110
AN26
111
AN27
Software trigger
0
00
ADTRG
TB2 interrupt request
01
•Intelligent I/O group2
channel 1 interrupt request (A/D0)
•Intelligent I/O group3
channel 1 interrupt request (A/D1)
10
1
A/Di trigger
TRG bit in
ADiCON0 register
TRG1 to TRG0 bits in
ADiCON2 register
AN00
000
AN01
001
AN02
010
OPA1 to OPA0 bits in
AD0CON1 register
AN03
011
AN04
100
ANEX1
1X
ANEX0
000
AN1
010
AN3
00
1
0
1
111
CH2 to CH0 bits in
AD1CON0 register
Comparator 0
AN156
AD10 register
AD01 register
AD11 register
AD02 register
AD12 register
Decoder
Decoder
AD04 register
AN157
111
Comparator 1
AD00 register
AD03 register
AD0CON0 register
AN155
101
110
CH2 to CH0 bits in
AD0CON0 register
AD13 register
AD14 register
AD05 register
AD15 register
AD06 register
AD16 register
AD07 register
AD17 register
Successive
conversion register
Successive
conversion register
Resistor ladder
AD1CON0 register
Resistor ladder
AD0CON1 register
AD1CON1 register
ØAD1
ØAD0
1
1/3
0
1
1/3
0
1
0
1/2
1
fAD
1/2
1/2
1/2
0
CSK0 bit in AD0CON0 register
CSK1 bit in AD0CON1 register
i=0,1
NOTES:
1. These pins are available in single-chip mode.
2. These pins are provided in the 144-pin package.
Figure 17.1 A/D Converter Block Diagram
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 226 of 488
1
0
1
fAD
(Note 2)
AN154
100
ADS bit in
AD0CON2 register
110
AN7
AN153
011
0
101
AN6
AN152
010
00
100
AN5
AN151
001
011
AN4
AN150
000
11 10
APS1 to APS0 bits in
AD1CON2 register
001
AN2
AN07
111
11
AN0
AN06
110
X1
(Note 1)
AN05
101
01
(Note 1)
0
CSK0 bit in AD1CON0 register
CSK1 bit in AD1CON1 register
17. A/D Converter
M32C/83 Group (M32C/83, M32C/83T)
Table 17.3 Pin Settings
Port
Function
Name
Bit and Setting
PS3(3),
PD10, PD0, PD2,
PD15,
PD9(3)
Registers
PS9
PSL3, IPS
Registers
-
Registers
P100
AN0
PD10_0 = 0
-
P101
AN1
PD10_1 = 0
P102
AN2
PD10_2 = 0
P103
AN3
PD10_3 = 0
P104
AN4
PD10_4 = 0
P105
AN5
PD10_5 = 0
P106
AN6
PD10_6 = 0
P107
AN7
PD10_7 = 0
P00
AN00(1)
PD0_0 = 0
P01
AN01(1)
PD0_1 = 0
P02
AN02(1)
PD0_2 = 0
P03
AN03(1)
PD0_3 = 0
P04
AN04(1)
PD0_4 = 0
P05
AN05(1)
PD0_5 = 0
P06
AN06(1)
PD0_6 = 0
P07
AN07(1)
PD0_7 = 0
P20
AN20(1)
PD2_0 = 0
P21
AN21(1)
PD2_1 = 0
P22
AN22(1)
PD2_2 = 0
P23
AN23(1)
PD2_3 = 0
P24
AN24(1)
PD2_4 = 0
P25
AN25(1)
PD2_5 = 0
P26
AN26(1)
PD2_6 = 0
P27
AN27(1)
PD2_7 = 0
P150
AN150(2)
P151
AN151(2)
P152
AN152(2)
P153
AN15 3(2)
PD15_3 = 0
-
P154
AN154(2)
PD15_4 = 0
PS9_4 = 0
P155
AN155(2)
PD15_5 = 0
PS9_5 = 0
P156
AN156(2)
PD15_6 = 0
-
P157
AN157(2)
PD15_7 = 0
-
P95
ANEX0
PD9_5 = 0
PS3_5 = 0
PSL3_5 = 1
P96
ANEX1
PD9_6 = 0
PS3_6 = 0
PSL3_6 = 1
PD9_7 = 0
PS3_7 = 0
-
PUR0, PUR3,
PUR4 Registers
PU30 = 0
PU31 = 0
-
-
PU00 = 0
PU01 = 0
-
-
PU04 = 0
-
-
PU05 = 0
PD15_0 = 0
PS9_0 = 0
IPS2 = 1
PU42 = 0
PD15_1 = 0
PS9_1 = 0
PD15_2 = 0
PU43 = 0
PU27 = 0
___________
ADTRG
P97
-
NOTES:
1. This pin is available in single-chip mode.
2. This pin is provided in the 144-pin package.
3. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not
generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to set
the PD9 and PS3 registers.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 227 of 488
17. A/D Converter
M32C/83 Group (M32C/83, M32C/83T)
A/D0 Control Register 0(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
AD0CON0
Bit
Symbol
Address
039616
After Reset
0016
Bit Name
Function
RW
b2 b1 b0
CH0
Analog Input Pin
Select Bit(2, 3, 4)
CH1
CH2
0 0 0 : AN0
0 0 1 : AN1
0 1 0 : AN2
0 1 1 : AN3
1 0 0 : AN4
1 0 1 : AN5
1 1 0 : AN6
1 1 1 : AN7
RW
RW
RW
b4 b3
MD0
RW
MD1
0 0 : One-shot mode
A/D Operation
0 1 : Repeat mode
Mode Select Bit 0(2) 1 0 : Single sweep mode
1 1 : Repeat sweep mode 0 or 1
TRG
Trigger Select Bit
0 : Software trigger
1 : External trigger, hardware trigger(5)
RW
ADST
A/D Conversion
Start Flag
0 : A/D conversion stops
1 : A/D conversion starts(5)
RW
CKS0
Frequency Select
Bit(6)
0 : Select from fAD/3 or fAD/4
1 : Select from fAD/1 or fAD/2
RW
RW
NOTES:
1. When the AD0CON0 register is rewritten during the A/D conversion, the conversion result is
indeterminate.
2. Analog input pins must be set again after changing A/D operation mode.
3. This bit is disabled in single sweep mode, repeat sweep mode 0 and repeat sweep mode 1.
4. Set the PSC_7 bit in the PSC register to "1" (AN4 to AN7) to use the P10 pin as a analog input pin.
5. To set the TRG bit to "1", select the cause of trigger by setting the TRG1 and TRG0 bits in the
AD0CON2 register. Then set the ADST bit to "1" after the TRG bit is set to "1".
6. AD frequency must be under 16 MHz when VCC=5V.
AD frequency must be under 10 MHz when VCC=3.3V.
Combination of the CKS0 and CKS1 bits selects AD.
CKS0
CKS1
0
0
fAD divided by 4
0
1
fAD divided by 3
1
0
fAD divided by 2
1
1
fAD
AD
Figure 17.2 AD0CON0 Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 228 of 488
17. A/D Converter
M32C/83 Group (M32C/83, M32C/83T)
A/D0 Control Register 1(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
AD0CON1
039716
Bit
Symbol
After Reset
0016
Bit Name
Function
RW
b0 b1
SCAN0
A/D Sweep Pin
Select Bit(2)
SCAN1
0 0 : AN0, AN1 (AN0)
0 1 : AN0 to AN3 (AN0, AN1)
1 0 : AN0 to AN5 (AN0 to AN2)
1 1 : AN0 to AN7 (AN0 to AN3)
RW
RW
MD2
A/D Operation
Mode Select Bit 1
0 : Any mode other than repeat sweep mode 1
1 : Repeat sweep mode 1
RW
BITS
8/10-bit Mode
Select Bit
0 : 8-bit mode
1 : 10-bit mode
RW
CKS1
Frequency Select
Bit(3)
0 : Select from fAD/2 or fAD/4
1 : Select from fAD/1 or fAD/3
RW
VCUT
VREF Connection
Bit
0 : No VREF connection(4)
1 : VREF connection
RW
b6 b7
OPA0
OPA1
External Op-Amp
Connection Mode
Bit(5)
0 0 : ANEX0 and ANEX1 are not used(6)
0 1 : Signal into ANEX0 is A/D converted
1 0 : Signal into ANEX1 is A/D converted
1 1 : External op-amp connection mode
RW
RW
NOTES:
1. When the AD0CON1 register is rewritten during the A/D conversion, the conversion result is
indeterminate.
2. This bit is disabled in one-shot mode and repeat mode. Pins in parentheses are those most
commonly used in the A/D conversions when the MD2 bit is set to "1".
3. AD frequency must be under 16 MHz when VCC=5V.
AD frequency must be under 10 MHz
when VCC=3.3V. Combination of the CKS0 and CKS1 bits selects AD (see the AD0CON0 register).
4. Do not set the VCUT bit to "0" during the A/D conversion. This is a reference voltage for the A/D0.
It does not affect D/A conversion.
5. In single sweep mode and repeat sweep mode 0 or 1, the OPA1 and OPA0 bits cannot be set to
"012"or "102".
6. When the OPA1 to OPA0 bits is set to "002", set the PSL3_5 bit in PSL3 register to "0" (other than
ANEX0) and the PSL3_6 bit to "0" (other than ANEX1).
Figure 17.3 AD0CON1 Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 229 of 488
17. A/D Converter
M32C/83 Group (M32C/83, M32C/83T)
A/D0 Control Register 2(1)
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0
Symbol
Address
AD0CON2
039416
Bit
Symbol
SMP
(b3 - b1)
ADS
After Reset
X000 00002
Bit Name
Function
RW
A/D Conversion
Method Select Bit
0 : Without the sample and hold function
RW
1 : With the sample and hold function
Reserved Bit
Set to "0"
RW
A/D Channel Replace 0 : Disables channel replacement
1 : Enables channel replacement(5)
Select Bit(2)
RW
b6 b5
TRG0
External Trigger
Request Cause
Select Bit
TRG1
PST
Simultaneous
Start Bit(2, 3, 4)
0 0 : Selects ADTRG
0 1 : Selects a timer B2 interrupt
request of the three-phase motor
control timer functions (after
ICTB2 counter completes
counting)
1 0 : Selects the intelligent I/O group 2
channel 1 interrupt
1 1 : Do not set to this value
RW
RW
When this bit is set to "1", A/D0 and
A/D1 start conversions simultaneously. WO
When read, its content is indeterminate.
NOTES:
1. When the AD0CON2 register is rewritten during the A/D conversion, the conversion result is
indeterminate.
2. Do not set the APS1 and APS0 bits to "1" while either A/D0 or A/D1 is operating.
3. The PST bit is enabled when the TRG bit in the AD0CON0 register is set to "0" (software trigger).
Do not set the PST bit to "1" when the TRG bit is set to "1" (external trigger).
4. Set both A/D0 and A/D1 to the same setting.
5. If the ADS bit is set to "1", do not select single sweep mode or repeat sweep mode as the A/D
operation mode.
A/D0 Register i (i =0 to 7)
b15
b8 b7
b0
Symbol
Address
After Reset
AD00 to AD02
038116 - 038016, 038316 - 038216, 038516 - 038416
038716 - 038616, 038916 - 038816, 038B16 - 038A16
038D16 - 038C16, 038F16 - 038E16
Indeterminate
AD03 to AD05
AD06 to AD07
Indeterminate
Function
RW
8 low-order bits in an A/D conversion result
RO
In 10-bit mode
In 8-bit mode
RO
: 2 high-order bits in an A/D conversion result
: When read, its contents is indeterminate.
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Figure 17.4 AD0CON2 Register, AD00 to AD07 Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Indeterminate
Page 230 of 488
17. A/D Converter
M32C/83 Group (M32C/83, M32C/83T)
A/D1 Control Register 0(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
AD1CON0
Bit
Symbol
Address
01D616
After Reset
0016
Bit Name
Function
RW
b2 b1 b0
CH0
CH1
Analog Input Pin
Select Bit(2, 3, 4, 5, 6)
CH2
0 0 0 : ANi0
0 0 1 : ANi1
0 1 0 : ANi2
0 1 1 : ANi3
1 0 0 : ANi4
1 0 1 : ANi5
1 1 0 : ANi6
1 1 1 : ANi7
RW
RW
(i=0, 2, 15)
b4 b3
MD0
A/D Operation
Mode Select Bit 0(2)
MD1
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode 0 or 1
RW
RW
RW
TRG
Trigger Select Bit
0 : Software trigger
1 : External trigger, hardware trigger(7)
RW
ADST
A/D Conversion
Start Flag
0 : A/D conversion stops
1 : A/D conversion starts(7)
RW
CKS0
Frequency Select
Bit(8)
0 : Select from fAD/3 or fAD/4
1 : Select from fAD/1 or fAD/2
RW
NOTES:
1. When the AD1CON0 register is rewritten during the A/D conversion, the conversion result is
indeterminate.
2. Set analog input pins again after changing A/D operation mode.
3. This bit is disabled in single sweep mode, repeat sweep mode 0 and repeat sweep mode 1.
4. The APS1 to APS0 bit in the AD1CON2 register select i=0, 2 or 15.
5. i=0 or 2 is available in single-chip mode only.
6. i=15 is available in the 144-pin package.
7. To set the TRG bit to "1", select the cause of trigger by setting the the TRG1 and TRG0 bits in the
AD1CON2 register. Then set the ADST bit to "1" after the TRG bit is set to "1".
8. AD frequency must be under 16 MHz when VCC=5V.
AD frequency must be under 10 MHz when VCC=3.3V.
Combination of the CKS0 and CKS1 bits selects AD.
CKS0
CKS1
0
0
fAD divided by 4
0
1
fAD divided by 3
1
0
fAD divided by 2
1
1
AD
Figure 17.5 AD1CON0 Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 231 of 488
fAD
17. A/D Converter
M32C/83 Group (M32C/83, M32C/83T)
A/D1 Control Register 1(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
AD1CON1
Bit
Symbol
Address
01D716
After Reset
XX00 00002
Bit Name
Function
RW
b1 b0
SCAN0
A/D Sweep Pin
Select Bit(2, 3, 4)
RW
0 0 : ANi0,ANi1 (ANi0)
0 1 : ANi0 to ANi3 (ANi0,ANi1)
1 0 : ANi0 to ANi5 (ANi0 to ANi2)
RW
1 1 : ANi0 to ANi7 (ANi0 to ANi3) (i=0, 2, 15)
MD2
A/D Operation
Mode Select Bit 1
0 : Any mode other than repeat sweep
mode 1
1 : Repeat sweep mode 1
RW
BITS
8/10-bit Mode
Select Bit
0 : 8-bit mode
1 : 10-bit mode
RW
CKS1
Frequency Select
Bit(5)
0 : Select from fAD/2 or fAD/4
1 : Select from fAD/1 or fAD/3
RW
VCUT
VREF Connection Bit
0 : VREF not connected(6)
1 : VREF connected
RW
SCAN1
(b7 - b6)
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
NOTES:
1. When the AD1CON1 register is rewritten during the A/D conversion, the conversion result is
indeterminate.
2. This bit is disabled in one-shot mode and repeat mode. Pins in parentheses are those most
commonly used for A/D conversions when the MD2 bit is set to "1" (repeat sweep mode 1).
3. The APS1 to APS0 bits in the AD1CON2 register select i=0, 2 or 15.
4. i=15 is available in the 144-pin package.
5. AD frequency must be under 16 MHz when VCC=5V. AD frequency must be under 10 MHz when
VCC=3.3V. Combination of the CKS0 and CKS1 bits selects AD (see the AD1CON0 register).
6. Do not set the VCUT bit to "0" during the A/D conversion. This is a reference voltage for the A/D1.
It does not affect the D/A conversion.
Figure 17.6 AD1CON1 Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 232 of 488
17. A/D Converter
M32C/83 Group (M32C/83, M32C/83T)
A/D1 Control Register 2(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
AD1CON2
Bit
Symbol
SMP
Address
01D416
After Reset
X00X X0002
Bit Name
A/D Conversion
Method Select Bit
Bit name
RW
0 : Without the sample and hold function
RW
1 : With the sample and hold function
b2 b1
APS0
Analog Input Port
Select Bit
APS1
0 0 : AN150 to AN157(2)
0 1 : Do not set to this value
1 0 : AN00 to AN07(3)
1 1 : AN20 to AN27(3)
RW
RW
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
(b4 - b3)
b6 b5
TRG0
External Trigger
Request Cause
Select Bit
TRG1
(b7)
0 0 : Selects ADTRG
0 1 : Selects a timer B2 interrupt
request of the three-phase motor
control timer functions (after the
ICTB2 counter completes
counting)
1 0 : Selects the Intelligent I/O group 3
channel 1 interrupt
1 1 : Do not set to this value
RW
RW
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
NOTES:
1. When the AD1CON2 register is rewritten during the A/D conversion, the conversion result is
indeterminate.
2. AN150 to AN157 are provided in the 144-pin package.
3. AN00 to AN07, AN20 to AN27 are available in single-chip mode only.
A/D1 Register j (j=0 to 7)
b15
b8 b7
b0
Symbol
AD10 to AD12
Address
01C116 - 01C016, 01C316 - 01C216, 01C516 - 01C416
AD13 to AD15
01C716 - 01C616, 01C916 - 01C816, 01CB16 - 01CA16 Indeterminate
AD16 to AD17
01CD16 - 01CC16, 01CF16 - 01CE16
Function
Indeterminate
RW
8 low-order bits in an A/D conversion result
RO
In 10-bit mode
In 8-bit mode
RO
: 2 high-order bits in an A/D conversion result
: When read, its content is indeterminate.
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Figure 17.7 AD1CON2 Register, AD10 to AD17 Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
After Reset
Indeterminate
Page 233 of 488
17. A/D Converter
M32C/83 Group (M32C/83, M32C/83T)
17.1 Mode Description
17.1.1 One-shot Mode
In one-shot mode, analog voltage applied to a selected pin is converted to a digital code once. Table 17.4
lists specifications of one-shot mode.
Table 17.4 One-shot Mode Specifications
Item
Specification
Function
Analog voltage, applied to a pin selected by the CH2 to CH0 bits in the ADiCON0
register (i=0, 1), is converted to a digital code once.
Start Condition
When the TRG bit in the ADiCON0 register is set to "0" (software trigger),
• The ADST bit in the ADiCON0 register is set to "1" (A/D conversion starts) by
program
• The PST bit in the AD0CON2 register is set to "1" (A/D0 and A/D1 start a
conversion simultaneously) by program
When the TRG bit is set to "1" (external trigger, hardware trigger),
__________
• A falling edge is applied to the AD TRG pin after the ADST bit is set to "1" by
program
• One of the following interrupt requests is generated after the ADST bit is set to
"1" by program:
- The timer B2 interrupt request of three-phase motor control timer functions
(after the ICTB2 counter completes counting) is generated
- The intelligent I/O interrupt request is generated
Channel 1 in the group 2 (A/D0), channel 1 in the group 3 (A/D1)
• A/D conversion is completed (the ADST bit is set to "0" when the internal trigger is
Stop Condition
selected)
• The ADST bit is set to "0" (A/D conversion stopped) by program
Interrupt Request Generation Timing A/D conversion is completed
Analog Voltage Input Pins
Select one from AN0 to AN7, ANEX0, or ANEX1
Select one from ANj0 to ANj7 (j=0, 2, 15)
Reading of A/D Conversion Result
The ADik register (k=0 to 7) corresponding to selected pin
17.1.2 Repeat Mode
In repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code. Table
17.5 lists specifications of repeat mode.
Table 17.5 Repeat Mode Specifications
Item
Specification
Function
Analog voltage, applied to a pin selected by the CH2 to CH0 bits in the ADiCON0
register (i=0, 1), is converted to a digital code once.
Start Condition
Stop Condition
Same as one-shot mode
The ADST bit in the ADiCON0 register is set to "0" (A/D conversion stopped) by
program
Interrupt Request Generation Timing Not generated
Analog Voltage Input Pins
Select one from AN0 to AN7, ANEX0, or ANEX1
Select from ANj0 to ANj7 (j=0, 2, 15)
Reading of A/D Conversion Result The ADik register (k=0 to 7) corresponding to selected pins
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 234 of 488
17. A/D Converter
M32C/83 Group (M32C/83, M32C/83T)
17.1.3 Single Sweep Mode
In single sweep mode, analog voltage that is applied to selected pins is converted one-by-one to a digital
code. Table 17.6 lists specifications of single sweep mode.
Table 17.6 Single Sweep Mode Specifications
Item
Specification
Function
Analog voltage, applied to pins selected by the SCAN1 to SCAN0 bits in the
Start Condition
Same as one-shot mode
Stop Condition
• A/D conversion is completed (the ADST bit in the ADiCON0 register is set to "0"
ADiCON0 register (i=0, 1), are converted one-by-one to a digital code
when the internal trigger is selected)
• The ADST bit is set to "0" (A/D conversion stopped) by program
Interrupt Request Generation Timing Sweep operation is completed
Analog Voltage Input Pins
Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), AN0 to
AN7 (8 pins)
Select from ANj0 (j=0, 2, 15) to ANj1 (2 pins), ANj0 to ANj3 (4 pins), ANj0 to ANj5 (6
pins), or ANj0 to ANj7 (8 pins)
Reading of A/D Conversion Result The ADik register (k=0 to 7) corresponding to selected pins
17.1.4 Repeat Sweep Mode 0
In repeat sweep mode 0, analog voltage applied to selected pins is repeatedly converted to a digital code.
Table 17.7 lists specifications of repeat sweep mode 0.
Table 17.7 Repeat Sweep Mode 0 Specifications
Item
Specification
Function
Analog voltage, applied to pins selected by the SCAN1 to SCAN0 bits in the
Start Condition
Same as one-shot mode
Stop Condition
The ADST bit in the ADiCON0 register is set to "0" (A/D conversion stopped) by program
ADiCON0 register (i=0, 1), are repeatedly converted to a digital code
Interrupt Request Generation Timing Not generated
Analog Voltage Input Pins
Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), AN0 to
AN7 (8 pins)
Select from ANj0 (j=0, 2, 15) to ANj1 (2 pins), ANj0 to ANj3 (4 pins), ANj0 to ANj5 (6
pins), or ANj0 to ANj7 (8 pins)
Reading of A/D Conversion Result The ADik register (k=0 to 7) corresponding to selected pins
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 235 of 488
17. A/D Converter
M32C/83 Group (M32C/83, M32C/83T)
17.1.5 Repeat Sweep Mode 1
In repeat sweep mode 1, analog voltage selectively applied to eight pins is repeatedly converted to a
digital code. Table 17.8 lists specifications of repeat sweep mode 1.
Table 17.8 Repeat Sweep Mode 1 Specifications
Item
Specification
Function
Analog voltage selectively applied to 8 pins selected by the SCAN1 to SCAN0 bits
in the ADiCON1 register (i=0,1) is repeatedly converted to a digital code.
e.g., When ANj0 is selected (j =none, 0, 2, 15), analog voltage is converted to a
digital code in the following order:
ANj0 ANj1 ANj0
Same as one-shot mode
Start Condition
Stop Condition
ANij2
ANj0
ANj3 ....... etc.
The ADST bit in the ADiCON1 register is set to "0" (A/D conversion stopped) by
program
Interrupt Request Generation Timing Not generated
Analog Voltage Input Pins
ANj0 to ANj7 (8 pins)
Prioritized Pins
Select from AN0 (1 pin), AN0 to AN1 (2 pins), AN0 to AN2 (3 pins), or AN0 to AN3 (4
pins)
Select from ANj0 (j=0, 2, 15) (1 pin), ANj0 to ANj1 (2 pins), AN0 to AN2 (3 pins),
ANj0 to ANj3 (4 pins)
Reading of A/D Conversion Result The ADik register (k=0 to 7) corresponding to selected pins
17.2 Function
17.2.1 Resolution Select Function
The BITS bit in the ADiCON1 (i=0, 1) register determines the resolution. When the BITS bit is set to "1"
(10-bit precision), the A/D conversion result is stored into bits 0 to 9 in the ADij register (j = 0 to 7). When
the BITS bit is set to "0" (8-bit precision), the A/D conversion result is stored into bits 0 to 7 in the ADij
register.
17.2.2 Sample and Hold
When the SMP bit in the ADiCON2 register is set to "1" (with the sample and hold function), A/D conversion rate per pin increases to 28 ØAD cycles for 8-bit resolution and 33 ØAD cycles for 10-bit resolution.
The sample and hold function is available in all operating modes. Start the A/D conversion after selecting
whether the sample and hold function is to be used or not.
17.2.3 Trigger Select Function
The TRG bit in the ADiCON0 register and the TRG1 to TRG0 bits in the ADiCON2 register determine the
trigger to start the A/D conversion. Table 17.9 lists settings of the trigger select function.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 236 of 488
17. A/D Converter
M32C/83 Group (M32C/83, M32C/83T)
Table 17.9 Trigger Select Function Settings
Bit and Setting
ADiCON0 Register
TRG = 0
Trigger
ADiCON2 Register
-
Software trigger
The A/Di starts the A/D conversion when the ADST bit in the
ADiCON0 register is set to "1"
-
Two-circuit simultaneous start
A/D0 and A/D1 start the A/D conversion simultaneously when the
PST bit in the AD0CON2 register is set to "1" by program (Refer to
17.2.4 Two-Circuit Simultaneous Start)
TRG =
1(1)
TRG1 to TRG0 = 002
External trigger(2)
__________
Falling edge of a signal applied to ADTRG
TRG1 to TRG0 = 012
Hardware trigger(2)
The timer B2 interrupt request of three-phase motor control timer
functions (after the ICTB2 counter completes counting)
TRG1 to TRG0 = 102
Hardware trigger(2)
The intelligent I/O interrupt request is generated
Channel 1 in the group 2 (A/D0), channel 1 in the group 3 (A/D1)
i= 0,1
NOTES:
1. The A/Di starts the A/D conversion when the ADST bit is set to "1" (A/D conversion started) and a trigger is
generated.
2. The A/D conversion is restarted if an external trigger or a hardware trigger is inserted during the A/D conversion.
(The A/D conversion in process is aborted.)
17.2.4 Two-Circuit Simultaneous Start (Software Trigger)
A/D0 and A/D1 start simultaneously when the PST bit in the AD0CON2 register is set to "1" (two-circuit
simultaneous start).
Do not set the PST bit to "1" while either A/D0 or A/D1 is performing an A/D conversion, or if the TRG bit
is set "1" (external trigger).
Do not set the ADST bit to "1" (A/D conversion started) when using the PST bit.
17.2.5 Pin Input Replacement Function
When the ADS bit in the AD0CON2 register is set to "1" (channel replacement enabled), channels of the
A/D0 can be replaced with channels of the A/D1 and vice versa.
Voltage applied to the ANj (j = 0 to 7) pin is converted to digital code in the A/D1 and the conversion result
is stored into the AD1j register. Voltage applied to the AN0j, AN2j or AN15j pin is converted to digital code
in the A/D0 and the conversion results are stored into the AD0j register.
To set the ADS bit to "1", set the MD1 to MD0 bits in the AD0CON0 register to "002" (one-shot mode) or
"012" (repeat mode). Single sweep, repeat sweep 0, and repeat sweep 1 modes cannot be used. Set the
OPA1 to OPA0 bits in the AD0CON1 register to "002" (no ANEX0 and ANEX1 used). Set the same value to
both AD0CON0 register and AD1CON0 register, and to both AD0CON1 register and AD1CON1 register.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 237 of 488
17. A/D Converter
M32C/83 Group (M32C/83, M32C/83T)
17.2.6 Extended Analog Input Pins
In one-shot mode and repeat mode, the ANEX0 and ANEX1 pins can be used as analog input pins. The
OPA1 to OPA0 bits in the AD0CON1 register select which pins to use as analog input pins. An A/D
conversion result for the ANEX0 pin is stored into the AD00 register. The result for the ANEX1 pin is
stored into the AD01 register.
17.2.7 External Operation Amplifier (Op-Amp) Connection Mode
In external op-amp connection mode, multiple analog voltage can be amplified by one external op-amp
using extended analog input pins ANEX0 and ANEX1.
When the OPA1 to OPA0 bits in the AD0CON1 register are set to "112" (external op-amp connection),
voltage applied to the AN0 to AN7 pins are output from ANEX0. Amplify this output signal by an external
op-amp and apply it to ANEX1.
Analog voltage applied to ANEX1 is converted to a digital code and the A/D conversion result is stored
into the corresponding ADij register (i=0, 1; j=0 to 7). A/D conversion rate varies depending on the
response of the external op-amp. Do not connect the ANEX0 pin to the ANEX1 pin directly.
Figure 17.8 shows an example of an external op-amp connection.
Table 17.10 Extended Analog Input Pin Settings
AD0CON1 Register
ANEX0 Function
ANEX1 Function
OPA1
OPA0
0
0
Not used
Not used
0
1
P95 as an analog input
Not used
1
0
Not used
P96 as an analog input
1
1
Output to an external op-amp
Input from an external op-amp
Microcomputer
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Analog
input
Resistor ladder
Successive conversion register
ANEX0
ANEX1
External op-amp
Figure 17.8 External Op-Amp Connection
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 238 of 488
Comparator
17. A/D Converter
M32C/83 Group (M32C/83, M32C/83T)
17.2.8 Power Consumption Reducing Function
When the A/D converter is not used, the VCUT bit in the ADiCON1 register (i=0, 1) isolates the resistor
ladder of the A/D converter from the reference voltage input pin (VREF). Power consumption is reduced by
shutting off any current flow into the resistor ladder from the VREF pin.
When using the A/D converter, set the VCUT bit to "1" (VREF connection) before setting the ADST bit in
the ADiCON0 register to "1" (A/D conversion started). Do not set the ADST bit and VCUT bit to "1"
simultaneously, nor set the VCUT bit to "0" (no VREF connection) during the A/D conversion. The VCUT
bit does not affect the VREF performance of the D/A converter.
17.2.9 Analog Input Pin and External Sensor Equivalent Circuit
Figure 17.9 shows an example of the analog input pin and external sensor equivalent circuit.
Microcomputer
Sensor equivalent
circuit
R0
R (7.8k
)
Sampling time
(the time needed until the capacitor is fully
charged after closing switch)
VIN
C (2.0pF)
VC
3
Sample and hold function is enabled : φAD
2
Sample and hold function is disabled : φAD
Figure 17.9 Analog Input Pin and External Sensor Equivalent Circuit
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 239 of 488
18. D/A Converter
M32C/83 Group (M32C/83, M32C/83T)
18. D/A Converter
The D/A converter consists of two separate 8-bit R-2R ladder D/A converters.
Digital code is converted to an analog voltage when a value is written to the corresponding DAi registers
(i=0,1). The DAiE bit in the DACON register determines whether the D/A conversion result is output or not.
Set the DAiE bit to "1" (output enabled) to disable a pull-up of a corresponding port.
Output analog voltage (V) is calculated from value n (n=decimal) set in the DAi register.
V = VREF x n (n = 0 to 255)
256
VREF : reference voltage (not related to VCUT bit setting in the ADiCON1 register)
Table 18.1 lists specifications of the D/A converter. Table 18.2 lists pin settings of the DA0 and DA1 pins.
Figure 18.1 shows a block diagram of the D/A converter. Figure 18.2 shows the D/A control register. Figure
18.3 shows a D/A converter equivalent circuit.
When the D/A converter is not used, set the DAi register to "0016" and the DAiE bit to "0" (output disabled).
Table 18.1 D/A Converter Specifications
Item
D/A Conversion Method
Resolution
Analog Output Pin
Specification
R-2R
8 bits
2 channels
Table 18.2 Pin Settings
Port
Function
Bit and Setting
PD9
Register(1)
PS3 Register(1)
PSL3 Register
P93
DA0 output
PD9_3=0
PS3_3=0
PSL3_3=1
P94
DA1 output
PD9_4=0
PS3_4=0
PSL3_4=1
NOTES:
1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write
enable). Do not generate an interrupt or a DMA transfer between the instruction to set the PRC2 bit to "1"
and the instruction to set the PD9 and PS3 registers.
Rev. 1.31 Jan.31, 2006 Page 240 of 488
REJ09B0034-0131
M32C/83 Group (M32C/83, M32C/83T)
18. D/A Converter
A
Low-Order Bits of Data Bus
DA0 Register
DA0E 0
R-2R Resistor Ladder
A
DA0
1
DA1 Register
DA1E 0
R-2R Resistor Ladder
DA1
1
DA0E, DA1E: Bits in the DACON register
Figure 18.1 D/A Converter
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 241 of 488
18. D/A Converter
M32C/83 Group (M32C/83, M32C/83T)
D/A Control Register
b7
b6
b5
b4
b3
b2
b1
Symbol
DACON
b0
Address
039C16
After Reset
XXXX XX002
Bit
Symbol
Bit Name
DA0E
D/A0 Output Enable Bit
0 : Disables an output
1 : Enables an output
RW
DA1E
D/A1 Output Enable Bit
0 : Disables an output
1 : Enables an output
RW
Function
RW
Nothing is assigned. When write, set to "0".
(b7 - b2) When read, its content is indeterminate.
D/A Register i (i=0, 1)
b7
b0
Symbol
DA0, DA1
Address
039816, 039A16
After Reset
Indeterminate
Function
Output value of D/A conversion
Setting Range
RW
0016 to FF16
RW
Figure 18.2 DACON Register, DA0 and DA1 Registers
DA0E
r
"0"
R
R
R
R
R
R
R
2R
DA0
"1"
2R
2R
2R
2R
2R
2R
2R
LSB
MSB
D/A register 0
2R
0
1
AVSS
VREF(4)
NOTES:
1. The above applies when the DA0 register is set to "2A16".
2. This circuitry is the same for D/A1.
3. To reduce power consumption when the D/A converter is not used, set the DAiE bit (i=0, 1) to "0"
(output disabled) and the DAi register to "0016" to stop current from flowing into the R-2R resistor.
4. This VREF is not related to VCUT bit setting in the AD0CON1 and AD1CON1 registers.
Figure 18.3 D/A Converter Equivalent Circuit
Rev. 1.31 Jan.31, 2006 Page 242 of 488
REJ09B0034-0131
M32C/83 Group (M32C/83, M32C/83T)
19. CRC Calculation
19. CRC Calculation
The CRC (Cyclic Redundancy Check) calculation detects an error in data blocks. A generator polynomial
of CRC_CCITT (X16 + X12 + X5 + 1) generates CRC code.
The CRC code is a 16-bit code generated for a block of data of desired length. This block of data is in 8-bit
units. The CRC code is set in the CRCD register every time one-byte data is transferred to the CRCIN
register after a default value is written to the CRCD register. CRC code generation for one-byte data is
completed in two cycles.
Figure 19.1 shows a block diagram of a CRC circuit. Figure 19.2 shows registers related to CRC. Figure
19.3 shows an example of the CRC calculation.
High-order bits of data bus
AAA
AAAA AAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAA
AAAAAA
Low-order bits of data bus
8 low-order bits
8 highorder bits
CRCD register
CRC code generation circuit
x16 + x12 + x5 + 1
CRCIN register
Figure 19.1 CRC Calculation Block Diagram
CRC Data Register
b15
b8 b7
b0
Symbol
Address
After Reset
CRCD
037D16- 037C16
Indeterminate
Function
Setting Range
RW
After default value is written to the CRCD
register, the CRC code can be read from the
CRCD register by writing data to the CRCIN
register. Bit position of the default value is
inversed. The inversed value is read as the CRC
code.
000016 to FFFF16
RW
CRC Input Register
b7
b0
Symbol
CRCIN
Address
037E16
Function
Data input.
Inverse bit position of data.
Figure 19.2 CRCD Register and CRCIN Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 243 of 488
After Reset
Indeterminate
Setting Range
RW
0016 to FF16
RW
19. CRC Calculation
M32C/83 Group (M32C/83, M32C/83T)
CRC Calculation and Setup Procedure to Generate CRC Code for "80C416"
CRC Calculation for M32C
value of the CRCIN register with inversed bit position
generator polynomial
CRC Code : a remainder of a division,
Generator Polynomial : X
16
12
+X
5
+ X + 1 (1 0001 0000 0010 00012)
Setting Steps
(1) Inverse a bit position of "80C416" per byte by program
"8016"
"0116", "C416"
"2316"
b15
b0
(2) Set "000016" (default value)
CRCD register
b7
b0
CRCIN register
Bit position of the CRC code for "8016"
(918816) is inversed to "118916", which is
stored into the CRCD register in 3rd cycle.
(3) Set "0116"
b15
b0
CRCD register
118916
b7
b0
CRCIN register
Bit position of the CRC code for "80C416"
(825016) is inversed to "0A4116", which is
stored into the CRCD register in 3rd cycle.
(4) Set "2316"
b15
b0
0A4116
CRCD register
Details of CRC Calculation
As shown in (3) above, bit position of "0116" (000000012) written to the CRCIN register is inversed and becomes
"100000002".
Add "1000 0000 0000 0000 0000 00002", as "100000002" plus 16 digits, to "000016" as the default value of the
CRCD register to perform the modulo-2 division.
1000 1000
Modulo-2 Arithmetic is
data
1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000
calculated on the law below.
1000 1000 0001 0000 1
0+0=0
1000 0001 0000 1000 0
0+1=1
Generator Polynomial
1000 1000 0001 0000 1
1+0=1
1001 0001 1000 1000
1+1=0
-1=1
CRC Code
"0001 0001 1000 10012 (118916)", the remainder "1001 0001 1000 10002 (918816)" with inversed bit position, can
be read from the CRCD register.
When going on to (4) above, "2316 (001000112)" written in the CRCIN register is inversed and becomes
"110001002".
Add "1100 0100 0000 0000 0000 00002", as "110001002" plus 16 digits, to "1001 0001 1000 10002" as a
remainder of (3) left in the CRCD register to perform the modulo-2 division.
"0000 1010 0100 00012 (0A4116)", the remainder with inversed bit position, can be read from CRCD register.
Figure 19.3 CRC Calculation
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 244 of 488
M32C/83 Group (M32C/83, M32C/83T)
20. XY Conversion
20. X/Y Conversion
The X/Y conversion rotates a 16 x 16 matrix data by 90 degrees and inverses high-order bits and low-order
bits of a 16-bit data. Figure 20.1 shows the XYC register.
The 16-bit XiR register (i=0 to 15) and 16-bit YjR register (j=0 to 15) are allocated to the same address. The
XiR register is a write-only register, while the YjR register is a read-only register. Access the XiR and YjR
registers from an even address in 16-bit units. Performance cannot be guaranteed if the XiR and YiR
registers are accessed in 8-bit units.
X/Y Control Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
XYC
02E016
Bit
Symbol
Bit Name
Function
RW
XYC0
Read-Mode Set Bit
0 : Data conversion
1 : No data conversion
RW
XYC1
Write-Mode Set Bit
0 : No bit alignment conversion
1 : Bit alignment conversion
RW
(b7 - b2)
Figure 20.1 XYC Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
After Reset
XXXX XX002
Page 245 of 488
Noting is assigned. When write, set to "0".
When read, its content is indeterminate.
20. XY Conversion
M32C/83 Group (M32C/83, M32C/83T)
The XYC0 bit in the XYC register determines how to read the YjR register.
By reading the YjR register when the XYC0 bit is set to "0" (data conversion), bit j in the X0R to X15R
registers can be read simultaneously.
For example, bit 0 in the X0R register can be read if reading bit 0 in the Y0R register, bit 0 in the X1R
register if reading bit 1 in the Y0R register..., bit 0 in the X14R register if reading bit 14 in the Y0R register
and bit 0 in the X15R register if reading bit 15 in the Y0R register.
Figure 20.2 shows the conversion table when the XYC0 bit is set to "0". Figure 20.3 shows an example of
the X/Y conversion.
Y15R register
Y14R register
Y13R register
Y12R register
Y11R register
Y10R register
Y9R register
Y8R register
Y7R register
Y6R register
Y5R register
Y4R register
Y3R register
Y2R register
Y1R register
Y0R register
Address to be read
b15
b0
Bits in the YjR register
b0
AA
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
AA
A
AAA
A
AA
AA
A
AAA
A
AA
b15
Address to
be written
X0R register
X1R register
X2R register
X3R register
X4R register
X5R register
X6R register
X7R register
X8R register
X9R register
X10R register
X11R register
X12R register
X13R register
X14R register
X15R register
Bits in the XiR register
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Figure 20.2 Conversion Table when Setting the XYC0 Bit to "0"
X0R register
X1R register
X2R register
Y0R register
Y1R register
Y2R register
X3R register
X4R register
X5R register
X6R register
X7R register
X8R register
Y3R register
Y4R register
Y5R register
Y6R register
Y7R register
Y8R register
X9R register
X10R register
X11R register
X12R register
X13R register
X14R register
X15R register
Y9R register
Y10R register
Y11R register
Y12R register
Y13R register
Y14R register
Y15R register
Figure 20.3 X/Y Conversion
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 246 of 488
AA
AA
AA
AAA
AA
AA
AA
AA
AA
AA
AA
A
AA
AA
AA
A
AA
AA
AA
AA
AA
AA
AA
AA
AAA
AA
A
M32C/83 Group (M32C/83, M32C/83T)
20. XY Conversion
By reading the YjR register when the XYC0 bit in the XYC register is set to "1" (no data conversion), the
value written to the XiR register can be read directly. Figure 20.4 shows the conversion table when the
XYC0 bit is set to "1."
Address to be written
Address to be read
A
AA
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
X0R register, Y0R register
X1R register, Y1R register
X2R register, Y2R register
X3R register, Y3R register
X4R register, Y4R register
X5R register, Y5R register
X6R register, Y6R register
X7R register, Y7R register
X8R register, Y8R register
X9R register, Y9R register
X10R register, Y10R register
X11R register, Y11R register
X12R register, Y12R register
X13R register, Y13R register
X14R register, Y14R register
X15R register, Y15R register
b15
b0
Bits in the XiR register
Bits in the YjR register
i=0 to 15
j=0 to 15
Figure 20.4 Conversion Table when Setting the XYC0 Bit to "1"
The XYC1 bit in the XYC register selects bit alignment of the value in the XiR register.
By writing to the XiR register while the XYC1 bit is set to "0" (no bit alignment conversion), bit alignment is
written as is. By writing to the XiR register while the XYC1 bit is set to "1" (bit sequence replaced), bit
alignment is written inversed.
Figure 20.5 shows the conversion table when the XYC1 bit is set to "1".
b15
b0
b15
b0
Data to be written
Bits in XiR register
(i=0 to 15)
Figure 20.5 Conversion Table when Setting the XYC1 Bit to "1"
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 247 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O
21. Intelligent I/O
The intelligent I/O is a multifunctional I/O port for time measurement, waveform generation, clock synchronous serial I/O, clock asynchronous serial I/O (UART), IEBus(1) communications, HDLC data processing
and more.
The intelligent I/O consists of four groups. Each group has one 16-bit base timer for free-running operation,
eight 16-bit registers for time measurement and waveform generation and two 8-bit shift registers (or one
16-bit shift register) for communications.
Table 21.1 lists functions and channels of the intelligent I/O.
NOTES:
1. IEBus is a trademark of NEC Electronics Corporation.
Table 21.1 Intelligent I/O Functions and Channels
Function
Group 0
Time Measurement(1)
8 channels
4 channels
(3 channels)(2) (2 channels)
Digital Filter
8 channels
(3 channels)
Trigger Input Prescaler
2 channels
Trigger Input Gate
Waveform Generation
Group 1
Group 2
2 channels
2 channels
8 channels
(3 channels)
Available
Available
Group 0, 1
cascaded
8 channels
(3 channels)
4 channels
Not
(2 channels) Available
2 channels
4 channels
(2 channels)
Group 3
Not
Available
8 channels
(3 channels)
2 channels
2 channels
8 channels
8 channels 8 channels
(3 channels) (2 channels) (3 channels)
Single-phase Waveform Output
Phase-delayed Waveform Output
SR Waveform Output
Available
Bit Modulation PWM Mode
Not
Available
RTP Mode
Available
Available
Not
Available
Not
Available
Parallel RTP Mode
Communication
8 bits fixed
Clock Synchronous Serial I/O Mode
UART Mode
Available
HDLC Data Processing Mode
IEBus Mode
Not Available
Variable
8 or 16 bits
Available
Available
Not
Available
Not
Available
Not
Available
Not
Available
Available
NOTES:
1. Time measurement function and waveform generation function share pins
2. The number of channels available in the 100-pin package are indicated in parentethese ( ).
The time measurement function and waveform generation function can be selected for each channel.
The communication function is available by a combination of multiple channels.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 248 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O
Figures 21.1 to 21.4 show block diagram of the intelligent I/O groups 0 to 3.
Request by matching the base timer with the G0PO0 register
Request from the group1
Request from the INT pin
BT0S
BTS
BCK1 to BCK0
00
10 : fBT0
Digital 11 : f1
filter
DF1 to DF0
10 : fBT0 00
11
:
f1
Digital
filter
DF1 to DF0
00
10 : fBT0
Digital 11 : f1
filter
DF1 to DF0
00
10 : fBT0
Digital 11 : f1
filter
DF1 to DF0
00
10 : fBT0
Digital 11 : f1
filter
DF1 to DF0
00
10 : fBT0
Digital 11 : f1
filter
DF1 to DF0
INPC00
INPC01
/ ISCLK0
INPC02
/ ISRxD0
INPC03
INPC04
(Note 1)
INPC05
00
10 : fBT0
Digital 11 : f1
filter
DF1 to DF0
00
10 : fBT0
Digital 11 : f1
filter
DF1 to DF0
INPC06
INPC07
fBT0
Divider
by 2(n+1)
DIV4 to DIV0
10
Two-phase
pulse signal
is applied
Group0 base timer reset
Reset
11
f1
Base timer
Base timer interrupt request(3)
Overflow of base timer bit 15
Edge
select
CTS1 to CTS0
G0TM0, G0PO0
register
Edge
select
CTS1 to CTS0
G0TM1, G0PO1
register
Edge
select
CTS1 to CTS0
G0TM2, G0PO2
register
000 to 010
PWM
output
MOD2 to MOD0
OUTC00/ISTxD0
111
000 to 010
111
MOD2 to MOD0
OUTC01/ISCLK0
PWM
output
G0TM3, G0PO3
register
Edge
select
CTS1 to CTS0
G0TM4, G0PO4
register
Edge
select
(Note 1)
G0TM5, G0PO5
register
Edge
select
CTS1 to CTS0
0
Prescaler
function 1
Gate
Edge
function 1
select
GT
CTS1 to CTS0
Prescaler
function 1
G0TM6, G0PO6
register
PR
0
0
G0TM7, G0PO7
register
PR
Ch0 to ch7
interrupt request signal
Waveform generation match
signal for group1
(For cascaded connection)
Time measurement trigger
for the group1
(For cascaded connection)
Transmit interrupt request
G0TB register
(Transmit buffer register)
SOF
generation circuit
Transmit
buffer
Bit insert circuit
Transmit
register
Transmit latch
Clock wait
control
circuit
OUTC05
0
Edge
Gate
select
function 1
GT
CTS1 to CTS0
ch0
Transmit
ch3
Clock operation clock
External clock selector
OUTC04
PWM
output
CTS1 to CTS0
Transmit data
generation circuit
Transmission
(SIO0TR)(3)
G0TCRC
register
Start bit
generation circuit
TXSL
Data
selector
0
1
Polarity
inverse
OPOL
G0TO register
Stop bit
generation circuit
Transmit
register
ch1
ch2
Clock
ch3 selector
External clock
HDLC data transmit
interrupt request
(G0TOR)(3)
Transmit
buffer
Receive operation clock
Arbitration
Receive
buffer
Receive
register
Receive data
generation circuit
G0RCRC
register
G0RI register
Bit insert
check
0
Polarity
inverse
1
RXSL
IPOL
G0DR register
(Receive data register)
Shift
register
Data
selector
Start bit
check
Stop bit
check
Buffer
register
G0CMP3 register
G0CMP3 register
G0CMP3 register
G0CMP3 register
Reception
G0RB register
Receive
buffer
Receive interrupt request
(SIO0RR)(3)
Receive
register
Special
interrupt
check
Special communication
interrupt request
(SRT0R)(3)
Comparator
Comparator
Comparator
Comparator
HDLC data receive
interrupt request
NOTES:
1. These pins are not connected to external pins in the 100-pin package.
2. Each register enters a reset state after the G0BCR0 register supplies the
clock.
3. See Figure 10.14.
(G0RIR)
DIV4 to DIV0 bits, BCK1 to BCK0 bits : Bits in the G0BCR0 register
BTS : Bit in the G0BCR1 register
BT0S : Bit in BTSR register
CTS1 to CTS0, DF1 to DF0, GT, PR : Bits in the G0TMCRj register (j = 0 to 7)
MOD2 to MOD0 : Bits in the G0POCRj register
TXSL, RXSL : Bits in the G0EMR register
OPOL, IPOL : Bits in the G0CR register
Figure 21.1 Intelligent I/O Group 0 Block Diagram
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 249 of 488
(3)
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O
Request by matching the base timer with the G1PO0 register
Request from the group0
Request from the INT pin
BT1S
BTS
Group1 base timer reset
overflow of bit 15 in
the group0 base timer
BCK1 to BCK0
f1
11
Two-phase pulse
signal is applied
10
1
fBT1
Divider
by 2(n+1)
DIV4 to DIV0
Base timer
0
Base timer interrupt request (BT1R)
(4)
Overflow of bit 15 in the base timer
Waveform generation match signal from
the group 0 (For cascaded connection)
Time measurement trigger from
the group 0 (For cascaded connection)
1
INPC11 /
ISCLK1
INPC12 /
ISRxD1
00
10 : fBT1
Digital 11 : f1
filter
DF1 to DF0
00
10 : fBT1
Digital 11 : f1
filter
DF1 to DF0
G1TM0, G1PO0
(Note 1)
register
0
1
1
1
(Note 2)
00
INPC17
10 : fBT1
Digital 11 : f1
filter
DF1 to DF0
Edge
select
G1TM5, G1PO5
register
OUTC15
(Note 2)
0
1
Gate
1
function
OUTC14
PWM
output
1
0
OUTC13
G1TM4, G1PO4
register
0
Gate
Edge
function
select
CTS1 to CTS0
OUTC12
G1TM3, G1PO3
register
0
10 : fBT1
Digital 11 : f1
filter
DF1 to DF0
OUTC11/ISCLK1
MOD2
to MOD0
PWM
output
CTS1 to CTS0
0
INPC16
000 to 010
111
G1TM2, G1PO2
register
0
00
OUTC10/ISTxD1/
BE1OUT
111
G1TM1, G1PO1
register
0
Edge
select
MOD2 to MOD0
PWM
output
1
Edge
select
CTS1 to CTS0
000 to 010
GT
Prescaler
function
0
1
PR
0
G1TM6, G1PO6
register
1
GT
Prescaler
function
0
1
PR
CTS1 to CTS0
OUTC16
PWM
output
0
G1TM7, G1PO7
register
1
OUTC17
CAS
Ch0 to ch7
interrupt request signal
Transmit interrupt request
(SIO1TR)(4)
G1TB register
(Transmit buffer register)
ch0
ch3
External clock
ch1
ch2
ch3
External clock
Transmit
Clock operation clock
selector
SOF
generation circuit
Transmit
buffer
Bit insert circuit
Transmit
register
Transmit latch
Clock wait
control
circuit
Transmit data
generation circuit
G1TCRC
register
Start bit
generation circuit
Transmission
TXSL
0
Data
selector
1
Polarity
inverse
OPOL
G1TO register
Stop bit
generation circuit
Transmit
register
HDLC data transmit
interrupt request
(G1TOR)(4)
Clock
selector
Transmit
buffer
Receive operation clock
Arbitration
Receive
buffer
Bit insert
check
0
Receive
register
Receive data
generation circuit
G1RCRC
register
G1RI register
Polarity
inverse
1
RXSL
IPOL
G1DR register
(Receive data register)
Shift
register
Data
selector
Start bit
check
Stop bit
check
buffer
register
G1CMP3 register
G1CMP3 register
G1CMP3 register
G1CMP3 register
Reception
G1RB register
Receive
buffer
Receive interrupt
request
(SIO1RR)(4)
Receive
register
Special
interrupt
check
Special communication
interrupt request
(SRT1R)(4)
Comparator
Comparator
Comparator
Comparator
HDLC data receive
interrupt request
NOTES:
1. The G1TM0 register can be used in a 32-bit cascaded connection only.
2. These pins are not connected to external pins in the 100-pin package.
3. Each register is in a reset state after the G1BCR0 register supplies the
clock.
4. See Figure 10.14.
Figure 21.2 Intelligent I/O Group 1 Block Diagram
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 250 of 488
(G1RIR)(4)
DIV4 to DIV0, BCK1 to BCK0 : Bits in the G1BCR0 register
CAS, BTS : Bits in the G1BCR1 register
BT1S : Bit in the BTSR register
CTS1 and CTS0, DF1 and DF0, GT, PR : Bits in the G1TMCRj register (j = 0 to 7)
MOD2 to MOD0 : Bits in the G1POCRj register
TXSL, RXSL : Bits in the G1EMR register
M32C/83 Group (M32C/83, M32C/83T)
Request from the group1
Request from the communication function
Request by matching the base
timer with the G2PO0 register
BT2S
BTS
Group2 base
timer reset
BCK1 to BCK0
f1
Divider fBT2
by 2(n+1)
11
21. Intelligent I/O
Base timer
Base timer interrupt request BT2R(3)
DIV4 to DIV0
Real time port
output value
Overflow of bit 15
in the base timer
G2PO0 register
ISCLK2
000 to 010, MOD2 to MOD0
100
OUTC20
Bit modulation
PWM
PWM
output
control
0
IEIN /ISRxD2
Digital
filter
1
G2PO1 register
DF
Bit modulation
PWM
/ISTxD2/IEOUT
111
000 to 010, MOD2 to MOD0
100
OUTC21
/ISCLK2
111
G2PO2 register
Bit modulation
PWM
G2PO3 register
Bit modulation
PWM
G2PO4 register
Bit modulation
PWM
G2PO5 register
Bit modulation
PWM
G2PO6 register
Bit modulation
PWM
G2PO7 register
OUTC22
PWM
output
control
OUTC23
OUTC24
PWM
output
control
OUTC25
(Note 1)
OUTC26
PWM
output
control
Bit modulation
PWM
OUTC27
Waveform generation
interrupt request
PO2jR(3)
G2TB register
Clock
selector
Bit
counter
Transmit register
Output control
function
OPOL
Transmit parity
calculation
Transmit
latch
Polarity
inverse
Byte counter
Arbitration
lost detection
ACK calculation
Start bit
detection
IPOL
IE start bit interrupt request (IE0R to IE2R)(3)
Receive parity
calculation
IE, serial I/O
interrupt control
Polarity
inverse
Receive register
ID detection
G2RB register
IE transmit interrupt request (IE0R to IE2R)(3)
IE receive interrupt request (IE0R to IE2R)(3)
Clock synchronous serial I/O
mode transmit interrupt request (SIO2TR)(3)
Clock synchronous serial I/O
mode receive interrupt request (SIO2RR)(3)
Statement length
detect function
ALL "F" detection
Address detect
function
NOTES:
1. In the 100-pin package, these pins are not connected to external pins.
2. Each register enters a reset state after the G2BCR0 register supplies the
clock.
3. See Figure 10.14.
Figure 21.3 Intelligent I/O Group 2 Block Diagram
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 251 of 488
DIV4 to DIV0, BCK1 to BCK0 : Bits in the G2BCR0 register
BTS : Bit in the G2BCR1 register
BT2S : Bit in the BTSR register
OPOL, IPOL : Bits in the G2CR register
DF : Bit in the IECR register
MOD2 to MOD0 : Bits in the G2POCRj register (j = 0 to 7)
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O
Request from group2
Request from communication function
BT3S
BTS
Reset
BCK1 to BCK0
f1
11
Request by matching the base
timer with the G3PO0 register
Group3 base
timer reset
Divider fBT3
by 2(n+1)
Base timer
DIV4 to DIV0
Overflow of the bit 15
in the base timer
G3PO0 register
ISCLK3(1)
Base timer interrupt request (BT3R)(3)
Bit modulation
PWM
G3PO1 register
Bit modulation
PWM
G3PO2 register
Bit modulation
PWM
Real time port
output value
000 to 010, 100
PWM
output
control
MOD2 to MOD0
OUTC30/ISTxD3
111
MOD2 to MOD0
OUTC31/ISCLK3(1)
000 to 010,
100
111
ISRxD3
G3PO3 register
Bit modulation
PWM
G3PO4 register
Bit modulation
PWM
G3MK4 register
G3PO5 register
OUTC32
PWM
output
control
OUTC33
OUTC34
PWM
output
control
Bit modulation
PWM
OUTC35
(Note 1)
G3MK5 register
G3PO6 register
Bit modulation
PWM
G3MK6 register
G3PO7 register
OUTC36
PWM
output
control
Bit modulation
PWM
OUTC37
Waveform generation
interrupt request
(PO3jR)(3)
G3MK7 register
Transmission
Clock
selector
OPOL
Transmit Shift
register
G3TB register
Polarity
inverse
Transmit interrupt
request
(SIO3TR)(3)
Shift counter
Transmit operation clock
Mode controller
Reception
Mode controller
Receive operation clock
Receive interrupt
request
(SIO3RR)(3)
Shift counter
IPOL
Polarity
inverse
Receive shift
register
NOTES:
1. In the 100-pin package, these pins are not connected to external pins.
2. Each register enters a reset state after the G3BCR0 register supplies the
clock.
Figure 21.4 Intelligent I/O Group 3 Block Diagram
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 252 of 488
G3RB register
DIV4 to DIV0, BCK1 to BCK0 : Bits in the G3BCR0 register
BTS : Bit in the G3BCR1 register
BT3S : Bit in the BTSR register
MOD2 to MOD0 : Bits in the G3POCRj register (j = 0 to 7)
OPOL, IPOL : Bits in the G3CR register
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O
Figures 21.5 to 21.15 show registers associated with the intelligent I/O base timer, the time measurement
function and waveform generation function. (For registers associated with the communication function, see
Figures 21.32 to 21.38, Figures 21.42 to 21.45, Figures 21.47 to 21.49.)
Group i Base Timer Register (i=0 to 3)(2)
b15
b8 b7
b0
Symbol
G0BT,G1BT
G2BT,G3BT
Address
00E116 - 00E016, 012116 - 012016
016116 - 016016, 01A116 - 01A016
After Reset
Indeterminate
Indeterminate
Setting Range
Function
When the base timer is counting:
When read, the value of the counter can be read.
When write, the counter starts counting from the
value written. When the base timer is reset, the
GiBT register is set to "000016"(1).
When the base timer is reset:
The GiBT register is set to "000016" but the
value is indeterminate. No value is written(1).
000016 to FFFF16
RW
RW
NOTES:
1. Each base timer stops only when the BCK1 to BCK0 bits in the GiBCR0 register are set to "002" (clock
stopped). The base timer counts when the BCK1 to BCK0 bits are set to a value other than "002".
When the BTiS bit in the BTSR register and the BTS bit in the GiBCR1 register are set to "0", the base
timer is reset continually, remaining set to "000016". This, in effect, places the base timer in a "no
counting" state. When either BTiS bit or BTS bit is set to "1", this state is cleared and counting starts.
2. The GiBT register reflects the value of the base timer with a delay of one half fBTi cycle.
Group i Base Timer Control Register 0 (i=0 to 3)(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
G0BCR0 to G3BCR0
Bit
Symbol
Address
00E216, 012216, 016216, 01A216
Bit Name
After Reset
0016
Function
RW
b1 b0
BCK0
Count Source
Select Bit
BCK1
0
0
1
1
RW
0 : Clock stops
1 : Do not set to this value
0 : Two-phase pulse signal is applied(2)
RW
1 : f1
If setting value is n (n = 0 to 31),
count source is divided by 2(n + 1).
No division if n=31.
DIV0
DIV1
RW
RW
b6 b5 b4 b3 b2
DIV2
Count Source
Divide Ratio
Select Bit
DIV3
(n=0) 0 0 0 0 0 : Divide-by-2
(n=1) 0 0 0 0 1 : Divide-by-4
(n=2) 0 0 0 1 0 : Divide-by-6
:
(n=30) 1 1 1 1 0 : Divide-by-62
(n=31) 1 1 1 1 1 : No division
DIV4
IT
RW
RW
RW
Base Timer
Interrupt Select Bit
0 : Bit 15 overflows
1 : Bit 14 overflows
RW
NOTES:
1. When the CAS bit in the GiBCR1 register is set to "1" (32-bit time measurement, waveform generation function), set the G0BCR0 register and G1BCR0 register to the same value.
2. This setting can be used only when the UD1 to UD0 bits in the GjBCR1 register (j=0, 1) of group 0
or 1 are set to "102" (two-phase signal processing mode). Do not set the BCK1 to BCK0 bits to
"102" in other modes or in group 2 or 3.
Figure 21.5 G0BT to G3BT Register and G0BCR0 to G3BCR0 Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 253 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O
Group i Base Timer Control Register 1 (i=0,1)
b7
b6
b5
b4
b3
0
b2
b1
b0
Symbol
G0BCR1, G1BCR1
Bit
Symbol
Address
00E316, 012316
Bit Name
After Reset
0016
Function
RW
RST0
Base Timer Reset
Cause Select Bit 0
0: The base timer is not reset by
synchronizing with the base timer reset
RW
1: The base timer is reset by synchronizing
with the base timer reset(1)
RST1
Base Timer Reset
Cause Select Bit 1
0: The base timer is not reset by
matching with the GiPO0 register
1: The base timer is reset by matching
with the GiPO0 register(2)
RW
RST2
Base Timer Reset
Cause Select Bit 2
0: The base timer is not reset by
applying "L" to the INTi pin
1: The base timer is reset by applying
"L" to the INTi pin(3)
RW
Reserved Bit
Set to "0"
RW
Base Timer
Start Bit(5, 6)
0: Base timer is reset
1: Base timer starts counting
RW
(b3)
BTS
b6 b5
UD0
UD1
CAS
RW
0 0 : Counter increment mode
0 1 : Counter increment/decrement mode
Counter Increment/
: Two-phase pulse signal processing
Decrement Control Bit 1 0
mode(7)
RW
:
Do
not set to this value
11
0: 16-bit time measurement or
Groups 0 and 1
waveform generation function
Cascaded Connection
1: 32-bit time measurement or
Function Select Bit
waveform generation function(4)
RW
NOTES:
1. In group 0, the base timer is reset by synchronizing with the group 1 base timer reset. In group 1,
the base timer is reset by synchronizing with the group 0 base timer reset.
2. The base timer is reset two fBTi clock cycles after the base timer matches the value set in the GiPO0
register. (See Figure 21.13 for details on the GiPO0 register.) When the RST1 bit is set to "1", the
value of the GiPOj register (j=1 to7) for the waveform generation function and communication
function must be set to a smaller value than that of the GiPO0 register.
3. In group 0, the base timer is reset when "L" is applied to the INT0 pin. In group 1, the base timer is
reset when "L" is applied to the INT1 pin.
4. When the CAS bit is set to "1" (32-bit time measurement, waveform generation function), set the
G0BCR1 register to "8116" and the G1BCR1 register to "1000 0XX02".
5. When starting the group 0 or 1 base timer separately, set the BTS bit to "1" after the BTkS bit (k=0 to
1) in the BTSR register is set to "0".
6. When starting the base timers in multiple groups simultaneously, use the BTSR register. Set the
BTS bit to "0".
7. In two-phase pulse signal processing mode, the base timer is not reset, even when the RST1 bit is
set to "1", if the counter is decremented two clock cycles after the base timer matches the value set
in the GiPO0 register
Figure 21.6 G0BCR1 and G1BCR1 Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 254 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O
Group 2 Base Timer Control Register 1
b7
b6
b5
b4
0 0
b3
b2
b1
b0
Symbol
G2BCR1
0
Bit
Symbol
Address
016316
Bit Name
After Reset
0016
Function
RW
RST0
Base Timer
Reset Cause
Select Bit 0
0 : The base timer is not reset by synchronizing
with the group 1 base timer reset
RW
1 : The base timer is reset by synchronizing
with the group 1 base timer reset
RST1
Base Timer
Reset Cause
Select Bit 1
0 : The base timer is not reset by matching
with the G2PO0 register
1 : The base timer is reset by matching with
the G2PO0 register(1)
RW
RST2
Base Timer
Reset Cause
Select Bit 2
0 : The base timer is not reset by a reset
request from the communication function
1 : The base timer is reset by a reset request
from the communication function
RW
Reserved Bit
Set to "0"
RW
Base Timer
Start Bit(3, 4)
0 : Base timer is reset
1 : Base timer starts counting
RW
Reserved Bit
Set to "0"
RW
(b3)
BTS
(b6 - b5)
PRP
Parallel Real-Time
0 : RTP output mode
Port Function
1 : Parallel RTP output mode
(2)
Select Bit
RW
NOTES:
1. The base timer is reset two fBT2 clock cycles after the base timer matches the value set in the G2PO0
register. (See Figure 21.13 for details on the G2PO0 register.) When the RST1 bit is set to "1", the
value of the G2POi register (i=1 to7), for the waveform generation function and communication
function, must be set to a smaller value than that of the G2PO0 register.
2. The PRP bit is valid when the RTP bit in the G2POCRi register is set to "1" (not used)
3. When starting the group 2 base timer, set the BTS bit to "1" after the BT2S bit in the BTSR register is
set to "0".
4. When starting the base timers in multiple groups simultaneously, use the BTSR register. Set the
BTS bit to "0".
Figure 21.7 G2BCR1 Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 255 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O
Group 3 Base Timer Control Register 1
b7
b6
b5
0 0
b4
b3
b2
b1
b0
Symbol
Address
01A316
G3BCR1
0
Bit
Symbol
Bit Name
After Reset
0016
Function
RW
RST0
Base Timer
Reset Cause
Select Bit 0
0 : The base timer is not reset by synchronizing
with the group 2 base timer reset
RW
1 : The base timer is reset by synchronizing
with the group 2 base timer reset
RST1
Base Timer
Reset Cause
Select Bit 1
0 : The base timer is not reset by matching
with the G3PO0 register
1 : The base timer is reset by matching with
the G3PO0 register(1)
RW
RST2
Base Timer
Reset Cause
Select Bit 2
0 : The base timer is not reset by a reset
request from the communication function
1 : The base timer is reset by a reset request
from the communication function
RW
Reserved Bit
Set to "0"
RW
Base Timer
Start Bit(3, 4)
0 : Base timer is reset
1 : Base timer starts counting
RW
Reserved Bit
Set to "0"
RW
(b3)
BTS
(b6 - b5)
PRP
Parallel Real-Time
0 : RTP output mode
Port Function
1 : Parallel RTP output mode
(2)
Select Bit
RW
NOTES:
1. The base timer is reset after two fBT3 clock cycles after the base timer matches the value set in the
G3PO0 register. (See Figure 21.13 for details on the G3PO0 register.) When the RST1 bit is set to
"1", the value of the G3POi register (i=1 to7), for the waveform generation function and communication
function, must be set to a smaller value than that of the G2PO0 register.
2. The PRP bit is valid when the RTP bit in the G3POCRi register is set to "1" (not used)
3. When starting the group 3 base timer, set the BTS bit to "1" after the BT3S bit in the BTSR register is
set to "0".
4. When starting the base timers in multiple groups simultaneously, use the BTSR register. Set the BTS
bit to "0".
Figure 21.8 G3BCR1 Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 256 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O
Base Timer Start Register(1, 2)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
BTSR
Bit
Symbol
Address
016416
Bit Name
After Reset
XXXX 00002
Function
RW
BT0S
Group 0 Base Timer
Start Bit
0 : Base timer reset
1 : Base timer starts counting
RW
BT1S
Group 1 Base Timer
Start Bit
0 : Base timer reset
1 : Base timer starts counting
RW
BT2S
Group 2 Base Timer
Start Bit
0 : Base timer reset
1 : Base timer starts counting
RW
BT3S
Group 3 Base Timer
Start Bit
0 : Base timer reset
1 : Base timer starts counting
RW
(b7 - b4)
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
NOTES:
1. Set registers as follows before using the intelligent I/O:
(1) Set the G2BCR0 register to supply the clock to the group 2 base timer
(2) Set all BT0S to BT3S bits in the BTSR register to "0" (base timer reset)
(3) Set other registers associated with the intelligent I/O
The BTiS bit (i=0 to 3) allows the base timers in multiple groups to start counting simultaneously.
When starting the base timers separately, set the BTiS bit to "0" before setting the BTS bit in the
GiBCR1 register.
2. Use the following procedure to start base timers in multiple groups simultaneously (including groups
1 and 2 cascaded connections). This procedure is not required when starting the base timers
individually.
• Set the BCK1 to BCK0 bits and DIV4 to DIV0 bits in the GiBCR0 register (i=0 to 3) of the groups to
be started simultaneously, to the same value.
• After the BCK1 to BCK0 bits or DIV4 to DIV0 bits are changed, use the following procedure to
start the base timer twice.
(1) Set the BTiS bit in the BTSR register to "1" (base timer starts counting).
(2) Set the BTiS bit to "0" (base timer stops counting) after one fBTi clock cycle.
(3) After waiting at least one additional fBTi clock cycle, set the BTiS bit to "1" (base timer starts
counting).
Figure 21.9 BTSR Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 257 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O
Group i Time Measurement Control Register j (i=0,1; j=0 to 7)(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
G0TMCR0 to G0TMCR3
G0TMCR4 to G0TMCR7
G1TMCR0 to G1TMCR3
G1TMCR4 to G1TMCR7
Bit
Symbol
Address
00D816, 00D916, 00DA16, 00DB16
00DC16, 00DD16, 00DE16, 00DF16
011816, 011916, 011A16, 011B16
011C16, 011D16, 011E16, 011F16
Bit Name
After Reset
0016
0016
0016
0016
Function
RW
b1 b0
CTS0
0
0
1
1
Time Measurement
Trigger Select Bit
CTS1
0
1
0
1
: No time measurement
: Rising edge
: Falling edge
: Both edges
RW
: No digital filter
: Do not set to this value
: fBTi
: f1
RW
RW
b3 b2
DF0
Digital Filter Function
Select Bit
DF1
GT
0
0
1
1
0
1
0
1
0 : Gate function is not used
1 : Gate function is used
Gate Function
Select Bit(2, 4)
RW
RW
0 : Not cleared
1 : The gate is cleared when the base RW
timer matches the GiPOk register
GOC
Gate Function Clear
Select Bit(2, 3, 5)
GSC
Gate Function Clear
Bit(2, 3)
The gate is cleared by setting the
GSC bit to "1"
RW
Prescaler Function
Select Bit(2)
0 : Not used
1 : Used
RW
PR
NOTES:
1. If the CAS bit in the GiBCR1 register is set to "0" (16-bit time measurement function), the G1TMCR0
and G1TMCR3 to G1TMCR5 registers cannot be used. When write, set these registers to "0016".
If the CAS bit is set to "1" (32-bit time measurement function), set the same values in the G0TMCRj
and G1TMCRj registers.
2. These bits are in the GiTMCR6 and GiTMCR7 registers.
Set all bits 4 to 7 in the GiTMCR0 to GiTMCR5 registers to "0".
3. These bits are enabled only when the GT bit is set to "1"
4. If the CAS bit in the GiBCR1 register is set to "1" (32-bit time measurement function), set the GT bit
to "0". The gate function cannot be used.
5. The GOC bit is set to "0" after the gate function is cleared. See Figure 18.13 for details on the
GiPOk register (k=4 when j=6; k=5 when j=7).
Group i Time Measurement Prescale Register j (i=0,1; j=6,7)
b7
b0
Symbol
G0TPR6 to G0TPR7
G1TPR6 to G1TPR7
Address
00E416, 00E516
012416, 012516
After Reset
0016
0016
Function
Setting Range
RW
If the setting value is n, the value of the base timer
is stored into GiTMj register whenever a trigger
input is counted by n+1(1)
0016 to FF16
RW
NOTES:
1. The first prescaler, after the PR bit in the GiTMCRj register is changed from "0" (prescaler function
used) to "1" (prescaler function not used), may be divided by n rather than n+1. The subsequent
prescaler is divided by n+1.
Figure 21.10 G0TMCR0 to G0TMCR7, G1TMCR0 to G1TMCR7, G0TPR6, G0TPR7, G1TPR6, and
G1TPR7 Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 258 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O
Group i Time Measurement Register j (i=0,1; j=0 to 7)
b15
b8 b7
b0
Symbol
G0TM0 to G0TM2
G0TM3 to G0TM5
G0TM6 to G0TM7
G1TM0 to G1TM2
G1TM3 to G1TM5
G1TM6 to G1TM7
Address
00C116 - 00C016, 00C316 - 00C216, 00C516 - 00C416
00C716 - 00C616, 00C916 - 00C816, 00CB16 - 00CA16
00CD16 - 00CC16, 00CF16 - 00CE16
010116 - 010016, 010316 - 010216, 010516 - 010416
010716 - 010616, 010916 - 010816, 010B16 - 010A16
010D16 - 010C16, 010F16 - 010E16
Function
After Reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Setting Range
RW
The value of the base timer is stored every
trigger input. When the CAS bit in the GiBCR1
register is set to "1" (32-bit time measurement),
16 low-order bits are stored into the G0TMj
register and 16 high-order bits are into stored the
G1TMj register.
RO
Group i Waveform Generation Control Register j (i=0 to 1; j=0 to 7)(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
G0POCR0 to G0POCR3
G0POCR4 to G0POCR7
G1POCR0 to G1POCR3
Address
00D016, 00D116, 00D216, 00D316
00D416, 00D516, 00D616, 00D716
011016, 011116, 011216, 011316
0X00 X0002
0X00 X0002
0X00 X0002
G1POCR4 to G1POCR7
011416, 011516, 011616, 011716
0X00 X0002
Bit
Symbol
Bit Name
After reset
Function
RW
b2 b1b0
MOD0
MOD1
Operation Mode
Select Bit
MOD2
(b3)
0 0 0 : Single waveform output mode
0 0 1 : SR waveform output mode(2)
0 1 0 : Phase-delayed waveform
output mode
0 1 1 : Do not set to this value
1 0 0 : Do not set to this value
1 0 1 : Do not set to this value
1 1 0 : Do not set to this value(3)
1 1 1 : Use a communication function
output(4)
Output Initial Value
Select Bit
RLD
0: Reloads the GiPOj register when
GiPOj Register Value
value is written
Reload Timing Select Bit 1: Reloads the GiPOj register when
the base timer is reset
INV
RW
RW
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
IVL
(b6)
RW
0: Outputs "L" as default value
1: Outputs "H" as default value
RW
RW
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Inverse Output Function 0: Output is not inversed
Select Bit(5)
1: Output is inversed
RW
NOTES:
1. Groups 0 and 1 have 16-bit and 32-bit waveform generation functions.
If the CAS bit in the GiBCR1 register is set to "0" (16-bit waveform generation function), the
G0POCR2 to G0POCR3 and G0POCR 6 to G0POCR7 registers cannot be used. When write, set
these registers to "0016".
If the CAS bit is set to "1" (32-bit waveform generation function), set the same values in the G0POCRj
and G1POCRj registers.
2. This setting is valid only for even channels. In SR waveform output mode, values written to the
corresponding odd channel (next channel after an even channel) are ignored. Even channels output
waveforms. Odd channels output no waveform.
3. To receive data in UART mode of group 0 and 1, set the GiPOCR2 register to "0000 01102".
4. This setting is valid only for channels 0 and 1. To use ISTxDi, set the MOD2 to MOD0 bits in the
GiPOCR0 register to "1112". To use ISCLKi for an output, set the MOD2 to MOD0 bits in the
GiPOCR1 register to"1112". Do not set the MOD2 to MOD0 bits to "1112" except in the channels 0
and 1 and for the communication function.
5. The inverse output function is the final step in the waveform generation process. If the INV bit is set to
"1", the output signal is "H" when the IVL bit is set to "0" and "L" when the IVL bit is set to "1".
Figure 21.11 G0TM0 to G0TM7, G1TM0 to G1TM7, Registers and G0POCR0 to G0POCR7, G1POCR0
to G1POCR7 Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 259 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O
Group i Waveform Generation Control Register j (i=2 to 3; j=0 to 7)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
G2POCR0 to G2POCR3
Address
015016, 015116, 015216, 015316
After Reset
0016
G2POCR4 to G2POCR7
G3POCR0 to G3POCR3
G3POCR4 to G2POCR7
015416, 015516, 015616, 015716
019016, 019116, 019216, 019316
019416, 019516, 019616, 019716
0016
0016
0016
Bit
Symbol
Bit Name
Function
RW
b2 b1b0
Operation Mode
Select Bit(5)
0 0 0 : Single waveform output mode RW
0 0 1 : SR waveform output mode(1)
0 1 0 : Inverse waveform output mode
0 1 1 : Do not set to this value
RW
1 0 0 : Bit-modulation PWM mode
1 0 1 : Do not set to this value
1 1 0 : Do not set to this value
1 1 1 : Use a communication function RW
output(2)
PRT
Parallel Real-time Port
Output Trigger
Select Bit(4)
0: Not triggered by matching the base
timer with the GiPO0 to GiPO7 registers
1: Triggered by matching the base timer RW
with the GiPO0 to GiPO7 registers
IVL
Output Initial Value
Select Bit
RLD
GiPOj Register Value
Reload Timing
Select Bit
0: Outputs "L" as default value
1: Outputs "H" as default value
0: Reloads the GiPOj register when
counter is written to
1: Reloads the GiPOj register when
the base timer is reset
RTP
Real-time Port Function
Select Bit
0: Not used
1: Used (RTP output mode or parallel RW
RTP output mode)
INV
Inverse Output Function 0: Output is not inversed
Select Bit(3)
1: Output is inversed
MOD0
MOD1
MOD2
RW
RW
RW
NOTES:
1. This setting is valid only for even channels. In SR waveform output mode, values written to the
corresponding odd channel (next channel after an even channel) are ignored. Even channels output
waveforms. Odd channels output no waveforms.
2. This setting is valid only for channels 0 and 1 in the groups 2 and 3. To use ISTxD2 or IEOUT, set the
MOD2 to MOD0 bits in the G2POCR0 register to "1112". To use ISCLK2 for an output, set the MOD2
to MOD0 bits in the G2POCR1 register to "1112". Do not set the MOD2 to MOD0 bits to "1112" except
in the channels 0 and 1.
To use ISTxD3, set the MOD2 to MOD0 bits in the G3POCR0 register to "1112". To use ISCLK3 for an
output, set the MOD2 to MOD0 bits in the G3POCR1 register to"1112". Do not set the MOD2 to
MOD0 bits to "1112" except in the channels 0 and 1.
3. The inverse output function is the final step in the waveform generation process. If the INV bit is set to
"1" (output inversed), the output signal is "H" when the IVL bit is set to "0" (outputs "L" as an initial
value) and "L" when the IVL bit is set to "1" (outputs "H" as an initial value).
4. The PRT bit is valid when the RTP bit is set to "1" (real-time port function used) and the PRP bit in the
GiBCR1 register is set to "1" (parallel RTP output mode).
5. When the RTP bit is set to "1", the value written to the MOD2 to MOD0 bits is ignored.
Figure 21.12 G2POCR0 to G2POCR7 and G3POCR0 to G3POCR7 Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 260 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O
Group i Waveform Generation Register j (i=0 to 3; j=0 to 7)
b15
b8 b7
Symbol
G0PO0 to G0PO2
G0PO3 to G0PO5
G0PO6 to G0PO7
G1PO0 to G1PO2
G1PO3 to G1PO5
G1PO6 to G1PO7
G2PO0 to G2PO2
G2PO3 to G2PO5
G2PO6 to G2PO7
G3PO0 to G3PO2
G3PO3 to G3PO5
G3PO6 to G3PO7
b0
Address
00C116-00C016, 00C316-00C216, 00C516-00C416
00C716-00C616, 00C916-00C816, 00CB16-00CA16
00CD16-00CC16, 00CF16-00CE16
010116-010016, 010316-010216, 010516-010416
010716-010616, 010916-010816, 010B16-010A16
010D16-010C16, 010F16-010E16
014116-014016, 014316-014216, 014516-014416
014716-014616, 014916-014816, 014B16-014A16
014D16-014C16, 014F16-014E16
018116-018016, 018316-018216, 018516-018416
018716-018616, 018916-018816, 018B16-018A16
018D16-018C16, 018F16-018E16
Function
• When the RLD bit in the GiPOCRj register is set
to "0",
value written is immediately reloaded into the
GiPOj register to output, for example, a waveform
reflecting the value
• When the RLD bit is set to "1",
the value is reloaded when the base timer is
reset. The value written can be read until reload.
After Reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Setting Range
RW
000016 to FFFF16
RW
Group 3 Waveform Generation Mask Register j (j=4 to 7)
b15
b8 b7
b0
Symbol
Address
G3MK4, G3MK5 019916-019816, 019B16-019A16
G3MK6, G3MK7 019D16-019C16, 019F16-019E16
Function
When one or more bit k (k=0 to 15) in this
register is set to "1", the bit k in the group 3 base
timer is masked. The masked value is compared
to the G3POj register(1).
After Reset
Indeterminate
Indeterminate
Setting Range
RW
000016 to FFFF16
RW
NOTES:
1. This function is enabled in single-phase waveform output mode or phase-delayed waveform output
mode. Set the G3MKi register to "000016" in other modes.
Figure 21.13 G0PO0 to G0PO7, G1PO0 to G1PO7, G2PO0 to G2PO7, G3PO0 to G3PO7 Registers
and G3MK4 to G3MK7 Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 261 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O
Group i Function Select Register (i=0, 1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
After Reset
G0FS, G1FS
00E716, 012716
0016
Bit
Symbol
FSC0
FSC1
Bit Name
Function
RW
Channel 0 Time Measurement/ 0 : Selects the waveform generation
Waveform Generation
RW
function
Function Select Bit
1 : Selects the time measurement
function
Channel 1 Time Measurement/
Waveform Generation
RW
Function Select Bit
FSC2
Channel 2 Time Measurement/
Waveform Generation
Function Select Bit
RW
FSC3
Channel 3 Time Measurement/
Waveform Generation
Function Select Bit
RW
FSC4
FSC5
Channel 4 Time Measurement/
Waveform Generation
Function Select Bit
Channel 5 Time Measurement/
Waveform Generation
Function Select Bit
RW
RW
FSC6
Channel 6 Time Measurement/
Waveform Generation
Function Select Bit
RW
FSC7
Channel 7 Time Measurement/
Waveform Generation
Function Select Bit
RW
NOTES:
1. No 16-bit waveform generation function is provided for channels 2, 3, 6 and 7 of the group 0.
No 16-bit time measurement function is provided for channels 0, 3, 4 and 5 of the group 1.
When the CAS bit in the GiBCR1 register is set to "1" (32-bit time measurement or waveform
generation function), set the same values in the G0FS and G1FS registers.
Group i Function Enable Register (i=0 to 3)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
After Reset
G0FE to G3FE
00E616, 012616, 016616, 01A616
0016
Bit
Symbol
Bit Name
Function
IFE0
Channel 0 Function
Enable Bit
IFE1
Channel 1 Function
Enable Bit
0 : Disables functions for channel j RW
1 : Enables functions for channel j
(j=0 to 7)
RW
IFE2
Channel 2 Function
Enable Bit
RW
IFE3
Channel 3 Function
Enable Bit
RW
IFE4
Channel 4 Function
Enable Bit
RW
IFE5
Channel 5 Function
Enable Bit
RW
IFE6
Channel 6 Function
Enable Bit
RW
IFE7
Channel 7 Function
Enable Bit
RW
Figure 21.14 G0FS and G1FS Registers and G0FE to G3FE Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
RW
Page 262 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Base Timer)
Group i RTP Output Buffer Register (i=2, 3)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
G2RTP, G3RTP 016716, 01A716
Bit
Symbol
Bit Name
Function
RW
Channel 0 RTP Output Buffer 0 : Outputs "L"
Channel 1 RTP Output Buffer 1 : Outputs "H"
RW
RTP1
RTP0
RW
RTP2
Channel 2 RTP Output Buffer
RW
RTP3
Channel 3 RTP Output Buffer
RW
RTP4
Channel 4 RTP Output Buffer
RW
RTP5
Channel 5 RTP Output Buffer
RW
RTP6
Channel 6 RTP Output Buffer
RW
RTP7
Channel 7 RTP Output Buffer
RW
Figure 21.15 G2RTP AND G3RTP Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
After Reset
0016
Page 263 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Base Timer)
21.1 Base Timer
The base timer is a free-running counter that counts an internally generated count source.
Table 21.2 lists specifications of the base timer. Figures 21.5 to 21.9 show registers associated with the
base timer. Figure 21.16 shows a block diagram of the base timer. Figure 21.17 shows an example of a
cascaded connection. Figure 21.18 shows an example of the base timer in counter increment mode. Figure
21.19 shows an example of the base timer in counter increment/decrement mode. Figure 21.20 shows an
example of two-phase pulse signal processing mode.
Table 21.2 Base Timer Specifications
Item
Count Source (fBTi) (i=0 to 3)
Counting Operation
Counter Start Condition
Specification
f1 divided by 2(n+1) (Group 0 to 3),
two-phase pulse input divided by 2(n+1) (Group 0 and 1)
n: determined by the DIV4 to DIV0 bits in the GiBCR0 register
n=0 to 31; however no division when n=31
The base timer increments the counter
The base timer increments/decrements the counter
Two-phase pulse signal processing
• When starting the base timer of each group separately, set the BTS bit in
the GiBCR1 register to "1" (base timer starts counting)
• When starting the base timer of multiple groups simultaneously, set the
BTiS bit in the BTSR register to "1" (base timer starts counting)
Counter Stop Condition
Set the BTiS bit in the BTSR register to "0" (base timer reset) and the BTS
bit in the GiBCR1 register to "0" (base timer reset)
Base Timer Reset Condition
• Synchronized with the base timer reset in different groups:
Group0 : synchronized with group 1 base timer reset
Group1 : synchronized with group 0 base timer reset
Group2 : synchronized with group 1 base timer reset
Group3 : synchronized with group 2 base timer reset
• Matching values in the base timer and GiPO0 register
• "L" signal applied
to the external interrupt pin
________
Group 0 : ________
INT0 pin
Group 1 : INT1 pin
• Reset request from communication function (Group 2 and 3)
Value when the Base Timer is Reset
"000016"
Interrupt Request
The BTiR bit in the interrupt request register is set to "1" (interrupt requested)
when bit 14 or bit 15 in the base timer overflows (See Figure 10.14.)
Read from Base Timer
• The GiBT register indicates counter value while the base timer is running
• The GiBT register is indeterminate when the base timer is reset
Write to Base Timer
When a value is written while the base timer is running, the counter
immediately starts counting from this value. No value can be written while
the base timer is reset.
Selectable Function
• Cascaded connection (Group 0 and 1)
Group 1 base timer is incremented every time bit 15 in the group 0 base
timer overflows (See Figure 21.17)
• Counter increment/decrement mode (Group 0 and 1)
The base timer starts when the BTS bit or the BTiS bit is set to "1". After
incrementing to "FFFF 16", the counter is then decremented back to
"000016". If the RST1 bit in the GiBCR1 register is set to "1" (the base timer
is reset by matching with the GiPO0 register), the counter decrements after
the base timer matches the GiPO0 register. The base timer increments the
counter again when the counter becomes "0000 16." (See Figure 21.19.)
Rev. 1.31 Jan.31, 2006 Page 264 of 488
REJ09B0034-0131
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Base Timer)
Table 21.2 Base Timer Specifications (Continued)
Item
Specification
Selectable Function
• Two-phase pulse processing mode (Group 0 and 1)
Two-phase pulse signals from P76 and P77 pins in group 0, and P80
and P81 pins in group 1 are counted (See Figure 21.20)
P76, P80
P77, P81
The timer increments
counter on all edge
The timer decrements
counter on all deges
fBTi
BCK1 to BCK0
Base timer
11
f1
Apply two-phase
pulse signal (
Group0,1)
Divider (1)
by 2(n+1)
10
b0 to b13
b14 b15
Overflow signal
0
BTiS bit in BTSR register
BTS bit in GiBCR1 register
1
RST0
IT
Base timer
interrupt request
(See the BTiR bit in Figure 10.14)
Other base timer reset
RST1
Base timer reset
Matching with the GiPO0 register
RST2
Apply "L" to the INTi pin (Group0,1)
Request from communication
function (Group2,3)
NOTES:
1. Divider is reset when both BTiS bit and BTS bit are set to "0".
i = 0 to 3
BCK1 to BCK0, IT : Bits in the GiBCR0 register
RST2 to RST0 : Bits in the GiBCR1 register
Figure 21.16 Base Timer Block Diagram
Table 21.3 Base Timer Associated Register Settings
(for Time Measurement Function, Waveform Generation Function, and Communication Function)
Register
Bit
Function
G2BCR0
Supplies operation clock to the BTSR register. Set to "0111 11112".
BTSR
Set to "0000 00002"
GiBCR0
BCK1 to BCK0
Select count source
DIV4 to DIV0
Select divide ratio of count source
IT
Selects the base timer interrupt
GiBCR1
RST2 to RST1
Select factors for a base timer reset
BTS
Used to start the base timer independently
UD1 to UD0
Select how to count (Group 0 and 1)
CAS
Selects cascaded connection (Group 0 and 1)
GiBT
Read or write base timer value
Set the following registers to set the RST1 bit to "1" (base timer reset by matching the base timer with the G1PO0 register).
GiPOCR0
MOD2 to MOD0
Set to "0002" (single-phase waveform output mode)
GiPO0
Set reset cycle
GiFS
FSC0
Set to "0" (waveform generation function)
GiFE
IFE0
Set to "1" (channel operation start)
i : Bit configurations and functions vary with each group
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 265 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Base Timer)
Request from group0
Request by matching the base timer
with the G1PO0 register
Request from group1
Request by matching the base timer
with the G0PO0 register
Request from the INT pin
Request from the INT pin
BT1S
BTS
BT0S
BTS
f1
Two-phase pulse
signal is applied
fBT1
11
Group0
base timer
Divider
by 2(n+1)
10
BCK1 to BCK0
0
Group1
base timer
1
Bit 15 overflow in
CAS
the group0 base timer
0
INPC1k triggered by
the time measurement
1
G1TMj register
CAS
INPC0j triggered by
the time measurement
G0TMj register
G1POj register
G0POj register
0
Waveform generation
match signal
1
CAS
j=0 to 7, k=1,2,6,7
BT0S, BT1S : Bits in the BTSR register
BTS, CAS : Bits in the GiBCR1 register (i=0,1)
BCK1 to BCK0 : Bits in the GiBCR0 register (i = 0,1)
Figure 21.17 Cascaded Connection
(1) The IT in the GiBCR0 register (i=0,1) is set to "0" (bit 15 in the base timer overflows)
FFFF16
Base Timer i
800016
000016
b15 overflow signal
"1"
"0"
BTkR bit in IIOjIR register "1"
Write "0" by program
if setting to "0"
"0"
j=4,7,8,11 k=0 to 3
The above applies under the following conditions:
• The RST1 bit in the GiBCR1 register is set to "0" (the base timer is not reset by matching the base
timer with the GiPO0 register)
• The UD1 to UD0 bits in the GiBCR1 register are set to "002" (counter increment mode)
(2) The IT in the GiBCR0 register (i=0,1) is set to "1" (bit 14 in the base timer overflows)
FFFF16
C00016
Base Timer i
800016
400016
000016
b14 overflow signal
BTkR bit in IIOjIR register
"1"
"0"
"1"
"0"
Write "0" by program
if setting to "0"
j=4,7,8,11 k=0 to 3
The above applies under the following conditions:
• The RST1 bit in the GiBCR1 register is set to "0" (the base timer is not reset by matching the base
timer with the GiPO0 register)
• The UD1 to UD0 bits in the GiBCR1 register are set to "002" (counter increment mode)
Figure 21.18 Counter Increment Mode (Group 0 and 1)
Rev. 1.31 Jan.31, 2006 Page 266 of 488
REJ09B0034-0131
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Base Timer)
(1) When the IT bit in the GiBCR0 register (i= 0 to 1) is set to "0" (bit 15 in the base timer overflows)
FFFF16
Base Timer i
800016
"1"
b15 overflow signal
"0"
"1"
BTkR bit in IIOjIR register
"0"
Write "0" by program
if setting to "0"
j=4, 7, 8, 11; k=0 to 3
The above applies under the following conditions:
• The RST1 in the GiBCR1 register is set to "0" (the base timer is not reset by matching the GiPO0 register).
• The UD1 to UD0 bits in the GiBCR1 register are set to "012" (counter increment/decrement mode).
(2) When the IT bit in the GiBCR0 register (i= 0 to 1) is set to "1" (bit 14 in the base timer overflows)
FFFF16
C00016
Base Timer i
800016
400016
000016
b14 overflow signal
BTkR bit in IIOjIR register
"1"
"0"
"1"
"0"
Write "0" by program
if setting to "0"
j=4, 7, 8, 11; k=0 to 3
The above applies under the following conditions:
• The RST1 in the GiBCR1 register is set to "0" (the base timer is not reset by matching the GiPO0 register).
• The UD1 to UD0 bits in the GiBCR1 register are set to "012" (counter increment/decrement mode).
(3) When the RST1 bit in the GiBCR1 register (i= 0 to 1) is set to "1" (the base timer is reset by matching with the GiPO0 register)
800216
800016
Base Timer i
000016
j=4, 7, 8, 11; k=0 to 3
The above applies under the following conditions:
• Value of GiPO0 register: "800016"
• The UD1 to UD0 bits in the GiBCR1 register are set to "012" (counter increment/decrement mode).
Figure 21.19 Counter Increment/ Decrement Mode (Group 0 and 1)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 267 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Base Timer)
(1) When the base timer is reset while the base timer increments the counter
Group0 : P76
Group1 : P80
(A-phase)
"H"
"L"
Input waveform
(
Group0 : P77
Group1 : P81
(B-phase)
"H"
fBTi
"H"
When selects no division
with the divider by 2(n+1)
)
Group0 : INT0
Group1 : INT1
(Z-phase)
min 1 µs
min 1 µs
"L"
"L"
"H"
(Note 1)
"L"
The base timer starts counting
Base Timer i
m
m+1
0
Set to "0" in this timing
1
2
Set to "1" in this timing
(2) When the base timer is reset while the base timer decrements the counter
Group0 : P76
Group1 : P80
(A-phase)
"H"
"L"
Input waveform
Group0 : P77
Group1 : P81
(B-phase)
(
min 1 µs
"L"
"H"
fBTi
When selects no division
with the divider by 2(n+1)
min 1 µs
"H"
)
Group0 : INT0
Group1 : INT1
(Z-phase)
"L"
(Note 1)
"H"
"L"
The base timer starts counting
Base Timer i
m
m-1
Set to "0" in this timing
0
FFFF16
FFFE16
Set to "FFFF16" in this timing
i=0, 1
NOTES:
1. 1.5 fBTi clock cycles or more are required.
Figure 21.20 Base Timer Operation in Two-phase Pulse Signal Proccessing Mode (Group 0 and 1)
Rev. 1.31 Jan.31, 2006 Page 268 of 488
REJ09B0034-0131
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Time Measurement Function)
21.2 Time Measurement Function (Group 0 and 1)
When external trigger is applied, the value of the base timer is stored into the GiTMj register (i=0 to 1; j=0 to
7). Table 21.4 shows specifications of the time measurement function. Table 21.5 lists pin settings of the
time measurement function. Table 21.6 lists settings of time measurement function associated registers.
Figures 21.21 and 21.22 show operating examples of the time measurement function. Figure 21.23 shows
an operating example of the prescaler function and gate function.
Table 21.4 Time Measurement Function Specifications
Item
Measurement Channel
Specification
Group 0: Channels 0 to 7
Group 1: Channels 1, 2, 6, 7
Trigger Input Polarity
Rising edge, falling edge or both edges of the INPCij pin(1)
Measurement Start Condition
The IFEj bit in the GiFE register is set to "1" (channel j function enabled)
when the FSCj bit (i=0 to1; j=0 to 7) in the GiFS register is set to "1" (time
measurement function selected)
Measurement Stop Condition
The IFEj bit is set to "0" (channel j function disabled)
Time Measurement Timing
• No prescaler : every time a trigger signal is applied
• Prescaler (for channel 6 and channel 7):
every GiTPRk register (k=6, 7) +1 times a trigger signal is applied
Interrupt Request Generation Timing
The TMijR bit in the interrupt request register (See Figure 10.14) is set to "1"
(interrupt requested) at time measurement timing
INPCij Pin
Function(1)
Selectable Function
Trigger input pin
• Digital filter function
The digital filter samples a trigger input signal level every f1 or fBTi cycles
and passes pulse signals, matching trigger input signal level, three times
• Cascaded connection function
Group 0 and group 1 are connected to operate as a 32-bit base timer
• Prescaler function (for channel 6 and channel 7)
Time measurement is executed every GiTPRk register value +1 times a
trigger signal is applied
• Gate function (for channel 6 and channel 7)
After time measurement by the first trigger input, trigger input cannot be
received. However, trigger input can be received again by matching the
base timer with the GiPOp register, or by setting the GSC bit in the
GiTMCRK register to "1", when the GOC bit in the GiTMCRk register is set
to "1" (gate cleared by matching the base timer with the GiPOp register
(p=4 when k=6, p=5 when k=7))
NOTES:
1. INPC00 to INPC07, INPC11 to INPC12, INPC16 to INPC17 pins (INPC00 to INPC07 pins during cascaded connection)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 269 of 488
21. Intelligent I/O (Time Measurement Function)
M32C/83 Group (M32C/83, M32C/83T)
Table 21.5 Pin Settings for Time Measurement Function
Pin(2)
Bit and Setting
PS1, PS2, PS5, PS8, PS9
PD7, PD8, PD11, PD14, PD15
Registers
Registers
P74/INPC11
PS1_4 = 0
PD7_4 = 0
P75/INPC12
PS1_5 = 0
PD7_5 = 0
P76/INPC00
PS1_6 = 0
PD7_6 = 0
P77/INPC01
PS1_7 = 0
PD7_7 = 0
P80/INPC02
PS2_0 = 0
PD8_0 = 0
P111/INPC11(1)
PS5_1 = 0
PD11_1 = 0
P112/INPC12(1)
PS5_2 = 0
PD11_2 = 0
P142/INPC16(1)
PS8_2 = 0
PD14_2 = 0
P143/INPC17(1)
PS8_3 = 0
PD14_3 = 0
P150/INPC00(1)
PS9_0 = 0
PD15_0 = 0
P151/INPC01(1)
PS9_1 = 0
PD15_1 = 0
P152/INPC02(1)
PD15_2 = 0
P153/INPC03(1)
PD15_3 = 0
P154/INPC04(1)
PS9_4 = 0
PD15_4 = 0
P155/INPC05(1)
PS9_5 = 0
PD15_5 = 0
P156/INPC06(1)
PD15_6 = 0
P157/INPC07(1)
PD15_7 = 0
IPS Register
IPS1 = 0
IPS0 = 0
IPS1 =1
IPS0 = 1, IPS2 = 0
IPS2 = 0
NOTES:
1. This port is provided in the 144-pin package only.
2. Apply trigger to INPC0j pin (j=0 to 7) when the CAS bit in the GiBCR register is set to "1" (32-bit time measurement
function). Trigger input to INPC1k pin (k=1, 2, 6, 7) is invalid.
Table 21.6 Time Measurement Function Associated Register Settings
Register
GiTMCRj
Bit
Function
CTS1 to CTS0
Select a time measurement trigger
DF1 to DF0
Select the digital filter function
GT, GOC, GSC
Select the gate function
PR
Select the prescaler function
GiTPRk
-
Setting value of the prescaler
GiFS
FSCj
Set to "1" (time measurement function)
GiFE
IFEj
Set to "1" (channel j function enabled)
i = 0 to 1;
j = 0 to 7;
k = 6, 7
Bit configurations and functions vary with channels and groups used.
Registers associated with the time measurement function must be set after setting registers associated with the base timer.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 270 of 488
M32C/83 Group (M32C/83, M32C/83T)
Input
to the INPCij pin
21. Intelligent I/O (Time Measurement Function)
"H"
"L"
FFFF16
n
Base timer i
p
m
000016
GiTMj register
m
n
p
Write "0" by program if setting to "0"
TMijR bit
"1"
"0"
i=0,1 j=0 to 7 (except j=1, 2, 6, 7 when i=1)
TMijR bit : Bits in the IIO0IIR to IIO8IR and IIO10IR to IIO11IR registers
The above applies under the following conditions:
The CTS1 to CTS0 bits in the GiTMCRj register are set to "012" (rising edge). The PR
bit is set to "0" (no prescaler used) and the GT bit is set to"0" (no gate function used).
The RTS2 to RTS0 bits in the GiBCR1 register are set to "0002" (no base timer reset).
The UD1 to UD0 bits are set to "002" (counter increment mode) and the CAS bit is set
to "0" (16-bit time measurement or waveform generation function).
To set the base timer to "000016" (setting the RST1 bit to "1" and the RST0 and RST2 bits
to "0") when the base timer matches the GiPO0 register, the base timer is set to "000016"
after it reaches the value set in the GiPO0 register + 2.
Figure 21.21 Time Measurement Function (1)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 271 of 488
21. Intelligent I/O (Time Measurement Function)
M32C/83 Group (M32C/83, M32C/83T)
(1) When selecting the rising edge as a time measurement trigger
(The CTS1 to CTS0 bits in the GiTMCR register (i=0,1, j=0 to 7)=012)
fBTi(1)
Base timer i
n-2
n-1
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9 n+10 n+11 n+12 n+13 n+14
(Note 3)
"H"
INPCij pin input
"L"
"1"
TMijR bit(2)
"0"
Write "0" by program
if setting to "0"
Delayed by max. 1 clock
GiTMj register
n
n+5
n+8
NOTES:
1. If the CAS bit in the GiBCR1 register is set to "1" (32-bit time measurement), the group 1 base timer
increments counter every time the group 0 base timer overflows.
2. Bits in the IIO0IR to IIO8IR, IIO10IR to IIO11R registers. The TM0jR bit if the CAS bit is set to "1".
3. Input pulses applied to the INPCij pin require 1.5 fBTi clock cycles or more.
(2) When selecting both edges as a time measurement trigger
(The CTS1 to CTS0 bits=112)
fBTi(1)
Base timer i
n-2
INPCij pin input
n-1
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9 n+10 n+11 n+12 n+13 n+14
"H"
"L"
(Note 3)
"1"
TMijR
bit(2)
"0"
Write "0" by program
if setting to "0"
GiTMj register
n
n+2
n+5
n+6
n+8
n+12
NOTES:
1. If the CAS bit in the GiBCR1 register is set to "1" (32-bit time measurement), the group 1 base timer increments
the counter whenever the group 0 base timer overflows.
2. Bits in the IIO0IR to IIO8IR, IIO10IR to IIO11R registers. The TM0jR register if the CAS bit is set to "1".
3. No interrupt is generated if the microcomputer receives a trigger signal when the TMijR bit is set to "1".
Howver, the value of the GiTMj register changes.
(3) Trigger signal when using the digital filter
(The DF1 to DF0 bits in the GiTMCR register =102 or 112)
fi or fBTi(1)
"H"
INPCij pin
"L"
Trigger signal
after passing the
digital filter
"H"
Signal, which does not match
three times, is stripped off
"L"
NOTES:
1. fBTi when the DF1 to DF0 bits are set to "102", and f1 when to "112".
Figure 21.22 Time Measurement Function (2)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 272 of 488
Maximum 3.5 fi or fBTi(1)
clock cycles
The trigger signal is delayed
by the digital filter
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Time Measurement Function)
(1) With the prescaler function
(When the GiTPRj register (i=0, 1, j=6, 7) =0216, the PR bit in the GiTMCR register=1)
fBTi(1)
Base timer i
n-2
n-1
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9 n+10 n+11 n+12 n+13 n+14
"H"
INPCij pin input
Internal time
measurement
trigger
"L"
"H"
"L"
Prescaler(2)
2
2
0
Write "0" by program
if setting to "0"
"1"
TMijR bit(3)
1
"0"
GiTMj register
n
n+12
NOTES:
1. If the CAS bit in the GiBCR1 register is set to "1" (32-bit time measurement), the group 1 base timer
increments the counter every time the group 0 base timer overflows.
2. This applies to the second or later prescaler cycles after the PR bit in the GiTMCRj register is set to "1".
3. Bits in the IIO0IR to IIO8IR, IIO10IR to IIO11IR registers. The TM0jR register if the CAS bit is set to "1".
(2) With the gate function
(The gate function is cleared by matching the base timer with the GiPOk register.
the GT bit in the GiTMCRj register=1, the GOC bit=1)
fBTi(1)
FFFF16
Value of the GiPOk register
Base timer i
000016
IFEj bit in GiFE
register
"1"
"0"
"H"
INPCij pin input
"L"
Internal time
measurement
trigger
GiPOk register
match signal
Gate control
signal(2)
"H"
"L"
"H"
"L"
"H"
"L"
Gate
"1"
TMijR bit(3)
This trigger input is disabled
due to the gate function.
Gate cleared
Gate
Write "0" by program if setting to "0"
"0"
GiTMj register
NOTES:
1. If the CAS bit in the GiBCR1 register is set to "1" (32-bit time measurement), the group 1 base timer
increments the counter every time the group 0 base timer overflows.
2. Bits in the IIO0IR to IIO8IR, IIO10IR to IIO11IR registers. The TM0jR register if the CAS bit is set to "1".
Figure 21.23 Prescaler Function and Gate Function
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 273 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Waveform Generation Function)
21.3 Waveform Generation Function
Waveforms are generated when the value of the base timer matches the GiPOj register (i=0 to 3; j=0 to 7).
The waveform generation function has the following six modes :
• Single-phase waveform output mode (group 0 to 3)
• Phase-delayed waveform output mode (group 0 to 3)
• Set/Reset waveform output (SR waveform output) mode (group 0 to 3)
• Bit modulation PWM output mode (group 2 and 3)
• Real-time port output (RTP output) mode (group 2 and 3)
• Parallel real-time port output (parallel RTP output) mode (group 2 and 3)
Table 21.7 lists pin settings of the waveform generation function. Table 21.8 lists registers associated with
the waveform generation function.
Table 21.7 Pin Settings for Waveform Generation Function (1/2)
Pin
Bit and Setting
PS0 to PS2, PS5 to PS9 Registers
PSL0, PSL1, PSL2, PSL3 Registers
PSC Register
P64/OUTC21
PS0_4 = 1
PSL0_4 = 1
-
P70/OUTC20
PS1_0 = 1
PSL1_0 = 0
PSC_0 = 1
P71/OUTC22
PS1_1 = 1
PSL1_1 = 0
PSC_1 = 1
P73/OUTC10(2)
PS1_3 = 1
PSL1_3 = 0
PSC_3 = 1
P74/OUTC11(2)
PS1_4 = 1
PSL1_4 = 0
PSC_4 = 1
P75/OUTC12(2)
PS1_5 = 1
PSL1_5 = 1
-
P76/OUTC00(2)
PS1_6 = 1
PSL1_6 = 0
PSC_6 = 0
P77/OUTC01(2)
PS1_7 = 1
-
-
P81/OUTC30
PS2_1 = 1
PSL2_1 = 1
-
P82/OUTC32
PS2_2 = 1
PSL2_2 = 0
-
P92/OUTC20
PS3_2 = 1
PSL3_2 = 1
-
P110/OUTC10(1,2)
PS5_0 = 1
-
-
P111/OUTC11(1,2)
PS5_1 = 1
P112/OUTC12(1,2)
PS5_2 = 1
P113/OUTC13(1,2)
PS5_3 = 1
P120/OUTC30(1)
PS6_0 = 1
-
-
P121/OUTC31(1)
PS6_1 = 1
P122/OUTC32(1)
PS6_2 = 1
P123/OUTC33(1)
PS6_3 = 1
P124/OUTC34(1)
PS6_4 = 1
P125/OUTC35(1)
PS6_5 = 1
P126/OUTC36(1)
PS6_6 = 1
P127/OUTC37(1)
PS6_7 = 1
P130/OUTC24(1)
PS7_0 = 1
-
-
P131/OUTC25(1)
PS7_1 = 1
NOTES:
1. This port is provided in the 144-pin package only.
2. When the CAS bit in the GiBCR1 register is set to "1" (32-bit time measurement function), the OUTC1j pin (j=0 to 7)
outputs a waveform and the OUTC0k pin (k=0, 1, 4, 5), set as above, outputs a 16-bit low-order waveform.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 274 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Waveform Generation Function)
Table 21.7 Pin Settings for Waveform Generation Function (2/2)
Pin
Bit and Setting
PS0 to PS2, PS5 to PS9 Registers
PSL0, PSL1, PSL2, PSL3 Registers
PSC Register
P132/OUTC26(1)
PS7_2 = 1
-
-
P133/OUTC23(1)
PS7_3 = 1
P134/OUTC20(1)
PS7_4 = 1
P135/OUTC22(1)
PS7_5 = 1
P136/OUTC21(1)
PS7_6 = 1
P137/OUTC27(1)
PS7_7 = 1
P140/OUTC14(1,2)
PS8_0 = 1
-
-
P141/OUTC15(1,2)
PS8_1 = 1
P142/OUTC16(1,2)
PS8_2 = 1
P143/OUTC17(1,2)
PS8_3 = 1
P150/OUTC00(1,2)
PS9_0 = 1
-
-
P151/OUTC01(1,2)
PS9_1 = 1
P154/OUTC04(1,2)
PS9_4 = 1
P155/OUTC05(1,2)
PS9_5= 1
NOTES:
1. This port is provided in the 144-pin package only.
2. When the CAS bit in the GiBCR1 register is set to "1" (32-bit time measurement function), the OUTC1j pin (j=0 to 7)
outputs a waveform and the OUTC0k pin (k=0, 1, 4, 5), set as above, outputs a 16-bit low-order waveform.
Table 21.8 Waveform Generation Function Associated Register Settings
Register
GiPOCRj
G2BCR1
G3BCR1
GiPOj
G3MK4 to
G3MK7
GiFS
GiFE
G2RTP
G3RTP
Bit
MOD2 to MOD0
PRT(1)
IVL
RLD
RTP(1)
Function
Select waveform output mode
Set to "1" when using the parallel RTP output mode
Select default value
Select reload timing of GiPOj register value
Set to "1" when using the RTP output or the parallel RTP output mode
MOD2 to MOD0 bits are invalid when the RTP bit is set to "1"
INV
PRP
Select inversed output
Set to "1" when using the parallel RTP output mode
-
Select output waveform inverse timing
Set masked values of the base timer and G3PO4 to G3PO7 registers
(group 3 only)
Set to "0" (waveform generation function) (group 0 and 1 only)
Set to "1" (enables channel j function)
FSCj
IFEj
RTP0 to
RTP7
Set RTP output value in RTP output or parallel RTP output mode
i = 0 to 3; j = 0 to 7
Bit configurations and functions vary with channels and groups used.
Set registers associated with the waveform generation function after setting registers associated with the base timer.
NOTES:
1. This bit is in the G2POCRj and G3POCRj registers only.
Rev. 1.31 Jan.31, 2006 Page 275 of 488
REJ09B0034-0131
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Waveform Generation Function)
21.3.1 Single-Phase Waveform Output Mode (Group 0 to 3)
Output signal level of the OUTCij pin (i=0 to 3; j=0 to 7) becomes high ("H") when the value of the base
timer matches that of the GiPOj register . The "H" signal switches to an "L" signal when the base timer
reaches "000016". If the IVL bit in the GiPOCRj register is set to "1" (outputs "H" as default value), an "H"
signal is output when waveform output starts. If the INV bit is set to "1" (output inversed), the level of the
waveform being output is inversed. See Figure 21.24 for details on single-phase waveform mode operation. Table 21.9 lists specifications of single-phase waveform mode.
Table 21.9 Single-phase Waveform Output Mode Specifications
Item
Specification
Output Waveform(3)
• Free-running operation
(the RST2 to RST0 bits in the GiBCR1 (i=0 to 3) register are set to "0002")
Cycle
:
"L" width
:
"H" width
:
65536
fBTi
m
fBTi
65536-m
fBTi
m : setting value of the GiPOj register (j=0 to 7), 000016 to FFFF16
• The base timer is reset by matching the base timer with the GiPO0 register
(the RST1 bit is set to "1", and the RST0 and the RST2 bit are set to "0")
n+2
Cycle
:
fBTi
m
"L" width
:
fBTi
n+2-m
fBTi
m : setting value of the GiPOj register (j=1 to 7), 000016 to FFFF16
"H" width
:
n : setting value of the GiPO0 register, 000116 to FFFD16
If m ≥ n+2, the output level is fixed to "L"
Waveform Output Start
Condition(1)
The IFEj bit in the GiFE register is set to "1" (channel j function enabled)
Waveform Output Stop Condition
The IFEj bit is set to "0" (channel j function disabled)
Interrupt Request
The POijR bit in the interrupt request register is set to "1" (interrupt requested)
when the value of the base timer matches that of the GiPOj register. (See
Figure 10.14)
OUTCij
Pin(2)
Selectable Function
Pulse signal output pin
• Default value set function : Set starting waveform output level
• Inversed output function : Waveform output level is inversed and output from
the OUTCij pin
• Cascaded connection function: Connect group 0 and group 1 to operate as a
32-bit base timer
NOTES:
1. Set the FSCj bit in the GiFS register to "0" (waveform generation function selected) when using channels shared by
both time measurement function and waveform generation function
2. OUTC00, OUTC01, OUTC04, OUTC05, OUTC10 to OUTC17, OUTC20 to OUTC27, and OUTC30 to OUTC37 pins
(OUTC10 to OUTC17 pins when using group 0 and group 1 cascaded connection)
3. When the INV bit in the GiPOCRj register is set to "1" (output inversed), the "L" width and "H" width are inversed
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 276 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Waveform Generation Function)
(1) Free-Running Operation
(The RST2 to RST0 bits in the GiBCR1 register are set to "0002")
FFFF16
Base Timer i
m
000016
m
fBTi
OUTCij pin(1)
"H"
"L"
OUTCij pin(2)
POijR bit in the
IIOiIR register
65536-m
fBTi
65536
fBTi
"H"
"L"
Write "0" by program
if setting to "0"
"1"
"0"
i=0 to 3; j=0 to 7 (however, i=0 when j=0, 1, 4, 5)
m : Setting value of the GiPOj register (000016 to FFFF16)
POijR bit: Bits in the IIO0IR to IIO11IR register
NOTES:
1. Waveform output when the INV bit in the GiPOCRj register is set to "0" (not inversed)
and the IVL bit is set to "0" (output "L" as default value).
2. Waveform output when the INV bit is set to "0" (not inversed) and the IVL bit is set to "1"
(output "H" as default value).
The above applies applies under the following conditions:
• The RST2 to RST0 bits in the GiBCR1 register are set to "0002" (no base timer reset),
the UD1 to UD0 bits to "002" (counter increment mode), and CAS bit to "0"
(16-bit waveform generation function)
(2) The Base Timer is Reset when the Base Timer Matches the GiPO0 Register
(The RST1 bit is set to "1", and the RST0 and RST2 bits are set to "0")
n+2
Base Timer i
m
000016
m
fBTi
n+2-m
fBTi
"H"
OUTCij pin
"L"
n+2
fBTi
POijR bit in the
IIOiIR register
"1"
"0"
Write "0" by
program if
setting to "0"
i=0 to 3; j=1 to 7 (however, i=0 when j=1, 4, 5)
m : Setting value of the GiPOj register (000016 to FFFF16)
n : Setting value of the GiPO0 register (000116 to FFFD16)
POijR bit: Bits in the IIO0IR to IIO11IR register
The above diagram applies under the following conditions:
• The IVL bit in the GiPOCRj register is set to "0" (outputs "L" as default value). The INV
bit is set to "0" (not inverse).
• The UD1 to UD0 bits in the GiBCR1 register are set to "002" (counter increment mode),
and the CAS bit to "0" (16-bit waveform generation function)
• m < n+2
Figure 21.24 Single-Phase Waveform Output Mode
Rev. 1.31 Jan.31, 2006 Page 277 of 488
REJ09B0034-0131
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Waveform Generation Function)
21.3.2 Phase-Delayed Waveform Output Mode (Group 0 to 3)
Output signal level of the OUTCij pin (i=0 to 3; j=0 to 7) is inversed every time the value of the base timer
matches that of the GiPOj register. Table 21.10 lists specifications of phase-delayed waveform mode.
Figure 21.25 shows an example of phase-delayed waveform mode operation.
Table 21.10 Phase-delayed Waveform Output Mode Specifications
Item
Specification
Output Waveform
• Free-running operation
(the RST2 to RST0 bits in the GiBCR1 register (i=0 to 3) are set to "0002")
Cycle
:
"H" and "L" width
:
65536 x 2
fBTi
65536
fBTi
Setting value of the GiPOj (j=0 to 7) register is 000016 to FFFF16
• The base timer is reset by matching the base timer with the GiPO0 register
(the RST1 bit is set to "1", and the RST0 and RST2 bit are set to "0")
2(n+2)
Cycle
:
fBTi
n+2
"H" and "L" width
:
fBTi
n : setting value of the GiPO0 register, 000116 to FFFD16
Setting value of the GiPOj (j=1 to 7) register is 000016 to FFFF16
If GiPOj register ≥ n+2, the output level is not inversed
Waveform Output Start
Condition(1)
The IFEj bit (j=0 to 7) in the GiFE register is set to "1" (channel j function
enabled)
Waveform Output Stop Condition
The IFEj bit is set to "0" (channel j function disabled)
Interrupt Request
The POijR bit in the interrupt request register is set to "1" (interrupt requested)
when the value of the base timer matches that of the GiPOj register. (See
Figure 10.14)
OUTC1j Pin
Pulse signal output pin
Selectable Function
• Default value set function : Set starting waveform output level
• Inversed output function : Waveform output level is inversed and output from
the OUTCij pin
• Cascaded connection function: Connect group 0 and group 1 to operate as a
32-bit base timer
NOTES:
1. Set the FSCj bit in the GiFS register to "0" (waveform generation function selected) when using channels shared by
both time measurement function and waveform generation function
2. OUTC00, OUTC01, OUTC04, OUTC05, OUTC10 to OUTC17, OUTC20 to OUTC27, and OUTC30 to OUTC37 pins
(OUTC10 to OUTC17 pins when using group 0 and group 1 cascaded connection)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 278 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Waveform Generation Function)
(1) Free-Running Operation
(The RST2 to RST0 bits in the GiBCR1 register are set to "0002")
FFFF16
Base Timer i
m
000016
65536
fBTi
65536
fBTi
"H"
OUTCij pin(1)
OUTCij
pin(2)
"H"
65536X2
fBTi
Inverse
Inverse
"L"
Write "0" by program
if setting to "0"
"1"
POijR bit
Inverse
Inverse
"L"
"0 "
i=0 to 3; j=0 to 7 (however, i=0 when j= 0, 1, 4, 5)
m : Setting value of the GiPOj register (000016 to FFFF16)
POijR bit: Bits in the IIO0IR to IIO11IR registers
NOTES:
1. Waveform output when the INV bit in the GiPOCRj register is set to "0" (not inversed) and
the IVL bit is set to "0" (output "L" as initial value).
2. Waveform output when the INV bit is set to "0" (not inversed) and the IVL bit is set to "1"
(output "H" as initial value).
The above diagram applies under the following condition:
• The RST2 to RST0 bits in the GiBCR1 register are set to "0002" (no base timer reset),
the UD1 to UD0 bits to "002" (counter increment mode), and the CAS bit to "0"
(16-bit waveform generation function).
(2) The Base Timer is Reset when the Base Timer Matches the GiPO0 Register
(The RST1 bit is set to "1", and the RST0 and RST2 bits are set to "0")
n+2
Base Timer i
m
000016
m
fBTi
OUTCij pin
PO1jR bit
"H"
"L"
"1"
n+2
fBTi
Inverse
Write "0" by
program if
setting to "0"
n+2
fBTi
Inverse
Inverse
2(n+2)
fBTi
"0"
i=0 to 3; j=0 to 7 (however, i=0 when j=1, 4, 5)
m : Setting value of the GiPOj register (000016 to FFFF16)
n : Setting value of the GiPO0 register (000116 to FFFD16)
POijR bit: Bits in the IIO0IR to IIO11IR registers
The above diagram applies under the following conditions:
• The IVL bit in the GiPOCRj register is set to "0" (outputs "L" as initial value). The INV bit is set
to "0" (not inversed).
• The UD1 to UD0 bits in the G1BCR1 register are set to "002" (counter increment mode) and
the CAS bit to "0" (16-bit waveform generation function).
• m < n+2
Figure 21.25 Phase-delayed Waveform Output Mode
Rev. 1.31 Jan.31, 2006 Page 279 of 488
REJ09B0034-0131
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Waveform Generation Function)
21.3.3 Set/Reset Waveform Output (SR Waveform Output) Mode (Group 0 to 3)
Output signal level of the OUTCij pin (i=0 to 3; j=0, 2, 4, 6) becomes "H" when the value of the base timer
matches that of the GiPOj register. The "H" signal switches to an "L" signal when the value of the base
timer matches that of the GiPOk register (k=j+1) or when the base timer is set to "000016". If the IVL bit
in the GiPOCRj register (j=0 to 7) is set to "1" (outputs "H" as initial value), an "H" signal is output when
waveform output starts. If the INV bit is set to "1" (output is inversed), the level of the waveform being
output is inversed. Table 21.11 lists specifications of SR waveform mode. Figure 21.26 shows an example of a SR waveform mode operation.
Table 21.11 SR Waveform Output Mode Specifications (1/2)
Item
Output Waveform(2)
Specification
• Free-running operation
(the RST2 to RST0 bits in the GiBCR1 register are set to "0002")
(1) m < n
"H" width
:
n-m
fBTi
"L" width
:
m (3)
fBTi
65536 - n(4)
fBTi
+
(2) m ≥ n
"H" width
"L" width
65536 - m
fBTi
m
:
fBTi
:
m : setting value of the GiPOj register (j=0, 2, 4, 6)
n : setting value of the GiPOk register (k=j+1)
m, n=000016 to FFFF16
• The base timer is reset by matching the base timer with the GiPO0 register (1)
(the RST1 bit is set to "1", and the RST0 and RST2 bits are set to "0")
(1) m < n < p+2
"H" width
:
"L" width
:
n-m
fBTi
m (3)
fBTi
+
p + 2 - n(4)
fBTi
(2) m < p+2 ≤ n
"H" width
:
"L" width
:
p+2-n
fBTi
m
fBTi
(3) If m ≥ p+2, the output level is fixed to "L"
m : setting value of the GiPOj register (j=2, 4, 6)
n : setting value of the GiPOk register (k=j+1)
p : setting value of the GiPO0 register
m, n=000016 to FFFF16
p=000116 to FFFD16
NOTES:
1. When the GiPO0 register resets the base timer, the channel 0 and 1 SR waveform generation functions are not
available.
2. When the INV bit in the GiPOCRj register is set to "1" (output inversed), the "L" width and "H" width are inversed.
3. Waveform from base timer reset until when output level becomes "H".
4. Waveform from when output level becomes "L" until base timer reset.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 280 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Waveform Generation Function)
Table 21.11 SR Waveform Output Mode Specifications (2/2)
Item
Specification
Waveform Output Start Condition(5) The IFEq bit (q=0 to 7) in the GiFE register is set to "1" (channel q function
enabled)
Waveform Output Stop Condition
The IFEq bit is set to "0" (channel q function disabled)
Interrupt Request
The POijR bit in the interrupt request register is set to "1" (interrupt requested)
when the value of the base timer matches that of the GiPOj register.
The POikR bit in the interrupt request register is set to "1" (interrupt requested)
when the value of the base timer matches that of the GiPOk register. (See
Figure 10.14)
OUTCij
Pin(6)
Selectable Function
Pulse signal output pin
• Default value set function : Set starting waveform output level
• Inversed output function : Waveform output level is inversed and output from
the OUTCij pin
• Cascaded connection function: Connect group 0 and group 1 to operate as a
32-bit base timer
NOTES:
5. Set the FSCj bit in the GiFS register to "0" (waveform generation function selected) when using channels shared by
both time measurement function and waveform generation function
6. OUTC00, OUTC04, OUTC10, OUTC12, OUTC14, OUTC16, OUTC20, OUTC22, OUTC24, OUTC26, OUTC30,
OUTC32, OUTC34, and OUTC36 pins
(OUTC10, OUTC12, OUTC14, and OUTC16 pins when using group 0 and group 1 cascaded connection)
Rev. 1.31 Jan.31, 2006 Page 281 of 488
REJ09B0034-0131
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Waveform Generation Function)
(1) Free-Running Operation
(The RST2 to RST0 bits in the GiBCR1 register are set to "0002")
FFFF16
n
Base Timer i
m
000016
n-m
fBTi
OUTCij pin(1)
OUTCij
pin(2)
65536-n+m
fBTi
"H"
"L"
65536
fBTi
"H"
"L"
"1"
POijR bit
Write "0" by program
if setting to "0"
"0"
Write "0" by program
if setting to "0"
"1"
POikR bit
"0"
i=0, 3; j=0, 2, 4, 6 (however, i=0 when j=0, 4); k=j+1
m : Setting value of the GiPOj register (000016 to FFFF16)
n : Setting value of the GiPOk register (000016 to FFFF16)
POijR, POikR bits: Bits in the IIO0IR to IIO11IR registers
NOTES:
1. Waveform output when the INV bit in the GiPOCRj register is set to "0" (not inversed) and
the IVL bit is set to "0" (output "L" as default value).
2. Waveform output when the INV bit is set to "0" (not inversed) and the IVL bit is set to "1"
(output "H" as default value).
The diagram above applies under the following condition:
• The RST2 to RST0 bits in the GiBCR1 register are set to "0002" (no base timer reset),
the UD1 to UD0 bits to "002" (counter increment mode), and the CAS bit to "0"
(16-bit waveform generation function).
• m<n
(2) The Base Timer is Reset when the Base Timer Matches the GiPO0 Register
(The RST1 bit is set to "1", and the RST0 and RST2 bits are set to "0")
p+2
n
Base timer i
m
000016
OUTCij pin
POijR bit
n-m
fBTi
"H"
"L"
"1"
"0"
"1"
POikR bit
p+2-n+m
fBTi
p+2
fBTi
Write "0" by program
if setting to "0"
Write "0" by program
if setting to "0"
"0"
i=0 to 3; j=2, 4, 6 (however, i=0 when j=4); k=j+1
m : Setting value of the GiPOj register (000016 to FFFF16)
n: Setting value of the GiPOk register (000016 to FFFF16)
p: Setting value of the GiPO0 register (000116 to FFFD16)
POijR, POikR bits: Bits in the IIO0IR to IIO11IR registers
The diagram above applies under the following conditions:
• The IVL bit in the GiPOCRk register is set to "0" (outputs "0" as default value). The INV bit is set
to "0" (not inversed).
• The UD1 to UD0 bits in the GiBCR1 register are set to "002" (counter increment mode) and
the CAS bit to "0" (16-bit waveform generation function).
• m < n < p+2
Figure 21.26 SR Waveform Output Mode
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 282 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Waveform Generation Function)
21.3.4 Bit Modulation PWM Output Mode (Group 2 and 3)
In bit modulation PWM output mode, PWM output has a 16-bit resolution. Pulses are output in repetitive
64
cycles, each cycle consisting of span t repeated 1024 times. Span t, itself, has a cycle of
. The six
fBTi
high-order bits in the GiPOj register (i=2 to 3; j=0 to 7) determine the "L" base width. The 10 low-order bits
determine the number of span t, within a cycle, in which "L" width is extended by the minimum resolution bit
width (1 clock cycle). If the INV bit is set to "1" (output is inversed), the level of the waveform being output
is inversed.
Table 21.12 lists specifications of bit modulation PWM output mode. Table 21.13 lists the number of
modulated span and minimum resolution bit width altered span t. Figure 21.27 shows an example of bit
modulation PWM mode operation.
Table 21.12 Bit Modulation PWM Output Mode Specifications
Item
Output Waveform(1,2)
Specification
PWM-repeated cycle T: 65536 (= 64 X1024)
fBTi
fBTi
64
Cycle of span t:
fBTi
n+1
"L" width: of m spans
fBTi
n
of (1024-m) spans
fBTi
m
1
Average "L" output width:
X (n+
)
1024
fBTi
n: Setting values (six high-order bits) of the GiPOj register (i=2 to 3; j=0 to 7)
0016 to 3F16
m: Setting values (ten low-order bits) of the GiPOj register 0016 to 3FF16
Waveform Output Start Condition
The IFEj bit in the GiFE register is set to "1" (channel j function enabled)
Waveform Output Stop Condition
The IFEj bit is set to "0" (channel j function disabled)
Interrupt Request
The POijR bit in the interrupt request register is set to "1" when the value of the
six low-order bits of the base timer matches those set in the six high-order bits
of the GiPOj register (see Figure 10.14).
OUTCij Pin
Pulse signal output pin
Selectable Function
• Default value set function : Set starting waveform output level
• Inversed output function : Waveform output level is inversed and output from
the OUTCij pin
NOTES:
1. Set the RST2 to RST0 bits in the GiBCR1 register to "0002" when using the bit modulation PWM mode.
2. When the INV bit in the GiPOCRj register is set to "1" (output inversed), the "L" width and "H" width are inversed.
Table 21.13. Number of Modulated Spans and Minimum Resolution Bit Width Extended Span t
00 0000 00002
none
00 0000 00012
t512
00 0000 00102
t256, t768
00 0000 01002
t128, t384, t640, t896
00 0000 10002
t64, t192, t320, t448, t576, t704, t832, t960
10 0000 00002
Rev. 1.31 Jan.31, 2006 Page 283 of 488
REJ09B0034-0131
•••
Minimum Resolution Bit Width Extended Span t
•••
Number of Modulated Spans
t1, t3, t5, t7, •••
t1019, t1021, t1023
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Waveform Generation Function)
Base width
n=0 to 63 (3F16)
b15
Modulated span
m=0 to 1023 (3FF16)
b10 b9
b0
GiPOj register
PWM-repeated cycle T
6 low-order bits
in the base timer
3F16
n
0016
n
OUTCij pin
t1
t2
t3
t510
t511
1 span
6 low-order bits
in the base timer
A
t512
t3
t1022
t1023
t1024
t513
t514
"L" width of m span out of 1024 is extended by
minimum resolution bit width
3F16
n
0016
fBTi
A
A
Minimum resolution bit width
Internal signal
n
OUTCij pin
POijR bit
n+1
Inverse
"L" level
Inverse
"L" level
Write "0" by program
if setting to "0"
Write "0" by program
if setting to "0"
m=1; i=2 to 3; j=0 to 7
POijR bit : Bits in the IIO3IR to IIO11IR registers
The above applies to the following conditions.
• The IVL bit in the GiPOCR is set to "0" (default value output as "L")
• The INV bit is set to "0" (no output inversed)
Figure 21.27 Bit Modulation PWM Mode
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 284 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Waveform Generation Function)
21.3.5 Real-Time Port (RTP) Output Mode (Group 2 and 3)
The OUTCij pin outputs the value set in the GiRTP register in one-byte units by matching the value of the
base timer with that of the GiPOj register (i=2 to 3, j=0 to 7). Table 21.14 lists specifications of RTP output
mode. Figure 21.28 shows a block diagram of the RTP output function. Figure 21.29 shows an example
of RTP output mode operation.
Table 21.14 RTP Output Mode Specifications
Item
Specification
Waveform Output Start Condition
The IFEj bit in the GiFE register (i=2 to 3, j=0 to 7) is set to "1" (channel j function
enabled)
Waveform Output Stop Condition
The IFEj bit is set to "0" (channel j function disabled)
Interrupt Request
The POijR bit in the interrupt request register is set to "1" when the value of
the base timer matches that of the GiPOj register (000016 to FFFF16(1)).
(See Figure 10.14.)
OUTCij Pin
RTP output pin
Selectable Function
• Default value set function : Set starting waveform output level
• Inversed output function : Waveform output level is inversed and output from
the OUTCij pin
NOTES:
1. Set the GiPO0 register to 000116 to FFFD16 when setting the base timer to "000016" (the RST1 bit in the GiBCR1
register is set to "1", and the RST0 and RST2 bits are set to "0") while the values in the base timer and the GiPO0
register match
Base Timer
AAA
AAA
AAA
AAA
AAA
AAA
GiRTP register
RTP0
GiPO0 register
RTP6
GiPO6 register
RTP7
GiPO7 register
Real-time Port Output
DQ
DQ
OUTCi6
T
DQ
T
Figure 21.28 Real-time Port Output Function Block Diagram
Rev. 1.31 Jan.31, 2006 Page 285 of 488
REJ09B0034-0131
OUTCi0
T
OUTCi7
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Waveform Generation Function)
(1) Free-running operation
(RST2 to RST0 bits in the GiBCR1 register are set to "0002")
FFFF16
Base timer i
m
000016
RTPj bit
0
1
0
1
"H"
"L"
OUTCij pin
65535
m
Write "0" by program
if setting to "0"
"1"
POijR bit
"0"
i=2 to 3, j=0 to 7
m : Setting value of the GiPOj register (000016 to FFFF16)
POijR bit : Bits in the IIO3IR to IIO11IR registers
The above applies to the following conditions.
The IVL bit in the GiPOCRj register is set to "0" (output "L" as an initial value). The INV
bit is set to "0" (no output inversed).
RST2 to RST0 bits in the GiBCR1 register are set to "0002" (no base timer reset).
(2) The base timer is reset when the base timer matches the GiPO0 register
(The RST1 bit is set to "1" and both RST0 and RST2 bits are set to "0")
FFFF16
n+2
Base timer i
m
000016
RTPj bit
OUTCij pin
POijR bit
1
0
0
1
"H"
"L"
m
n+2
"1"
"0"
Write "0" by program
if setting to "0"
i=2 to 3, j=1 to 7
m : Setting value of the GiPOj register (000016 to FFFF16)
n: Setting value of the GiPO0 register (000116 to FFFD16)
POijR bit : Bits in the IIO0IR to IIO11IR registers
The above applies to the following condition.
The IVL bit in the GiPOCRj register is set to "0" (output "L" as an initial value). The INV
bit is set to "0" (no output inversed).
m < n+2
Figure 21.29 Real-time Port Output Mode
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 286 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Waveform Generation Function)
21.3.6 Parallel Real-Time Port Output Mode (Group 2 and 3)
The OUTCij pin outputs the value set by the GiRTP register in one-byte units when the value of the base
timer matches that of the GiPOj register (i=2 to 3, j=0 to 7). Table 21.15 lists specifications of the parallel
RTP output mode. Figure 21.30 shows a block diagram of the parallel RTP output function. Figure 21.31
shows an example of the parallel RTP output mode operation. (See Figure 21.7 for the G2BCR1 register
and Figure 21.8 for the G3BCR1 register.)
Table 21.15 Parallel RTP Output Mode Specifications
Item
Specification
Waveform Output Start Condition
The IFEj bit in the GiFE register (i=2 to 3, j=0 to 7) is set to "1" (channel j function
enabled)
Waveform Output Stop Condition
The IFEj bit is set to "0" (channel j function disabled)
Interrupt Request
The POijR bit in the interrupt request register is set to "1" when value of the
base timer matches that of the GiPOj register (000016 to FFFF16(1)). (See
Figure 10.14.)
OUTCij Pin
RTP output
Selectable Function
• Default value set function: Set starting waveform output level
• Inverse output function: Waveform output level is inversed and output from
the OUTCij pin
NOTES:
1. Set the GiPO0 register to 000116 to FFFD16 when setting the base timer to "000016" (the RST1 bit in the GiBCR1
register is set to "1", and the RST0 and RST2 bits are set to "0") while the values in the base timer and the GiPO0
register match
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
GiRTP register
Base Timer
GiPO0 register
GiPO1 register
GiPO2 register
GiPO3 register
GiPO4 register
GiPO5 register
GiPO6 register
GiPO7 register
i=2 to 3
RTP0
RTP1
RTP2
RTP3
RTP4
RTP5
RTP6
RTP7
Figure 21.30 Parallel RTP Output Function Block Diagram
Rev. 1.31 Jan.31, 2006 Page 287 of 488
REJ09B0034-0131
Real-time Port Output
DQ
OUTCi0
T
DQ
OUTCi1
T
DQ
OUTCi2
T
DQ
OUTCi3
T
DQ
OUTCi4
T
DQ
OUTCi5
T
DQ
OUTCi6
T
DQ
T
OUTCi7
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Waveform Generation Function)
(1) Free-running operation
FFFF16
p
Base timer i
n
m
000016
GiRTP register
X0
X1
X3
X6
XC
OUTCi0 pin
OUTCi1 pin
OUTCi2 pin
OUTCi3 pin
POi0R bit
POi1R bit
POi2R bit
m : Setting value of the GiPO0 register
i=2,3
n : Setting value of the GiPO1 register
p : Setting value of the GiPO2 register
POi0R, POi1R, POi2R bit : Bits in the IIO3IR to IIO11IR registers
The above applies to the following conditions.
The IVL in the of GiPOCRj register is set to "0" (output "L" as an initial value).
The INV bit is set to "0" (no output inversed).
All RST0 to RST2 bits in the GiBCR1 register are set to "0002" (no base timer reset).
m<n<p
Figure 21.31 Parallel RTP Output Mode
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 288 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Group 0, 1 Communication Function)
21.4 Communication Unit 0 and 1 Communication Function
The communication function is available when two 8-bit shift registers are used with either timer measurement function or waveform generation function.
In the intelligent I/O groups 0 and 1, 8-bit clock synchronous serial I/O, 8-bit clock asynchronous serial I/O
(UART) and HDLC data processing are available.
Figures 21.32 to 21.38 show registers associated with the communication function.
Group i Receive Input Register (i=0,1)
b7
b0
Symbol
Address
00EC16, 012C16
G0RI,G1RI
Function
Set data to be transmitted to a received
data generation circuit
After Reset
Indeterminate
Setting Range
RW
0016 to FF16
WO
Group i Transmit Output Register (i=0,1)
b7
b0
Symbol
G0TO, G1TO
Address
00EE16, 012E16
After Reset
Indeterminate
Function
Can read data transmitted by a transmitted data generation circuit
Figure 21.32 G0RI to G1RI Registers and G0TO to G1TO Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 289 of 488
RW
RO
21. Intelligent I/O (Group 0, 1 Communication Function)
M32C/83 Group (M32C/83, M32C/83T)
Group i SI/O Communication Control Register (i=0,1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
After Reset
G0CR, G1CR
00EF16, 012F16
0000 X0002
Bit
Symbol
TI
Bit Name
Transmit Buffer
Empty Flag
Transmit Register
TXEPT
Empty Flag
RI
(b3)
Receive Complete
Flag
RW
0 : Data in the GiTB register
1 : No data in the GiTB register
RO
0 : Data in the transmit register
(during transmission)
1 : No data in the transmit register
(transmit completed)
RO
0 : No data in the GiRB register
1 : Data in the GiRB register
RO
Nothing is assigned. When write, set to "0".
When read, its contents is indeterminate.
TE
Transmit Enable Bit
0 : Transmit disable
1 : Transmit enable
RW
RE
Receive Enable Bit
0 : Receive disable
1 : Receive enable
RW
IPOL
ISRxD Input Polarity 0 : No inverse
1 : Inverse(1)
Switch Bit
RW
OPOL
ISTxD Output Polarity 0 : No inverse
1 : Inverse(1)
Switch Bit
RW
NOTES:
1. Set to "1" when using UART mode
Figure 21.33 G0CR to G1CR Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Function
Page 290 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Group 0, 1 Communication Function)
Group i SI/O Receive Buffer Register (i=0,1)
b15
b8 b7
b0
Symbol
G0RB, G1RB
Bit
Symbol
Address
00E916-00E816, 012916-012816
Bit Name
After Reset
XX00 XXXX XXXX XXX2
Function
Received data
(b7 - b0)
RW
RW
Nothing is assigned.
When read, its content is indeterminate.
(b11 - b8)
OER
Overrun Error Flag
0 : No overrun error
1 : Overrun error found
RO
FER
Framing Error Flag
0 : No framing error
1 : Framing error found
RO
Nothing is assigned.
(b15 - b14) When read, its content is indeterminate.
Group i SI/O Communication Mode Register (i=0,1)
b7
b6
b5
b4
0 0
b3
b2
b1
b0
Symbol
G0MR,G1MR
Bit
Symbol
Address
00ED16, 012D16
After Reset
0016
Bit Name
Function
RW
b1 b0
GMD0
Communication Mode
Select Bit
GMD1
0 0 : UART mode
RW
0 1 : Clock synchronous serial I/O
mode
1 0 : Special communication mode(1) RW
1 1 : HDLC data processing mode
CKDIR
Internal/External Clock
Select Bit
0 : Internal clock
1 : External clock
RW
STPS
Stop Bit Length
Select Bit
0 : 1 stop bit
1 : 2 stop bits
RW
Reserved Bit
Set to "0"
RW
UFORM
Transfer Direction
Select Bit
0 : LSB first
1 : MSB first
RW
IRS
Transmit Interrupt
Cause Select Bit
0 : No data in the transmit
buffer (TI=1)
1 : Transmission is completed
(TXEPT=1)
RW
(b5 - b4)
NOTES:
1. Do not set except when using in motor vehicles
Figure 21.34 G0RB to G1RB Registers and G0MR to G1MR Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 291 of 488
21. Intelligent I/O (Group 0, 1 Communication Function)
M32C/83 Group (M32C/83, M32C/83T)
Group i SI/O Expansion Mode Register (i=0,1)(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
G0EMR,G1EMR
Bit
Symbol
Address
After Reset
00FC16, 013C16
0016
Bit Name
Function
RW
SMODE
Synchronous Mode
Select Bit
0 : No re-synchronous mode used
1 : Re-synchronous mode
RW
CRCV
CRC Default Value
Select Bit
0 : Set to "000016"
1 : Set to "FFFF16"
RW
ACRC
CRC Reset Select Bit
0 : Not reset
1 : Reset(2)
RW
BSINT
Bit Stuffing Error
Interrupt Select Bit
0 : Not used
1 : Used
RW
RXSL
Receive Source
Switch Bit
0 : ISRxDi pin
1 : GiRI register
RW
TXSL
Transmit Source
Switch Bit
0 : ISTxDi pin
1 : GiTO register
RW
b7 b6
CRC0
CRC Generation
Polynomial Select Bit
CRC1
0
0
1
1
0
1
0
1
: X8+X4+X+1
: Do not set to this value
: X16+X15+X2+1
: X16+X12+X5+1
RW
RW
NOTES:
1. The GiEMR register is used in special communication mode or HDLC data processing mode. Do not
use in clock synchronous serial I/O mode or UART mode.
2. The CRC is reset when a data in the GiCMP3 register matches a received data.
Group i SI/O Expansion Transmit Control Register (i=0,1)(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
After Reset
G0ETC,G1ETC
00FF16, 013F16
0000 0XXX2
Bit
Symbol
Bit Name
Function
RW
Nothing is assigned. When write, set to "0".
(b2 - b0) When read, its content is indeterminate.
SOF
SOF Transmit
Request Bit
0 : No request to transmit SOF
1 : Request to transmit SOF
RW
TCRCE
Transmit CRC
Enable Bit
0 : Not used
1 : Used
RW
ABTE
Arbitration Enable Bit
0 : Not used
1 : Used
RW
TBSF0
Transmit Bit Stuffing
"1" Insert Select Bit
0 : "1" is not inserted
1 : "1" is inserted
RW
TBSF1
Transmit Bit Stuffing
"0" Insert Select Bit
0 : "0" is not inserted
1 : "0" is inserted
RW
NOTES:
1. The GiETC register is used in special communication mode or HDLC data processing mode. Do not
use in clock synchronous serial I/O mode or UART mode.
Figure 21.35 G0EMR to G1EMR Registers and G0ETC to G1ETC Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 292 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Group 0, 1 Communication Function)
Group i SI/O Expansion Receive Control Register (i=0,1)(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
G0ERC,G1ERC
Address
00FD16, 013D16
After Reset
0016
Bit
Symbol
Bit Name
CMP0E
Data Compare
Function 0
Select Bit
0 : The GiDR register (transmit data register) is
not compared with the GiCMP0 register
1 : The GiDR register is compared with the
GiCMP0 register
RW
CMP1E
Data Compare
Function 1
Select Bit
0 : The GiDR register (transmit data register) is
not compared with the GiCMP1 register
1 : The GiDR register is compared with the
GiCMP1 register
RW
CMP2E
Data Compare
Function 2
Select Bit
0 : The GiDR register (transmit data register) is
not compared with the GiCMP2 register
1 : The GiDR register is compared with the
GiCMP2 register
RW
CMP3E
Data Compare
Function 3
Select Bit
0 : The GiDR register (transmit data register) is
not compared with the GiCMP3 register
1 : The GiDR register is compared with the
GiCMP3 register(2)
RW
RCRCE
Receive CRC
Enable Bit
0 : Not used
1 : Used
RW
RSHTE
Receive Shift
Operation
Enable Bit
0 : Disables receive shift operation
1 : Enables receive shift operation
RW
RBSF0
Receive Bit
Stuffing
"1" Delete
Select Bit
0 : "1" is not deleted
1 : "1" is deleted
RW
RBSF1
Receive Bit
Stuffing
"0" Delete
Select Bit
0 : "0" is not deleted
1 : "0" is deleted
RW
Function
RW
NOTES:
1. The GiERC register is used in special communication mode or HDLC data processing mode.
Set to "0010 00002" in clock synchronous serial I/O mode. Do not use in UART mode.
2. When the ACRC bit in the GiEMR register is set to "1" (CRC reset function used), set the CMP3E bit
to "1".
Figure 21.36 G0ERC to G1ERC Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 293 of 488
21. Intelligent I/O (Group 0, 1 Communication Function)
M32C/83 Group (M32C/83, M32C/83T)
Group i SI/O Special Communication Interrupt Detect Register (i=0,1)(1,2)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
G0IRF,G1IRF
Bit
Symbol
Address
00FE16, 013E16
Bit Name
After Reset
0000 00XX2
Function
RW
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
(b1 - b0)
BSERR
Bit Stuffing Error
Detect Flag
0 : Not detected
1 : Detected
RW
ABT
Arbitration Lost
Detect Flag
0 : Not detected
1 : Detected
RW
IRF0
Interrupt Cause
Determination
Flag 0(2)
0 : The GiDR register (receive data register)
does not match the GiCMP0 register
1 : The GiDR register matches the GiCMP0
register
RW
IRF1
Interrupt Cause
Determination
Flag 1(2)
0 : The GiDR register (receive data register)
does not match the GiCMP1 register
1 : The GiDR register matches the GiCMP1
register
RW
IRF2
Interrupt Cause
Determination
Flag 2(2)
0 : The GiDR register (receive data register)
does not match the GiCMP2 register
1 : The GiDR register matches the GiCMP2
register
RW
IRF3
Interrupt Cause
Determination
Flag 3(2)
0 : The GiDR register (receive data register)
does not match the GiCMP3 register
1 : The GiDR register matches the GiCMP3
register
RW
NOTES:
1. The GiETC register is used in special communication mode or HDLC data processing mode. Do not
use in clock synchronous serial I/O mode or UART mode.
2. The SRTiR bit in the IIO4IR register is set to "1" if the BSERR bit, ABT bit or the IRF0 to IRF3 bits is
set to "0".
Group i Transmit Buffer (Receive Data) Register (i=0,1)(1)
b7
b0
Symbol
G0TB,G0DR
G1TB,G1DR
Address
00EA16
012A16
After Reset
Indeterminate
Indeterminate
Function
Set data to be transmitted.
Values written in these registers are written to the GiTB register.
Data read from these registers in HDLC data processing mode are
values written in the GiDR register
NOTES:
1. The GiTB register and the GiDR register share addresses.
Figure 21.37 G0IRF to G1IRF Registers and G0TB to G1TB Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 294 of 488
RW
WO
(RO)
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Group 0, 1 Communication Function)
Group i Data Compare Register j (i=0,1; j=0 to 3)
b7
b0
Symbol
Address
After Reset
G0CMP0 to G0CMP3
G1CMP0 to G1CMP3
00F016, 00F116, 00F216, 00F316
013016, 013116, 013216, 013316
Indeterminate
Indeterminate
Function
Setting Range
RW
0016 to FF16
RW
Data to be compared
NOTES:
1. Set the GiMSK0 register to use the GiCMP0 register.
Set the GiMSK1 register to use the GiCMP1 register.
Group i Data Mask Register j (i=0,1; j=0,1)
b7
b0
Symbol
Address
After Reset
G0MSK0,G0MSK1
G1MSK0,G1MSK1
00F416, 00F516
013416, 013516
Indeterminate
Indeterminate
Function
Masked data for received data
Set bits not being compared to "1"
Setting Range
RW
0016 to FF16
RW
Group i Transmit CRC Code Register (i=0,1)
b15
b8 b7
b0
Symbol
Address
After Reset
G0TCRC, G1TCRC
00FB16-00FA16, 013B16-013A16
000016
Function
RW
Result of the transmit CRC calculation(1,2)
RO
NOTES:
1. Calculation results are reset by setting the TE bit in the GiCR register to "0" (transmit disabled).
Default value is determined by setting the CRCV bit in the GiEMR register.
2. Transmit CRC calculation is performed with every bit of transmit data transmitted while the TCRCE
bit in the GiETC register is set to "1" (used).
Group i Receive CRC Code Register (i=0,1)
b15
b8 b7
b0
Symbol
Address
After Reset
G0RCRC, G1RCRC
00F916-00F816, 013916-013816
Indeterminate
Function
RW
Result of the receive CRC calculation(1, 2, 3)
RO
NOTES:
1. The calculation result is reset by setting the RCRCE bit in the GiERC register to "0" (not used). If the
the ACRC bit in the GiCMPj register is set to "1" (reset), the result is reset by matching the data in
the GiCMPj register with the received data.
2. The result is reset to the default value selected by the CRCV bit in the GiEMR register before
reception starts.
3. Receive CRC calculation occurs with every bit of transmit data transmitted while the RCRCE bit in
the GiERC register is set to "1" (used).
Figure 21.38 G0CMP0 to G0CMP3 Registers, G1CMP0 to G1CMP3 Registers, G0MSK0 to G0MSK1
Registers, G1MSK0 to G1MSK1 Registers, G0TCRC to G1TCRC Registers, and
G0RCRC to G1RCRC Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 295 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Group 0, 1 Communication Function)
21.4.1 Clock Synchronous Serial I/O Mode (Groups 0 and 1)
In clock synchronous serial I/O mode, data is transmitted and received with the transfer clock. When the
internal clock is selected as the transfer clock, the channel 0 and channel 3 waveform generation functions generate the internal clock. ISTxDi (i=0, 1), ISCLKi, and ISRxDi share pins with INPCi0 to INPCi2
and OUTCi0 to OUTCi2.
Table 21.16 lists specifications of clock synchronous serial I/O mode. Table 21.17 lists registers to be
used and their settings. Tables 21.18 to 21.21 list pin settings. Figure 21.39 shows an example of a
transmit and receive operation.
Table 21.16 Clock Synchronous Serial I/O Mode Specifications (Groups 0 and 1)
Item
Transfer Data Format
Transfer data :
Specification
Transfer Clock(1, 2)
When the CKDIR bit in the GiMR register (i=0, 1) is set to "0" (internal clock) :
8 bits long
fBTi
2(n+2)
n : setting value of the GiPO0 register, 000016 to FFFF16
• The GiPO0 register determines the bit rate and the transfer clock is generated in
phase-delayed waveform output mode by the channel 3 waveform generation function.
Transmit Start Condition
When the CKDIR bit is set to "1" (external clock) : input from the ISCLKi pin
Set registers associated with the waveform generation function, the GiMR register and the
GiERC register. Then set as written below after at least one transfer clock cycle:
• Set the TE bit in the GiCR register to "1" (transmit enable)
• Set the TI bit in the GiCR register to "0" (data in the GiTB register)
Receive Start Condition
Set registers associated with the waveform generation function, the GiMR register and
GiERC register. Then set as written below after at least one transfer clock cycle:
• Set the RE bit in the GiCR register to "1" (receive enable)
• Set the TE bit to "1" (transmit enable)
• Set the TI bit to "0" (data in the GiTB register)
Interrupt Request
• While transmitting, one of the following conditions can be selected to set the SIOiTR
bit to "1" (see Figure 10.14):
_
The IRS bit in the GiMR register is set to "0" (no data in the GiTB register) and data
is transferred to the transmit register from the GiTB register
_
The IRS bit is set to "1" (transmission completed) and data transfer from the
transmit register is completed
• While receiving, the following condition can be selected to set the SIOiRR bit to "1"
(see Figure 10.14):
Data is transferred from the receive register to the GiRB register
Error Detection
Overrun error(3)
This error occurs when the 8th bit of the next data is received before reading the GiRB register
Selectable Function
• LSB first/MSB first
Select either bit 0 or bit 7 to transmit/receive data
• ISTxDi and ISRxDi I/O polarity inverse
ISTxDi pin output level and ISRxDi pin input level are inversed
NOTES:
1. The transfer clock must be fBTi divided by six or more.
2. In clock synchronous serial I/O mode, set the RSHTE bit in the GiERC register (i=0, 1) to "1" (receive
shift operation enabled).
3. When an overrun error occurs, the GiRB register is indeterminate.
When the OPOL bit in the GiCR register is set to "0" (no ISTxDi output polarity inversed), the ISTxDi pin
outputs an "H" signal after selecting operation mode until transfer starts. When the OPOL bit is set to "1",
the ISTxDi pin outputs an "L" signal.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 296 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Group 0, 1 Communication Function)
Table 21.17 Registers to be Used and Settings
Register
GiBCR0
GiBCR1
GiPOCR0
GiPOCR1
GiPOCR3
Bit
BCK1 to BCK0
DIV4 to DIV0
IT
7 to 0
7 to 0
7 to 0
7 to 0
GiPO0
15 to 0
GiPO3
GiFS
GiFE
GiERC
GiMR
GiCR
GiTB
GiRB
Function
Set to "112"
Select divide ratio of count source
Set to "0"
Set to "0001 00102"
Set to "0000 01112"
Set to "0000 01112"
Set to "0000 00102" (1)
Set the bit rate
fBTi
2x(setting value + 2)
15 to 0
FSC3,1,0
IFE3,1,0
7 to 0
GMD1 to GMD0
CKDIR
STPS
UFORM
IRS
TI
TXEPT
RI
TE
RE
IPOL
OPOL
7 to 0
15 to 0
= transfer clock frequency(1)
Set to a value smaller than the GiPO0 register(1)
Set to "0"
Set to "1"
Set to "0010 00002"
Set to "012"
Select the internal clock or external clock
Set to "0"
Select either LSB first or MSB first
Select how the transmit interrupt is generated
Transmit buffer empty flag
Transmit register empty flag
Receive complete flag
Set to "1" to enable transmission and reception
Set to "1" to enable reception
Select ISRxD input polarity (usually set to "0")
Select ISTxD output polarity (usually set to "0")
Write data to be transmitted
Received data and error flag are stored
i = 0 to 1
NOTES:
1. The CKDIR bit in the GiMR register is set to "0" (internal clock)
Table 21.18 Pin Settings (1)
Port
Name
P73
P74
P75
P76
P77
Function
ISTxD1 output
ISCLK1 input
ISCLK1 output
ISRxD1 input
ISTxD0 output
ISCLK0 input
ISCLK0 output
Bit and Setting
PS1 Register PSL1 Register PSC Register PD7 Register
PS1_3 = 1
PSL1_3 = 0
PSC_3 = 1
PS1_4 = 0
PD7_4 = 0
PS1_4 = 1
PSL1_4 = 0
PSC_4 = 1
PS1_5 = 0
PD7_5 = 0
PS1_6 = 1
PSL1_6 = 0
PSC_6 = 0
PS1_7 = 0
PD7_7 = 0
PS1_7 = 1
-
Register(1)
IPS Register
IPS1 = 0
IPS1 = 0
IPS0 = 0
-
G1POCR0
G1POCR1
G0POCR0
G0POCR1
NOTES:
1. Set the MOD2 to MOD0 bits in the corresponding register to "1112" (output of the communication
function used).
Table 21.19 Pin Settings (2)
Port
Name
P80
Function
ISRxD0 input
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Bit and Setting
PS2 Register PD8 Register IPS register
PS2_0 = 0
PD8_0 = 0
IPS0 = 0
Page 297 of 488
Register
-
21. Intelligent I/O (Group 0, 1 Communication Function)
M32C/83 Group (M32C/83, M32C/83T)
Table 21. 20 Pin Settings (3)
Port
Name
P110
P111
P112
Bit and Setting
PS5 Register PD11 Register
ISTxD1 output PS5_0 = 1
ISCLK1 input
PS5_1 = 0
PD11_1 = 0
ISCLK1 output PS5_1 = 1
ISRxD1 input
PS5_2 = 0
PD11_2 = 0
Register(1)
Function
IPS Register
IPS1 = 1
IPS1 = 1
G1POCR0
G1POCR1
-
NOTES:
1. Set the MOD2 to MOD0 bits in the corresponding register to "1112" (output of the communication
function used).
Table 21. 21 Pin Settings (4)
Port
Name
P150
P151
P152
Bit and Setting
PS9 Register PD15 Register
ISTxD0 output PS9_0 = 1
ISCLK0 input
PS9_1 = 0
PD15_2 = 0
ISCLK0 output PS9_1 = 1
ISRxD0 input
PS9_2 = 0
PD15_2 = 0
Register(1)
Function
IPS Register
IPS0 = 1
IPS0 = 1
G0POCR0
G0POCR1
-
NOTES:
1. Set the MOD2 to MOD0 bits in the corresponding register to "1112" (output of the communication
function used).
Write to the GiTB register
The base timer is reset by the channel 0
waveform generation function
n+2
Base timer i
m
ISCLKi pin output
(transmit clock in the
channel 3 generation
function)
ISTxDi pin output
(data to be transmitted)
SIOiTR bit
when IRS=0
(no data in the
transmit buffer)
SIOiTR bit
when IRS=1
(transmission completed)
ISRxDi pin input
(received data)
Bit 0
Bit 1
Bit 2
Bit 6
Bit7
Write "0" by program
if setting to "0"
Write "0" by program
if setting to "0"
Bit 0
Bit 1
Bit 2
Bit 6
Bit 7
SIOiRR bit
Write "0" by program if setting to "0"
The above applies under the following conditions:
• The CKDIR bit in the GiMR register is set to "0" (internal clock)
• The UFORM bit in the GiMR register is be set to "0" (LSB first)
• The IPOL and OPOL bits in the GiCR register are set to "0" (no inverse)
Figure 21.39 Transmit and Receive Operation
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 298 of 488
n : Setting value of the GiPO0 register
m : Setting value of the GiPO3 register
i : 0,1
SIOiTR bit : Bit in the IIOjIR register (j = 1,3)
SIOiRR bit : Bit in the IIOkIR register (k = 0,2)
IRS bit
: Bit in the GiMR register
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Group 0, 1 Communication Function)
21.4.2 Clock Asynchronous Serial I/O Mode (UART) (Groups 0 and 1)
In clock asynchronous serial I/O mode (UART), data is transmitted at a desired bit rate and in a desired
transfer data format. Table 21.22 lists specifications of UART mode groups 0 and 1. Table 21.23 lists
registers to be used and their settings. Tables 21.24 to 21.27 list pin settings. Figure 21.40 shows an
example of transmit operation. Figure 21.41 shows an example of receive operation.
Table 21.22 UART Mode Specifications
Item
Specification
Transfer Data Format
Transfer Clock(1, 2)
• Character Bit (transfer data) :
• Start bit :
8 bits long
1 bit long
• Stop bit :
select length from 1 bit or 2 bits
When the CKDIR bit in the GiMR register (i=0, 1) is set to "0" (internal clock) :
fBTi
2(n+2)
n : setting value of the GiPO0 register, 000016 to FFFF16.
• The GiPO0 register determines the bit rate.
Transmit clock is generated in phase-delayed waveform output mode of the channel 3 waveform generation function.
Receive clock is generated with the channel 2 time measurement function.
Transmit Start Condition
Set the registers associated with the waveform generation function, the GiMR register and
GiERC register. Then, set as written below after at least one transfer clock cycle.
• Set the TE bit in the GiCR register to "1" (transmit enable)
• Set the TI bit in the GiCR register to "0" (data in the GiTB register)
Receive Start Condition
Set the registers associated with the waveform generation function, the GiMR register and
GiERC register. Then, set as written below after at least one transfer clock cycle.
• Set the RE bit in the GiCR register to "1" (receive enable)
• Detect the start bit
Interrupt Request
• While transmitting, one of the following conditions can be selected to set the SIOiTR
bit to "1" (see Figure 10.14):
_
The IRS bit in the GiMR register is set to "0" (no data in the GiTB register) and
data is transferred to the transmit register from the GiTB register.
_
The IRS bit is set to "1" (transmission completed) and data transfer from the
transmit register is completed
• While receiving, the following condition can be selected to set the SIOiRR bit to "1"
(see Figure 10.14) :
Data is transferred from the receive register to the GiRB register (data reception is
completed)
Error detection
• Overrun error(3)
This error occurs when the final stop bit of the next data is received before reading
the GiRB register
• Framing Error
This error occurs when the number of the stop bits set is not detected
Selectable function
• Stop bit length
The length of the stop bit is selected from 1 bit or 2 bits
• LSB first/MSB first
Select either bit 0 or bit 7 to transmit/receive data
NOTES:
1. The transfer clock must be fBTi divided by six or more.
2. Set the GiPOCR2 register and the GiTMCR2 register.
3. When an overrun error occurs, the GiRB register is indeterminate.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 299 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Group 0, 1 Communication Function)
Table 21.23 Registers to be Used and Settings
Register
GiBCR0
GiBCR1
GiPOCR0
GiPOCR2
GiPOCR3
GiTMCR2
Bit
BCK1 to BCK0
DIV4 to DIV0
IT
7 to 0
7 to 0
7 to 0
7 to 0
7 to 0
GiPO0
15 to 0
Set bit rate
fBTi
2 x (setting value + 2) = transfer clock frequency
GiPO3
GiFS
GiFE
GiMR
15 to 0
FSC3 to FSC0
IFE3 to IFE0
GMD1 to GMD0
CKDIR
STPS
UFORM
IRS
TI
TXEPT
RI
TE
RE
IPOL
OPOL
7 to 0
15 to 0
Set to a value smaller than the GiPO0 register
Set to "01002"
Set to "11012"
Set to "002"
Set to "0"
Select stop bit length
Select LBS first or MSB first
Select how the receive interrupt is generated
Transmit buffer empty flag
Transmit register empty flag
Receive complete flag
Set to "1" to enable transmission
Set to "1" to enable reception
Set to "1"
Set to "1"
Write data to be transmitted
Received data and error flag are stored
GiCR
GiTB
GiRB
Function
Set to "112"
Select divide ratio of count source
Set to "0"
Set to "0001 00102"
Set to "0000 01112"
Set to "0000 01102"
Set to "0000 00102"
Set to "0000 00102"
i = 0 to 1
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 300 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Group 0, 1 Communication Function)
Table 21.24 Pin Settings in UART Mode (1)
Port
Name
P73
P75
P76
Function
ISTxD1 output
ISRxD1 input
ISTxD0 output
Bit and Setting
PS1 Register PSL1 Register PSC Register PD7 Register
PS1_3 = 1
PSL1_3 = 0
PSC_3 = 1
PS1_5 = 0
PD7_5 = 0
PS1_6 = 1
PSL1_6 = 0
PSC_6 = 0
-
Register(1)
IPS Register
G1POCR0
IPS1 = 0
G0POCR0
NOTES:
1. Set the MOD2 to MOD0 bits in the corresponding register to "1112" (output of the communication
function used).
Table 21.25 Pin Settings (2)
Port
Name
P80
Function
ISRxD0 input
Bit and Setting
PS2 Register PSL2 Register PD8 Register IPS Register
PS2_0 = 0
PD8_0 = 0
IPS0 = 0
Register
-
Table 21.26 Pin Settings (3)
Port
Name
P110
P112
Function
ISTxD1 output
ISRxD1 input
Bit and Setting
Register(1)
PS5 Register PD11 Register IPS Register
PS5_0 = 1
G1POCR0
PS5_2 = 0
PD11_2 = 0
IPS1 = 1
-
NOTES:
1. Set the MOD2 to MOD0 bits in the corresponding register to "1112" (output of the communication
function used).
Table 21.27 Pin Settings (4)
Port
Name
P150
P152
Function
ISTxD0 output
ISRxD0 input
Bit and Setting
Register(1)
PS9 Register PD15 Register IPS Register
PS9_0 = 1
G0POCR0
PD15_2 = 0
IPS0 = 1
-
NOTES:
1. Set the MOD2 to MOD0 bits in the corresponding register to "1112" (output of the communication
function used).
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 301 of 488
21. Intelligent I/O (Group 0, 1 Communication Function)
M32C/83 Group (M32C/83, M32C/83T)
Tc
Transfer clock
"H"
ISTxDi pin
ST D0 D1 D2 D3 D4 D5 D6 D7 SP
ST D0 D1 D2 D3 D4 D5 D6 D7 SP
"L"
Set data in the GiTB register
Set data in the GiTB register
"1"
TI bit
"0"
"1"
TXEPT bit
"0"
"1"
SIOiTR bit
"0"
Write "0" by program
if setting to "0"
The above applies under the following conditions:
• The STPS bit in the GiMR register is set to "0" (1 stop bit)
• The UFORM bit in the GiMR register is set to "0" (LSB first)
• The INV bits in the GiPOCR0 to GiPOCR7 registers are set to "0" (no inverse)
• The IRS bit in the GiMR register is set to "0" (no data in the transmit buffer)
i : 0,1
TI, TXEPT bit : Bits in the GiCR register
SIOiTR bit
: Bit in the IIOjIR register (j = 1,3)
Figure 21.40 Transmit Operation
Transfer clock
ISRxDi pin
"H"
ST D0 D1 D2 D3 D4 D5 D6 D7 SP
ST D0 D1 D2 D3 D4 D5 D6 D7 SP
"L"
Read the GiDRB register
"1"
RI bit
"0"
"1"
SIOiRR bit
"0"
Write "0" by program
if setting to "0"
The above applies under the following conditions:
• The STPS bit in the GiMR register is set to "0" (1 stop bit)
• The UFORM bit in the GiMR register is set to "0" (LSB first)
• The INV bits in the GiPOCR0 to GiPOCR7 registers are set to "0" (no inverse)
Figure 21.41 Receive Operation
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 302 of 488
i : 0,1
SIOiRR bit : Bit in the IIOkIR register (k = 0,2)
RI bit
: Bit in the GiCR register
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Group 0, 1 Communication Function)
21.4.3 HDLC Data Processing Mode (Group 0 and 1)
In HDLC data processing mode, bit stuffing, flag detection, abort detection and CRC calculation are
available for HDLC control. The channel 0 and 1 are used to generate the transfer clock. No pins are
used.
To convert data, data to be transmitted is written to the GiTB register (i=0,1) and the data conversion
result is restored after data conversion. If any data are in the GiTO register after data conversion, the
conversion is terminated. If no data is in the GiTO register, bit stuffing processing is executed regardless
of there being no data in the transmit output buffer. A CRC value is calculated every time one bit is
converted. If no data is in the GiRI register, received data conversion is terminated.
Table 21.28 list specifications of the HDLC data processing mode. Table 21.29 lists registers to be used
and their settings.
Table 21.28 HDLC Processing Mode Specifications
Item
Specification
Input Data Format
8-bit data fixed, bit alignment is optional
Output Data Format
8-bit data fixed
Transfer Clock
When the CKDIR bit in the GiMR register (i=0, 1) is set to "0" (internal clock) :
fBTi
n+2
n : setting value of the GiPO0 register 000016 to FFFF16
• The GiPO0 register determines bit rate.
The transfer clock is generated in phase-delayed waveform output mode of the
channel 1 waveform generation function.
When the RSHTE bit in the GiERC register is set to "1" (reception shift operation
enabled), the transfer clock is generated in the receiver
I/O Method
• While transmitting,
value set in the GiTB register is converted in HDLC data processing mode and
transferred to the GiTO register
• While receiving,
value set in the GiRI register is converted in HDLC data processing mode and
transferred to the GiRB register. The value in the GiRI register is also transferred to
the GiDR register (received data register).
Bit Stuffing
While transmitting, "0" following five consecutive "1" is inserted.
While receiving, "0" following five consecutive "1" is deleted.
Flag Detection
Write the flag data "7E16" to the GiCMP3 register to use the special communication
interrupt (the SRTiR bit in the IIO4IR register)
Abort Detection
Write the masked data "0116" to the GiMSKk(k=0, 1) register
CRC
The CRC1 to CRC0 bits are set to "112" (X16+X12+X5+1)
The CRCV bit is set to "1" (set to "FFFF16")
• While transmitting, CRC calculation result is stored into the GiTCRC register.
The TCRCE bit in the GiETC register is set to "1" (transmit CRC used).
The CRC calculation result is reset when the TE bit in the GiCR register is set to "0"
(transmit disabled)(1).
• While receiving, CRC calculation result is stored into the GiRCRC register.
The RCRCE bit in the GiERC register is set to "1" (receive CRC used).
The CRC calculation result is reset by comparing the flag data "7E16" and matching
the result with the value in the GiCMP3 register. The ACRC bit in the GiEMR register is set to "1" (CRC reset)(2)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 303 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Group 0, 1 Communication Function)
Table 21.28 HDLC Processing Mode Specifications (Continued)
Item
Data Processing
Start Conditions
Specification
The following conditions are required to start transmit data processing:
• The TE bit in the GiCR register is set to "1" (transmit enable)
• Data is written to the GiTB register
The following conditions are required to start receive data processing:
• The RE bit in the GiCR register is set to "1" (receive enable)
• Data is written to the GiRI register
Interrupt Request(3)
During transmit data processing,
(1) One of the following conditions can be selected to set the GiTOR bit in the interrupt
request register to "1" (interrupt request) (see Figure 10.14)
_
When the IRS bit in the GiMR register is set to "0" (no data in the GiTB register)
and data is transferred from the GiTB register to the transmit register (transmit start)
_
When the IRS bit is set to "1" (transmission completed) and data transfer from
the transmit register to the GiTO register is completed
(2) When data, which is already converted to HDLC data, is transferred from the
receive register of the GiTO register to the transmit buffer, the GiTOR bit is set
to "1"
During received data processing,
(1) When data is transferred from the GiRI register to the GiRB register (reception
completed), the GiRIR bit is set to "1" (See Figure 10.14)
(2) When received data is transferred from the receive buffer of the GiRI register to
the receive register, the GiRIR bit is set to "1"
(3) When the GiTB register is compared to the GiCMPj register (j=0 to 3), the SRTiR
bit is set to "1"
NOTES:
1. Set the CRCV bit and ACRC bit in the GiEMR register to "1".
2. The CRC calculation circuit is reset after the GiRCRC register stores CRC data.
3. See Figure 10.14 for details on the GiTOR bit, GiRIR bit and SRTiR bit.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 304 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Group 0, 1 Communication Function)
Table 21.29 Registers to be Used and Settings
Register
GiBCR0
GiBCR1
GiPOCR0
GiPOCR1
GiPO0
GiPO1
GiFS
GiFE
GiMR
GiEMR
GiCR
GiETC
GiERC
GiIRF
GiCMP0,
GiCMP1
GiCMP2
GiCMP3
GiMSK0,
GiMSK1
GiTCRC
GiRCRC
GiTO
GiRI
GiRB
GiTB
Bit
BCK1 to BCK0
DIV4 to DIV0
IT
7 to 0
7 to 0
7 to 0
15 to 0
15 to 0
Function
Select count source
Select divide ratio of count source
Select the base timer interrupt
Set to "0001 00102"
Set to "0000 00002"
Set to "0000 00002"
Set bit rate
Set the timing of the rising edge of the transfer clock.
Timing of the falling edge (high-level signal ("H") width of the transfer clock) is
fixed.
Setting value of GiPO1 ≤ Setting value of GiPO0 .
FSC1 to FSC0
Set to "002"
IFE1 to IFE0
Set to "112"
GMD1 to GMD0 Set to "112"
CKDIR
Set to "0"
UFORM
Set to "0"
IRS
Select how the transmit interrupt is generated
7 to 0
Set to "1111 01102"
TI
Transmit buffer empty flag
TXEPT
Transmit register empty flag
RI
Receive complete flag
TE
Transmit enable bit
RE
Receive enable bit
SOF
Set to "0"
TCRCE
Select whether the transmit CRC is used or not
ABTE
Set to "0"
TBSF0, TBSF1
Transmit bit stuffing
CMP2E to CMP0E Select whether received data is compared or not
CMP3E
Set to "1"
RCRCE
Select whether receive CRC is used or not
RSHTE
Set to "1" to use it in the receiver
RBSF0, RBSF1 Receive bit stuffing
BSERR, ABT
Set to "0"
IRF3 to IRF0
Select how an interrupt is generated
7 to 0
Write "FE16" to abort processing
7 to 0
7 to 0
7 to 0
Data to be compared
Write "7E16"
Write "0116" to abort processing
15 to 0
15 to 0
7 to 0
7 to 0
7 to 0
7 to 0
Transmit CRC calculation result can be read
Receive CRC calculation result can be read
Data, which is output from a transmit data generation circuit, can be read
Set data input to a receive data generation circuit
Received data is stored
For transmission : write data to be transmitted
For reception
: received data for comparison is stored
i = 0,1
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 305 of 488
21. Intelligent I/O (Group 0, 1 Communication Function)
M32C/83 Group (M32C/83, M32C/83T)
21.5 Group 2 Communication Function
The communication function is available when two 8-bit shift registers are used with the waveform generation function.
In the intelligent I/O group 2, the variable clock synchronous serial I/O or IEBus(1) communication function
is available. Figures 21.42 to 21.45 show registers associated with the communication function.
NOTES:
1. IEBus is a trademark of NEC Electronics Corporation.
Group 2 SI/O Transmit Buffer Register
b15
b8 b7
b0
Symbol
Address
016D16-016C16
G2TB
Bit
Symbol
(b7 - b0)
After Reset
Indeterminate
Bit Name
Function
Transmit Buffer
Data to be transmitted
RW
RO
b10 b9 b8
SZ0
SZ1
SZ2
0
0
0
Transfer Bit Length 0
1
Select Bit
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
: 8 bits long
: 1 bits long
: 2 bits long
: 3 bits long
: 4 bits long
: 5 bits long
: 6 bits long
: 7 bits long
RW
RW
RW
Nothing is assigned. When write, set to "0".
(b12 - b11) When read, its content is indeterminate.
A
PC
P
ACK Function
Select Bit
0 : Adds no ACK bit
1 : Adds the ACK bit after last transmit bit
RW
Parity Calculation
Continuing Bit(1)
0 : Adds the parity bit after a data to be
transmitted
1 : Carries over a parity to a data to be
transmitted
RW
Parity Function
Select Bit
0 : No parity
1 : Parity (even parity only)
RW
NOTES:
1. Set the P bit to "0" before setting the PC bit to "1"
Group 2 SI/O Receive Buffer Register
b15
b8 b7
b0
Symbol
G2RB
Bit
Symbol
Address
016F16 - 016E16
After Reset
Indeterminate
Bit Name
(b7 - b0) Receive Buffer
Function
Received data
RW
RO
Nothing is assigned. When write, set to "0".
(b11 - b8) When read, its content is indeterminate.
OER
Overrun Error Flag(1)
0 : No overrun error
1 : Overrun error found
Nothing is assigned. When write, set to "0".
(b15 - b13) When read, its content is indeterminate.
NOTES:
1. The OER bit is set to "0" when the GMD1 to GMD0 bits in the G2MR register are set to "002"
(communication unit reset) or the RE bit in the G2CR register is set to "0" (receive disable).
Figure 21.42 G2TB and G2RB Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 306 of 488
RO
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Group 0, 1 Communication Function)
Group 2 SI/O Communication Mode Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
016A16
G2MR
Bit
Symbol
After Reset
00XX X0002
Bit Name
Function
RW
b1b0
GMD0
0 0 : Communication unit is reset
(The OER bit is set to "0")(1)
0 1 : Clock synchronous serial I/O
mode(2)
1 0 : IE mode(2)
1 1 : Do not set to this value
Communication Mode
Select Bit
GMD1
CKDIR
Internal/External Clock
Select Bit
0 : Internal clock
1 : External clock
RW
RW
RW
Nothing is assigned. When write, set to "0".
(b5 - b3) When read, its content is indeterminate.
UFORM
IRS
Transfer Format
Select Bit
0 : LSB first
1 : MSB first
RW
Transmit Interrupt
Cause Select Bit
0 : No data is in the transmit buffer
1 : Transmission is completed
RW
NOTES:
1. Run the base timer clock for one or more cycles after the GMD1 to GMD0 bits are set to "002"
(communication unit reset).
2. Set the GMD1 to GMD0 bits to "012" (clock synchronous serial I/O mode) or "102" (IE mode) while
the base timer clock is stopped.
Group 2 SI/O Communication Control Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
G2CR
Bit
Symbol
TE
Address
016B16
Bit Name
Transmit Enable Bit
Transmit Register
TXEPT
Empty Flag
TI
After Reset
0000 X0002
Transmit Buffer
Empty Flag
Function
RW
0 : Transmit disabled
1 : Transmit enabled
RW
0 : Data is in the transmit register
(during transmission)
1 : No data is in the transmit register
(transmission is completed)
RO
0 : Data is in the G2TB register
1 : No data is in the G2TB register
RO
(b3)
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
RE
Receive Enable Bit1
0 : Receive disabled
1 : Receive enabled
RW
RI
Receive Complete
Flag
0 : No data is in the G2RB register
1 : Data is in the G2RB register
RO
OPOL
ISTxD Output Polarity 0 : No inverse
Switch Bit
1 : Inverse
RW
IPOL
ISRxD Input Polarity 0 : No inverse
Switch Bit(1)
1 : Inverse
RW
NOTES:
1. The group 2 base timer may be reset when rewriting the RE or IPOL bit. To avoid resetting, set the
RST2 bit in the G2BCR1 register to "0" (no base timer reset by a reset request from the
communication function).
Figure 21.43 G2MR and G2CR Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 307 of 488
21. Intelligent I/O (Group 0, 1 Communication Function)
M32C/83 Group (M32C/83, M32C/83T)
Group 2 IEBus Control Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
After Reset
IECR
017216
00XX X0002
Bit
Symbol
IEB
IETS
IEBBS
Bit Name
Function
RW
IEBus Enable Bit(1)
0 : Disables IEBus(2)
1 : Enables IEBus
RW
IEBus Transmit Start
Request Bit
0 : Transmission is completed
1 : Transmission is started
RW
IEBus Busy Flag
0 : Idle state
RO
1 : Busy state (start condition is detected)
Nothing is assigned. When write, set to "0".
(b5 - b3) When read, its content is indeterminate.
DF
Digital Filter
Select Bit
0 : No digital filter
1 : Digital filter
RW
IEM
IEBus Mode
Select Bit
0 : Mode 1
1 : Mode 2
RW
NOTES:
1. Set the IEB bit while the base timer clock is stopped.
2. After the IEB bit is set to "0", keep "0" for at least 1 fBT2 cycle. Set the BCK1 to BCK0 bits in the
G2BCR0 register to "002" (clock stop) when setting the IEB bit to "1".
Group 2 IEBus Address Register
b15
b8 b7
Symbol
IEAR
b0
Address
017116 - 017016
Function
RW
Address data
RW
Address data
RW
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Figure 21.44 IECR and IEAR Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
After Reset
Indeterminate
Page 308 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Group 0, 1 Communication Function)
Group 2 IEBus Transmit Interrupt Cause Determination Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
After Reset
IETIF
017316
XXX0 00002
Bit
Symbol
Bit Name
Function
RW
IETNF
Normal Complete
Flag(1)
0 : Transmission is completed in error
1 : Transmission is completed as
RW
expected
IEACK
ACK Error Flag(1)
0 : No error found
1 : Error found
RW
IETMB
Maximum Transfer Byte 0 : No error found
1 : Error found
Error Flag(1)
RW
Timing Error Flag(1)
0 : No error found
1 : Error found
RW
Arbitration Lost Flag(1)
0 : No error found
1 : Error found
RW
IETT
IEABL
(b7 - b5)
Nothing is assigned. When write, set to "0".
When read, its contents is indeterminate.
NOTES:
1. This bit can be set to "0" by program, but cannot be set to "1". Set to "0" by setting the IEB bit in
the IECR register to "0" (IEBus disabled to use).
Group 2 IEBus Receive Interrupt Cause Determination Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
017416
IERIF
Bit
Symbol
Bit Name
After Reset
XXX0 00002
Function
IERNF
Normal Completed
Flag(1)
0 : Transmission is completed in error
RW
1 : Transmission is completed as
expected
IEPAR
Parity Error Flag(1)
0 : No error found
1 : Error found
RW
IERMB
Max. Transfer Byte
Error Flag(1)
0 : No error found
1 : Error found
RW
IERT
Timing Error Flag(1)
0 : No error found
1 : Error found
RW
Other Cause Receive
Completed Flag(1)
0 : No error found
1 : Error found
RW
IERETC
Nothing is assigned. When write, set to "0".
When read, its contents is indeterminate.
(b7 - b5)
NOTES:
1. This bit can be set to "0" by program, but not to "1". Set to "0" by setting the IEB bit in the IECR
register to "0" (IEBus disabled to use).
Figure 21.45 IETIF and IERIF Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
RW
Page 309 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Group 2 Communication Function)
21.5.1 Variable Clock Synchronous Serial I/O Mode (Group 2)
In variable clock synchronous serial I/O mode, data is transmitted and received using the transfer clock.
The length of data transferred is selected from 1 to 8 bits. Table 21.30 lists specifications of the group 2
variable clock synchronous serial I/O mode. Table 21.31 lists registers to be used and their settings.
Tables 21.32 to 21.35 lists pin settings. Figure 21.46 shows an example of a transmit and receive
operation.
Table 21.30 Variable Clock Synchronous Serial I/O Mode Specifications (Group 2)
Item
Specification
Transfer Data Format
• Transfer data length : 1 to 8 bits
Transfer Clock(1)
• When the CKDIR bit in the G2MR register is set to "0" (internal clock) :
fBT2
2(n+2)
n : setting value of the G2PO0 register 000016 to FFFF16
The G2PO0 register determines bit rate and the transfer clock is generated in
phase-delayed waveform output mode of the channel 2 waveform generation function.
• When the CKDIR bit is set to "1" (external clock) : input from the ISCLK2 pin(2)
Transmit Start Condition
• To start transmitting, the following conditions are required :
- Set the TE bit in the G2CR register to "1" (transmit enable)
- Write data to the G2TB register
Receive Start Condition
• To start receiving, the following conditions are required :
- Set the RE bit in the G2CR register to "1" (receive enable)
- Set the TE bit in the G2CR register to "1" (transmit enable)
- Write data to the G2TB register
Interrupt Request
• While transmitting, one of the following conditions can be selected to set the
SIO2TR bit in the IIO6IR register to "1" (see Figure 10.14):
- The IRS bit in the G2MR register is set to "0" (no data in the G2TB register):
when data is transferred from the G2TB register to the transmit register.
- The IRS bit is set to "1" (reception completed):
when data transfer from the transmit register is completed
• While receiving, the following condition can be selected to set the SIO2RR bit in the
IIO5IR register to "1" (interrupt request) (see Figure 10.14):
when data is transferred from the receive register to the G2RB register (data reception is completed)
Error Detection
Overrun error(3)
This error occurs when receiving the j bit (j=1 to 8) of the next data (transfer data
length: j bits) before reading the G2RB register
Selectable Function
• LSB first/MSB first
Select either bit 0 or bit 7 to transmit/receive data
• ISTxD2 and ISRxD2 I/O polarity inverse
ISTxD2 pin output level and ISRxD2 pin input level are inversed
• Data transfer bit length
Select from 1 to 8 bits
NOTES:
1. The transfer clock must be fBT2 divided by six or more when both transfer clock and transfer data are
transmitted. Under conditions other than this, the transfer clock must be fBT2 divided by 20 or more.
2. Transfer clocks must be fBT2 divided by 20 or more.
3. When an overrun error occurs, the G2RB register is indeterminate.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 310 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Group 2 Communication Function)
Table 21.31 Register to be Used and Settings
Register
G2BCR0
G2BCR1
G2POCR0
G2POCR1
G2BCR2
G2PO0
G2PO2
G2FE
G2MR
G2CR
G2TB
G2RB
Bit
BCK1 to BCK0
DIV4 to DIV0
IT
7 to 0
7 to 0
7 to 0
7 to 0
15 to 0
Function
Set to "112"
Select divide ratio of count source
Set to "0"
Set to "0001 00102"
Set to "0000 01112"
Set to "0000 01112"
Set to "0000 00102"
Set bit rate
fBT2
2 x (setting value + 2) = transfer clock frequency
15 to 0
IFE2 to IFE0
GMD1 to GMD0
CKDIR
UFORM
IRS
TE
TXEPT
TI
RE
RI
OPOL
IPOL
15 to 0
15 to 0
Set to a value smaller than the G2PO0 register
Set to "1112"
Set to "012"
Select internal or external clock
Select either LSB first or MSB first
Select how the transmit interrupt is generated
When transmission is enabled, set to "1"
Transmit register empty flag
Transmit buffer empty flag
When reception is enabled, set to "1"
Receive complete flag
ISTxD2 output polarity inverse (usually set to "0")
ISRxD2 input polarity inverse (usually set to "0")
Write transfer bit length and transmit data
Received data and error flag are stored
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 311 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Group 2 Communication Function)
Table 21.32 Pin Settings (1)
Port
Name
P70(1)
P71
Bit and Setting
Register(2)
PS1 Register PSL1 Register PSC Register PD7 Register IPS Register
ISTxD2 output PS1_0 = 1
PSL1_0 = 0 PSC_0 = 1
G2POCR0
ISRxD2 input PS1_1 = 0
PD7_1 = 0
IPS5 to 4 = 002 Function
NOTES:
1. P70 is a port for the N-channel open drain output.
2. Set the MOD2 to MOD0 bits in the corresponding register to "1112" (output of the communication
function is used).
Table 21.33 Pin Settings (2)
Port
Function
Bit and Setting
Register(2)
(1)
(1)
Name
PS3 Register PSL3 Register PD9 Register IPS Register
P91 ISRxD2 input
PS3_1=0
PD9_1=0
IPS5 to 4=012 P92 ISTxD2 output PS3_2=1
PSL3_2=1
G2POCR0
NOTES:
1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write
enable). Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1"
and the instruction to set the PD9 and PS3 registers.
2. Set the MOD2 to MOD0 bits in the corresponding register to "1112" (output of the communication
function used).
Table 21.34 Pin Settings (3)
Port
Name
P64
Bit and Setting
Register(1)
PS0 Register PSL0 Register PD6 Register IPS Register
ISCLK2 input
PS0_4 = 0
PD6_4 = 0
IPS6 = 0
ISCLK2 output PS0_4 = 1
PSL0_4 = 1
G2POCR1
Function
NOTES:
1. Set the MOD2 to MOD0 bits in the corresponding register to "1112" (output of the communication
function used).
Table 21.35 Pin Settings (4)
Port
Name
P134
P135
P136
Function
Bit and Setting
PS7 Register PD13 Register
ISTxD2 output PS7_4 = 1
ISRxD2 input
PS7_5 = 0
PD13_5 = 0
ISCLK2 input
PS7_6 = 0
PD13_6 = 0
ISCLK2 output PS7_6 = 1
-
Register(1)
IPS Register
G2POCR0
IPS5 to 4 = 102 IPS6 = 1
G2POCR1
NOTES:
1. Set the MOD2 to MOD0 bits in the corresponding register to "1112" (output of the communication
function used).
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 312 of 488
21. Intelligent I/O (Group 2 Communication Function)
M32C/83 Group (M32C/83, M32C/83T)
The base timer is reset by
the channel 0 waveform
generation function
k+2
Base timer 2
t
Set data in the
transmit register
(8-bit data)
Set data in the
transmit register
(4-bit data)
Transmit/Receive clock
by the channel 2
waveform generation
First write to
transmit buffer
bit 0
bit 7
bit 6
bit 2
bit 1
Second write to
transmit buffer
Received data
bit 8
bit 0
bit 1
bit 2
bit 5
bit 6
bit 7
bit 10
bit 9
bit 8
Transfer to the receive register
bit 9
bit 11
bit 10
bit 11
Transfer to the receive register
t : Value set in the channel 2 waveform generation register
Value set in the channel 3 waveform generation register
Figure 21.46 Transmit and Receive Operation
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 313 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Group 2 Communication Function)
21.5.2 IEBus Mode (Group 2)
Table 21.36 lists specifications of IEBus mode. Table 21.37 lists registers to be used and settings.
Tables 21.38 to 21.40 lists pin settings.
Table 21.36 IEBus Mode Specifications
Item
Specification
Transfer Data Format
• Transfer data length: 1 to 8 bits
Transfer Clock
• When the CKDIR bit in the G2MR register is set to "0" (internal clock) :
fBT2
2(n+2)
n : setting value of the G2PO0 register, 000016 to FFFF16.
The G2PO0 register determines bit rate and the transfer clock is generated
in phase-delayed waveform output mode of the channel 2 waveform generation
function.
The G2PO2 register = (n+2)/2(1)
• When the CKDIR bit is set to "1" (external clock) : input from the ISCLK2 pin(2)
Transmit Start Condition
To start transmitting, the following conditions are required :
• Set the TE bit in the G2CR register to "1" (transmit enable)
• Write data to G2TB register
Receive Start Condition
To start receiving, the following requirements must be met:
• Set the RE bit in the G2CR register to "1" (receive enable)
• Set the TE bit in the G2CR register to "1" (transmit enable)
• Write data to the G2TB register
Interrupt Request
• While transmitting, the following conditions can be selected to set the SIO2TR bit in
the IIO6IR register to "1" (see Figure 10.14):
- The IRS bit in the G2MR register is set to "0" (no data in the G2TB register):
when data is transferred to the transmit register from the G2TB register (transmission started)
- The IRS bit is set to "1" (transmission completed):
when data transfer from the transmit register to the G2TO register is completed
• While receiving, the following condition can be selected to set the SIO2RR bit in the
IIO5IR register to "1" (see Figure 10.14):
when data is transferred from receive register to the G2RB register (data reception
is completed)
Error Detection
Overrun error(3)
This error occurs when receiving the j bit (j=1 to 8) of the next data (transfer data
length: j bits) before reading the G2RB register
Selectable Function
• LSB first/MSB first select
Select either bit 0 or bit 7 to transmit/receive data
• ISTxD2 and ISRxD2 I/O polarity inverse
ISTxD2 pin output and ISRxD2 pin input levels are inversed
• Data transfer bit length
Select from 1 to 8 bits
NOTES:
1. The transfer clock must be fBT2 divided by six or more when both transfer clock and transfer data are
transmitted. Under conditions other than this, the transfer clock must be fBT2 divided by 20 or more.
2. Transfer clock must be input fBT2 divided by 20 or more.
3. When an overrun error occurs, the G2RB register is indeterminate.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 314 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Group 2 Communication Function)
Table 21.37 Registers to be Used and Settings
Register
G2BCR0
G2BCR1
G2POCR0
to G2POCR7
G2PO0 to
G2PO7
G2FE
G2MR
G2CR
IECR
IEAR
IETIF
IERIF
G2RB
G2TB
Bit
BCK1 to BCK0
DIV4 to DIV0
IT
7 to 0
MOD2 to MOD0
PRT
IVL
RLD
RTP
INV
15 to 0
Function
Set to "112"
Select divide ratio of count source
Set to "0"
Set to "000100102"
Set to "1112"
Set to "0"
Set to "0"
Set to "0"
Set to "0"
Set to "0"
Set compared data for waveform generation
7 to 0
GMD1 to GMD0
CKDIR
UFORM
IRS
TI
TXEPT
RI
TE
RE
IPOL
OPOL
IEB
IETS
IEBBS
DF
IEM
11 to 0
IETNF
IEACK
IETMB
IETT
IEABL
IERNF
IEPAR
IERMB
IERT
IERETC
7 to 0
OER
7 to 0
Set bit of corresponding channel to "1"
Select serial I/O mode
Select internal clock or external clock
Select either LSB first or MSB first
Select how the transmit interrupt is generated
Transmit buffer empty flag
Transmit register empty flag
Receive complete flag
When transmission is enabled, set to "1"
When reception is enabled, set to "1"
ISRxD2 input polarity inverse (usually set to "0")
ISTxD2 output polarity inverse (usually set to "0")
Set to "1"
When transmission starts, set to "1"
Select IEBus busy flag
Select whether the digital filter is available or not
Select mode
Set address data
Normal complete flag when transmitting
ACK error flag when transmitting
Maximum transfer byte error flag when transmitting
Timing error flag when transmitting
Arbitration lost flag when transmitting
Normal complete flag when receiving
Parity error flag when receiving
Maximum transfer byte error flag when receiving
Timing error flag when receiving
Other cause receive completed flag when receiving
Received data and error flag are stored
Overrun error flag
Write transfer bit length and data to be transmitted
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 315 of 488
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Group 2 Communication Function)
Table 21.38 Pin Settings (1)
Port
Name
P70(1)
P71
Bit and Setting
Register(2)
PS1 Register PSL1 Register PSC Register PD7 Register IPS Register
IEOUT output PS1_0 = 1
PSL1_0 = 0
PSC_0 = 1
G2POCR0
IEIN input
PS1_1 = 0
PD7_1 = 0
IPS5 to 4 = 002 Function
NOTES:
1. P70 is a port for the N-channel open drain output.
2. Set the MOD2 to MOD0 bits in the G2POCR0 register to "1112".
Table 21.39 Pin Settings (2)
Port
Function
Bit and Setting
Register(1)
(2)
(2)
Name
PS3 Register
PSL3 Register PD9 Register
IPS Register
P91 IEIN input
PS3_1 = 0
IPS5 to 4 = 012 P92 IEOUT output PS3_2 = 1
PSL3_2 = 1
PD9_2 = 0
G2POCR0
NOTES:
1. Set the MOD2 to MOD0 bits in the G2POCR0 register to "1112".
2. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write
enable). Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1"
and the instruction to set the PD9 and PS3 registers.
´
Table 21.40 Pin Settings (3)
Port
Name
P134
P135
Function
IEOUT output
IEIN input
Bit and Setting
Register(1)
PS7 Register PSL7 Register IPS Register
PS7_4 = 1
G2POCR0
PS7_5 = 0
PD13_5 = 0
IPS5 to 4 = 102 -
NOTES:
1. Set the MOD2 to MOD0 bits in the G2POCR0 register to "1112".
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 316 of 488
21. Intelligent I/O (Group 3 Communication Function)
M32C/83 Group (M32C/83, M32C/83T)
21.6 Group 3 Communication Function
The communication function is available when two 16-bit shift registers are used with the waveform generation function.
In the intelligent I/O group 3, 8-bit or 16-bit synchronous communication function is available. Figures
21.47 to 21.49 show registers associated with the communication function.
Group 3 SI/O Transmit Buffer Register
b15
b8
b7
b0
Symbol
G3TB
Address
017D16 - 017C16
Bit Name
After Reset
Indeterminate
Function
RW
Data to be transmitted (8 low-order bits)
WO
Transmit Buffer
Data to be transmitted (8 high-order bits) WO
Group 3 SI/O Receive Buffer Register
b15
b8
b7
b0
Symbol
G3RB
Address
017F16 - 017E16
Bit Name
After Reset
Indeterminate
Function
RW
Received data (8 low-order bits)
RO
Received data (8 high-order bits)
RO
Receive Buffer
Figure 21.47 G3TB Register and G3RB Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 317 of 488
21. Intelligent I/O (Group 3 Communication Function)
M32C/83 Group (M32C/83, M32C/83T)
Group 3 SI/O Communication Mode Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
G3MR
Bit
Symbol
Address
017A16
After Reset
00XX 00002
Bit Name
Function
RW
b1 b0
Communication Mode
Select Bit
0 0 : Communication unit is reset
RW
(The ROER bit is set to "0")
0 1 : Clock synchronous serial I/O mode
1 0 : Do not set to this value
RW
1 1 : Do not set to this value
Internal/External Clock
Select Bit
0 : Internal clock
1 : External clock
RW
Transfer Data Length
Select Bit
0 : 16 bits long
1 : 8 bits long
RW
GMD0
GMD1
CKDIR
TLD
Nothing is assigned. When write, set to "0".
(b5 - b4) When read, its content is indeterminate.
UFORM
IRS
Transfer Format
Select Bit
0 : LSB first
1 : MSB first
RW
Transmit Interrupt
Cause Select Bit
0 : No data is in the transmit buffer
1 : Transmission is completed
RW
Group 3 SI/O Communication Control Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
G3CR
Bit
Symbol
TE
Address
017B16
Bit Name
Transmit Enable Bit
Transmit Register
TXEPT
Empty Flag
TI
Transmit Buffer
Empty Flag
Function
RW
0 : Transmit disable
1 : Transmit enable
RW
0 : Data is in transmit register
(during transmission)
1 : No data is in the transmit register
(transmission is completed)
RO
0 : Data is in the G3TB register
1 : No data is in the G3TB register
RO
(b3)
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
RE
Receive Enable Bit
0 : Receive disabled
1 : Receive enabled
RW
RI
Receive Complete
Flag
0 : No data is in the G3RB register
1 : Data is in the G3RB register
RO
OPOL
ISTxD Output Polarity 0 : No inverse
Switch Bit
1 : Inverse
RW
IPOL
ISRxD Input Polarity 0 : No inverse
Switch Bit
1 : Inverse
RW
Figure 21.48 G3MR Register and G3CR Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
After Reset
0000 X0002
Page 318 of 488
21. Intelligent I/O (Group 3 Communication Function)
M32C/83 Group (M32C/83, M32C/83T)
Group 3 SI/O Communication Flag Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
G3FLG
Bit
Symbol
ROER
Address
01AD16
Bit Name
Receive Overrun
Error Flag(1)
After Reset
XXXX XXX02
Function
0 : No error found
1 : Error found
Nothing is assigned. When write, set to "0".
(b7 - b1) When read, its content is indeterminate.
NOTES:
1. The ROER bit is set to "0" when the RE bit in the G3CR register is set to "0".
Figure 21.49 G3FLG Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 319 of 488
RW
RO
M32C/83 Group (M32C/83, M32C/83T)
21. Intelligent I/O (Group 3 Communication Function)
21.6.1 8-bit or 16-bit Clock Synchronous Serial I/O Mode (Group 3)
In 8-bit or 16-bit clock synchronous serial I/O mode, data is transmitted and received using the transfer
clock. When the internal clock is selected as the transfer clock, the channel 0 and channel 2 waveform
generation functions generate the transfer clock. ISTxD3, ISCLK3 and ISRxD3 share pins with OUTC30
to OUTC32 and are available in the 144-pin package only.
Table 21.41 lists specifications of clock synchronous serial I/O mode. Table 21.42 lists registers to be
used and their settings. Tables 21.43 and 21.44 list pin settings. Figure 21.50 and 21.51 shows an
example of transmit and receive operation.
Table 21.41 Clock Synchronous Serial I/O Mode (Group 3)
Item
Transfer Data Format
• Transfer data :
Specification
8 bits or 16 bits long
Transfer Clock(1)
• When the CKDIR bit in the G3MR register is set to "0" (internal clock) :
fBT3
2(n+2)
n : setting value of the G3PO0 register, 000116 to FFFD16
The G3PO0 register determines the bit rate and the transfer clock is generated in phasedelayed waveform output mode of the channel 2 waveform generation function.
• When the CKDIR bit is set to "1" (external clock) : input from the ISCLK3 pin
Set registers associated with the waveform generation function and the G3MR register.
Then, set as written below after waiting at least one transfer clock cycle.
• Set the TE bit in the G3CR register to "1" (transmit enable)
• Set the TI bit in the G3CR register to "0" (data in the G3TB register)
Set registers associated with the waveform generation function and the G3MR register.
Then, set as written below after waiting at least one transfer clock cycle.
• Set the RE bit in the G3CR register to "1" (receive enable)
• Set theTE bit to "1" (transmit enable)
• Set the TI bit to "0" (data in the G3TB register)
• While transmitting, one of the following conditions can be selected to set the
SIO3TR bit in the IIO10IR register to "1" (see Figure 10.14) :
_ When the IRS bit in the G3MR register is set to "0" (no data in the transmit buffer),
one transfer clock cycle after data transmission starts
_ When the IRS bit is set to "1" (reception completed),
15 transfer clock cycles after data transmission starts in 16-bit clock synchronous
serial I/O mode (set the DLS bit in the G3MR register to "0"), or
7 transfer clock cycles after data transmission starts in 8-bit clock clock synchronous
serial I/O mode (set the DLS bit to "1").
• While receiving, the following condition can be selected to set the SIO3RR bit in the
IIO9IR register to "1" (see Figure 10.14) :
15.5 transfer clock cycles after data transmission starts in 16-bit clock synchronous
serial I/O mode, or
7.5 transfer clock cycles after data transmission starts in 8-bit clock synchronous
serial I/O mode
• Overrun error(3)
This error occurs in 16-bit clock synchronous serial I/O mode when the 15th bit of
the next data is received before reading the G3RB register.
This error occurs in 8-bit clock synchronous serial I/O mode when the 7th bit of the
next data is received before reading the G3RB register.
• LSB first/MSB first
Select either bit 0 or bit 7 to transmit/receive data
• ISTxD3 and ISRxD3 I/O polarity inverse
_
Transmit Start Condition(2)
Receive Start Condition
Interrupt Request
Error Detection
Selectable Function
ISTxD3 pin output level and ISRxD3 pin input level are inversed
NOTES:
1. The transfer clock must be fBT3 divided by six or more.
2. Transmit interrupt request is generated when the TE bit is set to "1". Set the interrupt-associated
registers after setting the TE bit.
3. When an overrun error occurs, the G3RB register is indeterminate.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 320 of 488
21. Intelligent I/O (Group 3 Communication Function)
M32C/83 Group (M32C/83, M32C/83T)
Table 21.42 Registers to be Used and Settings
Register
Bit
G3BCR0
Function
BCK1 to BCK0
Set to "112"
DIV4 to DIV0
Select divide ratio of count source
IT
Set to "0"
G3BCR1
7 to 0
Set to "0001 00102"
G3POCR0
7 to 0
Set to "0000 01112"
G3POCR1
7 to 0
Set to "0000 01112"
G3POCR2
7 to 0
Set to "0000 00102"
G3PO0
15 to 0
Set bit rate
fBT3
2 x (setting value + 2) = transfer clock frequency
G3PO2
15 to 0
Set to a value smaller than the G3PO0 register
G3FE
7 to 0
Set to "0000 01112"
G3MR
GMD1 to GMD0 Set to "012"
G3CR
CKDIR
Select the internal clock or external clock
TLD
Select transfer data length
UFORM
Select either LSB first or MSB first
IRS
Select how the transmit interrupt is generated
TE
Set to "1" to enable transmission
TXEPT
Transmit register empty flag
TI
Transmit buffer empty flag
RE
Set to "1" to enable reception
RI
Receive complete flag
OPOL
ISTxD3 output polarity inverse (usually set to "0")
IPOL
ISRxD3 input polarity inverse
G3TB
15 to 0
Write transmit data
G3RB
15 to 0
Received data is stored
Table 21.43 Pin Setting in Clock Synchronous Serial I/O Mode (Group 3)
Register(1)
Port
Function
Bit and Setting
Name
P81
ISTxD3 output
PS2 Register
PS2_1 = 1
PSL2 Register
PSL2_1 = 1
PD8 Register IPS Register
-
G3POCR0
P82
ISRxD3 input
PS2_2 = 0
-
PD8_2 = 0
-
IPS7 = 0
NOTES:
1. Set the MOD2 to MOD0 bits in the corresponding register to "1112" (output of the communication
function used).
Table 21.44 Pin Setting (Continued)
Port
Name
P120
Function
Register(1)
Bit and Setting
ISTxD3 output
PS6 Register
PS6_0 =1
PD12 Register
-
IPS Register
-
P121
ISCLK3 input
ISCLK3 output
PS6_1 = 0
PS6_1 = 1
PD12_1 = 0
-
-
G3POCR0
G3POCR1
P122
ISRxD3 input
PS6_2 = 0
PD12_2 = 0
IPS7 = 1
-
NOTES:
1. Set the MOD2 to MOD0 bits in the corresponding register to "1112" (output of the communication
function used).
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 321 of 488
21. Intelligent I/O (Group 3 Communication Function)
M32C/83 Group (M32C/83, M32C/83T)
Write to the G3TB register
The base timer is reset by the channel 0
waveform generation function
n+2
Base Timer 3
m
ISCLK3 pin output
(transmit clock in the
channel 2 waveform
generation function)
ISTxD3 pin output
(data to be transmitted)
SIO3TR bit
When IRS=0
(no data in the
transmit buffer)
SIO3TR bit
When IRS=1
(transmission completed)
ISRxD3 pin input
(received data)
Bit 0
Bit 1
Bit 2
Bit 6
Bit 7
Write "0" by program
if setting to "0"
Write "0" by program
if setting to "0"
Bit 0
Bit 1
Bit 2
Bit 6
Bit 7
SIO3RR bit
Write "0" by program if setting to "0"
The above timing applies under the following settings.
• The CKDIR bit in the G3MR register is set to "0" (internal clock)
• The UFORM bit in the G3MR register is set to "0" (LSB first)
• The IPOL bit and OPOL bit in the G3CR register are set to "0" (no inverse)
• The TLD bit in the G3CR register is set to "1" (8 bits long)
Figure 21. 50 Transmit and Receive Operation (8-bit Length)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 322 of 488
n : Setting value of the G3PO0 register
m : Setting value of the G3PO2 register
SIO3TR bit : Bit in the IIO10IR register
SIO3RR bit : Bit in the IIO9IR register
IRS bit
: Bit in the G3MR register
21. Intelligent I/O (Group 3 Communication Function)
M32C/83 Group (M32C/83, M32C/83T)
Write to the G3TB register
The base timer is reset by the channel 0
waveform generation function
n+2
Base Timer 3
m
ISCLK3 pin output
(transmit clock in the
channel 2 WG function)
ISTxD3 pin output
(data to be transmitted)
SIO3TR bit
when IRS=0
(no data in the
transmit buffer)
SIO3TR bit
when IRS=1
(transmission completed)
Bit 0
Bit 1
Bit 2
Bit 14
Bit 15
Write "0" by program
if setting to "0"
Write "0" by program
if setting to "0"
ISRxD3 pin input
(received data)
Bit 0
Bit 1
Bit 2
Bit 14
Bit 15
SIO3RR bit
Write "0" by program if setting to "0"
The above timing applies under the following settings.
• The CKDIR bit in the G3MR register is set to "0" (internal clock)
• The UFORM bit in the G3MR register is set to "0" (LSB first)
• The IPOL bit and OPOL bit in the G3CR register are set to "0" (no inverse)
• The TLD bit in the G3CR register is set to "1" (16 bits long)
Figure 21. 51 Transmit and Receive Operation (16-bit Length)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 323 of 488
n : Setting value of the G3PO0 register
m : Setting value of the G3PO2 register
SIO3TR bit : Bit in the IIO10IR register
SIO3RR bit : Bit in the IIO9IR register
IRS bit
: Bit in the G3MR register
22. CAN Module
M32C/83 Group (M32C/83, M32C/83T)
22. CAN Module
The CAN (Controller Area Network) module incorporated in the M32C/83 group is a Full CAN module,
compatible with CAN Specification 2.0 Part B. Table 22.1 lists specifications of the CAN module.
Table 22.1 CAN Module Specifications
Item
Specification
Protocol
Message Slots
Polarity
CAN Specification 2.0 Part B
16 slots
Dominant: "L"
Recessive: "H"
Global mask: 1 mask (for message slots 0 to 13)
Local mask: 2 masks (for message slots 14 and 15 respectively)
Acceptance Filter
1
Tq clock cycle x Tq per bit
Tq clock cycle = BRP + 1
f1
Tq per bit = SS + PTS +PBS1+PBS2
Tq: Time quantum
Baud Rate
Baud rate =
Remote Frame Automatic
Answering Function
Time Stamp Function
BasicCAN Mode
Transmit Abort Function
Loopback Function
Forcible Error Active
Clear Function
--- Max. 1 Mbps
BRP: Setting value in the C0BRP and C1BRP registers, 1-255
SS: Synchronization Segment; 1 Tq
PTS: Propagation Time Segment; 1 to 8 Tq
PBS1: Phase Buffer Segment 1; 2 to 8 Tq
PBS2: Phase Buffer Segment 2 ; 2 to 8 Tq
Message slot that receives the remote frame transmits the data frame
automatically
Time stamp function with a 16-bit counter. Count source can be selected
from the CAN bus bit clock divided by 1, 2, 3 or 4.
BasicCAN function can be used with the CANi message slots 14 and 15.
Transmit request is aborted
Frame transmitted by the CAN module is received by the same CAN module
The CAN module is forced into an error active state
NOTES:
1. Use an oscillator with maximum 1.58% oscillation tolerance.
Figure 22.1 shows a block diagram of the CAN module. Figure 22.2 shows CANi message slot buffer (the
message slot buffer) (i=0,1) and CANi message slot (the message slot) j (j=0 to 15). Table 22.2 lists pin
settings of the CAN module.
The message slot cannot be accessed directly from the CPU. Allocate the message slot j to be used to the
message slot buffer 0 or 1. The message slot j is accessed via the message slot buffer address. The
CiSBS register selects the message slot j to be allocated. Figure 22.2 shows the 16-byte message slot
buffer and message slot.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 324 of 488
M32C/83 Group (M32C/83, M32C/83T)
22. CAN Module
Data Bus
C0SLPR
register
f1
C0GMR0 to 4
registers
C0CTLR0, 1
registers
C0BRP
register
C0CONR
register
C0LMAR0 to 4
registers
C0IDR
register
C0LMBR0 to 4
registers
C0EIMKR
register
C0EISTR
register
C0SIMKR
register
C0SISTR
register
C0SLOT0_0 to15
registers
C0STR
register
C0TEC
register
C0REC
register
C0MCTL0 to 15
registers
C0SBS
register
Interrupt
control circuit
CANIN
Interrupt request
Acceptance
Filter
CAN protocol
controller
Ver 2.0B
CANOUT
C0AFS
register
C0SLOT1_0 to15
registers
Message
slots 0 to 15
16-bit timer
C0TSR
register
Figure 22.1 CAN Module Block Diagram
CAN0 message slot buffer 0 (addresses 01E016 to 01EF16)
CAN0 message slot buffer 1 (addresses 01F016 to 01FF16)
CAN0 message slot 0 to 15
CAN0 message slot buffer 0 standard ID0 (C0SLOT0_0)
CAN0 message slot buffer 0 standard ID1 (C0SLOT0_1)
CAN0 message slot buffer 0 standard ID0
CAN0 message slot buffer 0 extended ID0 (C0SLOT0_2)
CAN0 message slot buffer 0 standard ID1
CAN0 message slot buffer 0 extended ID1 (C0SLOT0_3)
CAN0 message slot buffer 0 extended ID0
CAN0 message slot buffer 0 extended ID2 (C0SLOT0_4)
CAN0 message slot buffer 0 extended ID1
CAN0 message slot buffer 0 data length code (C0SLOT0_5)
CAN0 message slot buffer 0 extended ID2
CAN0 message slot buffer 0 data 0 (C0SLOT0_6)
CAN0 message slot buffer 0 data length code
CAN0 message slot buffer 0 data 1 (C0SLOT0_7)
CAN0 message slot buffer 0 data 0
CAN0 message slot buffer 0 data 2 (C0SLOT0_8)
CAN0 message slot buffer 0 data 1
CAN0 message slot buffer 0 data 3 (C0SLOT0_9)
CAN0 message slot buffer 0 data 2
CAN0 message slot buffer 0 data 4 (C0SLOT0_10)
CAN0 message slot buffer 0 data 3
CAN0 message slot buffer 0 data 5 (C0SLOT0_11)
CAN0 message slot buffer 0 data 4
CAN0 message slot buffer 0 data 6 (C0SLOT0_12)
CAN0 message slot buffer 0 data 5
CAN0 message slot buffer 0 data 7 (C0SLOT0_13)
CAN0 message slot buffer 0 data 6
CAN0 message slot buffer 0 time stamp high-ordered (C0SLOT0_14)
CAN0 message slot buffer 0 data 7
CAN0 message slot buffer 0 time stamp low-ordered (C0SLOT0_15)
CAN0 message slot buffer 0 time stamp- high
CAN0 message slot buffer 1 time stamp low-ordered (C0SLOT1_15)
CAN0 message slot 0 standard ID0
CAN0 message slot 0 standard ID1
CAN0CAN0
message
slot 0 slot
extended
message
buffer ID0
0 standard ID0
CAN0CAN0
message
slot 0 slot
extended
message
buffer ID1
0 standard ID1
CAN0CAN0
message
slot 0 slot
extended
message
buffer ID2
0 extended ID0
CAN0CAN0
message
slot 0 slot
databuffer
length0 code
message
extended ID1
CAN0CAN0
message
slot 0 slot
databuffer
0
message
0 extended ID2
CAN0CAN0
message
slot 0 slot
databuffer
1
message
0 data length code
CAN0CAN0
message
slot 0 slot
databuffer
2
message
0 data 0
CAN0CAN0
message
slot 0 slot
databuffer
3
message
0 data 1
CAN0CAN0
message
slot 0 slot
databuffer
4
message
0 data 2
CAN0CAN0
message
slot 0 slot
databuffer
5
message
0 data 3
CAN0CAN0
message
slot 0 slot
databuffer
6
message
0 data 4
CAN0CAN0
message
slot 0 slot
databuffer
7
message
0 data 5
CAN0CAN0
message
slot 0 slot
timebuffer
stamp0 high
message
data 6
CAN0CAN0
message
slot 0 slot
timebuffer
stamp0 low
message
data 7
CAN0 message slot 15 time stamp low-ordered
Figure 22.2 Message Slot Buffer and Message Slot
Table 22.2 Pin Settings
Port
Function
Bit and Setting
PS1, PS2
PSL1, PSL2
Registers
CANOUT
PS1_6=1
P77
CANIN
PS1_7=0
P82
CANOUT
PS2_2=1
P83
CANIN
–
–
Page 325 of 488
IPS Registers
PD7, PD8
Registers
P76
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
PSC Registers
PSL1_6=0
Registers
PSC_6=1
–
–
–
–
IPS3=0
PD7_7=0
PSL2_2=1
–
–
–
–
IPS3=1
PD8_3=0
22. CAN Module
M32C/83 Group (M32C/83, M32C/83T)
22.1 CAN-Associated Registers
Figures 22.3 to 22.26 show registers associated with CAN. To access the associated registers, set the
MCD4 to MCD0 bits in the MCD register to "100102" (no division of CPU clock), the PM13 bit in the PM1
register to "1" (2 wait states), and the CM07 bit in the CM0 register to "0" (XIN-XOUT selected).
22.1.1 CAN0 Control Register 0 (C0CTLR0 Register)
CAN0 Control Register 0
b15
b8 b7
b0
Symbol
C0CTLR0
0
Bit
Symbol
Address
020116 - 020016
Bit Name
RESET0 CAN Reset Bit 0
LOOPBACK
(b2)
BASICCAN
Loop Back Mode
Select Bit
(b7 - b6)
Function
RW
0: CAN module reset exited
1: CAN module is reset(2)
RW
0: Disables Loop back function
1: Enables Loop back function
RW
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Basic CAN Mode
Select Bit
RESET1 CAN Reset Bit 1
(b5)
After Reset(1)
XXXX 0000 XX01 0X012
Reserved Bit
0 : Disables BasicCAN mode function
1 : Enables BasicCAN mode function
RW
0: CAN module reset exited
1: CAN module is reset(2)
RW
Set to "0".
RW
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
b9 b8
TSPRE0
0 0: Selects the CAN bus bit clock
Time Stamp
Prescaler Select Bit
TSPRE1
TSRESET
1 1: Selects the CAN bus bit clock divided by 4
Time Stamp
Counter Reset Bit
ECRESET Error Counter
Reset Bit
(b15 - b12)
0 1: Selects the CAN bus bit clock divided by 2
1 0: Selects the CAN bus bit clock divided by 3
When this bit is set to "1", the C0TSR
register is set to "000016". After that,
this bit is automatically set to "0".(3)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 326 of 488
RW
RW
When this bit is set to "1", the C0TEC
RW
and C0REC registers are set to "0016".
After that, this bit is automatically set to "0".(3)
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
NOTES:
1. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and
supplying a clock to the CAN module after reset.
2. Set the RESET0 bit and RESET1 bit to the same value simultaneously.
3. This bit can be set to "1" by program, but cannot be set to "0".
Figure 22.3 C0CTLR0 Register
RW
M32C/83 Group (M32C/83, M32C/83T)
22. CAN Module
22.1.1.1 RESET0 Bit and RESET1 Bit
When both RESET0 and RESET1 bits are set to "1", the CAN module is immediately reset regardless of ongoing CAN communication.
After the RESET0 and RESET1 bits are set to "1" and the CAN module reset is completed, the
C0TSR register is set to "000016". The C0TEC and C0REC registers are set to "0016" and the
STATE_ERRPAS and STATE_BUSOFF bits in the C0STR register are set to "0" as well.
When both RESET0 and RESET1 bits are changed "1" to "0", the C0TSR register starts counting.
CAN communication is available after 11 continuous recessive bits are detected.
NOTES:
1. Set the same value in both RESET0 and RESET1 bits simultaneously.
2. Set CAN configuration upon confirming that the STATE_RESET bit in the C0STR register is set
to "1" (CAN module reset completed) after setting the RESET0 and RESET1 bits to "1".
3. The CANOUT pin outputs an "H" signal as soon as the RESET0 and RESET1 bits are set to "1".
CAN bus error may occur when the RESET0 and RESET1 bits are set to "1" while the CAN
frame is transmitting.
4. For CAN communication, set the PS1, PS2, PSL1, PSL2, PSC, and IPS registers when the
STATE_RESET bit is set to "1" (CAN module reset completed).
22.1.1.2 LOOPBACK Bit
When the LOOPBACK bit is set to "1" (loopback function enabled) and the receive message slot has
a matched ID and frame format with a transmitted frame, the transmitted frame is stored to the
receive message slot.
NOTES:
1. No ACK for the transmitted frame is returned.
2. Change the LOOPBACK bit only when the STATE_RESET bit is set to "1" (CAN module reset
completed).
22.1.1.3 BASICCAN Bit
When the BASICCAN bit is set to "1", the message slots 14 and 15 enter BasicCAN mode.
In BasicCAN mode, the message slots 14 and 15 are used as dual-structured buffers. The message
slot 14 and 15 alternately store a received frame having matched ID detected by acceptance filtering.
The ID in the message slot 14 and the C0LMAR0 to C0LMAR4 registers are used for acceptance
filtering when the message slot 14 is active (the next received frame is to be stored in the message
slot 14). The ID in the message slot 15 and the C0LMBR0 to C0LMBR4 registers are used when the
message slot 15 is active. Both data frame and remote frame can be received.
When entering BasicCAN mode, set the same ID in two message slots and set the same values in
the C0LMAR0 to C0LMAR4 registers and in the C0LMBR0 to C0LMBR4 registers.
Follow the procedure below to enter BasicCAN mode.
(1) Set the BASICCAN bit to "1".
(2) Set IDs in the message slots 14 and 15. Set the C0LMAR0 to C0LMAR4 registers and C0LMBR0
to C0LMBR4 registers. (Set to the same values.)
(3) Set the IDE14 and 15 bits in the C0IDR register to select a frame format (standard or extended)
for the message slots 14 and 15. (Set to the same format.)
(4) Set the REMACTIVE bit in the C0MCTL14 and C0MCTL15 registers in the message slots 14 and
15 to "0" (data frame received) and the RECREQ bit to "1" (request to receive).
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 327 of 488
M32C/83 Group (M32C/83, M32C/83T)
22. CAN Module
NOTES:
1. Change the BASICCAN bit only when the STATE_RESET bit is set to "1" (CAN module reset
completed).
2. The message slot 14 is the first slot to become active after the RESET0 and RESET1 bits are
set to "0".
3. The message slots 0 to 13 are not affected by entering BasicCAN mode.
22.1.1.4 TSPRE1, TSPRE0 Bits
The TSPRE1 and TSPRE0 bits determine which count source is used for the time stamp counter.
NOTES:
1. Change the TSPRE1 to TSPRE0 bits only when the STATE_RESET bit is set to "1" (CAN
module reset completed).
22.1.1.5 TSRESET Bit
When the TSRESET bit is set to "1" (counter reset), the C0TSR register is set to "000016". The
TSRESET bit is automatically set to "0" after the C0TSR register is set to "000016".
22.1.1.6 ECRESET Bit
When the ECRESET bit is set to "1", the C0TEC and C0REC registers are set to "0016". The CAN
module forcibly goes into an error active state.
The ECRESET bit is automatically set to "0" after the CAN module enters an error active state.
NOTES:
1. In an error active state, the CAN module is ready to communicate when 11 continuous recessive bits are detected on the CAN bus.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 328 of 488
M32C/83 Group (M32C/83, M32C/83T)
22. CAN Module
22.1.2 CAN0 Control Register 1 (C0CTLR1 Register)
CAN0 Control Register 1
b7
b6
b5
b4
0 0
b3
b2
b1
b0
Symbol
C0CTLR1
0
Bit
Symbol
(b1 - b0)
(b2)
Bit Name
(b7 - b6)
Function
RW
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Reserved Bit
BANKSEL CAN0 Bank Switch Bit
(b5 - b4)
After Reset(1)
XX00 00XX2
Address
024116
Reserved Bit
Set to "0"
RW
0 : Selects the message slot control
register
1 : Selects the masked register
RW
Set to "0"
RW
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
NOTES:
1. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and
supplying a clock to the CAN module after reset.
Figure 22.4 C0CTLR1 Register
22.1.2.1 BANKSEL Bit
The BANKSEL bit in the C0CTLR1 register selects the registers allocated to addresses 0220 16 to
023F16.
The C0MCTL0 to C0MCTL15 registers can be accessed by setting the BANKSEL bit to "0". The
C0GMR0 to C0GMR4 registers, C0LMAR0 to C0LMAR4 registers and C0LMBR0 to C0LMBR4 registers can be accessed by setting the BANKSEL bit to "1".
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 329 of 488
22. CAN Module
M32C/83 Group (M32C/83, M32C/83T)
22.1.3 CAN0 Sleep Control Register (C0SLPR Register)
CAN0 Sleep Control Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
C0SLPR
Address
024216
Bit
Symbol
Bit Name
SLEEP
Sleep Mode Control Bit
After Reset
XXXX XXX02
Function
RW
0 : Enters sleep mode
1 : Exits sleep mode
(Note 1) RW
Nothing is assigned. When write, set to "0".
(b7 - b1) When read, its content is indeterminate.
NOTES:
1. Set up CAN module configuration after CAN sleep mode is exited. While the CAN module is in sleep
mode, no SFR (addresses 01E016 to 024516) for the CAN module, except the C0SLPR register, can
be accessed.
Figure 22.5 C0SLPR Register
22.1.3.1 SLEEP Bit
When the SLEEP bit is set to "0", the clock supplied to the CAN module stops running and enters
sleep mode.
When the SLEEP bit is set to "1", the clock supplied to the CAN module starts running and exits sleep
mode.
NOTES:
1. Enter sleep mode after the STATE_RESET bit in the C0STR register is set to "1" (CAN module
reset completed).
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 330 of 488
M32C/83 Group (M32C/83, M32C/83T)
22. CAN Module
22.1.4 CAN0 Status Register (C0STR Register)
CAN0 Status Register
b15
b8 b7
b0
Symbol
C0STR
Bit
Symbol
Bit Name
Function
b3 b2 b1 b0
MBOX0
MBOX1
After reset(1)
X000 0X01 0000 00002
Address
020316 - 020216
Active Slot
Determination Bit
0
0
0
0
0
0
0
0
0
0
1
1
0 : Message slot 0
1 : Message slot 1
0 : Message slot 2
1 : Message slot 3
RO
RO
RO
MBOX2
1 1 0 1 : Message slot 13
1 1 1 0 : Message slot 14
1 1 1 1 : Message slot 15
MBOX3
RW
RO
TRMSUCC
Transmit Complete
State Flag
0: Transmission is not completed
RO
1: Transmission is completed
RECSUCC
Receive Complete
State Flag
0: Reception is not completed
1: Reception is completed
RO
TRMSTATE
Transmit State Flag
0: Not transmitting
1: During transmission
RO
RECSTATE
Receive State Flag
0: Not receiving
1: During reception
RO
STATE_RESET CAN Reset State Flag
0: CAN module is operating
RO
1: CAN module reset is completed
STATE_LOOPBACK Loop Back State Flag
0: Mode except Loop back mode
RO
1: Loop back mode
(b10)
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
STATE_BASICCAN BasicCAN State Flag
0: Mode except BasicCAN mode
RO
1: BasicCAN mode
STATE_BUSERROR CAN Bus Error State Flag
0: No error occurs
1: Error occurs
RO
STATE_ERRPAS Error Passive State Flag
0: No error passive state
1: Error passive state
RO
STATE_BUSOFF Bus-off State Flag
0: No bus-off state
1: Bus-off state
RO
(b15)
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
NOTES:
1. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and
supplying a clock to the CAN module after reset.
Figure 22.6 C0STR Register
22.1.4.1 MBOX3 to MBOX0 Bits
The MBOX3 to MBOX0 bits store relevant slot numbers when the CAN module has completed transmitting data or storing received data.
22.1.4.2 TRMSUCC Bit
The TRMSUCC bit is set to "1" when the CAN module has transmitted data as expected.
The TRMSUCC bit is set to "0" when the CAN module has received data as expected.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 331 of 488
M32C/83 Group (M32C/83, M32C/83T)
22. CAN Module
22.1.4.3 RECSUCC Bit
The RECSUCC bit is set to "1" when the CAN module has received data as expected. (Whether
received message has been stored in the message slot or not is irrelevant.) If the received message
is transmitted in loopback mode, the TRMSUCC bit is set to "1" and the RECSUCC bit is set to "0".
The RECSUCC bit is set to "0" when the CAN module has transmitted data as expected.
22.1.4.4 TRMSTATE Bit
The TRMSTATE bit is set to "1" when the CAN module is performing as a transmit node.
The TRMSTATE bit is set to "0" when the CAN module is in a bus-idle state or starts performing as
a receive node.
22.1.4.5 RECSTATE Bit
The RECSTATE bit is set to "1" when the CAN module is performing as a receive node.
The RECSTATE bit is set to "0" when the CAN module is in a bus-idle state or starts performing as
a transmit node.
22.1.4.6 STATE_RESET Bit
After both RESET0 and RESET1 bits are set to "1" (CAN module reset), the STATE_RESET bit is
set to "1" as soon as the CAN module is reset.
The STATE_RESET bit is set to "0" when the RESET0 and RESET1 bits are set to "0".
22.1.4.7 STATE_LOOPBACK Bit
The STATE_ LOOPBACK bit is set to "1" when the CAN module is in loopback mode.
The STATE_LOOPBACK bit is set to "1" when the LOOPBACK bit in the C0CTLR0 register is set to "1"
(loop back function enabled).
The STATE_LOOPBACK bit is set to "0" when the LOOPBACK bit is set to "0" (loop back function
disabled).
22.1.4.8 STATE_BASICCAN Bit
The STATE_BASICCAN bit is set to "1" when the CAN module is in BasicCAN mode.
Refer to 22.1.1.3 BASICCAN Bit for BasicCAN mode.
The STATE_BASICCAN bit is set to "0" when the BASICCAN bit is set to "0" (BasicCAN mode
function disabled).
The STATE_BASICCAN bit is set to "1" when the BASICCAN bit is set to "1" (BasicCAN mode
function enabled), the REMACTIVE bits in the C0MCTL14 and C0MCTL15 registers in the message
slot 14 and 15 are set to "0" (data frame received) and the RECREQ bit is set to "1" (request to
receive the frame).
22.1.4.9 STATE_BUSERROR Bit
The STATE_BUSERROR bit is set to "1" when an CAN communication error is detected.
The STATE_BUSERROR bit is set to "0" when the CAN module has transmitted or received data as
expected. Whether a received message has been stored into the message slot or not is irrelevant.
NOTES:
1. When the STATE_BUSERROR bit is set to "1", the STATE_BUSERROR bit remains unchanged even if both RESET 0 and RESET1 bits are set to "1" (CAN module reset).
22.1.4.10 STATE_ERRPAS Bit
The STATE_ERRPAS bit is set to "1" when the value of the C0TEC or C0REC register exceeds 127
and places the CAN module in an error-passive state.
The STATE_ERRPAS bit is set to "0" when the CAN module in an error passive state is placed in
another error state.
The STATE_ERRPAS bit is set to "0" when both RESET0 and RESET1 bits are set to "1" (CAN
module is reset).
22.1.4.11 STATE_BUSOFF Bit
The STATE_BUSOFF bit is set to "1" when the value of the C0TEC register exceeds 255 and the
CAN module in a bus-off state.
The STATE_BUSOFF bit is set to "0" when the CAN module in a bus-off state is placed in an erroractive state.
The STATE_BUSOFF bit is set to "0" when both RESET0 and RESET1 bits are set to "1" (CAN
module reset).
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 332 of 488
M32C/83 Group (M32C/83, M32C/83T)
22. CAN Module
22.1.5 CAN0 Extended ID Register (C0IDR Register)
CAN0 Extended ID Register
b15
b8 b7
b0
Symbol
C0IDR
Bit
Symbol
Address
020516 - 020416
Bit Name
After Reset(1)
000016
Function
RW
IDE15
Extended ID15 (message slot 15)
IDE14
Extended ID14 (message slot 14)
IDE13
Extended ID13 (message slot 13)
IDE12
Extended ID12 (message slot 12)
IDE11
Extended ID11 (message slot 11)
IDE10
Extended ID10 (message slot 10)
RW
IDE9
Extended ID9 (message slot 9)
RW
IDE8
Extended ID8 (message slot 8)
RW
IDE7
Extended ID7 (message slot 7)
RW
IDE6
Extended ID6 (message slot 6)
RW
IDE5
Extended ID5 (message slot 5)
RW
IDE4
Extended ID4 (message slot 4)
RW
IDE3
Extended ID3 (message slot 3)
RW
IDE2
Extended ID2 (message slot 2)
RW
IDE1
Extended ID1 (message slot 1)
RW
IDE0
Extended ID0 (message slot 0)
RW
Standard or extended
format is set by the
corresponding message
slot
0: Standard format
1: Extended format
RW
RW
RW
RW
RW
NOTES:
1. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and
supplying a clock to the CAN module after reset.
Figure 22.7 C0IDR Register
Bits in the C0IDR register determine the frame format in the message slot corresponding to each bit.
The standard format is selected when the bit is set to "0".
The extended format is selected when the bit is to set "1".
NOTES:
1. Set each bit in the C0IDR register when neither transmit request nor receive request from the
message slot is generated.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 333 of 488
22. CAN Module
M32C/83 Group (M32C/83, M32C/83T)
22.1.6 CAN0 Configuration Register (C0CONR Register)
CAN0 Configuration Register
b15
b8 b7
b0
Symbol
C0CONR
Bit
Symbol
(b3 - b0)
SAM
After Reset(1)
0000 0000 0000 XXXX2
Address
020716 - 020616
Bit Name
Function
RW
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Sampling Number
0: Sampled once
1: Sampled three times
RW
b7 b6 b5
PTS0
PTS1
Propagation Time
Segment
PTS2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : PTS = 1Tq
1 : PTS = 2Tq
0 : PTS = 3Tq
1 : PTS = 4Tq
0 : PTS = 5Tq
1 : PTS = 6Tq
0 : PTS = 7Tq
1 : PTS = 8Tq
RW
RW
RW
b10 b9 b8
PBS10
PBS11
Phase Buffer
Segment 1
PBS12
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : Do not set to this value
1 : PBS1 = 2Tq
0 : PBS1 = 3Tq
1 : PBS1 = 4Tq
0 : PBS1 = 5Tq
1 : PBS1 = 6Tq
0 : PBS1 = 7Tq
1 : PBS1 = 8Tq
RW
RW
RW
b13b12 b11
PBS20
PBS21
Phase Buffer
Segment 2
PBS22
SJW0
SJW1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : Do not set to this value
1 : PBS2 = 2Tq
0 : PBS2 = 3Tq
1 : PBS2 = 4Tq
0 : PBS2 = 5Tq
1 : PBS2 = 6Tq
0 : PBS2 = 7Tq
1 : PBS2 = 8Tq
b15 b14
reSynchronization
Jump Width
0
0
1
1
0 : SJW = 1Tq
1 : SJW = 2Tq
0 : SJW = 3Tq
1 : SJW = 4Tq
RW
RW
RW
RW
RW
NOTES:
1. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and
supplying a clock to the CAN module after reset.
PTS: Propagation Time Segment, PBS1: Phase Buffer Segment 1, PBS2: Phase Buffer Segment 2,
SJW: reSynchronization Jump Width
Figure 22.8 C0CONR Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 334 of 488
M32C/83 Group (M32C/83, M32C/83T)
22. CAN Module
22.1.6.1 SAM Bit
The SAM bit determines the number of sample points to be taken per bit.
When the SAM bit is set to "0", only one sample is taken per bit at the end of the Phase Buffer
Segment 1 (PBS1) to determine the value of the bit.
When the SAM bit is set to "1", three samples per bit are taken; one time quantum and two time
quanta before the end of PBS1, and at the end of PBS1. The sample result value which is detected
more than twice becomes the value of the bit sampled.
22.1.6.2 PTS2 to PTS0 Bits
The PTS2 to PTS0 bits determine PTS width.
22.1.6.3 PBS12 to PBS10 Bits
The PBS12 to PBS10 bits determine PBS1 width. Set the PBS12 to 10 bits to "0012" or more.
22.1.6.4 PBS22 to PBS20 Bits
The PBS22 to PBS20 bits determine PBS2 width. Set the PBS22 to PBS20 bits to "0012" or more.
22.1.6.5 SJW1 to SJW0 Bits
The SJW1 to SJW0 bits determine SJW width. Set the SJW1 to SJW0 bits to a value equal to or less
than that of the PBS12 to PBS10 bits and PBS22 to PBS20 bits.
Table 22.3 Bit Timing when CPU Clock = 30 MHz
Baud Rate
BRP
Tq Clock Cycles (ns)
Tq Per Bit
1Mbps
1
66.7
15
1
66.7
15
1
66.7
15
2
100
10
2
100
10
2
100
10
500Kbps
2
100
20
2
100
20
2
100
20
3
133.3
15
3
133.3
15
3
133.3
15
4
166.7
12
4
166.7
12
4
166.7
12
5
200
10
5
200
10
5
200
10
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 335 of 488
PTS+PBS1
12
11
10
7
6
5
16
15
14
12
11
10
9
8
7
7
6
5
PBS2
2
3
4
2
3
4
3
4
5
2
3
4
2
3
4
2
3
4
Sample Point
87%
80%
73%
80%
70%
60%
85%
80%
75%
87%
80%
73%
83%
75%
67%
80%
70%
60%
22. CAN Module
M32C/83 Group (M32C/83, M32C/83T)
22.1.7 CAN0 Time Stamp Register (C0TSR Register)
CAN0 Time Stamp Register
b15
b8
b7
b0
Symbol
Address
After reset(1)
C0TSR
020916 - 020816
000016
Function
RW
Value of Time Stamp
RO
NOTES:
1. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and
supplying a clock to the CAN module after reset.
Figure 22.9 C0TSR Register
The C0TSR register is a 16-bit counter. The TSPRE0 and TSPRE1 bits in the C0CTLR0 register
select the CAN bus bit clock divided by 1, 2, 3 or 4 as the count source for the C0TSR register.
When data transmission or reception is completed, the value of the C0TSR register is automatically
stored into the message slot.
The C0TSR register starts a counter increment when the RESET0 and RESET1 bits in the C0CTLR0
register are set to "0".
The C0TSR register is set to "000016":
• at the next count timing after the C0TSR register is set to "FFFF16";
• when the RESET0 and RESET1 bits are set to "1" (CAN module reset) by program, or
• when the TSRESET bit is set to "1" (C0TSR register reset) by program.
In loopback mode, when either data frame receive message slot or remote frame receive message
slot is available to store the message, the value of the C0TSR register is also stored into the message slot when data reception is completed. The value of the C0TSR register is not stored when data
transmission is completed.
22.1.8 CAN0 Transmit Error Count Register (C0TEC Register)
CAN0 Transmit Error Count Register
b7
b0
Symbol
Address
After Reset(1)
C0TEC
020A16
0016
Function
Counter Value of Transmit Errors
RW
RO
NTOES:
1. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and
supplying a clock to the CAN module after reset.
Figure 22.10 C0TEC Register
In an error active or an error passive state, the count value of a transmission error is stored into the
C0TEC register. The counter is decremented when the CAN module has transmitted data as expected or is incremented when an transmit error occurs.
In a bus-off state, an indeterminate value is stored into the C0TEC register. The C0TEC register is
set to "0016" when the CAN module is placed in an error active state again.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 336 of 488
M32C/83 Group (M32C/83, M32C/83T)
22. CAN Module
22.1.9 CAN0 Receive Error Count Register (C0REC Register)
CAN0 Receive Error Count Register
b7
b0
Symbol
Address
After Reset(1)
C0REC
020B16
0016
Function
RW
Counter Value of Receive Error
RO
NOTES:
1. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and
supplying a clock to the CAN module after reset.
Figure 22.11 C0REC Register
In an error active or an error passive state, a count value of the reception error is stored into the
C0REC register. The counter is decremented when the CAN module has received data as expected
or is incremented when a receive error occurs.
The C0REC register is set to 127 when the C0REC register is 128 (error passive state) or more and
the CAN module has received as expected.
In a bus-off state, an indeterminate value is stored into the C0REC register. The C0REC register is
set to "0016" when the CAN module is placed in an error active state again.
22.1.10 CAN0 Baud Rate Prescaler (C0BRP Register)
CAN0 Baud Rate Prescaler
b7
b0
Symbol
C0BRP
Address
021716
Function
If setting value is n, the CPU clock is divided
by (n+1).
After reset(1)
0116
Setting Range
RW
0116 to FF16(2)
RW
NOTES:
1. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and
supplying a clock to the CAN module after reset.
2. Do not set to "0016" (divide-by-1).
Figure 22.12 C0BRP Register
The C0BRP register determines the Tq clock cycle of the CAN bit timing. The baud rate is obtained
from Tq clock cycle x Tq per bit.
Tq clock cycle = (BRP+1) / f1
1
Baud rate =
Tq clock cycle x Tq per bit
Tq per bit = SS + PTS + PBS1 + PBS2
Tq: Time quantum
BRP: Setting value of the C0BRP register; 1-255
SS: Synchronization Segment; 1 Tq
PTS: Propagation Time Segment; 1 to 8 Tq
PBS1: Phase Buffer Segment 1; 2 to 8 Tq
PBS2: Phase Buffer Segment 2; 2 to 8 Tq
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 337 of 488
22. CAN Module
M32C/83 Group (M32C/83, M32C/83T)
22.1.11 CAN0 Slot Interrupt Status Register (C0SISTR Register)
CAN0 Slot Interrupt Status Register
b15
b8 b7
b0
Symbol
Address
After Reset(1)
C0SISTR
020D16 - 020C16
000016
Bit
Symbol
SIS15
SIS14
Bit Name
Message Slot 15 Interrupt
Request Status Bit
Message Slot 14 Interrupt
Request Status Bit
SIS13
Message Slot 13 Interrupt
Request Status Bit
SIS12
Message Slot 12 Interrupt
Request Status Bit
SIS11
Message Slot 11 Interrupt
Request Status Bit
Function
RW
Determines whether an interrupt of a RW
corresponding message slot is
requested or not.
RW
0: No interrupt requested
(Note 2)
1: Interrupt requested
RW
RW
RW
SIS10
Message Slot 10 Interrupt
Request Status Bit
RW
SIS9
Message Slot 9 Interrupt
Request Status Bit
RW
SIS8
Message Slot 8 Interrupt
Request Status Bit
RW
SIS7
Message Slot 7 Interrupt
Request Status Bit
RW
SIS6
Message Slot 6 Interrupt
Request Status Bit
RW
SIS5
Message Slot 5 Interrupt
Request Status Bit
RW
SIS4
Message Slot 4 Interrupt
Request Status Bit
RW
SIS3
Message Slot 3 Interrupt
Request Status Bit
RW
SIS2
Message Slot 2 Interrupt
Request Status Bit
RW
SIS1
Message Slot 1 Interrupt
Request Status Bit
RW
SIS0
Message Slot 0 Interrupt
Request Status Bit
RW
NOTES:
1. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and
supplying a clock to the CAN module after reset.
2. Set to "0" by program. If it is set to "1", the value before setting to "1" remains.
Figure 22.13 C0SISTR Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 338 of 488
M32C/83 Group (M32C/83, M32C/83T)
22. CAN Module
When using the CAN interrupt, the C0SISTR register indicates which message slot is requesting an
interrupt. The SISi bits (i=0 to 15) are not automatically set to "0" (no interrupt requested) when an
interrupt is acknowledged. Set the SISj bits to "0" by program(1).
Refer to 22.3 CAN Interrupt for details.
22.1.11.1 Message Slot for Transmission
The SISi bit is set to "1" (interrupt requested) when the C0TSR register is stored into the message slot
i after data transmission is completed.
22.1.11.2 Message Slot for Reception
The SISi bit is set to "1" when the received message is stored in the message slot i after data reception
is completed.
NOTES:
1. Use the MOV instruction, instead of the bit clear instruction, to set the SISi bit to "0". Bits in the
C0SISTR register, which are not being changed to "0", must be to "1".
For example: To set the SIS0 bit to "0"
Assembly language:
mov.w #07FFFh, C0SISTR
C language:
c0sistr = 0x7FFF;
2. If the automatic answering function is enabled in the remote frame receive message slot, the
SISi bit is set to "1" after the remote frame is received and after the data frame is transmitted.
3. In the remote frame transmit message slot, the SISi bit is set to "1" after the remote frame is
transmitted and after the data frame is received.
4. The SISi bit is set to "1" if the SISi bit is set to "1" by an interrupt request and "0" by program
simultaneously.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 339 of 488
22. CAN Module
M32C/83 Group (M32C/83, M32C/83T)
22.1.12 CAN0 Slot Interrupt Mask Register (C0SIMKR Register)
CAN0 Slot Interrupt Mask Register
b15
b8 b7
b0
Symbol
Address
After Reset(1)
C0SIMKR
021116 - 021016
000016
Bit
Symbol
Bit Name
Function
RW
Determines whether the interrupt
request of the corresponding
message slot is enabled or masked.
RW
SIM15
Slot 15 Interrupt
Request Mask Bit
SIM14
Slot 14 Interrupt
Request Mask Bit
SIM13
Slot 13 Interrupt
Request Mask Bit
SIM12
Slot 12 Interrupt
Request Mask Bit
RW
SIM11
Slot 11 Interrupt
Request Mask Bit
RW
SIM10
Slot 10 Interrupt
Request Mask Bit
RW
SIM9
Slot 9 Interrupt
Request Mask Bit
RW
SIM8
Slot 8 Interrupt
Request Mask Bit
RW
SIM7
Slot 7 Interrupt
Request Mask Bit
RW
SIM6
Slot 6 Interrupt
Request Mask Bit
RW
SIM5
Slot 5 Interrupt
Request Mask Bit
RW
SIM4
Slot 4 Interrupt
Request Mask Bit
RW
SIM3
Slot 3 Interrupt
Request Mask Bit
RW
SIM2
Slot 2 Interrupt
Request Mask Bit
RW
SIM1
Slot 1 Interrupt
Request Mask Bit
RW
SIM0
Slot 0 Interrupt
Request Mask Bit
RW
0: Masks (disables) an interrupt request
1: Enables an interrupt request
RW
RW
NOTES:
1. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and
supplying a clock to the CAN module after reset.
Figure 22.14 C0SIMKR Register
The CiSIMKR register determines whether an interrupt request that is generated by a data transmission
or reception in the corresponding message slot is enabled or disabled. When the SIMi bit (i=0 to 15) is
set to "1", an interrupt request generated by a data transmission or reception in the corresponding
message slot is enabled. Refer to 22.3 CAN Interrupt for details.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 340 of 488
22. CAN Module
M32C/83 Group (M32C/83, M32C/83T)
22.1.13 CAN0 Error Interrupt Mask Register (C0EIMKR Register)
CAN0 Error Interrupt Mask Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
C0EIMKR
Bit
Symbol
Address
021416
Bit Name
After Reset(1)
XXXX X0002
Function
RW
BOIM
Bus-off Interrupt
Mask Bit
0: Masks (disables) an interrupt request
1: Enables an interrupt request
RW
EPIM
Error-passive Interrupt 0: Masks (disables) an interrupt request
1: Enables an interrupt request
Mask Bit
RW
BEIM
CAN bus-error Interrupt 0: Masks (disables) an interrupt request
1: Enables an interrupt request
Mask Bit
RW
Nothing is assigned. When write, set to "0".
(b7 - b3) When read, its content is indeterminate.
NOTES:
1. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and
supplying the clock to the CAN module after reset.
Figure 22.15 C0EIMKR Register
22.1.13.1 BOIM Bit
The BOIM bit determines whether an interrupt request is enabled or disabled when the CAN module is
placed in a bus-off state. When the BOIM bit is set to "1", the bus-off interrupt request is enabled.
22.1.13.2 EPIM Bit
The EPIM bit determines whether an interrupt request is enabled or disabled when the CAN module is
placed in an error passive state. When the EPIM bit is set to "1", the error passive interrupt request is
enabled.
22.1.13.3 BEIM Bit
The BEIM bit determines whether an interrupt request is enabled or disabled when a CAN bus error
occurs. When the BEIM bit is set to "1", the CAN bus error interrupt request is enabled.
Refer to 22.3 CAN Interrupt for details.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 341 of 488
22. CAN Module
M32C/83 Group (M32C/83, M32C/83T)
22.1.14 CAN0 Error Interrupt Status Register (C0EISTR Register)
CAN0 Error Interrupt Status Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
After Reset(1)
C0EISTR
021516
XXXX X0002
Bit
Symbol
Bit Name
Function
RW
BOIS
Bus-Off Interrupt
Status Bit(2)
0: No interrupt is requested
1: Interrupt is requested
RW
EPIS
Error-Passive Interrupt
Status Bit(2)
0: No interrupt is requested
1: Interrupt is requested
RW
BEIS
CAN Bus-Error Interrupt 0: No interrupt is requested
1: Interrupt is requested
Status Bit(2)
RW
Nothing is assigned. When write, set to "0".
(b7 - b3) When read, its content is indeterminate.
NOTES:
1. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and
supplying the clock to the CAN module after reset.
2. Set to "0" by program. If it is set to "1", the value before setting to "1" remains.
Figure 22.16 C0EISTR Register
When using the CAN interrupt, the C0EISTR register indicates the cause of the generated error interrupt. The BOIS, EPIS and BEIS bits are not automatically set to "0" (no interrupt requested) even if an
interrupt is acknowledged. Set these bits to "0" by program(1).
Refer to 22.3 CAN Interrupt for details.
22.1.14.1 BOIS Bit
The BOIS bit is set to "1" when the CAN module is placed in a bus-off state.
22.1.14.2 EPIS Bit
The EPIS bit is set to "1" when the CAN module is placed in an error passive state.
22.1.14.3 BEIS Bit
The BEIS bit is set to "1" when a CAN bus error is detected.
NOTES:
1. Use the MOV instruction, instead of the bit clear instruction, to set each bit in the CoEISTR register
to "0". Bits not being changed to "0" must be set to "1".
For example: To set the BOIS bit to "0"
Assembly language:
mov.b#006h, C0EISTR
C language:
c0eistr = 0x06;
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 342 of 488
22. CAN Module
M32C/83 Group (M32C/83, M32C/83T)
22.1.15 CAN0 Global Mask Register, CAN0 Local Mask Register A and CAN0 Local Mask
Register B (C0GMRj (j=0 to4), C0LMARj and C0LMBRj Registers)
The C0GMRj, C0LMARj and C0LMBRj registers are used for acceptance filtering.
The C0GMRj register determines whether the IDs in the message slots 0 to 13 are verified. The
C0LMARj register determines whether the ID in the message slot 14 is verified. The C0LMBRj register
determines whether the ID in the message slot 15 is verified.
• When bits in these registers are set to "0", each ID bit, standard ID 0 to 1 bit and extended ID0 to
2 bit in the CAN0 message slots i (i=0 to 15) corresponding to the bits in the above registers, is
masked while acceptance filtering. (The corresponding bits are assumed to have matching IDs.)
• When bits in these registers are set to "1", corresponding ID bits are compared with received IDs
while acceptance filtering. If the received ID matches the ID in the message slot i, the received
data having the matching ID is stored into that message slot.
NOTES:
1. Change the C0GMRj register only when the message slots 0 to 13 have no receive request.
2. Change the C0LMARj register only when the message slot 14 has no receive request.
3. Change the C0LMBRj register only when the message slot 15 has no receive request.
CAN0 Global Mask Register Standard ID0(1)
CAN0 Local Mask Register A Standard ID0(1)
CAN0 Local Mask Register B Standard ID0(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
C0GMR0
C0LMAR0
C0LMBR0
Bit
Symbol
Address
022816
023016(3)
023816(4)
Bit Name
After Reset(2)
XXX0 00002
XXX0 00002
XXX0 00002
Function
RW
SID6M Standard ID6
RW
SID7M Standard ID7
RW
SID8M Standard ID8
0: No ID is checked
1: ID is checked
RW
SID9M Standard ID9
RW
SID10M Standard ID10
RW
Nothing is assigned. When write, set to "0".
(b7 - b5) When read, its content is indeterminate.
NOTES:
1. This register can be accessed when the BANKSEL bit in the C0CTLR1 register is set to "1".
2. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and
supplying a clock to the CAN module after reset.
3. The C0LMAR0 register shares the same address with the C0MCTL0 register.
4. The C0LMBR0 register shares the same address with the C0MCTL8 register.
Figure 22.17 C0GMR0, C0LMAR0 and C0LMBR0 Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 343 of 488
22. CAN Module
M32C/83 Group (M32C/83, M32C/83T)
CAN0 Global Mask Register Standard ID1(1)
CAN0 Local Mask Register A Standard ID1(1)
CAN0 Local Mask Register B Standard ID1(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
C0GMR1
C0LMAR1
Address
022916
023116(3)
After Reset(2)
XX00 00002
XX00 00002
C0LMBR1
023916(4)
XX00 00002
Bit
Symbol
Bit Name
Function
RW
SID0M
Standard ID0
RW
SID1M
Standard ID1
RW
SID2M
Standard ID2
SID3M
Standard ID3
SID4M
Standard ID4
RW
SID5M
Standard ID5
RW
0: No ID is checked
1: ID is checked
RW
RW
Nothing is assigned. When write, set to "0".
(b7 - b6) When read, its content is indeterminate.
NOTES:
1. This register can be accessed when the BANKSEL bit in the C0CTLR1 register is set to "1".
2. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and
supplying a clock to the CAN module after reset.
3. The C0LMAR1 register shares the same address with the C0MCTL1 register.
4. The C0LMBR1 register shares the same address with the C0MCTL9 register.
CAN0 Global Mask Register Extended ID0(1)
CAN0 Local Mask Register A Extended ID0(1)
CAN0 Local Mask Register B Extended ID0(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
After Reset(2)
Address
C0GMR2
022A16
XXXX 00002
C0LMAR2
023216(3)
XXXX 00002
C0LMBR2
023A16(4)
XXXX 00002
Bit
Symbol
Bit Name
Function
EID14M Extended ID14
EID15M Extended ID15
EID16M Extended ID16
RW
RW
0: No ID is checked
1: ID is checked
EID17M Extended ID17
RW
RW
RW
Nothing is assigned. When write, set to "0".
(b7 - 4) When read, its content is indeterminate.
NOTES:
1. This register can be accessed when the BANKSEL bit in the C0CTLR1 register is set to "1".
2. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and
supplying a clock to the CAN module after reset.
3. The C0LMAR2 register shares the same address with the C0MCTL2 register.
4. The C0LMBR2 register shares the same address with the C0MCTL10 register.
Figure 22.18 C0GMR1, C0LMAR1 and C0LMBR1 Registers and
C0GMR2, C0LMAR2 and C0LMBR2 Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 344 of 488
22. CAN Module
M32C/83 Group (M32C/83, M32C/83T)
CAN0 Global Mask Register Extended ID1(1)
CAN0 Local Mask Register A Extended ID1(1)
CAN0 Local Mask Register B Extended ID1(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
C0GMR3
Address
022B16
After Reset(2)
0016
C0LMAR3
C0LMBR3
023316(3)
023B16(4)
0016
0016
Bit
Symbol
Bit Name
Function
RW
EID6M
Extended ID6
RW
EID7M
Extended ID7
RW
EID8M
Extended ID8
RW
EID9M
Extended ID9
EID10M Extended ID10
0: No ID is checked
1: ID is checked
RW
RW
EID11M Extended ID11
RW
EID12M Extended ID12
RW
EID13M Extended ID13
RW
NOTES:
1. This register can be accessed when the BANKSEL bit in the C0CTLR1 register is set to "1".
2. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and
supplying a clock to the CAN module after reset.
3. The C0LMAR3 register shares the same address with the C0MCTL3 register.
4. The C0LMBR3 register shares the same address with the C0MCTL11 register.
CAN0 Global Mask Register Extended ID2(1)
CAN0 Local Mask Register A Extended ID2(1)
CAN0 Local Mask Register B Extended ID2(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
After Reset(2)
C0GMR4
C0LMAR4
C0LMBR4
022C16
023416(3)
023C16(4)
XX00 00002
XX00 00002
XX00 00002
Bit
Symbol
Bit Name
Function
RW
EID0M
Extended ID0
RW
EID1M
Extended ID1
RW
EID2M
Extended ID2
EID3M
Extended ID3
EID4M
Extended ID4
RW
EID5M
Extended ID5
RW
0: No ID is checked
1: ID is checked
RW
RW
Nothing is assigned. When write, set to "0".
(b7 - b6) When read, its content is indeterminate.
NOTES:
1. This register can be accessed when the BANKSEL bit in the C0CTLR1 register is set to "1".
2. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and
supplying a clock to the CAN module after reset.
3. The C0LMAR4 register shares the same address with the C0MCTL4 register.
4. The C0LMBR4 register shares the same address with the C0MCTL12 register.
Figure 22.19 C0GMR3, C0LMAR3 and C0LMBR3 Registers and
C0GMR4, C0LMAR4 and C0LMBR4 Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 345 of 488
22. CAN Module
M32C/83 Group (M32C/83, M32C/83T)
22.1.16 CAN0 Message Slot i Control Register (C0MCTLi Register) (i=0 to 15)
CAN0 Message Slot i Control Register (i=0 to 15)(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
C0MCTL0 to C0MCTL3
Address
023016(3), 023116(3), 023216(3), 023316(3)
After Reset (2)
0000 00002
C0MCTL4 to C0MCTL7
C0MCTL8 to C0MCTL11
C0MCTL12 to C0MCTL15
023416(3), 023516, 023616, 023716
023816(3), 023916(3), 023A16(3), 023B16(3)
023C16(3), 023D16, 023E16, 023F16
0000 00002
0000 00002
0000 00002
Bit
Symbol
When receive,
NEWDATA
When transmit,
SENTDATA
When receive,
INVALDATA
When transmit,
TRMACTIVE
Bit Name
Receiving Flag
Transmitting Flag
MSGLOST Overwrite Flag
Remote Frame
REMACTIVE Transmit/Receive
Status Flag
Automatic
RSPLOCK Answering
Disable Mode
Select Bit
RW
Function
Receive Complete When transmitting
Flag
(4)
Transmit Complete 0: Not transmitted
1: Transmit complete
Flag
When transmitting
0: Stops transmitting
1: Transmits
When receiving
0: Not received(4)
1: Receive complete
When receiving
0: Stops receiving
1: Stores received data
0: No overrun error occurs
1: Overrun error occurs
RW
RO
(Note 4) RW
In modes other than BasicCan mode
0: Data frame
1: Remote frame
RO
In BasicCan mode
0: Receives the data frame (status)
1: Receives the remote frame (status)
0: Enables automatic answering of the remote
frame
RW
1: Disables automatic answering of the remote
frame
REMOTE
Remote Frame
Set Bit
0: Transmits/receives the data frame
1: Transmits/receives the remote frame
RW
RECREQ
Receive
Request Bit
0: No request to receive the frame
1: Request to receive data
RW
TRMREQ
Transmit
Request Bit
0: No request to transmit the frame
1: Request to transmit data
RW
NOTES:
1. This register can be accessed when the BANKSEL bit in the C0CTLR1 register is set to "1".
2. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and
supplying a clock to the CAN module after reset.
3. The C0MCTL0 to C0MCTL4 registers each share addresses with the C0MAR0 to C0MAR4
registers.
4. Each bit can be set to "0" by program. If it is set to "1", the value before setting to "1" remains.
Figure 22.20 C0MCTL0 to C0MCTL15 Registers
Table 22.4 C0MCTLi Register (i= 0 to 15) Settings and Transmit/Receive Mode
Settings for the C0MCTLi Register
TRMREQ RECREQ REMOTE RSPLOCK REMACTIVE MSGLOST TRMACTIVE SENTDATA Transmit/Receive Mode
INVALDATA NEWDATA
0
0
0
0
1
1
0
0
1
1
1
0
0
0
1
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
0
0
1
or
0
0
0
Page 346 of 488
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
No frame is transmitted or received
Data frame is received
Remote frame is received
(The data frame is transmitted
after receiving the remote frame.)
Data frame is transmitted
Remote frame is transmitted
(The data frame is received after
transmitting the remote frame)
M32C/83 Group (M32C/83, M32C/83T)
22. CAN Module
22.1.16.1 SENTDATA/NEWDATA Bit
The SENTDATA/NEWDATA bit indicates that the CAN module has transmitted or received the CAN
message. Set the SENTDATA/NEWDATA bit to "0 " (not transmitted or not received) by program
before data transmission and reception is started. The SENTDATA/NEWDATA bit is not set to "0"
automatically. When the TRMACTIVE/INVALDATA bit is set to "1" (during transmission or storing
received data), the SENTDATA/NEWDATA bit cannot be set to "0".
SENTDATA : The SENTDATA bit is set to "1" (transmit complete) when a data transmission is
completed in the transmit message slot.
NEWDATA
: The NEWDATA bit is set to "1" (receive complete) when the message to be stored into
the message slot i (i=0 to 15) is received in the receive message slot as expected.
NOTES:
1. To read a received data from the message slot i, set the NEWDATA bit to "0" before reading. If
the NEWDATA bit is set to "1" immediately after reading, this indicates that new received data
has been stored into the message slot while reading and the data read contains an indeterminate value. In this case, discard the data with indeterminate value and then read the message
slot again after the NEWDATA bit is set to "0".
2. When the remote frame is transmitted or received, the SENTDATA/NEWDATA bit remains unchanged after the remote frame transmission or reception is completed. The SENTDATA/
NEWDATA bit is set to "1" when a subsequent data frame transmission or reception is completed.
22.1.16.2 TRMACTIVE/INVALDATA Bit
The TRMACTIVE/INVALDATA bit indicates that the CAN module is transmitting or receiving a message and accessing the message slot i. The TRMACTIVE/INVALDATA bit is set to "1" when the CAN
module is accessing the message slot and to "0 " when not accessing the message slot.
TRMACTIVE : The TRMACTIVE bit is set to "1" (transmitting) when a data transmission is started
in the message slot. The TRMACTIVE bit is set to "0" (stops transmitting) if the
CAN module loses in bus arbitration and a CAN bus error occurs or when a data
transmission is completed.
INVALDATA : The INVALDATA bit is set to "1" (storing received data) when receiving a message
and storing a received data into the message slot i. Data, if read from the message
slot i while this bit is set to "1", is indeterminate.
22.1.16.3 MSGLOST Bit
The MSGLOST bit is valid only when the message slot is set for reception. The MSGLOST bit is set to
"1" (overrun error occurred) when the message slot i is overwritten by a new received message while
the NEWDATA bit set to "1" (already received).
The MSGLOST bit is not automatically set to "0". Set to "0" (no overrun error occurred) by program.
22.1.16.4 REMACTIVE Bit
The C0MCTL0 to C0MCTL15 registers all have the same function when the STATE_BASICCAN bit is
set to "0" (other than BasicCAN mode).
The REMACTIVE bit is set to "1" (remote frame) when the message slot i is set to transmit or receive
the remote frame. The REMACTIVE bit is set to "0" (data frame) after the remote frame has been
transmitted or received.
The functions of the C0MCTL14 and C0MCTL15 registers change when the STATE_BASICCAN bit is
set to "1" (BasicCAN mode). When the REMACTIVE bit is set to "0", this indicates that a message
stored into the message slot is the data frame. When the REMACTIVE bit is set to "1", this indicates a
message stored into the message slot is the remote frame.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 347 of 488
M32C/83 Group (M32C/83, M32C/83T)
22. CAN Module
22.1.16.5 RSPLOCK Bit
The RSPLOCK bit is valid only when remote frame reception shown in Table 22.4 is selected. The
RSPLOCK bit determines whether the received remote frame is processed or not.
When the RSPLOCK bit is set to "0" (automatic answering of the remote frame enabled), the slot
automatically changes to a transmit slot after the remote frame is received, and the message stored
into the message slot is automatically transmitted as the data frame.
When the RSPLOCK bit is set to "1" (automatic answering of the remote frame disabled), message is
not automatically transmitted upon receiving the remote frame.
Set the RSPLOCK bit to "0" to select any transmit/receive mode other than the remote frame reception.
22.1.16.6 REMOTE Bit
The REMOTE bit selects transmit/receive mode shown in Table 22.4. Set the REMOTE bit to "0" to
transmit or receive data frame. Set to "1" to transmit or receive remote frame.
The followings occur during remote frame transmission or reception.
• Transmitting the remote frame
A message stored into the message slot i (i=0 to 15) is transmitted as the remote frame. After
transmission, the slot automatically becomes ready to receive data frame.
If the data frame is received before the remote frame is transmitted, the data frame is stored into
the message slot i. The remote frame is not transmitted.
• Receiving the remote frame
The message slot receives the remote frame. The RSPLOCK bit determines whether or not to
process the received remote frame.
22.1.16.7 RECREQ Bit
The RECREQ bit selects transmit/receive mode shown in Table 22.4. Set the RECREQ bit to "1"
(receive requested) when data frame or remote frame is received. Set the RECREQ bit to "0" (no
receive requested) when data frame or remote frame is transmitted.
When a data frame is automatically transmitted after a remote frame is received, the RECREQ bit
remains set to "1". Set the RECREQ bit to "0" to transmit a remote frame. After a remote frame is
transmitted, a data frame is automatically received while the RECREQ bit remains set to "0".
When setting the TRMREQ bit to "1" (transmit requested), do not set the RECREQ bit to "1" (receive
requested).
22.1.16.8 TRMREQ Bit
The TRMREQ bit selects transmit/receive mode shown in Table 22.4. Set the TRMREQ bit to "1"
(transmit requested) when data frame or remote frame is transmitted.
Set the TRMREQ bit to "0" (no request to transmit the frame) when data frame or remote frame is received.
When the data frame is automatically received after the remote frame is transmitted, the TRMREQ bit
remains set to "1". Set the TRMREQ bit to "0" to receive the remote frame. After the remote frame is
received, data frame is automatically transmitted while the TRMREQ bit remains set to "0".
If the RECREQ bit is set to "1" (request to receive the frame), do not set the TRMREQ bit to "1" (
request to transmit the frame).
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 348 of 488
22. CAN Module
M32C/83 Group (M32C/83, M32C/83T)
22.1.17 CAN0 Slot Buffer Select Register (C0SBS Register)
CAN0 Slot Buffer Select Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
After Reset(2)
C0SBS
024016
0016
Bit
Symbol
Bit Name
Function
RW
b3 b2 b1 b0
SBS00
SBS01
SBS02
CAN0 Message
Slot Buffer 0
Number Select Bit
SBS03
0
0
0
0
0
0
0
0
0
0
1
1
0:
1:
0:
1:
RW
Message slot 0
Message slot 1
Message slot 2
Message slot 3
RW
(Note 1)
1
1
1
1
1
1
1
1
0
0
1
1
0:
1:
0:
1:
Message slot 12
Message slot 13
Message slot 14
Message slot 15
RW
Message slot 0
Message slot 1
Message slot 2
Message slot 3
RW
RW
b3 b2 b1 b0
SBS10
SBS11
SBS12
SBS13
CAN0 Message
Slot Buffer 1
Number Select Bit
0
0
0
0
0
0
0
0
0
0
1
1
0:
1:
0:
1:
RW
(Note 1)
1
1
1
1
1
1
1
1
0
0
1
1
0:
1:
0:
1:
Message slot 12
Message slot 13
Message slot 14
Message slot 15
RW
RW
NOTES:
1. 16 CAN0 message slots provided. Each message slot can be selected as a transmit or a receive
slot.
2. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and
supplying a clock to the CAN module after reset.
Figure 22.21 C0SBS Register
22.1.17.1 SBS03 to SBS00 Bits
If the SBS03 to SBS00 bits select a number i (i=0 to 15), the message slot i is allocated to the CAN0
message slot buffer 0. The message slot i can be accessed via addresses 01E016 to 01EF16.
22.1.17.2 SBS13 to SBS10 Bits
If the SBS13 to SBS10 bits select a number i, the message slot i is allocated to the CAN0 message slot
buffer 1. The message slot i can be accessed via addresses 01F016 to 01FF16.
22.1.18 Message Slot Buffer
The message slot, selected by setting the C0SBS register, is read by reading the message slot buffer. A
message can be written in the message slot selected by the C0SBS register if the message is written to
the message slot buffer.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 349 of 488
22. CAN Module
M32C/83 Group (M32C/83, M32C/83T)
CAN0 Message Slot Buffer i Standard ID0 (i=0,1)(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
C0SLOT0_0, C0SLOT1_0
Bit
Symbol
Address
01E016, 01F016
Bit Name
After Reset
Indeterminate
Function
RW
SID6
Standard ID6
Read or write the standard ID6
in the message slot j (j=0 to 15)
RW
SID7
Standard ID7
Read or write the standard ID7
in the message slot j
RW
SID8
Standard ID8
Read or write the standard ID8
in the message slot j
RW
SID9
Standard ID9
Read or write the standard ID9
in the message slot j
RW
SID10
Standard ID10
Read or write the standard ID10
in the message slot j
RW
Nothing is assigned. When write, set to "0".
(b7 - b5) When read, its content is indeterminate.
NOTES:
1. Select, by setting the C0SBS register, the message slot j to be accessed by the C0SLOTi_0
register.
CAN0 Message Slot Buffer i Standard ID1 (i=0,1)(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
C0SLOT0_1, C0SLOT1_1
Bit
Symbol
Bit Name
Address
01E116, 01F116
After Reset
Indeterminate
Function
RW
SID0
Standard ID0
Read or write the standard ID0
in the message slot j (j=0 to 15)
RW
SID1
Standard ID1
Read or write the standard ID1
in the message slot j
RW
SID2
Standard ID2
Read or write the standard ID2
in the message slot j
RW
SID3
Standard ID3
Read or write the standard ID3
in the message slot j
RW
SID4
Standard ID4
Read or write the standard ID4
in the message slot j
RW
SID5
Standard ID5
Read or write the standard ID5
in the message slot j
RW
Nothing is assigned. When write, set to "0".
(b7 - b6) When read, its content is indeterminate.
NOTES:
1. Select, by setting the C0SBS register, the message slot j to be accessed by the C0SLOTi_0
register.
Figure 22.22 C0SLOT0_0, C0SLOT1_0 Registers and C0SLOT0_1, C0SLOT1_1 Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 350 of 488
22. CAN Module
M32C/83 Group (M32C/83, M32C/83T)
CAN0 Message Slot Buffer i Extended ID0 (i=0,1)(1, 2)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
C0SLOT0_2, C0SLOT1_2
Bit
Symbol
Address
01E216, 01F216
Bit Name
After Reset
Indeterminate
Function
RW
EID14
Extended ID14
Read or write the extended ID14
in the message slot j (j=0 to 15)
RW
EID15
Extended ID15
Read or write the extended ID15
in the message slot j
RW
EID16
Extended ID16
Read or write the extended ID16
in the message slot j
RW
EID17
Extended ID17
Read or write the extended ID17
in the message slot j
RW
Nothing is assigned. When write, set to "0".
(b7 - b4) When read, its content is indeterminate.
NOTES:
1. If the receive slot is standard ID formatted, the EID17 to EID14 bits are indeterminate when the
received data is stored.
2. Select, by setting the C0SBS register, the message slot j to be accessed by the C0SLOTi_2 register.
CAN0 Message Slot Buffer i Extended ID1
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
C0SLOT0_3, C0SLOT1_3
Bit
Symbol
Bit Name
(i=0,1)(1, 2)
Address
01E316, 01F316
After Reset
Indeterminate
Function
RW
EID6
Extended ID6
Read or write the extended ID6
in the message slot j (j=0 to 15)
RW
EID7
Extended ID7
Read or write the extended ID 7
in the message slot j
RW
EID8
Extended ID8
Read or write the extended ID 8
in the message slot j
RW
EID9
Extended ID9
Read or write the extended ID 9
in the message slot j
RW
EID10
Extended ID10
Read or write the extended ID 10
in the message slot j
RW
EID11
Extended ID11
Read or write the extended ID 11
in the message slot j
RW
EID12
Extended ID12
Read or write the extended ID 12
in the message slot j
RW
EID13
Extended ID13
Read or write the extended ID 13
in the message slot j
RW
NOTES:
1. If the receive slot is standard ID formatted, the EID13 to EID6 bits are indeterminate when the received
data is stored.
2. Select, by setting the C0SBS register the message slot j to be accessed by the C0SLOTi_3 register.
Figure 22.23 C0SLOT0_2, C0SLOT1_2 Registers and C0SLOT0_3, C0SLOT1_3 Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 351 of 488
22. CAN Module
M32C/83 Group (M32C/83, M32C/83T)
CAN0 Message Slot Buffer i Extended ID2 (i=0,1)(1, 2)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
After Reset
C0SLOT0_4, C0SLOT1_4
01E416, 01F416
Indeterminate
Bit
Symbol
Bit Name
Function
RW
EID0
Extended ID0
Read or write the extended ID0
in the message slot j (j=0 to 15)
RW
EID1
Extended ID1
Read or write the extended ID1
in the message slot j
RW
EID2
Extended ID2
Read or write the extended ID2
in the message slot j
RW
EID3
Extended ID3
Read or write the extended ID3
in the message slot j
RW
EID4
Extended ID4
Read or write the extended ID4
in the message slot j
RW
EID5
Extended ID5
Read or write the extended ID5
in the message slot j
RW
Nothing is assigned. When write, set to "0".
(b7 - b6) When read, its content is indeterminate.
NOTES:
1. If the receive slot is standard ID formatted, the EID 5 to EID0 bits are indeterminate when received data
is stored.
2. Select, by setting the C0SBS register, the message slot j to be accessed by the C0SLOTi_4 register.
CAN0 Message Slot Buffer i Data Length Code (i=0,1)(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
C0SLOT0_5, C0SLOT1_5
Bit
Symbol
Bit Name
Address
01E516, 01F516
After Reset
Indeterminate
Function
DLC0
RW
RW
DLC1
RW
Data Length Set Bit
Read or write the data length set bit
in the message slot j (j=0 to 15)
DLC2
RW
DLC3
RW
Nothing is assigned. When write, set to "0".
(b7 - b4) When read, its content is indeterminate.
NOTES:
1. Select, by setting the C0SBS register, the message slot j to be accessed by the C0SLOTi_5
register.
Figure 22.24 C0SLOT0_4, C0SLOT1_4 Registers and C0SLOT0_5 and C0SLOT1_5 Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 352 of 488
22. CAN Module
M32C/83 Group (M32C/83, M32C/83T)
CAN0 Message Slot Buffer i Data k (i=0,1 k=0 to 7)(1)
b7
b0
Symbol
Address
After Reset
C0SLOT0_q(q=k+6,k=0 to 3)
C0SLOT0_q(q=k+6,k=4 to 7)
01E616, 01E716, 01E816, 01E916
01EA16, 01EB16, 01EC16, 01ED16
C0SLOT1_q(q=k+6,k=0 to 3)
C0SLOT1_q(q=k+6,k=4 to 7)
01F616, 01F716, 01F816, 01F916
01FA16, 01FB16, 01FC16, 01FD16
Function
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Setting Range
Read or write data k in the message slot j (j=0 to 15) 0016 to FF16
RW
RW
NOTES:
1. Select, by setting the C0SBS register, the data k in the message slot j to be accessed by the
C0SLOTi_q register.
CAN0 Message Slot Buffer i Time Stamp High-Ordered (i=0,1)(1)
b7
b0
Symbol
C0SLOT0_14, C0SLOT1_14
Address
01EE16, 01FE16
Function
Read or write the time stamp high-ordered
in the message slot j (j=0 to 15)
After Reset
Indeterminate
Setting Range
RW
0016 to FF16
RW
NOTES:
1. Select, by setting the COSBS register, the time stamp high-ordered in the message slot j to be
accessed by the C0SLOTi_14 register.
CAN0 Message Slot Buffer i Time Stamp Low-Ordered (i=0,1)(1)
b7
b0
Symbol
C0SLOT0_15, C0SLOT1_15
Address
01EF16, 01FF16
Function
Read or write the time stamp low-ordered
in the message slot j (j=0 to 15)
After Reset
Indeterminate
Setting Range
RW
0016 to FF16
RW
NOTES:
1. Select, by setting the COSBS register, the time stamp low-ordered in the message slot j to be
accessed by the C0SLOTi_15 register.
Figure 22.25 C0SLOT0_6 to C0SLOT0_13, C0SLOT1_6 to C0SLOT1_13, C0SLOT0_14,
C0SLOT1_14, C0SLOT0_15 and C0SLOT1_15 Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 353 of 488
22. CAN Module
M32C/83 Group (M32C/83, M32C/83T)
22.1.19 CAN0 Acceptance Filter Support Register (C0AFS Register)
CAN0 Acceptance Filter Support Register
b15
b8
b7
b0
Symbol
C0AFS
After Reset(1)
010016
Address
024516 - 024416
Function
Generates data to determine a received ID
Setting Range
RW
000016 to FFFF16
RW
NOTES:
1. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited)
and supplying the clock to the CAN module after reset.
b0
b15
Write
SID5 SID4 SID3 SID2 SID1 SID0
SID10 SID9 SID8 SID7 SID6
3-8 decoding
b15
Read
b0
b7
b8
CSID7 CSID6 CSID5 CSID4 CSID3 CSID2 CSID1 CSID0 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3
b7
Top+0016
Data used to search a data table is
generated from a received ID in standard format. The table search with this
data determines whether or not a received ID is valid.
Top+0116
Top+DE16
Top+FE16
Top+FF16
b6
b5
b15
b8
b2
b1
b0
7F716 7F616 7F516 7F416 7F316 7F216 7F116 7F016
"0"
"0"
"0"
"0"
"0"
"0"
"0"
"1"
7FF16 7FE16 7FD16 7FC16 7FB16 7FA16 7F916 7F816
"0"
"0"
"1"
"0"
"0"
"0"
"0"
"0"
Bit search information
b7
b0
SID5 SID4 SID3 SID2 SID1 SID0
SID10SID9 SID8 SID7 SID6
0 0 1 1 0 0 1 1 0 0 0 1 1 0 1 1
SID10
SID0
"6"
Received ID
Divide it to 8 bits and 3 bits
"F"
"3"
1 1 0 1 1 1 1 0 0 1 1
"D"
"E"
"3"
8 bits
b15
Read from
the C0AFS register
b3
6F716 6F616 6F516 6F416 6F316 6F216 6F116 6F016
"0"
"0"
"0"
"0"
"1"
"0"
"0"
"0"
Address search information
Write to
the C0AFS register
b4
00716 00616 00516 00416 00316 00216 00116 00016
"0"
"0"
"0"
"0"
"0"
"0"
"1"
"0"
00F16 00E16 00D16 00C16 00B16 00A16 00916 00816
"1"
"0"
"0"
"0"
"0"
"0"
"0"
"0"
b8
3 bits
b7
b0
0 0 0 0 1 0 0 0 1 1 0 1 1 1 1 0
"0816"
"D"
"E"
Bit search information
Bit search information
b7
0116
0216
0416
0816
1016
2016
4016
8016
0
0
0
0
0
0
0
1
b0
b3
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
Address search information
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
Because the value of
the 3 bits is 3, b3 in the
table on the left is 1.
(If the value of the 3 bits
is 4, b4 in the table in
the left is 1.)
3 low-order bits of received ID
016
116
216
316
416
516
616
716
Figure 22.26 C0AFS Register
The C0AFS register enables prompt performance of the table search to determine the validity of a
received ID. This function is for standard-formatted ID only.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 354 of 488
22. CAN Module
M32C/83 Group (M32C/83, M32C/83T)
22.2 Timing with CAN-Associated Registers
22.2.1 CAN Module Reset Timing
Figure 22.27 shows an operation example of when the CAN module is reset.
(1) The CAN module can be reset when the STATE_RESET bit in the C0STR register is set to "1" (CAN
module reset completed) after the RESET0 and RESET1 bits in the C0CTLR0 register are set to "1"
(CAN module reset).
(2) Set necessary CAN-associated registers.
(3) CAN communication can be established after the STATE_RESET bit is set to "0" (resetting) after
the RESET0 and RESET1 bits are set to "0" (CAN module reset exited) .
Set to "1" by program
simultaneously
Set to "0" by program
simultaneously
"1"
RESET0 bit
"0"
"1"
RESET1 bit
"0"
STATE_RESET bit
"1"
"0"
CAN operation
CAN counfiguration
Verify the STATE_RESET bit
Verify the STATE_RESET bit
Operation (1)
Operation (2)
Operation (3)
Figure 22.27 Example of CAN Module Reset Operation
22.2.2 CAN Transmit Timing
Figure 22.28 shows an operation example of when the CAN transmits a frame.
(1) When the TRMREQ bit is set to "1" (request to transmit the data frame) while the CAN bus is in as
idle state, the TRMACTIVE bit in the C0MCTLi register (i=0 to 15) is set to "1" (during transmission) and the TRMSTATE bit in the C0STR register is set to "1" (during transmission). The CAN
starts transmitting the frame.
(2) After a CAN frame transmission is completed, the SENTDATA bit in the C0MCTLi register is set to "1"
(already transmitted), the TRMSUCC bit in the C0STR register to "1" (transmission completed) and
the SISi bit in the C0SISTR register to "1" (interrupt requested). The MBOX3 to MBOX0 bits in the
C0STR register store transmitted message slot numbers.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 355 of 488
22. CAN Module
M32C/83 Group (M32C/83, M32C/83T)
Start transmtting
Transmission completed
(1)
CAN bus
Bus idle
(2)
Transmit frame
Intermission field
Bus idle
Transmit frame
"1"
SENTDATA bit
"0"
TRMACTIVE bit
"1"
Set to "1" by program
simultaneously
"0"
"1"
TRMREQ bit
Transmission-completed
message slot number
"0"
MBOX3 MBOX0 bits
"1"
TRMSUCC bit
"0"
TRMSTATE bit
"1"
"0"
"1"
SISi bit
"0"
i = 0 to 15
Figure 22.28 Example of CAN Data Frame Transmit Operation
22.2.3 CAN Receive Timing
Figure 22.29 shows an operation example of when the CAN receives a frame.
(1) When the RECREQ bit in the C0MCTLi register (i=0 to 15) is set to "1" (receive requested), the
CAN is ready to receive the frame at anytime.
(2) When the CAN starts receiving the frame, the RECSTATE bit in the C0STR register is set to "1"
(during reception).
(3) After the CAN frame reception is completed, the INVALDTA bit in the C0MCTLi register is set to
"1" (storing received data), the NEWDATA bit in the C0MCTLi register is set to "1" (receive complete) and the RECSUCC bit in the C0STR register is set to "1" (reception completed).
(4) After data is written to the message slot, the INVALDATA bit is set to "0" (stops receiving) and the
SISi bit is set to "1" (interrupt requested). The MBOX3 to MBOX0 bits store received message slot
numbers.
Start receiving
(1)
CAN bus
Bus idle
NEWDATA bit
"1"
INVALDATA bit
"1"
RECREQ bit
"1"
(3)
Receive frame
Receive frame
(4)
Bus idle
"0"
"0"
"0"
Set to "1" by program
simultaneously
MBOX3 MBOX0 bits
RECSUCC bit
"1"
RECSTATE bit
"1"
SISi bit
"1"
"0"
"0"
"0"
i = 0 to 15
Figure 22.29 Example of CAN Data Frame Receive Operation
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Intermission field
Reception completed
(2)
Page 356 of 488
Reception-completed
message slot number
22. CAN Module
M32C/83 Group (M32C/83, M32C/83T)
22.2.4 CAN Bus Error Timing
Figure 22.30 shows an operation example of when a CAN bus error occurs.
(1) When a CAN bus error is detected, the STATE_BUSERROR bit in the CiSTR register is set to "1",
(error occurred) and the BEIS bit in the CiEISTR register is set to "1" (interrupt requested). The
CAN starts transmitting the error frame.
Error detected
(1)
CAN bus
STATE_BUSERROR
bit
Transmit / receive frame
Error frame
"1"
"0"
"1"
BEIS bit
"0"
Figure 22.30 Operation Timing when CAN Bus Error Occurs
22.3 CAN Interrupts
The CANj interrupt (j=0 to 2) is provided as the CAN interrupt. Figure 22.31 shows a block diagram of the
CAN interrupt.
The following factors cause the CAN-associated interrupt request to be generated.
- The CAN0 slot i (i=0 to 15) completes a transmission
- The CAN0 slot i completes a reception
- The CAN0 module detects a bus error
- The CAN0 module moves into an error-passive state
- The CAN0 module moves into a bus-off state
The CANj interrupt, caused by one of the CANi interrupt request factors listed above, is generated via
the OR circuit.
If an interrupt request factor is established, the corresponding bit in the C0SISTR register is set to "1"
(interrupt requested) when the CAN0 slot k completes a transmission or a reception. The corresponding
bit in the C0EISTR register is set to "1" (interrupt requested) when the CANi module detects a bus error,
moves into an error-passive state, or moves into a bus-off state.
The CAN0 interrupt request signal is set to "1" when the corresponding bit in the C0SISTR or C0EISTR
is set to "1" and the corresponding bit in the C0SIMKR or C0EIMKR is set to "1".
When the CAN0 interrupt request signal changes from "0" to "1", all CANjR bits in the IIO9IR to IIO11IR
registers are set to "1" (interrupt requested).
If at least one of the CANjE bits in the IIO9IE to IIO11IE registers is set to "1" (interrupt enabled), the IR
bits in the corresponding CANjIC registers are set to "1" (interrupt requested). The CAN0 interrupt
request signal remains set to "1" if another interrupt request causes a corresponding bit in the C0SISTR
or C0EISTR to be set to "1" and the corresponding bit in the C0SIMKR or C0EIMKR to be set to "1" after
the CAN0 interrupt request signal changes "0" to "1". The CANjR and IR bits also remain unchanged.
Bits in the C0SISTR or C0EISTR register and CANjR bits (j=0 to 2) in the IIO9IR to IIO11IR registers are
not set to "0" automatically, interrupt acknowledgment notwithstanding. Set these bits to "0" by program.
The CANi interrupts are acknowledged when the CANjR bit in the IIO9IR to IIO11IR register and the
corresponding bit in the C0SISTR or C0EISTR register, which are set to enable interrupts though setting
the C0SIMKR or C0EIMKR register, are set to "0". If these bits remain set to "1", all CAN-associated
interrupt request factors become invalid.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 357 of 488
22. CAN Module
M32C/83 Group (M32C/83, M32C/83T)
CAN0 slot 0 received
SIS0 bit
CAN0 slot 0 transmitted
SIM0 bit
•
•
•
•
•
CAN0 interrupt
request signal
CAN0R bit in
IIO9IR register
CAN0(request)
CAN0E bit in
IIO9IE register
CAN1R bit in
IIO10IR register
CAN1E bit in
IIO10IE register
SIS15 bit
CAN1(enable)
SIM15 bit
CAN2R bit in
IIO11IR register
BEIS bit
CAN2E bit in
IIO11IE register
BEIM bit
CAN0 transition into
error-passive state
EPIS bit
EPIM bit
CAN0 transition into
bus-off state
BOIS bit
BOIM bit
Figure 22.31 CAN Interrupts
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
IR bit in CAN1IC
register
CAN1(request)
CAN2(request)
CAN0 bus error detection
IR bit in CAN0IC
register
CAN0(enable)
CAN0 slot15 received
CAN0 slot15 transmitted
•
•
•
Page 358 of 488
CAN2(enable)
IR bit in CAN2IC
register
M32C/83 Group (M32C/83, M32C/83T)
23. DRAMC
23. DRAMC
The DRAM controller (DRAMC) controls the DRAM area, which ranges from 512 Kbytes to 8 Mbytes. Table
23.1 lists specifications of the DRAMC.
Table 23.1 DRAMC Specifications
Item
Specification
DRAM Area
512 KB, 1 MB, 2 MB, 4 MB, 8 MB
Bus Control
2CAS/1W
________
Refresh
________
CAS-before-RAS refresh, Self refresh
Supported Function Mode EDO, fast page mode
Wait State Insertion
1-wait state, 2-wait state
Table 23.2 shows pins associated with DRAMC. Signals listed in Table 23.2 are output by setting the AR2
______
to AR0 bits in the DRAMCONT register for the DRAM area and accessing DRAM. See Table 7.9 for RAS,
________
________
_____
CASL, CASH and DW signal operations. Figure 23.1 shows the DRAMCONT register and REFCNT register.
Table 23.2 DRAMC-associated Pins
Bus for Device Access except DRAM(1)
Port
Bus for DRAM Access
P0
D0 to D7
D0 to D7
P1
D8 to D15
D8 to D15(2)
P3
A8 to D15
MA0 to MA7
P40 to P44
A16 to A20
MA8 to MA12
_______
_____
_________
P50
WRL / WR
CASL
_______
_________
P51
WRH / BHE
CASH
____
_____
P52
RD
DW
P56
ALE
RAS
________
_______
NOTES:
1. This is an example of the separate bus and 16-bit data bus.
2. This bus is available when the DS2 bit in the DS register is set to "1" (16-bit data bus) and the PM02 bit
____ _______ _______
in the PM0 register is set to "1" (RD/WRL/WRH in R/W mode).
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 359 of 488
M32C/83 Group (M32C/83, M32C/83T)
23. DRAMC
DRAM Control Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
DRAMCONT
Bit
Symbol
WT
Address
004016
After Reset
Indeterminate(1)
Bit Name
Wait Select Bit(2)
Function
0 : 2-wait state
1 : 1-wait state
RW
RW
b3 b2 b1
AR0
AR1
DRAM Area Select Bit
AR2
0 0 0 : Disables DRAM
0 0 1 : Do not set to this value
0 1 0 : 512KB
0 1 1 : 1MB
1 0 0 : 2MB
1 0 1 : 4MB
1 1 0 : 8MB
1 1 1 : Do not set to this value
RW
RW
RW
Nothing is assigned. When write, set to "0".
(b6 - b4) When read, its content is indeterminate.
SREF
Self-refresh Mode Bit(3)
0 : Self-refresh is off
1 : Self-refresh is on
RW
Notes:
1. Contents of the DRAMCONT register is indeterminate. DRAMC starts operation when this register
is written to.
2. Bus cycle with two waits is 3-2-2.... It is 2-1-1... with one wait.
3. Refer to 23.2.2 Self-refresh for SREF bit setup procedure.
When the SREF bit is set to "1", both RAS and CAS output "L". When any external device,
excluding DRAM, is attached, the WR signal is "L".
4. The DS register determines the data bus width . CASH is indeterminate when the 8-bit data bus is
selected.
DRAM Refresh Interval Set Register
b7
b0
Symbol
REFCNT
Address
004116
After Reset
Indeterminate
Function
If setting value is n,
Refresh interval = CPU clock cycle X (n + 1) X 32
Figure 23.1 DRAMCONT Register and REFCNT Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 360 of 488
Setting Range
RW
0016 to FF16
RW
M32C/83 Group (M32C/83, M32C/83T)
23. DRAMC
DRAMC is not available when the PM11 to PM10 bits in the PM1 register are set to "112" (mode 3). Set the
PM11 to PM10 bits to "002," "012" or "102" (mode 0 to 2). When the 16-bit DRAM data bus is selected, set
____ ________ ________
the PM02 bit in the PM0 register to "1" (RD/WRH/WRL).
Required wait time between DRAM power-on and memory operation, and necessary processing of dummy
cycle for refresh varies with externally attached DRAM specifications.
23.1 DRAMC Multiplexed Address Output
DRAMC outputs signals, which are multiplexed row addresses and column addresses, to address bus A8 to
A20. Figure 23.2 shows an output format for multiplexed addresses.
23.2 Refresh
23.2.1 Refresh
_______
_______
Refresh method is the CAS-before-RAS refresh. The REFCNT register controls the refresh interval. Refresh signals are not output in a hold state.
The setting value of the REFCNT register is obtained as follows:
The value of the REFCNT register (0016 to FF16) = refresh interval time / (CPU clock frequency X 32) - 1
23.2.2 Self-Refresh
The refresh signal described in 23.2.1 stops while the CPU stops in stop mode, etc. The DRAM selfrefresh function can be activated by setting the self-refresh before the CPU stops. Setting and cancellation procedures for the self-refresh are as follows:
(1) Setting self-refresh (with 1 wait state, 4 Mbytes)
•••
mov.b #00000001b,DRAMCONT
;Set the AR2 to AR0 bits to "0002" (DRAM disabled)
mov.b #10001011b,DRAMCONT
;Set the AR2 to AR0 bits again and the SREF bit to "1"
(self-refresh on) simultaneously
nop
nop
•••
;Execute the nop instruction twice
;
(2) Cancellation of self-refresh (with 1 wait state, 4M bytes)
•••
mov.b #00000001b,DRAMCONT
;Set the AR2 to 0 bits to "0002" (self-refresh cancellation)
and the SREF bit to "0" (DRAM disabled) simultaneously
mov.b #00001011b,DRAMCONT
;Set the AR2 to AR0 bits again
mov.b 400h, 400h
;DRAM access is disabled immediately after cancellation.
This is an example of a dummy read operation.
•••
_______
_______
Both RAS and CAS are held "L" during self-refresh. When devices other than DRAM are attached, the
______
_____
WR signal is held "L". Take procedures such as applying an "H" signal to the CS.
Figures 23.3 to 23.5 show bus timings during DRAM access.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 361 of 488
M32C/83 Group (M32C/83, M32C/83T)
23. DRAMC
(1) In 8-bit Bus Mode
Pin Function
MA12 MA11 MA10 MA9
(A20) (A19) (A18) (A17)
Row Address
(A20)
MA8
(A16)
MA7
(A15)
MA6
(A14)
MA5
(A13)
MA4
(A12)
MA3
(A11)
MA2
(A10)
MA1
(A9)
MA0
(A8)
(A19)
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
–
Column Address (A22) (A22)
A19
A8
A7
A6
A5
A4
A3
A2
A1
A0
–
Address used for 512K-byte and 1M-byte DRAM area
(A20)
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
–
Column Address (A22)
A21
A20
A8
A7
A6
A5
A4
A3
A2
A1
A0
–
Row Address
Address used for 2M-byte and 4M-byte DRAM area
Row Address
A20
Column Address (A22)
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
–
A22
A21
A8
A7
A6
A5
A4
A3
A2
A1
A0
–
Address used for 8M-byte DRAM area
(2) In 16-bit Bus Mode
Pin Function
MA12 MA11 MA10
(A20) (A19) (A18)
Row Address
(A20)
(A19)
Column Address (A22) (A20)
MA9
(A17)
MA8
(A16)
MA7
(A15)
MA6
(A14)
MA5
(A13)
MA4
(A12)
MA3
(A11)
MA2
(A10)
MA1
(A9)
MA0
(A8)
A18
A17
A16
A15
A14
A13
A12
A11
A10
(A9)
–
A9
A8
A7
A6
A5
A4
A3
A2
A1
(A0)
–
Address used for 512K-byte DRAM area
(A20)
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
(A9)
–
Column Address (A22)
A20
A9
A8
A7
A6
A5
A4
A3
A2
A1
(A0)
–
Row Address
Address used for 1M-byte and 2M-byte DRAM area
Row Address
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
(A9)
–
Column Address
A22
A21
A9
A8
A7
A6
A5
A4
A3
A2
A1
(A0)
–
Address used for 4M-byte and
8M-byte(1) DRAM
area
( ): disabled bits,
:bits which output addresses changed by data bus width and the
DRAM area
–: indetermimate
NOTES:
1. The above applies when using a 4Mx1 or 4Mx4 memory configuration. When using a 4Mx16
configuration, implement the following combinations:
For row addresses, MA0 to MA12; for column addresses, MA2 to MA8, MA11 and MA12.
Or for row addresses, MA1 to MA12; for column addresses, MA2 to MA9, MA11 and MA12.
Figure 23.2 Multiplexed Address Output Pattern
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 362 of 488
M32C/83 Group (M32C/83, M32C/83T)
23. DRAMC
(1) Read cycle (WT bit = 0 with 2 wait states)
BCLK
Row
address
MA0 to MA12
Column
address 1
Column
address 2
Column
address 3
RAS
CASH
CASL
'H'
DW
D0 to D15
(EDO mode)
NOTES:
1. With an 8-bit data bus, only CASL outputs a data enabled to read. CASH outputs an indeterminate data.
(2) Write cycle (WT bit = 0)
BCLK
MA0 to MA12
Row
address
Column
address 1
Column
address 2
Column
address 3
RAS
CASH
CASL
DW
D0 to D15
NOTES:
1. With an 8-bit data bus, only CASL outputs data enabled to read. CASH outputs an indeterminate data.
Figure 23.3 Bus Timing during DRAM Access (1)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 363 of 488
M32C/83 Group (M32C/83, M32C/83T)
23. DRAMC
(1) Read cycle (WT bit = 1 with 1 wait state)
BCLK
Row
address
MA0 to MA12
Column
address 1
Column
address 2
Column
address 3
Column
address 4
RAS
CASH
CASL
'H'
DW
D0 to D15
(EDO mode)
NOTES:
1. With an 8-bit data bus, only CASL outputs a data enabled to read. CASH outputs an indeterminate data.
(2) Write cycle (WT bit = 1)
BCLK
MA0 to MA12
Row
address
Column
address 1
Column
address 2
Column
address 3
Column
address 4
RAS
CASH
CASL
DW
D0 to D15
NOTES:
1. With an 8-bit data bus, only CASL outputs a data enabled to read. CASH outputs an indeterminate data.
Figure 23.4 Bus Timing during DRAM Access (2)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 364 of 488
M32C/83 Group (M32C/83, M32C/83T)
(1) CAS-before-RAS refresh cycle
BCLK
RAS
CASH
CASL
"H"
DW
NOTES:
1. With an 8-bit data bus, only CASL outputs a data enabled to read.
CASH outputs an indeterminate data.
(1) Self-Refresh cycle
BCLK
RAS
CASH
CASL
"H"
DW
NOTES:
1. With an 8-bit data bus, only CASL outputs a data enabled to read.
CASH outputs an indeterminate data.
Figure 23.5 Bus Timing during DRAM Access (3)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 365 of 488
23. DRAMC
M32C/83 Group (M32C/83, M32C/83T)
24. Programmable I/O Port
24. Programmable I/O Ports
87 programmable I/O ports from P0 to P10 (excluding P85) are available in the 100-pin package and 123
programmable I/O ports from P0 to P15 (excluding P85) are in the 144-pin package. The direction registers
determine each port status, input or output. The pull-up control registers determine whether the ports,
divided into groups of four ports, are pulled up or not. P85 is an input port and no pull-up for this port is
______
______
allowed. The P8_5 bit in the P8 register indicates an NMI input level since P85 shares pins with NMI.
Figures 24.1 to 24.4 show programmable I/O port configurations.
Each pin functions as the programmable I/O port, an I/O pin for internal peripheral functions or the bus
control pin.
To use the pins as input or output pins for internal peripheral functions, refer to the explanations for each
function. Refer to 7. Bus when used as the bus control pin.
The registers, described below, are associated with the programmable I/O ports.
24.1 Port Pi Direction Register (PDi Register, i=0 to 15)
Figure 24.5 shows the PDi register.
The PDi register selects input or output status of a programmable I/O port. Each bit in the PDi register
corresponds to a port.
_____
In memory expansion and microprocessor mode, pins being used as bus control pins (A0 to A22, A23, D0 to
_______
_______ ________ ______ _________
________ _______ _____ ______
_________
D15, MA0 to MA12, CS0 to CS3, WRL/WR/CASL, WRH/BHE, RD/DW, BCLK/ALE/CLKOUT, HLDA/ALE,
_________
_______
_______
HOLD, ALE/RAS, and RDY) cannot be controlled by the PDi register. No bits controlling P85 are provided
in the direction registers .
24.2 Port Pi Register (Pi Register, i=0 to 15)
Figure 24.6 shows the Pi register.
The Pi register writes and reads data to communicate with external devices. The Pi register consists of a
port latch to hold output data and a circuit to read pin states. Each bit in the Pi register corresponds to a port.
_____
In memory expansion and microprocessor mode, pins being used as bus control pins (A0 to A22, A23, D0 to
_______
_______ ________ ______ _________
________ _______ _____ ______
_________
D15, MA0 to MA12, CS0 to CS3, WRL/WR/CASL, WRH/BHE, RD/DW, BCLK/ALE/CLKOUT, HLDA/ALE,
_________
_______
_______
HOLD, ALE/RAS, and RDY) cannot be controlled by the Pi register.
24.3 Function Select Register Aj (PSj Register) (j=0 to 3, 5 to 9)
Figures 24.7 to 24.11 show the PSj registers.
The PSj register selects either I/O port or peripheral function output if an I/O port shares pins with a peripheral function output (excluding DA0 and DA1.)
Tables 24.3 to 24.12 list peripheral function output control settings for each pin.
When multiple peripheral function outputs are assigned to a pin, set the PSLk (k=0 to 3) and PSC registers
to select which function is used.
24.4 Function Select Register Bk (PSLk Register) (k=0 to 3)
Figures 24.12 and 24.13 show the PSL0 to PSL3 registers.
When multiple peripheral function outputs are assigned to a pin, the PSL0 to PSL3 registers select which
peripheral function output is used.
Refer to 24.9 Analog Input and Other Peripheral Function Input for the PSL3_3 to PSL3_6 bits in the
PSL3 register.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 366 of 488
M32C/83 Group (M32C/83, M32C/83T)
24. Programmable I/O Port
24.5 Function Select Register C (PSC Register)
Figure 24.14 show the PSC register.
When multiple peripheral function outputs are assigned to a pin, the PSC register select which peripheral
function output is used.
Refer to 24.9 Analog Input and Other Peripheral Function Input for the PSC_7 bit in the PSC register.
24.6 Pull-up Control Register 0 to 4 (PUR0 to PUR4 Registers)
Figures 24.15 to 24.16 show the PUR0 to PUR4 registers.
The PUR0 to PUR4 registers select whether the ports, divided into groups of four ports, are pulled up or not.
Ports with bits in the PUR0 to PUR4 registers set to "1" (pull-up) and the direction registers set to "0" (input
mode) are pulled up.
Set bits in the PUR0 and PUR1 registers which control P0 to P5, running as bus, to "0" (no pull-up) in
memory expansion and microprocessor mode. P0, P1, P40 to P43 can be pulled up when they are used as
input ports in memory expansion mode and microprocessor mode.
24.7 Port Control Register (PCR Register)
Figure 24.17 shows the PCR register.
The PCR register selects either CMOS output or N-channel open drain output as the P1 output format. If
the PCR0 bits is set to "1" (N-channel open drain output), N-channel open drain output is selected because
the P-channel in the CMOS port is turned off. This is, however, not a perfect open drain. Therefore, the
absolute maximum rating of the input voltage is from -0.3V to Vcc + 0.3V.
If P1 is used as the data bus in memory expansion and microprocessor mode, set the PCR0 bit to "0"
(CMOS output). If P1 is used as a port in memory expansion and microprocessor mode, the PCR0 bit
determines the output format.
24.8 Input Function Select Register (IPS Register)
Figure 24.18 shows the IPS registers.
The IPS0 to IPS1 and IPS3 bits in the IPS register and the IPSA_0 and IPSA_3 bits in the IPSA register
select which pin is assigned the intelligent I/O or CAN input functions.
Refer to 24.9 Analog Input and Other Peripheral Function Input for the IPS2 bit.
24.9 Analog Input and Other Peripheral Function Input
The PSL3_3 to PSL3_6 bits in the PSL3 register, the PSC_7 bit in the PSC register and the IPS2 bit in the
IPS register each separate analog I/O ports from other peripheral functions. Setting the corresponding bit to
"1" (analog I/O) to use the analog I/O port (DA0, DA1, ANEX0, ANEX1, AN4 to AN7 or AN150 to AN157)
prevents an intermediate potential from being impressed to other peripheral functions. The impressed intermediate potential may cause increase in power consumption.
Set the corresponding bit to "0" (except analog I/O) when analog I/O is not used. All peripheral function
inputs except the analog I/O port are available when the corresponding bit is set to "0". These inputs are
indeterminate when the bit is set to "1". When the PSC_7 bit is set to "1", key input interrupt request remains
_____
_____
unchanged regardless of KI0 to KI3 pin input level change.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 367 of 488
24. Programmable I/O Port
M32C/83 Group (M32C/83, M32C/83T)
Programmable I/O Ports
Select Pull-Up
Direction Register
Port Latch
Data Bus
A
Input to each
Peripheral Function
B
C
Analog Signal
Option
Port
(A)
Hysteresis
Circuit (B)
Peripheral Function
Input
P00 to P07
P20 to P27
P30 to P37
P40 to P47
P50 to P52
P54
P55
P56
P57
P83, P84
P86
P87
P100 to P103
P104 to P107
P114
P144 to P146
(Note 1)
P152, P153
P156, P157
: Available,
: Not available
NOTES:
1. These ports are provided in the 144-pin package only.
Figure 24.1 Programmable I/O Ports (1)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 368 of 488
Circuit (C)
Analog I/F
24. Programmable I/O Port
M32C/83 Group (M32C/83, M32C/83T)
Programmable I/O Ports with the Port Control Register
Select Pull-Up
Direction Register
PCR Register
Port Latch
Data Bus
A
Input to each
Peripheral Function
Option
Port
B
(A)
Hysteresis
Circuit (B)
Peripheral Function
Input
P10 to P14
P15 to P17
: Available,
: Not available
Programmable I/O Ports with the Function Select Register
INV03
Write Signal to INV03
D
Value written to INV03
T
Q
R
RESET
NMI
INV05
INV02
Select Pull-up
PS1 and PS2
Registers
Direction Register
Output from each
Peripheral Function
Data Bus
Port Latch
Input to each
Peripheral Function
Port : P72, P73, P74, P75, P80, P81
Figure 24.2 Programmable I/O Ports (2)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 369 of 488
24. Programmable I/O Port
M32C/83 Group (M32C/83, M32C/83T)
Programmable I/O Ports with the Function Select Register
Select Pull-Up
D
PS0 to PS9
Register
Direction Register
Output from each
Peripheral Function
Data Bus
Port Latch
A
Input to each
Peripheral Function
B
C
Analog Signal
Option
Port
(A)
Hysteresis
Circuit (B)
Peripheral Function
Input
P53
P60 to P67
(Note 1)
P70, P71
P76, P77
P82
P90 to P92
P93 to P96
P97
P110
P111, P112
P113
P120
P121, P122
P123 to P127
P130 to P134
(Note 2)
P135, P136
P137
P140, P141
P142, P143
P150, P151
P154, P155
: Available,
: Not available
NOTES:
1. P70 and P71 are ports for the N-channel open drain output.
2. These ports are provided in the 144-pin package only.
Figure 24.3 Programmable I/O Ports (3)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 370 of 488
Circuit (C)
Analog I/F
Circuit (D)
24. Programmable I/O Port
M32C/83 Group (M32C/83, M32C/83T)
Input Port (P85)
Data Bus
NMI
Figure 24.4 Programmable I/O Ports (4)
Port Pi Direction Register
b7
b6
b5
b4
b3
b2
b1
(i=0 to 15)
(2)
b0
Symbol
PD0 to PD3
PD4 to PD7
PD8
PD9 to PD10
PD11
PD12 to PD13
PD14
PD15
Bit
Symbol
Address
03E216, 03E316, 03E616, 03E716
03EA16, 03EB16, 03C216, 03C316
03C616(4)
03C716(1), 03CA16
03CB16(3,4)
03CE, 03CF16
03D216(3,4)
03D316(3)
Bit Name
After Reset
0016
0016
00X0 00002
0016
XXX0 00002
0016
X000 00002
0016
Function
RW
PDi_0
Port Pi0 Direction 0 : Input mode (Functions as input port)
Register
1 : Output mode (Functions as output port)
RW
PDi_1
Port Pi1 Direction 0 : Input mode (Functions as input port)
Register
1 : Output mode (Functions as output port)
RW
PDi_2
Port Pi2 Direction 0 : Input mode (Functions as input port)
1 : Output mode (Functions as output port)
Register
RW
PDi_3
Port Pi3 Direction 0 : Input mode (Functions as input port)
1 : Output mode (Functions as output port)
Register
RW
PDi_4
Port Pi4 Direction 0 : Input mode (Functions as input port)
1 : Output mode (Functions as output port)
Register
RW
PDi_5
Port Pi5 Direction 0 : Input mode (Functions as input port)
1 : Output mode (Functions as output port)
Register
RW
PDi_6
Port Pi6 Direction 0 : Input mode (Functions as input port)
1 : Output mode (Functions as output port)
Register
RW
PDi_7
Port Pi7 Direction 0 : Input mode (Functions as input port)
1 : Output mode (Functions as output port)
Register
RW
NOTES:
1. Set the PD9 register immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do
not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the
instruction to set the PD9 register.
2. In memory expansion and microprocessor mode, the direction register of pins being used as bus
control pins (A0 to A22, A23, D0 to D15, MA0 to MA12, CS0 to CS3, WRL/WR/CASL,
WRH/BHE/CASH, RD/DW, BCLK/ALE/CLKOUT, HLDA/ALE, HOLD, ALE/RAS and RDY) cannot be
changed.
3. Set the PD11 to PD15 registers to "FF16" in the 100-pin package.
4. Nothing is assigned to the PD8_5 bit in the PD8 register, the PD11_5 to PD11_7 bits in the PD11
register and the P14_7 bit in the PD14 register. If write, set these bits to "0". When read, their
contents are indeterminate.
Figure 24.5 PD0 to PD15 Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 371 of 488
24. Programmable I/O Port
M32C/83 Group (M32C/83, M32C/83T)
Port Pi Register (i=0 to 15)(1, 2)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
P0 to P5
P6 to P10
Address
03E016, 03E116, 03E416, 03E516, 03E816, 03E916
03C016, 03C116(3), 03C416(4), 03C516, 03C816
P11 to P15
03C916(5), 03CC16, 03CD16, 03D016(5), 03D116
Bit
Symbol
Function
Bit Name
After Reset
Indeterminate
Indeterminate
Indeterminate
RW
Pi_0
Port Pi0 Register
RW
Pi_1
Port Pi1 Register
RW
Pi_2
Port Pi2 Register
Pi_3
Port Pi3 Register
Pi_4
Port Pi4 Register
Pi_5
Port Pi5 Register
RW
Pi_6
Port Pi6 Register
RW
Pi_7
Port Pi7 Register
RW
Pin levels can be read by reading
bits corresponding to programmable RW
ports in input mode.
Pin levels can be controlled by
writing to bits corresponding to
RW
programmable ports in output mode.
0 : "L" level
1 : "H" level
RW
NOTES:
1. In memory expansion and microprocessor mode, the direction register of pins being used as bus
control pins (A0 to A22, A23, D0 to D15, MA0 to MA12, CS0 to CS3, WRL/WR/CASL, WRH/BHE/CASH,
RD/DW, BCLK/ALE/CLKOUT, HLDA/ALE, HOLD, ALE/RAS, and RDY) cannot be changed.
2. The P11 to P15 registers are provided in the 144-pin package only.
3. P70 and P71 are ports for the N-channel open drain output. The pins go into a high-impedance state
when P70 and P71 output a high-level signal ("H").
4. The P85 bit is for read only.
5. Nothing is assigned to the P11_5 to P11_7 bits in the P11 register and the P14_7 bit in the P14
register. If write, set these bits to "0". When read, their contents are indeterminate.
Figure 24.6 P0 to P15 Registers
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 372 of 488
24. Programmable I/O Port
M32C/83 Group (M32C/83, M32C/83T)
Function Select Register A0
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PS0
Bit
Symbol
Address
03B016
Bit Name
After Reset
0016
Function
RW
PS0_0
0 : I/O port
Port P60 Output
Function Select Bit 1 : RTS0
RW
PS0_1
0 : I/O port
Port P61 Output
Function Select Bit 1 : CLK0 output
RW
PS0_2
Port P62 Output
0 : I/O port
Function Select Bit 1 : Selected by the PSL0_2 bit
RW
PS0_3
0 : I/O port
Port P63 Output
Function Select Bit 1 : TXD0/SDA0 output
RW
PS0_4
Port P64 Output
0 : I/O port
Function Select Bit 1 : Selected by the PSL0_4 bit
RW
PS0_5
0 : I/O port
Port P65 Output
Function Select Bit 1 : CLK1 output
RW
PS0_6
Port P66 Output
0 : I/O port
Function Select Bit 1 : Selected by the PSL0_6 bit
RW
PS0_7
0 : I/O port
Port P67 Output
Function Select Bit 1 : TXD1/SDA1 output
RW
Function Select Register A1
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PS1
Bit
Symbol
Address
03B116
Bit Name
Function
RW
PS1_0
Port P70 Output
0 : I/O port
Function Select Bit 1 : Selected by the PSL1_0 bit
RW
PS1_1
0 : I/O port
Port P71 Output
Function Select Bit 1 : Selected by the PSL1_1 bit
RW
PS1_2
Port P72 Output
0 : I/O port
Function Select Bit 1 : Selected by the PSL1_2 bit
RW
PS1_3
Port P73 Output
0 : I/O port
Function Select Bit 1 : Selected by the PSL1_3 bit
RW
PS1_4
Port P74 Output
0 : I/O port
Function Select Bit 1 : Selected by the PSL1_4 bit
RW
PS1_5
Port P75 Output
0 : I/O port
Function Select Bit 1 : Selected by the PSL1_5 bit
RW
PS1_6
Port P76 Output
0 : I/O port
Function Select Bit 1 : Selected by the PSL1_6 bit
RW
PS1_7
Port P77 Output
0 : I/O port
Function Select Bit 1 : OUTC01/ISCLK0 output
RW
Figure 24.7 PS0 Register and PS1 Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
After Reset
0016
Page 373 of 488
24. Programmable I/O Port
M32C/83 Group (M32C/83, M32C/83T)
Function Select Register A2
b7
b6
b5
0 0
b4
b3
b2
b1
b0
0 0
Symbol
Address
PS2
03B416
Bit
Symbol
After Reset
00X0 00002
Bit Name
Function
RW
PS2_0
Port P80 Output
Function Select Bit
0 : I/O port
1 : Selected by the PSL2_0 bit
RW
PS2_1
Port P81 Output
Function Select Bit
0 : I/O port
1 : Selected by the PSL2_1 bit
RW
PS2_2
Port P82 Output
Function Select Bit
0 : I/O port
1 : Selected by the PSL2_2 bit
RW
Reserved Bit
Set to "0"
RW
(b4 - b3)
(b5)
(b7 - b6)
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Reserved Bit
Set to "0"
RW
Function Select Register A3(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PS3
Bit
Symbol
Address
03B516
After Reset
0016
Bit Name
Function
RW
PS3_0
Port P90 Output
Function Select Bit
0 : I/O port
1 : CLK3 output
RW
PS3_1
Port P91 Output
Function Select Bit
0 : I/O port
1 : Selected by the PSL3_1 bit
RW
PS3_2
Port P92 Output
Function Select Bit
0 : I/O port
1 : Selected by the PSL3_2 bit
RW
PS3_3
Port P93 Output
Function Select Bit
0 : I/O port
1 : RTS3
RW
PS3_4
Port P94 Output
Function Select Bit
0 : I/O port
1 : RTS4
RW
PS3_5
Port P95 Output
Function Select Bit
0 : I/O port
1 : CLK4 output
RW
PS3_6
Port P96 Output
Function Select Bit
0 : I/O port
1 : TXD4/SDA4 output
RW
PS3_7
Port P97 Output
Function Select Bit
0 : I/O port
1 : Selected by the PSL3_7 bit
RW
NOTES:
1. Set the PD9 register immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do
not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the
instruction to set the PD9 register.
Figure 24.8 PS2 Register and PS3 Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 374 of 488
24. Programmable I/O Port
M32C/83 Group (M32C/83, M32C/83T)
Function Select Register A5(1)
b7
b6
b5
b4
b3
b2
b1
b0
0
Symbol
Address
PS5
03B916
Bit
Symbol
After Reset
XXX0 00002
Bit Name
Function
RW
PS5_0
Port P110 Output
Function Select Bit
0 : I/O port
1 : OUTC10/ ISTXD1/BE1OUT
RW
PS5_1
Port P111 Output
Function Select Bit
0 : I/O port
1 : OUTC11/ ISCLK1 output
RW
PS5_2
Port P112 Output
Function Select Bit
0 : I/O port
1 : OUTC12
RW
PS5_3
Port P113 Output
Function Select Bit
0 : I/O port
1 : OUTC13
RW
Set to "0"
RW
Reserved Bit
(b4)
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
(b7 - b5)
NOTES:
1. The PS5 register is provided in the 144-pin package only.
Function Select Register A6(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PS6
Bit
Symbol
Address
03BC16
Bit Name
0016
Function
RW
PS6_0
Port P120 Output
0 : I/O port
Function Select Bit 1 : OUTC30/ISTxD3
RW
PS6_1
Port P121 Output
0 : I/O port
Function Select Bit 1 : OUTC31/ISCLK3 output
RW
PS6_2
Port P122 Output
0 : I/O port
Function Select Bit 1 : OUTC32
RW
PS6_3
Port P123 Output
0 : I/O port
Function Select Bit 1 : OUTC33
RW
PS6_4
Port P124 Output
0 : I/O port
Function Select Bit 1 : OUTC34
RW
PS6_5
Port P125 Output
0 : I/O port
Function Select Bit 1 : OUTC35
RW
PS6_6
Port P126 Output
0 : I/O port
Function Select Bit 1 : OUTC36
RW
PS6_7
0 : I/O port
Port P127 Output
Function Select Bit 1 : OUTC37
RW
NOTES:
1. The PS6 register is provided in the 144-pin package only.
Figure 24.9 PS5 Register and PS6 Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
After Reset
Page 375 of 488
24. Programmable I/O Port
M32C/83 Group (M32C/83, M32C/83T)
Function Select Register A7(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PS7
Bit
Symbol
Address
03BD16
After Reset
0016
Bit Name
Function
RW
PS7_0
Port P130 Output 0 : I/O port
Function Select Bit 1 : OUTC24
RW
PS7_1
Port P131 Output 0 : I/O port
Function Select Bit 1 : OUTC25
RW
PS7_2
Port P132 Output 0 : I/O port
Function Select Bit 1 : OUTC26
RW
PS7_3
Port P133 Output 0 : I/O port
Function Select Bit 1 : OUTC23
RW
PS7_4
Port P134 Output 0 : I/O port
Function Select Bit 1 : OUTC20/ISTXD2/IEOUT
RW
PS7_5
Port P135 Output 0 : I/O port
Function Select Bit 1 : OUTC22
RW
PS7_6
Port P136 Output 0 : I/O port
Function Select Bit 1 : OUTC21/ISCLK2 output
RW
PS7_7
Port P137 Output 0 : I/O port
Function Select Bit 1 : OUTC27
RW
NOTES:
1. The PS7 register is provided in the 144-pin package only.
Function Select Register A8(1)
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0
Symbol
PS8
Bit
Symbol
Address
03A016
After Reset
X000 00002
Bit Name
Function
PS8_0
0 : I/O port
Port P140 Output
Function Select Bit 1 : OUTC14
RW
PS8_1
0 : I/O port
Port P141 Output
Function Select Bit 1 : OUTC15
RW
PS8_2
Port P142 Output
0 : I/O port
Function Select Bit 1 : OUTC16
RW
PS8_3
0 : I/O port
Port P143 Output
Function Select Bit 1 : OUTC17
RW
(b6 - b4)
(b7)
Reserved Bit
Set to "0"
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
NOTES:
1: The PS8 register is provided in the 144-pin package only.
Figure 24.10 PS7 Register and PS8 Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 376 of 488
RW
RW
24. Programmable I/O Port
M32C/83 Group (M32C/83, M32C/83T)
Function Select Register A9(1)
b7
b6
b5
b4
0 0
b3
b2
b1
b0
Symbol
PS9
0 0
Bit
Symbol
Address
03A116
After Reset
0016
Bit Name
Function
RW
PS9_0
Port P150 Output 0 : I/O port
Function Select Bit 1 : OUTC00/ ISTXD0/BE0OUT
RW
PS9_1
Port P151 Output 0 : I/O port
Function Select Bit 1 : OUTC01/ ISCLK0 output
RW
Reserved Bit
RW
Set to "0"
(b3 - b2)
PS9_4
Port P154 Output 0 : I/O port
Function Select Bit 1 : OUTC04
RW
PS9_5
Port P155 Output 0 : I/O port
Function Select Bit 1 : OUTC05
RW
Reserved Bit
RW
(b7 - b6)
Set to "0"
NOTES:
1. The PS9 register is provided in the 144-pin package only.
Figure 24.11 PS9 Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 377 of 488
24. Programmable I/O Port
M32C/83 Group (M32C/83, M32C/83T)
Function Select Register B0
b7
b6
0
b5
b4
0
b3
b2
0
b1
b0
Symbol
Address
0
0
PSL0
03B216
Bit
Symbol
After Reset
0016
Bit Name
PSL0_2
RW
Port P62 Output Peripheral 0 : SCL0
Function Select Bit
1 : STXD0
RW
Reserved bit
RW
Set to "0"
(b3)
PSL0_4
(b5)
PSL0_6
(b7)
RW
Set to "0"
Reserved Bit
(b1 - b0)
Function
Port P64 Output Peripheral 0 : RTS1
Function Select Bit
1 : OUTC21/ISCLK2 output
RW
Reserved Bit
Set to "0"
RW
Port P66 Output Peripheral
Function Select Bit
0 : SCL1 output
1 : STXD1
RW
Reserved Bit
Set to "0"
RW
Function Select Register B1
b7
b6
b5
b4
0
b3
b2
b1
b0
Symbol
PSL1
Address
03B316
After Reset
0016
Bit
Symbol
Bit Name
PSL1_0
Port P70 Output Peripheral
Function Select Bit
0 : Selected by the PSC_0 bit
1 : TA0OUT output
RW
PSL1_1
Port P71 Output Peripheral
Function Select Bit
0 : Selected by the PSC_1 bit
1 : STXD2
RW
PSL1_2
Port P72 Output Peripheral
Function Select Bit
0 : Selected by the PSC_2 bit
1 : TA1OUT output
RW
PSL1_3
Port P73 Output Peripheral
Function Select Bit
0 : Selected by the PSC_3 bit
1:V
RW
PSL1_4
Port P74 Output Peripheral
Function Select Bit
0 : Selected by the PSC_4 bit
1:W
RW
PSL1_5
Port P75 Output Peripheral
Function Select Bit
0:W
1 : OUTC12
RW
PSL1_6
Port P76 Output Peripheral
Function Select Bit
0 : Selected by the PSC_6 bit
1 : TA3OUT output
RW
(b7)
Reserved Bit
Function
Set to "0"
RW
RW
NOTES:
1. Set the corresponding PSC_i bit in the PSC register to "0" when setting the PSL1_i bit (i=0 to 4, 6) to "1".
Figure 24.12 PSL0 Register and PSL1 Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 378 of 488
24. Programmable I/O Port
M32C/83 Group (M32C/83, M32C/83T)
Function Select Register B2
b7
b6
b5
b4
b3
0
0
0 0
b2
b1
b0
Symbol
PSL2
Address
03B616
Bit
Symbol
After Reset
00X0 00002
Bit Name
Function
RW
PSL2_0
Port P80 Output Peripheral 0 : TA4OUT output
Function Select Bit
1:U
RW
PSL2_1
Port P81 Output Peripheral 0 : U
Function Select Bit
1 : OUTC30/ISTxD3
RW
PSL2_2
Port P82 Output Peripheral 0 : OUTC32
Function Select Bit
1 : CANOUT
RW
Reserved Bit
RW
(b4 - b3)
Set to "0"
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
(b5)
Reserved Bit
(b7 - b6)
RW
Set to "0"
Function Select Register B3
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PSL3
0
Bit
Symbol
(b0)
Address
03B716
After Reset
0016
Bit Name
Reserved Bit
Function
Set to "0"
RW
RW
PSL3_1
Port P91 Output Peripheral 0 : SCL3 output
Function Select Bit
1 : STxD3
RW
PSL3_2
Port P92 Output Peripheral
Function Select Bit
0 : TxD3/SDA3 output
1 : OUTC20/ISTxD2/IEOUT
RW
PSL3_3
Port P93 Output Peripheral
Function Select Bit
0 : Other than DA0
1 : DA0(1)
RW
PSL3_4
Port P94 Output Peripheral
Function Select Bit
0 : Other than DA1
1 : DA1(1)
RW
PSL3_5
Port P95 Output Peripheral
Function Select Bit
0 : Other than ANEX0
1 : ANEX0(1)
RW
PSL3_6
Port P96 Output Peripheral
Function Select Bit
0 : Other than ANEX1
1 : ANEX1(1)
RW
PSL3_7
Port P97 Output Peripheral 0 : SCL4 output
Function Select Bit
1 : STxD4
RW
NOTES:
1. Although DA0, DA1, ANEX0 and ANEX1 can be used when this bit is set to "0", power consumption
may increase.
Figure 24.13 PSL2 Register and PSL3 Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 379 of 488
24. Programmable I/O Port
M32C/83 Group (M32C/83, M32C/83T)
Function Select Register C
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PSC
Bit
Symbol
Address
03AF16
Bit Name
After Reset
00X0 00002
Function
RW
PSC_0
Port P70 Output Peripheral 0 : TxD2/SDA2 output
Function Select Bit
1 : OUTC20/ISTXD2/IEOUT
RW
PSC_1
Port P71 Output Peripheral 0 : SCL2 output
Function Select Bit
1 : OUTC22
RW
PSC_2
Port P72 Output Peripheral 0 : CLK2 output
Function Select Bit
1:V
RW
PSC_3
Port P73 Output Peripheral 0 : RTS2
Function Select Bit
1 : OUTC10/ISTxD1/BE1OUT
RW
PSC_4
Port P74 Output Peripheral 0 : TA2OUT output
Function Select Bit
1 : OUTC11/ISCLK1 output
RW
(b5)
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
PSC_6
Port P76 Output Peripheral 0 : OUTC00/ISTXD0/BE0OUT
Function Select Bit
1 : CANOUT
RW
PSC_7
Key Input Interrupt Validity
Select Bit
RW
0 : P104 to P107 or KI0 to KI3
1 : AN4 to AN7(1)
NOTES:
1. Set the ILVL2 to ILVL0 bits in the KUPIC register to "0002" (interrupt disabled) when changing the
PSC_7 bit.
Although the AN4 to AN7 pins can be used when this bit is set to "0", power consumption may
increase.
Figure 24.14 PSC Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 380 of 488
24. Programmable I/O Port
M32C/83 Group (M32C/83, M32C/83T)
Pull-Up Control Register 0(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
After Reset
PUR0
03F016
0016
Bit
Symbol
Bit Name
Function
RW
PU00
P00 to P03 Pull-Up
PU01
P04 to P07 Pull-Up
PU02
P10 to P13 Pull-Up
Pull-up setting for corresponding port RW
0 : Not pulled up
RW
1 : Pulled up
RW
PU03
P14 to P17 Pull-Up
RW
PU04
P20 to P23 Pull-Up
RW
PU05
P24 to P27 Pull-Up
RW
PU06
P30 to P33 Pull-Up
RW
PU07
P34 to P37 Pull-Up
RW
NOTES:
1. Set each bit in the PUR0 register to "0" since P0 to P5 operate as the address bus in the
memory expansion mode and microprocessor mode. Pull-up or no pull-up setting can be
selected when using these ports as I/O ports.
Pull-Up Control Register 1(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PUR1
Address
03F116
Bit
Symbol
After Reset
XXXX 00002
Bit Name
Function
RW
PU10
P40 to P43 Pull-Up
PU11
P44 to P47 Pull-Up
PU12
P50 to P53 Pull-Up
Pull-up setting for corresponding port RW
0 : Not pulled up
RW
1 : Pulled up
RW
PU13
P54 to P57 Pull-Up
RW
(b7 - b4)
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
NOTES:
1. Set each bit in the PUR1 register to "0" since P0 to P5 operate as the address bus in the
memory expansion mode and microprocessor mode. Pull-up or no pull-up setting can be
selected when using these ports as I/O ports.
Pull-Up Control Register 2
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PUR2
Bit
Symbol
Address
03DA16
After Reset
0016
Bit Name
Function
Pull-up setting for corresponding port RW
0 : Not pulled up
RW
1 : Pulled up
RW
PU20
P60 to P63 Pull-Up
PU21
P64 to P67 Pull-Up
PU22
P72 to P73 Pull-Up(1)
PU23
P74 to P77 Pull-Up
RW
PU24
P80 to P83 Pull-Up
RW
PU25
P84 to P87 Pull-Up(2)
RW
PU26
P90 to P93 Pull-Up
RW
PU27
P94 to P97 Pull-Up
RW
NOTES:
1. P70 and P71 cannot be pulled up.
2. P85 cannot be pulled up.
Figure 24.15 PUR0 Register, PUR1 Register and PUR2 Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
RW
Page 381 of 488
24. Programmable I/O Port
M32C/83 Group (M32C/83, M32C/83T)
<144-pin package>
Pull-Up Control Register 3
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
After Reset
PUR3
03DB16
0016
Bit
Symbol
Bit Name
Function
Pull-up setting for corresponding port RW
0 : Not pulled up
RW
1 : Pulled up
RW
PU30
P100 to P103 Pull-Up
PU31
P104 to P107 Pull-Up
PU32
P110 to P113 Pull-Up
PU33
P114 Pull-Up
RW
PU34
P120 to P123 Pull-Up
RW
PU35
P124 to P127 Pull-Up
RW
PU36
P130 to P133 Pull-Up
RW
PU37
P134 to P137 Pull-Up
RW
<100-pin package>
Pull-Up Control Register 3
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0 0 0
RW
Symbol
PUR3
Address
03DB16
Bit
Symbol
0016
Bit Name
PU30
P100 to P103 Pull-Up
PU31
P104 to P107 Pull-Up
(b7 - b2)
After Reset
Reserved Bit
Function
RW
Pull-up setting for corresponding port
RW
0 : Not pulled up
1 : Pulled up
RW
Set to "0"
RW
Pull-Up Control Register 4(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
PUR4
03DC16
Bit
Symbol
Bit Name
PU40
P140 to P143 Pull-Up
PU41
P144 to P147 Pull-Up
PU42
P150 to P153 Pull-Up
PU43
P154 to P157 Pull-Up
(b7 - b4)
After Reset
XXXX 00002
Function
Pull-up setting for corresponding port
0 : Not pulled up
1 : Pulled up
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
NOTES:
1. Set the PUR4 register to "0016" in the 100-pin package.
Figure 24.16 PUR3 Register and PUR4 Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 382 of 488
RW
RW
RW
RW
RW
24. Programmable I/O Port
M32C/83 Group (M32C/83, M32C/83T)
Port Control Register(1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PCR
Bit
Symbol
PCR0
Address
03FF16
After Reset
XXXX XXX02
Bit Name
Port P1 Control
Bit
Function
0 : CMOS output as P1 output format
1 : N-channel open drain output(2)
RW
RW
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
(b7 - b1)
NOTES:
1. Set the PUR0 bit to "0" since P1 operates as the data bus in memory expansion mode and
microprocessor mode. When using the ports as I/O ports, CMOS port or N-channel open drain
can be selected.
2. This function is designed, not to make port P1 a full open drain, but to turn off the P channel in the
CMOS port.Absolute maximum rating of the input voltage is from -0.3V to VCC + 0.3V.
Figure 23.17 PCR Register
Input Function Select Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
IPS
Bit
Symbol
Address
017816
After Reset
0016
Bit Name
Function
RW
Group 0 Input Pin
Select Bit 0
Assigns each function of INPC00,
INPC01/ISCLK0 and INPC02/ISRxD0
/BE0IN to the following ports.
RW
0 : P76, P77, P80
1 : P150, P151, P152
IPS1
Group 1 Input Pin
Select Bit 1
Assigns each function of INPC11
/ISCLK1 and INPC12/ISRxD1/BE1IN
to the following ports.
0 : P74, P75
1 : P111, P112
IPS2
Port P15 Input Peripheral 0 : Except AN15(1)
Function Select Bit
1 : AN15
RW
IPS3
CANIN Function
Pin Select Bit
RW
IPS0
0 : P77
1 : P83
RW
b5 b4
IPS4
ISRxD2/IEIN Function
Pin Select Bit
IPS5
0
0
1
1
0
1
0
1
: P71
: P91
: P135
: Do not set to this value
RW
RW
IPS6
ISCLK2 Function
Pin Select Bit
0 : P64
1 : P136
RW
IPS7
ISRxD3 Function
Pin Select Bit
0 : P81, P82
1 : P120, P122
RW
NOTES:
1. Although AN150 to AN157 can be used when the IPS bit is set to "0", the power consumption may
increase.
Figure 24.18 IPS Register
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 383 of 488
M32C/83 Group (M32C/83, M32C/83T)
24. Programmable I/O Port
Table 24.1 Unassigned Pin Settings in Single-chip Mode
Pin Name
P0 to P15
(excluding P85)(1,2,3.4,6)
XOUT(5)
_______
NMI(P85)
Setting
Enter input mode and connect each pin to VSS via a resistor (pull-down);
or enter output mode and leave pins open
Leave pin open
Connect pin to VCC via a resistor (pull-up)
AVCC
Connect pin to VCC
AVSS, VREF, BYTE
Connect pins to VSS
NOTES:
1. P11 to P15 are provided in the 144-pin package only.
2. If the port enters output mode and is left open, it is in input mode before output mode is entered by
program after reset. While the port is in input mode, voltage level on the pins is indeterminate and
power consumption may increase.
Direction register settings may be changed by noise or failure caused by noise. Configure direction
register settings regulary to increase the reliability of the program.
3. Use the shortest possible wiring to connect the microcomputer pins to unassigned pins (within 2 cm).
4. P70 and P71 must output low-level ("L") signals if they are in output mode. They are ports for the Nchannel open drain outputs.
5. When the external clock is applied to the XIN pin, set the pin as written above.
6. In the 100-pin package, set "FF16" in the following addresses, in addition to the above settings:
Addresses 0003CB16, 0003CE16, 0003CF16, 0003D216, 0003D316
Table 24.2 Unassigned Pin Setting in Memory Expansion Mode and Microprocessor Mode
Pin Name
Setting
P6 to P15
Enter input mode and connect each pin to VSS via a resistor (pull-down);
(excluding P85)(1,2,3.4,6) or enter output mode and leave pins open
_________
BHE, ALE, HLDA,
Leave pin open
(5)
XOUT , BCLK
_______
_______ __________
NMI(P85), RDY, HOLD Connect pin to VCC via a resistor (pull-up)
AVCC
Connect pin to VCC
AVSS, VREF
Connect pins to VSS
NOTES:
1. P11 to P15 are provided in the 144-pin package only.
2. If the port enters output mode and is left open, it is in input mode before output mode is entered by
program after reset. While the port is in input mode, voltage level on the pins is indeterminate and
power consumption may increase.
Direction register settings may be changed by noise or failure caused by noise. Configure direction
register settings regulary to increase the reliability of the program.
3. Use the shortest possible wiring to connect the microcomputer pins to unassigned pins (within 2 cm).
4. P70 and P71 must output low-level ("L") signals if they are in output mode. They are ports for the Nchannel open drain outputs.
5. When the external clock is applied to the XIN pin, set the pin as written above.
6. In the 100-pin package, set "FF16" in the following addresses, in addition to the above settings:
Addresses 0003CB16, 0003CE16, 0003CF16, 0003D216, 0003D316
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 384 of 488
24. Programmable I/O Port
M32C/83 Group (M32C/83, M32C/83T)
Microcomputer
Microcomputer
P0 to P15(1) (except for P85)
P6 to P15(1) (except for P85)
(Input mode)
·
·
·
(Input mode)
(Output mode)
(Input mode)
·
·
·
(Input mode)
··
·
(Output mode)
Open
··
·
Open
NMI(P85)
BHE
HLDA
ALE
XOUT
BCLK
NMI(P85)
XOUT
Open
VCC
AVCC
BYTE
VREF
AVCC
AVSS
VREF
VSS
In memory expansion mode or
microprocessor mode
NOTES:
1. P11 to P15 are provided in the 144-pin package only.
2. M32C/83T cannot be used in memory expansion mode and microprocessor mode.
Figure 24.19 Unassigned Pin Handling
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 385 of 488
VCC
HOLD
RDY
AVSS
In single-chip mode
Open
VSS
24. Programmable I/O Port
M32C/83 Group (M32C/83, M32C/83T)
Table 24.3 Port P6 Peripheral Function Output Control
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
PS0 Register
_________ _______
0: P6
0/CTS0/SS0
________
1: RTS0
0: P61/CLK0 (input)
1: CLK0 (output)
0: P62/RxD0/SCL0 (input)
1: Selected by the PSL0 register
0: P63/SRxD0/SDA0 (input)
1: TxD0/SDA0 (output)
_________ _______
0: P64/CTS1/SS1/ISCLK2 (input)
1: Selected by the PSL0 register
0: P65/CLK1(input)
1: CLK1(output)
0: P66/RxD1/SCL1 (input)
1: Selected by the PSL0 register
0: P67/SRxD1/SDA1 (input)
1: TxD1/SDA1 (output)
PSL0 Register
Set to "0"
Set to "0"
0: SCL0 (output)
1: STxD0
Set to "0"
________
0: RTS1
1: OUT21/ISCLK2(output)
Set to "0"
0: SCL1(output)
1: STxD1
Set to "0"
Table 24.4 Port P7 Peripheral Function Output Control
PS1 Register
Bit 0 0: P70/SRxD2/TA0OUT(input)/ SDA2(input)
1: Selected by the PSL1 register
Bit 1 0: P71/TB5IN/TA0IN/RxD2/ISRxD2/IEIN/
SCL2(input)
1: Selected by the PSL1 register
Bit 2 0: P72/TA1OUT(input)/CLK2(input)
1: Selected by the PSL1 register
_________ ______
Bit 3 0: P73/TA1IN/CTS2/SS2
1: Selected by the PSL1 register
Bit 4 0: P74/INPC11/ISCLK1(input)/TA2OUT(input)
1: Selected by the PSL1 register
Bit 5 0: P75/TA2IN/INPC12/ISRxD1/BE1IN
1: Selected by the PSL1 register
Bit 6 0: P76/INPC00/TA3OUT(input)
1: Selected by the PSL1 register
Bit 7 0: P77/TA3IN/CANIN/ISCLK0(input)/INPC01
1: OUTC01/ISCLK0(output)
PSL1 Register
0: Selected by the PSC register
1: TA0OUT(output)
0: Selected by the PSC register
PSC Register(1)
0: TxD2/SDA2(output)
1: OUTC20/ISTxD2/IEOUT
0: SCL2(output)
1: STxD2
0: Selected by the PSC register
1: TA1OUT(output)
0: Selected
by the PSC register
__
1: V
0: Selected by the PSC register
1: W
___
0: W
1: OUTC12
0: Selected by the PSC register
1: TA3OUT(output)
Set to "0"
1: OUTC22
0: CLK2(output)
1: V
_________
0: RTS2
1: OUTC10/ISTxD1/BE1OUT
0: TA2OUT(output)
1: OUTC11/ISCLK1(output)
Set to "0"
0: OUTC00/ISTxD0/BE0OUT
1: CAN0OUT
_____
_____
0: P104 to P107 or KI0 to KI3
1: AN4 to AN7
(No relation to P77)
NOTES:
1. Set the corresponding PSC_i bit to "0" when setting the PSL1_i bit (i=0 to 4, 6) to "1".
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 386 of 488
24. Programmable I/O Port
M32C/83 Group (M32C/83, M32C/83T)
Table 24.5 Port P8 Peripheral Function Output Control
PS2 Register
0: P80/INPC02/ISRxD0/BE0OUT/TA4OUT(input)
1: Selected by the PSL2 register
Bit 1
0: P81/TA4IN
1: Selected
by the PSL2 register
________
Bit 2
0: P82/INT0/ISRxD3
1: Selected by the PSL2 register
Bit 3 to 7 Set to "0"
Bit 0
PSL2 Register
0: TA4OUT(output)
1: ___
U
0: U
1: OUTC32/ISTxD3
0: OUTC32
1: CANOUT
Table 24.6 Port P9 Peripheral Function Output Control
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
PS3 Register
0: P90/TB0IN/CLK3(input)
1: CLK3(output)
0: P91/TB1IN/RxD3/ISRxD2/SCL3(input)/IEIN
1: Selected by the PSL3 register
0: P92/TB2IN/SRxD3/SDA3(input)
1: Selected by_______
the PSL3
register
_______
0: P9
3/TB3IN/CTS3/SS3/DA0(output)
________
1: RTS3
________ ______
0: P9
4/TB4IN/CTS4/SS4/DA1(output)
________
1: RTS4
0: P95/ANEX0/CLK4(input)
1: CLK4(output)
0: P96/SRxD4/ANEX1/SDA4(input)
1: TxD4/SDA4(output)
__________
0: P97/RxD4/ADTRG/SCL4(input)
1: Selected by the PSL3 register
PSL3 Register
Set to "0"
0: SCL3(output)
1: STxD3
0: TxD3/SDA3(output)
1: OUTC20/ISTxD2/IEIN
0: Except DA0
1: DA0
0: Except DA1
1: DA1
0: Except ANEX0
1: ANEX0
0: Except ANEX1
1: ANEX1
0: SCL4(output)
1: STxD4
Table 24.7 Port P10 Peripheral Function Output Control
Bit 7
PSC Register
_____
_____
0: P104 to P107 or KI0 to KI3
1: AN4 to AN7
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 387 of 488
M32C/83 Group (M32C/83, M32C/83T)
Table 24.8 Port P11 Peripheral Function Output Control
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4 to 7
PS5 Register
0: P110
1: OUTC10/ISTxD1/BE1OUT
0: P111/INPC11/ISCLK1(input)
1: OUTC11/ISCLK1(output)
0: P112/INPC12/ISRxD1/BE1IN
1: OUTC12
0: P113
1: OUTC13
Set to "0"
Table 24.9 Port P12 Peripheral Function Output Control
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
PS6 Register
0: P120
1: OUTC30/ISTxD3
0: P121/ISCLK3(input)
1: OUTC31/ISCLK3(output)
0: P122/ISRxD3
1: OUTC32
0: P123
1: OUTC33
0: P124
1: OUTC34
0: P125
1: OUTC35
0: P126
1: OUTC36
0: P127
1: OUTC37
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 388 of 488
24. Programmable I/O Port
M32C/83 Group (M32C/83, M32C/83T)
Table 24.10 Port P13 Peripheral Function Output Control
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
PS7 Register
0: P130
1: OUTC24
0: P131
1: OUTC25
0: P132
1: OUTC26
0: P133
1: OUTC23
0: P134
1: OUTC20/ISTxD2/IEOUT
0: P135/ISRxD2/IEIN
1: OUTC22
0: P136/ISCLK2(input)
1: OUTC21/ISCLK2(output)
0: P137
1: OUTC27
Table 24.11 Port P14 Peripheral Function Output Control
PS8 Register
0: P140
1: OUTC14
Bit 1
0: P141
1: OUTC15
Bit 2
0: P142/INPC16
1: OUTC16
Bit 3
0: P143/INPC17
1: OUTC17
Bit 4 to 7 Set to " 0"
Bit 0
Table 24.12 Port P15 Peripheral Function Output Control
PS9 Register
0: P150/INPC00/AN150
1: OUTC00/ISTxD0/BE0OUT
Bit 1
0: P151/INPC01/AN151/ISCLK0(input)
1: OUTC01/ISCLK0(output)
Bit 2 to 3 Set to "0"
Bit 4
0: P154/INPC04/AN154
1: OUTC04
Bit 4
0: P155/INPC05/AN155
1: OUTC05
Bit 6 to 7 Set to " 0"
Bit 0
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 389 of 488
24. Programmable I/O Port
M32C/83 Group (M32C/83, M32C/83T)
25. Flash Memory Version
25. Flash Memory Version
Aside from the built-in flash memory, the flash memory version microcomputer has the same functions as the
masked ROM version.
In the flash memory version, rewrite operations to the flash memory can be performed in three modes: CPU
rewrite mode, standard serial I/O mode and parallel I/O mode.
Table 25.1 lists specifications of the flash memory version. See Tables 1.1 and 1.2 for the items not listed in
Table 25.1.
Table 25.1 Flash Memory Version Specifications
Item
Supply Voltage
Program and Erase Voltage
Specification
4.2V to 5.5V (f(XIN) = 32MHz, no wait)
3.0V to 5.5V (f(XIN) = 20MHz, no wait)
4.2V to 5.5V (through VDC), 3.0V to 3.6V (not through VDC)
CPU clock=12.5MHz (1 wait state), CPU clock=6.25MHz (no wait)
3 modes (CPU rewrite, standard serial I/O, parallel I/O)
See Figure 25.1
1 block (8 Kbytes)(1)
Per page (256 bytes)
All block erase, erase per block
Software commands control programming and erasing on the flash memory
The lock bit protects each block in the flash memory
8 commands
100 cycles(3)
10 years
Standard serial I/O mode and parallel I/O mode supported
Flash Memory Rewrite Mode
Erase Block
User ROM Area
Boot ROM Area
Program Method
Erase Method
Program and Erase Control Method
Protect Method
Number of Commands
Program and Erase Endurance
Data Retention
ROM Code Protection
NOTES:
1. The rewrite control program for standard serial I/O mode is stored in the boot ROM area before shipment. This space can be rewritten in parallel I/O mode only.
Table 25.2 Flash Memory Rewrite Mode Overview
Flash Memory
Rewrite Mode
CPU Rewrite Mode
Standard Serial I/O Mode
Parallel I/O Mode
Function
Software command execution
by CPU rewrites the user ROM
area.
A dedicated serial
programmer rewrites the user
ROM area.
Standard serial I/O mode 1:
Clock synchronous serial I/O
Standard serial I/O mode 2:
UART
A dedicated parallel
programmer rewrites the
boot ROM area and user
ROM area.
Space which
can be
Rewritten
User ROM area
User ROM area
User ROM area
Boot ROM area
Operating
Mode
Single-chip mode
Memory expansion mode
Boot mode
Boot mode
Parallel I/O mode
Programmer
None
Serial programmer
Parallel programmer
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 390 of 488
M32C/83 Group (M32C/83, M32C/83T)
25. Flash Memory Version
25.1 Memory Map
The flash memory contains a user ROM area, with space to store microcomputer operating programs in
single-chip mode or memory expansion mode, and a separate 8-Kbyte boot ROM area. Figure 25.1 shows
a block diagram of the flash memory.
The user ROM area is divided into several blocks, each of which can be protected (locked) from program
and erase. The user ROM area can be rewritten in CPU rewrite, standard serial I/O and parallel I/O modes.
The boot ROM area is allocated in the same addresses as the user ROM area. It can only be rewritten in
parallel I/O mode (refer to 25.5 Parallel I/O Mode). A program in the boot ROM area is executed after a
hardware reset occurs while an "H" signal is applied to the CNVSS and P50 pins and an "L" signal is applied
to the P55 pin (refer to 25.1.1 Boot Mode). A program in the user ROM area is executed after a hardware
reset occurs while an "L" signal is applied to the CNVSS pin. Consequently, the boot ROM area cannot be
read.
F8000016
Block 10 : 64 Kbytes
F9000016
Block 9 : 64 Kbytes
FA000016
Block 8 : 64 Kbytes
FB000016
Block 7 : 64 Kbytes
FC000016
Block 6 : 64 Kbytes
FD000016
FE000016
Block 5 : 64 Kbytes
Block 4 : 64 Kbytes
FF000016
Block 3 : 32 Kbytes
FF800016
FFA00016
FFC00016
Block 2 : 8 Kbytes
Block 1 : 8 Kbytes
Block 0 : 16 Kbytes
FFFFFF16
User ROM Area
Figure 25.1 Flash Memory Block Diagram
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
NOTES:
1. The boot ROM area can be rewritten in parallel I/O
mode
only. (Refer to 25.5.1 Boot Mode)
2. When specifying a block, use the highest-order even
address in the block to be specified.
Page 391 of 488
FFE00016
FFFFFF16
8 Kbytes
Boot ROM Area
M32C/83 Group (M32C/83, M32C/83T)
25. Flash Memory Version
25.1.1 Boot Mode
The microcomputer enters boot mode when a hardware reset is performed while an "H" signal is applied
to the CNVSS and P50 pins and an "L" signal is applied to the P55 pin. The program in the boot ROM area
is executed.
In boot mode, the FMR05 bit in the FMR0 register selects access to either the boot ROM area or the user
ROM area.
The rewrite control program for standard serial I/O mode (refer to 25.4 Standard Serial I/O Mode) is
stored in the boot ROM area before shipment.
The boot ROM area can be rewritten in parallel I/O mode only. If any rewrite control program using erasewrite mode is written in the boot ROM area, the flash memory can be rewritten according to the system
implemented.
25.2 Functions to Prevent the Flash Memory from Rewriting
The flash memory has the ROM code protect function for parallel I/O mode and the ID code verify function
for standard I/O mode to prevent the flash memory from reading or rewriting.
25.2.1 ROM Code Protect Function
The ROM code protect function prevents the flash memory from reading and rewriting in parallel I/O
mode. Figure 25.2 shows the ROMCP register. The ROMCP register is located in the user ROM area.
The ROM code protect function is enabled when the ROMCP1 bit is set to "002". The ROM code protect
function is disabled when the ROMCR bit is set to "002", regardless of the ROMCP1 bit setting.
Therefore, set the ROMCR bit to "112" and the ROMCP1 bit to "002" when setting up the ROM code
protect function.
Once the ROM code protect function is enabled, the ROMCR bit cannot be changed in parallel I/O mode.
Rewrite the ROMCR bit to "002" in standard serial I/O mode or CPU rewrite mode when disabling the
ROM code protect function.
25.2.2 ID Code Verify Function
Use the ID code verify function in standard serial I/O mode. The ID code sent from the serial programmer
is compared with the ID code written in the flash memory for a match. If the ID codes do not match,
commands sent from the serial programmer are not accepted. However, if the four bytes of the reset
vector are "FFFFFFFF16", ID codes are not compared, and all commands are accepted.
The ID codes are 7-byte data stored consecutively, starting with the first byte, into addresses
0FFFFDF16, 0FFFFE316, 0FFFFEB16, 0FFFFEF16, 0FFFFF316, 0FFFFF716 and 0FFFFFB16. The flash
memory must have a program with the ID codes set in these addresses.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 392 of 488
M32C/83 Group (M32C/83, M32C/83T)
25. Flash Memory Version
ROM Code Protect Control Address(3)
b7
b6
b5
b4
b3
b2
b1
b0
1 1 1 1
Symbol
Address
ROMCP
0FFFFFF16
Bit
Symbol
(b3 - b0)
After Reset
FF16
Bit Name
Function
Reserved Bit
Set to "1"
b5 b4
ROMCR
ROM Code Protect
Reset Bit(1)
0 0 : Disables ROM code protection
0 1 : Enables the ROMCP bit
1 0 : Enables the ROMCP bit
1 1 : Enables the ROMCP bit
RW
RW
RW
RW
b7 b6
ROM Code Protect
ROMCP1
Level 1 Set Bit(2)
0 0 : Enables ROM code protection
0 1 : Enables ROM code protection
1 0 : Enables ROM code protection
1 1 : ROM code protection inactive
RW
RW
NOTES:
1. When the ROMCR bit is set to "002", the ROM code protect level 1 is disabled. When the ROM code
protect level 1 is enabled, the ROMCR bit cannot be changed in parallel I/O mode. Change the
ROMCR bit in standard serial I/O mode, etc.
2. When the ROM code protect level 1 is enabled, the flash memory is protected against reading or
rewriting in parallel I/O mode.
3. The ROMCP register can be written with the page program command.
4. When a value of the ROMCP address is "0016" or "FF16", the ROM code protect function is disabled.
Figure 25.2 ROMCP Register
Address
FFFFDC16 to FFFFDF16
ID1
Undefined Instruction Vector
FFFFE016 to FFFFE316
ID2
Overflow Vector
FFFFE416 to FFFFE716
BRK Instruction Vector
FFFFE816 to FFFFEB16
ID3
FFFFEC16 to FFFFEF16
ID4
FFFFF016 to FFFFF316
ID5
FFFFF416 to FFFFF716
ID6
FFFFF816 to FFFFFB16
ID7
FFFFFC16 to FFFFFF16
Address Match Vector
Watchdog Timer Vector
NMI Vector
Reset Vector
4 bytes
Figure 25.3 Address to Store ID Code
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 393 of 488
M32C/83 Group (M32C/83, M32C/83T)
25. Flash Memory Version
25.3 CPU Rewrite Mode
In CPU rewrite mode, the user ROM area can be rewritten when the CPU executes software commands.
The user ROM area can be rewritten with the microcomputer mounted on a board, without using a parallel
or serial programmer.
Write the rewrite control program to either the user ROM area or the boot ROM area, beforehand. No
program in the flash memory can be executed in CPU rewrite mode. Therefore, transfer rewrite control
program to an area other than flash memory (internal RAM, etc.), and execute.
CPU rewrite mode can be entered when the microcomputer is in single-chip, memory expansion, and boot
mode.
Software commands, listed in Table 25.3, can be used in CPU rewrite mode. Refer to 25.3.3 Software
Command for details of each command.
Read or write commands and data from or to even addresses in the user ROM area, in 16-bit units. The 8
high-order bits (D15 to D8) are ignored when writing command codes.
Table 25.3 Software Commands
First Bus Cycle
Software Command
Mode
Address
Data
(D15 to D0)
Read Array
Write
X
xxFF16
Read Status Register
Write
X
xx7016
Clear Status Register
Second Bus Cycle
Third Bus Cycle
Data
Data
Mode Address
Mode Address
(D15 to D0)
(D15 to D0)
Read
X
SRD
Write
X
xx5016
Page Program
Write
X
xx4116
Write
WA
WD
Block Erase
Write
X
xx2016
Write
BA
xxD016
Erase All Unlocked Block
Write
X
xxA716
Write
X
xxD016
xxD016
D6
Lock Bit Program
Write
X
xx7716
Write
BA
Read Lock Bit Status
Write
X
xx7116
Read
BA
SRD:
WA:
WD:
BA:
D 6:
X:
xx:
Data in the SRD register (D7 to D0)
Address to be written (Increment A7 to A0 by 2 from "0016" to "FE16".)
16-bit write data
Highest-order block address (A0 = 0)
Lock bit (D6=1: unlock, D6=0: locked)
Any even address in the user ROM area (A0 = 0)
8 high-order bits of command code (ignored)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 394 of 488
Write
WA+2
WD
M32C/83 Group (M32C/83, M32C/83T)
25. Flash Memory Version
25.3.1 Flash Memory Control Register 0 (FMR0 Register)
Figure 25.4 shows the FMR0 register.
Flash Memory Control Register 0
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
FMR0
005716
0
Bit
Symbol
FMR00
After Reset
XX00 00012
Bit Name
RY/BY Signal
Status Bit
Function
RW
0 : BUSY (auto-writing, auto-erasing)
1 : READY (auto-write completed, auto-erase
completed)
RO
FMR01
CPU Rewrite Mode
Select Bit(1, 6)
0 : Disables CPU rewrite mode
1 : Enables CPU rewrite mode
RW
FMR02
Lock Bit Disable Bit(1, 3, 4)
0 : Enables the lock bit
1 : Disables the lock bit
RW
FMR03
By setting the bit to "1" just after setting it to "0",
Flash Memory Reset Bit(5) a flash memory access is interrupted to reset the
flash memory control circuit
RW
Reserved Bit
Set to"0"
RW
User ROM Area Select
Bit (Available in boot
mode only)(2, 6)
0: Access the boot ROM area
1: Access the user ROM area
RW
(b4)
FMR05
(b7 - b6)
Noting is assigned. When write, set to "0".
When read, its content is indeterminate.
NOTES:
1. Set this bit to "1" immediately after setting it to "0". Do not generate an interrupt or a DMA transfer
between setting the bit to "0" and setting it to "1". Write "0" to this bit when setting it to "0".
2. Set the FMR05 bit by program in a space other than the flash memory.
3. When the FMR01 bit is set to "0", the FMR02 bit is also set to "0" simultaneously.
4. The FMR02 bit can be set only when the FMR01 bit is set to "1".
5. When the FMR01 bit is set "0", set the FMR03 bit to "0".
Access the FMR03 bit when the FMR01 bit is set to "1".
6. Set the FMR05 bit while applying "H" to the NMI pin.
Figure 25.4 FMR0 Register
25.3.1.1 FMR00 Bit
The FMR00 bit indicates the write status machine (WSM) operation state during an auto write and
auto erase operation. The FMR00 bit is set to "0" during an auto write or auto erase operation and is
set to "1" when an auto write or auto erase operation is completed. The FMR00 bit changes while
executing the page program, block erase, erase all unlocked block or lock bit program command.
Determine whether the auto write or erase operation is completed by reading the FMR00 bit . The
FMR00 bit is changed by the above commands only.
25.3.1.2 FMR01 Bit
Commands can be accepted when the FMR01 bit is set to "1" (CPU rewrite mode). To set the FMR01
bit to "1", set to "1" immediately after setting it to "0". To set the FMR01 bit to "0", set it to "0".
CPU rewrite mode is entered by setting the FMR01 bit to "1" and programs in the flash memory cannot
be executed. Execute an instruction written to this bit in a space (internal RAM, etc.) other than the
flash memory.
If a command for CPU rewrite mode is executed in boot mode, set the FMR05 bit to "1" (user ROM
area access).
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 395 of 488
M32C/83 Group (M32C/83, M32C/83T)
25. Flash Memory Version
25.3.1.3 FMR02 Bit
The lock bit set for each block can be disabled by setting the FMR02 bit to "1" (lock bit disabled).
(Refer to 25.3.3 Data Protect Function.) The lock bit is enabled by setting the FMR02 bit to "0" (lock
bit enabled). The FMR02 bit can be set when the FMR01 bit is set to "1". To set the FMR02 bit to "1",
set it to "1" immediately after setting it to "0". To set the FMR02 bit to "0", set it to "0".
The FMR02 bit does not change the lock bit state, but disables the lock bit function. If the block erase
or erase all unlocked block command is executed while the FMR02 bit is set to "1", the lock bit state
changes "0" (locked) to "1" (unlocked) after command execution is completed.
25.3.1.4 FMR03 Bit
By setting the FMR03 bit to "0" following "1", access to the user ROM area is interrupted to reset the
flash memory control circuit. The flash memory enters read array mode after reset. The FMR00 bit is
set to "1" (READY) and the Status register is set to "8016". (Refer to 25.3.2 Status Register.)
When the FMR03 bit resets the flash memory control circuit during an auto write or auto erase operation, an auto write or auto erase operation is interrupted. Data in the block is invalid.
To set the FMR03 bit to "0", set it to "0" immediately after setting it to "1".
25.3.1.5 FMR05 Bit
The FMR05 bit selects the boot ROM or user ROM area in boot mode. Set to "0" to access (read) the
boot ROM area or to "1" (user ROM access) to access (read, write or erase) the user ROM area.
Execute an instruction written to the FMR05 bit in a space (internal RAM, etc.) other than the flash
memory.
In modes other than boot mode, the user ROM area is accessed (read) regardless of the FMR05 bit
setting.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 396 of 488
M32C/83 Group (M32C/83, M32C/83T)
25. Flash Memory Version
25.3.2 Status Register
The write state machine (WSM) in the flash memory controls programming and erasing of the flash
memory. The status register indicates whether or not the WSM is operating as expected, and whether or
not a program or erase operation is completed as expected. Refer to 25.3.6 Full Status Check for
details on each error.
Table 25.4 lists the status register.
The status register can be read by the read status command (Refer to 25.3.5 Software Command).
Table 25.4 Status Register
Symbol
Definition
Status Name
0
1
SR0 (D0)
Reserved bit
-
-
SR1 (D1)
Reserved bit
-
-
SR2 (D2)
Reserved bit
-
-
SR3 (D3)
Block status after program
Completed as expected
Error (excessive write error)
SR4 (D4)
Program status
Completed as expected
Error (program error)
SR5 (D5)
Erase status
Completed as expected
Error (erase error)
SR6 (D6)
Reserved bit
-
-
SR7 (D7)
Write state machine (WSM) status
BUSY
READY
D7 to D0 : These data bus are read when the read status register command is executed.
25.3.2.1 Block Status After Program (SR3)
The SR3 bit is set to "1" when a page program command execution is completed with an excessive
write error. The SR3 bit is set to "0" when the clear status command is executed.
The SR3 bit is set to "0" after reset or after setting the FMR03 bit to "0" following "1".
25.3.2.2 Program Status (SR4)
The SR4 bit is set to "1" when a program error occurs while the page program or lock bit program
command is being executed. The SR4 bit is set to "0" when the clear status command is executed.
The SR4 bit is set to "0" after reset or after setting the FMR03 bit to "0" following "1".
25.3.2.3 Erase Status (SR5)
The SR5 bit is set to "1" when an erase error occurs while the block erase or erase all unlocked block
command is being executed. The SR5 bit is set to "0" when the clear status command is executed.
The SR5 bit is set to "0" after reset or after setting the FMR03 bit to "0" following "1".
25.3.2.4 Write State Machine (WSM) Status (SR7)
The SR7 bit indicates the WSM operation state. The SR7 bit is set to "0" during auto write or auto
erase and to "1" when an auto write or auto erase operation is completed. The SR7 bit changes while
the page program, block erase, erase all unlocked block or lock bit program command is being executed. The SR7 bit changes with the above commands only. The SR7 bit is set to "1" after reset or
after setting the FMR03 bit to "0" following "1",.
The FMR00 bit indicates the WSM status. Read the FMR00 bit to determine whether the auto write or
erase operation is completed.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 397 of 488
M32C/83 Group (M32C/83, M32C/83T)
25. Flash Memory Version
25.3.3 Data Protect Function
Each block in the flash memory has a nonvolatile lock bit. The lock bit is enabled by setting the FMR02 bit
to "0" (lock bit enabled). The lock bit individually protects (locks) each block against program and erase.
This prevents data from being inadvertently written to or erased from the flash memory.
• When the lock bit status is set to "0", the block is locked (block is protected against program and erase).
• When the lock bit status is set to "1", the block is not locked (block can be programmed or erased).
The lock bit status is set to "0" (locked) by executing the lock bit program command and to "1" (unlocked)
by erasing the block. The lock bit status cannot be set to "1" by any commands.
The lock bit status can be read by the read lock bit status command.
The lock bit function is disabled by setting the FMR02 bit to "1". All blocks are unlocked. However,
individual lock bit status remains unchanged. The lock bit function is enabled by setting the FMR02 bit to
"0". Lock bit status is retained.
If the block erase or erase all unlocked block command is executed while the FMR02 bit is set to "1", the
target block or all blocks are erased regardless of lock bit status. The lock bit status of each block is set to
"1" after an erase operation has been completed.
Refer to 25.3.5 Software Commands for details on each command.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 398 of 488
M32C/83 Group (M32C/83, M32C/83T)
25. Flash Memory Version
25.3.4 How to Enter and Exit CPU Rewrite Mode
Figure 25.5 shows how to enter and exit CPU rewrite mode.
No program in the flash memory can be executed in CPU rewrite mode. Execute rewrite control program
in a space other than the flash memory (internal RAM, etc.) after transferring the program to that space.
Rewrite control program
Single-chip mode,
Memory expansion mode,
Boot mode
In boot mode only
Set the FMR05 bit to "1" (User ROM area
accessed)
Set the PM0, PM1 and MCD register(1)
Set the FMR01 bit to "1" (CPU rewrite
mode enabled) following "0"
Transfer the rewrite control program in
CPU rewrite mode to space other than
the flash memory
Jump to the rewrite control program
transferred to space other than the flash
memory. (On the following steps, use the
rewrite control program in space other than
the flash memory.)
Execute software commands
Set the FMR03 bit to "0" after executing a
read array command or after setting the
FMR03 bit to "1" (2)
Set the FMR01 bit to "0" (CPU rewrite mode
disabled)
In boot mode only
Set the FMR05 bit to "0" (boot ROM area
accessed)(3)
Jump to a desired address in the
flash memory
NOTES:
1. Set the MCD register to the following CPU clock frequency:
When the PM12 bit in the PM1 register is set to "0" (no internal access wait), 6.25 MHz or less
When the PM12 bit in the PM1 register is set to "1" (internal access wait), 12.5 MHz or less
2. Exit CPU rewrite mode after excuting the read array command or resetting the flash memory.
3. When CPU rewrite mode is exited while the FMR05 bit is set to "1", the user ROM area can be accessed.
Figure 25.5 How to Enter and Exit CPU Rewrite Mode
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 399 of 488
M32C/83 Group (M32C/83, M32C/83T)
25. Flash Memory Version
25.3.5 Software Commands
Read or write commands and data from or to even addresses in the user ROM area, in 16-bit units. When
writing a command code, 8 high-order bits (D15 to D8) are ignored.
25.3.5.1 Read Array Command
The read array command reads the flash memory.
Read array mode is entered by writing command code "xxFF16" in the first bus cycle. Content of a
specified address can be read after the next bus cycle.
The microcomputer remains in read array mode until another command is written. Therefore, contents
from multiple addresses can be read consecutively.
25.3.5.2 Read Status Register Command
The read status register command reads the status register (refer to 25.3.7 Status Register for details).
By writing command code "xx7016" in the first bus cycle, the status register can be read in the second
bus cycle. Read an even address in the user ROM area.
25.3.5.3 Clear Status Register Command
The clear status register command clears the status register. By writing "xx5016" in the first bus cycle,
the SR5 to SR3 bits in the status register (see Table 25.4) are set to "0".
25.3.5.4 Page Program Command
The page program command executes programs in 128-word (256-byte) units.
After writing command code "xx4116" in the first bus cycle, write data to the 2nd through 129th bus
cycles in 16-bit units. Increment by two, from "0016" to "FE16", the 8 low-order bits of the write address.
Auto write, programming and verification of data, is performed when 128 word data has been written.
Do not access the flash memory or execute the next command during auto write operation.
The FMR00 bit in the FMR0 register indicates whether an auto program operation is completed.
After an auto write operation is completed, the Status register indicates whether the auto write operation is completed as expected or not. (Refer to 25.3.6 Full Status Check.)
Figure 25.6 shows a flow chart of the page program command programming. When programming a
space which is already programmed, execute erase (block erase) before programming. If the page
program command is executed to a space already programmed, no program error occurs but the page
is indeterminate.
The lock bit can protect blocks from being programmed. (Refer to 25.3.3 Data Protect Function.)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 400 of 488
M32C/83 Group (M32C/83, M32C/83T)
25. Flash Memory Version
Start
Write command code
"xx4116"
n=0
Write data to the
address to be written
n = FE16
Address to be written
address to be written + 2
n=n+2
NO
YES
FMR00 bit = 1?
(auto write operation
completed?)
NO
YES
Full status check
Page program
operation is
completed
Figure 25.6 Program Command
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 401 of 488
See Figure 25.11
M32C/83 Group (M32C/83, M32C/83T)
25. Flash Memory Version
25.3.5.5 Block Erase Command
The block erase command erases each block.
By writing command code "xx2016" in the first bus cycle and "xxD016" to the highest-order even address
of a block in the second bus cycle, an auto erase operation (erase and verify) starts in the specified
block. Do not access the flash memory or execute the next command during auto erase operations.
The FMR00 bit in the FMR0 register indicates whether an auto erase operation has been completed.
After the completion of an auto erase operation, the Status register indicates whether or not the auto
erase operation has been completed as expected. (Refer to 25.3.6 Full Status Check.)
Figure 25.7 shows a flow chart of the block erase command programming.
The lock bit can protect blocks from being erased. (Refer to 25.3.6 Data Protect Function.)
Start
Write command code
"xx2016"
Write "xxD016" to the
highest-order block address
FMR00 bit = 1?
(auto erase operation
completed?)
NO
YES
Full status check
Block erase
operation is
completed
Figure 25.7 Block Erase Command
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 402 of 488
See Figure 25.11
M32C/83 Group (M32C/83, M32C/83T)
25. Flash Memory Version
25.3.5.6 Erase All Unlocked Block Command
By writing command code "xxA716" in the first bus cycle and "xxD016" in the second bus cycle, an auto
erase (erase and verify) operation will run in all blocks. Do not access the flash memory or execute
the next command during auto erase operations.
The FMR00 bit in the FMR0 register indicates whether an auto erase operation is completed.
After the completion of an auto erase operation, the Status register indicates whether or not the auto
erase operation is completed as expected.
Figure 25.8 shows a flow chart of the erase all unlocked block command programming.
The lock bit can protect each block from being erased. (Refer to 25.3.6 Data Protect Function.)
Start
Write command code
"xxA716"
Write "xxD016"
FMR00 bit = 1?
NO
(auto erase operation
completed?)
YES
Full status check
All unlocked block
erase operation is
completed
Figure 25.8 Erase All Unlocked Block Command
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 403 of 488
See Figure 25.11
M32C/83 Group (M32C/83, M32C/83T)
25. Flash Memory Version
25.3.5.7 Lock Bit Program Command
The lock bit program command sets the lock bit for a specified block to "0" (locked).
By writing command code "xx7716" in the first bus cycle and "xxD016" to the highest-order even address of a block in the second bus cycle, auto write operation starts, and the lock bit for the specified
block is set to "0". Do not access the flash memory or execute the next instructions during the lock bit
program operation.
The FMR00 bit in the FMR0 register indicates whether or not the lock bit program operation has been
completed. After the completion of a lock bit program operation, the Status register indicates whether
or not the operation has been completed as expected. (Refer to 25.3.6 Full Status Check.)
Figure 25.9 shows a flow chart of the lock bit program command programming.
Refer to 25.3.6 Data Protect Function for details on how to set the lock bit function to "0" (unlocked).
Start
Write command code
"xx7716"
Write "xxD016" to the highestorder block address
FMR00 bit = 1?
NO
(auto write operation
completed?)
YES
Full status check
Lock bit program
operation is
completed
Figure 25.9 Lock Bit Program Command
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 404 of 488
See Figure 25.11
M32C/83 Group (M32C/83, M32C/83T)
25. Flash Memory Version
25.3.5.8 Read Lock Bit Status Command
The read lock bit status command reads the lock bit state of a specified block.
By writing command code "xx7116" in the first bus cycle and reading the highest-order address (however, A0=0) of a block in the second bus cycle, the lock bit state information of a specified block is read
out to the data bus (D6).
Figure 25.10 shows a flow chart of the read lock bit status command programming.
Start
Write command code
"xx7116"
Read the value in the
highest-order block address
D6 = 0?
NO
YES
Blocks are locked
Figure 25.10 Read Lock Bit Status Command
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 405 of 488
No block is locked
M32C/83 Group (M32C/83, M32C/83T)
25. Flash Memory Version
25.3.6 Full Status Check
If an error occurs when a program or erase operation is completed, the SR3 to SR5 bits in the status
register are set to "1", indicating a specific error. Therefore, execution results can be confirmed by verifying these bits (full status check).
Table 25.5 lists errors and status register state. Figure 25.12 shows a flow chart of the full status check
and handling procedure for each error.
Table 25.5 Errors and Status Register State
Status Register
Error
SR5 SR4 SR3
1
1
0
Command sequence
error
Error Occurrence Conditions
• An incorrect command is written
• A value other than "xxD016" or "xxFF16" is written in the second bus cycle of the lock bit program, block erase or erase
all unlocked block command(1)
1
0
0
Erase error
• The block erase command is executed on a locked block2
• The block erase or erase all unlocked block command is
executed on an unlock block but the erase operation is not
completed as expected
0
1
0
Program error
0
0
1
Excessive write error
• The page program command is executed on a locked
block(2)
• The page program command is executed in an unlocked
block but the program operation is not completed as expected
• The lock bit program command is executed but the program operation is not completed as expected
Excessive write occurs after the page program command
is executed
NOTES:
1. The flash memory enters read array mode when command code "xxFF16" is written in the second bus
cycle of these commands. The command code written in the first bus cycle becomes invalid.
2. If the FMR02 bit is set to "1" (lock bit disabled), no error occurs even under the conditions listed above.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 406 of 488
M32C/83 Group (M32C/83, M32C/83T)
25. Flash Memory Version
Start
Write command code
"xx7016"
Read even address
in user ROM area
SR4=1
and
SR5=1
?
NO
SR5=0 ?
YES
NO
Command sequence
error
Erase error
YES
SR4=0 ?
NO
Program error
YES
SR3=0 ?
NO
Excessive write error
YES
(1) Execute the clear status register command,
and set the SR4 and SR5 bits to "0".
(2) Execute the correct command again.
NOTE: If similar error occurs, that block cannot be used.
(1) Execute the clear status register command and set the SR5 bit to "0".
(2) Execute the lock bit read status command, and set the FMR02 bit to "1" if
the lock bit in the block where the error occurred is set to "0" (locked).
(3) Execute the block erase or erase all unlocked block command again.
NOTE: If similar error occurs, that block cannot be used.
If the lock bit is set to "1" (unlocked) in (2) above, that block cannot
be used.
[When a page program operation is executed]
(1) Execute the clear status register command and set the SR4 bit to "0".
(2) Execute the read lock bit status command, and set the FMR02 bit to "1" if
the lock bit in the block where the error occurred is set to "0" (locked) .
(3) Execute the page program command again.
NOTE: If similar error occurs, that block cannot be used.
If the lock bit is set to "1" (unlocked) in (2) above, that block cannot
be used.
[When a lock bit program operation is executed]
(1) Execute the clear status register command and set the SR4 bit to "0".
(2) Set the FMR02 bit to "1".
(3) Execute the block erase command to erase the block where the error
occurred.
(4) Execute the lock bit program command again.
NOTE: If similar error occurs, that block cannot be used.
(1) Execute the clear status register command and set the SR3 bit to "0".
(2) Execute the block erase command to erase the block where the error
occurred.
(3) Execute the page program command again.
NOTE: If similar error occurs, that block cannot be used.
Completed
NOTE: When any of the SR5 to SR3 bits are set to "1", the page program, block erase, erase all unlocked block and lock bit program
commands cannot be accepted.
Execute the clear status register command before each command.
Figure 25.11 Full Status Check and Handling Procedure for Each Error
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 407 of 488
M32C/83 Group (M32C/83, M32C/83T)
25. Flash Memory Version
25.3.7 Precautions in CPU Rewrite Mode
25.3.7.1 Operating Speed
Set the MCD register to the following CPU clock before entering CPU rewrite mode .
When the PM12 bit in the PM register is set to "0" (no wait state), 6.25MHz or less
When the PM12 bit in the PM register is set to "1" (wait state), 12.5MHz or less
25.3.7.2 Prohibited Instructions
In CPU rewrite mode, programs cannot be executed, nor can interrupt vectors be read in the flash
memory. Execute the rewrite control program after the program is transferred to a space other than
the flash memory. (See Figure 25.5.)
The following instructions cannot be used because the CPU tries to read data in the flash memory: the
UND instruction, INTO instruction, JMPS instruction, JSRS instruction and BRK instruction.
25.3.7.3 Interrupts
• To use interrupts having vectors in a relocatable vector table, the vectors must be relocated to the
RAM area.
_______
• The NMI and watchdog timer interrupts are available since the FMR01 is forcibly reset when either
interrupt occurs. Allocate the jump addresses for each interrupt service routine and write to the fixed
_______
vector table. Flash memory rewrite operation is aborted when the NMI or watchdog timer interrupt
occurs. Execute the rewrite program again after exiting the interrupt routine.
• The address match interrupt is not available since the CPU tries to read data in the flash memory.
25.3.7.4 Reading and Writing Commands and Data
Read or write 16-bit commands and data from or to even addresses in the user ROM area.
25.3.7.5 Reset
Reset is always enabled.
25.3.7.6 Access Prohibited
Write the FMR01 bit and FMR05 bit in a space other than the flash memory.
25.3.7.7 How to Access
To set the FMR01 bit and FMR02 bits to "1", set to "1" immediately after setting to "0". Do not generate
an interrupt or a DMA transfer between the instruction to set the bits to "1" and the instruction to set the
______
bits to "0". Set the FMR01 bit to "1" after an "H" signal is applied to the P85/NMI pin.
25.3.7.8 Rewriting in the User ROM Area
If the supply voltage drops while in CPU rewrite mode, when rewriting the block where the rewrite
control program is stored, the flash memory cannot be rewritten because the rewrite control program
is not correctly rewritten. If this error occurs, rewrite the user ROM area while in standard serial I/O
mode or parallel I/O mode.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 408 of 488
M32C/83 Group (M32C/83, M32C/83T)
25. Flash Memory Version
25.4 Standard Serial I/O Mode
In standard serial I/O mode, the serial programmer supporting the M32C/83 group can be used to rewrite
the flash memory user ROM area, while the microcomputer is mounted on a board. For more information
about the serial programmer, contact your serial programmer manufacturer. Refer to the user's manual
included with your serial programmer for instructions.
Standard serial I/O mode includes:
• Standard serial I/O mode 1 (clock synchronous)
• Standard serial I/O mode 2 (clock asynchronous)
25.4.1 Pin Function
Table 25.6 lists pin descriptions (flash memory standard serial I/O mode). Figures 2.12 to 25.14 show pin
connections in serial I/O mode.
25.4.2 ID Code Verify Function
The ID code verify function determines whether the ID codes sent from the serial programmer matches
those written in the flash memory. (Refer to 25.2 Functions to Prevent Flash Memory from Rewriting.)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 409 of 488
25. Flash Memory Version
M32C/83 Group (M32C/83, M32C/83T)
Table 25.6 Pin Description (Flash Memory Standard Serial I/O Mode)
Symbol
Function
I/O Type
Description
VCC
Power Supply
VSS
Input
CNVSS
CNVSS
I
Connect this pin to VCC
RESET
Reset Input
I
Reset input pin. Apply 20 or more clock cycles to the XIN pin while "L"
_______
I
Apply 4.2 V to 5.5 V to the VCC pin
Apply 0 V to the VSS pin
____________
is applied to the RESET pin.
XIN
Clock Input
I
Connect a ceramic resonator or crystal oscillator between XIN and
XOUT
Clock Output
O
XOUT. To use the external clock, input the clock from XIN and leave
XOUT open.
BYTE
BYTE Input
I
Connect this pin to VSS or VCC
AVCC
Analog Power
I
Connect AVCC to VCC
AVSS
Supply Input
I
Connect AVSS to VSS
VREF
Reference
I
Reference voltage input pin for the A/D converter.
Voltage Input
P00 to P07
Input Port P0
I
Apply "H" or "L" to this pin, or leave open
P10 to P17
Input Port P1
I
Apply "H" or "L" to this pin, or leave open
P20 to P27
Input Port P2
I
Apply "H" or "L" to this pin, or leave open
P30 to P37
Input Port P3
I
Apply "H" or "L" to this pin, or leave open
P40 to P47
Input port P4
I
Apply "H" or "L" to this pin, or leave open
I
Apply "H" to this pin.
___
P50
CE Input
_____
P55
EPM Input
I
Apply "L" to this pin.
P51 to P54
Input Port P5
I
Apply "H" or "L" to this pin, or leave open
P60 to P63
Input Port P6
I
Apply "H" or "L" to this pin, or leave open
P64
BUSY Output
O
Standard serial I/O mode 1: BUSY signal output pin
P65
SCLK Input
I
Standard serial I/O mode 1: Serial clock input pin
P56, P57
Standard serial I/O mode 2: Program running verify monitor
Standard serial I/O mode 2: Apply "L" to this pin
P66
RxD
I
Serial data input pin
P67
TxD
O
Serial data output pin(1)
P70 to P77
Input Port P7
I
Apply "H" or "L" to this pin, or leave open
P80 to P84
Input Port P8
I
Apply "H" or "L" to this pin, or leave open
P86, P87
____
P85
NMI Input
I
Connect this pin to VCC
P90 to P97
Input Port P9
I
Apply "H" or "L" to this pin, or leave open
P100 to P107
Input Port P10
I
Apply "H" or "L" to this pin, or leave open
Input Port P11
I
Apply "H" or "L" to this pin, or leave open
P120 to P127(2) Input Port P12
I
Apply "H" or "L" to this pin, or leave open
Input Port P13
I
Apply "H" or "L" to this pin, or leave open
P140 to P146(2) Input Port P14
I
Apply "H" or "L" to this pin, or leave open
I
Apply "H" or "L" to this pin, or leave open
P110 to
P130 to
P150 to
P114(2)
P137(2)
P157(2)
Input Port P15
NOTES:
1. In standard serial I/O mode 1, apply an "L" signal to the TxD pin while applying "L" to the RESET pin.
Connect P67 to VSS via a resistor. P67 becomes a data output pin after reset. Adjust the value of the
pull-down resistor on your system so as not to affect data transfer.
2. These pins are provided in the 144-pin package only.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 410 of 488
M32C/83 Group (M32C/83, M32C/83T)
25. Flash Memory Version
Mode settings
Signal
Value
CNVss
Vcc
EPM
Vss
RESET
CE
Vss >> Vcc
Vcc
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
M32C/83 Group
(M32C/83, M32C/83T)
Flash Memory Version
(PRQP0100JB-A(100P6S-A))
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
CE
EPM
BUSY
SCLK
RxD
TxD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Vss
Vcc
RESET
CNVss
Connect to
oscillation
circuit
Figure 25.12 Pin Connections in Standard Serial I/O Mode (1)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 411 of 488
25. Flash Memory Version
M32C/83 Group (M32C/83, M32C/83T)
Mode settings
Signal
Value
CNVss
Vcc
EPM
RESET
CE
Vss
Vss >> Vcc
Vcc
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
M32C/83 Group
(M32C/83, M32C/83T)
Flash Memory Version
(PLQP0100KB-A(100P6Q-A))
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
CE
EPM
BUS
Y
TX
D
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
VSS
RESET
CNVSS
VCC
Connect to
oscillation
circuit
Figure 25.13 Pin Connections in Standard Serial I/O Mode (2)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 412 of 488
SCLK
RXD
M32C/83 Group (M32C/83, M32C/83T)
25. Flash Memory Version
Mode settings
Signal
Value
CNVss
Vcc
EPM
Vss
RESET
Vss >> Vcc
CE
Vcc
108 107 106 105 104 103 102 101 100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
109
72
110
71
111
70
112
69
113
68
114
67
115
66
116
65
117
64
118
63
119
62
120
CE
61
M32C/83 Group
121
122
123
(M32C/83, M32C/83T)
124
125
Flash Memory Version
126
127
128
(PLQP0144KA-A(144P6Q-A))
129
60
59
58
57
56
55
54
52
51
131
50
132
49
133
48
134
47
135
46
136
45
137
44
138
43
139
42
140
41
141
40
142
39
143
38
144
37
1
2
3
4
5
6
7
8
EPM
53
130
BUSY
SCLK
RxD
TxD
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
VCC
VSS
RESET
CNVSS
Connect to
oscillation
circuit
Figure 25.14 Pin Connections in Standard Serial I/O Mode (3)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 413 of 488
25. Flash Memory Version
M32C/83 Group (M32C/83, M32C/83T)
25.4.3 Precautions in Standard Serial I/O Mode
• Serial I/O mode cannot be used after boot ROM area is written in parallel I/O mode.
• If an user reset signal becomes "L" in serial I/O mode, break connection between the user reset signal
___________
and the RESET pin by using, for example, a jumper selector.
25.4.4 Circuit Application in Standard Serial I/O Mode
Figure 25.15 shows an example of a circuit application in standard serial I/O mode 1. Figure 25.16 shows
an example of a circuit application in serial I/O mode 2. Refer to the user's manual of your serial programmer to handle pins controlled by the serial programmer.
Microcomputer
Clock Input
SCLK
Data Output
TXD
BUSY Output
BUSY
P50(CE)
P55(EPM)
CNVss
RxD
Data Input
Reset Input
RESET
NMI
User Reset
Signal
NOTES:
1. Control pins and external circuitry vary with serial programmer. Refer to the user's manual included
with the serial programmer.
2. In this example, a selector is used to switch between single-chip mode and standard serial I/O
mode.
3. In standard serial I/O mode 1, if the user reset signal becomes "L" while in serial I/O mode, break
connection between the user reset signal and the RESET pin using, for example, a jumper selector.
Figure 25.15 Circuit Application in Standard Serial I/O Mode 1
Microcomputer
SCLK
Monitor Output
BUSY
Data Input
RXD
Data Output
TXD
CNVss
NMI
P50(CE)
P55(EPM)
NOTES:
1. In this example, a selector is used to switch between single-chip mode and standard serial I/O
mode.
Figure 25.16 Circuit Application in Standard Serial I/O Mode 2
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 414 of 488
M32C/83 Group (M32C/83, M32C/83T)
25. Flash Memory Version
25.5 Parallel I/O Mode
In parallel I/O mode, the user ROM area and the boot ROM area (see Figure 25.1) can be rewritten by a
parallel programmer supporting the M32C/83 Group. Contact your parallel programmer manufacturer for
more information on the parallel programmer. Refer to the user's manual included with your parallel programmer for instructions.
25.5.1 Boot ROM Area
Within the boot ROM area, 8K bytes equal one block.
The rewrite control program in standard serial I/O mode is written in the boot ROM area before shipment.
Do not rewrite the boot ROM area if using a serial programmer.
In parallel I/O mode, the boot ROM area is allocated to addresses 0FFE00016 to 0FFFFFF16. Rewrite
only this address range when rewriting the boot ROM area. (Do not access addresses other than addresses 0FFE00016 to 0FFFFFF16.)
25.5.2 ROM Code Protect Function
The ROM code protect function prevents the flash memory from being read and rewritten in parallel I/O
mode. (Refer to 25.2 Functions to Prevent Flash Memory from Rewriting.)
25.5.3 Precautions on Parallel I/O Mode
Standard serial I/O mode cannot be used if rewriting the boot ROM area in parallel I/O mode. (Refer to
25.4 Standard Serial I/O Mode.)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 415 of 488
M32C/83 Group (M32C/83, M32C/83T)
26. Electrical Characteristics
26. Electrical Characteristics
26.1 Electrical Characteristics (M32C/83)
Table 26.1 Absolute Maximum Ratings
Symbol
VCC
Parameter
Supply Voltage
AVCC
Analog Supply Voltage
VI
Input Voltage
Condition
Value
Unit
VCC=AVCC
-0.3 to 6.0
V
VCC=AVCC
RESET, CNVSS, BYTE, P00-P07, P10-P17, P20-P27,
P30-P37, P40-P47, P50-P57, P60-P67, P72-P77, P80-
-0.3 to 6.0
V
-0.3 to VCC+0.3
V
-0.3 to 6.0
V
-0.3 to VCC+0.3
V
500
mW
-20 to 85
°C
-65 to 150
°C
P87, P90-P97, P100-P107, P110-P114, P120-P127,
P130-P137, P140-P146, P150-P157(1), VREF, XIN
P70, P71
VO
Output Voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50P57, P60-P67, P72-P77, P80-P84, P86, P87, P90-P97,
P100-P107, P110-P114, P120-P127, P130-P137, P140P146, P150-P157(1), XOUT
Pd
Power Dissipation
Topr
Operating Ambient Temperature
Tstg
Storage Temperature
NOTES:
1. P11 to P15 are provided in the 144-pin package.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 416 of 488
Topr=25° C
26. Electrical Characteristics
M32C/83 Group (M32C/83, M32C/83T)
Table 26.2 Recommended Operating Conditions (VCC = 3.0V to 5.5V at Topr = – 20 to 85oC)
Symbol
VCC
AVCC
VSS
AVSS
VIH
VIL
IOH(peak)
IOH(avg)
IOL(peak)
Parameter
Standard
Supply Voltage (Through VDC)
Supply Voltage (Not through VDC)
Analog Supply Voltage
Supply Voltage
Analog Supply Voltage
Input High ("H") P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P72-P77, P80Voltage
P87(3), P90-P97, P100-P107, P110-P114, P120-P127, P130P137, P140-P146, P150-P157(4), XIN, RESET, CNVSS, BYTE
P70, P71
Input Low ("L")
Voltage
Min
3.0
3.0
Unit
Max
5.5
3.6
V
V
V
V
V
V
0.8VCC
VCC
0.8VCC
6.0
P00-P07, P10-P17 (in single-chip mode)
0.8VCC
VCC
V
P00-P07, P10-P17
(in memory expansion mode and microprocesor mode)
P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80P87(3), P90-P97, P100-P107, P110-P114, P120-P127, P130P137, P140-P146, P150-P157(4), XIN, RESET, CNVSS, BYTE
P00-P07, P10-P17 (in single-chip mode)
0.5VCC
VCC
V
0
0.2VCC
V
0
0.2VCC
V
0
0.16VCC
V
-10.0
mA
-5.0
mA
10.0
mA
5.0
mA
32
20
20
MHz
MHz
MHz
50
kHz
P00-P07, P10-P17
(in memory expansion mode and microprocesor mode)
Peak Output
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60High ("H")
P67, P72-P77, P80-P84, P86, P87, P90-P97, P100-P107, P110Current(2)
P114, P120-P127, P130-P137, P140-P146, P150-P157(4)
Average Output P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60High ("H")
P67, P72-P77, P80-P84, P86, P87, P90-P97, P100-P107, P110Current(1)
P114, P120-P127, P130-P137, P140-P146, P150-P157(4)
Peak Output
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60Low ("L")
P67, P70-P77, P80-P84, P86, P87, P90-P97, P100-P107, P110Current(2)
P114, P120-P127, P130-P137, P140-P146, P150-P157(4)
IOL(avg)
Average Output P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60Low ("L")
P67, P70-P77, P80-P84, P86, P87, P90-P97, P100-P107, P110Current(1)
P114, P120-P127, P130-P137, P140-P146, P150-P157(4)
f(XIN)
Main Clock
Input
Frequency
Through VDC
Not through VDC
VCC=4.2 to 5.5V
VCC=3.0 to 4.3V
VCC=3.0 to 3.6
0
0
0
f(XCIN)
Sub Clock Oscillation Frequency
NOTES:
1. Typical values when average output current is 100ms.
2. Total IOL(peak) for P0, P1, P2, P86, P87, P9, P10, P11, P14 and P15 must be 80mA or less.
Total IOH(peak) for P0, P1, P2, P86, P87, P9, P10, P11, P14 and P15 must be -80mA or less.
Total IOL(peak) for P3, P4, P5, P6, P7, P80 to P84, P12 and P13 must be 80mA or less.
Total IOH(peak) for P3, P4, P5, P6, P72 to P77, P80 to P84, P12 and P13 must be -80mA or less.
3. VIH and VIL reference for P87 applies when P87 is used as a programmable input port.
It does not apply to P87 used as XCIN.
4. P11 to P15 are provided in the 144-pin package only.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Typ
5.0
3.3
VCC
0
0
Page 417 of 488
32.768
26. Electrical Characteristics
M32C/83 Group (M32C/83, M32C/83T)
VCC=5V
Table 26.3 Electrical Characteristics (VCC=4.2 to 5.5V, VSS=0V
at Topr= –20 to 85oC, f(XIN)=32MHZ unless otherwise specified)
Symbol
VOH
VOL
VT+-VT-
IIH
Parameter
Output High ("H")
Voltage
Output Low ("L")
Voltage
Hysteresis
Input High ("H")
Current
RPULLUP
Pull-up Resistance
IOH=-5mA
IOH=-200µA
Vcc - 0.3
XCOUT
No load applied
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47,
P50-P57, P60-P67, P70-P77, P80-P84, P86, P87,
P90-P97, P100-P107, P110-P114, P120-P127,
P130-P137, P140-P146, P150-P157(1)
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47,
P50-P57, P60-P67, P70-P77, P80-P84, P86, P87,
IOL=5mA
2.0
V
IOL=200µA
0.45
V
P90-P97, P100-P107, P110-P114, P120-P127,
P130-P137, P140-P146, P150-P157(1)
XOUT
IOL=1mA
2.0
V
XCOUT
No load applied
IOH=-1mA
TA0OUT-TA4OUT, NMI, KI0-KI3, RxD0-RxD4,
SCL0-SCL4, SDA0-SDA4
RESET
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47,
P50-P57, P60-P67, P70-P77, P80-P87, P90-P97,
BYTE
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47,
P50-P57, P60-P67, P72-P77, P80-P84, P86, P87,
P90-P97, P100-P107, P110-P114, P120-P127,
NOTES:
1. P11 to P15 are provided in the 144-pin package only.
Page 418 of 488
Max
V
3.0
V
3.3
V
0
V
0.2
1.0
V
0.2
VI=5V
1.8
5.0
V
µA
VI=0V
-5.0
µA
167
kΩ
54
MΩ
MΩ
V
mA
VI=0V
P130-P137, P140-P146, P150-P157(1)
Feedback Resistance XIN
Feedback Resistance XCIN
RAM Standby Voltage Through VDC
Power Supply
Measurement conditions:
f(XIN)=32 MHz, square wave,
Current
In single-chip mode, output
no division
pins are left open and other
f(XCIN)=32 kHz, with a wait state,
pins are connected to VSS.
Topr=25° C
Topr=25° C when the clock
stops
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Unit
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47,
P50-P57, P60-P67, P72-P77, P80-P84, P86, P87,
P90-P97, P100-P107, P110-P114, P120-P127,
P130-P137, P140-P146, P150-P157(1)
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47,
P50-P57, P60-P67, P70-P77, P80-P84, P86, P87,
P90-P97, P100-P107, P110-P114, P120-P127,
P130-P137, P140-P146, P150-P157(1)
XOUT
P100-P107, P110-P114, P120-P127, P130-P137,
P140-P146, P150-P157(1), XIN, RESET, CNVSS,
BYTE
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47,
P50-P57, P60-P67, P70-P77, P80-P87, P90-P97,
P100-P107, P110-P114, P120-P127, P130-P137,
P140-P146, P150-P157(1), XIN, RESET, CNVSS,
Input Low ("L")
Current
Standard
Min
Typ
Vcc - 2.0
HOLD, RDY, TA0IN-TA4IN, TB0IN-TB5IN, INT0INT5, ADTRG, CTS0-CTS4, CLK0-CLK4,
IIL
RfXIN
RfXCIN
VRAM
ICC
Condition
30
50
1.5
10
2.5
40
µA
470
0.4
20
µA
26. Electrical Characteristics
M32C/83 Group (M32C/83, M32C/83T)
VCC=5V
Table 26.4 A/D Conversion Characteristics (VCC = AVCC = VREF = 4.2 to 5.5V, Vss = AVSS = 0V
at Topr = –20 to 85oC, f(XIN) = 32MHZ unless otherwise specified)
Symbol
Parameter
Standard
Measurement Condition
Min Typ
-
Resolution
INL
VREF=VCC
Integral Nonlinearity Error
DNL
-
Unit
Max
10
AN0 to AN7
ANEX0, ANEX1
±3
External op-amp
connection mode
±7
Bits
LSB
LSB
VREF=VCC=5V
LSB
LSB
Differential Nonlinearity Error
±1
LSB
Offset Error
±3
LSB
±3
LSB
40
kΩ
Gain Error
RLADDER
Resistor Ladder
tCONV
10-bit Conversion Time
VREF=VCC
8
2.1
µs
µs
tCONV
8-bit Conversion Time
1.8
tSAMP
Sample Time
0.2
VREF
Reference Voltage
2
VCC
V
VIA
Analog Input Voltage
0
VREF
V
µs
NOTES:
1. Divide f(XIN), if exceeding 16 MHz, to keep φAD frequency at 16 MHz or less.
Table 26.5 D/A Conversion Characteristics (VCC = VREF = 4.2 to 5.5V, VSS = AVSS = 0V
at Topr = –20 to 85oC, f(XIN) = 32MHZ unless otherwise specified)
Symbol
Parameter
Standard
Measurement Condition
Min Typ
-
Resolution
-
Absolute Accuracy
tSU
Setup Time
RO
Output Resistance
IVREF
Reference Power Supply
Input Current
Unit
Max
8
4
10
(Note 1)
1.0
%
3
µs
20
kΩ
1.5
mA
NOTES:
1. Measurement results when using one D/A converter. The DAi register (i=0, 1) of the
D/A converter not being used is set to "0016". The resistor ladder in the A/D converter is exclued.
IVREF flows even if the VCUT bit in the ADiCON1 register is set to "0" (no VREF connection).
Table 26.6 Flash Memory Version Electrical Characteristics
Standard
Parameter
Unit
Min
Typ
Max
Program Time (per page)
8
120
ms
Block Erase Time (per block)
50
600
ms
NOTES:
1. VCC= 4.2 to 5.5V (through VDC), 3.0 to 3.6V (not through VDC) at Topr= 0 to 60° C, unless
otherwise specified
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 419 of 488
Bits
26. Electrical Characteristics
M32C/83 Group (M32C/83, M32C/83T)
VCC=5V
Timing Requirements (VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to
85oC
unless otherwise specified)
Table 26.7 External Clock Input
Symbol
Parameter
Standard
Min
Unit
Max
tc
External Clock Input Cycle Time
33
ns
tw(H)
External Clock Input High ("H") Pulse Width
13
ns
tw(L)
External Clock Input Low ("L") Pulse Width
13
ns
tr
External Clock Rise Time
5
ns
tf
External Clock Fall Time
5
ns
Table 26.8 Memory Expansion and Microprocessor Modes
Symbol
tac1(RD-DB)
Parameter
Standard
Min
Data Input Access Time (RD standard, with no wait state)
Max
(Note 1)
Unit
ns
tac1(AD-DB)
Data Input Access Time (AD standard, CS standard, with no wait state)
(Note 1)
ns
tac2(RD-DB)
Data Input Access Time (RD standard, with a wait state)
(Note 1)
ns
tac2(AD-DB)
Data Input Access Time (AD standard, CS standard, with a wait state)
(Note 1)
ns
tac3(RD-DB)
Data Input Access Time (RD standard, when accessing a space with the multiplexed bus)
(Note 1)
ns
tac3(AD-DB)
Data Input Access Time (AD standard, CS standard, when accessing a space with the multiplexed
bus)
(Note 1)
ns
tac4(RAS-DB)
Data Input Access Time (RAS standard, when accessing a DRAM space)
(Note 1)
ns
tac4(CAS-DB)
Data Input Access Time (CAS standard, when accessing a DRAM space)
(Note 1)
ns
tac4(CAD-DB)
Data Input Access Time (CAD standard, when accessing a DRAM space)
(Note 1)
ns
tsu(DB-BCLK)
Data Input Setup Time
tsu(RDY-BCLK)
RDY Input Setup Time
26
ns
26
ns
tsu(HOLD-BCLK) HOLD Input Setup Time
30
ns
th(RD-DB)
Data Input Hold Time
0
ns
th(CAS-DB)
Data Input Hold Time
0
ns
th(BCLK-RDY)
RDY Input Hold Time
0
ns
th(BCLK-HOLD)
HOLD Input Hold Time
0
td(BCLK-HLDA)
HLDA Output Delay Time
ns
25
NOTES:
1. Values can be obtained from the following equations, according to BCLK frequecncy. Insert a wait state or lower
the operation frequency, f(BCLK), if the calculated value is negative.
tac1(RD – DB) =
10 9
f(BCLK) X 2
10 9
tac1(AD – DB) =
f(BCLK)
– 35
[ns]
– 35
[ns]
– 35
[ns] (m=3 with 1 wait state, m=5 with 2 wait states
and m=7 with 3 wait states)
– 35
[ns] (n=2 with 1 wait state, n=3 with 2 wait states
and n=4 with 3 wait states)
9
10 X m
tac2(RD – DB) = f(BCLK) X 2
9
10 X n
f(BCLK)
tac2(AD – DB) =
9
10 X m
tac3(RD – DB) = f(BCLK) X 2 – 35
tac3(AD – DB) =
10 9 X n
– 35
f(BCLK) X 2
[ns] (m=3 with 2 wait states and m=5 with 3 wait states)
[ns] (n=5 with 2 wait states and n=7 with 3 wait states)
tac4(RAS – DB) =
10 9X m
f(BCLK) X 2
– 35
[ns] (m=3 with 1 wait state and m=5 with 2 wait states)
tac4(CAS – DB) =
10 9 X n
f(BCLK) X 2
– 35
[ns] (n=1 with 1 wait state and n=3 when 2 wait states)
tac4(CAD – DB) =
10 9 X l
f(BCLK)
– 35
[ns] (l=1 with 1 wait state and l=2 with 2 wait states)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 420 of 488
ns
26. Electrical Characteristics
M32C/83 Group (M32C/83, M32C/83T)
VCC=5V
Timing Requirements
(VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 26.9 Timer A Input (Count Source Input in Event Counter Mode)
Symbol
Parameter
Standard
Min
Unit
Max
tc(TA)
TAiIN Input Cycle Time
tw(TAH)
TAiIN Input High ("H") Pulse Width
40
ns
tw(TAL)
TAiIN Input Low ("L") Pulse Width
40
ns
100
ns
Table 26.10 Timer A Input (Gate Input in Timer Mode)
Standard
Symbol
Parameter
Min
Max
Unit
tc(TA)
TAiIN Input Cycle Time
400
ns
tw(TAH)
TAiIN Input High ("H") Pulse Width
200
ns
tw(TAL)
TAiIN Input Low ("L") Pulse Width
200
ns
Table 26.11 Timer A Input (External Trigger Input in One-Shot Timer Mode)
Standard
Symbol
Parameter
Unit
Min
Max
tc(TA)
TAiIN Input Cycle Time
200
ns
tw(TAH)
TAiIN Input High ("H") Pulse Width
100
ns
tw(TAL)
TAiIN Input Low ("L") Pulse Width
100
ns
Table 26.12 Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard
Symbol
Parameter
Unit
Min
Max
tw(TAH)
TAiIN Input High ("H") Pulse Width
100
ns
tw(TAL)
TAiIN Input Low ("L") Pulse Width
100
ns
Table 26.13 Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min
Max
tc(UP)
TAiOUT Input Cycle Time
2000
ns
tw(UPH)
TAiOUT Input High ("H") Pulse Width
1000
ns
tw(UPL)
TAiOUT Input Low ("L") Pulse Width
1000
ns
tsu(UP-TIN)
TAiOUT Input Setup Time
400
ns
th(TIN-UP)
TAiOUT Input Hold Time
400
ns
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 421 of 488
26. Electrical Characteristics
M32C/83 Group (M32C/83, M32C/83T)
VCC=5V
Timing Requirements
(VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 26.14 Timer B Input (Count Source Input in Event Counter Mode)
Symbol
Parameter
Standard
Min
Max
Unit
tc(TB)
TBiIN Input Cycle Time (counted on one edge)
100
ns
tw(TBH)
TBiIN Input High ("H") Pulse Width (counted on one edge)
40
ns
tw(TBL)
TBiIN Input Low ("L") Pulse Width (counted on one edge)
40
ns
tc(TB)
TBiIN Input Cycle Time (counted on both edges)
200
ns
tw(TBH)
TBiIN Input High ("H") Pulse Width (counted on both edges)
80
ns
tw(TBL)
TBiIN Input Low ("L") Pulse Width (counted on both edges)
80
ns
Table 26.15 Timer B Input (Pulse Period Measurement Mode)
Symbol
Parameter
Standard
Min
Max
Unit
tc(TB)
TBiIN Input Cycle Time
400
ns
tw(TBH)
TBiIN Input High ("H") Pulse Width
200
ns
tw(TBL)
TBiIN Input Low ("L") Pulse Width
200
ns
Table 26.16 Timer B Input (Pulse Width Measurement Mode)
Standard
Symbol
Parameter
Unit
Min
Max
tc(TB)
TBiIN Input Cycle Time
400
ns
tw(TBH)
TBiIN Input High ("H") Pulse Width
200
ns
tw(TBL)
TBiIN Input Low ("L") Pulse Width
200
ns
Table 26.17 A/D Trigger Input
Symbol
Standard
Parameter
Min
Unit
Max
tc(AD)
ADTRG Input Cycle Time (required for re-trigger)
1000
ns
tw(ADL)
ADTRG Input Low ("L") Pulse Width
125
ns
Table 26.18 Serial I/O
Symbol
Parameter
Standard
Min
Max
Unit
tc(CK)
CLKi Input Cycle Time
200
ns
tw(CKH)
CLKi Input High ("H") Pulse Width
100
ns
tw(CKL)
CLKi Input Low ("L") Pulse Width
100
ns
td(C-Q)
TxDi Output Delay Time
th(C-Q)
TxDi Hold Time
0
80
ns
tsu(D-C)
RxDi Input Set Up Time
30
ns
th(C-Q)
RxDi Input Hold Time
90
ns
ns
_______
Table 26.19 External Interrupt INTi Input
Symbol
Parameter
Standard
Min
Max
Unit
tw(INH)
INTi Input High ("H") Pulse Width
250
ns
tw(INL)
INTi Input Low ("L") Pulse Width
250
ns
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 422 of 488
26. Electrical Characteristics
M32C/83 Group (M32C/83, M32C/83T)
VCC=5V
Switching Characteristics
(VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 26.20 Memory Expansion Mode and Microprocessor Mode (with No Wait State)
Symbol
Parameter
td(BCLK-AD)
Measurement
Condition
Standard
Min
Address Output Delay Time
Unit
Max
18
ns
th(BCLK-AD)
Address Output Hold Time (BCLK standard)
-3
ns
th(RD-AD)
Address Output Hold Time (RD standard)
0
ns
th(WR-AD)
Address Output Hold Time (WR standard)
(Note 1)
td(BCLK-CS)
Chip-select Signal Output Delay Time
ns
18
ns
th(BCLK-CS)
Chip-select Signal Output Hold Time (BCLK standard)
-3
ns
th(RD-CS)
Chip-select Signal Output Hold Time (RD standard)
0
ns
th(WR-CS)
Chip-select Signal Output Hold Time (WR standard)
td(BCLK-ALE)
ALE Signal Output Delay Time
th(BCLK-ALE)
ALE Signal Output Hold Time
td(BCLK-RD)
RD Signal Output Delay Time
th(BCLK-RD)
RD Signal Output Hold Time
td(BCLK-WR)
WR Signal Output Delay Time
See Figure 26.1 (Note 1)
ns
18
-2
ns
18
ns
18
ns
-5
th(BCLK-WR) WR Signal Output Hold Time
ns
ns
-3
ns
td(DB-WR)
Data Output Delay Time (WR standard)
(Note 1)
ns
th(WR-DB)
Data Output Hold Time (WR standard)
(Note 1)
ns
tw(WR)
WR Output Width
(Note 1)
ns
NOTES:
1. Values can be obtained from the following equations, according to BCLK frequency.
td(DB – WR) =
10 9
f(BCLK)
– 20
[ns]
th(WR – DB) =
10 9
f(BCLK) X 2
– 10
[ns]
th(WR – AD) =
10 9
f(BCLK) X 2
– 10
[ns]
th(WR – CS) =
10 9
f(BCLK) X 2
– 10
[ns]
tw(WR) =
10 9
f(BCLK) X 2
– 15
[ns]
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 423 of 488
26. Electrical Characteristics
M32C/83 Group (M32C/83, M32C/83T)
VCC=5V
Switching Characteristics
(VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 26.21 Memory Expansion Mode and Microprocessor Mode
(With a Wait State, Accessing an External Memory)
Symbol
Parameter
td(BCLK-AD)
Address Output Delay Time
th(BCLK-AD)
Address Output Hold Time (BCLK standard)
Measurement
Condition
Standard
Min
Unit
Max
18
-3
ns
ns
th(RD-AD)
Address Output Hold Time (RD standard)
0
ns
th(WR-AD)
Address Output Hold Time (WR standard)
(Note 1)
ns
td(BCLK-CS)
Chip-select Signal Output Delay Time
th(BCLK-CS)
Chip-select Signal Output Hold Time (BCLK standard)
-3
th(RD-CS)
Chip-select Signal Output Hold Time (RD standard)
0
th(WR-CS)
Chip-select Signal Output Hold Time (WR standard)
td(BCLK-ALE)
ALE Signal Output Delay Time
th(BCLK-ALE)
ALE Signal Output Hold Time
td(BCLK-RD)
RD Signal Output Delay Time
th(BCLK-RD)
RD Signal Output Hold Time
td(BCLK-WR)
WR Signal Output Delay Time
18
ns
ns
See Figure 26.1 (Note 1)
ns
18
ns
18
ns
18
ns
-2
ns
-5
th(BCLK-WR) WR Signal Output Hold Time
ns
ns
-3
ns
ns
td(DB-WR)
Data Output Delay Time (WR standard)
(Note 1)
th(WR-DB)
Data Output Hold Time (WR standard)
(Note 1)
ns
tw(WR)
WR Output Width
(Note 1)
ns
NOTES:
1. Values can be obtained from the following equations, according to BCLK frequency.
td(DB – WR) =
10 9 X n
f(BCLK)
– 20
[ns] (n=1 with 1 wait state, n=2 with 2 wait states
and n=3 with 3 wait states)
th(WR – DB) =
10 9
f(BCLK) X 2
– 10
[ns]
th(WR – AD) =
10 9
f(BCLK) X 2
– 10
[ns]
th(WR – CS) =
10 9
f(BCLK) X 2
– 10
[ns]
tw( WR) =
10 9 X n
f(BCLK) X 2
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
– 15
Page 424 of 488
[ns] (n=1 with 1 wait state, n=3 with 2 wait states
and n=5 with 3 wait states)
26. Electrical Characteristics
M32C/83 Group (M32C/83, M32C/83T)
VCC=5V
Switching Characteristics
(VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 26.22 Memory Expansion Mode and Microprocessor Mode
(With a Wait State, Accessing an External Memory and Selecting a Space with the
Multiplexed Bus)
Symbol
Measurement
Condition
Parameter
td(BCLK-AD)
Address Output Delay Time
th(BCLK-AD)
Address Output Hold Time (BCLK standard)
Standard
Min
Unit
Max
18
ns
-3
ns
th(RD-AD)
Address Output Hold Time (RD standard)
(Note 1)
ns
th(WR-AD)
Address Output Hold Time (WR standard)
(Note 1)
ns
td(BCLK-CS)
Chip-select Signal Output Delay Time
th(BCLK-CS)
Chip-select Signal Output Hold Time (BCLK standard)
th(RD-CS)
th(WR-CS)
18
ns
-3
ns
Chip-select Signal Output Hold Time (RD standard)
(Note 1)
ns
Chip-select Signal Output Hold Time (WR standard)
See Figure 26.1 (Note 1)
ns
td(BCLK-RD)
RD Signal Output Delay Time
th(BCLK-AD)
RD Signal Output Hold Time
td(BCLK-WR)
WR Signal Output Delay Time
18
ns
18
ns
-5
ns
th(BCLK-WR)
WR Signal Output Hold Time
-3
ns
td(DB-WR)
Data Output Delay Time (WR standard)
(Note 1)
ns
th(WR-DB)
Data Output Hold Time (WR standard)
(Note 1)
ns
td(BCLK-ALE)
ALE Signal Output Delay Time (BCLK standard)
th(BCLK-ALE)
ALE Signal Output Hold Time (BCLK standard)
td(AD-ALE)
18
ns
-2
ns
ALE Signal Output Delay Time (address standard)
(Note 1)
ns
th(ALE-AD)
ALE Signal Output Hold Time (address standard)
(Note 1)
ns
tdz(RD-AD)
Address Output High-Impedance Time
8
NOTES:
1. Values can be obtained from the following equations, according to BCLK frequency.
th(RD – AD) =
10 9
f(BCLK) X 2
– 10
[ns]
th(WR – AD) =
10 9
f(BCLK) X 2
– 10
[ns]
th(RD – CS) =
10 9
f(BCLK) X 2
– 10
[ns]
th(WR – CS) =
10 9
f(BCLK) X 2
– 10
[ns]
td(DB – WR) =
10 X m
– 25
f(BCLK) X 2
[ns] (m=3 with 2 wait states and m=5 with 3 wait states)
th(WR – DB) =
10 9
f(BCLK) X 2
– 10
[ns]
– 20
[ns]
– 10
[ns]
9
td(AD – ALE) =
th(ALE – AD) =
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
10
9
f(BCLK) X 2
10
9
f(BCLK) X 2
Page 425 of 488
ns
26. Electrical Characteristics
M32C/83 Group (M32C/83, M32C/83T)
VCC=5V
Switching Characteristics
(VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 26.23 Memory Expansion Mode and Microprocessor Mode
(With a Wait State, Accessing an External Memory and Selecting the DRAM Space)
Symbol
Standard
Measurement
Condition
Parameter
Min
td(BCLK-RAD) Row Address Output Delay Time
th(BCLK-RAD) Row Address Output Hold Time (BCLK standard)
th(BCLK-CAD) Column Address Output Hold Time (BCLK standard)
th(RAS-RAD)
Row Address Output Hold Time after RAS Output
tRP
RAS High ("H") Hold Time
18
See Figure 26.1
DB Signal Output Hold Time (BCLK standard)
-3
ns
ns
18
-3
10 9
f(BCLK) X 2
– 13
[ns]
tRP =
10 9X 3
f(BCLK) X 2
– 20
[ns]
tsu(DB – CAS) =
10 9
f(BCLK)
– 20
[ns]
9
tsu(CAS – RAS) =
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
10
f(BCLK) X 2
– 13
Page 426 of 488
[ns]
ns
ns
18
ns
-5
ns
(Note 1)
ns
-7
ns
(Note 1)
ns
NOTES:
1. Values can be obtained from the following equation, according to BCLK frequency.
th(RAS – RAD) =
ns
(Note 1)
th(BCLK-DW) DW Output Hold Time (BCLK standard)
tsu(CAS-RAS) CAS Output Setup Time before RAS Output (refresh)
ns
ns
td(BCLK-DW) DW Output Delay Time (BCLK standard)
th(BCLK-DB)
ns
ns
th(BCLK-CAS) CAS Output Hold Time (BCLK standard)
CAS Output Setup Time after DB Output
18
-3
td(BCLK-CAS) CAS Output Delay Time (BCLK standard)
tsu(DB-CAS)
ns
(Note 1)
td(BCLK-RAS) RAS Output Delay Time (BCLK standard)
th(BCLK-RAS) RAS Output Hold Time (BCLK standard)
18
-3
td(BCLK-CAD) Column Address Output Delay Time
Unit
Max
26. Electrical Characteristics
M32C/83 Group (M32C/83, M32C/83T)
P0
P1
P2
P3
P4
P5
P6
P7
30pF
P8
P9
P10
P11
P12
P13
Note 1
P14
P15
NOTES:
1. P11 to P15 are provided in the 144-pin package only.
Figure 26.1 P0 to P15 Measurement Circuit
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 427 of 488
26. Electrical Characteristics
M32C/83 Group (M32C/83, M32C/83T)
Vcc=5V
Memory Expansion Mode and Microprocessor Mode (with no wait state)
Read Timing
BCLK
td(BCLK-ALE)
18ns.max
th(BCLK-ALE)
-2ns.min
ALE
td(BCLK-CS)
th(BCLK-CS)
18ns.max(1)
-3ns.min
CSi
th(RD-CS)
tcyc
0ns.min
td(BCLK-AD)
th(BCLK-AD)
18ns.max(1)
-3ns.min
ADi
BHE
td(BCLK-RD)
18ns.max
th(RD-AD)
0ns.min
RD
th(BCLK-RD)
tac1(RD-DB)(2)
-5ns.min
tac1(AD-DB)(2)
Hi-Z
DB
tsu(DB-BCLK)
th(RD-DB)
26ns.min(1)
0ns.min
NOTES:
1. Values guaranteed only when the microcomputer is used independently.
A maximum of 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK).
2. Varies with operation frequency:
tac1(RD-DB)=(tcyc/2-35)ns.max
tac1(AD-DB)=(tcyc-35)ns.max
Write Timing (written in 2 cycles with no wait state)
BCLK
18ns.max
td(BCLK-ALE)
th(BCLK-ALE)
-2ns.min
ALE
th(BCLK-CS)
td(BCLK-CS)
18ns.max
-3ns.min
CSi
tcyc
th(WR-CS)(3)
td(BCLK-AD)
ADi
BHE
th(BCLK-AD)
18ns.max
-3ns.min
td(BCLK-WR)
18ns.max
th(WR-AD)(3)
tw(WR)(3)
WR,WRL,
WRH
th(BCLK-WR)
-3ns.min
td(DB-WR)(3)
th(WR-DB)(3)
DBi
NOTES:
3. Varies with operation frequency:
td(DB-WR)=(tcyc-20)ns.min
th(WR-DB)=(tcyc/2-10)ns.min
th(WR-AD)=(tcyc/2-10)ns.min
th(WR-CS)=(tcyc/2-10)ns.min
tw(WR)=(tcyc/2-15)ns.min
Figure 26.2 VCC=5V Timing Diagram (1)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 428 of 488
Measurement Conditions:
• VCC=4.2 to 5.5V
• Input high and low voltage: VIH=2.5V, VIL=0.8V
• Output high and low voltage: VOH=2.0V, VOL=0.8V
26. Electrical Characteristics
M32C/83 Group (M32C/83, M32C/83T)
Vcc=5V
Memory Expansion Mode and Microprocessor Mode (with a wait state)
Read Timing
BCLK
18ns.max
td(BCLK-ALE) th(BCLK-ALE)
-2ns.min
ALE
th(BCLK-CS)
td(BCLK-CS)
-3ns.min
18ns.max(1)
CSi
th(RD-CS)
tcyc
0ns.min
td(BCLK-AD)
ADi
BHE
th(BCLK-AD)
18ns.max(1)
-3ns.min
td(BCLK-RD)
18ns.max
th(RD-AD)
0ns.min
RD
th(BCLK-RD)
tac2(RD-DB)(2)
-5ns.min
tac2(AD-DB)(2)
DB
Hi-Z
tsu(DB-BCLK)
26ns.min(1)
th(RD-DB)
0ns.min
Notes :
1. Value guaranteed only when the microcomputer is used independently.
A maximum of 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK).
2. Varies with operation frequency:
tac2(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 with 1 wait state, m=5 with 2 wait states and m=7 with 3 wait states.)
tac2(AD-DB)=(tcyc x n-35)ns.max (n=2 with 1 wait state, n=3 with 2 wait states and n=4 with 3 wait states.)
Write Timing (written in 2 cycles with no wait state)
BCLK
18ns.max
td(BCLK-ALE)
th(BCLK-ALE)
-2ns.min
ALE
th(BCLK-CS)
td(BCLK-CS)
-3ns.min
18ns.max
CSi
tcyc
th(WR-CS)(3)
th(BCLK-AD)
td(BCLK-AD)
ADi
BHE
-3ns.min
18ns.max
td(BCLK-WR)
WR,WRL,
WRH
tw(WR)(3)
th(WR-AD)(3)
18ns.max
th(BCLK-WR)
-3ns.min
td(DB-WR)(3)
th(WR-DB)(3)
DBi
NOTES:
3. Varies with operation frequency:
td(DB-WR)=(tcyc x n-20)ns.min
(n=1 with 1 wait state, n=2 with 2 wait states and n=3 with 3 wait states)
th(WR-DB)=(tcyc/2-10)ns.min
th(WR-AD)=(tcyc/2-10)ns.min
th(WR-CS)=(tcyc/2-10)ns.min
tw(WR)=(tcyc/2 x n-15)ns.min
(n=1 with 1 wait state, n=3 with 2 wait states and n=5 with 3 wait states)
Figure 26.3 VCC=5V Timing Diagram (2)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 429 of 488
Measurement conditions
• VCC=4.2 to 5.5V
• Input high and low voltage:
VIH=2.5V, VIL=0.8V
• Output high and low voltage:
VOH=2.0V, VOL=0.8V
26. Electrical Characteristics
M32C/83 Group (M32C/83, M32C/83T)
Vcc=5V
Memory Expansion Mode and Microprocessor Mode
(with a wait state, when accessing an external memory and using the multiplexed bus)
Read Timing
BCLK
18ns.max
th(BCLK-ALE)
td(BCLK-ALE)
-2ns.min
ALE
th(BCLK-CS)
tcyc
td(BCLK-CS)
-3ns.min
18ns.max
th(RD-CS)(1)
CSi
td(AD-ALE)(1)
ADi
/DBi
th(ALE-AD)(1)
Address
Data input
tdz(RD-AD)
8ns.max
tsu(DB-BCLK)
td(BCLK-AD)
ADi
BHE
tac3(AD-DB)(1)
td(BCLK-RD)
th(BCLK-RD)
18ns.max
0ns.min
26ns.min
tac3(RD-DB)(1)
18ns.max
Address
th(RD-DB)
th(BCLK-AD)
-3ns.min
th(RD-AD)(1)
-5ns.min
RD
NOTES:
1. Varies with operation frequency:
td(AD-ALE)=(tcyc/2-20)ns.min
th(ALE-AD)=(tcyc/2-10)ns.min, th(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min
tac3(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 with 2 wait states and m=5 with 3 wait states)
tac3(AD-DB)=(tcyc/2 x n-35)ns.max (n=5 with 2 wait states and n=7 with 3 wait states)
Write Timing (written in 2 cycles with no wait state)
BCLK
18ns.max
th(BCLK-ALE)
td(BCLK-ALE)
-2ns.min
ALE
th(BCLK-CS)
tcyc
td(BCLK-CS)
th(WR-CS)(2)
18ns.max
CSi
th(ALE-AD)(1)
td(AD-ALE)(2)
ADi
/DBi
Data output
Address
td(DB-WR)(2)
td(BCLK-AD)
Address
th(WR-DB)(2)
td(BCLK-WR)
18ns.max
WR,WRL,
WRH
NOTES:
2. Varies with operation frequency:
td(AD-ALE)=(tcyc/2-20)ns.min
th(ALE-AD)=(tcyc/2-10)ns.min, th(WR-AD)=(tcyc/2-10)ns.min
th(WR-CS)=(tcyc/2-10)ns.min, th(WR-DB)=(tcyc/2-10)ns.min
td(DB-WR)=(tcyc/2 x m-25)ns.min
Figure 26.4 VCC=5V Timing Diagram (3)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 430 of 488
th(BCLK-AD)
-3ns.min
18ns.max
ADi
BHE
-3ns.min
th(BCLK-WR)
th(WR-AD)(2)
-3ns.min
Measurement Conditions:
• VCC=4.2 to 5.5V
• Input high and low voltage:
VIH=2.5V, VIL=0.8V
• Output high and low voltage:
VOH=2.0V, VOL=0.8V
26. Electrical Characteristics
M32C/83 Group (M32C/83, M32C/83T)
Memory Expansion Mode and Microprocessor Mode
(When accessing the DRAM area)
Read Timing
BCLK
tcyc
td(BCLK-RAD) th(BCLK-RAD)
18ns.max -3ns.min
MAi
td(BCLK-CAD)
th(BCLK-CAD)
18ns.max(1)
-3ns.min
Column address
Row address
th(RAS-RAD)(2)
tRP(2)
RAS
td(BCLK-RAS)
CASL
CASH
18ns.max(1)
td(BCLK-CAS)
18ns.max(1)
th(BCLK-RAS)
-3ns.min
th(BCLK-CAS)
-3ns.min
DW
tac4(CAS-DB)(2)
tac4(CAD-DB)(2)
tac4(RAS-DB)(2)
Hi-Z
DB
tsu(DB-BCLK)
26ns.min(1)
th(CAS-DB)
0ns.min
NOTES:
1. Values guaranteed only when the microcomputer is used independently.
A maximum of 35ns is guaranteed for the following combinations.
td(BCLK-RAS) + tsu(DB-BCLK)
td(BCLK-CAS) + tsu(DB-BCLK)
td(BCLK-CAD) + tsu(DB-BCLK)
2. Varies with operation frequency:
tac4(RAS-DB)=(tcyc/2 x m-35)ns.max (m=3 with 1 wait state and m=5 with 2 wait states)
tac4(CAS-DB)=(tcyc/2 x n-35)ns.max (n=1 with 1 wait state and n=3 with 2 wait states)
tac4(CAD-DB)=(tcyc x l-35)ns.max (l=1 with 1 wait state and l=2 with 2 wait states)
th(RAS-RAD)=(tcyc/2-13)ns.min
tRP=(tcyc/2 x 3-20)ns.min
Measurement Conditions:
• VCC=4.2 to 5.5V
• Input high and low voltage: VIH=2.5V, VIL=0.8V
• Output high and low voltage: VOH=2.0V, VOL=0.8V
Figure 26.5 VCC=5V Timing Diagram (4)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 431 of 488
Vcc=5V
26. Electrical Characteristics
M32C/83 Group (M32C/83, M32C/83T)
Memory Expansion Mode and Microprocessor Mode
Vcc=5V
(When accessing the DRAM area)
Write Timing
BCLK
tcyc
td(BCLK-RAD)
18ns.max
MAi
th(BCLK-RAD)
-3ns.min
td(BCLK-CAD)
th(BCLK-CAD)
18ns.max
-3ns.min
Column address
Row address
th(RAS-RAD)(1)
tRP(1)
RAS
td(BCLK-RAS)
18ns.max
td(BCLK-CAS)
18ns.max
CASL
CASH
th(BCLK-RAS)
-3ns.min
th(BCLK-CAS)
td(BCLK-DW)
-3ns.min
18ns.max
DW
th(BCLK-DW)
tsu(DB-CAS)(1)
DB
-5ns.min
Hi-Z
th(BCLK-DB)
-7ns.min
NOTES:
1. Varies with operation frequency:
th(RAS-RAD)=(tcyc/2-13)ns.min
tRP=(tcyc/2 x 3-20)ns.min
tsu(DB-CAS)=(tcyc-20)ns.min
Measurement Conditions:
• VCC=4.2 to 5.5V
• Input high and low voltage: VIH=2.5V, VIL=0.8V
• Output high and low voltage: VOH=2.0V, VOL=0.8V
Figure 26.6 VCC=5V Timing Diagram (5)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 432 of 488
26. Electrical Characteristics
M32C/83 Group (M32C/83, M32C/83T)
Memory Expansion Mode and Microprocessor Mode
Refresh Timing (CAS-before-RAS refresh)
Vcc=5V
BCLK
td(BCLK-RAS)
tcyc
18ns.max
RAS
th(BCLK-RAS)
tsu(CAS-RAS)(1)
CASL
CASH
-3ns.min
td(BCLK-CAS)
th(BCLK-CAS)
-3ns.min
18ns.max
DW
NOTES :
1. Varies with operation frequency:
tsu(CAS-RAS)=(tcyc/2-13)ns.min
Refresh Timing (Self-refresh)
BCLK
td(BCLK-RAS)
tcyc
18ns.max
RAS
th(BCLK-RAS)
tsu(CAS-RAS)(2)
CASL
CASH
td(BCLK-CAS)
18ns.max
DW
NOTES:
2. Varies with operation frequency:
tsu(CAS-RAS)=(tcyc/2-13)ns.min
Measurement Conditions:
• VCC=4.2 to 5.5V
• Input high and low voltage: VIH=2.5V, VIL=0.8V
• Output high and low voltage: VOH=2.0V, VOL=0.8V
Figure 26.7 VCC=5V Timing Diagram (6)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 433 of 488
-3ns.min
th(BCLK-CAS)
-3ns.min
26. Electrical Characteristics
M32C/83 Group (M32C/83, M32C/83T)
Vcc=5V
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Counter increment/
decrement input)
In event counter mode
TAiIN input
(When counting on the falling edge)
th(TIN–UP)
tsu(UP–TIN)
TAiIN input
(When counting on the rising edge)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C–Q)
TxDi
td(C–Q)
tsu(D–C)
th(C–D)
RxDi
tw(INL)
INTi input
tw(INH)
NMI input
2 clock cycles + 300ns
ore more ("L" width)
Figure 26.8 VCC=5V Timing Diagram (7)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 434 of 488
2 clock cycles + 300ns
or more
26. Electrical Characteristics
M32C/83 Group (M32C/83, M32C/83T)
Vcc=5V
Memory Expansion Mode and Microprocessor Mode
(Valid only with a wait state)
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
th(BCLK–RDY)
tsu(RDY–BCLK)
(Valid with a wait state or with no wait state)
BCLK
tsu(HOLD–BCLK)
th(BCLK–HOLD)
HOLD input
HLDA output
td(BCLK–HLDA)
P0, P1, P2,
P3, P4,
P50 to P52
td(BCLK–HLDA)
Hi–Z
Measurement Conditions:
• VCC=4.2 to 5.5V
• Input high and low voltage: VIH=4.0V, VIL=1.0V
• Output high and low voltage: VOH=2.5V, VOL=2.5V
Figure 26.9 VCC=5V Timing Diagram (8)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 435 of 488
26. Electrical Characteristics
M32C/83 Group (M32C/83, M32C/83T)
VCC=3.3V
Table 26.24 Electrical Characteristics (VCC=3.0 to 3.6V, VSS=0V at Topr = –20 to
f(XIN)=20MHZ unless otherwise specified)
Symbol
VOH
VOL
Parameter
Output High ("H")
Voltage
Output Low ("L")
Voltage
VT+-VT-
Hysteresis
IIH
Input High ("H")
Current
IIL
Input Low ("L")
Current
RPULLUP
RfXIN
RfXCIN
VRAM
ICC
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47,
P50-P57, P60-P67, P72-P77, P80-P84, P86, P87,
P90-P97, P100-P107, P110-P114, P120-P127,
P130-P137, P140-P146, P150-P157(1)
XOUT
Condition
IOH=-1mA
IOH=-0.1mA
XCOUT
No load applied
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47,
P50-P57, P60-P67, P70-P77, P80-P84, P86, P87,
IOL=1mA
P90-P97, P100-P107, P110-P114, P120-P127,
P130-P137, P140-P146, P150-P157(1)
XOUT
IOL=0.1mA
XCOUT
No load applied
HOLD, RDY, TA0IN-TA4IN, TB0IN-TB5IN, INT0INT5, ADTRG, CTS0-CTS4, CLK0-CLK4, TA0OUTTA4OUT, NMI, KI0-KI3, RxD0-RxD4, SCL0-SCL4,
SDA0-SDA4
RESET
VI=3V
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47,
P50-P57, P60-P67, P70-P77, P80-P87, P90-P97,
P100-P107, P110-P114, P120-P127, P130-P137,
P140-P146, P150-P157(1), XIN, RESET, CNVSS,
BYTE
VI=0V
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47,
P50-P57, P60-P67, P70-P77, P80-P87, P90-P97,
P100-P107, P110-P114, P120-P127, P130-P137,
P140-P146, P150-P157(1), XIN, RESET, CNVSS,
BYTE
Pull-up Resistance
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47,
VI=0V
P50-P57, P60-P67, P72-P77, P80-P84, P86, P87,
P90-P97, P100-P107, P110-P114, P120-P127,
P130-P137, P140-P146, P150-P157(1)
Feedback Resistance XIN
Feedback Resistance XCIN
RAM Standby
Through VDC
Voltage
Not through VDC
Power Supply
Measurement condition:
f(XIN)=20 MHz, square wave,
Current
In single-chip mode, output
no division
pins are left open and other
f(XCIN)=32 kHz, with a wait state,
pins are connected to VSS.
not through VDC, Topr=25° C
f(XCIN)=32 kHz, with a wait state,
through VDC, Topr=25° C
Topr=25° C when the clock stops
NOTES:
1. P11 to P15 are provided in the 144-pin package only.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 436 of 488
85oC,
Standard
Unit
Min
Typ Max
Vcc-0.6
V
2.7
V
3.3
V
0.5
V
0.5
V
0
V
0.2
1.0
V
0.2
1.8
4.0
V
µA
-4.0
µA
500
kΩ
38
MΩ
MΩ
V
V
mA
66
120
3.0
20.0
2.5
2.0
26
5.0
µA
340
µA
0.4
20
µA
26. Electrical Characteristics
M32C/83 Group (M32C/83, M32C/83T)
VCC=3.3V
Table 26.25 A/D Conversion Characteristics (VCC = AVCC = VREF = 3.0 to 3.6V,
at Topr = –20 to 85oC, f(XIN) = 20MHZ unless otherwise specified)
Symbol
INL
Resolution
Standard
Min Typ
Unit
Max
VREF=VCC
Integral Nonlinearity Error
DNL
Measurement
Condition
Parameter
VSS = AVSS = 0V
No S&H function (8-bit) VCC=VREF=3.3V
10
Bits
±2
LSB
Differential Nonlinearity Error No S&H function (8-bit)
±1
LSB
-
Offset Error
No S&H function (8-bit)
±2
LSB
-
Gain Error
No S&H function (8-bit)
±2
LSB
40
kΩ
RLADDER
Resistor Ladder
VREF=VCC
8
µs
tCONV
8-bit Conversion Time
4.9
VREF
Reference Voltage
3.0
VCC
V
VIA
Analog Input Voltage
0
VREF
V
S&H: Sample and hold
NOTES:
1. Divide f(XIN), if exceeding 10 MHz, to keep φAD frequency at 10 MHz or less.
Table 26.26 D/A Conversion Characteristics (VCC = VREF = 3.0 to 3.6V, VSS = AVSS = 0V
at Topr = –20 to 85oC, f(XIN) = 20MHZ unless otherwise specified)
Symbol
Parameter
Standard
Measurement Condition
Min Typ
tSU
-
Resolution
-
Absolute Accuracy
Setup Time
RO
Output Resistance
IVREF
Reference Power Supply Input Current
4
Unit
Max
10
(Note 1)
8
Bits
1.0
%
3
µs
20
kΩ
1.0
mA
NOTES:
1. Measurement results when using one D/A converter. The DAi register (i=0, 1) of the D/A converter not
being used is set to "0016". The resistor ladder in the A/D converter is exclued.
IVREF flows even if the VCUT bit in the ADiCON1 register is set to "0" (no VREF connection).
Table 26.27 Flash Memory Version Electrical Characteristics
Standard
Parameter
Unit
Min
Typ
Max
Program Time (per page)
8
120
ms
Block Erase Time (per block)
50
600
ms
NOTES:
1. VCC= 4.2 to 5.5V (through VDC), 3.0 to 3.6V (not through VDC) at Topr= 0 to 60° C, unless
otherwise specified
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 437 of 488
26. Electrical Characteristics
M32C/83 Group (M32C/83, M32C/83T)
VCC=3.3V
Timing Requirements (VCC = 3.0 to 3.6V, VSS = 0V at Topr = –20 to
85oC
unless otherwise specified)
Table 26.28 External Clock Input
Symbol
Parameter
Standard
Min
Unit
Max
tc
External Clock Input Cycle Time
50
ns
tw(H)
External Clock Input High ("H") Pulse Width
22
ns
tw(L)
External Clock Input Low ("L") Pulse Width
22
tr
External Clock Rise Time
5
ns
tf
External Clock Fall Time
5
ns
ns
Table 26.29 Memory Expansion Mode and Microprocessor Mode
Symbol
Parameter
Standard
Min
Max
Unit
tac1(RD-DB)
Data Input Access Time (RD standard, with no wait state)
(Note 1)
ns
ns
tac1(AD-DB)
Data Input Access Time (AD standard, CS standard, with no wait state)
(Note 1)
tac2(RD-DB)
Data Input Access Time (RD standard, with a wait state)
(Note 1)
ns
tac2(AD-DB)
Data Input Access Time (AD standard, CS standard, with a wait state)
(Note 1)
ns
tac3(RD-DB)
Data Input Access Time (RD standard, when accessing a space with the multiplexed bus)
(Note 1)
ns
tac3(AD-DB)
Data Input Access Time (AD standard, CS standard, when accessing a space with the multiplexed bus)
(Note 1)
ns
tac4(RAS-DB)
Data Input Access Time (RAS standard, when accessing a DRAM space)
(Note 1)
ns
tac4(CAS-DB)
Data Input Access Time (CAS standard, when accessing a DRAM space)
(Note 1)
ns
tac4(CAD-DB)
Data Input Access Time (CAD standard, when accessing a DRAM space)
(Note 1)
ns
tsu(DB-BCLK)
Data Input Setup Time
30
ns
tsu(RDY-BCLK)
RDY Input Setup Time
40
ns
tsu(HOLD-BCLK) HOLD Input Setup Time
60
ns
th(RD-DB)
Data Input Hold Time
0
ns
th(CAS-DB)
Data Input Hold Time
0
ns
ns
th(BCLK-RDY)
RDY Input Hold Time
0
th(BCLK-HOLD)
HOLD Input Hold Time
0
td(BCLK-HLDA)
HLDA Output Delay Time
NOTES:
1. Values can be obtained from the following equations, according to BCLK frequency. Insert a wait state or lower
operation frequency, f(BCLK), if the calculated value is negative.
tac1(RD – DB) =
10 9
f(BCLK) X 2
10 9
tac1(AD – DB) =
f(BCLK)
– 35
[ns]
– 35
[ns]
– 35
[ns] (m=3 with 1 wait state, m=5 with 2 wait states
and m=7 with 3 wait states)
– 35
[ns] (n=2 with 1 wait state, n=3 with 2 wait states
and n=4 with 3 wait states)
9
10 X m
tac2(RD – DB) = f(BCLK) X 2
9
10 X n
f(BCLK)
tac2(AD – DB) =
9
10 X m
tac3(RD – DB) = f(BCLK) X 2 – 35
tac3(AD – DB) =
10 9 X n
– 35
f(BCLK) X 2
[ns] (m=3 with 2 wait states and m=5 with 3 wait states)
[ns] (n=5 with 2 wait states and n=7 with 3 wait states)
tac4(RAS – DB) =
10 9X m
f(BCLK) X 2
– 35
[ns] (m=3 with 1 wait state and m=5 with 2 wait states)
tac4(CAS – DB) =
10 9 X n
f(BCLK) X 2
– 35
[ns] (n=1 with 1 wait state and n=3 when 2 wait states)
tac4(CAD – DB) =
10 9 X l
f(BCLK)
– 35
[ns] (l=1 with 1 wait state and l=2 with 2 wait states)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 438 of 488
ns
25
ns
26. Electrical Characteristics
M32C/83 Group (M32C/83, M32C/83T)
VCC=3.3V
Timing Requirements
(VCC = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 26.30 Timer A Input (Count Source Input in Event Counter Mode)
Symbol
Parameter
Standard
Min
Unit
Max
tc(TA)
TAiIN Input Cycle Time
100
ns
tw(TAH)
TAiIN Input High ("H") Pulse Width
40
ns
tw(TAL)
TAiIN Input Low ("L") Pulse Width
40
ns
Table 26.31 Timer A Input (Gate Input in Timer Mode)
Standard
Symbol
Parameter
Min
Max
Unit
tc(TA)
TAiIN Input Cycle Time
400
ns
tw(TAH)
TAiIN Input High ("H") Pulse Width
200
ns
tw(TAL)
TAiIN Input Low ("L") Pulse Width
200
ns
Table 26.32 Timer A Input (External Trigger Input in One-Shot Timer Mode)
Standard
Symbol
Parameter
Unit
Min
Max
tc(TA)
TAiIN Input Cycle Time
200
ns
tw(TAH)
TAiIN Input High ("H") Pulse Width
100
ns
tw(TAL)
TAiIN Input Low ("L") Pulse Width
100
ns
Table 26.33 Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard
Symbol
Parameter
Unit
Min
Max
tw(TAH)
TAiIN Input High ("H") Pulse Width
100
ns
tw(TAL)
TAiIN Input Low ("L") Pulse Width
100
ns
Table 26.34 Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min
Max
tc(UP)
TAiOUT Input Cycle Time
2000
ns
tw(UPH)
TAiOUT Input High ("H") Pulse Width
1000
ns
tw(UPL)
TAiOUT Input Low ("L") Pulse Width
1000
ns
tsu(UP-TIN)
TAiOUT Input Setup Time
400
ns
th(TIN-UP)
TAiOUT Input Hold Time
400
ns
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 439 of 488
26. Electrical Characteristics
M32C/83 Group (M32C/83, M32C/83T)
VCC=3.3V
Timing Requirements
(VCC = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 26.35 Timer B input (Count Source Input in Event Counter Mode)
Symbol
Parameter
Standard
Min
Max
Unit
tc(TB)
TBiIN Input Cycle Time (counted on one edge)
100
ns
tw(TBH)
TBiIN Input High ("H") Pulse Width (counted on one edge)
40
ns
tw(TBL)
TBiIN Input Low ("L") Pulse Width (counted on one edge)
40
ns
tc(TB)
TBiIN Input Cycle Time (counted on both edges)
200
ns
tw(TBH)
TBiIN Input High ("H") Pulse Width (counted on both edges)
80
ns
tw(TBL)
TBiIN Input Low ("L") Pulse Width (counted on both edges)
80
ns
Table 26.36 Timer B input (Pulse Period Measurement Mode)
Symbol
Parameter
Standard
Min
Max
Unit
tc(TB)
TBiIN Input Cycle Time
400
ns
tw(TBH)
TBiIN Input High ("H") Pulse Width
200
ns
tw(TBL)
TBiIN Input Low ("L") Pulse Width
200
ns
Table 26.37 Timer B input (Pulse Width Measurement Mode)
Standard
Symbol
Parameter
Unit
Min
Max
tc(TB)
TBiIN Input Cycle Time
400
ns
tw(TBH)
TBiIN Input High ("H") Pulse Width
200
ns
tw(TBL)
TBiIN Input Low ("L") Pulse Width
200
ns
Table 26.38 A/D Trigger Input
Symbol
Standard
Parameter
Min
Unit
Max
tc(AD)
ADTRG Input High ("H") Pulse Width (required for re-trigger)
1000
ns
tw(ADL)
ADTRG Input Low ("L") Pulse Width
125
ns
Table 26.39 Serial I/O
Symbol
Parameter
Standard
Min
Max
Unit
tc(CK)
CLKi Input Cycle Time
200
ns
tw(CKH)
CLKi Input High ("H") Pulse Width
100
ns
tw(CKL)
CLKi Input Low ("L") Pulse Width
100
ns
td(C-Q)
TxDi Output Delay Time
th(C-Q)
TxDi Hold Time
0
80
ns
ns
tsu(D-C)
RxDi Input Set Up Time
30
ns
th(C-Q)
RxDi Input Hold Time
90
ns
_______
Table 26.40 External Interrupt INTi input
Symbol
Parameter
Standard
Min
Max
Unit
tw(INH)
INTi Input High ("H") Pulse Width
250
ns
tw(INL)
INTi Input Low ("L") Pulse Width
250
ns
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 440 of 488
26. Electrical Characteristics
M32C/83 Group (M32C/83, M32C/83T)
VCC=3.3V
Switching Characteristics
(VCC = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC, unless otherwise specified)
Table 26.41 Memory Expansion Mode and Microprocessor Mode (with No Wait State)
Symbol
Parameter
td(BCLK-AD)
Address Output Delay Time
th(BCLK-AD)
Address Output Hold Time (BCLK standard)
Measurement
Condition
Standard
Min
Unit
Max
18
0
ns
ns
th(RD-AD)
Address Output Hold Time (RD standard)
0
ns
th(WR-AD)
Address Output Hold Time (WR standard)
(Note 1)
ns
td(BCLK-CS)
Chip-select Signal Output Delay Time
18
ns
th(BCLK-CS)
Chip-select Signal Output Hold Time (BCLK standard)
0
ns
th(RD-CS)
Chip-select Signal Output Hold Time (RD standard)
0
ns
th(WR-CS)
Chip-select Signal Output Hold Time (WR standard)
(Note 1)
ns
td(BCLK-ALE)
ALE Signal Output Delay Time
th(BCLK-ALE)
ALE Signal Output Hold Time
td(BCLK-RD)
RD Signal Output Delay Time
th(BCLK-RD)
RD Signal Output Hold Time
td(BCLK-WR)
WR Signal Output Delay Time
See Figure 26.1
18
ns
18
ns
-2
ns
-3
ns
18
th(BCLK-WR) WR Signal Output Hold Time
ns
0
ns
(Note 1)
ns
td(DB-WR)
Data Output Delay Time (WR standard)
th(WR-DB)
Data Output Hold Time (WR standard)
(Note 1)
ns
tw(WR)
WR Output Width
(Note 1)
ns
NOTES:
1. Values can be obtained from the following equations according to the BCLK frequency.
td(DB – WR) =
10 9
f(BCLK)
– 20
[ns]
th(WR – DB) =
10 9
f(BCLK) X 2
– 10
[ns]
th(WR – AD) =
10 9
f(BCLK) X 2
– 10
[ns]
th(WR – CS) =
10 9
f(BCLK) X 2
– 10
[ns]
tw(WR) =
10 9
f(BCLK) X 2
– 15
[ns]
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 441 of 488
26. Electrical Characteristics
M32C/83 Group (M32C/83, M32C/83T)
VCC=3.3V
Switching Characteristics
(VCC = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 26.42 Memory Expansion Mode and Microprocessor Mode
(With a Wait State, Accessing an External Memory)
Symbol
Parameter
td(BCLK-AD)
Address Output Delay Time
th(BCLK-AD)
Address Output Hold Time (BCLK standard)
Measurement
Condition
Standard
Min
Unit
Max
18
0
ns
ns
th(RD-AD)
Address Output Hold Time (RD standard)
0
ns
th(WR-AD)
Address Output Hold Time (WR standard)
(Note 1)
ns
td(BCLK-CS)
Chip-select Signal Output Delay Time
th(BCLK-CS)
Chip-select Signal Output Hold Time (BCLK standard)
0
ns
th(RD-CS)
Chip-select Signal Output Hold Time (RD standard)
0
ns
th(WR-CS)
Chip-select Signal Output Hold Time (WR standard)
td(BCLK-ALE)
ALE Signal Output Delay Time
th(BCLK-ALE)
ALE Signal Output Hold Time
td(BCLK-RD)
RD Signal Output Delay Time
th(BCLK-RD)
RD Signal Output Hold Time
td(BCLK-WR)
WR Signal Output Delay Time
18
See Figure 26.1 (Note 1)
ns
18
ns
18
ns
18
ns
-2
ns
-3
th(BCLK-WR) WR Signal Output Hold Time
ns
ns
0
ns
ns
td(DB-WR)
Data Output Delay Time (WR standard)
(Note 1)
th(WR-DB)
Data Output Hold Time (WR standard)
(Note 1)
ns
tw(WR)
WR Output Width
(Note 1)
ns
NOTES:
1. Values can be obtained from the following equations, according to BCLK frequency.
td(DB – WR) =
10 9 X n
f(BCLK)
– 20
[ns] (n=1 with 1 wait state, n=2 with 2 wait states
and n=3 with 3 wait states)
th(WR – DB) =
10 9
f(BCLK) X 2
– 10
[ns]
th(WR – AD) =
10 9
f(BCLK) X 2
– 10
[ns]
th(WR – CS) =
10 9
f(BCLK) X 2
– 10
[ns]
tw( WR) =
10 9 X n
f(BCLK) X 2
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
– 15 [ns] (n=1 with 1 wait state, n=3 with 2 wait states
and n=5 with 3 wait states)
Page 442 of 488
26. Electrical Characteristics
M32C/83 Group (M32C/83, M32C/83T)
VCC=3.3V
Switching Characteristics
(VCC = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 26.43 Memory Expansion Mode and Microprocessor Mode
(With a Wait State, Accessing an External Memory and Selecting a Space with the
Multiplexed Bus)
Symbol
td(BCLK-AD)
Parameter
Measurement
Condition
Standard
Min
Address Output Delay Time
Unit
Max
18
ns
th(BCLK-AD)
Address Output Hold Time (BCLK standard)
0
ns
th(RD-AD)
Address Output Hold Time (RD standard)
(Note 1)
ns
th(WR-AD)
Address Output Hold Time (WR standard)
(Note 1)
td(BCLK-CS)
Chip-select Signal Output Delay Time
th(BCLK-CS)
Chip-select Signal Output Hold Time (BCLK standard)
th(RD-CS)
ns
18
ns
0
ns
Chip-select Signal Output Hold Time (RD standard)
(Note 1)
ns
th(WR-CS)
Chip-select Signal Output Hold Time (WR standard)
See Figure 26.1 (Note 1)
td(BCLK-RD)
RD Signal Output Delay Time
th(BCLK-AD)
RD Signal Output Hold Time
ns
18
-3
td(BCLK-WR)
WR Signal Output Delay Time
th(BCLK-WR)
WR Signal Output Hold Time
td(DB-WR)
ns
ns
18
ns
0
ns
Data Output Delay Time (WR standard)
(Note 1)
ns
(Note 1)
th(WR-DB)
Data Output Hold Time (WR standard)
td(BCLK-ALE)
ALE Signal Output Delay Time (BCLK standard)
th(BCLK-ALE)
ALE Signal Output Hold Time (BCLK standard)
ns
18
-2
ns
ns
td(AD-ALE)
ALE Signal Output Delay Time (address standard)
(Note 1)
ns
th(ALE-AD)
ALE Signal Output Hold Time (address standard)
(Note 1)
ns
tdz(RD-AD)
Address Output High-Impedance Time
8
NOTES:
1. Values can be obtained from the following equations, according to BCLK frequency.
th(RD – AD) =
10 9
f(BCLK) X 2
– 10
[ns]
th(WR – AD) =
10 9
f(BCLK) X 2
– 10
[ns]
th(RD – CS) =
10 9
f(BCLK) X 2
–10
[ns]
th(WR – CS) =
10 9
f(BCLK) X 2
– 10
[ns]
td(DB – WR) =
10 X m
– 25
f(BCLK) X 2
[ns] (m=3 with 2 wait states and m=5 with 3 wait states)
th(WR – DB) =
10 9
f(BCLK) X 2
– 10
[ns]
td(AD – ALE) =
10 9
f(BCLK) X 2
– 20
[ns]
th(ALE – AD) =
10 9
f(BCLK) X 2
– 10
[ns]
9
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 443 of 488
ns
26. Electrical Characteristics
M32C/83 Group (M32C/83, M32C/83T)
VCC=3.3V
Switching Characteristics
(VCC = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 26.44 Memory Expansion Mode and Microprocessor Mode
(With a Wait State, Accessing an External Memory and Selecting the DRAM Area)
Symbol
Measurement
Condition
Parameter
Standard
Min
td(BCLK-RAD) Row Address Output Delay Time
th(BCLK-RAD) Row Address Output Hold Time (BCLK standard)
th(BCLK-CAD) Column Address Output Hold Time (BCLK standard)
th(RAS-RAD)
Row Address Output Hold Time after RAS Output
tRP
RAS High ("H") Hold Time
tsu(DB-CAS)
CAS Output Setup Time after DB output
th(BCLK-DB)
DB Signal Output Hold Time (BCLK standard)
tsu(CAS-RAS) CAS Output Setup Time before RAS Output (refresh)
10 9
f(BCLK) X 2
tRP =
10 9 X 3
f(BCLK) X 2
tsu(DB – CAS) =
tsu(CAS – RAS) =
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
10 9
f(BCLK)
10
– 13
[ns]
– 20 [ns]
– 20
[ns]
9
f(BCLK) X 2
– 13
Page 444 of 488
[ns]
ns
ns
18
See Figure 26.1
ns
0
ns
(Note 1)
ns
18
0
ns
ns
18
ns
-3
ns
(Note 1)
ns
-7
ns
(Note 1)
ns
NOTES:
1. Values can be obtained from the following equations, according to the BCLK frequency.
th(RAS – RAD) =
ns
ns
td(BCLK-DW) DW Output Delay Time (BCLK standard)
th(BCLK-DW) DW Output Hold Time (BCLK standard)
18
0
td(BCLK-CAS) CAS Output Delay Time (BCLK standard)
th(BCLK-CAS) CAS Output Hold Time (BCLK standard)
ns
(Note 1)
td(BCLK-RAS) RAS Output Delay Time (BCLK standard)
th(BCLK-RAS) RAS Output Hold Time (BCLK standard)
18
0
td(BCLK-CAD) Column Address Output Delay Time
Unit
Max
26. Electrical Characteristics
M32C/83 Group (M32C/83, M32C/83T)
Vcc=3.3V
Memory Expansion Mode and Microprocessor Mode (with no wait state)
Read Timing
BCLK
td(BCLK-ALE)
18ns.max
th(BCLK-ALE)
-2ns.min
ALE
th(BCLK-CS)
td(BCLK-CS)
0ns.min
18ns.max(1)
CSi
th(RD-CS)
tcyc
0ns.min
td(BCLK-AD)
th(BCLK-AD)
18ns.max(1)
0ns.min
ADi
BHE
th(RD-AD)
0ns.min
td(BCLK-RD)
18ns.max
RD
tac2(RD-DB)(2)
th(BCLK-RD)
-3ns.min
tac2(AD-DB)(2)
Hi-Z
DB
tsu(DB-BCLK)
th(RD-DB)
30ns.min(1)
0ns.min
NOTES:
1. Values guaranteed only when the microcomputer is used independently.
A maximum of 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK).
2. Varies with operation frequency:
tac2(RD-DB)=(tcyc/2-35)ns.max
tac2(AD-DB)=(tcyc-35)ns.max
Write Timing
BCLK
td(BCLK-ALE)
18ns.max
th(BCLK-ALE)
-2ns.min
ALE
th(BCLK-CS)
td(BCLK-CS)
0ns.min
18ns.max
CSi
th(WR-CS)(1)
tcyc
td(BCLK-AD)
th(BCLK-AD)
18ns.max
ADi
BHE
0ns.min
td(BCLK-WR)
18ns.max
tw(WR)(1)
WR,WRL,
WRH
th(WR-AD)(1)
th(BCLK-WR)
0ns.min
d(DB-WR)(1)
t
th(WR-DB)(1)
DBi
NOTES:
1. Varies with operation frequency.
td(DB-WR)=(tcyc-20)ns.min
th(WR-DB)=(tcyc/2-10)ns.min
th(WR-AD)=(tcyc/2-10)ns.min
th(WR-CS)=(tcyc/2-10)ns.min
tw(WR)=(tcyc/2-15)ns.min
Figure 26.10 VCC=3.3V Timing Diagram (1)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 445 of 488
Measurement Conditions:
• VCC=3.0 to 3.6V
• Input high and low voltage: VIH=1.5V, VIL=0.5V
• Output high and low voltage: VOH=1.5V, VOL=1.5V
26. Electrical Characteristics
M32C/83 Group (M32C/83, M32C/83T)
Vcc=3.3V
Memory Expansion Mode and Microprocessor Mode (with a wait state)
Read Timing
BCLK
18ns.max
td(BCLK-ALE) th(BCLK-ALE)
-2ns.min
ALE
td(BCLK-CS)
th(BCLK-CS)
18ns.max(1)
0ns.min
CSi
th(RD-CS)
tcyc
0ns.min
th(BCLK-AD)
td(BCLK-AD)
ADi
BHE
18ns.max(1)
0ns.min
td(BCLK-RD)
18ns.max
th(RD-AD)
0ns.min
RD
th(BCLK-RD)
tac2(RD-DB)(2)
-3ns.min
tac2(AD-DB)(2)
DB
Hi-Z
tsu(DB-BCLK)
30ns.min(1)
th(RD-DB)
0ns.min
NOTES:
1. Values guaranteed only when the microcomputer is used independently. A maximum of 35ns is guaranteed
for td(BCLK-AD)+tsu(DB-BCLK).
2. Varies with operation frequency.
tac2(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 with 1 wait state, m=5 with 2 wait states and m=7 with 3 wait states)
tac2(AD-DB)=(tcyc x n-35)ns.max (n=2 with 1 wait state, n=3 with 2 wait states and n=4 with 3 wait states)
Write Timing
BCLK
18ns.max
td(BCLK-ALE)
th(BCLK-ALE)
-2ns.min
ALE
th(BCLK-CS)
td(BCLK-CS)
0ns.min
18ns.max
CSi
th(WR-CS)(1)
tcyc
td(BCLK-AD)
th(BCLK-AD)
18ns.max
0ns.min
ADi
BHE
td(BCLK-WR) tw(WR)(1)
WR,WRL,
WRH
th(WR-AD)(1)
18ns.max
th(BCLK-WR)
0ns.min
d(DB-WR)(1)
t
th(WR-DB)(1)
DBi
NOTES:
1. Varies with operation frequency.
td(DB-WR)=(tcyc x n-20)ns.min
(n=1 with 1 wait state, n=2 with 2 wait states and n=3 with 3 wait
states)
th(WR-DB)=(tcyc/2-10)ns.min
th(WR-AD)=(tcyc/2-10)ns.min
th(WR-CS)=(tcyc/2-10)ns.min
tw(WR)=(tcyc/2 x n-15)ns.min
(n=1 with 1 wait state, n=3 with 2 wait states and n=5 with 3 wait
states)
Figure 26.11 VCC=3.3V Timing Diagram (2)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 446 of 488
Measurement Conditions:
• VCC=3.0 to 3.6V
• Input high and low voltage:
VIH=1.5V, VIL=0.5V
• Output high and low voltage:
VOH=1.5V, VOL=1.5V
26. Electrical Characteristics
M32C/83 Group (M32C/83, M32C/83T)
Vcc=3.3V
Memory Expansion Mode and Microprocessor Mode
(with a wait state, when accessing an external memory and using the multiplexed bus)
Read Timing
BCLK
td(BCLK-ALE)
th(BCLK-ALE)
18ns.max
-2ns.min
ALE
th(BCLK-CS)
tcyc
td(BCLK-CS)
0ns.min
18ns.max
h(RD-CS)(1)
t
CSi
td(AD-ALE)(1)
ADi
/DBi
th(ALE-AD)(1)
Address
th(RD-DB)
8ns.max
tsu(DB-BCLK)
td(BCLK-AD)
ADi
BHE
tac3(RD-DB)
td(BCLK-RD)
tac3(AD-DB)(1)
0ns.min
th(BCLK-AD)
30ns.min
(1)
18ns.max
Address
Data input
tdz(RD-AD)
th(BCLK-RD)
18ns.max
0ns.min
th(RD-AD)(1)
-3ns.min
RD
NOTES:
1. Varies with operation frequency.
td(AD-ALE)=(tcyc/2-20)ns.min
th(ALE-AD)=(tcyc/2-10)ns.min, th(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min
tac3(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 with 2 wait states and m=5 with 3 wait states)
tac3(AD-DB)=(tcyc/2 x n-35)ns.max (n=5 with 2 wait states and n=7 with 3 wait states)
Write Timing
BCLK
td(BCLK-ALE)
18ns.max
th(BCLK-ALE)
-2ns.min
ALE
CSi
th(BCLK-CS)
tcyc
td(BCLK-CS)
th(WR-CS)(1)
18ns.max
0ns.min
td(AD-ALE)(1) th(ALE-AD)(1)
ADi
/DBi
td(DB-WR)(1)
td(BCLK-AD)
ADi
BHE
th(WR-DB)(1)
18ns.max
WR,WRL,
WRH
NOTES:
1. Varies with operation frequency.
td(AD-ALE)=(tcyc/2-20)ns.min
th(ALE-AD)=(tcyc/2-10)ns.min, th(WR-AD)=(tcyc/2-10)ns.min
th(WR-CS)=(tcyc/2-10)ns.min, th(WR-DB)=(tcyc/2-10)ns.min
td(DB-WR)=(tcyc/2 x m-25)ns.min
(m=3 with 2 wait states and m=5 with 3 wait states)
Figure 26.12 VCC=3.3V Timing Diagram (3)
Page 447 of 488
th(BCLK-AD)
0ns.min
18ns.max
td(BCLK-WR)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Address
Data output
Address
th(BCLK-WR)
th(WR-AD)()
0ns.min
Measurement Conditions:
• VCC=3.0 to 3.6V
• Input high and low voltage:
VIH=1.5V, VIL=0.5V
• Output high and low voltage:
VOH=1.5V, VOL=1.5V
26. Electrical Characteristics
M32C/83 Group (M32C/83, M32C/83T)
Vcc=3.3V
Memory Expansion Mode and Microprocessor Mode
(With 2 wait states, when accessing the DRAM area)
Read Timing
BCLK
tcyc
td(BCLK-RAD)
th(BCLK-RAD)
18ns.max(1)
MAi
td(BCLK-CAD)
th(BCLK-CAD)
18ns.max(1)
0ns.min
0ns.min
Column address
Row address
tRP(2)
th(RAS-RAD)(1)
RAS
td(BCLK-RAS)
18ns.max(1)
th(BCLK-RAS)
td(BCLK-CAS)
0ns.min
18ns.max(1)
CASL
CASH
th(BCLK-CAS)
0ns.min
DW
tac4(CAS-DB)(2)
tac4(CAD-DB)(2)
tac4(RAS-DB)(2)
Hi-Z
DB
tsu(DB-BCLK)
30ns.min(1)
th(CAS-DB)
0ns.min
NOTES:
1. Values guaranteed only when the microcomputer is used independently. A maximum of 35ns is
guaranteed for the followings:
td(BCLK-RAS) + tsu(DB-BCLK)
td(BCLK-CAS) + tsu(DB-BCLK)
td(BCLK-CAD) + tsu(DB-BCLK)
2. It varies with the operation frequency.
tac4(RAS-DB)=(tcyc/2 x m-35)ns.max (m=3 with 1 wait state and m=5 with 2 wait states)
tac4(CAS-DB)=(tcyc/2 x n-35)ns.max (n=1 with 1 wait state and n=3 with 2 wait states)
tac4(CAD-DB)=(tcyc x l-35)ns.max (l=1 with 1 wait state and l=2 with 2 wait states)
th(RAS-RAD)=(tcyc/2-13)ns.min
tRP=(tcyc/2 x 3-20)ns.min
Measurement Conditions:
• VCC=3.0 to 3.6V
• Input high and low voltage: VIH=1.5V, VIL=0.5V
• Output high and low voltage: VOH=1.5V, VOL=1.5V
Figure 26.13 VCC=3.3V Timing Diagram (4)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 448 of 488
26. Electrical Characteristics
M32C/83 Group (M32C/83, M32C/83T)
Vcc=3.3V
Memory Expansion Mode and Microprocessor Mode
(With 2 wait states, when accessing the DRAM area)
Write Timing
BCLK
tcyc
td(BCLK-RAD)
18ns.max
th(BCLK-RAD)
0ns.min
MAi
td(BCLK-CAD)
th(BCLK-CAD)
18ns.max
Row address
0ns.min
Column address
tRP(1)
th(RAS-RAD)(1)
RAS
td(BCLK-RAS) td(BCLK-CAS)
18ns.max
CASL
CASH
18ns.max
th(BCLK-RAS)
0ns.min
th(BCLK-CAS)
td(BCLK-DW)
0ns.min
18ns.max
DW
th(BCLK-DW)
tsu(DB-CAS)(1)
DB
-3ns.min
Hi-Z
th(BCLK-DB)
-7ns.min
NOTES:
1. Varies with operation frequency.
th(RAS-RAD)=(tcyc/2-13)ns.min
tRP=(tcyc/2 x 3-20)ns.min
tsu(DB-CAS)=(tcyc-20)ns.min
Figure 26.14 VCC=3.3V Timing Diagram (5)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 449 of 488
Measurement Conditions:
• VCC=3.0 to 3.6V
• Input high and low voltage:
VIH=1.5V, VIL=0.5V
• Output high and low voltage:
VOH=1.5V, VOL=1.5V
26. Electrical Characteristics
M32C/83 Group (M32C/83, M32C/83T)
Vcc=3.3V
Memory Expansion Mode and Microprocessor Mode
Refresh Timing (CAS-before-RAS refresh)
BCLK
td(BCLK-RAS)
tcyc
18ns.max
RAS
th(BCLK-RAS)
tsu(CAS-RAS)(1)
CASL
CASH
0ns.min
td(BCLK-CAS)
th(BCLK-CAS)
0ns.min
18ns.max
DW
NOTES:
1. Varies with operation frequency.
tsu(CAS-RAS)=(tcyc/2-13)ns.min
Refresh Timing (Self-refresh)
BCLK
td(BCLK-RAS)
tcyc
18ns.max
RAS
tsu(CAS-RAS)(1)
CASL
CASH
td(BCLK-CAS)
18ns.max
DW
NOTES:
1. Varies with operation frequency.
tsu(CAS-RAS)=(tcyc/2-13)ns.min
Measurement Conditions:
• VCC=3.0 to 3.6V
• Input high and low voltage: VIH=1.5V, VIL=0.5V
• Output high and low voltage: VOH=1.5V, VOL=1.5V
Figure 26.15 VCC=3.3V Timing Diagram (6)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 450 of 488
th(BCLK-RAS)
0ns.min
th(BCLK-CAS)
0ns.min
26. Electrical Characteristics
M32C/83 Group (M32C/83, M32C/83T)
Vcc=3.3V
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Counter increment/
decrement input)
In event counter mode
TAiIN input
(When counting on falling edge)
th(TIN–UP)
tsu(UP–TIN)
TAiIN input
(When counting on rising edge)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C–Q)
TxDi
td(C–Q)
tsu(D–C)
th(C–D)
RxDi
tw(INL)
INTi input
tw(INH)
NMI input
2 clock cycles + 300ns
or more ("L" width)
Figure 26.16 VCC=3.3V Timing Diagram (7)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 451 of 488
2 clock cycles + 300ns
or more
26. Electrical Characteristics
M32C/83 Group (M32C/83, M32C/83T)
Vcc=3.3V
Memory Expansion Mode and Microprocessor Mode
(Valid only with a wait state)
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
tsu(RDY–BCLK)
(Valid with a wait state and no wait state)
BCLK
tsu(HOLD–BCLK)
th(BCLK–HOLD)
HOLD input
HLDA output
td(BCLK–HLDA) td(BCLK–HLDA)
P0, P1, P2,
P3, P4,
P50 to P52
Hi–Z
Measurement Conditions:
• VCC=3.0 to 3.6V
• Input high and low voltage: VIH=2.4V, VIL=0.6V
• Output high and low voltage: VOH=1.5V, VOL=1.5V
Figure 26.17 VCC=3.3V Timing Diagram (8)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 452 of 488
th(BCLK–RDY)
M32C/83 Group (M32C/83, M32C/83T)
26. Electrical Characteristics (M32C/83T)
26.2 Electrical Characteristics (M32C/83T)
Table 26.45 Absolute Maximum Ratings
Symbol
Parameter
Condition
Value
Unit
VCC
Supply Voltage
VCC=AVCC
-0.3 to 6.0
V
AVCC
Analog Supply Voltage
VCC=AVCC
-0.3 to 6.0
V
VI
Input Voltage
-0.3 to VCC+0.3
V
RESET, CNVSS, BYTE, P00-P07, P10-P17, P20-P27,
P30-P37, P40-P47, P50-P57, P60-P67, P72-P77, P80P87, P90-P97, P100-P107, P110-P114, P120-P127,
P130-P137, P140-P146, P150-P157(1), VREF, XIN
P70, P71
VO
Output Voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50P57, P60-P67, P72-P77, P80-P84, P86, P87, P90-P97,
-0.3 to 6.0
V
-0.3 to VCC+0.3
V
400
mW
-40 to 85
°C
-65 to 150
°C
P100-P107, P110-P114, P120-P127, P130-P137, P140P146, P150-P157(1), XOUT
Pd
Power Dissipation
Topr
Operating Ambient Temperature
Tstg
Storage Temperature
NOTES:
1. P11 to P15 are provided in the 144-pin package.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 453 of 488
Topr=25° C
T version
26. Electrical Characteristics (M32C/83T)
M32C/83 Group (M32C/83, M32C/83T)
Table 26.46 Recommended Operating Conditions
(VCC=4.2 to 5.5V, VSS=0V at Topr = -40 to 85oC (T version) unless otherwise specified)
Symbol
Parameter
VCC
AVCC
Supply Voltage
Analog Supply Voltage
VSS
Supply Voltage
AVSS
Analog Supply Voltage
Input High ("H")
Voltage
VIL
Input Low ("L")
Voltage
IOH(avg)
IOL(peak)
IOL(avg)
f(XIN)
f(XCIN)
Max.
5. 5
Unit
V
V
V
0
V
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60P67, P72-P77, P80-P87(3), P90-P97, P100-P107, P110-P114,
P120-P127, P130-P137, P140-P146, P150-P157(4), XIN,
RESET, CNVSS, BYTE
0.8VCC
P70, P71
0.8VCC
6.0
0
0.2VCC
V
-10.0
mA
-5.0
mA
10.0
mA
5.0
mA
32
MHz
50
kHz
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60P67, P70-P77, P80-P87(3), P90-P97, P100-P107, P110-P114,
P120-P127, P130-P137, P140-P146, P150-P157(4), XIN,
RESET, CNVSS, BYTE
Peak Output
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60High ("H")
P67, P72-P77, P80-P84, P86, P87, P90-P97, P100-P107, P110Current(2)
P114, P120-P127, P130-P137, P140-P146, P150-P157(4)
Average Output P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60High ("H")
P67, P72-P77, P80-P84, P86, P87, P90-P97, P100-P107, P110Current(1)
P114, P120-P127, P130-P137, P140-P146, P150-P157(4)
Peak Output Low P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60("L") Current(2)
P67, P70-P77, P80-P84, P86, P87, P90-P97, P100-P107, P110P114, P120-P127, P130-P137, P140-P146, P150-P157(4)
Average Output P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60Low ("L")
P67, P70-P77, P80-P84, P86, P87, P90-P97, P100-P107, P110Current(1)
P114, P120-P127, P130-P137, P140-P146, P150-P157(4)
Main Clock Input VCC=4.2 to 5.5V
Frequency
NOTES:
1. Typical values when average output current is 100ms.
2. Total IOL(peak) for P0, P1, P2, P86, P87, P9, P10, P11, P14 and P15 must be 80mA or less.
Total IOH(peak) for P0, P1, P2, P86, P87, P9, P10, P11, P14 and P15 must be -80mA or less.
Total IOL(peak) for P3, P4, P5, P6, P7, P80 to P84, P12 and P13 must be 80mA or less.
Total IOH(peak) for P3, P4, P5, P6, P72 to P77, P80 to P84, P12 and P13 must be -80mA or less.
3. VIH and VIL reference for P87 applies when P87 is used as a programmable input port.
It does not apply when P87 is used as XCIN.
4. P11 to P15 are provided in the 144-pin package only.
Page 454 of 488
VCC
0
Sub Clock Oscillation Frequency
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Typ.
5.0
VCC
0
VIH
IOH(peak)
Standard
Min.
4.2
32.768
V
M32C/83 Group (M32C/83, M32C/83T)
26. Electrical Characteristics (M32C/83T)
VCC=5V
Table 26.47 Electrical Characteristics (VCC = 4.2 to 5.5 V, VSS = 0V
at Topr = –40 to 85oC(T version), f(XIN)=32MHZ unless otherwise specified)
Symbol
VOH
Parameter
Output High ("H")
Voltage
Condition
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, IOH=-5mA
P50-P57, P60-P67, P72-P77, P80-P84, P86,
P87, P90-P97, P100-P107, P110-P114, P120P127, P130-P137, P140-P146, P150-P157(1)
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, IOH=-200µA
P50-P57, P60-P67, P72-P77, P80-P84, P86,
Standard
Min
VCC-2.0
Typ
Unit
Max
V
VCC-0.3
P87, P90-P97, P100-P107, P110-P114, P120-
VOL
Output Low ("L")
Voltage
P127, P130-P137, P140-P146, P150-P157(1)
XOUT
IOH=-1mA
XCOUT
No load applied
3.0
V
3.3
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, IOL=5mA
P50-P57, P60-P67, P70-P77, P80-P84, P86,
P87, P90-P97, P100-P107, P110-P114, P120P127, P130-P137, P140-P146, P150-P157(1)
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, IOL=200µA
P50-P57, P60-P67, P70-P77, P80-P84, P86,
VT+-VT-
Hysteresis
P87, P90-P97, P100-P107, P110-P114, P120P127, P130-P137, P140-P146, P150-P157(1)
XOUT
IOL=1mA
XCOUT
No load applied
HOLD, RDY, TA0IN-TA4IN, TB0IN-TB5IN,
INT0-INT5, ADTRG, CTS0-CTS4, CLK0-
V
2.0
V
0.45
V
2.0
V
0
0.2
V
1.0
V
CLK4, TA0OUT-TA4OUT, NMI, KI0-KI3, RxD0RxD4, SCL0-SCL4, SDA0-SDA4
IIH
Input High ("H")
Current
RESET
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, VI=5V
P50-P57, P60-P67, P70-P77, P80-P87, P90-P97,
P100-P107, P110-P114, P120-P127, P130-
0.2
1.8
V
5.0
µA
-5.0
µA
167
kΩ
54
MΩ
MΩ
V
mA
P137, P140-P146, P150-P157(1), XIN, RESET,
IIL
RPULLUP
RfXIN
RfXCIN
VRAM
ICC
Input Low ("L")
Current
Pull-up Resistance
CNVSS, BYTE
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, VI=0V
P50-P57, P60-P67, P70-P77, P80-P87, P90-P97,
P100-P107, P110-P114, P120-P127, P130P137, P140-P146, P150-P157(1), XIN, RESET,
CNVSS, BYTE
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, VI=0V
P50-P57, P60-P67, P72-P77, P80-P84, P86,
P87, P90-P97, P100-P107, P110-P114, P120P127, P130-P137, P140-P146, P150-P157(1)
Feedback Resistance XIN
Feedback Resistance XCIN
RAM Standby Voltage
Power Supply
Measurement conditions:
f(XIN)=32 MHz, square wave,
Current
In single-chip mode, output no division
pins are left open and other f(XCIN)=32 kHz, with a wait state,
pins are connected to VSS
Topr=25° C
Topr=25° C when the clock stops
NOTES:
1. P11 to P15 are provided in the 144-pin package only.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 455 of 488
30
50
1.5
10
2.5
40
µA
470
0.4
20
µA
26. Electrical Characteristics (M32C/83T)
M32C/83 Group (M32C/83, M32C/83T)
VCC=5V
Table 26.48 A/D Conversion Characteristics (VCC = AVCC = VREF = 4.2 to 5.5V, Vss = AVSS = 0V
at Topr = –40 to 85oC (T version), f(XIN) = 32MHZ unless otherwise specified)
Symbol
Parameter
Standard
Measurement Condition
Min Typ
-
INL
Resolution
VREF=VCC
Integral Nonlinearity Error
DNL
Unit
Max
10
AN0 to AN7
ANEX0, ANEX1
±3
External op-amp
connection mode
±7
Bits
LSB
LSB
VREF=VCC=5V
LSB
LSB
Differential Nonlinearity Error
±1
LSB
-
Offset Error
±3
LSB
-
Gain Error
±3
LSB
40
kΩ
RLADDER
Resistor Ladder
VREF=VCC
8
tCONV
10-bit Conversion Time
2.1
µs
tCONV
8-bit Conversion Time
1.8
µs
tSAMP
Sample Time
0.2
µs
VREF
Reference Voltage
2
VCC
V
VIA
Analog Input Voltage
0
VREF
V
NOTES:
1. Divide f(XIN), if exceeding 16 MHz, to keep φAD frequency at 16 MHz or less.
Table 26.49 D/A Conversion Characteristics (VCC = VREF = 4.2 to 5.5V, VSS = AVSS = 0V
at Topr = –40 to 85oC (T version), f(XIN) = 32MHZ unless otherwise specified)
Symbol
Parameter
Standard
Measurement Condition
Min Typ
-
Resolution
8
Absolute Accuracy
t SU
Setup Time
RO
Output Resistance
IVREF
Reference Power Supply
Input Current
Unit
Max
4
1.0
%
3
µs
20
kΩ
1.5
mA
10
(Note 1)
NOTES:
1. Measurement results when using one D/A converter. The DAi register (i=0, 1) of the
D/A converter not being used is set to "0016". The resistor ladder in the A/D converter is exclued.
IVREF flows even if the VCUT bit in the ADiCON1 register is set to "0" (no VREF connection).
Table 26.50 Flash Memory Version Electrical Characteristics
Standard
Parameter
Unit
Min
Typ
Max
Program Time (per page)
8
120
ms
Block Erase Time (per block)
50
600
ms
NOTES:
1. VCC= 4.2 to 5.5V at Topr= 0 to 60° C, unless otherwise specified
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 456 of 488
Bits
26. Electrical Characteristics (M32C/83T)
M32C/83 Group (M32C/83, M32C/83T)
Timing Requirements (VCC = 4.2 to 5.5V, VSS = 0V at Topr = –40 to 85oC (T version) unless
otherwise specified)
VCC=5V
Table 26.51 External Clock Input
Symbol
Parameter
Standard
Min
Unit
Max
tc
External Clock Input Cycle Time
33
ns
tw(H)
External Clock Input High ("H") Pulse Width
13
ns
13
tw(L)
External Clock Input Low ("L") Pulse Width
tr
External Clock Rise Time
5
ns
tf
External Clock Fall Time
5
ns
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 457 of 488
ns
M32C/83 Group (M32C/83, M32C/83T)
26. Electrical Characteristics (M32C/83T)
VCC=5V
Timing Requirements
(VCC = 4.2 to 5.5V, VSS = 0V at Topr = –40 to 85oC (T version) unless otherwise specified)
Table 26.52 Timer A Input (Count Source Input in Event Counter Mode)
Symbol
Parameter
Standard
Min
Unit
Max
tc(TA)
TAiIN Input Cycle Time
100
ns
tw(TAH)
TAiIN Input High ("H") Pulse Width
40
ns
tw(TAL)
TAiIN Input Low ("L") Pulse Width
40
ns
Table 26.53 Timer A Input (Gate Input in Timer Mode)
Standard
Symbol
Parameter
Min
Max
Unit
tc(TA)
TAiIN Input Cycle Time
400
ns
tw(TAH)
TAiIN Input High ("H") Pulse Width
200
ns
tw(TAL)
TAiIN Input Low ("L") Pulse Width
200
ns
Table 26.54 Timer A Input (External Trigger Input in One-Shot Timer Mode)
Standard
Symbol
Parameter
Unit
Min
Max
tc(TA)
TAiIN Input Cycle Time
200
ns
tw(TAH)
TAiIN Input High ("H") Pulse Width
100
ns
tw(TAL)
TAiIN Input Low ("L") Pulse Width
100
ns
Table 26.55 Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard
Symbol
Parameter
Unit
Min
Max
tw(TAH)
TAiIN Input High ("H") Pulse Width
100
ns
tw(TAL)
TAiIN Input Low ("L") Pulse Width
100
ns
Table 26.56 Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min
Max
tc(UP)
TAiOUT Input Cycle Time
2000
ns
tw(UPH)
TAiOUT Input High ("H") Pulse Width
1000
ns
tw(UPL)
TAiOUT Input Low ("L") Pulse Width
1000
ns
tsu(UP-TIN)
TAiOUT Input Setup Time
400
ns
th(TIN-UP)
TAiOUT Input Hold Time
400
ns
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 458 of 488
M32C/83 Group (M32C/83, M32C/83T)
26. Electrical Characteristics (M32C/83T)
Timing Requirements
(VCC = 4.2 to 5.5V, VSS = 0V at Topr = –40 to 85oC (T version) unless otherwise specified)
Table 26.57 Timer B Input (Count Source Input in Event Counter Mode)
Symbol
Parameter
Standard
Min
Max
Unit
tc(TB)
TBiIN Input Cycle Time (counted on one edge)
100
ns
tw(TBH)
TBiIN Input High ("H") Pulse Width (counted on one edge)
40
ns
tw(TBL)
TBiIN Input Low ("L") Pulse Width (counted on one edge)
40
ns
tc(TB)
TBiIN Input Cycle Time (counted on both edges)
200
ns
tw(TBH)
TBiIN Input High ("H") Pulse Width (counted on both edges)
80
ns
tw(TBL)
TBiIN Input Low ("L") Pulse Width (counted on both edges)
80
ns
Table 26.58 Timer B Input (Pulse Period Measurement Mode)
Symbol
Parameter
Standard
Min
Max
Unit
tc(TB)
TBiIN Input Cycle Time
400
ns
tw(TBH)
TBiIN Input High ("H") Pulse Width
200
ns
tw(TBL)
TBiIN Input Low ("L") Pulse Width
200
ns
Table 26.59 Timer B Input (Pulse Width Measurement Mode)
Standard
Symbol
Parameter
Unit
Min
Max
tc(TB)
TBiIN Input Cycle Time
400
ns
tw(TBH)
TBiIN Input High ("H") Pulse Width
200
ns
tw(TBL)
TBiIN Input Low ("L") Pulse Width
200
ns
Table 26.60 A/D Trigger Input
Symbol
Standard
Parameter
Min
Unit
Max
tc(AD)
ADTRG Input Cycle Time (required for re-trigger)
1000
ns
tw(ADL)
ADTRG Input Low ("L") Pulse Width
125
ns
Table 26.61 Serial I/O
Symbol
Parameter
Standard
Min
Max
Unit
tc(CK)
CLKi Input Cycle Time
200
ns
tw(CKH)
CLKi Input High ("H") Pulse Width
100
ns
tw(CKL)
CLKi Input Low ("L") Pulse Width
100
ns
td(C-Q)
TxDi Output Delay Time
th(C-Q)
TxDi Hold Time
0
tsu(D-C)
RxDi Input Set Up Time
30
ns
th(C-Q)
RxDi Input Hold Time
90
ns
80
ns
ns
_______
Table 26.62 External Interrupt INTi Input
Symbol
Parameter
Standard
Min
Max
Unit
tw(INH)
INTi Input High ("H") Pulse Width
250
ns
tw(INL)
INTi Input Low ("L") Pulse Width
250
ns
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 459 of 488
VCC=5V
26. Electrical Characteristics (M32C/83T)
M32C/83 Group (M32C/83, M32C/83T)
P0
P1
P2
P3
P4
P5
P6
P7
30pF
P8
P9
P10
P11
P12
P13
Note 1
P14
P15
NOTES:
1. P11 to P15 are provided in the 144-pin package only.
Figure 26.18 P0 to P15 Measurement Circuit
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 460 of 488
26. Electrical Characteristics (M32C/83T)
M32C/83 Group (M32C/83, M32C/83T)
Vcc=5V
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Counter increment/
decrement input)
In event counter mode
TAiIN input
(When counting on the falling edge)
th(TIN–UP)
tsu(UP–TIN)
TAiIN input
(When counting on the rising edge)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C–Q)
TxDi
td(C–Q)
tsu(D–C)
th(C–D)
RxDi
tw(INL)
INTi input
tw(INH)
NMI input
2 clock cycles + 300ns
or more ("L" width)
Figure 26.19 VCC = 5 V Timing Diagram(1)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 461 of 488
2 clock cycles + 300ns
or more
M32C/83 Group (M32C/83, M32C/83T)
27. Precautions (Processor Mode)
27. Precautions
27.1 Processor Mode
27.1.1 Microprocessor Mode
SFR, internal RAM and external space can be accessed when in microprocessor mode. The internal
ROM cannot be accessed.
The internal ROM cannot be accessed, despite entering memory expansion mode or single-chip mode ,
if the microcomputer begins operation in microprocessor mode while the CNVSS is held high ("H") after
reset.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 462of 488
M32C/83 Group (M32C/83, M32C/83T)
27. Precautions (Bus)
27.2 Bus
__________
27.2.1 HOLD Signal
When entering microprocessor mode or memory expansion mode from single-chip mode and using
__________
HOLD input, set the PM01 to PM00 bits to "112" (microprocessor mode) or to "102" (memory expansion
mode) after setting the PD4_0 to PD4_7 bits in the PD4 register and the PD5_0 to PD5_2 bits in the PD5
register to "0" (input mode).
_____ _______
_______
______ ______ ________ ______ _______ ________
P40 to P47 (A16 to A22, A23, CS0 to CS3, MA8 to MA12) and P50 to P52 (RD/WR/BHE, RD/WRL,WRH) do
__________
not enter a high-impedance state even when an "L" signal is applied to the HOLD pin, if the PM01 to
PM00 bits are set to "112" (microprocessor mode) or to "102" (memory expansion mode) after setting the
PD4_0 to PD4_7 bits in the PD4 register and the PD5_0 to PD5_2 bits in the PD5 register to "1" (output
mode) in single-chip mode.
27.2.2 External Bus
The internal ROM cannot be read when an "H" signal is applied to the CNVSS pin and the hardware reset
(hardware reset 1 or hardware reset 2) occurs.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 463 of 488
27. Precautions (SFR)
M32C/83 Group (M32C/83, M32C/83T)
27.3 SFR
27.3.1 100-Pin Package
Set address space for 03CB16, 03CE16, 03CF16, 03D216, 03D316 to "FF16" after reset when using the
100-pin package. 03DC16 must be set to "0016" after reset.
27.3.2 Register Settings
Table 27.1 lists registers containing bits which can only be written to. Set these registers with immediate
values. When establishing the next value by altering the present value, write the present value to the
RAM as well as to the register. Transfer the next value to the register after making changes in the RAM.
Table 27.1 Registers with Write-only Bits
Register
WDTS register
G0RI register
G1RI register
G2TB register
G3TB register
U4BRG register
U4TB register
TA11 register
TA21 register
TA41 register
DTT register
ICTB2 register
U3BRG register
U3TB register
Address
000E16
00EC16
012C16
016D16, 016C16
017D16, 017C16
02F916
02FB16, 02FA16
030316, 030216
030516, 030416
030716, 030616
030C16
030D16
032916
032B16, 032A16
Register
U2BRG register
U2TB register
UDF register
TA0 register(1)
TA1 register(1)
TA2 register(1)
TA3 register(1)
TA4 register(1)
U0BRG register
U0TB register
U1BRG register
U1TB register
AD0CON2 register
NOTES :
1. In one-shot timer mode and pulse width modulation mode only.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 464of 488
Address
033916
033B16, 033A16
034416
034716, 034616
034916, 034816
034B16, 034A16
034D16, 034C16
034F16, 034E16
036916
036B16, 036A16
02E916
02EB16, 02EA16
039416
M32C/83 Group (M32C/83, M32C/83T)
27. Precautions (Clock Generation Circuit)
27.4 Clock Generation Circuit
27.4.1 PLL Frequency Synthesizer
Stabilize supply voltage when using the PLL frequency synthesizer. The ripple of supply voltage at 5V
must be less than 10kHz in frequency, 0.5V (peak to peak) in voltage fluctuation range, and 1V/ms in
voltage fluctuation rate. The ripple of supply voltage at 3.3V must be less than 100Hz in frequency, 0.2V
(peak to peak) in voltage fluctuation range, and 0.1V/ms in voltage fluctuation rate.
27.4.2 Power Consumption Control
____________
• When resetting the microcomputer to exit stop mode, apply an "L" signal to the RESET pin until the main
clock oscillation stabilizes.
• Write at least 4 NOP instructions after the WAIT instruction or instructions to set the CM10 bit in the CM1
register to "1" (all clocks stop). When entering wait mode or stop mode, the instruction queue reads
ahead to instructions following the WAIT instruction and instructions to set the CM10 bit to "1", and the
program stops. The next instruction may be executed before entering wait mode or stop mode, depending on the combination of instructions and their execution timing.
• The followings are suggestions for reducing power consumption when programming or designing systems:
Ports: I/O ports maintains the same state despite the microcomputer entering wait mode or stop
mode. Current flows through active output ports. Feedthrough current flows through input ports in a
high-impedance state. Set unused ports as input ports and stablize electrical potential before entering
wait mode or stop mode.
A/D Converter: If the A/D conversion is not performed, set the VCUT bit in the AD0CON1 register to
"0"(no VREF connection). Set the VCUT bit to "1" (VREF connection) and wait at least 1µs before
starting the A/D conversion.
D/A Converter: Set the DAi bit (i=0 to 1) in the DACON register to "0" (output disabled) and set the
DAi register to "0016" when the D/A conversion is not performed.
Peripheral Function Stop: Set the CM02 bit in the CM0 register while in wait mode to stop unnecessary peripheral functions. However, this does not reduce power consumption because the peripheral
function clock (fc32) generating from the sub clock does not stop. When in low-speed mode and lowpower consumption mode, do not enter wait mode when the CM02 bit is set to "1" (peripheral clock
stops in wait mode).
External Clock: When an external clock is selected as the CPU clock, set the CM05 bit in the CM0
register to "1" (main clock stops). This disables the XOUT pin and reduces power consumption. (When
using an external clock input, the clock is applied regardless of the CM05 bit setting.)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 465 of 488
M32C/83 Group (M32C/83, M32C/83T)
27. Precautions (Clock Generation Circuit)
27.4.3 Wait Mode
When entering wait mode, the instruction queue reads ahead to instructions following the WAIT instruction, and the program stops. Write at least 4 NOP instructions after WAIT instruction.
27.4.4 Stop Mode
• If stop mode is exited by any reset, apply an "L" signal to the RESET pin until a main clock oscillation is
stabilized enough.
• When entering stop mode, the instruction queue reads ahead to instructions following the instruction
setting the CM10 bit in the CM1 register to "1" (all clocks stopped), and the program stops. When the
microcomputer exits stop mode, the instruction lined in the instruction queue is executed before the
interrupt routine for recovery is done.
Write the JMP.B instruction as follows, after the instruction setting the CM10 bit to "1".
e.g., bset 0, prcr
fset I
bset 0, cm1
jmp.b LABEL_001
LABEL_001;
nop
nop
nop
nop
mov.b #0, prcr
•
•
•
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
; protection removed
; I flag set
; all clocks stopped (stop mode)
; jmp.b instruction executed (no instruction between jmp.b and LABEL)
; nop (1)
; nop (2)
; nop (3)
; nop (4)
; Protection set
Page 466of 488
M32C/83 Group (M32C/83, M32C/83T)
27. Precautions (Protection)
27.5 Protection
The PRC2 bit in the PRCR register is changed to "0" (write disable) when an instruction is written to any
address after the PRC2 bit is set to "1" (write enable). Write instruction immediately after setting the PRC2
bit to "1" to change registers protected by the PRC2 bit. Do not generate an interrupt or a DMA transfer
between the instruction to set the PRC2 bit to "1" and the following instruction.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 467 of 488
27. Precautions (Interrupts)
M32C/83 Group (M32C/83, M32C/83T)
27.6 Interrupts
27.6.1 ISP Setting
After reset, the ISP is set to "00000016". The program runs out of control if an interrupt is acknowledged
before the ISP is set. Therefore, the ISP must be set before an interrupt request is acknowledged. Set the
ISP to an even address, which allows interrupt sequences to be executed at a higher speed.
_______
_______
To use NMI interrupt, set the ISP at the beginning of the program. The NMI interrupt can be acknowledged after the first instruction has been executed after reset.
_______
27.6.2 NMI Interrupt
_______
_______
• NMI interrupt cannot be denied. Connect the NMI pin to VCC via a resistor (pull-up) when not in use.
_______
• The P8_5 bit in the P8 register indicates the NMI pin value. Read the P8_5 bit only to determine the pin
_______
level after a NMI interrupt occurs.
_______
• H" and "L" of a signal applied to the NMI pin must be over 2 CPU clock cycles + 300 ns wide.
______
27.6.3 INT Interrupt
• Edge sensitive
______
______
"H" and "L" of a signal applied to the INT0 to INT5 pins must be at least 250 ns wide, regardless of the
CPU clock.
• Level sensitive
______
______
"H" and "L" of a signal applied to the INT0 to INT5 pins must be at least 1 CPU clock cycle + 200 ns
wide. For example, "H" and "L" must be at least 234ns wide if XIN=30MHz with no division.
______
______
• The IR bit may change to "1" (interrupt requested) when switching the polarity of the INT0 to INT5 pins.
Set the IR bit to "0" (no interrupt requested) after selecting the polarity. Figure 27.1 shows an example
______
of the switching procedure for the INT interrupt.
Set the ILVL2 to ILVL0 bits in the INTiIC
register (i = 0 to 5) to "0002" (level 0)
(INT interrupt disabled)
Set the POL bit in the INTiIC register
Set the IR bit in the INTiIC register to "0"
Set the ILVL2 to ILVL0 bits to "0012" (level 1)
to "1112" (level 7)
(INT interrupt request acknowledgement enabled)
______
Figure 27.1 Switching Procedure for INT Interrupt
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 468of 488
M32C/83 Group (M32C/83, M32C/83T)
27. Precautions (Interrupts)
27.6.4 Watchdog Timer Interrupt
Reset the watchdog timer after a watchdog timer interrupt occurs.
27.6.5 Changing Interrupt Control Register
To change the interrupt control register while the interrupt request is disabled, follow the instructions
below.
Changing Bits Except IR Bit
When an interrupt request occurs while executing an instruction, the IR bit may not be set to "1"
(interrupt requested) and the interrupt may be ignored. If this is a problem, use the following instructions to change the register: AND, OR, BCLR, BSET
Changing IR bit
The IR bit may not change to "0" (no interrupt requested) depending on the instructions written. If this
is a problem, use the following instruction to change the register: MOV
27.6.6 Changing IIOiIR Register (i = 0 to 11)
Use the following instructions to set bits 1 to 7 in the IIOilR register to "0" (no interrupt requested).
AND, BCLR
27.6.7 Changing RLVL Register
The DMAII bit is indeterminate after reset. When using the DMAII bit to generate an interrupt, set the
interrupt control register after setting the DMACII bit to "0" (interrupt priority level 7 available for interrupts).
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 469 of 488
M32C/83 Group (M32C/83, M32C/83T)
27. Precautions (DMAC)
27.7 DMAC
• Set DMAC-associated registers while the MDi1 to MDi0 bits (i=0 to 3) in the channel to be used are set
to "002" (DMA disabled). Set the MDi1 to MDi0 bits to "012" (single transfer) or "112" (repeat transfer) at
the end of the setup procedure to start DMA requests.
• Do not set the DRQ bit in the DMiSL register to "0" (no request).
When a DMA request is generated but the receiving channel is not ready to receive(1), the DMA transfer
does not occur and the DRQ bit is set to "0".
NOTES:
1. The MDi1 to MDi0 bits are set to "002" or the DCTi register is set to "000016" (transferred 0
times).
• To start a DMA transfer by a software trigger, set the DSR bit and DRQ bit in the DMiSL register to "1"
simultaneously.
e.g.,
OR.B #0A0h,DMiSL Set the DSR and DRQ bits to "1" simultaneously.
• Do not generate a channel i DMA request when setting the MDi1 to MDi0 bits in the DMDj register (j=0,1)
corresponding to channel i to "012" (single transfer) or "112" (repeat transfer), if the DCTi register of
channel i is set to "1".
• Select the peripheral function which causes the DMA request after setting the DMA-associated registers.
______
If none of the conditions above (setting INT interrupt as DMA request source) apply, do not write "1" to
the DCTi register.
• Enable DMA(2) after setting the DMiSL register (i=0 to 3) and waiting 6 BCLK cycles or more by program.
NOTES:
2. DMA is enabled when the values set in the MDi1 to MDi0 bits in the DMDj register are changed
from "002" (DMA disabled) to "012" (single transfer) or "112" (repeat transfer).
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 470of 488
M32C/83 Group (M32C/83, M32C/83T)
27. Precautions (Timer)
27.8 Timer
27.8.1 Timers A and B
The timers stop after reset. Set the TAiS(i=0 to 4) bit or TBjS(j=0 to 5) bit in the TABSR register or TBSR
register to "1" (starts counting) after setting operation mode, count source and counter.
Set the following registers and bits while the TAiS bit or TBjS bit is set to "0" (stops counting).
• TAiMR, TBjMR register
• TAi, TBj register
• UDF register
• TAZIE, TA0TGL, TA0TGH bits in the ONFS register
• TRGSR register
27.8.2 Timer A
27.8.2.1 Timer A (Timer Mode)
(a) The TAiS bit (i=0 to 4) in the TABSR register is set to "0" (stops counting) after reset. Set the TAiS
bit to "1" (starts counting) after selecting operation mode and setting the TAi register.
(b) The TAi register indicates the counter value during counting at any given time. However, the
counter will read "FFFF16" when reloading. The setting value can be read after setting the TAi register while the counter is stopped and before the counter starts counting.
(c) TA1OUT, TA2OUT and TA4OUT pins are placed in high-impedance states when an "L" signal is
_______
applied to the NMI pin while INV03 to INV02 bits in the INVC0 register are set to "112" (forced cutoff
_______
of the three-phase output by an "L" signal applied to the NMI pin)
27.8.2.2 Timer A (Event Counter Mode)
(a) TAiS (i=0 to 4) bit in the TABSR register is set to "0" (stops counting) after reset. Set the TAiS bit to
"1" (starts counting) after selecting operation mode and setting the TAi register.
(b) The TAi register indicates the counter values during counting at any given time. However, the
counter will read "FFFF16" during underflow and "000016" during overflow, when reloading. The
setting value can be read after setting the TAi register while the counter is stopped and before the
counter starts counting.
(c) The TA1OUT, TA2OUT and TA4OUT pins are placed in high-impedance states when an "L" signal is
_______
applied to the NMI pin while the INV03 to INV02 bit in the INVC0 register are set to "112" (forced
_______
cutoff of the three-phase output by an "L" signal applied to the NMI pin).
27.8.2.3 Timer A (One-shot Timer Mode)
(a) TAiS (i=0 to 4) bit in the TABSR register is set to "0" (stops counting) after reset. Set TAiS bit to "1"
(starts counting) after selecting operation mode and setting the TAi register.
(b) The followings occur when setting the TABSR register to "0" (stops counting) while counting:
• The counter stops counting and the microcomputer reloads contents of the reload register.
• The TAiOUT pin becomes low ("L").
• The IR bit in the TAiIC register is set to "1" (interrupt requested) after 1 CPU clock cycle.
(c) The output of the one-shot timer is synchronized with an internal count source. When set to an
external trigger, there is a delay of 1 count source cycle maximum, from trigger input to the TAiIN pin
to the one-shot timer output.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 471 of 488
M32C/83 Group (M32C/83, M32C/83T)
27. Precautions (Timer)
(d) The IR bit is set to "1" when the timer operation mode is selected as follows:
• one-shot timer mode is selected after reset.
• timer mode is switched to one-shot timer mode.
• event counter mode is switched to one-shot timer mode.
Therefore, set the IR bit to "0" by program when generating a timer Ai interrupt (IR bit), if the timer
operation mode is selected as is described above.
(e) When a trigger is generated while counting, the reload register reloads and continues counting
after the counter has downcounted once following a re-trigger. To generate a trigger while counting,
wait at least 1 count source cycle after the previous trigger has been generated and generate a retrigger.
(f) The TA1OUT, TA2OUT and TA4OUT pins are placed in high-impedance states when an "L" signal is
_______
applied to the NMI pin while the INV03 to INV02 bits in the INVC0 register is set to "112" (forced
_______
cutoff of the three-phase output by an "L" signal applied to the NMI pin).
(g) If an external trigger input is selected to start counting in timer A one-shot timer mode, do not
provide another external trigger input again for 300 ns before the timer A counter value reaches
"000016". One-shot timer may stop counting.
27.8.2.4 Timer A (Pulse Width Modulation Mode)
(a) TAiS(i=0 to 4) bit in the TABSR register is set to "0" (stops counting) after reset. Set TAiS bit to "1"
(starts counting) after selecting an operating mode and setting the TAi register.
(b) The IR bit is set to "1" when the timer operation mode is selected as follows:
• PWM mode is selected after reset.
• timer mode is switched to PWM mode.
• event counter mode is switched to PWM mode.
Therefore, set the IR bit to "0" by program when generating a timer Ai interrupt (IR bit), if the timer
operation mode is selected as is described above.
(c) The followings occur when the TAiS bit is set to "0" (stops counting) while PWM pulse is output:
• The counter stops counting.
• The IR bit changes to "1" and the output level changes to low ("L") when TAiOUT pin is held high ("H").
• The IR bit and the output level remain unchanged when TAiOUT pin is held low ("L").
(d) The TA1OUT, TA2OUT and TA4OUT pins are placed in high-impedance states when an "L" signal is
_______
applied to the NMI pin while the INV03 to INV02 bits in the INVC0 register are set to "1" (three-phase
output forced cutoff enabled).
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 472of 488
M32C/83 Group (M32C/83, M32C/83T)
27. Precautions (Timer)
27.8.3 Timer B
27.8.3.1 Timer B (Timer Mode, Event Counter Mode)
(a) TBiS (i=0 to 5) bit is set to "0" (stops counting) after reset. Set TBiS bit to "1" (starts counting) after
selecting an operation mode and setting the TBi register.
The TB0S to TB2S bits are the bits 5 to 7 in the TABSR register. The TB3S to TB5S bits are bits 5
to 7 in the TBSR register.
(b) The TBi register indicates the counter value during counting at any given time. However, the
counter will read "FFFF16" when reloading . The setting value can be read after setting the TBi
register while the counter stops and before the counter starts counting.
27.8.3.2 Timer B (Pulse Period/Pulse Width Measurement Mode)
(a) The IR bit in the TBiIC register is set to "1" (overflow) when the valid edge of a pulse to be measured is input and when the timer Bi counter overflows. The MR3 bit in the TBiMR register determines the interrupt source within an interrupt service routine.
(b) Count overflow on a different timer if an interrupt source cannot be determined by the MR3 bit,
such as when a pulse to be measured is input at the same time the timer overflows.
(c) To set the MR3 bit in the TBiMR register to "0" (no overflow), set when the TBiS bit is set to "1"
(count starts) and at least one count is counted after the MR3 bit is set to "1" (overflow).
(d) The IR bit in the TBiIC register is used to detect overflow only. Use the MR3 bit only to determine
interrupt source within an interrupt service routine.
(e) Indeterminate values are transferred to the reload register during the first valid edge input following
the start of the count. Timer B interrupt request is not acknowledged at this time.
(f) The counter value is indeterminate at the start of a count. Therefore, the MR3 bit may change to "1"
(overflow) and cause timer B interrupt requests to be generated, until a valid edge is input after the
count begins.
(g) The IR bit may be set to "1" (interrupt requested) if the MR1 to MR0 bits in the TBiMR register are
set to a different value after a count begins. If the MR1 to MR0 bits are rewritten, but to the same
value as before, the IR bit remains unchanged.
(h) Pulse width measurement measures pulse width continuously. Use program to determine whether
measurement results are high ('"H") or low ("L").
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 473 of 488
M32C/83 Group (M32C/83, M32C/83T)
27. Precautions (Three-Phase Motor Control Functions)
27.9 Three-Phase Motor Control Timer Functions
27.9.1 Changing TAi and TAi1 (i=1, 2, 4) Registers
Do not write to the TAi and TAi1 registers at the same time timer B2 underflows. Follow the procedure
below when rewriting the TAi1 register.
(1) Write value to the TAi1 register
(2) Wait 1 timer Ai count source cycle
(3) Write the same value to the TAi1 register again
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 474of 488
27. Precautions (Serial I/O)
M32C/83 Group (M32C/83, M32C/83T)
27.10 Serial I/O
27.10.1 Clock Synchronous Serial I/O Mode
27.10.1.1 Transmission / Reception
_______
________
When the RTS function is used while an external clock is selected, the output level of the RTSi pin is
held low ("L") indicating that the microcomputer is ready for reception. The transmitting microcomputer
________
is notified that reception is possible. The output level of the RTSi pin becomes high ("H") when recep________
________
tion begins. Therefore, connecting the RTSi pin to the CTSi pin of the transmitting microcomputer
_______
synchronizes transmission and reception. The RTS function is disabled if an internal clock is selected.
_______
The RTS2 pin and CLK2 pin are placed in high-impedance states when an "L" signal is applied to the
______
NMI pin while the INV02 to INV01 bits in the INVC0 register are set to "112" (forced cutoff of the three_______
phase output by low-level signal ("L") applied to NMI pin).
27.10.1.2 Transmission
When an external clock is selected while the CKPOL bit in the UiC0 register is set to "0" (data is
transmitted on the falling edge of the transfer clock and received on the rising edge) and the external
clock is held high ("H") or when the CKPOL bit is set to "1" (data is transmitted on the rising edge of the
transfer clock and received on the falling edge) and the external clock is held low ("L"), meet the
following conditions:
• Set the TE bit in the UiC1 register to "1" (transmit enabled)
• Set the TI bit in the UiC1 register to "0" (data in the UiBT register)
________
________
• Apply "L" signal to the CTSi pin if the CTS function is selected
27.10.1.3 Reception
Activating the transmitter in clock synchronous serial I/O mode generates the shift clock. Therefore,
set for transmission even if the microcomputer is used for reception only. Dummy data is output from
the TxDi pin while receiving.
If an internal clock is selected, the shift clock is generated when the TE bit in the UiC1(i=0 to 2)
registers is set to "1" (receive enable) and dummy data is set in the UiTB register. If an external clock
is selected, the shift clock is generated when the external clock is input into CLKi pin while the TE bit
is set to "1" (receive enable) and dummy data is set in the UiTB register.
When receiving data consecutively while the RE bit in the UiC1(i=0 to 2) register is set to "1" (data in
the UiRB register) and the next data is received by the UARTi reception register, an overrun error
occurs and the OER bit in the UiRB register becomes "1" (overrun error). In this case, the UiRB
register is indeterminate. When overrun error occurs, program both reception and transmission registers to retransmit earlier data. The IR bit in the SiRIC does not change when an overrun error occurs.
When receiving data consecutively, feed dummy data to the low-order byte in the UiTB register every
time a reception is made.
When an external clock is selected while the CKPOL bit in the UiC0 register is set to "0" (data is
transmitted on the falling edge of the transfer clock and received on the rising edge) and the external
clock is held high ("H") or when the CKPOL bit is set to "1" (data is transmitted on the rising edge of the
transfer clock and received on the falling edge) and the external clock is held low ("L"), meet the
following conditions:
• Set the RE bit in the UiC1 register to "1" (receive enabled)
• Set the TE bit in the UiC1 register to "1" (transmit enabled)
• Set the TI bit in the UiC1 register to "0" (data in the UiTB register)
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 475 of 488
M32C/83 Group (M32C/83, M32C/83T)
27. Precautions (Serial I/O)
27.10.2 UART Mode
• Set the UiERE bit in the UiC1 register after setting the UiMR register.
_______
______
• The RTS2 and CLK2 pins will enter a high-impedance state when an "L" signal is applied to the NMI
pin while the INV03 to INV02 bits in the INVC0 register are set to "112" (forced cutoff of the three_______
phase output by an "L" signal applied to the NMI pin).
27.10.3 Special Mode 2
_______
______
The RTS2 and CLK2 pins will enter high-impedance states when an "L" signal is applied to the NMI pin
while the INV03 to INV02 bits in the INVC0 register are set to "112" (forced cutoff of the three-phase
_______
output by an "L" signal applied to the NMI pin).
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 476of 488
27. Precautions (A/D Converter)
M32C/83 Group (M32C/83, M32C/83T)
27.11 A/D Converter
• Set the ADiCON0 (i=0,1) (bit 6 excluded), ADiCON1, and ADiCON2 registers while the A/D conversion
is stopped (before trigger is generated).
• Wait a minimum of 1µs before starting the A/D conversion when changing the VCUT bit in the ADiCON1
register from "0" (VREF no connection) to "1" (VREF connection). Change the VCUT bit from "1" to "0"
after the A/D conversion is completed.
• Insert capacitors between pins AVCC, VREF, analog input pin ANjk (j=none, 0, 2, 15; k=0 to 7) and AVSS
to prevent latch-ups and malfunctions due to noise and to minimize conversion errors. The same applies to pins VCC and VSS. Figure 27.2 shows the procedure.
Microcomputer
AVCC
VCC
VREF
C4
C1
VSS
C2
AVSS
C3
ANjk
Note 1: C1≥0.47µF, C2≥0.47µF, C3≥100pF, C4≥0.1µF (reference)
Note 2: Use thick and shortest possible wiring to connect capacitors.
Figure 27.2 Use of Capacitors to Reduce Noise
• Set the bit in the port direction register, which corresponds to the pin being used as the analog input, to
__________
"0" (input mode). Set the bit in the port direction register, which corresponds to the ADTRG pin, to "0"
___________
(input mode) if the TRG1 to TRG0 bits in the ADiCON2 register are set to "002" (ADTRG).
• When generating a key input interrupt, do not use the AN4 to AN7 pins as analog input pins (key input
interrupt request is generated when the A/D input voltage becomes "L").
• When the sample and hold function is not activated, ØAD frequency must be 250kHz or more. If the
sample and hold function is activated, ØAD frequency must be 1MHz or more.
• Set the CH2 to CH0 bits in the ADiCON0 register or the SCAN1 to SCAN0 bits in the ADiCON1 register
to select analog input pins again when changing A/D conversion mode.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 477 of 488
M32C/83 Group (M32C/83, M32C/83T)
27. Precautions (A/D Converter)
• Wrong values are stored in the ADij register (i=0,1; j=0 to 7) if the CPU reads the ADij register while the
ADij register is storing results from a completed A/D conversion. This occurs when the CPU clock is set
to a divided main clock or a sub clock.
In one-shot mode or single sweep mode, read the corresponding ADij register after verifying that the A/
D conversion has been completed. The IR bit in the ADiIC register can determine the completion of the
A/D conversion.
In repeat mode, repeat sweep mode 0 and repeat sweep mode 1, use an undivided main clock as the
CPU clock.
• Conversion results of the A/Di is indeterminate if the ADST bit in the ADiCON0 register (i=0,1) is set to
"0" (A/D conversion stopped) and the conversion is forcibly terminated by program. The ADij register
(j=0 to 7) not performing an A/D conversion may also be indeterminate.
If A/Di is forcibly terminated, do not use any values obtained from the ADij registers.
If either A/D0 or A/D1 is forcibly terminated while the ADS bit in the ADiCON2 register is set to "0"
(channel replacement disabled), the other A/D converter, A/Di, will perform normally. The values of ADij
registers not performing an A/D conversion remain unchanged.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 478of 488
M32C/83 Group (M32C/83, M32C/83T)
27. Precautions (Intelligent I/O)
27.12 Intelligent I/O
27.12.1 Register Setting
Operations controlled by the values written to the GiBT (i=0 to 3), GiBCR1, BTSR, GjTMCR0 to
GjTMCR7 (j=0,1), GiTPR6, GiTPR7, GjTM0 to GjTM7, GiPOCR0 to GiPOCR7, GiPO0 to GiPO7, G3MK4
to G3MK7, GjFS, GiFE, G2RTP, and G3RTP registers are affected by the count source (fBTi) set in the
BCK1 to BCK0 bits in the GiBCR0 register.
Set the BCK1 to BCK0 bits before setting the GiBT, GiBCR1, BTSR, GjTMCR0 to GjTMCR7, GiTPR6,
GiTPR7, GjTM0 to GjTM7, GiPOCR0 to GiPOCR7, GiPO0 to GiPO7, G3MK4 to G3MK7, GjFS, GiFE,
G2RTP, and G3RTP registers.
Operations controlled by the values written to the GjRI, GjTO, GiCR, GiRB, GiMR, GjEMR, GjETC,
GjERC, GjIRF, GiTB, GjCMP0 to GjCMP3, GjMSK0, GjMSK1, GjTCRC, GjRCRC, IECR, IEAR, IETIF,
IERIF, and G3FLG registers are affected by the transfer clock. Set transfer clock before setting the GjRI,
GjTO, GiCR, GiRB, GiMR, GjEMR, GjETC, GjERC, GjIRF, GiTB, GjCMP0 to GjCMP3,
GjMSK0,GjMSK1, GjTCRC, GjRCRC, IECR, IEAR, IETIF, IERIF, and G3FLG registers.
27.12.2 BTSR Register Setting
The BTSR register is a located in the intelligent I/O group 2. When starting the base timer using the BTiS
bit in the BTSR register, set the BTiS bit to "1" (base timer starts counting) after selecting the count source
for the intelligent I/O group 2. If the BTiS bit is not being used, set the BTiS bit to "0" (base timer reset)
after selecting the count source for the intelligent I/O group 2.
Set only either the BTiS bit or the BTS bit in the GiBCR1 register to "1" when starting the base timer. If
both BTiS bit and the BTS bit are set to "0", both bits must be set "0" when stopping the base timer.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 479 of 488
27. Precautions (Programmable I/O Port)
M32C/83 Group (M32C/83, M32C/83T)
27.13 Programmable I/O Port
Because ports P72 to P75, P80, and P81 have the three-phase PWM output forced cutoff function, they are
_______
affected by the three-phase motor control timer function and the NMI pin when these ports are set for output
functions (port output, timer output, three-phase PWM output, serial I/O output, intelligent I/O output).
_______
Table 27.2 shows the relationship between the INVC0 register setting, the NMI pin input level and the state
of output ports.
_______
Table 27.2 INVC0 Register and the NMI Pin
Setting Value of INVC0 Register
INV02 bit
INV03 bit
Input Level
to NMI Pin
-
-
0 (not using three-phase
motor control function)
1 (using three-phase motor 0 (three-phase PWM
control timer function
output disabled)
1 (three-phase PWM
output enabled)(1)
-
States of P72 to P75, P80, and P81
Pins (when setting an output pin)
Output functions selected in the PS1,
PSL1, PSC, PS2, and PSL2, registers
High-impedance
H
Output functions selected in the PS1,
PSL1, PSC, PS2, and PSL2, registers
L (forcibly
terminated)
High-impedance
NOTES :
_______
1. The INV03 bit is set to "0" after an "L" signal is applied to the NMI pin.
The input threshold voltage differs with programmable I/O ports and peripheral functions. Therefore, if the
level of the voltage applied to a pin shared by both programmable I/O ports and peripheral functions is not
within the recommended operating condition, VIH and VIL (neither "H" nor "L"), the level determined will
differ with the programmable I/O ports and peripheral functions.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 480of 488
M32C/83 Group (M32C/83, M32C/83T)
27. Precautions (Flash Memory Version)
27.14 Flash Memory Version
27.14.1 Differences Between Flash Memory Version and Masked ROM Version
Due to differences in internal ROM and layout pattern, flash memory version and mask ROM version
have varying electrical characteristics such as attributes, performance margins, noise endurance capacity, and noise radiation. When switching to masked ROM version, administer system evaluation tests
equal to those held on the flash memory version.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 481 of 488
M32C/83 Group (M32C/83, M32C/83T)
27. Precautions (Noise)
27.15 Noise
Connect a bypass capacitor (approx. 0.1µF) between Vcc and Vss by shortest path, using thick wires.
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 482of 488
27. Precautions (Low Voltage Operations)
M32C/83 Group (M32C/83, M32C/83T)
27.16 Low Voltage Operations
The voltage down converter (VDC) is a circuit used to step down external supply voltage to the internal
operation voltage of 3.3V. Disconnect the VDC when applying a 3.3V supply voltage to reduce power
consumption.
Figure 27.3 shows the procedure for disconnecting the VDC.
Perform these settings immediately after reset, while the CPU clock is divided by 8. Do not set the VDC0
register (001B16) to other values. Furthermore, do not write to the VDC0 register when applying a supply
voltage of 3.3V or more.
Set PRC3 bit in PRCR register to "1" (write enable)
Set VDC0 register to "0F16"
Set VDC0 register to "8F16"
Set PRC3 bit in PRCR register to "0" (write disable)
Figure 27.3 VDC Disconnection Procedure
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 483 of 488
Package Dimensions
M32C/83 Group (M32C/83, M32C/83T)
Package Dimensions
PLQ0144KA-A (144P6Q-A)
JEITA Package Code
P-LQFP144-20x20-0.50
Plastic 144pin 20 X 20 mm body LQFP
RENESAS Code
PLQP0144KA-A
Previous Code
144P6Q-A / FP-144L / FP-144LV
MASS[Typ.]
1.2g
HD
*1
D
108
73
109
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
72
bp
c
Reference
Symbol
*2
E
HE
c1
b1
Terminal cross section
Index mark
c
36
A
1
ZD
A2
37
ZE
144
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
A1
F
L
L1
*3
e
y
bp
PRQP0100JB-A (100P6S-A)
JEITA Package Code
P-QFP100-14x20-0.65
e
x
y
ZD
ZE
L
L1
Detail F
x
Dimension in Millimeters
Min Nom Max
19.9 20.0 20.1
19.9 20.0 20.1
1.4
21.8 22.0 22.2
21.8 22.0 22.2
1.7
0.05 0.1 0.15
0.17 0.22 0.27
0.20
0.09 0.145 0.20
0.125
0°
8°
0.5
0.08
0.10
1.25
1.25
0.35 0.5 0.65
1.0
Plastic 100pin 14 X 20 mm body LQFP
RENESAS Code
PRQP0100JB-A
Previous Code
100P6S-A
MASS[Typ.]
1.6g
HD
*1
D
80
51
81
50
E
*2
HE
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
ZE
Reference
Symbol
100
31
30
c
F
A2
Index mark
ZD
A1
A
1
L
*3
e
y
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 484 of 488
bp
Detail F
D
E
A2
HD
HE
A
A1
bp
c
e
y
ZD
ZE
L
Dimension in Millimeters
Min Nom Max
19.8 20.0 20.2
13.8 14.0 14.2
2.8
22.5 22.8 23.1
16.5 16.8 17.1
3.05
0.1 0.2
0
0.25 0.3 0.4
0.13 0.15 0.2
0°
10°
0.5 0.65 0.8
0.10
0.575
0.825
0.4 0.6 0.8
M32C/83 Group (M32C/83, M32C/83T)
Package Dimensions
PLQP0100KB-A (100P6Q-A)
JEITA Package Code
P-LQFP100-14x14-0.50
Plastic 100pin 14 X 14 mm body LQFP
RENESAS Code
PLQP0100KB-A
Previous Code
100P6Q-A / FP-100U / FP-100UV
MASS[Typ.]
0.6g
HD
*1
D
51
75
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
50
76
bp
c1
Reference
Symbol
c
E
*2
HE
b1
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
26
1
ZE
Terminal cross section
100
25
Index mark
ZD
y
e
*3
bp
A1
c
A
A2
F
L
x
L1
Detail F
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Page 485 of 488
e
x
y
ZD
ZE
L
L1
Dimension in Millimeters
Min Nom Max
13.9 14.0 14.1
13.9 14.0 14.1
1.4
15.8 16.0 16.2
15.8 16.0 16.2
1.7
0.05 0.1 0.15
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
0°
8°
0.5
0.08
0.08
1.0
1.0
0.35 0.5 0.65
1.0
M32C/83 Group (M32C/83, M32C/83T)
Register Index
Register Index
A
C0SLOT0_0 350
C0SLOT0_1 350
C0SLOT0_2 351
C0SLOT0_3 351
C0SLOT0_4 352
C0SLOT0_5 352
C0SLOT0_6 to C0SLOT0_13 353
C0SLOT0_14 353
C0SLOT0_15 353
C0SLOT1_0 350
C0SLOT1_1 350
C0SLOT1_2 351
C0SLOT1_3 351
C0SLOT1_4 352
C0SLOT1_5 352
C0SLOT1_6 to C0SLOT1_13 353
C0SLOT1_14 353
C0SLOT1_15 353
C0SLPR 330
C0STR 331
C0TEC 336
C0TSR 336
CM0 67, 113
CM1 68
CM2 70
CPSRF 71
CRCD 243
CRCIN 243
AD00 to AD07 230
AD0CON0 228
AD0CON1 229
AD0CON2 230
AD10 to AD17 233
AD1CON0 231
AD1CON1 232
AD1CON2 233
AIER 107
B
BTSR 257
C
C0AFS 354
C0BPR 337
C0CONR 334
C0CTLR0 326
C0CTLR1 329
C0EIMKR 341
C0EISTR 342
C0GMR0 343
C0GMR1 344
C0GMR2 344
C0GMR3 345
C0GMR4 345
C0IDR 333
C0LMAR0 343
C0LMAR1 344
C0LMAR2 344
C0LMAR3 345
C0LMAR4 345
C0LMBR0 343
C0LMBR1 344
C0LMBR2 344
C0LMBR3 345
C0LMBR4 345
C0MCTL0 to C0MCTL15
C0REC 337
C0SBS 349
C0SIMKR 340
C0SISTR 338
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
D
346
page 486 of 488
DA0 to DA1 242
DACON 242
DCT0 to DCT3 119
DM0SL to DM3SL 116
DMA0 to DMA3 120
DMD0 to DMD1 117, 118
DRA0 to DRA3 120
DRAMCONT 360
DRC0 to DRC3 119
DS 52
DSA0 to DSA3 120
DTT 166
M32C/83 Group (M32C/83, M32C/83T)
F
FMR0 395
G
G0BCR0 to G3BCR0 253
G0BCR1 and G1BCR1 254
G0BT to G3BT 253
G0CMP0 to G0CMP3 295
G0CR to G1CR 290
G0EMR to G1EMR 292
G0ERC to G1ERC 293
G0ETC to G1ETC 292
G0FE to G3FE 262
G0FS and G1FS 262
G0IRF to G1IRF 294
G0MR to G1MR 291
G0MSK0 to G0MSK1 295
G0PO0 TO G0PO7 261
G0POCR0 to G0POCR7 259
G0RB to G1RB 291
G0RCRC to G1RCRC 295
G0RI to G1RI 289
G0TB to G1TB 294
G0TCRC to G1TCRC 295
G0TM0 to G0TM7 259
G0TMCR0 to G0TMCR7 258
G0TO to G1TO 289
G0TPR6 and G0TPR7 258
G1CMP0 to G1CMP3 295
G1MSK0 to G1MSK1 295
G1PO0 to G1PO7 261
G1POCR0 to G1POCR7 259
G1TM0 to G1TM7 259
G1TMCR0 to G1TMCR7 258
G1TPR6 and G1TPR7 258
G2BCR1 255
G2CR 307
G2MR 307
G2PO0 to G2PO7 261
G2POCR0 to G2POCR7 260
G2RB 306
G2RTP and G3RTP 263
G2TB 306
G3BCR1 256
G3CR 318
G3FLG 319
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
page 487 of 488
Register Index
G3MK4 to G3MK7 261
G3MR 318
G3PO0 to G3PO7 261
G3POCR0 to G3POCR7
G3RB 317
G3TB 317
I
ICTB2 167
IDB0 to IDB1 166
IEAR 308
IECR 308
IERIF 309
IETIF 309
IFSR 105, 181
IIO0IE to IIO11IE 110
IIO0IR to IIO11IR 109
Interrupt Control 96, 97
INVC0 164
INVC1 165
IPS 383
M
MCD
69
O
ONSF
138
P
P0 to P15 372
PCR 383
PD0 to PD15 371
PLC0 72
PLC1 73
PLV 72
PM0 49
PM1 50
PRCR 88
PS0 373
PS1 373
PS2 374
PS3 374
PS5 375
PS6 375
PS7 376
PS8 376
260
M32C/83 Group (M32C/83, M32C/83T)
PS9 377
PSC 380
PSL0 378
PSL1 378
PSL2 379
PSL3 379
PUR0 381
PUR1 381
PUR2 381
PUR3 382
PUR4 382
W
WCR 58
WDC 112
WDTS 112
X
X0R to X15R
XYC 245
245
Y
Y0R to Y15R
R
REFCNT 360
RLVL 98, 126
RMAD0 to RMAD7 107
ROMCP 393
T
TA0 to TA4 136
TA0MR to TA4MR 137, 142, 145, 148, 150
TA1, TA2, TA4, TA11, TA21, TA41 167
TA1MR, TA2MR, TA4MR 169
TABSR 137, 153, 168
TB0 to TB5 152
TB0MR to TB5MR 153, 155, 157, 159
TB2 168
TB2MR 169
TB2SC 167
TBSR 154
TCSPR 71, 139
TRGSR 139, 168
U
U0BRG to U4BRG 175
U0C0 to U4C0 176
U0C1 to U4C1 177
U0MR to U4MR 175
U0RB to U4RB 174
U0SMR to U4SMR 177
U0SMR2 to U4SMR2 178
U0SMR3 to U4SMR3 179
U0SMR4 to U4SMR4 180
U0TB to U4TB 174
UDF 138
Rev. 1.31 Jan.31, 2006
REJ09B0034-0131
Register Index
page 488 of 488
245
REVISION HISTORY
Rev.
M32C/83 GROUP (M32C/83, M32C/83T) Hardware Manual
Description
Summary
Date
Page
1.01
2002-12
All
23
65
88
137
154
163
174
264
Full-fledged revision
• Modify the notation system of registers and bits
Reset
• Delete the figure “Device’s internal status after a reset is cleared”.
System Clock
• Modify the figure “Clock Generation Circuit”.
• Add descriptions about the ‘PLL clock’.
• Modify the figure “Status Transition”.
Interrupt
• Modify the figure “Intelligent I/O Interrupt and CAN Interrupt”.
• Add tables ‘registers to be used and settings’.
• Change symbols of the bits in the interrupt request register.
• Change symbols of the bits in the interrupt enable register.
Timer A
• Modify the figure “Timer A Configuration”.
• Add tables ‘registers to be used and settings’.
Timer B
• Modify the figure “Timer B Configuration”.
• Add tables ‘registers to be used and settings’.
Three-Phase Control Timer Function
• Change the bit name, the ‘INV17bit’ in the INVC1 register to reserved bit.
Serial I/O
• Modify the figure “UARTi Block Diagram”.
• Add the table ‘registers to be used and settings’ in each mode.
• Add distributions about the ‘clock-divided synchronous function (GCI mode)’.
• Add descriptions about the ‘bus conflict detect function (IE mode)’.
Intelligent I/O
• Modify the figure “Intelligent I/O Group 0 Block Diagram”.
• Modify the figure “Intelligent I/O Group 1 Block Diagram”.
• Modify the figure “Intelligent I/O Group 2 Block Diagram”.
• Modify the figure “Intelligent I/O Group 3 Block Diagram”.
• Add the table ‘registers and settings’ associated with each function and mode.
• Add a bit function of ‘the BCK0 to BCK1 bit in the G0BCR0 to G3BCR0 register’.
-Group 0 and 1
• Add descriptions about the ‘HDLC data processing mode’. -Group 0 and 1
• Add distributions about the ‘IEBus mode’. -Group2
• Add descriptions about the ‘8-bit and 16-bit clock synchronous serial I/O
function’. -Group3
C-1
REVISION HISTORY
Rev.
M32C/83 GROUP (M32C/83, M32C/83T) Hardware Manual
Description
Summary
Date
Page
338
355
394
1.02
2003-1
2-3
3
33
78
78
80
117
141
186
192
206
A/D Convertor
• Modify the figure “A/D Convertor Block Diagram”.
• Add the table ‘pin settings’.
D/A Convertor
• Add the table ‘pin settings’.
Usage Precaution
• Add descriptions about the ‘PLL synthesizer’.
• Add descriptions about the ‘Timer A’ and ‘Timer B’.
• Add descriptions about the ‘Low-Voltage Operation’.
Overview
• Add -40 to 85°C to ‘Operating ambient temperature’ row in Table 1.1.1 and 1.1.2.
• Delete 8-bit or 16-bit clock synchronous serial I/O:1 channel (group3) on
‘Peripheral function’ row in Table 1.1.2.
SFR
• Modify 00?0 X0002 to 0000 X0002 on ‘value after RESET’ column on ‘017B16’
row.
System Clock
• Modify 0 to 1 on ‘PLC00’ column and ‘10MHz’ row in Table 1.8.2.
• Modify the PLC02 to PLC0 bits and the PLC05 to PLC04 bits to the PLC0 register
in the third step in Figure 1.8.13.
• Modify 1 to 0 on ‘CM00’ column and ‘BCLK output’ row in Table 1.8.5.
DMAC
• Add the note 3 in Figure 1.11.2.
Timer
• Modify TA4 and TA1 to TA0 and TA2 on the TA1TGL and TA1TGH in the top
figure of Table 1.14.5.
• Modify TA4 and TA1 to TA1 and TA3 on the TA2TGL and TA2TGH in the top
figure of Table 1.14.5.
• Modify TA4 and TA1 to TA2 and TA4 on the TA3TGL and TA3TGH in the top
figure of Table 1.14.5.
• Modify TA4 and TA1 to TA3 and TA0 on the TA4TGL and TA4TGH in the top
figure of Table 1.14.5.
Serial I/O
• Modify PD7_0=0 to PD7_2=0 on ‘PD7 register’ column and ‘CLK2 input’ row in
Table 1.18.4.
• Modify PD7_0=0 to PD7_2=0 on ‘PD7 register’ column and ‘CLK2 input’ row in
Table 1.19.4.
• Modify a function description on ‘UiRRM’ row in Table 1.20.9.
C-2
REVISION HISTORY
Rev.
M32C/83 GROUP (M32C/83, M32C/83T) Hardware Manual
Description
Summary
Date
Page
207
216
226
296
304
315
317
320
324
334
364
385
388
390
391
393
394
398
400
429
• Modify PD7_2=0 to PD7_0=0 on ‘PD7 register’ column and ‘SRxD2 input’ row in
Table 1.20.11.
• Modify PD7_0=0 to PD7_2=0 on ‘PD7 register’ column and ‘CLK2 input’ row in
Table 1.20.11.
• Modify PS3_4=0 to PS3_5=0 on ‘PS3 register’ column and ‘CLK4 input’ row in
Table 1.20.23.
CAN Module
• Modify PSL2_2=0 to PSL2_1=0 on ‘PSL1 and PSL2 registers’ column and ‘P82’
row in Table 1.21.2.
Intelligent I/O
• Modify Setting value of the GiPO0 register to Setting value of the GiPOk register
as n and m on the second figure in Figure 1.22.26.
• Modify RxD to ISRxD on ‘IPOL’ row and TxD to ISTxD on ‘OPOL’ row in Figure
1.22.33.
• Modify IPS=1 to IPS1=1 on IPS registers column and ‘P11 2’ row in Table
1.22.26.
• Modify TCRCRC to TCRCE on ‘CRC’ row in Table 1.22.28.
• Delete SIOiTR and SIOiRR and add SRTiR in note 3 in Table 1.22.28.
• Modify IER to OER in note 1 in the second figure of Figure 1.22.42.
• Modify SIOiTR to SIO2TR and SIO5RR to SIO2RR in Table 1.22.30 and 1.22.36.
• Modify GiCR to G3CR in Table 1.22.41.
DRAMC
• Modify SRDF to SREF in note 3 in Figure 1.27.1.
• Modify IOUTC10 to OUTC10 on ‘PSC_3’ row in Figure 1.28.14.
• Modify P0 to P5 to P1 in note 1 in Table 1.28.17.
Programable I/O Port
• Modify INPC1 to INPC11 on ‘PS1 register’ column and ‘Bit 4’ row in Table 1.28.4.
• Modify INPC0 to INPC02 on ‘PS2 register’ column and ‘Bit 0’ row in table 1.28.5.
• Modify ISCLK input to ISCLK0 input on ‘Bit 1’ row in table 1.28.12.
Usage Precaution
_________
• Modify PM0 to PM00 in “HOLD Signal”
• Modify all SP to ISP in (1) SP Setting of “Interrupts”.
• Modify all TAi to TBi in 1. Timer Mode and Event Counter Mode of “Timer B”.
• Modify the CAN module to the microcomputer in “Resetting CNVSS Pin with H”.
• Delete a discription of ‘Difference between Flash Memory version and Masked
ROM’
Electric Charactistics
• Modify IOH=5mA to IOL=5mA on ‘VOL’ row and ‘Mesurement Condition’ column
in Table 1.31.3.
C-3
REVISION HISTORY
Rev.
M32C/83 GROUP (M32C/83, M32C/83T) Hardware Manual
Description
Summary
Date
Page
1.10
2004-3
All Pages Chapter numbers, section numbers, etc., added; Table and Figure numbers
modified; Chapter sequence modified; Word Phrasing in Revision History
changed
Overview
2, 3
• Tables 1.1 and 1.2 M32C/83 Group Performance
Shortest Instruction Execution Time modified: 31.3ns(f(BCLK)=30MHz
changed to 31.3ns(f(BCLK)=32MHz, 50ns(f(BCLK)=20MHz added;
Performance details of Multifunction Timer, Intelligent I/O, Clock Generating
Circuit, and Electrical Characteristics revised;
Oscillator Stop Detect Function added;
32MHz added to Supply Voltage and Power Consumption
Note 3 added
4
• Figure 1.1 M32C/83 Block Diagram modified
5
• Table 1.3 M32C/83 Group Product deleted
9, 13
• Tables 1.4 and 1.5 Pin Characteristics VREF pin changed from “analog pin”
to “control pin”
15 to 18 • Table 1.6 Pin Description SDA0 to SDA4 changed from “output” to “input”;
20
23
24 to 45
46
47
48
49
50
Descriptions of A/D-related pin functions revised
Centeral Processing Unit
• Figure 2.1 CPU Register modified
Memory
• Figure 3.1 Memory Map Product deleted; Diagram modified
SFR
Value after reset and lisiting sequence modified
• “? : Indetermination” changed to “X : Indeterminate”
• Notation “Users cannot use any symbols with *” deleted
• Register names, symbols, and Values after RESET of addresses 001F16 to
002516, 003016 to 003516, 005516 to 005616, 01AC16, and 01AE16 to 01BF16
deleted
• Notations added to PM0 and TCSPR registers
• Value after reset in the RLVL register modified
Reset
• Figure 5.1 Reset Circuit modified
• Figure 5.2 Reset Sequence Diagram modified; Note 1 added
• 5.3 Watchdog Timer Reset added
• Figure 5.3 CPU Register after Reset modified
Processor Mode
• 6.2.2 Applying VCC to CNVSS Pin Contents added
C-4
REVISION HISTORY
Rev.
M32C/83 GROUP (M32C/83, M32C/83T) Hardware Manual
Description
Summary
Date
Page
55
60
64
65
67
68
69
72
75
77
79
80
81
84
85
86
87
88
93
95
99
103
104
106
Bus
• 7.1.3.2 Multiplexed Bus revised
• 7.2.4 Bus Timing revised
________
• 7.6 RDY Signal revised
_____
________
• Figure 7.7 RD Signal Output Extended by RDY Signal modified
Clock Generating Circuit
Chapter name changed from “System Clock “ to “Clock Generating Circuit”
• Table 8.1 Clock Generation Circuit Specifications
Main clock clock frequency modified; “Ceramic oscillator” changed to “Ceramic
resonator”; Reference point added to PLL Frequency Synthesizer
• Figure 8.1 Clock Generation Circuit revised
• Figure 8.2 CM0 Register Bit 3 function changed from “Nothing is assigned” to
“Reserved Bit”
• Figure 8.5 CM2 Register CM21 bit function modified; Note 5 revised
• Figure 8.8 PLC1 Register Note 3 revised; Note 4 added
• 8.1.2 Sub Clock revised
• Figure 8.11 Switching Procedure form On-chip Oscillator Clock to Main
Clock modified
• 8.1.4 PLL Clock revised
• Table 8.2 Bit Settings to Use PLL Clock as CPU Clock Source Setting added
for when f(XIN) is 8MHz
• Figure 8.13 Procedure to Use PLL Clock as CPU Clock Source modified
• 8.2 CPU Clock and BCLK revised
• 8.5.2.2 Before Entering Wait Mode revised
• 8.5.2.5 Entering Wait Mode added
• 8.5.3 Stop Mode revised
• 8.5.3.1 Before Entering Stop Mode revised
• 8.5.3.3 Exiting Stop Mode revised
• 8.5.3.4 Entering Stop Mode added
• Figure 8.15 Status Transition modified
Interrupts
• Table 10.1 Fixed Vector Table Point of reference changed
• Table 10.2 Relocatable Vector Tables Reserved Space added
• Figure 10.5 RLVL Register Value after reset changed; Note 3 revised; Note 4
added
• 10.6.2.3 RLVL2 to RLVL0 Bits revised
• Figure 10.8 Interrupt Priority “Oscillation Stop Detect” added
• Figure 10.9 Interrupt Priority Level Select Circuit modified
• 10.8 NMI Interrupt revised
C-5
REVISION HISTORY
Rev.
M32C/83 GROUP (M32C/83, M32C/83T) Hardware Manual
Description
Summary
Date
Page
108
111
115
114
125
126
129
130
132
135
140
149
152
159
161
162
163
164
166
168
• “10.11 Intelligent I/O and CAN Interrupt” changed to “10.11 Intelligent I/O
Interrupt and CAN Interrupt”
• Precautions pertaining to Interrupts are compiled into one chapter, “27.
Precaution”
Watchdog Timer
Contents revised
DMAC
• 12. DMAC revised
• Table 12.1 DMAC Specifications CAN interrupt added to DNA Request
Factors; Note 1 revised
• Precautions pertaining to DMAC are compiled into one chapter, “27.
Precaution”
DMAC II
• Table 13.1 DMAC II Specifications Note 2 added
• Figure 13.1 RLVL Register Values after reset modified; Note 3 revised; Note 4
added
• 13.3 Transfer Data Contents added
• 13.4.2 Burst Transfer revised
• 13.4.4 Chain Transfer revised
• 13.5 Execution Time revised
Timer
• 14.1 Timer A Contents added
• Table 14.1 Pin Settings for Output from TAiOUT Pin (i= 0 to 4) modified
• 14.1.4 Pulse Width Modulation Mode Settings changed for 16-bit PWM and
8-bit PWM
• 14.2 Timer B Contents added
• Figure 14.22 TB0MR to TB5MR Registers (Pulse Period/ Pulse Width
Measurement Mode) Values after reset modified
Three-Phase Motor Control Timer Function
• Table 15.1 Three-Phase Motor Control Timer Functions Specification
modified
• Figure 15.1 Three-Phase Motor Control Function Block Diagram modified
• Figure 15.2 INVC0 Register modified
• Figure 15.3 INVC1 Register modified
• Figure 15.5 ICTB2 Register, TA1, TA2, TA4, TA11, TA21 and TA41 Registers
and TB2SC Register Notes 2 and 3 added to ICTB2 register; Note 7 added to
TAi and TAi1 registers
• Figure 15.7 TAiMR Register (i=1, 2, 4) MR1 bit function modified
C-6
REVISION HISTORY
Rev.
M32C/83 GROUP (M32C/83, M32C/83T) Hardware Manual
Description
Summary
Date
Page
169
170
• Figure 15.8 Triangular Wave Modulation Operation modified
• Figure 15.9 Sawtooth Wave Modulation Operation modified
Serial I/O
173
• Figure 16.2 U0TB to U4TB Registers and U0RB to U4RB Registers Note 3
added to U0RB to U4RB registers
175
• Figure 16.4 UiC0 Register Note 3 added to UFORM bit
176
• Figure 16.5 UiC1 Register Note 2 added to UiLCH bit; Note 1 added to
SCLKSTPB (UiERE) bit
181
• Table 16.1 Clock Synchrnous Serial I/O Mode Specifications Explanation of
CLK Polarity in Selectable Functions revised
182 to 219 • Tables 16.2, 16.7, 16.12, 16.19, 16.24, and 16.34 Registers to be Used and
Settings Points of reference deleted
183
• Table 16.3 Pin Settings in Clock Synchronous Serial I/O Mode (1) revised
184
• Figure 16.10 Transmit and Receive Operation modified
188
• Table 16.7 Registers to be Used and Settings in UART Mode Function of the
UiERE bit in the UiC1 register modified
189
• Table 16.8 Pin Settings in UART (1) revised
190
• Figure 16.14 Transmit Operation modified
192
• Figure 16.17 Serial Data Logic Inverse modified
195
• Table 16.12 Registers to be Used and Settings (I2C Mode) Setting values for
master and slave indicated separately
196
• Table 16.13 I2C Mode Functions “P61, P65, P72, P90, P75 Pin Functions”
changed to “P61, P65, P72, P90, P95 Pin Functions”
197, 198 • Tables 16.14 to 16.16 Pin Settings in I2C Mode modified
200
• 16.3.4 Transfer Clock revised
203
• Table 16.19 Registers to be Used and Settings in Special Mode 2 Functions
of the UFORM bit in the UiC0 register and the UiRRM bit in the UiC1 register
modified
204
• Table 16.20 Pin Settings in Special Mode 2 (1) revised
• Table 16.21 Pin Settings in Special Mode 2 (2) revised
• Table 16.22 Pin Settings in Special Mode 2 (3) revised
208
• Table 16.23 GCI Mode Specifications Explanations of Transmit/Receive Start
Conditions revised
210
• Table 16.25 Pin Settings in GCI Mode (1) revised
• Table 16.26 Pin Settings in GCI Mode (2) revised
• Table 16.27 Pin Settings in GCI Mode (3) revised
213
• Table 16.31 Pin Settings in IE Mode (2) revised
• Table 16.32 Pin Settings in IE Mode (3) revised
219
• Figure 16.29 SIM Interface Operation modified
C-7
REVISION HISTORY
Rev.
M32C/83 GROUP (M32C/83, M32C/83T) Hardware Manual
Description
Summary
Date
Page
221
• Figure 16.32 SIM Interface Format modified
A/D Converter
Sequence of content modified
223
• Table 17.1 A/D Converter Specifications Explanaition of A/D Conversion
Start Conditions revised; φ A/D frequency modified
226, 227 • Figure 17.2 AD0CON0 Register, Figure 17.3 AD0CON1 Register φ A/D
frequency modified
229, 230 • Figure 17.5 AD1CON0 Register, Figure 17.6 AD1CON1 Register φ A/D
frequency modified
232
• Table 17.4 One-shot Mode Specifications Explanation of Start Condition
revised
235
• Table 17.9 Trigger Select Function Settings Table modified; Note 2 added
237
• Figure 17.9 Analog Input Pin and External Sensor Equivalent Circuit
Capacitance of the capacitor modified
238 to 247 Sequence of the following Chapters have been changed: D/A Converter, CRC
Calculation, XY Conversion
Intelligent I/O
248
• Figure 21.2 Intelligent I/O Group 1 Block Diagram modified
251
• Figure 21.5 G0BT to G3BT Registers and G0BCR0 to G3BCR0 Registers
Note 2 added to G0BT to G3BT registers, Note 3 deleted from G0BCR0 to
G3BCR0 registers
252
• Table 21.2 Base Timer Specifications Explanation of Counter increment/
decrement mode in Selectable Function modified
263
• Tables 21.3, 21.6, 21.8, 21.17, 21.23, 21.29, 21.31, 21.37, and 21,42
Associated Register Settings Point of reference deleted
266
• Figure 21.18 Counter Increment Mode (Group 0 and 1) modified
265
• Figure 21.19 Counter Increment/Decrement Mode (Group 0 and 1) modified
266
• Figure 21.20 Base Timer Operation in Two-Phase Pulse Signal Processing
Mode Note 1 revised
267
• 21.2 Time Measurement Function (Group 0 and 1) Contents added
270
• Figure 21.22 Time Measurement Function (2) modified
271
• Figure 21.23 Prescaler Function and Gate Function Diagram modified; Note
2 of Gate Function deleted
272
• Table 21.7 Pin Settings for Waveform Generation Function modified
273
• Table 21.8 Waveform Generation Function Associated Register Settings
Note 1 added
274
• 21.3.1 Single-Phase Waveform Output Mode (Group 0 to 3) revised
• Table 21.9 Single-Phase Waveform Output Mode Specifications revised
275
• Figure 21.24 Single-Phase Waveform Output Mode modified
C-8
REVISION HISTORY
Rev.
M32C/83 GROUP (M32C/83, M32C/83T) Hardware Manual
Description
Summary
Date
Page
276
277
278
280
281
283
284
285
286
290
291
292
293
294
297
301
308
312
318
322
• Table 21.10 Phase-Delayed Waveform Output Mode Specifications revised
• Figure 21.25 Phase-Delayed Waveform Output Mode modified
• 21.3.3 Set/Reset Waveform Output (SR Waveform Output) Mode revised
• Table 21.11 SR Waveform Output Mode Specifications revised
• Figure 21.26 SR Waveform Output Mode modified
• 21.3.4 Bit-Modulation PWM Output Mode revised
• Table 21.12 Bit Modulation PWM Output Mode revised
• Figure 21.27 Bit Modulation PWM Mode Pulse numbering added
• 21.3.5 Real-Time Port (RTP) Output Mode (Group 2 and 3) revised
• Table 21.14 RTP Output Mode Specifications Note 1 added
• Figure 21.29 Real-Time Port Output Mode modified
• 21.3.6 Parallel Real-Time Port Output Mode (Group 2 and 3) revised
• Table 21.15 Parallel RTP Output Mode Note 1 added
• Figure 21.31 Parallel RTP Output Mode modified
• Figure 21.35 G0EMR to G1EMR Registers and G0ETC to G1ETC Registers
Note 1 added
• Figure 21.36 G0ERC to G1ERC Registers Note 1 added
• Figure 21.37 G0IRF to G1IRF Registers and G0TB to G1TB Registers Notes
1 and 2 in G0IRF to G1IRF registers revised; Note 1 added to G0TB to G1TB
registers
• Figure 21. 38 G0CMP0 to G0CMP3 Registers, G1CMP0 to G1CMP3
Registers, G0MSK0 to G0MSK1 Registers, G1MSK0 to G1MSK1 Registers,
G0TCRC to G1TCRC Registers, and G0RCRC to G1RCRC Registers Note 1
revised and Note 2 added to G0TCRC to G1TCRC registers; Note 3 in G0RCRC
to G1RCRC registers revised
• Table 21.16 Clock Synchronous Serial I/O Mode Specifications (Group 0
and 1) Explanation of transfer clock revised
• Table 21.22 UART Mode Specifications (Group 0 and 1) Explanation of
transfer clock and Note 2 revised
• Table 21.28 HDLC Processing Mode Specifications (Group 0 and 1)
Explanation of transfer clock revised
• Table 21.30 Variable Clock Synchronous Serial I/O Mode Specifications
(Group 2) Explanation of transfer clock revised
• Table 21.36 IE Bus Mode Specification Explanation of transfer clock revised
• Table 21.41 Clock Synchronous Serial I/O Mode (Group 3) Explanation of
transfer clock revised
CAN
Bit symbols of each register are now capitalized (e.g. Reset0 is changed to
RESET0)
C-9
REVISION HISTORY
Rev.
M32C/83 GROUP (M32C/83, M32C/83T) Hardware Manual
Description
Summary
Date
Page
325
344
345
346
364
365
367
369
371
372
376
377
378
379
383
384
387
389
393
395
397
405
406
412
• 22.1.1.3 BASICCAN Bit revised
• 22.1.16 CANi Message Slotj Control Register (CiMCTLj Register) (i=0, 1;
j=0 to 15) Funtion of the INVALDATA/TRMACTIVE bit when set to “1” changed
to “Transmits”; Note 4 in REMACTIVE deleted; RW modified to RO
• Table 22.4 C0MCTLi Register (i=0 to 15) Setting and Transmit/Receive
Mode Hyphens (-) changed to “0”
• 22.1.16.4 REMACTIVE Bit revised
• 22.1.16.5 RSPLOCK Bit revised
Programmable I/O Port
• 24.4 Function Select Register Bk (PSLk Register) (k=0 to 3) revised
• 24.5 Function Select Register C (PSC Register) revised
• 24.7 Port Control Register (PCR Register) revised
• Figure 24.2 Programmable I/O Ports (2) modified
• Figure 24.5 PD0 to PD15 Registers Note 4 added
• Figure 24.7 PS0 Register and PS1 Register PS0 register revised
• Figure 24.8 PS2 Register and PS3 Register PS3 register revised
• Figure 24.12 PSL0 Register and PSL1 Register Note 1 added to PSL1
register
• Figure 24.13 PSL2 Register and PSL3 Register PSL3 register revised
• Figure 24.14 PSC Register revised
• Figure 24.15 PUR0 Register, PUR1 Register and PUR2 Register Note 1
revised
• Table 24.3 Port P6 Peripheral Function Output Control Bits 3 and 7
modified
• Table 24.4 Port P7 Peripheral Function Output Control Note 1 added to
PSC register; Bit 0 modified
• Table 24.6 Port P9 Peripheral Function Output Control Bit 2 and 6 modified
Flash Memory Version
• Table 25.1 Flash Memory Version Specifications Supply voltage modified
• 25.2.1 ROM Code Protect Function revised
• 25.2.2 ID Code Check Function revised
• 25.3.1.3 FMR02 Bit revised
• 25.3.3 Data Protect Function revised
• 25.3.5.3 Clear status Register revised
• 25.3.7.8 Rewriting the User ROM Area
• 25.4.2 ID Code Check Function revised
• 25.5.2 ROM Code Protect Function revised
C-10
REVISION HISTORY
Rev.
M32C/83 GROUP (M32C/83, M32C/83T) Hardware Manual
Description
Summary
Date
Page
413
414
416
416, 434
1.20
2004-6
1.31
2006-1
Electrical Characteristics
• Table 26.1 Absolute Maximum Ratings VREF, XIN P70 and P71 deleted and
XOUT added to Output Voltage
• Table 26.2 Recommended Operation Conditions (VCC= 3.0V to 5.5V at
Topr= -20 to 85°C) Maximum value of 50MHz added to f(XCIN) Sub Clock
Oscillation Frequency
• Table 26.4 A/D Conversion Characteristics φAD frequency modified
• Tables 26.6 Flash Memory Version Electrical Characteristics added
Precautions
450 to 472 • Overall structure modified
All pages Words standardized: On-chip oscillator, A/D converter and D/A converter
Interrupts
111
• Figure 10.15 IIO0IE to IIO11IE Registers Note 2 added
Watchdog Timer
112
• Figure 11.1 Watchdog Timer Block Diagram modified
Electrical Characteristics
432
• Figure 26.8 VCC=5V Timing Diagram (7) Figure modified
449
• Figure 26.16 VCC=3.3V Timing Diagram (7) Figure modified
All Pages
M32C/83T version added; Package code changed: 144P6Q-A to PLQP0144KAA, 100P6Q-A to PLQP0100KB-A, 100P6S-A to PRQP0100JB-A
All Pages Word standardized: Clock Generation Circuit , On-chip Oscillator, A/D Converter,
D/A Converter, XY Conversion, Low -power consumption
Overview
1
• 1.1 Applications Automobile added
2, 3
• Tables 1.1 and 1.2 M32C/83 Group (M32C/83, M32C/83T) Performance
5
• Table 1.3 M32C/83 Group (1) (M32C/83) Information updated
• Table 1.3 M32C/83 Group (2) (M32C/83T) M32C/83T product information
added
• Figure 1.2 Product Numbering System Classification modified
• Table 1.4 Pin Characteristics for 144-Pin Package Note 1 added
• Table 1.5 Pin Characteristics for 100-Pin Package Note 1 added
• Table 1.6 Pin Description modified, notes added
Memory
21
• Figure 3.1 Memory Map modified; Note 2 modified, notes 3 and 4 added
Special Function Registers (SFR)
22 to 23 • Note 2 added
Reset
45
• Figure 5.2 Reset Sequence Note 2 added
C-11
REVISION HISTORY
Rev.
M32C/83 GROUP (M32C/83, M32C/83T) Hardware Manual
Description
Summary
Date
Page
48
49
50
52
54
58
67
68
71
74
75
76
78
80
81
82
83
84-85
85
86
97
98
109
110
113
115
119
Processor Mode
• Chapter Note added
• Figure 6.1 PM0 Register Note 9 added
• Figure 6.2 PM1 Register Note 6 added
Bus
• Chapter note added
• Figure 7.1 DS Register Note 2 added
• Table 7.2 Processor Mode and Port Function Note 3 modified
• Table 7.3 WCR Register Note 3 added
Clock Generation Circuit
• Figure 8.2 CM0 Register Function of the CM07 bit modified
• Figure 8.3 CM1 Register Note mark position changed
• Figure 8.6 TCSPR and CPSRF Register Note 2 added for TCSPR register
• Figure 8.9 Main Clock Circuit Connection modified
• Figure 8.10 Sub Clock Connection Circuit modified
• 8.1.3.2 How to Use Oscillation Stop Detect Function partially modified
• Figure 8.12 External Circuit with PLL Frequency Synthesizer modified
• Table 8.5 BLCK/CLKOUT Pin in Memory Expansion Mode and
Microprocessor Mode Note 4 added
• 8.5.1 Normal Operation Mode Description partially modified
• 8.5.2 Wait Mode modified
• Table 8.6 Pin States in Wait Mode Note 2 added
• 8.5.3 Stop Mode modified
• Table 8.8 Pin Status in Stop Mode Note 2 added
• Figure 8.14 Status Transition in Wait Mode and Stop Mode The mode
between stop mode and low-speed mode, low-power consumption mode
changed; Note 2 deleted
Interrupts
• Figure 10.4 Interrupt Control Register (2) Note mark position changed
• Figure 10.5 RLVL Register Note 3 modified
• Figure 10.14 IIO0IR to IIO11IR Registers partially modified
• Figure 10.15 IIO0IE to IIO11IE Registers partially modified
Watchdog Timer
• Figure 11.3 CM0 Register Function of the CM07 bit modified
DMAC
• Table 12.1 DMAC Specifications Specification of DMA Transfer Cycles
partially modified
• Figure 12.4 DCT0 to DCT3 Registers Notes 3 and 4 modified; DRC0 to DRC3
Registers Notes 2 and 4 modified
C-12
REVISION HISTORY
Rev.
M32C/83 GROUP (M32C/83, M32C/83T) Hardware Manual
Description
Summary
Date
Page
120
126
140
139
141-156
173
175
176
177
191
192
204
221
225
242
250
274, 275
296
297
299
304
• Figure 12.5 DMA0 to DMA Registers Notes 3 and 4 modified; DSA0 to DSA3
Registers Notes 3 and 4 modified
DMACII
• Figure 13.1 RLVL Register Note 3 modified
• 13.4.2 Burst Transfer partially added
Timer
• Figure 14.7 TCSPR Register Note 2 added
• Table 14.4 Specification in Event Counter Mode (when not processing two phase pulse signal) to Table 14.7 Specifications in Pulse Width Modulation
Mode; Table 14.9 Specifiations in Timer Mode and Table 14.10
Specifications in Event Counter Mode Condition for “Write to Timer” modified
Serial I/O
• Figure 16.1 UARTi Block Diagram modified between transmit control circuit
________ ________
and CTSi/RTSi pins
• Figure 16.3 U0BRG to U4BRG Registers Note 3 added
• Figure 16.4 U0C0 to U4C0 Registers Note 4 added
• Figure 16.5 U0C1 to U4C1 Register and U0SMR to U4SMR Registers
RI bit revised
• Figure 16.14 Transmit Operation Timing modified
• 16.2.1 Bit Rate added
• Table 16.19 Special Mode 2 Specifications Transmit Start Condition modified;
Specification for Error Detection partially added
• Figure 16.29 SIM Interface Operation Timing modified
A/D Converter
• Table 17.1 A/D Converter Specifications Note 3 added
D/A Converter
• Figure 18.3 D/A Converter Equivalent Circuit modified
Intelligent I/O
• Figure 21.2 Intelligent I/O Group 1 Block Diagram modified
• Table 21.7 Pin Settings for Waveform Generation Function PSL3 register
added
• Table 21.16 Clock Synchronous Serial I/O Mode Specifications (Groups 0
and 1) Specification for interrupt request modified
• Table 21.19 Pin Settings (2) Bit and Setting modified for the PD8 register
• Table 21.22 UART Mode Specifications Specification for interrupt request
modified
• Table 21.28 HDLC Processing Mode Specifications Specification for interrupt
request modified
C-13
REVISION HISTORY
Rev.
M32C/83 GROUP (M32C/83, M32C/83T) Hardware Manual
Description
Summary
Date
Page
314
315
369
384
385
387
393
453-461
418
426
434
436
444
451
453-461
476
472
• Table 21.36 IEBus Mode Specifications Specification for interrupt request
modified
• Table 21.37 Registers to be Used and Settings Description for the IPOL bit in
the G2CR register is modified
Programmable I/O Ports
• Figure 24.2 Programmable I/O Ports (2) Figure modified
• Table 24.1 Unassigned Pin Settings in Single-chip Mode Notes 2, 3, 4, and 6
added
• Table 24.2 Unassigned Pin Settings in Memory Expansion Mode and
Microprocessor Mode Notes 2, 3, 4, and 6 added
• Figure 24.19 Unassigned Pin Handling Note 2 added
• Table 24.7 Port P10 Peripheral Function Output Control Title modified
Flash Memory Version
Figure 25.2 ROMCP Register Note 4 added
Electrical Characteristics
• 26.2 Electrical Characteristics (M32C/83T) Newly added
• Table 26.3 Electrical Characteristics Minimum standard values for V OH
revised, values for ICC when f(XIN)=32 MHz, square wave, no division revised,
one condition of “f(XIN)=32 MHz, square wave, no division” deleted
• Table 26.23 Memory Expansion Mode and Microprocessor Mode Symbols
for Row Address Output Delay Time and for Row Address Output Hold Time
(BCLK standard) modified
_______
• Figure 26.8 VCC=5 V Timing Diagram (7) Timing for NMI input added
• Table 26.24 Electrical Characteristics Minimum standard value for VOH
revised
• Table 26.44 Memory Expansion Mode and Microprocessor Mode Symbols
for Row Address Output Delay Time and for Row Address Output Hold Time
(BCLK standard) modified
_______
• Figure 26.8 VCC=3.3 V Timing Diagram (7) Timing for NMI input added
• 26.2 Electrical Characteristics (M32C/83T) Newly added
Precautions
• 27.4.3 Wait Mode modified
• 27.4.4 Stop Mode modified
27.8.2.3 Timer A (One-shot Timer Mode) Information (g) newly added
C-14
RENESAS 16/32-BIT SINGLE-CHIP MICROCOMPUTER
HARDWARE MANUAL
M32C/83 Group (M32C/83, M32C/83T)
Publication Data:
Published by:
Rev.1.01 Dec. 2002
Rev.1.31 Jan. 31, 2006
Sales Strategic Planning Div.
Renesas Technology Corp.
© 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
M32C/83 Group (M32C/83, M32C/83T)
Hardware Manual
2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan