1
2
3
4
5
6
A
A
B
B
C
C
Drawn By:
J Garcia
Engineer:
D
D
Dan Meacham
PartNumber:
Project Title
ADM00619
MCP37xxx 12-Bit ADC VTLA Eval Bd.
Designed with
Sheet Title
Block Diagram Circuit Schematic
Size
File:
1
2
3
4
5
B
Sch #:03-00619
Revision: 1
Date: 10/30/2014 10:30:29 AM
Sheet 1 of 6
1- ADM00619 Block Diagram.SchDot
6
Altium.com
1
2
3
4
Jin.0
SMA (angle)
A
3 UinA.0
R2n.0
0
4.99
1
Rin.0
49.9/DNI
2
CT
1
NC
5
5
6
WBC1-1TL_
NC
4
CT
2
3
WBC1-1TL_
VCM
C1.0
150pF/DNI
C2.0
3.3pF
Rin.4
49.9/DNI
3 UinA.1
1
R3p.0
49.9
R1p.0
R2p.0
0
4.99
R1n.1
R2n.1
0
4.99
1
1
5
6
WBC1-1TL_
NC
4
CT
3
WBC1-1TL_
VCM
Rin.5
49.9/DNI
SMA (angle)
3 UinA.2
6 Uin.2
4
R1n.2
R2n.2
0
4.99
2
CT
1
NC
5
5
6
WBC1-1TL_
NC
1
4
CT
3
WBC1-1TL_
VCM
IN2_N
3 UinA.3
1
NC
6
WBC1-1TL_
5
5
NC
1
4
CT
R1n.5
R2n.5
0
4.99
5
1
NC
4
0
2
3
WBC1-1TL_
VCM
C1.5
150pF/DNI
24.9
Cc.5
R3p.5
49.9
R1p.5
R2p.5
0
4.99
R1n.6
R2n.6
0
4.99
6 Uin.6
4
NC
5
5
1
NC
6
WBC1-1TL_
4
B
0
2
3
WBC1-1TL_
VCM
C1.6
150pF/DNI
Cc.6
R3p.6
49.9
IN2_P
4.99
R1n.3
R2n.3
IN3_N
R1n.7
R2n.7
0
4.99
0
4.99
SMA (angle)
R3n.3
49.9
Rin.7
49.9/DNI
2
CT
1
Cc.3
R3p.3
49.9
4.99
NC
5
5
1
NC
6
WBC1-1TL_
4
IN5_P
R3n.7
49.9
Rcn.7
6 Uin.7
4
24.9
Rc.7
C2.3
3.3pF
0.1uF
0
IN6_N
Jin.7
3 UinA.7
R2p.3
C2.6
3.3pF
0.1uF
24.9
R2p.6
R1p.3
IN6_P
R3n.6
49.9
24.9
CT
0
Rcp.3
IN1_N
Rcn.6
R1p.6
C1.3
150pF/DNI
C2.5
3.3pF
0.1uF
4.99
VCM
IN1_P
R3n.5
49.9
24.9
CT
R2p.2
0
IN4_N
Rcp.6
24.9
24.9
4.99
0
2
3
WBC1-1TL_
5
6
WBC1-1TL_
CT
1
Rcn.3
6 Uin.3
4
CT
R2p.4
0
R1p.2
Rc.3
2
2
R3p.2
49.9
Jin.3
Rin.3
49.9/DNI
R3p.4
49.9
R1p.4
Rc.6
Rin.6
49.9/DNI
Cc.2
SMA (angle)
C2.4
3.3pF
Cc.4
SMA (angle)
C2.2
3.3pF
Rcp.2
VCM
0.1uF
24.9
Jin.6
0.1uF
24.9
2
R3n.2
49.9
C1.2
150pF/DNI
A
Rcn.15
6 Uin.5
4
NC
3 UinA.6
0
CT
3
WBC1-1TL_
IN7_P
24.9
2
4
C1.4
150pF/DNI
Rcp.5
Rcn.2
Rc.2
Rin.2
49.9/DNI
CT
R3p.1
49.9
Jin.2
B
2
Cc.1
4.99
NC
0
Rc.5
C2.1
3.3pF
Rcp.1
0
5
SMA (angle)
1
R2p.1
5
IN4_P
R3n.4
49.9
Jin.5
IN7_N
C1.1
150pF/DNI
R1p.1
4.99
24.9
R3n.1
49.9
0.1uF
24.9
NC
6
WBC1-1TL_
3 UinA.5
0
2
R2n.4
0
Rcp.4
24.9
Rc.1
5
1
IN0_P
Rcn.1
6 Uin.1
4
NC
CT
Cc.0
SMA (angle)
CT
2
0.1uF
24.9
6 Uin.4
4
R1n.4
Rcn.4
Rc.4
Jin.1
2
SMA (angle)
3 UinA.4
0
Rcp.0
Rin.1
49.9/DNI
Jin.4
IN0_N
24.9
Rc.0
6
R3n.0
49.9
Rcn.0
6 Uin.0
4
R1n.0
5
CT
0
2
3
WBC1-1TL_
VCM
C1.7
150pF/DNI
C2.7
3.3pF
0.1uF
24.9
Cc.7
R3p.7
49.9
Rcp.7
IN3_P
R1p.7
R2p.7
0
4.99
IN5_N
C
C
R136
R39
CK_N
0
PLACE XO FOOTPRINTS OVER EACH OTHER ON PCB LAYOUT
3.3VA
0/DNI
3.3VA
C173
5.6nF
3
4
VCC
N/C
OUT_P
GND
OUT_N
200.000 MHz/DNI
6
4
5
XO_P
XO_N
1
NC
R40
49.9
100.000 MHz/DNI
GND VDD
2
EN
OUT
3
1
R42
C32
1.2VA
D5
1k/DNI
HSMS-2812-TR1G
5
R89
49.9
NC
4
XO_P
CT
3
WBC1-1TL_
XO_P
2
1
6 U10
R90
49.9
Y1
Y2
D
R41
24.9/DNI
3
XO_N
R36
D
0.1uF
2
C31
R44
24.9/DNI
Drawn By:
R45
5.6nF
1k/DNI
J Garcia
2
3.3VA
C105
150pF/DNI
1
NOTE:
Engineer:
Dan Meacham
C106
150pF/DNI
R49
CK_P
0
0/DNI
J10
SMA
PartNumber:
Project Title
ADM00619
MCP37xxx 12-Bit ADC VTLA Eval Bd.
Designed with
Sheet Title
Input and Clock Net Circuit Schematic
Size
File:
1
2
3
4
5
C
Sch #:03-00619
Revision: 1
Date: 10/30/2014 10:30:29 AM
Sheet 2 of 6
2 - INPUT AND CLOCK NET.SchDoc
6
Altium.com
1
2
3
4
5
NOTE: PLACE ALL DECOUPLING CAPS CLOSE TO CHIP. PLACE
{150pF 1nF} PAIRS NEAR EACH PIN. PLACE EACH {5.6nF 10uF
100uF} PAIR NEAR VOLTAGE BANK.
SENSE_MON
1.2VA
1.2VD
6
VBG_MON
1.8VA
1.8VD
1.2VD
R47
49.9
1.2VA
1.2VM
R48
1k/DNI
R38
0
R115
10k
C46
1uF
VCM
C48
2.2uF
1.8VPLL
C58
5.6nF
5.6nF
1.8VA
B
C89
C90
C91
C92
C93
150pF
0.1uF
1uF
1nF
5.6nF
1.2VA
C70
C79
C84
C83
C72
1nF
150pF
0.1uF
1uF
5.6nF
VBG
SENSE
VCM
IN1_P
IN1_N
INP1
INN1
IN2_P
IN2_N
INP2
INN2
IN3_P
IN3_N
INP3
INN3
IN4_P
IN4_N
INP4
INN4
IN5_P
IN5_N
INP5
INN5
WCK
OVR
WCK_N
WCK_P
IN6_P
IN6_N
INP6
INN6
CSB
SCLK
SDIO
CSB
SCLK
SDIO
IN7_P
IN7_N
INP7
INN7
RESB
RES_B
REFP0
C57
0.1uF
REFN0
C54
1uF
REFP1
C53
1nF
CAL
C52
150pF
CKINN
CKINP
C51
1nF
REFN1
INP0
INN0
INN_C
INP_C
C50
U8
WCAA0_VTLA124
IN0_P
IN0_N
VCM
24.9
150pF
A
VBG
DCKON
DCKOP
DM2
DM1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
Rcm
VCM
1.8VD
C49
SENSE
d/c
d/c
d/c
d/c
5.6nF
AVDD12M
C43
5.6nF
AVDD12
C42
1uF
AVDD12C
C39
0.1uF
AVDD18
C38
1nF
TESTMODE
CHIPID0
SLAVE
SYNC
VDDQ
C37
150pF
DVDD12
C36
1nF
AVDD18P
C35
150pF
DVDD18
C34
PADDLE
A
DCK_N
DCK_P
DM1_N
DM1_P
D0_N
D0_P
D1_N
D1_P
D2_N
D2_P
D3_N
D3_P
D4_N
D4_P
D5_N
D5_P
D6_N
D6_P
D7_N
D7_P
B
1
1
TP3
TEST POINT
D1
C62
C69
C80
C85
C73
150pF
1nF
0.1uF
1uF
5.6nF
4.7uF
C98
22nF/DNI
LED
C61
C99
TP1
C165
22nF/DNI
C166
22nF
22nF
C164
C160
220nF
220nF
C163
C161
REF0_P
C
R116
49.9
TP12
REF0_N
1
REF1_N
1.2VM
REF1_P
CK_N
CK_P
C
R2
330
1.8VPLL
1
TP4
2.2uF
TEST POINT
C100
C101
150pF
1nF
R118
10k
J5
VCM
R119
VCM_MON
10k
D
2.2uF
R121
10k
C111
C112
C114
150pF
1nF
5.6nF
VBG_MON
2
4
6
8
10
12
1
3
5
7
9
11
C107
220nF/DNI
C110
220nF
R120
C108 10k
220nF/DNI
C109
220nF
R117
10k
REF0N_MON
SENSE_MON
VCM_MON
REF1P_MON
REF1N_MON
REF0P_MON
REF0N_MON
REF1P_MON
REF1N_MON
REF0P_MON
Drawn By:
J Garcia
Engineer:
D
Dan Meacham
HEADER 6x2
PartNumber:
Project Title
ADM00619
MCP37xxx 12-Bit ADC VTLA Eval Bd.
Designed with
Sheet Title
WCAAO_VTLA24 Circuit Schematic
Size
File:
1
2
3
4
5
B
Sch #:03-00619
Revision: 1
Date: 10/30/2014 10:30:29 AM
Sheet 3 of 6
3 - WCAA0_VTLA124.SchDoc
6
Altium.com
1
2
3
4
TP19
1
CON_SDI_1V8
TP21
1
I2C_SDA
TEST POINT
R96
R51
C168
1k
1k
220nF/DNI
DCK_N
DCK_P
U20
R97
TP20
1
A1
6
Y1
D6_N
D6_P
10k
1
2
I2C_SCL
TEST POINT
3
GND
5
VCC
A2
4
Y2
D4_N
D4_P
R52
1k
TP14
NC7WZ07P6X
1
D2_N
D2_P
CON_SDO_3V3
TEST POINT
3.3VD
SDIO
U1
TP15
1
A0
A1
A2
VSS
CON_SDI_3V3
TEST POINT
TP16
VCC
WP
SCL
SDA
1.8VD
I2C_SCL
I2C_SDA
24LC128
1
R109
10k
CON_CSB_3V3
TEST POINT
C167
U21
CON_SCLK_1V8
TP17
1
2
1
R111
10k
CON_SCLK_3V3
CON_CSB_1V8
TEST POINT
B
D0_N
D0_P
CON_SDO_1V8
R98
10k
3.3VD
6
Y1
GND
R102
10k
5
VCC
A2
SCLK
4
Y2
CSB
A1
C1
B1
D1
BG1 DG1
A2
C2
B2
D2
BG2 DG2
A3
C3
B3
D3
BG3 DG3
A4
C4
B4
D4
BG4 DG4
A5
C5
B5
D5
BG5 DG5
A6
C6
B6
D6
BG6 DG6
A7
C7
B7
D7
BG7 DG7
A8
C8
B8
D8
BG8 DG8
A9
C9
B9
D9
BG9 DG9
A10
C10
B10
D10
BG10 DG10
D7_N
D7_P
D5_N
D5_P
A
D3_N
D3_P
D1_N
D1_P
DM1_N
DM1_P
WCK_N
WCK_P
B
TYCO60
NC7WZ07P6X
R99
10k
TP18
3
220nF/DNI
A1
6
J13
RES_B
TEST POINT
A
5
1.8VD
1
TEST POINT
3.3VD
J15
1.8VD
C169
3.3VD
VCCB
CON_SDO_3V3
OE_B
C183
220nF/DNI
CON_CSB_3V3
R59
10k
CON_SCLK_3V3
10
1
2
R122
7
SN74AVC2T245
3
RES_B
1
1k
C116
SW1
R112
10k/DNI
1nF
RSTB_1V8
8
9
U11
DIR1
DIR2
A1
A2
7
5
4
220nF
CON_CSB_3V3
CON_SCLK_3V3
5
4
B1
B2
RSTB_3V3
R104
0
2
OE_B
SN74AVC2T245
5VIN_CC
2
1.8VD
3.3VD
C171
3.3VD
I2C_SCL
R29
10k
I2C_SDA
C
R103
CON_CSB_3V3
0
CON_SDI_1V8
CON_SDO_1V8
8
9
A1
A2
7
C172
220nF
VCCB
DIR1
DIR2
VCCA
10
1
GND
U23
6
TYCO60
220nF/DNI
D
CON_SDI_3V3
R123
10k
VCCB
B1
B2
6
C182
VCCA
A1
A2
VCCA
8
9
1.8VD
3.3VD
220nF
GND
CON_SCLK_1V8
C170
3
CON_CSB_1V8
C
DIR1
DIR2
GND
U22
10
1
6
220nF/DNI
R28
10k
A1
C1
B1
D1
BG1 DG1
A2
C2
B2
D2
BG2 DG2
A3
C3
B3
D3
BG3 DG3
A4
C4
B4
D4
BG4 DG4
A5
C5
B5
D5
BG5 DG5
A6
C6
B6
D6
BG6 DG6
A7
C7
B7
D7
BG7 DG7
A8
C8
B8
D8
BG8 DG8
A9
C9
B9
D9
BG9 DG9
A10
C10
B10
D10
BG10 DG10
Drawn By:
J Garcia
B1
B2
OE_B
5
4
CON_SDI_3V3
Engineer:
CON_SDO_3V3
D
Dan Meacham
2
SN74AVC2T245
PartNumber:
Project Title
ADM00619
MCP37xxx 12-Bit ADC VTLA Eval Bd.
Designed with
3
Sheet Title
Connectors Circuit Schematic
Size
File:
1
2
3
4
5
B
Sch #:03-00619
Revision: 1
Date: 10/30/2014 10:30:29 AM
Sheet 4 of 6
4 - CONNECTORS.SchDoc
6
Altium.com
1
2
3
4
5
6
3.3VA
FB6
BEAD FERRITE
A
A
U6
Vin+
C30
4.7uF
VDD
SDA
SCL
VSS
I2C_SDA
I2C_SCL
1.2VA
1.2VM
R37
1
FB2
U5
VIN-
Vin
Vin
MCP3421-1
OUT
R65
3
40k
TRIMPOT_200k/DNI
C29
0.1uF
C124
10uF
C126
100uF/DNI
BEAD FERRITE
2
SHDN#
GND
1500mA
MCP1727
U30
SHDN_1.2VA
C121
4.7uF
1
ADJ
Cdelay
PWRGD
C127
100uF/DNI
C125
3.3uF/DNI
R67
20K
3.3VA
B
B
FB8
BEAD FERRITE
U13
1.8VPLL
Vin+
C40
4.7uF
VDD
SDA
SCL
VSS
I2C_SDA
I2C_SCL
1.8VA
R46
1
FB5
U12
VIN-
Vin
Vin
MCP3421-0
OUT
3
R63
69.8K
3.3VA
1
F1
SMD 1812
0ZCG0075AF2B
FB13
U14
Vin
Vin
BEAD FERRITE
SHDN_1.8VA
C117
4.7uF
OUT
1500mA
MCP1727
R72
C135
10uF
147k
C
6V
D2
SMBJ5340B-TP
SHDN#
GND
C131
4.7uF
1500mA
MCP1727
SHDN#
GND
ADJ
Cdelay
PWRGD
BEAD FERRITE
C118
3.3uF/DNI
2
U26
5VIN
TRIMPOT_200k/DNI
C41
0.1uF
C123
10uF
C120
100uF/DNI
C119
100uF/DNI
R66
20K
C137
100uF/DNI
C
ADJ
Cdelay
PWRGD
C136
3.3uF/DNI
R74
C138
100uF/DNI
20K
3.3VA
R27
10K
R34
10K
R31
10K
R61
10K
SW2
SHDN_1.2VA
SHDN_1.2VD
D
SHDN_1.8VD
SHDN_1.8VA
1
1
2
3
4
Drawn By:
0
5
6
7
8
J Garcia
J16
1
3
5
7
9
11
1.2VA
1.8VA
3.3VA
1.8VD
1.2VD
2
4
6
8
10
12
HEADER 6x2
Engineer:
PartNumber:
Project Title
ADM00619
MCP37xxx 12-Bit ADC VTLA Eval Bd.
2
3
4
Designed with
Sheet Title
Analog Regulators Circuit Schematic
Size
File:
1
D
Dan Meacham
5
B
Sch #:03-00619
Revision: 1
Date: 10/30/2014 10:30:29 AM
Sheet 5 of 6
5 - ANALOG REGULATORS.SchDoc
6
Altium.com
1
2
3
4
5
M1
M2
MOUNTHOLE/DNI
MOUNTHOLE/DNI
6
A
A
5VIN_PJ
5VIN_CC
J17
Power Jack
3.3VD
U16
4
1
3
2
Vin
Vin
OUT
R76
C142
10uF
147k
C141
4.7uF
ADJ
Cdelay
PWRGD
SHDN#
GND
1500mA
MCP1727
M3
M4
M5
MOUNTHOLE/DNI
MOUNTHOLE/DNI
MOUNTHOLE/DNI
C143
3.3uF/DNI
R77
20k
3.3VA
NOTE: PCB MAY BE POWERED FROM EXTERNAL
POWER JACK OR CAPTURE CARD INTERFACE
FB9
BEAD FERRITE
5VIN_PJ
B
FB4
5VIN
FB3
5VIN_CC
B
U18
Vin+
C44
4.7uF
I2C_SDA
I2C_SCL
VDD
SDA
SCL
VSS
1.8VD
BEAD FERRITE
R60
1
BEAD FERRITE/DNI
D3
D4
LED
LED
U17
VIN-
Vin
Vin
MCP3421-2
OUT
R84
TRIMPOT_200k/DNI
C63
0.1uF
3
69.8k
SHDN_1.8VD
C147
4.7uF
SHDN#
GND
1500mA
MCP1727
U29
2
1
ADJ
Cdelay
PWRGD
C148
10uF
C149
3.3uF/DNI
R86
R81
330
C150
100uF/DNI
R82
330
C151
100uF/DNI
20k
3.3VA
C
1.8VD
1.8VA
C
FB11
FB7
BEAD FERRITE
FB1
BEAD FERRITE/DNI
U25
Vin+
C45
4.7uF
I2C_SDA
I2C_SCL
VDD
SDA
SCL
VSS
BEAD FERRITE
R43
1
1.2VD
1.2VD
1.2VA
U19
VIN-
FB10
Vin
Vin
MCP3421-3
OUT
R923
40k
TRIMPOT_200k/DNI
C33
0.1uF
C155
10uF
C157
100uF/DNI
BEAD FERRITE/DNI
SHDN_1.2VD
C153
4.7uF
SHDN#
GND
1500mA
MCP1727
D
1
ADJ
Cdelay
PWRGD
U28
2
C156
3.3uF/DNI
C76
R93
2.2uF
20K
C158
100uF/DNI
Drawn By:
J Garcia
Engineer:
D
Dan Meacham
PartNumber:
Project Title
ADM00619
MCP37xxx 12-Bit ADC VTLA Eval Bd.
Designed with
Sheet Title
Digital Regulators Circuit Schematic
Size
File:
1
2
3
4
5
B
Sch #:03-00619
Revision: 1
Date: 10/30/2014 10:30:30 AM
Sheet 6 of 6
6 - DIGITAL REGULATORS.SchDoc
6
Altium.com