LTC2000 16-/14-/11-Bit 2.5Gsps DACs Features Description 80dBc SFDR at 70MHz fOUT n>68dBc SFDR from DC to 1000MHz f OUT n40mA Nominal Full-Scale, ±1V Output Compliant n10mA to 60mA Adjustable Full-Scale Current Range n Single or Dual Port DDR LVDS and DHSTL Interface n Low Latency (7.5 Cycles for Single Port, 11 Cycles for Dual Port) n>78dBc 2-Tone IMD from DC to 1000MHz f OUT n–165dBc/Hz Additive Phase Noise at 1MHz Offset for 65MHz fOUT n170-Lead (9mm × 15mm) BGA Package The LTC®2000 is a family of 16-/14-/11-bit 2.5Gsps current steering DACs with exceptional spectral purity. Applications A serial peripheral interface (SPI) port allows configuration and read back of internal registers. Operating from 1.8V and 3.3V supplies, the LTC2000 consumes 2.2W at 2.5Gsps and 1.3W at 1.25Gsps. n n n n n n n The single (1.25Gsps mode) or dual (2.5Gsps mode) port source synchronous LVDS interface supports data rates of up to 1.25Gbps using a 625MHz DDR data clock, which can be either in quadrature or in phase with the data. An internal synchronizer automatically aligns the data with the DAC sample clock. Additional features such as pattern generation, LVDS loopout and junction temperature sensing simplify system development and testing. Broadband Communication Systems DOCSIS CMTS Direct RF Synthesis Radar Instrumentation Automatic Test Equipment L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 8330633. Block Diagram TSTP/N PD JUNCTION TEMPERATURE PATTERN GENERATOR CS SCK SDI SVDD SDO SPI SFDR vs fOUT, fDAC = 2.5Gsps 100 DAP/N[15:0] DDR DATA FLIP-FLOPS 16-BIT DAC 4:1 50Ω IOUTN GAIN ADJUST DCKIP/N CLK DIVIDER ÷2 OR ÷4 AVDD18 DVDD18 FSADJ CLK RECEIVER AVDD33 90 DVDD33 GND CKP/N 80 70 60 CLOCK SYNC DELAY ADJUST DCKOP/N DIGITAL AMPLITUDE = 0dBFS IOUTFS = 40mA 50Ω SFDR (dBc) LVDS RECEIVERS DBP/N[15:0] IOUTP REFIO 10k 50 0 200 400 600 800 fOUT (MHz) 1000 1200 2000 TA01b REF 2000 BD 2000f For more information www.linear.com/LTC2000 1 LTC2000 Table of Contents Features...................................................... 1 Applications................................................. 1 Block Diagram............................................... 1 Description.................................................. 1 Absolute Maximum Ratings............................... 3 Pin Configuration........................................... 3 Order Information........................................... 4 Electrical Characteristics.................................. 5 Timing Characteristics..................................... 8 Typical Performance Characteristics.................... 9 Pin Functions............................................... 16 Block Diagram.............................................. 17 Timing Diagrams.......................................... 18 Operation................................................... 18 Introduction............................................................. 18 Dual-Port Mode....................................................... 19 Single-Port Mode..................................................... 19 Serial Peripheral Interface (SPI)..............................22 Power-On Reset.......................................................22 Power Down............................................................22 Reference Operation................................................22 Setting the Full-Scale Current..................................23 DAC Transfer Function............................................. 24 Analog Outputs (IOUTP/N)......................................... 24 DAC Sample Clock (CKP/N).....................................25 Divided Clock Output (DCKOP/N).............................25 LVDS Data Clock Input (DCKIP/N)...........................25 LVDS Data Input Ports (DAP/N, DBP/N)..................26 Clock Synchronizer.................................................. 27 Minimizing Harmonic Distortion..............................29 Measuring LVDS Input Timing Skew........................29 Measuring Internal Junction Temperature (TJ)........ 32 Pattern Generator.................................................... 32 2 SPI Register Summary.................................... 33 Applications Information................................. 34 Sample Start-Up Sequence......................................34 Output Configurations ............................................35 Generating the DAC Sample Clock...........................35 Synchronizing Multiple LTC2000s in Dual-Port Mode.......................................................................36 Synchronizing Multiple LTC2000s in Single-Port Mode.......................................................................38 PCB Layout Considerations.....................................40 Pin Locations (LTC2000-16).............................. 45 PIn Locations (LTC2000-14).............................. 47 Pin Locations (LTC2000-11).............................. 49 Package Description...................................... 51 Typical Application........................................ 52 Related Parts............................................... 52 2000f For more information www.linear.com/LTC2000 LTC2000 Absolute Maximum Ratings (Notes 1, 2) AVDD33, DVDD33, SVDD.................................. –0.3V to 4V AVDD18, DVDD18............................................ –0.3V to 2V IOUTP, IOUTN..................–1.2V to Min (AVDD33 + 0.3V, 4V) FSADJ, REFIO............. –0.3V to Min (AVDD33 + 0.3V, 4V) DCKIP, DCKIN.............–0.3V to Min (DVDD33 + 0.3V, 4V) DCKOP, DCKON...........–0.3V to Min (DVDD33 + 0.3V, 4V) DAP/N, DBP/N.............–0.3V to Min (DVDD33 + 0.3V, 4V) TSTP, TSTN................. –0.3V to Min (AVDD33 + 0.3V, 4V) CKP, CKN.................... –0.3V to Min (AVDD18 + 0.3V, 2V) CS, PD, SCK, SDI, SDO....–0.3V to Min (SVDD + 0.3V, 4V) Operating Temperature Range LTC2000C................................................. 0°C to 70°C LTC2000I..............................................–40°C to 85°C Maximum Junction Temperature........................... 125°C Storage Temperature Range................... –55°C to 125°C Lead Temperature (Soldering, 10 sec).................... 260°C Pin Configuration LTC2000-16 1 2 A 3 TOP VIEW 4 5 6 7 LTC2000-14 8 9 1 10 A GND B 2 C AVDD18 D DVDD18 E LTC2000-11 8 9 10 1 C AVDD18 D DVDD18 F G G H H H J J L L M M N N N P P R S AVDD33 R GND DVDD33 Q GND S 10 GND K M DVDD33 9 DVDD18 J GND L Q 8 E F AVDD33 TOP VIEW 5 6 7 C G K 4 D F K 3 GND B E GND 2 A GND B AVDD18 3 TOP VIEW 4 5 6 7 AVDD33 P DVDD33 Q R S GND BGA PACKAGE 170-LEAD (9mm × 15mm × 1.54mm) BGA PACKAGE 170-LEAD (9mm × 15mm × 1.54mm) BGA PACKAGE 170-LEAD (9mm × 15mm × 1.54mm) TJMAX = 125°C, θJA = 20°C/W, θJB = 8°C/W, θJCtop = 9°C/W, θJCbottom = 3°C/W TJMAX = 125°C, θJA = 20°C/W, θJB = 8°C/W, θJCtop = 9°C/W, θJCbottom = 3°C/W TJMAX = 125°C, θJA = 20°C/W, θJB = 8°C/W, θJCtop = 9°C/W, θJCbottom = 3°C/W 2000f For more information www.linear.com/LTC2000 3 LTC2000 Order Information LTC2000 C Y –16 #PBF LEAD FREE DESIGNATOR PBF = Lead Free RESOLUTION 16 = 16-Bit Resolution 14 = 14-Bit Resolution 11 = 11-Bit Resolution PACKAGE TYPE 170-Lead (15mm × 9mm × 1.54mm) BGA TEMPERATURE GRADE C = Commercial Temperature Range (0°C to 70°C) I = Industrial Temperature Range (–40°C to 85°C) PRODUCT PART NUMBER PART NUMBER BALL FINISH PART MARKING* PACKAGE TYPE MSL RATING LTC2000CY-16#PBF SAC305 (RoHS) LTC2000CY-14#PBF SAC305 (RoHS) LTC2000CY-11#PBF LTC2000IY-16#PBF TEMPERATURE RANGE LTC2000Y-16 BGA 3 0°C to 70°C LTC2000Y-14 BGA 3 0°C to 70°C SAC305 (RoHS) LTC2000Y-11 BGA 3 0°C to 70°C SAC305 (RoHS) LTC2000Y-16 BGA 3 –40°C to 85°C LTC2000IY-14#PBF SAC305 (RoHS) LTC2000Y-14 BGA 3 –40°C to 85°C LTC2000IY-11#PBF SAC305 (RoHS) LTC2000Y-11 BGA 3 –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear.com/packaging/ 4 2000f For more information www.linear.com/LTC2000 LTC2000 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AVDD18, DVDD18 = 1.71V to 1.89V, AVDD33, DVDD33 = 3.135V to 3.465V, SVDD = 1.71V to 3.465V, RFSADJ = 500Ω, 12.5Ω load from IOUTP/N to GND including internal 50Ω termination, unless otherwise specified. SYMBOL PARAMETER DC Performance Resolution DNL INL Differential Nonlinearity Integral Nonlinearity Offset Error Offset Error Drift Gain Error Gain Error Drift Power Supply Rejection Ratio Analog Output Full-Scale Output Current Output Compliance Range Output Resistance Output Capacitance Output Bandwidth AC Performance Maximum Update Rate SFDR Spurious Free Dynamic Range fDAC = 1.25Gsps, 0dBFS Spurious Free Dynamic Range fDAC = 2.5Gsps, 0dBFS IMD 2-Tone Intermodulation Distortion fOUT2 = fOUT1 + 1.25MHz fDAC = 1.25Gsps, –6dBFS 2-Tone Intermodulation Distortion fOUT2 = fOUT1 + 1.25MHz fDAC = 2.5Gsps, –6dBFS CONDITIONS LTC2000-16 LTC2000-14 LTC2000-11 LTC2000-16 LTC2000-14 LTC2000-11 LTC2000-16 LTC2000-14 LTC2000-11 LTC2000-16 LTC2000-14 LTC2000-11 MIN l l l MAX 16 14 11 ±0.5 ±0.2 ±0.1 ±1 ±0.5 ±0.2 l l l l l l l l l ±2.7 ±1 ±0.5 ±4 ±2 ±1 ±0.05 ±0.06 ±0.09 1 ±0.5 5 69 Full-Scale; AVDD33 = 3.135V to 3.465V RFSADJ = 500Ω 40 l IOUTP/N to GND TYP l –1 42 RIOUTP/N = 12.5Ω, –3dB Excluding sin(x)/x l Dual-Port Mode l Single-Port Mode fOUT = 50MHz, LIN_DIS = 0, LIN_GN = 75% fOUT = 100MHz, LIN_DIS = 0, LIN_GN = 75% fOUT = 250MHz, LIN_DIS = 0, LIN_GN = 75% fOUT = 500MHz, LIN_DIS = 0, LIN_GN = 75% fOUT = 100MHz, LIN_DIS = 0, LIN_GN = 75% fOUT = 200MHz, LIN_DIS = 0, LIN_GN = 75% l fOUT = 500MHz, LIN_DIS = 0, LIN_GN = 75% fOUT = 1000MHz, LIN_DIS = 0, LIN_GN = 75% fOUT = 500MHz, LIN_DIS = 1 fOUT = 1000MHz, LIN_DIS = 1 fOUT = 50MHz, LIN_DIS = 0, LIN_GN = 75% fOUT = 100MHz, LIN_DIS = 0, LIN_GN = 75% fOUT = 250MHz, LIN_DIS = 0, LIN_GN = 75% fOUT = 500MHz, LIN_DIS = 0, LIN_GN = 75% fOUT = 100MHz, LIN_DIS = 1 fOUT = 200MHz, LIN_DIS = 1 fOUT = 500MHz, LIN_DIS = 1 fOUT = 1000MHz, LIN_DIS = 1 fOUT = 500MHz, LIN_DIS = 0, LIN_GN = 75% fOUT = 1000MHz, LIN_DIS = 0, LIN_GN = 75% 50 6 2.1 2.5 1.25 67 82 82 74 74 76 74 72 68 66 62 100 90 90 82 87 86 84 78 80 67 1 58 UNITS Bits Bits Bits LSB LSB LSB LSB LSB LSB % FSR % FSR % FSR ppm/°C % FSR ppm/°C dB mA V Ω pF GHz Gsps Gsps dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc 2000f For more information www.linear.com/LTC2000 5 LTC2000 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AVDD18, DVDD18 = 1.71V to 1.89V, AVDD33, DVDD33 = 3.135V to 3.465V, SVDD = 1.71V to 3.465V, RFSADJ = 500Ω, 12.5Ω load from IOUTP/N to GND including internal 50Ω termination, unless otherwise specified. SYMBOL NSD WCDMA ACLR Latency PARAMETER Noise Spectral Density 0dBFS Single Tone, fDAC = 2.5Gsps, IOUTFS = 40mA Phase Noise fDAC = 2.5Gsps, fOUT = 65MHz 0dBFS Single Tone, IOUTFS = 40mA WCDMA ACLR (Single Carrier) Adjacent/Alternate Adjacent Channel Latency (Note 5) Aperature Delay Settling Time CONDITIONS LTC2000-16, fOUT = 100MHz LTC2000-16, fOUT = 350MHz LTC2000-16, fOUT = 550MHz LTC2000-16, fOUT = 950MHz LTC2000-14, fOUT = 100MHz LTC2000-14, fOUT = 350MHz LTC2000-14, fOUT = 550MHz LTC2000-14, fOUT = 950MHz LTC2000-11, fOUT = 100MHz LTC2000-11, fOUT = 350MHz LTC2000-11, fOUT = 550MHz LTC2000-11, fOUT = 950MHz 10kHz Offset 1MHz Offset MIN fDAC = 2.5Gsps, fOUT = 350MHz fDAC = 2.5Gsps, fOUT = 950MHz TYP –166 –161 –158 –156 –164 –160 –158 –155 –156 –155 –154 –153 –147 –165 MAX 77/79 72/75 Single-Port Mode Dual-Port Mode, DAP/N Data Dual-Port Mode, DBP/N Data CKP/N Rising to IOUTP/N Transition UNITS dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBc/Hz dBc/Hz dBc dBc 7.5 10 11 3 2.2 Cycles Cycles Cycles ns ns Reference Output Voltage Input Voltage Reference Temperature Coefficient Output Impedance DAC Clock Inputs (CKP, CKN) Differential Input Voltage Range Common-Mode Input Voltage Sampling Clock Frequency Input Impedance LVDS Inputs (DCKIP, DCKIN, DAP/N, DBP/N) Differential Input Voltage Range Common-Mode Voltage Range Differential Input Impedance Maximum Data Rate LVDS Clock Frequency 6 l l 1.225 1.1 1.25 1.275 1.4 V V ppm/°C kΩ ±1.8 V V MHz kΩ ±25 10 l ±0.3 Set Internally 1 l 50 2500 5 l l l ±0.2 0.4 95 l l 25 120 ±0.6 1.8 145 1250 625 V V Ω Mbps MHz 2000f For more information www.linear.com/LTC2000 LTC2000 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AVDD18, DVDD18 = 1.71V to 1.89V, AVDD33, DVDD33 = 3.135V to 3.465V, SVDD = 1.71V to 3.465V, RFSADJ = 500Ω, 12.5Ω load from IOUTP/N to GND including internal 50Ω termination, unless otherwise specified. SYMBOL PARAMETER LVDS Output (DCKOP, DCKON) Differential Output Voltage Common-Mode Output Voltage Internal Termination Resistance CMOS Digital Inputs (CS, PD, SCK, SDI) Digital Input High Voltage VIH VIL Digital Input Low Voltage ILK Digital Input Leakage Digital Input Capacitance CIN CMOS Digital Output (SDO) Digital Output High Voltage VOH VOL Digital Output Low Voltage Hi-Z Output Leakage Hi-Z Output Capacitance Power Supply AVDD33, DVDD33 Supply Voltage VVDD33 AVDD18, DVDD18 Supply Voltage VVDD18 SVDD SPI Supply Voltage VSVDD AVDD33 Supply Current, AVDD33 = 3.3V IAVDD33 IDVDD33 DVDD33 Supply Current, DVDD33 = 3.3V IAVDD18 AVDD18 Supply Current, AVDD18 = 1.8V IDVDD18 DVDD18 Supply Current, DVDD18 = 1.8V ISVDD SVDD Supply Current (Note 4), SVDD = 3.3V Total Power Dissipation CONDITIONS 100Ω Differential Load, DCKO_ISEL = 0 50Ω Differential Load, DCKO_ISEL = 1 MIN TYP MAX UNITS l 0.24 0.24 1.075 0.36 0.36 1.2 100 0.48 0.48 1.325 V V V Ω l 70 l l DCKO_TRM = 1 l VIN = GND or SVDD l 30 ±10 %VSVDD %VSVDD µA pF 15 ±10 %VSVDD %VSVDD µA pF 8 ISOURCE = 0.2mA ISINK = 1.6mA l 85 l l 8 l l l PD = SVDD PD = GND PD = SVDD PD = GND fDAC = 2500MHz fDAC = 1250MHz fDAC = 0Hz, PD = SVDD fDAC = 0Hz, PD = GND fDAC = 2500MHz fDAC = 1250MHz fDAC = 0Hz, PD = SVDD fDAC = 0Hz, PD = GND fSCK = 0Hz fDAC = 2500MHz fDAC = 1250MHz fDAC = 0Hz, PD = SVDD fDAC = 0Hz, PD = GND l l l l l l l l l l l l l 3.135 1.71 1.71 3.3 1.8 68 0.1 8 0.1 720 375 23 3 350 190 10 0.1 0.1 2180 1270 310 6 3.465 1.89 3.465 72 10 12 5 790 420 27 180 395 215 14 240 5 V V V mA µA mA µA mA mA mA µA mA mA mA µA µA mW mW mW µW 2000f For more information www.linear.com/LTC2000 7 LTC2000 Timing Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AVDD18, DVDD18 = 1.71V to 1.89V, AVDD33, DVDD33 = 3.135V to 3.465V, SVDD = 1.71V to 3.465V, RFSADJ = 500Ω, output load 50Ω double terminated, unless otherwise specified. SYMBOL t1 t2 t3 t4 t5 t6 t7 t10 t13 t11 t12 PARAMETER SDI Valid to SCK Setup SDI Valid to SCK Hold SCK High Time SCK Low Time CS Pulse Width SCK High to CS High CS Low to SCK High CS High to SCK High SCK Low to SDO Valid SCK Frequency LVDS DAP/N, DBP/N to DCKI Setup Time (Note 3) LVDS DAP/N, DBP/N to DCKI Hold Time (Note 3) CONDITIONS (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) Unloaded (Note 3) 50% Duty Cycle (Note 3) DCKI_Q = 1 DCKI_Q = 0, DCKI_TADJ = 000 DCKI_Q = 1 DCKI_Q = 0, DCKI_TADJ = 000 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltages are with respect to GND. 8 l l l l l l l l l MIN 4 4 9 9 10 7 7 7 10 l l MAX 50 l l l TYP 200 600 200 –200 UNITS ns ns ns ns ns ns ns ns ns MHz ps ps ps ps Note 3: Guaranteed by design and not production tested. Note 4: Digital inputs at 0V or SVDD. Note 5: Latency is the delay from a transition on DCKIP/N until the CKP/N transition which causes the sample on DAP/N or DBP/N to appear at the DAC output IOUTP/N, as measured in DAC sample clock (CKP/N) cycles. 2000f For more information www.linear.com/LTC2000 LTC2000 Typical Performance Characteristics IOUTFS = 40mA, TA = 25°C, AVDD18 = DVDD18 = 1.8V, AVDD33 = DVDD33 = 3.3V, RLOAD = 12.5Ω, unless otherwise noted. LTC2000-16 Integral Nonlinearity (INL) LTC2000-16 Differential Nonlinearity (DNL) 4 2 2 1 6 INL vs IOUTFS and Temperature 4 INL (POS) 0 INL (LSB) DNL (LSB) INL (LSB) 2 0 0 –2 –1 –2 –4 –4 –32768 –16384 0 16384 –2 –32768 32768 0 –16384 16384 DNL vs IOUTFS and Temperature 0 0.02 0 –0.02 –2 16 BIT 14 BIT 11 BIT –0.04 –4 DNL (NEG) –25 0 25 50 TEMPERATURE (°C) 75 100 –0.06 –50 –25 0 25 50 TEMPERATURE (°C) 75 Reference Output Voltage vs Temperature 1.255 –1.0 –50 100 I (mA) 1.250 30 25 AVDD18 400 DVDD18 2000 G07 0 100 DVDD18 AVDD18 SVDD AVDD33 DVDD33 15 10 5 AVDD33 DVDD33 100 100 75 20 200 75 0 25 50 TEMPERATURE (°C) Shutdown Current vs Temperature 700 300 1.245 –25 2000 G06 35 500 VREF (V) –0.5 800 600 0 25 50 TEMPERATURE (°C) 0 Supply Current vs fDAC 1.260 –25 0.5 2000 G05 2000 G04 1.240 –50 40mA 60mA Gain Error vs Temperature GAIN ERROR (% FSR) DNL (POS) –6 –50 100 2000 G03 1.0 I (µA) DNL (LSB) 2 75 0.04 OFFSET ERROR (%FSR) 4 Offset Error vs Temperature 0.06 40mA 60mA 0 25 50 TEMPERATURE (°C) 10mA 20mA 2000 G02 2000 G01 10mA 20mA INL (NEG) –25 CODE CODE 6 –6 –50 32768 0 500 1000 1500 fDAC (MHz) 2000 2500 0 –5 –50 –25 0 25 50 75 100 TEMPERATURE (°C) 2000 G08 2000 G09 2000f For more information www.linear.com/LTC2000 9 LTC2000 Typical Performance Characteristics IOUTFS = 40mA, TA = 25°C, AVDD18 = DVDD18 = 1.8V, AVDD33 = DVDD33 = 3.3V, RLOAD = 12.5Ω, LIN_DIS = 0, LIN_ GN = 75% unless otherwise noted. 0 Single-Tone Spectrum at fOUT = 990MHz, fDAC = 2.5Gsps 0 RBW = 2kHz, VBW = 5kHz REF = 5dBm, ATTEN = 25dB SWEEP = 620s (1001 PTS) –10 –20 –20 –30 –40 10dB/DIV 10dB/DIV –30 fDAC-fOUT IMAGE –50 –60 –70 –70 –80 –80 20 516 –90 2500 2004 1508 1012 FREQUENCY (MHz) HD2 AND HD3 IN 2ND NYQUIST BAND –50 20 516 60 50 200 400 600 800 fOUT (MHz) 1000 80 80 50 0 200 400 600 800 fOUT (MHz) 1000 1200 0 200 400 600 800 fOUT (MHz) 2000 G16 10 1000 80 70 50 1200 0 200 400 600 800 fOUT (MHz) 60 100 90 80 70 0dBFS –3dBFS –6dBFS –12dBFS –16dBFS 60 200 400 600 800 fOUT (MHz) 1200 HD2 vs fOUT and Digital Amplitude (dBFS), fDAC = 2.5Gsps DIGITAL AMPLITUDE = 0dBFS 2.5Gsps 2.0Gsps 1.6Gsps 1.25Gsps 0 1000 2000 G15 HD3 vs fOUT and fDAC 70 50 1200 60 HD2 (dBc) 90 HD3 (dBc) HD2 (dBc) 100 1000 60mA 40mA 20mA 10mA 90 SFDR (dBc) 70 90 60 600 800 fOUT (MHz) 2000 G14 HD2 vs fOUT and fDAC DIGITAL AMPLITUDE = 0dBFS 2.5Gsps 2.0Gsps 1.6Gsps 1.25Gsps 400 100 0dBFS –3dBFS –6dBFS –12dBFS –16dBFS 80 50 1200 70 200 SFDR vs fOUT and IOUTFS, fDAC = 2.5Gsps 60 0 0 2000 G12 SFDR vs fOUT and Digital Amplitude (dBFS), fDAC = 2.5Gsps 2000 G13 100 50 2500 2004 1508 1012 FREQUENCY (MHz) 90 SFDR (dBc) SFDR (dBc) 70 70 60 100 DIGITAL AMPLITUDE = 0dBFS 90°C 25°C –40°C 80 80 2000 G11 SFDR vs fOUT and Temperature, fDAC = 2.5Gsps 90 DIGITAL AMPLITUDE = 0dBFS 2.5Gsps 2.0Gsps 1.6Gsps 1.25Gsps HD3 2000 G10 100 SFDR vs fOUT and fDAC 90 fDAC-fOUT IMAGE –40 –60 –90 RBW = 2kHz VBW = 5kHz REF = 5dBm ATTEN = 25dB SWEEP = 620s (1001 PTS) –10 100 SFDR (dBc) Single-Tone Spectrum at fOUT = 70MHz, fDAC = 2.5Gsps 1000 1200 2000 G17 50 0 200 400 600 800 fOUT (MHz) 1000 1200 2000 G18 2000f For more information www.linear.com/LTC2000 LTC2000 Typical Performance Characteristics IOUTFS = 40mA, TA = 25°C, AVDD18 = DVDD18 = 1.8V, AVDD33 = DVDD33 = 3.3V, RLOAD = 12.5Ω, LIN_DIS = 0, LIN_ GN = 75% unless otherwise noted. 2-Tone IMD vs fOUT and fDAC 110 90 100 80 90 70 0dBFS –3dBFS –6dBFS –12dBFS –16dBFS 60 0 200 400 600 800 fOUT (MHz) 1000 80 60 1200 0 200 400 600 800 fOUT (MHz) 1000 2000 G19 90 80 200 90 80 400 600 800 fOUT (MHz) 1000 60 1200 0 200 400 600 800 fOUT (MHz) 1000 200 400 600 800 fOUT (MHz) 1000 1200 2000 G25 HD3 (dBc) 1000 SFDR vs fOUT and Linearization Setting, fDAC = 2.5Gsps DIGITAL AMPLITUDE = 0dBFS LIN_GN = 100% LIN_GN = 75% LIN_GN = 50% LIN_DIS = 1 0 200 400 600 800 fOUT (MHz) 1000 LTC2000-16 Single-Tone NSD vs fOUT and IOUTFS DIGITAL AMPLITUDE = 0dBFS fDAC = 2.5Gsps 12.5Ω TOTAL OUTPUT LOAD –150 60mA 40mA –160 –160 1200 2000 G24 –155 –155 –170 1200 70 –145 20mA –165 –165 0 600 800 fOUT (MHz) 80 50 1200 DIGITAL AMPLITUDE = 0dBFS 40mA FULL-SCALE CURRENT 0dBm SINGLE-TONE 2.5Gsps 1.25Gsps –150 NSD (dBm/Hz) 60 400 60 –145 DIGITAL AMPLITUDE = 0dBFS LIN_GN = 100% LIN_GN = 75% LIN_GN = 50% LIN_DIS = 1 70 200 90 DIGITAL AMPLITUDE = –6dBFS F2 = F1 + 1.25MHz LTC2000-16 Single-Tone NSD vs fOUT and fDAC 80 0 2000 G23 HD3 vs fOUT and Linearization Setting, fDAC = 2.5Gsps 90 50 100 70 LIN_DIS = 0 LIN_GN = 75% 0 0dBFS –6dBFS –12dBFS –16dBFS 2000 G21 LIN_GN = 100% LIN_GN = 75% LIN_GN = 50% LIN_GN = 1% 2000 G22 100 60 1200 2-Tone IMD vs fOUT and Linearization Setting, fDAC = 2.5Gsps 100 70 60 80 70 SFDR (dBc) IMD (dBc) 100 110 IMD (dBC) DIGITAL AMPLITUDE = –6dBFS F2 = F1 + 1.25MHz 2.5Gsps 2.0Gsps 1.6Gsps 1.25Gsps 90 2000 G20 2-Tone IMD vs fOUT and fDAC with Default Linearization 110 F2 = F1 + 1.25MHz LIN_DIS = 1 100 2.5Gsps 2.0Gsps 1.6Gsps 1.25Gsps 70 2-Tone IMD vs fOUT and Digital Amplitude, fDAC = 2.5Gsps NSD (dBm/Hz) 50 110 DIGITAL AMPLITUDE = –6dBFS F2 = F1 + 1.25MHz LIN_DIS = 1 IMD (dBC) 100 IMD (dBC) HD3 (dBc) HD3 vs fOUT and Digital Amplitude (dBFS), fDAC = 2.5Gsps –170 0 200 400 600 800 fOUT (MHz) 1000 1200 2000 G26 0 200 400 600 800 fOUT (MHz) 1000 1200 2000 G27 2000f For more information www.linear.com/LTC2000 11 LTC2000 Typical Performance Characteristics IOUTFS = 40mA, TA = 25°C, AVDD18 = DVDD18 = 1.8V, AVDD33 = DVDD33 = 3.3V, RLOAD = 12.5Ω, LIN_DIS = 0, LIN_ GN = 75% unless otherwise noted. LTC2000-16 Single Carrier DOCSIS Low Band Wideband ACLR, fDAC = 2.5Gsps –40 –60 –70 –89.2dBm/6MHz –90 –30 –50 –89.9dBm/6MHz –70 –80 –110 –120 –120 50 150 250 350 450 550 650 750 850 950 FREQUENCY (MHz) –40 –50 –14dBm/6MHz –60 –70 –80 –90 –89.4dBm/6MHz –100 –89.2dBm/6MHz –89.2dBm/6MHz –110 –120 50 150 250 350 450 550 650 750 850 950 FREQUENCY (MHz) 50 150 250 350 450 550 650 750 850 950 FREQUENCY (MHz) 2000 G28 2000 G29 2000 G30 Single Carrier DOCSIS Low Band Narrowband ACLR, fDAC = 2.5Gsps Single Carrier DOCSIS Mid Band Narrowband ACLR, fDAC = 2.5Gsps Single Carrier DOCSIS High Band Narrowband ACLR, fDAC = 2.5Gsps –20 RBW = 30kHz VBW = 3kHz REF = –20dBm ATTEN = 5dB SWEEP = 24s –30 –40 –50 –30 –40 –50 10dB/DIV –60 –70 –80 –20 RBW = 30kHz VBW = 3kHz REF = –20dBm ATTEN = 5dB SWEEP = 24s –60 –70 –80 –40 –50 –60 –70 –80 –90 –90 –90 –100 –100 –100 –110 –110 –110 –120 173 –120 523 183 193 203 213 FREQUENCY (MHz) 223 2000 G31 CARRIER POWER = –11.16dBm, CENTER FREQ = 200MHz OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz 12 BW 750kHz 5.25MHz 6MHz 6MHz 6MHz LOWER –100.31dBm –96.02dBm –96.47dBm –96.40dBm –96.40dBm 533 UPPER –94.84dBm –94.67dBm –95.48dBm –96.29dBm –96.57dBm 543 553 563 FREQUENCY (MHz) RBW = 30kHz VBW = 3kHz REF = –20dBm ATTEN = 5dB SWEEP = 24s –30 10dB/DIV –20 10dB/DIV RBW = 20kHz VBW = 2kHz REF = –20dBm ATTEN = 5dB SWEEP = 60s –30 –84.1dBm/6MHz –100 –110 –20 RBW = 20kHz VBW = 2kHz REF = –20dBm ATTEN = 5dB SWEEP = 60s –60 –90 –87.3dBm/6MHz –100 –11.7dBm/6MHz –40 10dB/DIV 10dB/DIV –50 –80 –20 RBW = 20kHz VBW = 2kHz REF = –20dBm ATTEN = 5dB SWEEP = 60s –30 –11.2dBm/6MHz Single Carrier DOCSIS High Band Wideband ACLR, fDAC = 2.5Gsps 10dB/DIV –20 Single Carrier DOCSIS Mid Band Wideband ACLR, fDAC = 2.5Gsps 573 –120 953 963 2000 G32 973 983 993 FREQUENCY (MHz) 1003 2000 G33 CARRIER POWER = –11.66dBm, CENTER FREQ = 550MHz CARRIER POWER = –14.04dBm, CENTER FREQ = 980MHz OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz BW 750kHz 5.25MHz 6MHz 6MHz 6MHz LOWER –95.63dBm –93.01dBm –94.66dBm –95.19dBm –94.97dBm UPPER –93.62dBm –92.97dBm –94.51dBm –94.87dBm –95.15dBm OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz BW 750kHz 5.25MHz 6MHz 6MHz 6MHz LOWER –89.47dBm –87.24dBm –93.04dBm –93.52dBm –93.33dBm UPPER –89.52dBm –87.00dBm –92.94dBm –92.51dBm –92.03dBm 2000f For more information www.linear.com/LTC2000 LTC2000 Typical Performance Characteristics IOUTFS = 40mA, TA = 25°C, AVDD18 = DVDD18 = 1.8V, AVDD33 = DVDD33 = 3.3V, RLOAD = 12.5Ω, LIN_DIS = 0, LIN_ GN = 75% unless otherwise noted. LTC2000-16 32-Carrier DOCSIS Low Band Wideband ACLR, fDAC = 2.5Gsps –50 –60 –70 –40 –50 –60 –80 –90 –30 RBW = 20kHz VBW = 2kHz REF = –30dBm ATTEN = 5dB SWEEP = 60s –40 –50 –60 –70 10dB/DIV 10dB/DIV –30 RBW = 20kHz VBW = 2kHz REF = –30dBm ATTEN = 5dB SWEEP = 60s –40 10dB/DIV –30 32 Carrier DOCSIS High Band Wideband ACLR, fDAC = 2.5Gsps 32-Carrier DOCSIS Mid Band Wideband ACLR, fDAC = 2.5Gsps –80 –90 –70 –80 –90 –100 –100 –100 –110 –110 –110 –120 –120 –120 –130 –130 50 150 250 350 450 550 650 750 850 950 FREQUENCY (MHz) 2000 G34 2000 G35 32-Carrier DOCSIS Low Band Narrowband ACLR, fDAC = 2.5Gsps 32 Carrier DOCSIS Mid Band Narrowband ACLR, fDAC = 2.5Gsps –40 –50 –60 –70 –40 –50 –60 10dB/DIV 10dB/DIV –30 RBW = 30kHz VBW = 3kHz REF = –30dBm ATTEN = 5dB SWEEP = 24s –80 –90 32 Carrier DOCSIS High Band Narrowband ACLR, fDAC = 2.5Gsps –30 RBW = 30kHz VBW = 3kHz REF = –30dBm ATTEN = 5dB SWEEP = 24s –40 –50 –60 –70 –80 –90 –80 –90 –100 –100 –110 –110 –110 –120 –120 –120 –130 359 –130 473 379 389 399 FREQUENCY (MHz) 409 2000 G37 CARRIER POWER = –28.64dBm, CENTER FREQ = 386MHz OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz BW 750kHz 5.25MHz 6MHz 6MHz 6MHz LOWER –39.32dBm –29.01dBm –28.68dBm –28.54dBm –28.49dBm 483 UPPER –103.86dBm –95.18dBm –94.68dBm –94.97dBm –95.08dBm 493 503 513 FREQUENCY (MHz) 523 RBW = 30kHz VBW = 3kHz REF = –30dBm ATTEN = 5dB SWEEP = 24s –70 –100 369 50 150 250 350 450 550 650 750 850 950 FREQUENCY (MHz) 2000 G36 10dB/DIV –30 –130 50 150 250 350 450 550 650 750 850 950 FREQUENCY (MHz) RBW = 20kHz VBW = 2kHz REF = –30dBm ATTEN = 5dB SWEEP = 60s –130 773 783 2000 G38 793 803 813 FREQUENCY (MHz) 823 2000 G39 CARRIER POWER = –28.42dBm, CENTER FREQ = 500MHz CARRIER POWER = –29.31dBm, CENTER FREQ = 800MHz OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz BW 750kHz 5.25MHz 6MHz 6MHz 6MHz LOWER –102.49dBm –94.71dBm –94.02dBm –94.36dBm –93.72dBm UPPER –39.23dBm –28.92dBm –28.69dBm –28.71dBm –28.74dBm OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz BW 750kHz 5.25MHz 6MHz 6MHz 6MHz LOWER –98.23dBm –90.00dBm –89.76dBm –89.72dBm –89.76dBm UPPER –40.42dBm –29.56dBm –29.20dBm –29.25dBm –29.55dBm 2000f For more information www.linear.com/LTC2000 13 LTC2000 Typical Performance Characteristics IOUTFS = 40mA, TA = 25°C, AVDD18 = DVDD18 = 1.8V, AVDD33 = DVDD33 = 3.3V, RLOAD = 12.5Ω, LIN_DIS = 0, LIN_ GN = 75% unless otherwise noted. LTC2000-16 128 Carrier DOCSIS Low Band Wideband ACLR, fDAC = 2.5Gsps –30 –30 RBW = 20kHz, VBW = 2kHz REF = –30dBm, ATTEN = 5dB SWEEP = 60s –40 –50 –40 –50 –30 RBW = 20kHz, VBW = 2kHz REF = –30dBm, ATTEN = 5dB SWEEP = 60s –50 –70 –70 –90 10dB/DIV –60 –70 –80 –80 –90 –80 –90 –100 –100 –100 –110 –110 –110 –120 –120 –120 –130 –130 50 150 250 350 450 550 650 750 850 950 FREQUENCY (MHz) –60 –30 –40 –50 10dB/DIV –70 –80 –90 2000 G42 157 Carrier Tones with Gap Channel Narrowband ACLR, fDAC = 2.5Gsps –30 RBW = 30kHz, VBW = 3kHz REF = –30dBm, ATTEN = 5dB SWEEP = 24s –40 –50 –60 –60 –70 –70 10dB/DIV –50 30 130 230 330 430 530 630 730 830 930 FREQUENCY (MHz) 157 Carrier DOCSIS Gap Channel Narrowband ACLR, fDAC = 2.5Gsps RBW = 30kHz VBW = 3kHz REF = –30dBm ATTEN = 5dB SWEEP = 24s –40 –130 30 130 230 330 430 530 630 730 830 930 FREQUENCY (MHz) 2000 G41 128 Carrier DOCSIS Low Band Narrowband ACLR, fDAC = 2.5Gsps –30 RBW = 20kHz, VBW = 2kHz, REF = –30dBm, ATTEN = 5dB, SWEEP = 60s, LIN_DIS = 1 –40 –60 2000 G40 10dB/DIV 157 Carrier Tones with Gap Channel Wideband ACLR, fDAC = 2.5Gsps –60 10dB/DIV 10dB/DIV 157 Carrier DOCSIS Gap Channel Wideband ACLR, fDAC = 2.5Gsps –80 –90 –80 –90 –100 –100 –100 –110 –110 –110 –120 –120 –120 –130 805 –130 481 –130 510 815 825 835 845 FREQUENCY (MHz) 855 CARRIER POWER = –37.59dBm, CENTER FREQ = 832MHz OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz 14 BW 750kHz 5.25MHz 6MHz 6MHz 6MHz LOWER –48.37dBm –37.97dBm –37.33dBm –37.13dBm –37.15dBm 491 2000 G43 UPPER –103.39dBm –95.72dBm –95.55dBm –96.33dBm –95.91dBm 501 511 521 FREQUENCY (MHz) 531 2000 G44 GAP CHANNEL POWER = –96.45dBm, CENTER FREQ = 508MHz OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz BW 750kHz 5.25MHz 6MHz 6MHz 6MHz LOWER –48.05dBm –36.61dBm –36.32dBm –36.48dBm –36.54dBm RBW = 30kHz, VBW = 3kHz REF = –30dBm, ATTEN = 10dB SWEEP = 24s, LIN_DIS = 1 520 515 FREQUENCY (MHz) 525 2000 G45 UPPER –47.93dBm –36.50dBm –36.27dBm –36.45dBm –36.57dBm 2000f For more information www.linear.com/LTC2000 LTC2000 Typical Performance Characteristics IOUTFS = 40mA, TA = 25°C, AVDD18 = DVDD18 = 1.8V, AVDD33 = DVDD33 = 3.3V, RLOAD = 12.5Ω, LIN_DIS = 0, LIN_ GN = 75% unless otherwise noted. LTC2000-16 Single Carrier WCDMA ACLR vs fOUT, fDAC = 2.5Gsps LTC2000-16 Single Carrier WCDMA ACLR at 350MHz, fDAC = 2.5Gsps RBW = 30kHz VBW = 3kHz REF = –20dBm ATTEN = 5dB SWEEP = 24s –40 –50 –60 10dB/Hz ACLR (dBc) –60 –70 –80 –90 –100 –80 –90 –70 200 400 600 800 fOUT (MHz) 1000 –130 323 333 OFFSET FREQ 5.00MHz 10.00MHz 15.00MHz 20.00MHz 25.00MHz 343 353 363 FREQUENCY (MHz) 1 0.5 4096 8192 CODE BW 3.84MHz 3.84MHz 3.84MHz 3.84MHz 3.84MHz LOWER –94.15dBm –95.61dBm –95.72dBm –96.97dBm –96.07dBm 100 0.1 1 10 OFFSET FREQUENCY (kHz) 2000 G48 LTC2000-14 Single-Tone NSD vs fOUT and fDAC –145 DIGITAL AMPLITUDE = 0dBFS 40mA FULL-SCALE CURRENT 0dBm SINGLE TONE –150 0 –1.0 –8192 1000 UPPER –94.40dBm –94.99dBm –95.55dBm –96.37dBm –96.50dBm 2.5Gsps 1.25Gsps –155 –160 –165 –4096 0 4096 8192 CODE 2000 G49 –160 2000 G47 –0.5 0 –150 –180 0.01 373 NSD (dBm/Hz) 1.0 DNL (LSB) INL (LSB) 2 –4096 –140 LTC2000-14 Differential Nonlinearity (DNL) LTC2000-14 Integral Nonlinearity (INL) –2 –8192 –130 CARRIER POWER = –17.06dBm, CENTER FREQ = 350MHz 2000 G46 –1 –120 –170 –120 1200 0 –110 –110 ADJ CHANNEL 2ND ADJ CHANNEL 5TH ADJ CHANNEL 0 –100 PHASE NOISE (dBc/Hz) –30 –50 Additive Phase Noise, fOUT = 65MHz, fDAC = 2.5Gsps 2000 G50 –170 0 200 400 600 800 fOUT (MHz) 1000 1200 2000 G51 2000f For more information www.linear.com/LTC2000 15 LTC2000 Typical Performance Characteristics IOUTFS = 40mA, TA = 25°C, AVDD18 = DVDD18 = 1.8V, AVDD33 = DVDD33 = 3.3V, RLOAD = 12.5Ω, LIN_DIS = 0, LIN_ GN = 75% unless otherwise noted. LTC2000-11 Differential Nonlinearity (DNL) 0.50 0.5 0.25 0 –145 –150 0 –155 –160 DIGITAL AMPLITUDE = 0dBFS 40mA FULL-SCALE CURRENT 0dBm SINGLE TONE –0.25 –0.5 –1.0 –1024 LTC2000-11 Single-Tone NSD vs fOUT and fDAC NSD (dBm/Hz) 1.0 DNL (LSB) INL (LSB) LTC2000-11 Integral Nonlinearity (INL) –165 –512 0 512 1024 –1.50 –1024 –512 0 512 1024 CODE CODE 2000 G53 2000 G52 –170 2.5Gsps 1.25Gsps 0 200 400 600 800 fOUT (MHz) 1000 1200 2000 G54 Pin Functions AVDD18: 1.8V Analog Supply Voltage Input. 1.71V to 1.89V. AVDD33: 3.3V Analog Supply Voltage Input. 3.135V to 3.465V. CKP, CKN: DAC Sample Clock Inputs. Maximum clock frequency (fDAC) is 2500MHz. Clock signal should be AC coupled. CS: Serial Interface Chip Select Input. When CS is low, SCK is enabled for shifting data on SDI into the register. When CS is taken high, SCK is disabled and SDO is high impedance. DAP[15:0], DAN[15:0]: Port A LVDS Data Inputs. Maximum data rate is 1.25Gbps. Port A is used only in dual-port mode. Connect to GND if not used. The data input format is two’s complement. DBP[15:0], DBN[15:0]: Port B LVDS Data Inputs. Maximum data rate is 1.25Gbps. In single-port mode, only Port B is used. In dual-port mode, the sample from Port B appears at IOUTP/N one cycle after the sample from Port A. The data input format is two’s complement. DCKIP, DCKIN: LVDS Data Clock Inputs. Maximum frequency (fDCKI) is 625MHz. In dual-port mode, fDCKI = fDAC/4. In single-port mode, fDCKI = fDAC/2 16 DCKOP, DCKON: LVDS Data Clock Outputs. Maximum frequency is 625MHz. Select frequency (fDAC/4 or fDAC/2), output current (3.5mA or 7mA), and termination (none or 100Ω) using register 0x02. DVDD18: 1.8V Digital Supply Voltage Input. 1.71V to 1.89V. DVDD33: 3.3V Digital Supply Voltage Input. 3.135V to 3.465V. FSADJ: Full-Scale Adjust Pin. The DAC full-scale current is 16 • (VREFIO/RFSADJ). Connect a 500Ω resistor from FSADJ to GND to set the full-scale current to 40mA. GND: Ground. IOUTP, IOUTN: DAC Analog Current Outputs. Differential output is nominally ±40mA. Maximum update rate is 2.5Gsps. The output current is evenly divided between IOUTP and IOUTN when the two’s compliment DAC code is set to mid-scale (all zeros). PD (Pin S1): Active Low Power-Down Input. When PD is low, the LTC2000 supply current is less than 440µA. To exit power-down mode switch PD high to SVDD. 2000f For more information www.linear.com/LTC2000 LTC2000 Pin Functions REFIO: Reference Voltage Input or Output. The 1.25V internal reference is available at the pin through a 10k internal resistor. May be overdriven with an external reference voltage between 1.1V and 1.4V. SCK: Serial Interface Clock Input. Maximum frequency is 50MHz. SDI: Serial Interface Data Input. Data on SDI is clocked in on the rising edge of SCK. SDO: Serial Interface Data Output. Data is clocked out onto SDO by the falling edge of SCK. SDO is high impedance when CS is high. SVDD: SPI Supply Voltage Input. 1.71V to 3.465V. TSTP, TSTN: Test Output Pins. May be optionally used to measure internal temperature or timing of LVDS inputs. See Measuring Internal Junction Temperature and Measuring LVDS Input Timing Skew sections in Applications Information. Use SPI internal registers 0x18 and 0x19 to control TSTP/N. Connect to GND if not used. Note: For pin locations, refer to the Pin Locations section of this data sheet. Block Diagram TSTP/N PD JUNCTION TEMPERATURE CS PATTERN GENERATOR SCK SDI SVDD SDO SPI DAP/N[15:0] DDR DATA FLIP-FLOPS LVDS RECEIVERS DBP/N[15:0] IOUTP 50Ω 16-BIT DAC 4:1 50Ω IOUTN GAIN ADJUST DCKIP/N CLOCK SYNC DELAY ADJUST CLK DIVIDER ÷2 OR ÷4 DCKOP/N AVDD18 DVDD18 FSADJ CLK RECEIVER AVDD33 DVDD33 GND CKP/N REFIO 10k REF 2000 BD 2000f For more information www.linear.com/LTC2000 17 LTC2000 Timing Diagrams t1 t2 SCK t3 1 t6 t4 2 3 15 16 t10 SDI t5 t7 CS t13 Hi-Z SDO Hi-Z 2000 F01 Figure 1. Serial Interface Timing t12 t12 t11 t11 DAP/N, DBP/N DCKI 2000 F02 Figure 2. LVDS Interface Timing (DCKI_Q = 0, DCK_TADJ = 000) t11 t11 DAP/N, DBP/N DCKI 2000 F03 t12 t12 Figure 3. LVDS Interface Timing (DCKI_Q = 1) Operation Introduction The LTC2000 is a family of 2.5Gsps current steering DACs. Three resolutions (16-, 14-, 11-bit) are available in a 170-lead BGA package. The LTC2000 features high output bandwidth and output current, while maintaining a clean output spectrum with low spurs, making it ideal for generating high frequency or broadband signals. The LTC2000 output current is nominally 40mA and is a scaled (16x) replica of the current flowing out of the FSADJ pin (nominally 2.5mA). The high output current allows 18 flexibility in the output impedance, and the high FSADJ current and low scaling factor give excellent close-in phase noise performance. The LTC2000 has two 16-, 14-, 11-bit wide LVDS or DHSTLcompatible parallel data input ports (DAP/N, DBP/N). Each data input port is capable of receiving two’s complement data at up to 1.25Gbps using a double data rate (DDR) data input clock (DCKIP/N) at up to 625MHz. The DDR data input clock may be either in quadrature or in phase with the data arriving on the data input ports. 2000f For more information www.linear.com/LTC2000 LTC2000 Operation After incoming data is sampled by DCKIP/N, an internal multiplexer interleaves the data for resampling by the DAC sample clock (CKP/N). See Figures 4a and 4b. After a pipeline delay (latency) of up to 11 DAC sample clock cycles, the rising edges of CKP/N update the DAC code and a proportional differential output current is steered between the two outputs (IOUTP/N). Note it takes about 3ns (aperature delay) from the CKP/N rising edge that updates a DAC code to the actual IOUTP/N transition for that DAC code. An internal clock synchronizer monitors the incoming phase of DCKIP/N and chooses the appropriate phase for the multiplexer control signals to ensure that the data is sampled correctly by CKP/N. The LTC2000 also generates an LVDS clock output (DCKOP/N) by dividing the sample clock frequency to simplify clocking of the host FPGA or ASIC. Additional features such as pattern generation, LVDS loopout, and junction temperature sensing simplify system development and testing. The serial peripheral interface (SPI) port allows configuration and read back of the internal registers which control the above functions. Dual-Port Mode In dual-port mode, data is written to both ports A and B simultaneously and then subsequently interleaved inside the LTC2000, allowing DAC output sampling rates of up to 2.5Gsps. Figures 4a and 4b show a simplified block diagram and sample waveforms for dual-port operation. The LVDS data input ports A and B are sampled on both the falling and rising edges of the DDR data input clock (DCKIP/N) by four groups of flip-flops. The contents of these flip-flops are then interleaved by the 4:1 mux and sampled by the DAC sample clock (CKP/N) at frequencies up to 2.5GHz, with data from port A (DAP/N) preceding data from port B (DBP/N) at the DAC output. Note that the sample clock (CKP/N) frequency is always four times the DDR data input clock (DCKIP/N) frequency in dual-port mode. For example, to use the DAC at 2.5Gsps, apply a 2.5GHz clock to CKP/N and a 625MHz clock to DCKIP/N and send data into both ports A and B (DAP/N, DBP/N) at 1.25Gsps per port. Latency is defined as the delay from the DCKIP/N transition that samples a DAC code to the CKP/N rising transition which causes that sample to appear at the DAC output IOUTP/N. In dual-port mode the latency from DAP/N to IOUTP/N is 10 sample clock cycles and the latency from DBP/N to IOUTP/N is 11 cycles, starting from the CKP/N rising edge that immediately follows the DCKIP/N transition that sampled the DAC code (Figure 4b). Single-Port Mode In single-port mode, data is written to port B (DBP/N) only, allowing DAC output sampling rates of up to 1.25Gsps. Figures 4c and 4d show a block diagram and sample waveforms representing single-port operation. Samples are written to port B (DBP/N) and sampled on both the falling and rising edges of the DDR data input clock (DCKIP/N) by two groups of flip-flops. The contents of these flip-flops are then interleaved into a single data stream by the 2:1 mux and sampled by the DAC sample clock (CKP/N) at frequencies up to 1.25GHz. Note that in single-port mode the sample clock (CKP/N) frequency is always twice the DDR data input clock (DCKIP/N) frequency. For example, to use the DAC at 1.25Gsps, apply a 1.25GHz clock to CKP/N and a 625MHz clock to DCKIP/N and send data into port B (DBP/N) at 1.25Gsps. In singleport mode, port A (DAP/N) should be grounded. Due to the design of the internal clock synchronizer in single port mode, there is a half cycle shift in the single port latency. The latency from DBP/N to IOUTP/N in single-port mode is 7.5 sample clock cycles, starting from the CKP/N falling edge that immediately follows the DCKIP/N transition that sampled the DAC code (Figure 4d). 2000f For more information www.linear.com/LTC2000 19 LTC2000 Operation DAP/N[15:0] N IOUTP N+1 N+2 4:1 MUX DBP/N[15:0] 50Ω 16-BIT DAC 50Ω IOUTN N+3 CLOCK SYNC DCKIP/N CKP/N 2000 F04a Figure 4a. Simplified Block Diagram – Dual-Port Operation DAP/N[15:0] N N+2 N+4 N+6 N+8 N+10 DBP/N[15:0] N+1 N+3 N+5 N+7 N+9 N+11 DCKIP/N CKP/N 1 2 3 4 5 6 7 8 IOUTP/N 9 10 11 N 10 CYCLE LATENCY 11 CYCLE LATENCY N+1 2000 F04b Figure 4b. Sample Waveforms – Dual-Port Operation 20 2000f For more information www.linear.com/LTC2000 LTC2000 Operation DBP/N[15:0] IOUTP N 2:1 MUX N+1 50Ω 16-BIT DAC 50Ω IOUTN CLOCK SYNC DCKIP/N CKP/N 2000 F04c Figure 4c. Simplified Block Diagram – Single-Port Operation DBP/N[15:0] N N+1 N+2 N+3 N+4 N+5 N+6 N+6 N+7 DCKIP/N CKP/N 0.5 1.5 2.5 3.5 4.5 5.5 6.5 IOUTP/N 7.5 N 7.5 CYCLE LATENCY 2000 F04b Figure 4d. Sample Waveforms – Single-Port Operation 2000f For more information www.linear.com/LTC2000 21 LTC2000 Operation Serial Peripheral Interface (SPI) Power-On Reset The LTC2000 uses an SPI/MICROWIRE-compatible 3-wire serial interface to configure and read back internal registers. The SVDD pin is the power supply for the SPI interface (nominally 1.8V or 3.3V). The CS input is level triggered. When this input is taken low, it acts as a chipselect signal, enabling the SDI and SCK buffers and the SPI input register. After the falling edge of CS, the first data byte clocked into SDI by the rising edges of SCK is the command byte. The first bit of the command byte signifies a read (R/W = 1) or write (R/W = 0) operation. The next seven bits contain the register address, which completes the command byte. The internal power-on reset circuit will reset the LTC2000 upon power up and clear the output to mid-scale when power is first applied, making system initialization consistent and repeatable. All internal registers are reset to 0x00, with the exception of register address 0x08, which resets to 0x08. A software reset can also be applied by using the SPI interface to load 0x01 into register address 0x01, setting SW_RST to 1 (see Table 1). Note that the SW_RST bit is automatically cleared when CS returns high. It is recommended that users perform a software reset once all power supplies are stable. Power Down The next byte transferred after the command byte is the data byte. For write operations, the data byte is written to the SPI register specified by the register address set in the command byte. During read operations, the data byte is ignored, and the contents of the selected SPI register are clocked out onto the SDO pin by the falling edges of SCK. During write operations, SDO will be low. When CS goes high, SDO is high impedance. Figure 5 shows the SPI command and data input. Users wishing to save power when the DAC is not being used may reduce the supply current to less than 440µA by pulling the PD pin to GND or by writing to register 0x01 to set FULL_PD = 1. Alternatively, users may power down unused portions of the chip individually using DAC_PD, CK_PD, DCKO_DIS, DCKI_EN, DA_EN, and DB_EN in registers 0x01, 0x02, 0x03, and 0x04 (see Table 1). Reference Operation Users wishing to transfer multiple bytes of data at once may do so, with the address for each subsequent byte automatically incremented internally. The address will continue to increment until CS goes high or until address bits A[4:0] reach 0x1F, after which subsequent bytes will continue to be written to the same address. The LTC2000 has a 1.25V internal bandgap voltage reference that drives the REFIO pin through a 10k internal resistor, and should be buffered if driving any additional external load. For noise performance, a 0.1µF capacitor to GND is recommended on the REFIO pin, but is not required for stability. Reserved address and bit locations should not be written with any value other than zero. Table 11 contains a full description of all internal SPI registers and can be found in the SPI Register Summary section. In the case where an external reference would be preferred, the external reference is simply applied to the REFIO pin and overdrives the internal reference. The acceptable external reference range is 1.1V to 1.4V. COMMAND BYTE READ/WRITE R/W A6 REGISTER ADDRESS A5 A4 A3 A2 DATA BYTE A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 2000 F05 Figure 5. SPI Command and Data Input 22 2000f For more information www.linear.com/LTC2000 LTC2000 Operation Table 1. Power-On Reset and Power-Down SPI Registers ADDRESS BIT 0x01 0x02 NAME DESCRIPTION 0 SW_RST Software Reset. Set SW_RST = 1 to restore all registers to their power-on reset state. SW_RST is automatically cleared when CS returns high. All registers reset to 0x00, except address 0x08 which resets to 0x08. 1 DAC_PD DAC Power Down. Set DAC_PD = 1 to power down the DAC and FSADJ bias circuits. 2 FULL_PD Full Power Down. Set FULL_PD = 1 to power down all active circuits on the chip and reduce the supply current to less than 100µA. 0 CK_PD 4 DCKO_DIS CKP/N Clock Receiver Power Down. CKP/N clock receiver is powered down when CK_PD = 1. 0x03 0 DCKI_EN 0x04 0 DA_EN DAC Data Port A LVDS Receiver Enable. Set DA_EN = 1 to enable port A (DAP/N) LVDS receivers. For DA_EN = 0, port A LVDS receivers are powered down and port A data will be zeroes. 1 DB_EN DAC Data Port B LVDS Receiver Enable. Set DB_EN = 1 to enable port B (DBP/N) LVDS receivers. For DB_EN = 0, port B LVDS receivers are powered down and port B data will be zeroes. DCKOP/N Output Disable. Set DCKO_DIS = 1 to power down the DCKO LVDS transmitter. For DCKO_DIS = 1, DCKOP/N are high impedance. DCKIP/N Clock Receiver Enable. Set DCKI_EN = 1 to enable the DCKI clock receiver. Note: Registers 0x01 to 0x04 reset to 0x00 (default). Setting the Full-Scale Current The full-scale DAC output current (IOUTFS) is nominally 40mA, but can be adjusted as low as 10mA or as high as 60mA. The full-scale current is set by placing an external resistor (RFSADJ) between the FSADJ pin and GND. An internal reference control loop amplifier sets the current flowing through RFSADJ such that the voltage at FSADJ is equal to the voltage at REFIO, which is typically 1.25V. IOUTFS is set as a scaled replica of the current flowing out of the FSADJ pin (IFSADJ): IFSADJ = VREFIO RFSADJ IOUTFS =16 •IFSADJ • 256 256+GAIN_ ADJ Changing GAIN_ADJ to 0x1F (+31) will decrease the current by 10.8% to 35.7mA. Changing GAIN_ADJ to 0x20 (–32) will increase the current by 14.3% to 45.7mA. Note that GAIN_ADJ appears in the denominator of the equation for IOUTFS, so the adjustment resolution varies from 0.5% to 0.3% per step. The circuit shown in Figure 6 may be used to vary the full-scale output current beyond the range of the GAIN_ADJ register. DAC linearity and harmonic distortion may be degraded when using full-scale currents other than 40mA. The fullscale current must not exceed 60mA, and is recommended to be at least 10mA. LTC2000 REF LTC2630-LM12 where GAIN_ADJ is a 6-bit two’s complement number from –32 to 31 (nominally 0) which can be programmed using SPI register 0x09 as shown in Table 2. For example, for RFSADJ = 500Ω, VREFIO = 1.25V, and GAIN_ADJ = 0x00, the control loop will force 1.25V at the FSADJ pin, causing 2.5mA to flow through RFSADJ. IOUTFS will then be set to 16 • 2.5mA = 40mA. 10k 0V TO 2.5V 1.25V 1k REFIO – FSADJ + 500Ω 2000 F06 Figure 6. LTC2000 Full-Scale Adjust from 20mA to 60mA 2000f For more information www.linear.com/LTC2000 23 LTC2000 Operation Table 2. Full-Scale Gain Adjustment ADDRESS BIT NAME 0x09 [5:0] GAIN_ADJ DESCRIPTION GAIN_ADJ (HEX) GAIN_ADJ (DECIMAL) GAIN ADJUSTMENT FULL-SCALE CURRENT (RFSADJ = 500Ω, VREFIO = 1.25V) 0x1F +31 89.2% 35.68mA 0x1E +30 89.5% 35.80mA — — — — 0x01 +1 99.6% 39.84mA 0x00 0 100.0% 40.00mA 0x3F –1 100.4% 40.16mA — — — — 0x21 –31 113.8% 45.51mA 0x20 –32 114.3% 45.71mA Note: Register 0x09 resets to 0x00 (default). DAC Transfer Function The LTC2000 contains an array of current sources that are steered through differential switches to either IOUTP or IOUTN, depending on the DAC code programmed through the LVDS parallel interface. The LTC2000 uses a 16‑/14‑/11‑bit two’s complement DAC code. The complementary current outputs, IOUTP and IOUTN, source current from 0mA to IOUTFS. For IOUTFS = 40mA (nominal), IOUTP swings from 0mA (for zero-scale DAC code) to 40mA (for full-scale DAC code). IOUTN is complementary to IOUTP. When the DAC code is set to mid-scale (all zeros), IOUTFS is evenly divided between IOUTP and IOUTN. IOUTP and IOUTN are given by the following formulas: The LTC2000 differential output currents typically drive a resistive load either directly or drive an equivalent resistive load through a transformer (see the Output Configurations section). The voltage outputs generated by the IOUTP and IOUTN outputs currents are then: VOUTP = IOUTP • RLOAD VOUTN = IOUTN • RLOAD VDIFF = VOUTP – VOUTN = (IOUTP-IOUTN) • RLOAD Substituting the values above gives: LTC2000-16: VDIFF = VREFIO • (RLOAD/RFSADJ) • (2 • CODE + 1)/4096 LTC2000-14: VDIFF = VREFIO • (RLOAD/RFSADJ) • (2 • CODE + 1/4)/1024 LTC2000-16: IOUTP = IOUTFS • (CODE + 32768)/65536 + IOUTCM IOUTN = IOUTFS • (32768 – CODE – 1)/65536 + IOUTCM LTC2000-11: VDIFF = VREFIO • (RLOAD/RFSADJ) • (2 • CODE + 1/32)/128 LTC2000-14: IOUTP = IOUTFS • (CODE + 8192)/16384 + IOUTCM IOUTN = IOUTFS • (8192 – CODE – 1/4)/16384 + IOUTCM Note that the gain of the DAC depends on the ratio of RLOAD to RFSADJ, and the gain error tempco is affected by the temperature tracking of RLOAD with RFSADJ. LTC2000-11: IOUTP = IOUTFS • (CODE + 1024)/2048 + IOUTCM IOUTN = IOUTFS • (1024 – CODE – 1/32)/2048 + IOUTCM Analog Outputs (IOUTP/N) –2N-1 2N-1 The DAC code ranges from to – 1, with N being the DAC resolution (16/14/11). IOUTCM is a small, constant common-mode output current that is equal to approximately 0.2% full-scale, or 80µA for IOUTFS = 40mA. 24 The two complementary analog outputs (IOUTP/N) have low output capacitance that, with appropriate RLOAD values, can achieve high output bandwidths of 2.1GHz. The analog outputs also have an internal impedance of 50Ω to GND that will affect the calculation of RLOAD and the output 2000f For more information www.linear.com/LTC2000 LTC2000 Operation voltage swing of the DAC. For example, loading both IOUTP and IOUTN with external 50Ω resistors to GND will cause RLOAD to equal 25Ω. Assuming an IOUTFS of 40mA, VDIFF will swing between 1V and –1V. The specified output compliance voltage range is ±1V. Above 1V, the differential current steering switches will start to approach the transition from saturation to linear region and degrade DAC linearity. Below –1V protection diodes will limit the swing of the DAC. Small voltage swings and low common-mode voltages typically result in the best distortion performance. DAC Sample Clock (CKP/N) The DAC sample clock (CKP/N) is used to update the LTC2000 outputs at rates of up to 2.5Gsps. Provide a clean, low jitter differential clock at up to 2.5GHz on pins CKP/N (see Generating the DAC Sample Clock section). The DC bias point of CKP/N is set internally through a 5kΩ impedance. A 0dBm DAC sample clock should be sufficient to obtain the performance shown in the Typical Performance Characteristics section. For best jitter and phase noise, AC couple a differential clock onto CKP/N with balanced duty cycle and the highest possible amplitude and slew rate. Use SPI register 0x02 to control the DAC sample clock receiver (Table 3). The LTC2000 contains a clock detector which sets CK_OK = 1 if the DAC sample clock is present and fDAC > 50MHz. When the sample clock is not present (CK_OK = 0), the DAC output is forced to mid-scale and the internal data path is held at reset. Set CK_PD = 1 to power down the clock receiver and save power when the DAC is not being used. Note that at power-on reset, the DAC sample clock receiver is on by default. Divided Clock Output (DCKOP/N) The LTC2000 contains a programmable clock divider and LVDS transmitter which provide a divided version (either fDAC/4 or fDAC/2) of the DAC sample clock for use by the host FPGA or ASIC. Use SPI register 0x02 to control DCKOP/N (Table 3). At power-on reset, the LVDS transmitter will provide a clock signal at fDAC/4 with a 3.5mA differential output current. If desired, set DCKO_DIV = 1 to change the divided clock output frequency to fDAC/2. The output current can be increased to 7mA by setting DCKO_ISEL = 1, and an internal 100Ω differential termination can be enabled by setting DCKO_TRM = 1. Set DCKO_DIS = 1 to disable the LVDS transmitter and save power when not in use. LVDS Data Clock Input (DCKIP/N) The DAC code data written to the LTC2000 is captured on both the rising and falling edges of DCKIP/N. For single-port operation, provide a DDR clock at half the DAC sample clock frequency (fDCKI = fDAC/2). To use a 1.25GHz sample clock in single-port mode, provide a 625MHz clock on DCKIP/N. For dual-port operation, provide a DDR clock at one quarter the DAC sample clock frequency (fDCKI = fDAC/4). To use a 2.5GHz sample clock in dual-port mode, provide a 625MHz clock on DCKIP/N. Table 3. DAC Sample Clock, and Divided Clock Output SPI Registers ADDRESS BIT NAME 0x02 0 CK_PD CKP/N Clock Receiver Power Down When CK_PD = 1 DESCRIPTION 1 CK_OK CKP/N Clock Present Indicator. When CK_OK = 1, clock is present at CKP/N pins and fDAC > 50MHz. When CK_OK = 0, DAC output is forced to mid-scale. CK_OK is read only. 4 DCKO_DIS DCKOP/N Output Disable. Set DCKO_DIS = 1 to power down the DCKO LVDS transmitter. For DCKO_DIS = 1, DCKOP/N are high impedance. 5 DCKO_DIV DCKOP/N Divide Select. When DCKO_DIV = 0, fDCKOP/N = fDAC/4. When DCKO_DIV = 1, FDCKOP/N = fDAC/2. 6 DCKO_ISEL DCKOP/N Output Current Select. When DCKO_ISEL = 0, output current is 3.5mA. When DCKO_ISEL = 1, output current is 7mA. 7 DCKO_TRM DCKOP/N Internal Termination On. When DCKO_TRM = 0, there is no internal termination at DCKOP/N. When DCKO_TRM = 1, there is 100Ω between DCKOP and DCKON. Note: Register 0x02 resets to 0x00 (default). 2000f For more information www.linear.com/LTC2000 25 LTC2000 Operation Table 4. LVDS Clock SPI Registers ADDRESS 0x03 BIT NAME DESCRIPTION 0 DCKI_EN DCKIP/N Clock Receiver Enable. DCKI_EN = 1 enables LVDS clock receiver. 1 DCKI_OK DCKIP/N Clock Present Indicator. When DCKI_OK = 1, clock is present at DCKIP/N pins and fDCKIP/N > 25MHz. When DCKI_OK = 0, DAC output is forced to mid-scale unless pattern generator is enabled (PGEN_EN = 1). DCKI_OK is read only. 2 DCKI_Q DCKIP/N Quadrature Phase Select. For DCKI_Q = 0, DCKIP/N should be in phase with DAP/N and DBP/N. Set DCKI_Q = 1 to use DCKI in quadrature with DAP/N and DBP/N. [6:4] DCKI_TADJ DCKIP/N Delay Adjust. Use with DCKI_Q = 0 to adjust delay of DCKIP/N relative to DAP/N and DBP/N. For DCKI_Q = 1, DCKIP/N delay matches DAP/N and DBP/N and is unaffected by DCKI_TADJ. NOMINAL DCKIP/N DELAY DCKI_TADJ DCKI_Q = 1 110 0ps DCKI_Q = 0 230ps 111 0ps 315ps 000 0ps 400ps (Default) 001 0ps 485ps 010 0ps 570ps Note: Register 0x03 resets to 0x00 (default). Use SPI register 0x03 to control the LVDS data clock input (see Table 4). Setting DCKI_EN=1 will enable the LVDS receiver at DCKIP/N. The LTC2000 contains a clock detector which sets DCKI_OK=1 if the data input clock is present and has a frequency greater than 25MHz (fDCKI > 25MHz). When the data clock is not present (DCKI_OK = 0), the DAC output is forced to mid-scale and the internal data path is held at reset. For maximum setup/hold margin, set DCKI_Q = 1 and provide DCKIP/N in quadrature (90° out of phase) with the data on DAP/N and DBP/N (Figure 3 in the Timing Diagrams section). For DCKI_Q = 1, the internal delays on DCKIP/N, DAP/N, and DBP/N are nominally matched. Alternatively, it is possible to leave DCKI_Q = 0 and provide the clock at DCKIP/N in phase with the data on DAP/N and DBP/N (see Figure 2 of the Timing Diagram section). In this case, an internal 400ps delay on DCKIP/N is used to provide setup/hold margin. Note that for DCKI_Q = 0, supply and temperature variation may reduce the setup/ hold margin on the bus by up to 150ps. If desired, users may use the DCKI_TADJ bits in register 0x03 to adjust the 400ps internal DCKIP/N delay with a typical resolution of 85ps. Board trace lengths on DCKIP/N, DAP/N, and DBP/N must be carefully matched to ensure that phase alignment is 26 maintained on all inputs. If desired during development, users may observe the relative timing of neighboring LVDS inputs on the TSTP/N pins (refer to the Measuring LVDS Input Timing Skew section). LVDS Data Input Ports (DAP/N, DBP/N) The LTC2000-16/LTC2000-14/LTC2000-11 allow for DAC Code Data to be applied through one or two parallel 16-/14-/11-bit LVDS ports (DAP/N, DBP/N). Each port can run up to 1.25Gbps using a double-data-rate (DDR) LVDS data clock (DCKIP/N) at frequencies up to 625MHz. The data input format is two’s complement. There are two modes of operation for applying the DAC code to the LTC2000 — single-port mode and dual-port mode. Single port operation uses only LVDS port B (DBP/N) and allows sample rates of up to 1.25Gsps. Dual port operation uses both LVDS ports (DAP/N and DBP/N) and allows sample rates up to 2.5Gsps. Use SPI register 0x04 to control the LVDS data input ports (see Table 5). After the clocks have stabilized and the synchronizer has initialized itself, set DATA_EN = 1 to allow the data from ports A and B to be used to update the DAC code. Clear DATA_EN = 0 to mute the DAC and force the DAC code to mid-scale as desired. 2000f For more information www.linear.com/LTC2000 LTC2000 Operation Table 5. LVDS Data Input SPI Registers ADDRESS BIT 0x04 NAME DESCRIPTION 0 DA_EN DAC Data Port A LVDS Receiver Enable. DA_EN = 1 enables port A receivers. For DA_EN = 0, receivers are powered down and port A data is 0x0000. 1 DB_EN DAC Data Port B LVDS Receiver Enable. DB_EN = 1 enables port B receivers. For DB_EN = 0, receivers are powered down and port B data is 0x0000. 2 DATA_SP DAC Data Single Port Mode Select. DATA_SP = 1 sets single port mode and only port B data is used to update the DAC code. DATA_SP = 0 sets dual-port mode and data from both ports A and B are used. 3 DATA_EN DAC Data Enable. DATA_EN = 0 mutes the DAC output by forcing the DAC code to mid-scale. DATA_EN = 1 allows data from data ports A and B to be used to update the DAC code. Note: Register 0x04 resets to 0x00 (default). For single port operation, set DATA_SP = 1, DA_EN = 0, DB_EN = 1 and provide data to LVDS port B (DBP/N) only. For dual port operation leave DATA_SP = 0, set DA_EN = 1 and DB_EN = 1, and provide interleaved data to LVDS ports A and B (DAP/N, DBP/N). The data on port A will precede the data on port B at the DAC output. Clock Synchronizer Figure 7 shows a simplified block diagram of the internal clock synchronizer. The synchronizer monitors the incoming phase of DCKIP/N using a pair of internal phase comparators. The synchronizer then automatically adjusts DAP/N[15:0] IOUTP 4:1 MUX 50Ω DBP/N[15:0] 50Ω IOUTN SYNC_PS SYNC_PH[7:4] SYNC_PH[3:0] LOGIC 16-BIT DAC DCKIP/N PHASE CMP 0° 90° 180° 270° PHASE CMP ÷4 CKP/N 2000 F07 Figure 7. Simplified Block Diagram — Clock Synchronizer in Dual-Port Mode 2000f For more information www.linear.com/LTC2000 27 LTC2000 Operation the phase of the mux control signals as needed to track any slow drift in the phase between the DCKIP/N and CKP/N due to supply and temperature variation. This ensures that data is sampled correctly by CKP/N. Use SPI registers 0x05 and 0x06 (Table 6) to observe and control the operation of the synchronizer. Upon power-up, apply clocks to CKP/N and DCKIP/N and set DCKI_EN = 1 (register 0x03) to enable the LVDS data clock receiver. Allow at least 1ms after the clocks have stabilized for the synchronizer to initialize, after which the LTC2000 is ready to accept LVDS input data. The synchronizer uses phase comparators to monitor the phase of the data input clock relative to the sample clock divider which controls the mux. The outputs of these phase comparators (SYNC_PH) may be observed in register 0x06. The SYNC_PS bits control the phase of the data multiplexer. For SYNC_MSYN = 0, the SYNC_PS bits are readonly and are automatically adjusted by the synchronizer as needed, based upon the phase of DCKIP/N indicated by SYNC_PH. Users may choose to override the automatic synchronizer by setting SYNC_MSYN = 1 and writing values manually to SYNC_PS to set the phase of the internal multiplexer. When using SYNC_MSYN = 1, users must monitor SYNC_PH and adjust SYNC_PS as needed according to Table 6. For further details see the Synchronizing Multiple LTC2000s section. Table 6. Clock Synchronizer SPI Registers ADDRESS BIT 0x05 [1:0] 2 0x06 [7:0] NAME DESCRIPTION SYNC_PS Synchronizer Phase Select. Selects phase of internal data multiplexer. SYNC_PS is read-only when SYNC_MSYN = 0. SYNC_MSYN Synchronizer Manual Mode Select. When SYNC_MSYN = 0, SYNC_PS is set automatically by the clock synchronizer based upon SYNC_PH. When SYNC_MSYN = 1, SYNC_PS must be set by the user. SYNC_PH Synchronizer Phase Comparator Outputs. SYNC_PH indicates the phase of the LVDS data clock (DCKIP/N) relative to the DAC sample clock (CKP/N) divider used to control the data multiplexer. SYNC_PH is read only. OPTIMAL SYNC_PS SETTING SYNC_PH DUAL-PORT MODE SINGLE-PORT MODE 0x03 10 00 0x04 10 00 0x05 10 00 0x15 10 00 0x25 10 00 0x35 00 10 0x45 00 10 0x55 00 10 0x54 00 10 0x53 00 10 0x52 01 10 0x51 01 10 0x50 01 10 0x40 01 10 0x30 01 10 0x20 11 00 0x10 11 00 0x00 11 00 0x01 11 00 0x02 11 00 Note: Registers 0x05 and 0x06 reset to 0x00 (default). 28 2000f For more information www.linear.com/LTC2000 LTC2000 Operation Minimizing Harmonic Distortion The LTC2000 contains proprietary dynamic linearization circuitry which dramatically reduces 3rd order harmonic distortion in the DAC output. SPI registers 0x07 and 0x08 are used to control these circuits (see Table 7). Optimal performance is normally achieved by setting LIN_VMX and LIN_VMN (register 0x08) to correspond to the maximum and minimum voltages expected at IOUTP/N. At power-on reset the default values are 0b1000 and 0b0000, which are appropriate for IOUTP/N swinging between 500mV and GND. If an application requires a different voltage swing, LIN_VMX and LIN_VMN can be programmed by writing to register 0x08 (see Table 7). For applications in which IOUTP/N swing below GND, use LIN_VMN = 0b0000. In some applications where 2-tone intermodulation distortion (IMD) is a critical specification, it may be desired to vary the amount of 3rd order harmonic correction. For high sampling frequencies (fDAC > 2Gsps), adjusting LIN_GN in register 0x07 (see Table 7) can improve 2-tone intermodulation distortion at the expense of higher 3rd order harmonic distortion. For best IMD performance at high sampling frequencies, users may also choose to disable dynamic linearization by setting LIN_DIS = 1. SFDR and IMD curves in the Typical Performance Characteristics section show more detail regarding this effect. Note that for fDAC < 2Gsps, it is recommended to leave the dynamic linearization enabled. Measuring LVDS Input Timing Skew It is important to ensure that the LVDS inputs (DCKIP/N, DAP/N, DBP/N) are well aligned. Skew between clock and data lines, for example due to board trace length mismatch or output timing mismatch inside the host FPGA or ASIC, will degrade the setup and hold margin of the incoming data. The LTC2000 includes an internal test multiplexer which may be used during development to verify timing alignment by comparing the timing of LVDS inputs one pair at a time through the TSTP/N pins. Use SPI register 0x18 to control this test multiplexer (see Table 8). Be sure TDIO_EN = 0 in register 0x19 and then set LMX_EN = 1 to enable the test multiplexer output. The signal from the LVDS data input will be driven onto TSTP/N by an NMOS differential pair steering a 6.6mA sink current onto an external load. Connect a pair of 50Ω resistors from TSTP/N to 3.3V and observe TSTP/N on a high speed oscilloscope. Apply clocks to CKP/N and DCKIP/N and apply the pattern shown in Figure 8 to port B for single-port mode or ports A and B for dual-port mode. This pattern is designed to simplify comparison of rising-to-rising and falling-tofalling edge timing for each input pair. Set LMX_ADR to select a pair of LVDS inputs for timing comparison. Set LMX_MSEL = 0 to observe the first signal at TSTP/N. Set LMX_MSEL = 1 to observe the second signal with inverted output polarity. For example, to compare DB15P/N to DCKIP/N, first write 0x60 to register 0x18 to set LMX_EN = 1, LMX_ADR = 10000, and LMX_SEL = 0. The signal from DB15P/N will be driven onto TSTP/N. Write 0x61 to register 0x18 to set LMX_SEL = 1 and cause DCKIP/N to appear at TSTP/N with inverted polarity. Record the skew between the two signals and repeat this measurement for each pair of inputs. After all pairs have been measured, add the skews to calculate the total skew from DCKIP/N to each data input (DAP/N, DBP/N). In this way the skew of all LVDS data inputs (DAP/N, DBP/N) relative to DCKIP/N can be accurately measured to within 100ps. Note that due to internal delays inside the test multiplexer, it is only valid to compare timing between neighboring LVDS pairs using the same LMX_ADR setting. Similarly, the multiplexer itself contains up to 400ps of skew between rising and falling edges, so it is only valid to compare the timing of a rising edge at TSTP/N to another rising edge, and a falling edge to another falling edge. Note that Figure 8 shows the suggested input pattern for the LTC2000-16. LTC2000-14 users should apply codes 0x1555 and 0x2AAA, and LTC2000-11 users should apply codes 0x555 and 0x2AA. Also note that for the LTC2000‑14 and LTC2000-11 in dual-port mode, the timing skew of LVDS port A (DAP/N) cannot be compared to that of the LVDS clock (DCKIP/N) and LVDS port B (DBP/N), as there is no single test multiplexer address (LMX_ADR) that enables a timing comparison between signals DA0N/P and DCKIP/N (see Table 8). It is recommended to keep LMX_EN = 0 during normal operation. For more information www.linear.com/LTC2000 2000f 29 LTC2000 Operation Table 7. Dynamic Linearization SPI Registers ADDRESS 0x07 BIT NAME DESCRIPTION 0 LIN_DIS Dynamic Linearization Disable. Disabled when LIN_DIS = 1. [3:1] LIN_GN Dynamic Linearization Gain Select. Changing LIN_GN varies the amount of 3rd order harmonic correction applied to the DAC output. LIN_GN = 000 is normally optimal. LIN_GN 0x08 LINEARIZATION PERCENTAGE 110 50% 111 63% 000 75% (default) 001 88% 010 100% 011 113% 100 125% 101 138% [3:0] LIN_VMX Dynamic Linearization Max IOUTP/N Voltage Select. For optimal 3rd order harmonic performance, set LIN_VMX to correspond to the maximum voltage expected at IOUTP/N. Reset state is LIN_VMX = 1000, which corresponds to 0.51V. LIN_VMX must be greater than LN_VMN. [7:4] LIN_VMN Dynamic Linearization Min IOUTP/N Voltage Select. For optimal 3rd order harmonic performance, set LIN_VMN to correspond to the minimum voltage expected at IOUTP/N. Reset state is LIN_VMN = 0000, which corresponds to 0.0V. LIN_VMN must be less than LN_VMX. LIN_VMX/N MAX/MIN VOLTAGE EXPECTED AT IOUTP/N 0000 0.00V (Default for LIN_VMN) 0001 0.16V 0010 0.19V 0011 0.22V 0100 0.25V 0101 0.31V 0110 0.38V 0111 0.44V 1000 0.51V (Default for LIN_VMX) 1001 0.63V 1010 0.75V 1011 0.87V 1100 1.00V Note: Register 0x07 resets to 0x00 (default). Register 0x08 resets to 0x08 (default). 30 2000f For more information www.linear.com/LTC2000 LTC2000 Operation Table 8. SPI Registers for Measuring LVDS Input Timing Skew ADDRESS BIT NAME DESCRIPTION 0x18 0 LMX_MSEL LVDS Test Mux Select. Set LMX_MSEL high or low to select between a pair of neighboring LVDS signals for comparison at TSTP/N. [5:1] LMX_ADR LVDS Test Mux Address. Use LMX_ADR to select which pair of LVDS signals will be compared at TSTP/N (See Below). 6 LMX_EN LMX_ADR LVDS Test Mux Enable. Set LMX_EN=1 to compare timing of neighboring signals at TSTP/N. Ensure TDIO_EN = 0 when LMX_EN = 1. LTC2000-16 LTC2000-14 LTC2000-11 LMX_MSEL = 0 LMX_MSEL = 1 (INVERTED) LMX_MSEL = 0 LMX_MSEL = 1 (INVERTED) DA15N/P DA12P/N DA13N/P DA9P/N DA10N/P DA[14:6]N/P DA[11:3]P/N DA[12:4]N/P DA[8:0]P/N DA[9:1]N/P LMX_MSEL = 0 LMX_MSEL = 1 (INVERTED) 00000 DA14P/N 00001…01001 DA[13:5]P/N 01010 DA4P/N DA5N/P DA2P/N DA3N/P — DA0N/P 01011 DA3P/N DA4N/P DA1P/N DA2N/P — — 01100 DA2P/N DA3N/P DA0P/N DA1N/P — — 01101 DA1P/N DA2N/P — DA0N/P — — 01110 DA0P/N DA1N/P — — — — 01111 DCKIP/N DA0N/P DCKIP/N — DCKIP/N — 10000 DB15P/N DCKIN/P DB13P/N DCKIN/P DB10P/N DCKIN/P 10001 DB14P/N DB15N/P DB12P/N DB13N/P DB9P/N DB10N/P 10010…11010 DB[13:5]P/N DB[14:6]N/P DB[11:3]P/N DB[12:4]N/P DB[8:0]P/N DB[9:1]N/P 11011 DB4P/N DB5N/P DB2P/N DB3N/P — DB0N/P 11100 DB3P/N DB4N/P DB1P/N DB2N/P — — 11101 DB2P/N DB3N/P DB0P/N DB1N/P — — 11110 DB1P/N DB2N/P — DB0N/P — — 11111 DB0P/N DB1N/P — — — — Note: Register 0x18 resets to 0x00 (default). DAP/N[15:0] 0xAAAA 0x5555 0xAAAA 0x5555 DBP/N[15:0] 0x5555 0xAAAA 0x5555 0xAAAA DCKI 2000 F08 Figure 8. Sample Pattern for Measuring LVDS Input Timing Skew (LTC2000-16) 2000f For more information www.linear.com/LTC2000 31 LTC2000 Operation Measuring Internal Junction Temperature (TJ) To use this feature, do the following: The LTC2000 test multiplexer may also be used to connect internal junction temperature measurment diodes to the TSTP/N pins. Ensure LMX_EN = 0 (register address 0x18) and use SPI register 0x19 to set TDIO_EN = 1 to enable this function (Table 9). There are two methods the user can choose from to measure internal junction temperature (TJ). For TDIO_SEL = 0, an unbiased NPN transistor is diode-connected between the TSTP/N pins. This diode is suitable for use with external temperature sensors such as the LTC2991 or LTC2997. 1.Set DCKO_DIV = 0 in register 0x02, DATA_SP = 0 and DATA_EN = 0 in register 0x04, and PGEN_EN = 0 in register 0x1E. If such a temperature sensor is not available, set TDIO_SEL = 1 to directly observe a temperature dependent voltage between TSTP and TSTN. The typical expected voltage at TSTP is VTSTP = 2.02V – 5.5mV/°C • (TJ – 25°C). The junction temperature can be calculated as TJ = 25°C + (2.02V – VTSTP)/(5.5mV/°C). For best accuracy with TDIO_SEL = 1, use TSTN to sense GND at the bottom of the diode and calibrate the voltage at a known temperature. Typical uncalibrated accuracy is ±5°C. Pattern Generator A 64 sample deep pattern generator is included in the LTC2000 to simplify system development and debug. The pattern generator allows the user to send a repeating 64 sample pattern to the DAC, completely independent of the presence or absence of valid signals on DCKIP/N, DAP/N, and DBP/N. Table 9. Internal Junction Temperature SPI Registers ADDRESS 0x19 BIT 0 1 2.Write 128 bytes of pattern data to address 0x1F (PGEN_D) to fill the pattern generator with 64 samples. Data is written MSB first, and will be applied to the DAC in the order written. Data may be written one byte at a time or in larger multi-byte words. For the LTC2000‑14 and LTC2000-11, data should be left justified with zeros filling the remaining two (LTC2000-14) or five (LTC2000-11) bits. 3.Set PGEN_EN = 1 to start the pattern generator. 4.Wait at least 1ms to ensure that the synchronizer has initialized. 5.Set DATA_EN = 1 in register 0x04. The DAC will then begin to output the 64 sample pattern. The pattern generator will send the repeating 64 sample pattern to the DAC until the user writes PGEN_EN = 0 or DATA_EN = 0. To read back the pattern, set DATA_EN = 0 and PGEN_EN = 0 and then read 128 bytes from address 0x1F. Note that the starting point of the pattern may have changed while the pattern was running. To modify the pattern, set DATA_EN = 0 and PGEN_EN = 0 and write a new 64 sample pattern to address 0x1F. Ensure PGEN_EN = 0 when reading or writing to address 0x1F, and always read or write an entire 64 sample pattern prior to setting PGEN_EN = 1. See Table 10. NAME TDIO_EN DESCRIPTION TSTP/N Junction Temperature Diode Enable. Set TDIO_EN = 1 to measure internal junction temperature (TJ) at TSTP/N. Ensure LMX_EN = 0 when TDIO_EN = 1. TDIO_SEL Selects which internal temperature diode is observable at TSTP/N. For TDIO_SEL = 1, the typical voltage at TSTP with respect to TSTN is VTSTP = 2.02V – 5.5mV/°C • (TJ – 25ºC). Junction temperature can be calculated as TJ = 25°C + (2.02V – VTSTP)/(5.5mV/°C). Typical accuracy is ±5°C. For TDIO_SEL = 0, an unbiased diode is connected b/w TSTP/N for use with external temperature sensors. Note: Register 0x19 resets to 0x00 (default). Table 10 – Pattern Generator SPI Registers ADDRESS 0x1E NAME DESCRIPTION PGEN_EN Pattern Generator Enable. Set PGEN_EN = 1 to use the internal 64 sample pattern generator to provide data to the DAC. Set DATA_SP = 0, DCKO_DIV = 0, and DATA_EN = 1 when PGEN_EN = 1. 0x1F [7:0] PGEN_D Pattern Generator Data. Write 128 bytes of data to this address to fill the pattern generator with 64 samples. Data is written MSB first. Reading this location causes the pattern generator data to be shifted out through SDO. Ensure PGEN_EN = 0 when reading or writing to address 0x1F. Read or write an even number of bytes to address 0x1F prior to setting PGEN_EN = 1 to avoid corrupting the data inside the pattern generator. Note: Registers 0x1E and 0x1F reset to 0x00 (default). 2000f 32 BIT 0 For more information www.linear.com/LTC2000 LTC2000 SPI Register Summary Table 11. SPI Register List RESET VALUE R/W Software Reset. SW_RST = 1 resets all registers. 0 R/W DAC_PD DAC Power Down. DAC_PD = 1 to power down DAC core. 0 R/W FULL_PD Full Power Down. FULL_PD = 1 to power down LTC2000. 0 R/W 00-16b 01-14b 11-11b R CKP/N Clock Receiver Power Down. CK_PD = 1 disables 0 R/W CKP/N Clock Present Indicator. CK_OK = 1 clock present 0 R ADDRESS BIT NAME 0x00 [7:0] Reserved Reserved 0x01 0 SW_RST 1 2 3 Reserved Reserved [5:4] DAC_RES DAC Resolution Indicator. DAC_RES = 00 for LTC2000-16. DAC_RES = 01 for LTC2000-14. DAC_RES = 11 for LTC2000-11. Note that for PD = GND or FULL_PD = 1, DAC_RES = 00. DAC_RES is read only. [7:6] Reserved Reserved 0 CK_PD 0x02 0x03 0x04 0x05 DESCRIPTION 1 CK_OK [3:2] Reserved Reserved 4 DCKO_DIS DCKOP/N Output Disable. DCKO_DIS = 1 disables 0 R/W 5 DCKO_DIV DCKOP/N Divide Select. (0 = fDAC/4, 1 = fDAC/2). 0 R/W 6 DCKO_ISEL DCKOP/N Output Current Select. (0=3.5mA, 1 = 7mA) 0 R/W 7 DCKO_TRM DCKOP/N Internal Termination On. DCKO_TRM = 1 enables internal 100Ω termination 0 R/W 0 DCKI_EN DCKIP/N Clock Receiver Enable. DCKI_EN = 1 enables. 0 R/W 1 DCKI_OK DCKIP/N Clock Present Indicator. DCKI_OK = 1 indicates clock present 0 R 2 DCKI_Q DCKIP/N Quadrature Phase Select. (0 = In Phase, 1 = Quadrature) 0 R/W 3 Reserved Reserved [6:4] DCKI_TADJ 000 R/W 7 Reserved 0 DA_EN Port A LVDS Receiver Enable. DA_EN = 1 to enable 0 R/W 1 DB_EN Port B LVDS Receiver Enable. DB_EN = 1 to enable 0 R/W 2 DATA_SP Port Mode Select. (0 = Dual port, 1 = Single port) 0 R/W 0 R/W 00 R/W 0 R/W DCKIP/N Delay Adjust. (See Table 4) Reserved 3 DATA_EN DAC Data Enable. DATA_EN = 0 forces DAC output to mid-scale. [7:4] Reserved Reserved [1:0] SYNC_PS Clock Synchronizer Phase Select. 2 SYNC_MSYN Clock Synchronizer Manual Mode Select. SYNC_MSYN = 0: SYNC_PS is set automatically. SYNC_MSYN = 1: SYNC_PS is set by the user. [7:3] Reserved Reserved 0x06 [7:0] SYNC_PH Clock Phase Comparator Outputs. (See Table 6) 0x07 0 LIN_DIS Dynamic Linearization Disable. LIN_DIS = 1 disables. [3:1] LIN_GN Dynamic Linearization Gain Select. (See Table 7) [7:4] Reserved Reserved [3:0] LIN_VMX [7:4] LIN_VMN 0x08 0x00 R 0 R/W 000 R/W Dynamic Linearization Max IOUTP/N Voltage Select. (See Table 7) 1000 R/W Dynamic Linearization Min IOUTP/N Voltage Select. (See Table 7) 0000 R/W 2000f For more information www.linear.com/LTC2000 33 LTC2000 SPI Register Summary Table 11. SPI Register List (cont) ADDRESS 0x09 BIT NAME DESCRIPTION RESET VALUE R/W 0x00 R/W 0 R/W 0x00 R/W [5:0] GAIN_ADJ DAC Gain Adjustment. (See Table 2) [7:6] Reserved Reserved 0x0A Thru 0x17 [7:0] Reserved Reserved 0x18 0 LMX_MSEL LVDS Test Mux Select. (See Table 8) [5:1] LMX_ADR LVDS Test Mux Address Select. (See Table 8) 6 LMX_EN LVDS Test Mux Enable. LMX_EN = 1 enables LVDS text mux. Ensure TDIO_EN = 0 when LMX_EN = 1. 7 Reserved Reserved 0 TDIO_EN TSTP/N Junction Temperature Diode Enable. TDIO_EN = 1 enables temperature (TJ) measurement. Ensure LMX_EN = 0 when TDIO_EN = 1. 0 R/W 1 TDIO_SEL Junction Temperature Select. TDIO_SEL = 0 uses a diode-connected unbiased NPN transistor. TDIO_SEL = 1 outputs a voltage to calculate internal die temperature using: TJ = 25°C + (2.02V – VTSTP)/(5.5mV/°C). (See Table 9) 0 R/W [7:2] Reserved Reserved 0x1A Thru 0x1D [7:0] Reserved Reserved 0x1E 0 PGEN_EN Pattern Generator Enable. PGEN_EN = 1 enables. 0 R/W 0x00 R/W 0x19 [7:1] Reserved Reserved 0x1F [7:0] PGEN_D Pattern Generator Data. 0x20 Thru 0x7F [7:0] Reserved Reserved Applications Information Sample Start-Up Sequence The following is an example of a common start-up sequence. 1. Apply valid supply voltages to AVDD33, DVDD33, AVDD18, DVDD18 and SVDD. 2. Write 0x01 to address 0x01 to perform a software reset. 3. Apply a clock to CKP/N at the desired fDAC frequency. The LTC2000 will generate a clock at DCKOP/N at fDAC/4. 4. Apply a clock to DCKIP/N at fDAC/4 for dual-port mode or fDAC/2 for single-port mode. 6. Write to address 0x03 to enable the DCKIP/N LVDS receiver. Set address 0x03 to 0x01 if the LVDS clock (DCKI) and data (DA, DB) are in phase with each other. Set address 0x03 to 0x05 if they are in quadrature. 7. Write 0x06 to address 0x04 for dual-port mode, or write 0x04 to address 0x04 for single-port mode to enable the DAP/N and DBP/N LVDS receivers. 8. Wait at least 1ms for the synchronizer to finish initializing. 9. Write 0x0B to address 0x04 for dual-port mode, or write 0x0E to address 0x04 for single-port mode to set DATA_EN = 1. 5. Apply zeroes to ports A and B (DAP/N, DBP/N) for dual-port mode, or only to port B for single-port mode. 34 For more information www.linear.com/LTC2000 2000f LTC2000 Applications Information 10.)Apply desired data pattern to ports A and B (DAP/N, DBP/N) for dual-port mode, or only to port B for single-port mode. Port A samples will precede port B samples at the DAC output when using dual-port mode. For any output configuration, any imbalances in the output impedance between the IOUTP and IOUTN pins results in asymmetrical signal swings that lead to distortion (mostly even order). Careful consideration is needed to select the best output configuration for a given application. Output Configurations Generating the DAC Sample Clock The LTC2000’s complementary current outputs (IOUTP/N) source current into an external load referenced to GND. Output load configuration, component selection, and layout are critical to the performance of the LTC2000. For best AC performance, the output stages should be configured for differential (or balanced) operation. For best AC performance, it is important that the DAC sample clock waveforms be clean, with low phase noise and good jitter performance, as the phase noise and spurious content of the clock source will appear directly in the DAC output spectrum. A differential resistor loaded output is a very simple output stage. Well matched resistors are connected between GND and IOUTP/N, with the resistance values setting both the output swing and non-zero output common-mode voltage (Figure 9). While it is economical, this type of output stage can drive only differential loads with impedance levels and amplitudes appropriate for the DAC outputs. Differential transformer-coupled output configurations usually give the best AC performance and provide excellent rejection of common mode distortion and noise over a broad frequency range. Figure 10 shows a transformer output configuration that uses a Mini-Circuits TC1-1-13M and a JTX-2-10T RF transformer for differential to singleended conversion. LTC2000 A differential clock should be AC coupled onto the CKP/N pins, since the DC bias point of CKP/N is set internally to 1V through a 5kΩ impedance. Figure 11 shows the DAC sample clock receiver input and common-mode voltage control. While the differential input voltage range of the clock receiver spans from ±300mV to ±1.8V, a signal with the highest possible slew rate and amplitude and a balanced duty cycle is recommended. Traces that carry the differential clock signal need to have accurately controlled impedance and accurate termination as close to the CKP/N pins of the LTC2000 as possible. There are several ways to generate the DAC sample clock. For lab evaluation and testing, a high quality RF signal generator can provide a clean high frequency sine wave that is converted to the DAC sample clock with a 1:1 RF transformer or balun (see Figure 12). IOUTP LTC2000 AVDD18 IOUTN R R CKP 2000 F09 1V Figure 9. Differential Resistor Output Load IOUTP LTC2000 • 5k CKN MINI-CIRCUITS TC1-1-13M MINI-CIRCUITS JTX-2-10T 5k • • • GND 2000 F11 IOUTN 2000 F10 Figure 10. Transformer-Based Output Configuration for Differential to Single-Ended Conversion Figure 11. DAC Sample Clock Receiver For more information www.linear.com/LTC2000 2000f 35 LTC2000 Applications Information 50Ω 1nF + RF SIGNAL GENERATOR the default behavior is for the output of DAC Y to update with sample N one cycle earlier than the output of DAC X. It is possible to correct this misalignment and synchronize DACs X and Y by adjusting the clock synchronizer settings to subtract one cycle of latency from DAC X, as shown in the adjusted waveform at the bottom of Figure 15a. See the Clock Synchronizer section and Figure 7 for more details on the operation of the clock synchronizer. MINI-CIRCUITS TC1-1-13M • • CKP 50Ω + 1nF 50Ω LTC2000 + 100pF CKN LTC2000 F12 Figure 12. DAC Sample Clock Generation with an RF Signal Generator and a 1:1 Balun A more integrated clock source is one based on a low phase noise, low jitter PLL. Figure 13 shows how the DAC sample clock can be generated from the LTC6946, a high performance PLL with an internal VCO that can provide output frequencies from 0.37GHz to 5.7GHz. See the LTC6946 data sheet for details. Synchronizing Multiple LTC2000s in Dual-Port Mode In some applications, it is necessary to synchronize multiple LTC2000s to each other such that related samples arrive at all DAC outputs simultaneously. Figures 14 and 15a show a block diagram and sample waveforms for such a system in which two DACs (X and Y) are to be synchronized in dual-port mode. Note that in this example a small timing skew between the two data signals at the DCKIP/N pins of DACs X and Y has caused the DCKIP/N rising edges to arrive on opposite sides of a DAC sample clock (CKP/N) rising edge, and thus within different CKP/N clock cycles. As a result LOOP FILTER CP 2700pF RZ 453Ω CI 0.022µF LF(s) 25 CP ICP = 11.2mA VRF+ f PFD KPFD In order to synchronize multiple DACs as shown in Figures 14 and 15a, distribute the DAC sample clock carefully with matched delays so that it arrives at the CKP/N pins of all DACs simultaneously. Any remaining timing mismatch between sample clocks will appear directly as mismatch in the DAC output timing. Ensure that the timing mismatch between LVDS data clock signals at the DCKIP/N pins of all DACs is less than 0.4 cycles of the DAC sample clock, minus any timing mismatch between the DAC sample clocks. Be sure to maintain sufficient matching between the timing of the LVDS data inputs (DAP/N, DBP/N) and DCKIP/N for each DAC to meet the setup and hold time specifications (t11, t12) in the Timing Characteristics section. For example, let us consider a system using multiple DACs at 2.5Gsps in which the sample clock is designed to arrive at the CKP/N pins of all DACs within 30ps of one another. The sample clock period is 400ps, so the maximum allowable timing mismatch between the data clock signals at the DCKIP/N pins of all DACs will be (0.4 • 400ps) – 30ps = 130ps. For a system using multiple DACs at 1.25Gsps, the allowable mismatch between DCKIP/N pins will be (0.4 • 800ps) – 30ps = 290ps. In both cases, once the DACs LTC6946 REF± R_DIV (fREF) ÷R = 10 L1 68nH fREF* L2 68nH 100pF 50Ω ÷N = 250 15 TUNE O_DIV f KVCO VCO ÷O = 1 CKP + N_DIV RF± (fRF) RF+ RF– 100pF 50Ω + *CRYSTEK CVHD-950-100.000 100MHz OSCILLATOR 100pF + LTC2000 CKN 2000 F13 Figure 13. DAC Sample Clock Generation with the LTC6946 36 2000f For more information www.linear.com/LTC2000 LTC2000 Applications Information MATCHED DELAYS CLOCK SOURCE MATCHED DELAYS CKP/N DCKIP/N DAC X LTC2000 DAP/N LVDS CLK LVDS DATA 2000 F14 DBP/N FPGA CKP/N DCKIP/N DAC Y LTC2000 DAP/N LVDS CLK LVDS DATA DBP/N Figure 14. System with Multiple LTC2000 DACs Synchronized CKP/N DAP/N[15:0] N N+2 N+4 N+6 N+8 N+10 DBP/N[15:0] N+1 N+3 N+5 N+7 N+9 N+11 DAC X DCKIP/N 0.9 CYCLES DAC Y DCKIP/N 0.1 CYCLES 10 CYCLES DAC X N IOUTP/N 9 CYCLES DAC X IOUTP/N (ADJUSTED) N N+1 10 CYCLES DAC Y N IOUTP/N N+1 2000 F15a Figure 15a. Sample Waveforms — Synchronizing Multiple LTC2000s in Dual Port Mode are synchronized the mismatch in the DAC output timing will be limited to 30ps. Once all the DAC sample clocks and LVDS data clocks are aligned, determine whether any DACs are being updated one cycle late (such as DAC X in Figure 15a) by determining whether DCKIP/N is arriving at the DACs within the same CKP/N clock cycle. To do this in dual-port mode, first use the phase comparator outputs SYNC_PH and Table 12 to determine the delay from the DCKIP/N rising edge to the next CKP/N rising edge for each DAC (measured in sample clock cycles). Recall that the DCKIP/N timing mismatch must be kept below 0.4 cycles of the sample clock. If DCKIP/N arrives at both DACs within the same sample clock cycle, the difference in DCKIP/N to CKP/N delays indicated by SYNC_PH will equal the actual DCKIP/N timing mismatch, and thus will be less than 0.4 cycles. If DCKIP/N arrives at the DACs within different cycles, as in Figure 15a, the difference in the delays indicated by SYNC_PH will equal 1 cycle minus the actual DCKIP/N timing mismatch, and thus will be greater than 0.4 cycles. Thus if the difference between the delays indicated by SYNC_PH is greater than 2000f For more information www.linear.com/LTC2000 37 LTC2000 Applications Information 0.4 cycles, the DCKIP/N rising edges are arriving in different sample clock cycles. For the example in Figure 15a, we might read 0x25 for SYNC_PH on DAC X and 0x52 on DAC Y. Table 12 tells us that the DCKIP/N to CKP/N delay is greater than 0.8 cycles for DAC X and less than 0.2 cycles for DAC Y, and thus the difference between them is at least 0.6 cycles. We conclude that the DCKIP/N rising edge of DAC X must fall within a later sample clock cycle than that of DAC Y, and thus that DAC X is being updated one cycle later than DAC Y. To correct any such misalignment and synchronize the DACs, consult Table 12 and adjust the SYNC_PS settings for those DACs which are being updated one cycle late (DAC X in the above example) by setting the synchronizer to manual mode (SYNC_MSYN = 1) and overwriting the SYNC_PS value. In this example, reading register 0x06 of DAC X shows SYNC_PH = 0x25 and that the SYNC_PS setting needs to change from the default (10) to the desired adjusted value (00), subtracting one cycle from the latency of DAC X (refer to Table 12). Write 0x04 to register 0x05 of DAC X to set SYNC_MSYN = 1 and SYNC_PS = 00. The outputs of DAC X should now align with DAC Y as shown in Figure 15a. See Table 6 for details regarding the synchronizer registers 0x05 and 0x06. Sample verilog code implementing the synchronization of multiple LTC2000s using Tables 12 and 13 can be found at: http://www.linear.com/docs/44845 Synchronizing Multiple LTC2000s in Single-Port Mode Figure 15b shows sample waveforms for synchronizing two LTC2000s in single port mode. Synchronizing multiple LTC2000s in single port mode is essentially the same Table 12. Adjusting Latency in Dual-Port Mode PHASE COMPARATOR OUTPUTS SYNC_PH (REG 0x06) SYNC_PS SETTING DELAY FROM DCKIP/N RISING EDGE TO NEXT CKP/N RISING EDGE (CKP/N CYCLES) (DEFAULT) (ADJUSTED TO REDUCE LATENCY BY 1 CYCLE)* 0x03 0 to 0.2 10 N/A 0x04 0.2 to 0.4 10 N/A 0x05 0.4 to 0.6 10 N/A 0x15 0.6 to 0.8 10 00 0x25 0.8 to 1.0 10 00 0x35 0 to 0.2 00 N/A 0x45 0.2 to 0.4 00 N/A 0x55 0.4 to 0.6 00 N/A 0x54 0.6 to 0.8 00 01 0x53 0.8 to 1.0 00 01 0x52 0 to 0.2 01 N/A 0x51 0.2 to 0.4 01 N/A 0x50 0.4 to 0.6 01 N/A 0x40 0.6 to 0.8 01 11 0x30 0.8 to 1.0 01 11 0x20 0 to 0.2 11 N/A 0x10 0.2 to 0.4 11 N/A 0x00 0.4 to 0.6 11 N/A 0x01 0.6 to 0.8 11 10 0x02 0.8 to 1.0 11 10 *N/A indicate SYNC_PH values that should not occur if the timing mismatch requirements described above are met. If such a case occurs, keep SYNC_PS as the default value. 38 2000f For more information www.linear.com/LTC2000 LTC2000 Applications Information CKP/N DBP/N[15:0] N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 DAC X DCKIP/N 0.8 CYCLES DAC Y DCKIP/N 0.1 CYCLES 7.5 CYCLES DAC X N N+1 N N+1 N+2 N N+1 IOUTP/N 6.5 CYCLES DAC X IOUTP/N (ADJUSTED) 7.5 CYCLES DAC Y IOUTP/N N+2 2000 F15b Figure 15b. Sample Waveforms — Synchronizing Multiple LTC2000s in Single Port Mode procedure as when operating in dual port mode—DAC sample clocks must all be aligned to arrive at the CKP/N pins of all DACs simultaneously and timing mismatch between LVDS data clock signals at the DCKIP/N pins of all DACs must be less than 0.4 cycles of the DAC sample clock, minus any timing mismatch between the DAC sample clocks. To determine whether any DACs are being updated one cycle late in single port mode, first use the phase comparator outputs SYNC_PH and Table 13 to determine the delay from the DCKIP/N rising edge to the next CKP/N falling edge (as opposed to rising edge in dual port mode) for each DAC. If the difference between the delays indicated by SYNC_PH is greater than 0.4 cycles, the DCKIP/N rising edges are arriving in different sample clock cycles. For the example in Figure 15b, we might read 0x15 for SYNC_PH on DAC X and 0x20 on DAC Y. Table 13 shows that the DCKIP/N to CKP/N delay is greater than 0.8 cycles for DAC X and less than 0.1 cycles for DAC Y, and thus the difference between them is at least 0.7 cycles. This indicates that DAC X is being updated one cycle later than DAC Y. Consult Table 13 and use the same procedure described above in the dual-port mode case to correct the SYNC_PS settings for those DACs that are updating one cycle late. In this single port example, writing 0x06 to register 0x05 of DAC X would set SYNC_MSYN = 1 and SYNC_PS = 10, reducing the latency of DAC X by one cycle and aligning its output with DAC Y, as shown in Figure 15b. Note that variations in system temperature or supply voltage may cause the phase of the data clock (DCKIP/N) and sample clock (CKP/N) to vary with time. When using the LTC2000 with SYNC_MSYN = 1, it is recommended that users monitor SYNC_PH and adjust SYNC_PS using Tables 12 or 13 as needed to maintain proper alignment. The synchronization procedures described above also work for systems with more than two DACs. Simply determine the minimum DCKIP/N to CKP/N delay of all DACs by reading SYNC_PH, and then adjust the SYNC_PS settings to subtract one cycle of latency to those DACs whose DCKIP/N to CKP/N delays are at least 0.4 cycles more than the minimum. Sample verilog code implementing the synchronization of multiple LTC2000s using Tables 12 and 13 can be found at: http://www.linear.com/docs/44845 2000f For more information www.linear.com/LTC2000 39 LTC2000 Applications Information Table 13. Adjusting Latency in Single-Port Mode SYNC_PS SETTING PHASE COMPARATOR OUTPUTS SYNC_PH (REG 0x06) DELAY FROM DCKIP/N RISING EDGE TO NEXT CKP/N FALLING EDGE (CKP/N CYCLES) (DEFAULT) (ADJUSTED TO REDUCE LATENCY BY 1 CYCLE)* 0x03 0.5 to 0.6 00 N/A 0x04 0.6 to 0.7 00 10 0x05 0.7 to 0.8 00 10 0x15 0.8 to 0.9 00 10 0x25 0.9 to 1.0 00 10 0x35 0 to 0.1 10 N/A 0x45 0.1 to 0.2 10 N/A 0x55 0.2 to 0.3 10 N/A 0x54 0.3 to 0.4 10 N/A 0x53 0.4 to 0.5 10 N/A 0x52 0.5 to 0.6 10 N/A 0x51 0.6 to 0.7 10 00 0x50 0.7 to 0.8 10 00 0x40 0.8 to 0.9 10 00 0x30 0.9 to 1.0 10 00 0x20 0 to 0.1 00 N/A 0x10 0.1 to 0.2 00 N/A 0x00 0.2 to 0.3 00 N/A 0x01 0.3 to 0.4 00 N/A 0x02 0.4 to 0.5 00 N/A *N/A indicate SYNC_PH values that should not occur if the timing mismatch requirements described above are met. If such a case occurs, keep SYNC_PS as the default value. PCB Layout Considerations The close proximity of high frequency digital data lines and high dynamic range, wideband analog signals make clean printed circuit board design and layout an absolute necessity. Figures 16 and 17 show a schematic and PCB layers for an evaluation circuit for the LTC2000. A single, solid ground plane should be used, while separate supply planes for AVDD18, DVDD18, AVDD33, and DVDD33 should be kept all the way to the individual supply or LDO. All LVDS input (DCKIP/N, DAP/N, DBP/N) board traces must be carefully matched to ensure proper phase alignment. These LVDS inputs should be kept far away from both the IOUTP/N and CKP/N traces to avoid any data dependent coupling into the analog output and DAC sample clock. 40 The CKP/N traces should be routed either over the analog ground plane or over their own section on the ground plane. These traces also need to have accurately controlled impedance and should be well terminated near the LTC2000. The IOUTP/N traces should also be carefully matched to each other, routed over the ground plane, away from the LVDS inputs and CKP/N signals. Bypass capacitors are required on AVDD18, DVDD18, AVDD33, and DVDD33, and should all be connected to the analog ground plane. 2.2µF ceramic capacitors with low ESR are recommended to be placed close to the LTC2000 with minimum trace lengths. A sample PCB layout and schematic can be found below. 2000f For more information www.linear.com/LTC2000 LTC2000 Applications Information 3.3V MATCHED LVDS DATA AND CLOCK LINES FROM FPGA CLOCK SOURCE L6 1nH C66 1pF C47 10pF T1 ANAREN B0430J50100AHF 6 1 GND 2 3 IN GND 5 4 C41 100pF SPI PORTS DAP[15:0] DAN[15:0] J10 DCKIP J8 DCKIN DBP[15:0] DBN[15:0] K8 DCKOP K7 DCKON S1 PD S2 LTC2000 CS S3 SDO S4 SDI S5 SCK R29 50Ω C42 100pF C43 0.01µF R26 50Ω CKP 47µF SVDD AVDD33 DVDD33 AVDD18 DVDD18 1.8V 47µF R4 TSTP R3 TSTN H1 IOUTP IOUTN J1 M1 REFIO M2 FSADJ CKN GND R40 50Ω R47 50Ω R46 50Ω R48 50Ω 2000 F16 R45 500Ω C40 10µF Figure 16 Layer 1 Layer 2 2000f For more information www.linear.com/LTC2000 41 LTC2000 Applications Information Layer 3 42 Layer 4 2000f For more information www.linear.com/LTC2000 LTC2000 Applications Information Layer 5 Layer 6 2000f For more information www.linear.com/LTC2000 43 LTC2000 Applications Information Layer 7 44 Layer 8 2000f For more information www.linear.com/LTC2000 LTC2000 Pin Locations (LTC2000-16) LTC2000-16 BGA Pinout PIN ID FUNCTION PIN ID FUNCTION A1 GND B1 GND A2 CKN B2 GND A3 CKP B3 GND A4 GND B4 GND A5 DVDD18 B5 A6 GND A7 DAN15 A8 DAP15 PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION C1 AVDD18 D1 AVDD18 E1 AVDD18 F1 GND C2 AVDD18 D2 AVDD18 E2 AVDD18 F2 GND C3 AVDD18 D3 AVDD18 E3 DVDD18 F3 GND C4 AVDD18 D4 DVDD18 E4 DVDD18 F4 GND DVDD18 C5 DVDD18 D5 DVDD18 E5 DVDD18 F5 GND B6 GND C6 GND D6 GND E6 GND F6 GND B7 DAN14 C7 DAN13 D7 DAN12 E7 DAN11 F7 DAN10 B8 DAP14 C8 DAP13 D8 DAP12 E8 DAP11 F8 DAP10 A9 DBN15 B9 DBN14 C9 DBN13 D9 DBN12 E9 DBN11 F9 DBN10 A10 DBP15 B10 DBP14 C10 DBP13 D10 DBP12 E10 DBP11 F10 DBP10 PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION G1 GND H1 IOUTP J1 IOUTN K1 GND L1 GND M1 REFIO G2 GND H2 GND J2 GND K2 GND L2 GND M2 FSADJ G3 GND H3 GND J3 GND K3 GND L3 GND M3 GND G4 GND H4 GND J4 GND K4 GND L4 GND M4 AVDD33 G5 GND H5 GND J5 GND K5 GND L5 GND M5 DVDD33 G6 GND H6 GND J6 GND K6 GND L6 GND M6 GND G7 DAN9 H7 DAN8 J7 DCKON K7 DAN7 L7 DAN6 M7 DAN5 G8 DAP9 H8 DAP8 J8 DCKOP K8 DAP7 L8 DAP6 M8 DAP5 G9 DBN9 H9 DBN8 J9 DCKIN K9 DBN7 L9 DBN6 M9 DBN5 G10 DBP9 H10 DBP8 J10 DCKIP K10 DBP7 L10 DBP6 M10 DBP5 PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION N1 GND P1 AVDD33 Q1 AVDD33 R1 GND S1 PD N2 GND P2 AVDD33 Q2 AVDD33 R2 GND S2 CS N3 GND P3 AVDD33 Q3 AVDD33 R3 TSTN S3 SDO N4 AVDD33 P4 AVDD33 Q4 AVDD33 R4 TSTP S4 SDI N5 DVDD33 P5 DVDD33 Q5 DVDD33 R5 GND S5 SCK N6 GND P6 GND Q6 GND R6 GND S6 SVDD N7 DAN4 P7 DAN3 Q7 DAN2 R7 DAN1 S7 DAN0 N8 DAP4 P8 DAP3 Q8 DAP2 R8 DAP1 S8 DAP0 N9 DBN4 P9 DBN3 Q9 DBN2 R9 DBN1 S9 DBN0 N10 DBP4 P10 DBP3 Q10 DBP2 R10 DBP1 S10 DBPO 2000f For more information www.linear.com/LTC2000 45 LTC2000 Pin Locations (LTC2000-16) 1 2 3 CKN CKP TOP VIEW 4 5 6 7 8 9 10 A B GND C AVDD18 D GND DVDD18 E F GND G H J K IOUTP IOUTN M REFIO FSADJ GND DVDD33 P AVDD33 Q GND R GND S PD 46 CS TSTN TSTP SDO SDI DBN15 DBP15 DAN14 DAP14 DBN14 DBP14 DAN13 DAP13 DBN13 DBP13 DAN12 DAP12 DBN12 DBP12 DAN11 DAP11 DBN11 DBP11 DAN10 DAP10 DBN10 DBP10 DAN9 DAP9 DBN9 DBP9 DAN8 DAP8 DBN8 DBP8 DCKIN DCKIP DCKON DCKOP GND L N DAN15 DAP15 SCK SVDD DAN7 DAP7 DBN7 DBP7 DAN6 DAP6 DBN6 DBP6 DAN5 DAP5 DBN5 DBP5 DAN4 DAP4 DBN4 DBP4 DAN3 DAP3 DBN3 DBP3 DAN2 DAP2 DBN2 DBP2 DAN1 DAP1 DBN1 DBP1 DAN0 DAP0 DBN0 DBP0 2000f For more information www.linear.com/LTC2000 LTC2000 PIn Locations (LTC2000-14) LTC2000-14 BGA Pinout PIN ID FUNCTION PIN ID FUNCTION A1 GND B1 GND A2 CKN B2 GND A3 CKP B3 GND A4 GND B4 GND A5 DVDD18 B5 A6 GND A7 DAN13 A8 DAP13 PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION C1 AVDD18 D1 AVDD18 E1 AVDD18 F1 GND C2 AVDD18 D2 AVDD18 E2 AVDD18 F2 GND C3 AVDD18 D3 AVDD18 E3 DVDD18 F3 GND C4 AVDD18 D4 DVDD18 E4 DVDD18 F4 GND DVDD18 C5 DVDD18 D5 DVDD18 E5 DVDD18 F5 GND B6 GND C6 GND D6 GND E6 GND F6 GND B7 DAN12 C7 DAN11 D7 DAN10 E7 DAN9 F7 DAN8 B8 DAP12 C8 DAP11 D8 DAP10 E8 DAP9 F8 DAP8 A9 DBN13 B9 DBN12 C9 DBN11 D9 DBN10 E9 DBN9 F9 DBN8 A10 DBP13 B10 DBP12 C10 DBP11 D10 DBP10 E10 DBP9 F10 DBP8 PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION G1 GND H1 IOUTP J1 IOUTN K1 GND L1 GND M1 REFIO G2 GND H2 GND J2 GND K2 GND L2 GND M2 FSADJ G3 GND H3 GND J3 GND K3 GND L3 GND M3 GND G4 GND H4 GND J4 GND K4 GND L4 GND M4 AVDD33 G5 GND H5 GND J5 GND K5 GND L5 GND M5 DVDD33 G6 GND H6 GND J6 GND K6 GND L6 GND M6 GND G7 DAN7 H7 DAN6 J7 DCKON K7 DAN5 L7 DAN4 M7 DAN3 G8 DAP7 H8 DAP6 J8 DCKOP K8 DAP5 L8 DAP4 M8 DAP3 G9 DBN7 H9 DBN6 J9 DCKIN K9 DBN5 L9 DBN4 M9 DBN3 G10 DBP7 H10 DBP6 J10 DCKIP K10 DBP5 L10 DBP4 M10 DBP3 PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION N1 GND P1 AVDD33 Q1 AVDD33 R1 GND S1 PD N2 GND P2 AVDD33 Q2 AVDD33 R2 GND S2 CS N3 GND P3 AVDD33 Q3 AVDD33 R3 TSTN S3 SDO N4 AVDD33 P4 AVDD33 Q4 AVDD33 R4 TSTP S4 SDI N5 DVDD33 P5 DVDD33 Q5 DVDD33 R5 GND S5 SCK N6 GND P6 GND Q6 GND R6 GND S6 SVDD N7 DAN2 P7 DAN1 Q7 DAN0 R7 GND S7 GND N8 DAP2 P8 DAP1 Q8 DAP0 R8 GND S8 GND N9 DBN2 P9 DBN1 Q9 DBN0 R9 GND S9 GND N10 DBP2 P10 DBP1 Q10 DBP0 R10 GND S10 GND 2000f For more information www.linear.com/LTC2000 47 LTC2000 Pin Locations (LTC2000-14) 2 3 CKN CKP 1 A TOP VIEW 4 5 6 7 B E GND DAN12 DAP12 DBN12 DBP12 AVDD18 DVDD18 DAN7 DAP7 DBN7 DBP7 IOUTP DAN6 DAP6 DBN6 DBP6 IOUTN DCKON DCKOP DCKIN DCKIP DAN4 DAP4 DBN4 DBP4 DVDD33 DAN1 DAP1 DBN1 DBP1 DAN0 DAP0 DBN0 DBP0 GND PD 48 DAN2 DAP2 DBN2 DBP2 AVDD33 Q S DAN3 DAP3 DBN3 DBP3 REFIO FSADJ P R DAN5 DAP5 DBN5 DBP5 GND L N DAN8 DAP8 DBN8 DBP8 GND K M DAN10 DAP10 DBN10 DBP10 DAN9 DAP9 DBN9 DBP9 G J 10 DAN11 DAP11 DBN11 DBP11 F H 9 DAN13 DAP13 DBN13 DBP13 C D 8 CS TSTN TSTP SDO SDI GND SCK SVDD 2000f For more information www.linear.com/LTC2000 LTC2000 Pin Locations (LTC2000-11) LTC2000-11 BGA Pinout PIN ID FUNCTION PIN ID FUNCTION A1 GND B1 GND A2 CKN B2 GND A3 CKP B3 GND A4 GND B4 GND A5 DVDD18 B5 A6 GND A7 DAN10 A8 DAP10 PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION C1 AVDD18 D1 AVDD18 E1 AVDD18 F1 GND C2 AVDD18 D2 AVDD18 E2 AVDD18 F2 GND C3 AVDD18 D3 AVDD18 E3 DVDD18 F3 GND C4 AVDD18 D4 DVDD18 E4 DVDD18 F4 GND DVDD18 C5 DVDD18 D5 DVDD18 E5 DVDD18 F5 GND B6 GND C6 GND D6 GND E6 GND F6 GND B7 DAN9 C7 DAN8 D7 DAN7 E7 DAN6 F7 DAN5 B8 DAP9 C8 DAP8 D8 DAP7 E8 DAP6 F8 DAP5 A9 DBN10 B9 DBN9 C9 DBN8 D9 DBN7 E9 DBN6 F9 DBN5 A10 DBP10 B10 DBP9 C10 DBP8 D10 DBP7 E10 DBP6 F10 DBP5 PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION G1 GND H1 IOUTP J1 IOUTN K1 GND L1 GND M1 REFIO G2 GND H2 GND J2 GND K2 GND L2 GND M2 FSADJ G3 GND H3 GND J3 GND K3 GND L3 GND M3 GND G4 GND H4 GND J4 GND K4 GND L4 GND M4 AVDD33 G5 GND H5 GND J5 GND K5 GND L5 GND M5 DVDD33 G6 GND H6 GND J6 GND K6 GND L6 GND M6 GND G7 DAN4 H7 DAN3 J7 DCKON K7 DAN2 L7 DAN1 M7 DAN0 G8 DAP4 H8 DAP3 J8 DCKOP K8 DAP2 L8 DAP1 M8 DAP0 G9 DBN4 H9 DBN3 J9 DCKIN K9 DBN2 L9 DBN1 M9 DBN0 G10 DBP4 H10 DBP3 J10 DCKIP K10 DBP2 L10 DBP1 M10 DBP0 PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION N1 GND P1 AVDD33 Q1 AVDD33 R1 GND S1 PD N2 GND P2 AVDD33 Q2 AVDD33 R2 GND S2 CS N3 GND P3 AVDD33 Q3 AVDD33 R3 TSTN S3 SDO N4 AVDD33 P4 AVDD33 Q4 AVDD33 R4 TSTP S4 SDI N5 DVDD33 P5 DVDD33 Q5 DVDD33 R5 GND S5 SCK N6 GND P6 GND Q6 GND R6 GND S6 SVDD N7 GND P7 GND Q7 GND R7 GND S7 GND N8 GND P8 GND Q8 GND R8 GND S8 GND N9 GND P9 GND Q9 GND R9 GND S9 GND N10 GND P10 GND Q10 GND R10 GND S10 GND 2000f For more information www.linear.com/LTC2000 49 LTC2000 Pin Locations (LTC2000-11) 2 3 CKN CKP 1 A TOP VIEW 4 5 6 7 B C D DAN9 DAP9 DBN9 DBP9 AVDD18 DAN8 DAP8 DBN8 DBP8 DVDD18 DAN7 DAP7 DBN7 DBP7 DAN6 DAP6 DBN6 DBP6 DAN5 DAP5 DBN5 DBP5 GND G DAN4 DAP4 DBN4 DBP4 IOUTP DAN3 DAP3 DBN3 DBP3 IOUTN DCKON DCKOP DCKIN DCKIP K N DAN1 DAP1 DBN1 DBP1 REFIO FSADJ DANO DAPO DBNO DBPO DVDD33 P AVDD33 Q GND R GND S PD 50 DAN2 DAP2 DBN2 DBP2 GND L M 10 GND F J 9 DAN10 DAP10 DBN10 DBP10 E H 8 CS TSTN TSTP SDO SDI SCK SVDD 2000f For more information www.linear.com/LTC2000 LTC2000 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. BGA Package 170-Lead (15.00mm × 9.00mm × 1.54mm) (Reference LTC DWG# 05-08-1890 Rev B) A aaa Z E Y A2 X Z SEE NOTES DETAIL A SEE NOTES 10 9 8 7 6 5 4 3 2 7 1 PIN 1 3 A A1 PIN “A1” CORNER B ccc Z C 4 b D E b1 MOLD CAP F SUBSTRATE H F Z // bbb Z D G H1 H2 J DETAIL B K L M e Øb (170 PLACES) N ddd M Z X Y eee M Z P Q R S aaa Z DETAIL A 3.60 2.80 2.00 1.20 0.40 0.00 0.40 1.20 2.55 4.80 4.00 3.20 2.40 1.60 0.80 0.00 0.80 1.60 2.40 3.20 4.00 4.80 5.60 6.40 2. ALL DIMENSIONS ARE IN MILLIMETERS DIMENSIONS 5.60 SUGGESTED PCB LAYOUT TOP VIEW PACKAGE BOTTOM VIEW NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 6.40 0.40 ±0.025 Ø 170x b G DETAIL B PACKAGE SIDE VIEW 2.00 2.80 3.05 PACKAGE TOP VIEW 3.60 e 5.35 5.85 SYMBOL A A1 A2 b b1 D E e F G H1 H2 aaa bbb ccc ddd eee MIN 1.39 0.35 1.04 0.45 0.35 0.39 0.65 NOM 1.54 0.40 1.14 0.50 0.40 15.00 9.00 0.80 12.80 7.20 0.44 0.70 MAX 1.69 0.45 1.24 0.55 0.45 0.49 0.75 0.15 0.10 0.12 0.15 0.08 TOTAL NUMBER OF BALLS: 170 NOTES 3 BALL DESIGNATION PER JESD MS-028 AND JEP95 4 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. SOLDER BALL COMPOSITION CAN BE 96.5% Sn/3.0% Ag/0.5% Cu OR Sn Pb EUTECTIC 7 ! PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY LTXXXXXX COMPONENT PIN “A1” TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION BGA 170 1112 REV B 2000f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. For more information www.linear.com/LTC2000 51 LTC2000 Typical Application LTC2000 High Speed DAC Driving LT5579 Mixer as an Upconverting Transmitter with Low Noise Power Supply Solution 5V 1µF 5V 1µF 5 8 3 6 7 5 8 3 6 7 LT1763CS8-3.3 SHDN IN GND GND GND 1 OUT 2 SEN 0.01µF BYP 47µF L6 1nH C65 10pF 47µF 10µF 4.7µF 3.24k 1k SHDN IN GND GND GND 1 OUT 2 SEN 47µF 0.01µF BYP 47µF 4 T1 ANAREN B0430J50100AHF 6 1 GND 3 IN GND 5 C41 100pF C42 100pF 4 SPI PORTS C43 0.01µF AVDD33 DVDD33 DAP[15:0] SVDD AVDD18 DAN[15:0] J10 DVDD18 DCKIP J8 DCKIN DBP[15:0] DBN[15:0] K8 DCKOP TSTP K7 DCKON TSTN S1 PD IOUTN S2 LTC2000Y-16 CS S3 SDO S4 SDI S5 SCK IOUTP A3 CKP R29 50Ω REFIO R26 50Ω A2 FSADJ CKN LT3080EDD 3 7 V VIN 2 OUT 8 VOUT VIN 1 VOUT 5 9 PAD VCTRL SET 7.15k LT3080EDD 3 7 V VIN 2 OUT 8 V VIN 1 OUT V 5 9 OUT PAD VCTRL SET LT1763CS8-3.3 2 C66 1pF 1µF 4 MATCHED LVDS DATA AND CLOCK LINES FROM FPGA CLOCK SOURCE 7 1 SHDN OUTF 6 2 V OUTS 8 3 IN GND GND 5 4 GND GND LTC6655CH MS8-2.048 3.3V 4.7µF 3.24k 3.3V 3.3V 1µF 5V 3.3V 1µF 5V S6 3.3V C74 10µF R4 R3 R52 20Ω R49 0Ω J1 C26 0.1µF R53 11.5Ω C66 47pF C68 82pF R54 11.5Ω C65 47pF C67 82pF 1 L8 2.7nH M1 M2 GND R51 20Ω R45 500Ω C72 100pF 0.1dB CHEBYCHEV, BW = 535MHz L11 L9 1.5nH 2.7nH 1 2 1 2 C25 0.1µF R50 0Ω H1 C73 1µF 2 1 L10 1.5nH C71 10pF 4 IF – C68 22pF 2 3 VCC LO LT5579 IF + GND RF LO INPUT 22 15 RF OUTPUT L12 1.8nH C69 1.2pF 2000 TA01 C40 10µF Related Parts PART NUMBER DESCRIPTION COMMENTS LTC1666/LTC1667/ LTC1668 12-/14-/16-Bit 50Msps DACs with 10mA Full Scale VCC = ±5V, –1V to 1V Output Compliance, 28-Pin SSOP Package LTC2153/LTC2158 Single/Dual 14-/12-Bit 310Msps ADCs 88dB SFDR, 1.25GHz Bandwidth Sample-and-Hold LTC2630 LTC2991 Single 12-/10-/8-Bit Rail-to-Rail DACs with Internal Reference VCC = 2.7V to 5.5V, SC70 Package VCC = 3V to 5.5V, 16-Lead MSOP Package Octal I2C Voltage, Current, and Temperature Monitor LTC2997 Remote/Internal Temperature Sensor VCC = 2.V to 5.5V, 170µA, 6-Lead 2mm × 3mm DFN Package LT®5521 Very High Linearity Active Mixer 10MHz to 3.7GHz, 24.2dBm OIP3 at 1.95GHz LT5579 High Linearity Upconverting Mixer 1.5GHz to 3.8GHz, 27.3dBm OIP3 at 2.14GHz LT5578 High Linearity Upconverting Mixer 400MHz to 2.7GHz, 24.3dBm IIP3 at 1.95GHz LTC6406 3GHz, Low Noise, Rail-to-Rail Input Differential Amplifier/Driver Low Noise: 1.6nV/√Hz RTI , 18mA at 3V, Low Distortion LTC6430-15 High Linearity Differential RF/IF Amplifier 20MHz to 2GHz Bandwidth, 50dBm OIP3 at 240MHz, 15.2dB Gain LTC6946 Ultralow Noise and Spurious Integer-N Synthesizer with Integrated VCO 0.37GHz to 5.7GHz, –226dBc/Hz Normalized In-Band Phase Noise, –274dBc/Hz Normalized In-Band 1/f Noise 52 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC2000 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2000 2000f LT 0714 • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2014