IDT ICS850S1201I

ICS850S1201I
12:1 SINGLE-ENDED MULTIPLEXER
General Description
Features
The ICS850S1201I is a low skew12:1 Single-ended
Clock Multiplexer and is a member of the
HiPerClockS™
HiPerClockS™ family of High Performance Clock
Solutions from IDT. The ICS850S1201I has 12
selectable single-ended clock inputs and 1 singleended clock output. The device operates up to 250MHz and is
packaged in a 20 TSSOP package.
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ICS
Block Diagram
12:1 single-ended multiplexer
Nominal output impedance: 20Ω (VDD = 3.3V)
Maximum output frequency: 250MHz
Propagation delay: 2.7ns (maximum)
Full 3.3V or 2.5V supply modes
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Pin Assignment
CLK_SEL0 Pulldown
CLK8
CLK9
CLK10
CLK11
VDD
CLK_SEL0
CLK_SEL1
CLK_SEL2
CLK_SEL3
OE
CLK_SEL1 Pulldown
CLK_SEL2 Pulldown
CLK_SEL3 Pulldown
CLK0 Pulldown
CLK1 Pulldown
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLK7
CLK6
CLK5
CLK4
CLK3
CLK2
CLK1
CLK0
GND
Q
ICS850S1201I
20-Lead TSSOP
6.50mm x 4.40mm x 0.925mm
package body
G Package
Top View
Q
CLK10 Pulldown
CLK11 Pulldown
OE Pullup
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Table 1. Pin Descriptions
Number
Name
Type
1
CLK8
Input
2
CLK9
Input
Pulldown
Single-ended clock input. LVCMOS/LVTTL interface levels.
3
CLK10
Input
Pulldown
Single-ended clock input. LVCMOS/LVTTL interface levels.
4
CLK11
Input
Pulldown
Single-ended clock input. LVCMOS/LVTTL interface levels.
5
VDD
Power
6,
7.
8,
9
CLK_SEL0,
CLK_SEL1,
CLK_SEL2,
CLK_SEL3
Input
Pulldown
10
OE
Input
Pullup
11
Q
Output
Single-ended clock output. LVCMOS/LVTTL interface levels.
12
GND
Power
Power supply ground.
13
CLK0
Input
Pulldown
Single-ended clock input. LVCMOS/LVTTL interface levels.
14
CLK1
Input
Pulldown
Single-ended clock input. LVCMOS/LVTTL interface levels.
15
CLK2
Input
Pulldown
Single-ended clock input. LVCMOS/LVTTL interface levels.
16
CLK3
Input
Pulldown
Single-ended clock input. LVCMOS/LVTTL interface levels.
17
CLK4
Input
Pulldown
Single-ended clock input. LVCMOS/LVTTL interface levels.
18
CLK5
Input
Pulldown
Single-ended clock input. LVCMOS/LVTTL interface levels.
19
CLK6
Input
Pulldown
Single-ended clock input. LVCMOS/LVTTL interface levels.
20
CLK7
Input
Pulldown
Single-ended clock input. LVCMOS/LVTTL interface levels.
Pulldown
Description
Single-ended clock input. LVCMOS/LVTTL interface levels.
Power supply pin.
Clock select inputs. See Table 3. LVCMOS / LVTTL interface levels.
Output enable pin for Q output. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
CPD
Power Dissipation Capacitance
RPULLUP
Test Conditions
Minimum
Typical
Maximum
Units
2
pF
VDD = 3.465V
10
pF
VDD = 2.625V
8
pF
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
ROUT
Output Impedance
VDD = 3.3V±5%
20
Ω
VDD = 2.5V±5%
25
Ω
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Function Tables
Table 3. Clock Input Function Table
Inputs
CLK_SEL3
CLK_SEL2
CLK_SEL1
CLK_SEL0
Input Selected to Q
0
0
0
0
CLK0
0
0
0
1
CLK1
0
0
1
0
CLK2
0
0
1
1
CLK3
0
1
0
0
CLK4
0
1
0
1
CLK5
0
1
1
0
CLK6
0
1
1
1
CLK7
1
0
0
0
CLK8
1
0
0
1
CLK9
1
0
1
0
CLK10
1
0
1
1
CLK11
1
1
0
0
Output goes LOW
1
1
0
1
Output goes LOW
1
1
1
0
Output goes LOW
1
1
1
1
Output goes LOW
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, VO
-0.5V to VDD + 0.5V
Package Thermal Impedance, θJA
87.2°C/W (0 mps)
Storage Temperature, TSTG
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VDD
Positive Supply Voltage
IDD
Power Supply Current
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
49
mA
Output Unterminated
Table 4B. Power Supply DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VDD
Positive Supply Voltage
IDD
Power Supply Current
IDT™ / ICS™ 12:1, SINGLE-ENDED MULTIPLEXER
Test Conditions
Output Unterminated
4
Minimum
Typical
Maximum
Units
2.375
2.5
2.625
V
41
mA
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Table 4C. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VIH
Input
High Voltage
VIL
Input
Low Voltage
IIH
Input
High Current
IIL
Input
Low Current
Test Conditions
Minimum
VDD = 3.465V
Typical
Maximum
Units
2
VDD + 0.3
V
VDD = 2.625V
1.7
VDD + 0.3
V
VDD = 3.465V
-0.3
0.8
V
VDD = 2.625V
-0.3
0.7
V
CLK[0:11],
CLK_SEL[0:3]
VDD = VIN = 3.465V or 2.625V
150
µA
OE
VDD = VIN = 3.465V or 2.625V
10
µA
CLK[0:11],
CLK_SEL[0:3]
VDD = 3.465V or 2.625V, VIN = 0V
-10
µA
OE
VDD = 3.465V or 2.625V, VIN = 0V
-150
µA
VDD = 3.3V ± 5%, IOH = -12mA
2.6
V
VDD = 2.5V ± 5%, IOH = -12mA
1.8
V
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
VDD = 3.3V ± 5% or 2.5V ± 5%,
IOL = 12mA
0.5
V
NOTE 1: Output terminated with 50Ω to VDD/2. See Parameter Measurement Information section. Load Test Circuit diagrams.
AC Electrical Characteristics
Table 5A. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Parameter
Symbol
Test Conditions
Minimum
Typical
fMAX
Output Frequency
tpLH
Propagation Delay, Low-to-High;
NOTE 1
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
tsk(i)
Input Skew
175
ps
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
600
ps
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle; NOTE 4
MUXISOLATION
MUX Isolation
1.4
155.52MHz, Integration
Range: 12kHz – 20MHz
Maximum
Units
250
MHz
2.7
ns
0.35
ps
20% to 80%
100
500
ps
f ≤ 200MHz
46
54
%
f = 250MHz
40
155.52MHz
60
43
%
dB
NOTE 1: Measured from VDD/2 of the input to VDD/2 of the output.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 3: This parameter is defined according with JEDEC Standard 65.
NOTE 4: Input duty cycle must be 50%.
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Table 5B. AC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
Parameter
Symbol
fMAX
Output Frequency
tpLH
Propagation Delay, Low-to-High;
NOTE 1
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
tsk(i)
Input Skew
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle; NOTE 4
MUXISOLATION
MUX Isolation
Test Conditions
Minimum
Typical
1.5
155.52MHz, Integration
Range: 12kHz – 20MHz
Maximum
Units
250
MHz
2.7
ns
0.32
ps
195
ps
600
ps
20% to 80%
80
600
ps
f ≤ 200MHz
46
54
%
f = 250MHz
40
60
%
155.52MHz
43
dB
NOTE 1: Measured from VDD/2 of the input to VDD/2 of the output.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 3: This parameter is defined according with JEDEC Standard 65.
NOTE 4: Input duty cycle must be 50%.
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Additive Phase Jitter
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz band
to the power in the fundamental. When the required offset is
specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
SSB Phase Noise dBc/Hz
Additive Phase Jitter @ 155.52MHz
12kHz to 20MHz = 0.35ps (typical)
Offset Frequency (Hz)
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
IDT™ / ICS™ 12:1, SINGLE-ENDED MULTIPLEXER
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
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Parameter Measurement Information
1.25V±5%
1.65V±5%
SCOPE
VDD
SCOPE
VDD
Qx
Qx
LVCMOS
LVCMOS
GND
GND
-1.65V±5%
-1.25V±5%
3.3V Output Load AC Test Circuit
2.5V Output Load AC Test Circuit
Par t 1
V
DD
Qx
2
CLK1
Par t 2
V
DD
Qy
CLK2
2
tsk(pp)
Q
Part-to-Part Skew
tPD1
tPD2
tsk (i)
tsk(i) = tPD2 – tPD1
V
DDO
2
Q
t PW
t
odc =
PERIOD
t PW
Input Skew
x 100%
t PERIOD
Output Duty Cycle/Pulse Width/Period
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Parameter Measurement Information, continued
Spectrum
CLKx
MUX_ISOL
Q
(static) CLKy
Q
CLKx
80%
80%
tR
tF
20%
20%
CLKy
CLK_SELy
MUX Isolation
Output Rise/Fall Time
VDD
2
CLK0:
CLK11
VDD
2
Q
t
PD
Propagation Delay
Recommendations for Unused Input Pins
Inputs:
CLK Inputs
For applications not requiring the use of a clock input, it can be left
floating. Though not required, but for additional protection, a 1kΩ
resistor can be tied from the CLK input to ground.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
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Reliability Information
Table 6. θJA vs. Air Flow Table for a 20 Lead TSSOP
θJA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
87.2°C/W
82.9
80.7
Transistor Count
The transistor count for ICS850S1201I is: 649
Package Outline and Package Dimensions
Package Outline - G Suffix for 20 Lead TSSOP
Table 7. Package Dimensions
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
20
A
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
6.40
6.60
E
6.40 Basic
E1
4.30
4.50
e
0.65 Basic
L
0.45
0.75
α
0°
8°
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
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Ordering Information
Table 8. Ordering Information
Part/Order Number
850S1201AGILF
850S1201AGILFT
Marking
ICS0S1201BIL
ICS0S1201BIL
Package
“Lead-Free” 20 Lead TSSOP
“Lead-Free” 20 Lead TSSOP
Shipping Packaging
Tube
2500 Tape & Reel
Temperature
-40°C to 85°C
-40°C to 85°C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT
product for use in life support devices or critical medical instruments.
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Contact Information:
www.IDT.com
www.IDT.com
Sales
Technical Support
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
www.IDT.com/go/contactIDT
[email protected]
+480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
© 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
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trademarks used to identify products or services of their respective owners.
Printed in USA