ICS8545-02 LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Description Features The ICS8545-02 is a low skew, high performance 1-to-4 LVCMOS/LVTTL-to-LVDS Clock Fanout HiPerClockS™ Buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from IDT. Utilizing Low Voltage Differential Signaling (LVDS) the ICS8545-02 provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100Ω. The ICS8545-02 accepts an LVCMOS/LVTTL input level and translates it to 3.3V LVDS output levels. • • Four differential LVDS output pairs • • • • • • • • • Maximum output frequency: 350MHz ICS Guaranteed output and part-to-part skew characteristics make the ICS8545-02 ideal for those applications demanding well defined performance and repeatability. Q LE 00 CLK2 Pulldown 11 Output skew: 60ps (maximum) Part-to-part skew: 450ps (maximum) Propagation delay: 1.45ns (maximum) Additive phase jitter, RMS: 0.14ps (typical) Full 3.3Vsupply mode 0°C to 70°C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages GND CLK_EN CLK_SEL CLK1 nc CLK2 nc nD CLK1 Pulldown Translates LVCMOS/LVTTL input signals to LVDS levels Pin Assignment Block Diagram CLK_EN Pullup Two LVCMOS/LVTTL clock inputs to support redundant or selectable frequency fanout applications CLK_SEL Pulldown Q0 nQ0 Q1 nQ1 OE GND VDD Q2 nQ2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Q0 nQ0 VDD Q1 nQ1 Q2 nQ2 GND Q3 nQ3 ICS8545-02 Q3 nQ3 20-Lead TSSOP OE Pullup 6.5mm x 4.4mm x 0.925mm package body G Package Top View IDT™ / ICS™ LVDS FANOUT BUFFER 1 ICS8545AG-02 REV. A March 3, 2009 ICS8545-02 LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Table 1. Pin Descriptions Number Name Type Description 1, 9, 13 GND Power 2 CLK_EN Input Pullup 3 CLK_SEL Input Pulldown Clock select input. When HIGH, selects CLK2 input. When LOW, selects CLK1 input. LVCMOS / LVTTL interface levels. 4 CLK1 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 5, 7 nc Unused 6 CLK2 Input Power supply ground. Synchronizing clock enable. When HIGH, clock outputs follows clock input. When LOW, Qx outputs are forced low, nQx outputs are forced high. LVCMOS / LVTTL interface levels. No connect. Pulldown Pullup Single-ended clock input. LVCMOS/LVTTL interface levels. Output enable. Controls enabling and disabling of outputs Q0/nQ0 through Q3/nQ3. LVCMOS/LVTTL interface levels. 8 OE Input 10, 18 VDD Power Positive supply pins. 11, 12 Q3, Q3 Output Differential output pair. LVDS interface levels. 14, 15 Q2, Q2 Output Differential output pair. LVDS interface levels. 16, 17 Q1, Q1 Output Differential output pair. LVDS interface levels. 19, 20 Q0, Q0 Output Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ IDT™ / ICS™ LVDS FANOUT BUFFER Test Conditions 2 Minimum Typical Maximum Units ICS8545AG-02 REV. A March 3, 2009 ICS8545-02 LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Function Tables Table 3A. Control Input Function Table Inputs Outputs OE CLK_EN CLK_SEL 0 X X 1 0 0 1 0 1 1 Selected Source Q0:Q3 nQ0:nQ3 Hi-Z Hi-Z CLK1 Low High 1 CLK2 Low High 1 0 CLK1 Active Active 1 1 CLK2 Active Active After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK1 and CLK2 inputs as described in Table 3B. Enabled Disabled CLK1, CLK2 CLK_EN nQ0:nQ3 Q0:Q3 Figure 1. CLK_EN Timing Diagram Table 3B. Clock Input Function Table Inputs Outputs CLK1 or CLK2 Q0:Q3 nQ0:nQ3 0 LOW HIGH 1 HIGH LOW IDT™ / ICS™ LVDS FANOUT BUFFER 3 ICS8545AG-02 REV. A March 3, 2009 ICS8545-02 LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuos Current Surge Current 10mA 15mA Package Thermal Impedance, θJA 91.1°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditions VDD Positive Supply Voltage IDD Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 90 mA Maximum Units Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditions Minimum Typical VIH Input High Voltage 2 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current IIL Input Low Current CLK1, CLK2, CLK_SEL VDD = VIN = 3.465V 150 µA OE, CLK_EN VDD = VIN = 3.465V 5 µA CLK1, CLK2, CLK_SEL VDD = 3.465V, VIN = 0V -5 µA OE, CLK_EN VDD = 3.465V, VIN = 0V -150 µA Table 4C. LVDS DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter VOD Differential Output Voltage ∆VOD VOD Magnitude Change VOS Offset Voltage ∆VOS VOS Magnitude Change IDT™ / ICS™ LVDS FANOUT BUFFER Test Conditions Minimum Typical Maximum Units 525 mV 50 mV 1.25 1.4 V 5 50 mV 275 1.1 4 ICS8545AG-02 REV. A March 3, 2009 ICS8545-02 LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER AC Electrical Characteristics Table 5. AC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Parameter Symbol Test Conditions Minimum Typical Maximum Units 350 MHz 1.45 ns fMAX Output Frequency tPD Propagation Delay; NOTE 1 tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section tsk(o) Output Skew; NOTE 2, 4 60 ps tsk(pp) Part-to-Part Skew; NOTE 3, 4 450 ps tR / tF Output Rise/Fall Time odc Output Duty Cycle; NOTE 5 1.0 155.52MHz, Integration Range: 12kHz – 20MHz 0.14 ps 20% to 80% 150 700 ps ƒ ≤ 166MHz 45 55 % ƒ > 166MHz 40 60 % All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: Measured using 50% duty cycle. IDT™ / ICS™ LVDS FANOUT BUFFER 5 ICS8545AG-02 REV. A March 3, 2009 ICS8545-02 LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band SSB Phase Noise dBc/Hz to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. Offset Frequency (Hz) device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the IDT™ / ICS™ LVDS FANOUT BUFFER 6 ICS8545AG-02 REV. A March 3, 2009 ICS8545-02 LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Parameter Measurement Information VDD SCOPE 3.3V±5% POWER SUPPLY + Float GND – Qx VDD nQ0:nQ3 V LVDS Cross Points PP V CMR Q0:Q3 nQx GND - - 3.3V LVDS Output Load AC Test Circuit nQx Differential Output Level Par t 1 nQx Qx Qx nQy Par t 2 nQy Qy Qy tsk(o) tsk(pp) Part-to-Part Skew Output Skew nQ0:nQ3 VDD Q0:Q3 CLK1, CLK2 t PW t PERIOD t PW odc = 2 nQ0:nQ3 Q0:Q3 x 100% tPD t PERIOD Output Duty Cycle/Pulse Width/Period IDT™ / ICS™ LVDS FANOUT BUFFER Propagation Delay 7 ICS8545AG-02 REV. A March 3, 2009 ICS8545-02 LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Parameter Measurement Information, continued VDD out ➤ 80% 80% VOD DC Input 20% 20% LVDS 100 tF tR out Output Rise/Fall Time ➤ VOD/∆ VOD ➤ Clock Outputs Differential Output Voltage Setup VDD out LVDS ➤ DC Input out ➤ VOS/∆ VOS ➤ Offset Voltage Setup IDT™ / ICS™ LVDS FANOUT BUFFER 8 ICS8545AG-02 REV. A March 3, 2009 ICS8545-02 LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Application Information Recommendations for Unused Input and Output Pins Inputs: Outputs: CLK Inputs LVDS Outputs For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground. All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, there should be no trace attached. LVCMOS Control Pins All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. 3.3V LVDS Driver Termination A general LVDS interface is shown in Figure 2. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 3.3V 50Ω 3.3V LVDS Driver + R1 100Ω – 50Ω 100Ω Differential Transmission Line Figure 2. Typical LVDS Driver Termination IDT™ / ICS™ LVDS FANOUT BUFFER 9 ICS8545AG-02 REV. A March 3, 2009 ICS8545-02 LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Power Considerations This section provides information on power dissipation and junction temperature for the ICS8545-02. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8545-02 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 90mA = 311.85mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 91.1°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.312W * 91.1°C/W = 98.4°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer). Table 6. Thermal Resistance θJA for 20 Lead TSSOP, Forced Convection θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards IDT™ / ICS™ LVDS FANOUT BUFFER 0 1 2.5 91.1°C/W 86.7°C/W 84.6°C/W 10 ICS8545AG-02 REV. A March 3, 2009 ICS8545-02 LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Reliability Information Table 7. θJA vs. Air Flow Table for a 20 Lead TSSOP θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 91.1°C/W 86.7°C/W 84.6°C/W Transistor Count The transistor count for ICS8545-02 is: 360 Package Outline and Package Dimension Package Outline - G Suffix for 20 Lead TSSOP Table 8. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 20 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 α 0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT™ / ICS™ LVDS FANOUT BUFFER 11 ICS8545AG-02 REV. A March 3, 2009 ICS8545-02 LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Ordering Information Table 9. Ordering Information Part/Order Number ICS8545AG-02 ICS8545AG-02T ICS8545AG-02LF ICS8545AG-02LFT Marking ICS8545AG-02 ICS8545AG-02 ICS8545AG-02LF ICS8545AG-02LF Package 20 Lead TSSOP 20 Lead TSSOP “Lead-Free” 20 Lead TSSOP “Lead-Free” 20 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Tube 2500 Tape & Reel Temperature 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ / ICS™ LVDS FANOUT BUFFER 12 ICS8545AG-02 REV. A March 3, 2009 ICS8545-02 LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 © 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA