PRELIMINARY ICS8535BI-01 LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO3.3V LVPECL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS8535BI-01 is a low skew, high performance ICS 1-to-4 LVCMOS/LVTTL-to-3.3V LVPECL fanout HiPerClockS™ buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from IDT. The ICS8535BI-01 has two single ended clock inputs. the single ended clock input accepts LVCMOS or LVTTL input levels and translate them to 3.3V LVPECL levels. The clock enable is internally synchronized to eliminate runt clock pulses on the output during asynchronous assertion/deassertion of the clock enable pin. • Four differential 3.3V LVPECL outputs Guaranteed output and part-to-part skew characteristics make the ICS8535BI-01 ideal for those applications demanding well defined performance and repeatability. • Part-to-part skew: TBD • Selectable CLK0 or CLK1 inputs for redundant and multiple frequency fanout applications • CLK0 or CLK1 can accept the following input levels: LVCMOS or LVTTL • Maximum output frequency: 266MHz • Translates LVCMOS and LVTTL levels to 3.3V LVPECL levels • Output skew: TBD • Propagation delay: 1.3ns (typical) • Additive phase jitter, RMS: 0.04ps (typical) • 3.3V operating supply • 0°C to 70°C ambient operating temperature PIN ASSIGNMENT nQ1 Q1 VCC nQ0 Q0 VEE CLK_EN CLK_SEL nc CLK0 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Q2 nQ2 VCC nc Q3 nQ3 VCC nc nc CLK1 BLOCK DIAGRAM D CLK_EN Q LE ICS8535BI-01 20-Lead TSSOP 4.4mm x 6.5mm x 0.925mm body package G Package Top View CLK0 0 CLK1 1 Q0 nQ0 Q1 nQ1 Q2 nQ2 VCC Q1 NQ1 nQ0 Q0 CLK_SEL VCC 1 20 19 18 17 16 15 VCC nQ3 2 14 Q2 VCC CLK_EN 5 7 8 9 11 10 nc nc 6 CLK1 nQ2 12 nc 13 4 CLK0 3 CLK_SEL Q3 VEE Q3 nQ3 ICS8535BI-01 20-Lead VFQFN 4mm x 4mm x 0.925mm body package K Package Top View The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice. IDT ™ / ICS™ 3.3V LVPECL FANOUT BUFFER 1 ICS8535BGI-01 REV. A NOVEMBER 9, 2007 ICS8535BI-01 LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER PRELIMINARY TABLE 1. PIN DESCRIPTIONS Name Type VEE Power CLK_EN Input CLK_SEL Input CLK0 Input CLK1 nc Input Unused VCC Power nQ3, Q3 nQ2, Q2 nQ1, Q1 nQ0, Q0 NOTE: Pullup Description Negative supply pin. Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, Pullup Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects CLK1 input. When LOW, selects CLK0 input. Pulldown LVCMOS / LVTTL interface levels. Pulldown LVCMOS / LVTTL clock input. Pulldown LVCMOS / LVTTL clock input. No connect. Positive supply pins. Output Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Output Output Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Output and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions Minimum Typical 4 Maximum Units pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ IDT ™ / ICS™ 3.3V LVPECL FANOUT BUFFER 2 ICS8535BGI-01 REV. A NOVEMBER 9, 2007 ICS8535BI-01 LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER PRELIMINARY TABLE 3A. CONTROL INPUT FUNCTION TABLE Inputs CLK_EN 0 Outputs CLK_SEL 0 Selected Source CLK0 Q0:Q3 Disabled; LOW nQ0:nQ3 Disabled; HIGH 0 1 CLK1 Disabled; LOW Disabled; HIGH 1 0 CLK0 Enabled Enabled 1 1 CLK1 Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show in Figure 1. In the active mode, the state of the outputs are a function of the CLK0 and CLK1 inputs as described in Table 3B. Enabled Disabled CLK0, CLK1 CLK_EN nQ0:nQ3 Q0:Q3 FIGURE 1. CLK_EN TIMING DIAGRAM TABLE 3B. CLOCK INPUT FUNCTION TABLE Inputs CLK0 or CLK1 0 1 Outputs Q0:Q3 LOW HIGH IDT ™ / ICS™ 3.3V LVPECL FANOUT BUFFER nQ0:nQ3 HIGH LOW 3 ICS8535BGI-01 REV. A NOVEMBER 9, 2007 ICS8535BI-01 LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER PRELIMINARY ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause per manent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 20 Lead TSSOP 73.2°C/W (0 lfpm) 20 Lead VFQFN 60.4°C/W (0 mps) -65°C to 150°C Storage Temperature, TSTG TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VCC Positive Supply Voltage Test Conditions IEE Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 45 mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Maximum Units CLK0, CLK1 Test Conditions Minimum 2 Typical VCC + 0.3 V CLK_EN, CLK_SEL 2 VCC + 0.3 V CLK0, CLK1 -0.3 1.3 V CLK_EN, CLK_SEL -0.3 0.8 V 150 µA 5 µA CLK0, CLK1, CLK_SEL CLK_EN VIN = VCC = 3.465V VIN = VCC = 3.465V CLK0, CLK1, CLK_SEL VIN = 0V, VCC = 3.465V -5 µA CLK_EN VIN = 0V, VCC = 3.465V -150 µA TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions Minimum VCC - 1.4 Typical VCC - 0.9 V VOL Output Low Voltage; NOTE 1 VCC - 2.0 VCC - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1. 0 V NOTE 1: Outputs terminated with 50Ω to VCC - 2V. IDT ™ / ICS™ 3.3V LVPECL FANOUT BUFFER 4 ICS8535BGI-01 REV. A NOVEMBER 9, 2007 ICS8535BI-01 LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER PRELIMINARY TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fMAX Output Frequency Test Conditions Minimum Typical Maximum Units 266 MHz tPD Propagation Delay; NOTE 1 1.3 ns t sk(o) Output Skew; NOTE 2, 4 TBD ps t sk(pp) Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section Output Rise/Fall Time TBD ps 0.04 ps 450 ps t jit t R / tF ƒ = 155.52MHz (Integration Range: 12kHz - 20MHz) 20% to 80% @ 50MHz odc Output Duty Cycle 50 % All parameters measured at 266MHz unless noted otherwise. The cycle-to-cycle jitter on the input will equal the jitter on the output. The par t does not add jitter. NOTE 1: Measured from the VCC/2 of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. IDT ™ / ICS™ 3.3V LVPECL FANOUT BUFFER 5 ICS8535BGI-01 REV. A NOVEMBER 9, 2007 ICS8535BI-01 LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER PRELIMINARY ADDITIVE PHASE JITTER band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz 0 -10 Additive Phase Jitter @ 155.52MHz -20 (12kHz to 20MHz) = 0.04ps typical -30 -40 -50 SSB PHASE NOISE dBc/HZ -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M OFFSET FROM CARRIER FREQUENCY (HZ) As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device IDT ™ / ICS™ 3.3V LVPECL FANOUT BUFFER meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. 6 ICS8535BGI-01 REV. A NOVEMBER 9, 2007 ICS8535BI-01 LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER PRELIMINARY PARAMETER MEASUREMENT INFORMATION 2V VCC Qx SCOPE PART 1 nQx Qx PART 2 nQy LVPECL nQx VEE Qy tsk(pp) -1.3V ± 0.165V 3.3V OUTPUT LOAD AC TEST CIRCUIT PART-TO-PART SKEW nQx 80% 80% Qx VSW I N G Clock Outputs nQy 20% 20% tF tR Qy tsk(o) OUTPUT RISE/FALL TIME OUTPUT SKEW nQ0:nQ3 CLK0, CLK1 Q0:Q3 t PW t nQ0:nQ3 Q0:Q3 odc = tPD PERIOD t PW x 100% t PERIOD PROPAGATION DELAY IDT ™ / ICS™ 3.3V LVPECL FANOUT BUFFER OUTPUT DUTY CYCLE/ PULSE WIDTH/PERIOD 7 ICS8535BGI-01 REV. A NOVEMBER 9, 2007 ICS8535BI-01 LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER PRELIMINARY APPLICATION INFORMATION RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CLK INPUTS For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground. LVPECL OUTPUTS All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. TERMINATION FOR LVPECL OUTPUTS transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω 3.3V Zo = 50Ω 125Ω FOUT FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω RTT = 125Ω 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o 50Ω Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 2A. LVPECL OUTPUT TERMINATION IDT ™ / ICS™ 3.3V LVPECL FANOUT BUFFER FIN 84Ω FIGURE 2B. LVPECL OUTPUT TERMINATION 8 ICS8535BGI-01 REV. A NOVEMBER 9, 2007 ICS8535BI-01 LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER PRELIMINARY VFQFN EPAD THERMAL RELEASE PATH are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/ slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadfame Base Package, Amkor Technology. In order to maximize both the removal of heat from the package and the electrical perfor mance, a land patter n must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 3. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE SOLDER LAND PATTERN THERMAL VIA PIN PIN PAD (GROUND PAD) FIGURE 3. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE) IDT ™ / ICS™ 3.3V LVPECL FANOUT BUFFER 9 ICS8535BGI-01 REV. A NOVEMBER 9, 2007 ICS8535BI-01 LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER PRELIMINARY POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8535BI-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8535BI-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 45mA = 155.9mW • Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 4 x 30mW = 120mW Total Power_MAX (3.465V, with all outputs switching) = 155.9mW + 120mW = 275.9mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air low of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6A below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.276W * 66.6°C/W = 103.38°C. This is well below the limit of 125°C. This calculation is only an example, and the Tj will obviously vary depending on the number of outputs that are loaded, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6A. THERMAL RESISTANCE θJA FOR 20-LEAD TSSOP, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 6B. θJAVS. AIR FLOW TABLE FOR 20 LEAD VFQFN θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards IDT ™ / ICS™ 3.3V LVPECL FANOUT BUFFER 10 0 1 3 60.4°C/W 52.8°C/W 46.0°C/W ICS8535BGI-01 REV. A NOVEMBER 9, 2007 ICS8535BI-01 LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER PRELIMINARY 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC • For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V (VCC_MAX - VOH_MAX) = 1.0V • For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V (VCC_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX - 2V))/R ] * (VCC_MAX - VOH_MAX) = [(2V - (V L CC_MAX - VOH_MAX))/R ] * (VCC_MAX - VOH_MAX) = L [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(V OL_MAX – (V CC_MAX - 2V))/R ] * (V L CC_MAX -V OL_MAX ) = [(2V - (V CC_MAX -V OL_MAX ))/R ] * (V L CC_MAX -V OL_MAX )= [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW IDT ™ / ICS™ 3.3V LVPECL FANOUT BUFFER 11 ICS8535BGI-01 REV. A NOVEMBER 9, 2007 ICS8535BI-01 LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER PRELIMINARY RELIABILITY INFORMATION TABLE 7A. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 114.5°C/W 73.2°C/W 98.0°C/W 66.6°C/W 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 7B. θJAVS. AIR FLOW TABLE FOR 20 LEAD VFQFN θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 3 60.4°C/W 52.8°C/W 46.0°C/W TRANSISTOR COUNT The transistor count for ICS8535BI-01 is: 412 IDT ™ / ICS™ 3.3V LVPECL FANOUT BUFFER 12 ICS8535BGI-01 REV. A NOVEMBER 9, 2007 ICS8535BI-01 LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER PRELIMINARY PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP TABLE 8A. PACKAGE DIMENSIONS FOR TSSOP Millimeters SYMBOL Minimum N A Maximum 20 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MO-153 IDT ™ / ICS™ 3.3V LVPECL FANOUT BUFFER 13 ICS8535BGI-01 REV. A NOVEMBER 9, 2007 ICS8535BI-01 LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER PRELIMINARY PACKAGE OUTLINE - K SUFFIX FOR 20 LEAD VFQFN NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 8 below. TABLE 8B. PACKAGE DIMENSIONS FOR 20 LEAD VFQFN JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL MINIMUM 20 N A 0.80 A1 0 1.0 0.05 0.25 Reference A3 b MAXIMUM 0.18 0.30 e 0.50 BASIC ND 5 NE 5 D 4.0 D2 0.75 2.80 4.0 E E2 0.75 2.80 L 0.35 0.75 Reference Document: JEDEC Publication 95, MO-220 IDT ™ / ICS™ 3.3V LVPECL FANOUT BUFFER 14 ICS8535BGI-01 REV. A NOVEMBER 9, 2007 ICS8535BI-01 LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER PRELIMINARY TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS8535BGI-01 ICS8535BGI01 20 Lead TSSOP tube -40°C to 85°C ICS8535BGI-01T ICS8535BGI01 20 Lead TSSOP 2500 tape & reel -40°C to 85°C ICS8535BGI-01LF ICS8535BI01L 20 Lead "Lead Free" TSSOP tube -40°C to 85°C ICS8535BGI-01LFT ICS8535BI01L 20 Lead "Lead Free" TSSOP 2500 tape & reel -40°C to 85°C ICS8535BKI-01 35BI01 20 Lead VFQFN tube -40°C to 85°C ICS8535BKI-01T 35BI01 20 Lead VFQFN 2500 tape & reel -40°C to 85°C ICS8535BKI-01LF 5BI01L 20 Lead "Lead-Free" VFQFN tube -40°C to 85°C ICS8535BKI-01LFT 5BI01L 20 Lead "Lead-Free" VFQFN 2500 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ 3.3V LVPECL FANOUT BUFFER 15 ICS8535BGI-01 REV. A NOVEMBER 9, 2007 ICS8535BI-01 LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER PRELIMINARY Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 © 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA