ISL6115A ® Data Sheet February 25, 2009 FN6855.0 12V Power Distribution Controllers Features This fully featured hot swap power controller targets +12V applications. The ISL6115A with its integrated charge pump has a higher (6.5V vs 5V) gate drive than its sister part the ISL6115 making this part an immediate efficiency improvement replacement. • HOT SWAP Single Power Distribution Control for +12V This IC features programmable overcurrent (OC) detection, current regulation (CR) with time delay to latch-off and softstart. • Rail-to-Rail Common Mode Input Voltage Range The current regulation level is set by 2 external resistors; RISET sets the CR Vth and the other is a low ohmic sense element across, which the CR Vth is developed. The CR duration is set by an external capacitor on the CTIM pin, which is charged with a 20µA current once the CR Vth level is reached. If the voltage on the CTIM capacitor reaches 1.9V the IC then quickly pulls down the GATE output latching off the pass FET. • Undervoltage and Overcurrent Latch Indicators Ordering Information • Pb-Free (RoHS Compliant) PART NUMBER • Overcurrent Fault Isolation • Programmable Current Regulation Level • Programmable Current Regulation Time to Latch-Off • Enhanced Internal Charge Pump Drives N-Channel MOSFET gate to 6.5V above IC bias. • Adjustable Turn-On Ramp • Protection During Turn-On • Two Levels of Overcurrent Detection Provide Fast Response to Varying Fault Conditions • 1µs Response Time to Dead Short PART TEMP. PACKAGE PKG. MARKING RANGE (°C) (Pb-free) DWG. # Applications ISL6115AIBZ 6115A IBZ -40 to +85 8 Ld SOIC M8.15 • Power Distribution Control ISL6115AIBZ-T* 6115A IBZ -40 to +85 8 Ld SOIC M8.15 • Hot Plug Components and Circuitry ISL6115ACBZ 6115A CBZ 0 to +70 8 Ld SOIC M8.15 ISL6115ACBZ-T* 6115A CBZ 0 to +70 8 Ld SOIC M8.15 Pinout ISL6115A (8 LD SOIC) TOP VIEW ISL6115AEVAL1Z Evaluation Platform *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. ISET 1 8 PWRON ISEN 2 7 PGOOD GATE 3 6 CTIM VSS 4 5 VDD Application Circuits- High Side Controller LOAD + 1 2 - 8 ISL6115A PWRON 7 3 6 4 5 PGOOD OC +V SUPPLY TO BE CONTROLLED 1 +12V CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL6115A Simplified Block Diagram VDD + POR + QN 8V ISET R + R Q UV PWRON S + VREF - ENABLE 12V ISEN PGOOD 20µA UV DISABLE CLIM OC GATE FALLING EDGE DELAY 10µA + - 7.5k + + 1.86V WOCLIM 18V - ENABLE VSS 20µA 18V 2 CTIM + - RISING EDGE PULSE VDD FN6855.0 February 25, 2009 ISL6115A Pin Descriptions PIN # SYMBOL FUNCTION DESCRIPTION 1 ISET Current Set Connect to the low side of the current sense resistor through the current limiting set resistor. This pin functions as the current limit programming pin. 2 ISEN Current Sense Connect to the more positive end of sense resistor to measure the voltage drop across this resistor. 3 GATE External FET Gate Drive Pin Connect to the gate of the external N-Channel MOSFET. A capacitor from this node to ground sets the turn-on ramp. At turn-on this capacitor will be charged to VDD +6.5V by an 14µA current source. 4 VSS Chip Return 5 VDD Chip Supply 12V chip supply. This can be either connected directly to the +12V rail supplying the switched load voltage or to a dedicated VSS +12V supply. 6 CTIM Current Limit Timing Capacitor Connect a capacitor from this pin to ground. This capacitor determines the time delay between an overcurrent event and chip output shutdown (current limit time-out). The duration of current limit time-out is equal to 93kΩ x CTIM. 7 PGOOD Power Good Indicator Indicates that the voltage on the ISEN pin is satisfactory. PGOOD is driven by an open drain N-Channel MOSFET and is pulled low when the output voltage (VISEN) is less than the UV level for the particular IC. 8 PWRON Power-ON PWRON is used to control and reset the chip. The chip is enabled when PWRON pin is driven high to a maximum of 5V or is left open. Do not drive this input >5V. After a current limit time-out, the chip is reset by a low level signal applied to this pin. This input has 20µA pull-up capability. 3 FN6855.0 February 25, 2009 ISL6115A Absolute Maximum Ratings TA = +25°C Thermal Information VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +16V GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 8V ISEN, PGOOD, PWRON, CTIM, ISET. . . . . . . -0.3V to VDD + 0.3V Thermal Resistance (Typical, Note 1) Operating Conditions VDD Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . +12V ±15% Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C θJA (°C/W) 8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . 98 Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. All voltages are relative to GND, unless otherwise specified. 3. Limits should be considered typical and are not production tested. Electrical Specifications VDD = 12V, TA = TJ = full temperature range, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 17 20 22 µA 19 20 21 µA -4.5 0 4.5 mV CURRENT CONTROL ISET Current Source IISET_ft ISET Current Source IISET_pt TJ = +15°C to +55°C Current Limit Amp Offset Voltage Vio_ft VISET - VISEN Current Limit Amp Offset Voltage Vio_pt VISET - VISEN, TJ = +15°C to +55°C -2 0 2 mV GATE DRIVE GATE Response Time to Severe OC pd_woc_amp VGATE to 10.8V - 100 - ns GATE Response Time to Overcurrent pd_oc_amp VGATE to 10.8V - 600 - ns IGATE VGATE to = 6V 10.8 14 16.7 µA 45 82 124 mA - 0.8 - A 8.9 9.6 10.2 V - V GATE Turn-On Current GATE Pull-Down Current OC_GATE_I_4V GATE Pull-Down Current (Note 3) Undervoltage Threshold WOC_GATE_I_4V Overcurrent Severe Overcurrent 12VUV_VTH GATE High Voltage 12VG GATE Voltage VDD + 5.7V VDD + 6.5V BIAS VDD Supply Current IVDD - 3 3.9 mA VDD POR Rising Threshold VDD_POR_L2H VDD Low to High 7 8.4 9 V VDD POR Falling Threshold VDD_POR_H2L VDD High to Low 6.9 8.1 8.7 V VDD POR Threshold Hysteresis VDD_POR_HYS VDD_POR_L2H - VDD_POR_H2L 0.1 0.3 0.5 V - 5 - V 2.5 3.2 - V Maximum PWRON Pull-Up Voltage PWRN_PUV Maximum External Pull-up Voltage PWRON Pull-Up Voltage PWRN_V PWRON Pin Open PWRON Rising Threshold PWR_Vth 1.1 1.7 2.35 V PWRON Hysteresis PWR_hys 125 170 250 mV PWRON Pull-Up Current PWRN_I 12.6 17 24 µA 17.2 20.5 25 µA - 20 - mA CURRENT REGULATION DURATION/POWER GOOD CTIM Charging Current CTIM_ichg0 VCTIM = 0V CTIM Fault Pull-Up Current (Note 3) Current Limit Time-Out Threshold Voltage Power Good Pull Down Current 4 CTIM_Vth CTIM Voltage 1.6 1.8 2.1 V PG_Ipd VOUT = 0.5V - 8 - mA FN6855.0 February 25, 2009 ISL6115A Description and Operation The ISL6115A is targeted for +12V single power supply distribution control for generic hot swap switching applications. This ICs features a highly accurate programmable current regulation (CR) level with programmable time delay to latch-off, and programmable soft-start turn-on ramp all set with a minimum of external passive components. It also includes severe OC protection that immediately shuts down the MOSFET switch should a rapid load current transient such as with a dead short cause the CR Vth to exceed the programmed level by 150mV. Additionally, it has an UV indicator and an OC latch indicator. The functionality of the PGOOD feature is enabled once the IC is biased, monitoring and reporting any UV condition on the ISEN pin. Upon initial power-up, the IC can either isolate the voltage supply from the load by holding the external N-Channel MOSFET switch off or apply the supply rail voltage directly to the load for true hot swap capability. The PWRON pin must be pulled low for the device to isolate the power supply from the load by holding the external N-Channel MOSFET off. With the PWRON pin held high or floating the IC will be in true hot swap mode. In both cases the IC turns on in a soft-start mode protecting the supply rail from sudden inrush current. At turn-on, the external gate capacitor of the N-Channel MOSFET is charged with a 11µA current source resulting in a programmable ramp (soft-start turn-on). The internal ISL6115A charge pump supplies the gate drive for the 12V supply switch driving that gate to ~VDD +6.5V. Load current passes through the external current sense resistor. When the voltage across the sense resistor exceeds the user programmed CR voltage threshold value, (see Table 1 for RISET programming resistor value and resulting nominal current regulation threshold voltage, VCR) the controller enters its current regulation mode. At this time, the time-out capacitor, on CTIM pin is charged with a 20µA current source and the controller enters the current limit time to latch-off period. The length of the current limit time to latch-off duration is set by the value of a single external capacitor (see Table 2) for CTIM capacitor value and resulting nominal current limited time-out to latch-off duration placed from the CTIM pin (pin 6) to ground. The programmed current level is held until either the OC event passes or the time-out period expires. If the former is the case then the N-Channel MOSFET is fully enhanced and the CTIM capacitor is discharged. Once CTIM charges to ~1.8V signaling that the time-out period has expired, an internal latch is set whereby the FET gate is quickly pulled to 0V turning off the N-Channel MOSFET switch, isolating the faulty load. 5 TABLE 1. RISET PROGRAMMING RESISTOR VALUE RISET RESISTOR NOMINAL CR VTH 10kΩ 200mV 4.99kΩ 100mV 2.5kΩ 50mV 1.25kΩ 25mV NOTE: Nominal Vth = RISET x 20µA. TABLE 2. CTIM CAPACITOR VALUE CTIM CAPACITOR NOMINAL CURRENT LIMITED PERIOD 0.022µF 2ms 0.047µF 4.4ms 0.1µF 9.3ms NOTE: Nominal time-out period = CTIM x 93kΩ. This IC responds to a severe overcurrent load (defined as a voltage across the sense resistor >150mV over the OC Vth set point) by immediately driving the N-Channel MOSFET gate to 0V in about 10µs. The gate voltage is then slowly ramped up turning on the N-Channel MOSFET to the programmed current regulation level; this is the start of the time-out period. Upon a UV condition, the PGOOD signal will pull low when connected through a resistor to the logic or VDD supply. This pin is a UV fault indicator. For an OC latch-off indication, monitor CTIM, pin 6. This pin will rise rapidly from 1.8V to VDD once the time-out period expires. See Figures 2 through 13 for graphs and waveforms related to text. The IC is reset after an OC latch-off condition by a low level on the PWRON pin and is turned on by the PWRON pin being driven high. Application Considerations Design applications where the CR Vth is set extremely low (25mV or less), there is a two-fold risk to consider. • There is the susceptibility to noise influencing the absolute CR Vth value. This can be addressed with a 100pF capacitor across the RSET resistor. • Due to common mode limitations of the overcurrent comparator, the voltage on the ISET pin must be 20mV above the IC ground either initially (from ISET*RSET) or before CTIM reaches time-out (from gate charge-up). If this does not happen, the IC may incorrectly report overcurrent fault at start-up when there is no fault. Circuits with high load capacitance and initially low load current are susceptible to this type of unexpected behavior. Do not signal nor pull-up the PWRON input to > 5V. Exceeding 6V on this pin will cause the internal charge pump to malfunction. During the soft-start and the time-out delay duration with the IC in its current limit mode, the VGS of the external N-Channel MOSFET is reduced driving the MOSFET switch into a (linear FN6855.0 February 25, 2009 ISL6115A region) high rDS(ON) state. Strike a balance between the CR limit and the timing requirements to avoid periods when the external N-Channel MOSFETs may be damaged or destroyed due to excessive internal power dissipation. Refer to the MOSFET SOA information in the manufacturer’s data sheet. When driving particularly large capacitive loads a longer soft-start time to prevent current regulation upon charging and a short CR time may offer the best application solution relative to reliability and FET MTF. . CORRECT INCORRECT TO ISEN AND RISET CURRENT SENSE RESISTOR Physical layout of RSENSE resistor is critical to avoid the possibility of false overcurrent occurrences. Ideally, trace routing between the RSENSE resistors and the IC is as direct and as short as possible with zero current in the sense lines (see Figure 1). FIGURE 1. SENSE RESISTOR PCB LAYOUT Typical Performance Curves 3.5 22.0 3.4 21.5 21.0 ISET (µA) Idd (mA) 3.3 3.2 3.1 3.0 20.0 19.5 19.0 2.9 2.8 20.5 18.5 -40 0 70 25 85 TEMPERATURE (°C) 18.0 125 FIGURE 2. VDD BIAS CURRENT 0 25 70 TEMPERATURE (°C) 85 125 FIGURE 3. ISET SOURCE CURRENT 20.8 1.82 20.6 20.4 1.81 CTIM - 0V 20.2 CTIM VTH (V) CTIM CHARGE CURRENT (µA) -40 20.0 19.8 19.6 19.4 19.2 1.80 1.79 1.78 19.0 18.8 -40 0 25 70 TEMPERATURE (°C) 85 FIGURE 4. CTIM CURRENT SOURCE 6 125 1.77 -40 0 25 70 TEMPERATURE (°C) 85 125 FIGURE 5. CTIM OC VOLTAGE THRESHOLD FN6855.0 February 25, 2009 ISL6115A Typical Performance Curves (Continued) GATE TURN-ON CURRENT (µA) 9.80 UVTH (V) 9.75 9.70 9.65 9.60 -40 0 25 70 85 125 16.0 15.5 15.0 14.5 14.0 13.5 13.0 12.5 12.0 -40 0 TEMPERATURE (°C) 22 8.2 21 VDD LO TO HI 8.0 7.9 7.8 7.7 VDD HI TO LO 7.5 -40 0 GATE VOLTAGE (V) POWER ON RESET (V) 8.3 7.6 85 125 FIGURE 7. GATE CHARGE CURRENT FIGURE 6. UV THRESHOLD 8.1 25 70 TEMPERATURE (°C) +85°C 20 +25°C 19 18 -40°C 17 16 15 14 25 70 TEMPERATURE (°C) 85 125 FIGURE 8. POWER-ON RESET VOLTAGE THRESHOLD PWRON 13 9 10 11 12 13 BIAS VOLTAGE (V) 14 15 FIGURE 9. GATE VOLTAGE vs BIAS and TEMPERATURE PWRON GATE GATE PGOOD PGOOD VOUT VOUT FIGURE 10. ISL6115A TURN-ON 7 FIGURE 11. ISL6115A TURN-OFF FN6855.0 February 25, 2009 ISL6115A Typical Performance Curves (Continued) ILOAD ILOAD GATE GATE VOUT VOUT CTIM CTIM FIGURE 12. IOC REGULATION and TURN-OFF ISL6115AEVAL1Z Board The ISL6115AEVAL1Z is default provided as a +12V high side switch controller with the CR level set at ~2.5A. See Figure 11 for ISL6115AEVAL1Z schematic and Table 3 for BOM. Bias and load connection points are provided along with test points for each IC pin. With J1 installed the ISL6115A will be biased from the +12V supply (VIN) being switched. Connect the load to VLOAD+. PWRON pin pulls high internally enabling the ISL6115A if not driven low via PWRON test point or J2. VOUT R3 Reconfiguring the ISL6115AEVAL1Z board for a higher CR level can be done by changing the RSENSE and/or RISET resistor values as the provided FET is rated for a much higher current. J2 2 3 PWRON 8 1 ISL6115A 7 U2 6 4 U1 With R3 = 1.24kΩ the CR Vth is set to 24.8mV and with the 10mΩ sense resistor (R1) the ISL6115AEVAL1Z has a nominal CR level of 2.5~A. The 0.01µF delay time to latch-off capacitor results in a nominal 1ms before latch-off of output after an OC event. AGND VLOAD+ R1 FIGURE 13. WOC TURN-OFF and RESTART PGOOD CTIM 5 C3 R2 R4 C2 C1 J1 VIN +12V VBIAS VBIAS FIGURE 14. ISL6115AEVAL1Z HIGH SIDE SWITCH APPLICATION and PHOTOGRAPH 8 FN6855.0 February 25, 2009 ISL6115A TABLE 3. BILL OF MATERIALS, ISL6115AEVAL1Z COMPONENT DESIGNATOR COMPONENT NAME COMPONENT DESCRIPTION U1 N-FET 11.5mΩ, 30V, 11.5A Logic Level N-Channel Power MOSFET or equivalent R1 Load Current Sense Resistor WSL-2512 10mΩ 1W Metal Strip Resistor R2 Gate Stability Resistor 20Ω 0603 Chip Resistor R3 Overcurrent Voltage Threshold Set Resistor 1.24kΩ 0603 Chip Resistor (Vth = 24.8mV) R4 PGOOD Pull up Resistor 10kΩ 0603 Chip Resistor C1 Gate Timing Capacitor 0.001µF 0402 Chip Capacitor (<2ms) C2 IC Decoupling Capacitor 0.1µF 0402 Chip Capacitor C3 Time Delay Set Capacitor 0.01µF 0402 Chip Capacitor (1ms) J1 Bias Voltage Selection Jumper Install if switched rail voltage is = +12V. Remove and provide separate +12V bias voltage to U2 via VBIAS if ISL6116, ISL6117 or ISL6120 is being evaluated. J2 PWRON Disable Install J2 to disable U2. Connects PWRON to GND. 9 FN6855.0 February 25, 2009 ISL6115A Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) N 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES E SYMBOL -B1 2 3 L SEATING PLANE -A- A D h x 45° -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M MIN MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 e α B S 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N a NOTES: MILLIMETERS 8 0° 8 8° 0° 7 8° 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. Rev. 1 6/05 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 10 FN6855.0 February 25, 2009