Datasheet

DATASHEET
3A, Radiation Hardened, Positive, Ultra Low Dropout
Regulator
ISL75051SEH
Features
The ISL75051SEH is a radiation hardened low-voltage,
high-current, single-output LDO specified for up to 3.0A of
continuous output current. These devices operate over an input
voltage range of 2.2V to 6.0V and are capable of providing
output voltages of 0.8V to 5.0V adjustable based on resistor
divider setting. Dropout voltages as low as 65mV can be
realized using the device.
• DLA SMD#5962-11212
• Output current up to 3.0A at TJ = +150°C
• Output accuracy ±1.5% over MIL temp range
• Ultra low dropout:
- 65mV (Typ) dropout at 1.0A
- 225mV (Typ) dropout at 3.0A
The OCP pin allows the short circuit output current limit
threshold to be programmed by means of a resistor from the
OCP pin to GND. The OCP setting range is from 0.5A minimum
to 8.5A maximum. The resistor sets the constant current
threshold for the output under fault conditions. The thermal
shutdown disables the output if the device temperature
exceeds the specified value. It subsequently enters an ON/OFF
cycle until the fault is removed. The ENABLE feature allows the
part to be placed into a low current shutdown mode that
typically draws about 1µA. When enabled, the device operates
with a typical low ground current of 11mA, which provides for
operation with low quiescent power consumption.
• Noise of 100µVRMS from 300Hz to 300kHz
• SET mitigation with no added filtering/diodes
• Input supply range: 2.2V to 6.0V
• Fast load transient response
• Shutdown current of 1µA (Typ)
• Output adjustable using external resistors
• PSRR 66dB (Typ) at 1kHz
• Enable and PGood feature
• Programmable soft-start/in-rush current limiting
The device is optimized for fast transient response and single
event effects. This reduces the magnitude of SET seen on the
output. Additional protection diodes and filters are not needed.
The device is stable with tantalum capacitors as low as 47µF
and provides excellent regulation all the way from no load to
full load. Programmable soft-start allows the user to program
the in-rush current by means of the decoupling capacitor value
used on the BYP pin.
• Adjustable overcurrent limit from 0.5A to 8.5A
• Over-temperature shutdown
• Stable with 47µF min tantalum capacitor
• 18 Ld ceramic flatpack package
• Radiation environment
- High dose rate (50-300rad(Si)/s) . . . . . . . . . . 100krad(Si)
- Low dose rate (0.01rad(Si)/s) . . . . . . . . . . . . 100krad(Si)*
*Product capability established by initial characterization. The
"EH" version is acceptance tested on a wafer-by-wafer basis to
50 krad(Si) at low dose rate
Applications
• LDO regulator for space application
• DSP, FPGA and µP core power supplies
Related Literature
• Post-regulation of switched mode power supplies
• Down-hole drilling
• AN1947, “Intersil’s Radiation Hardened Low Power FPGA
Power Solutions”
0.30
+150°C
EN
EN
BYP
OCP
0.1µF
ADJ
ISL75051SEH
VIN
220µF
VOUT
VIN
VOUT
PG
GND
R1
0.1µF
0.1µF
2.67k
VIN
4.7nF
PG
R2
100pF
220µF
DROPOUT VOLTAGE (V)
ROCP
0.25
+125°C
0.20
0.15
+25°C
0.10
0.05
0.00
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
IOUT (A)
FIGURE 1. TYPICAL APPLICATION
December 15, 2014
FN8294.5
1
FIGURE 2. DROPOUT vs IOUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2012, 2014. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL75051SEH
Block Diagram
VIN
CURRENT
LIMIT ADJ
OCP
520MV
POWER
PMOS
REFERENCE
BIAS
BYPASS
VOUT
CURRENT
LIMIT
THERMAL
SHUTDOWN
LEVEL
SHIFT
ENABLE
ADJ
VADJ
PGOOD
DELAY
450mV
GND
Typical Applications
EN
EN
10
9
BYP
OCP
11
8
ADJ
VIN
12
7
VOUT
VIN
13
6
VOUT
VIN
14
5
ISL75051SEH
VOUT
VIN
15
4
VOUT
VIN
16
3
VOUT
VIN
17
2
VOUT
PG
18
1
GND
511
0.2µF
VIN
VOUT
220µF
0.1µF
0.1µF
4.32k
220µF
2.67k
4.7n
VIN
2.26k
5.49k
100pF
PG
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ISL75051SEH
Pin Configuration
ISL75051SEH
(18 LD CDFP)
TOP VIEW
GND
1
18
PG
VOUT
2
17
VIN
VOUT
3
16
VIN
VOUT
4
15
VIN
VOUT
5
14
VIN
VOUT
6
13
VIN
VOUT
7
12
VIN
VADJ
8
11
OCP
BYP
9
10
EN
GND
NOTE: The ESD triangular mark is indicative of pin #1. It is a part of the device
marking and is placed on the lid in the quadrant where pin #1 is located.
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
12, 13, 14
15, 16, 17
VIN
Input supply pins.
18
PG
VOUT in regulation signal. Logic low defines when VOUT is not in regulation. Must be grounded if not used.
1
GND
GND pin.
2, 3, 4
5, 6, 7
VOUT
Output voltage pins.
8
VADJ
VADJ pin allows VOUT to be programmed with an external resistor divider.
9
BYP
To filter the internal reference, connect a 0.1µF capacitor from BYP pin to GND.
10
EN
VIN independent chip enable. TTL and CMOS compatible.
11
OCP
Allows current limit to be programmed with an external resistor.
Top Lid
GND
The top lid is connected to GND pin of the package.
Ordering Information
ORDERING NUMBER
(Notes 1, 2)
PART NUMBER
TEMP RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG
DWG. #
5962R1121202VXC
ISL75051SEHVF
-55 to +125
18 Ld CDFP
K18.D
5962R1121202V9A
ISL75051SEHVX
-55 to +125
Die
5962R1121202VYC
ISL75051SEHVFE
-55 to +125
18 Ld CDFP with Bottom Metal K18.E
ISL75051SEHFE/PROTO
ISL75051SEHFE/PROTO
-55 to +125
18 Ld CDFP with Bottom Metal K18.E
ISL75051SEHX/SAMPLE
ISL75051SEHX/SAMPLE
-55 to +125
Die
ISL75051SRHEVAL1Z
Evaluation Board
NOTES:
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in this
“Ordering Information” table must be used when ordering.
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ISL75051SEH
Absolute Maximum Ratings
Thermal Information
VIN Relative to GND (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to + 6.7V
VOUT Relative to GND (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to + 6.7V
PG, EN, OCP/ADJ Relative to GND (Note 3). . . . . . . . . . . . -0.3 to + 6.7VDC
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
ESD Rating
Human Body Model (Tested per MIL-PRF-883 3015.7). . . . . . . . . .2.5kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 250V
Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . . . 1kV
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
18 Ld CDFP Package (Notes 7, 8) . . . . . . .
28
4
18 Ld CDFP Package with Bottom
Metal and Solder Mount (Notes 7, 8). . .
24
3.3
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions (Note 4)
Maximum Total Dose
Dose Rate = 50-300rad(Si)/s. . . . . . . . . . . . . . . . . . . . . . . . . 100krad (Si)
Dose Rate = 0.01rad(Si)/s (Note 5) . . . . . . . . . . . . . . . . . . . . 100krad (Si)
SEE Performance
SET (VOUT < ±5% During Events) (Note 6) . . . . . . . . . . .86MeV•cm2/mg
SEL/SEB (No Latchup/Burnout. . . . . . . . . . . . . . . . . . . .86MeV•cm2/mg
Ambient Temperature Range (TA) . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Junction Temperature (TJ) (Note 3). . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
VIN Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2V to 6.0V
VOUT Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.8V to 5.0V
PG, EN, OCP/ADJ Relative to GND . . . . . . . . . . . . . . . . . . . . . . . 0V to +6.0V
Radiation Information
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. Extended operation at these conditions may compromise reliability. Exceeding these limits will result in damage. Recommended operating conditions
define limits where specifications are guaranteed.
4. Refer to “Thermal Guidelines” on page 16.
5. Product capability established by initial characterization. The "EH" version is acceptance tested on a wafer-by-wafer basis to 50 krad(Si) at low dose
rate.
6. Specify EVAL test conditions for SET/SEB/SEL here.
7. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379
8. For JC, the “case temp” location is the center of the package underside.
9. The device can work down to VOUT = 0.8V; however, the SET performance of < ±5% at LET = 86MeV•cm2/mg is guaranteed at VOUT = >1.5V only.
SET tests performed with 220µF 10V 25mΩ and 0.1µF CDR04 capacitor on the input and output.
Electrical Specifications
Unless otherwise noted, all parameters are guaranteed over the following specified conditions: VIN = VOUT +
0.4V, VOUT = 1.8V, CIN = COUT = 220µF 25mΩ and 0.1µF X7R, TJ = +25°C, IL = 0A. Applications must follow thermal guidelines of the package to
determine worst-case junction temperature (see Note 13). Boldface limits apply across the operating temperature range, -55°C to +125°C. Pulse load
techniques used by ATE to ensure TJ = TA defines guaranteed limits.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 10)
TYP
MAX
(Note 10)
UNITS
-1.5
0.2
1.5
%
-1.5
0.2
1.5
%
514.8
520
525.2
mV
DC CHARACTERISTICS
DC Output Voltage Accuracy
VOUT
VOUT resistor adjust to 0.52V, 1.5V and 1.8V
2.2V < VIN < 3.6V; 0A < ILOAD < 3.0A
VOUT resistor adjust to 5.0V
VOUT + 0.4V < VIN < 6.0V; 0A < ILOAD < 3.0A
VADJ Pin Voltage
VADJ
2.2V < VIN < 6.0V; ILOAD = 0A
BYP Pin
VBYP
2.2V < VIN < 6.0V; ILOAD = 0A
520
DC Input Line Regulation
2.2V < VIN < 3.6V, VOUT = 1.5V, +25°C and -55°C
(Note 11)
1.13
3.5
mV
DC Input Line Regulation
2.2V < VIN < 3.6V, VOUT = 1.5V, +125°C (Note 11)
1.13
8.0
mV
DC Input Line Regulation
2.2V < VIN < 3.6V, VOUT = 1.8V, +25°C and -55°C
(Note 11)
1.62
3.5
mV
DC Input Line Regulation
2.2V < VIN < 3.6V, VOUT = 1.8V, +125°C (Note 11)
1.62
10.5
mV
DC Input Line Regulation
VOUT + 0.4V < VIN < 6.0V, VOUT = 5.0V (Note 11)
12.50
20.0
mV
DC Output Load Regulation
VOUT = 1.5V; 0A < ILOAD < 3.0A, VIN = VOUT + 0.4V
(Note 11)
-0.8
-0.1
mV
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-4.0
mV
FN8294.5
December 15, 2014
ISL75051SEH
Electrical Specifications
Unless otherwise noted, all parameters are guaranteed over the following specified conditions: VIN = VOUT +
0.4V, VOUT = 1.8V, CIN = COUT = 220µF 25mΩ and 0.1µF X7R, TJ = +25°C, IL = 0A. Applications must follow thermal guidelines of the package to
determine worst-case junction temperature (see Note 13). Boldface limits apply across the operating temperature range, -55°C to +125°C. Pulse load
techniques used by ATE to ensure TJ = TA defines guaranteed limits. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 10)
TYP
MAX
(Note 10)
UNITS
DC Output Load Regulation
VOUT = 1.8V; 0A < ILOAD < 3.0A, VIN = VOUT + 0.4V
(Note 11)
-4.0
-1.2
-0.05
mV
DC Output Load Regulation
VOUT = 5.0V; 0A < ILOAD < 3.0A, VIN = VOUT + 0.4V
(Note 11)
-15.0
-6.0
-0.05
mV
VADJ Input Current
VADJ = 0.5V
1
µA
Ground Pin Current
IQ
VOUT = 1.5V; ILOAD = 0A, VIN = 2.2V
11
12
mA
Ground Pin Current
IQ
VOUT = 5.0V; ILOAD = 0A, VIN = 6.0V
16
18
mA
Ground Pin Current
IQ
VOUT = 1.5V; ILOAD = 3.0A, VIN = 2.2V
11
13
mA
Ground Pin Current
IQ
VOUT = 5.0V; ILOAD = 3.0A, VIN = 6.0V
16
18
mA
ENABLE Pin = 0V, VIN = 6.0V
1
10
µA
Dropout Voltage
VDO
ILOAD = 1.0A, VOUT = 2.5V (Note 12)
65
100
mV
Dropout Voltage
VDO
ILOAD = 2.0A, VOUT = 2.5V (Note 12)
140
200
mV
Dropout Voltage
VDO
ILOAD = 3.0A, VOUT = 2.5V (Note 12)
225
300
mV
Output Short Circuit Current
ISCL
VOUT = 0V, VIN = 2.2V, RSET = 5.11k
1.1
A
Output Short Circuit Current
ISCL
VOUT = 0V, VIN = 6.0V, RSET = 5.11k
1.2
A
Output Short Circuit Current
ISCH
VOUT = 0V, VIN = 2.2V, RSET = 511Ω
5.7
A
Output Short Circuit Current
ISCH
VOUT = 0V, VIN = 6.0V, RSET = 511Ω
6.2
A
Thermal Shutdown Temperature
TSD
VOUT + 0.4V < VIN < 6.0V
175
°C
Thermal Shutdown Hysteresis
(Rising Threshold)
TSDn
VOUT + 0.4V < VIN < 6.0V
25
°C
Input Supply Ripple Rejection
PSRR
VP-P = 300mV, f = 1kHz, ILOAD = 3A; VIN = 2.5V,
VOUT = 1.8V
66
dB
Input Supply Ripple Rejection
PSRR
VP-P = 300mV, f = 100kHz, ILOAD = 3A; VIN = 2.5V,
VOUT = 1.8V
30
dB
Ground Pin Current in Shutdown
ISHDN
AC CHARACTERISTICS
42
Phase Margin
PM
VOUT = 1.8V, CL = 220µF Tantalum
70
dB
Gain Margin
GM
VOUT = 1.8V, CL = 220µF Tantalum
16
dB
ILOAD = 10mA, BW = 300Hz < f < 300kHz, BYPASS
to GND capacitor = 0.2µF
100
µVRMS
Output Noise Voltage
DEVICE START-UP CHARACTERISTICS: ENABLE PIN
Rising Threshold
2.2V < VIN < 6.0V
0.6
0.9
1.2
V
Falling Threshold
2.2V < VIN < 6.0V
0.47
0.7
0.9
V
Enable Pin Leakage Current
VIN = 6.0V, EN = 6.0V
1
µA
Enable Pin Propagation Delay
VIN = 2.2V, EN rise to IOUT rise
225
300
450
µs
Hysteresis
Must be independent of VIN; 2.2V < VIN < 6.0V
90
200
318
mV
2.2V < VIN < 6.0V
85
90
96
%
DEVICE START-UP CHARACTERISTICS: PG PIN
PG Rising Threshold
PG Falling Threshold
2.2V < VIN < 6.0V
82
88
93
%
PG Hysteresis
2.2V < VIN < 6.0V
2.5
3.2
4.0
%VOUT
PG Low Voltage
ISINK = 1mA
35
100
mV
PG Low Voltage
ISINK = 6mA
185
400
mV
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Electrical Specifications
Unless otherwise noted, all parameters are guaranteed over the following specified conditions: VIN = VOUT +
0.4V, VOUT = 1.8V, CIN = COUT = 220µF 25mΩ and 0.1µF X7R, TJ = +25°C, IL = 0A. Applications must follow thermal guidelines of the package to
determine worst-case junction temperature (see Note 13). Boldface limits apply across the operating temperature range, -55°C to +125°C. Pulse load
techniques used by ATE to ensure TJ = TA defines guaranteed limits. (Continued)
PARAMETER
SYMBOL
PG Leakage Current
TEST CONDITIONS
VIN = 6.0V, PG = 6.0V
MIN
(Note 10)
TYP
MAX
(Note 10)
UNITS
0.01
1
µA
NOTES:
10. Parameters with MIN and/or MAX limits are 100% tested at -55°C, +25°C and +125°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
11. Line and Load Regulation done under pulsed condition for T<10ms.
12. Dropout is defined as the difference between the supply VIN and VOUT, when the supply produces a 2% drop in VOUT from its nominal value. Data
measured within a 3ms period.
13. Please refer to “Applications Information” on page 14 of the datasheet and Tech Brief TB379.
High Dose Rate Post Radiation Characteristics TA = +25°C, unless otherwise noted. This data is typical test data post
radiation exposure at a rate of 50 to 300rad(Si)/s. This data is intended to show typical parameter shifts due to high dose rate radiation (see Note 14).
These are not limits nor are they guaranteed.
ITEM #
DESCRIPTION
CONDITION
0k RAD
100k RAD
UNITS
1
DC Output Voltage Accuracy
VOUT = 0.52V; VIN = 2.2V; IOUT = 0A
0.520575
0.520975
V
2
DC Output Voltage Accuracy
VOUT = 0.52V; VIN = 2.2V; IOUT = 3A
0.520000
0.520300
V
3
DC Output Voltage Accuracy
VOUT = 0.52V; VIN = 3.6V; IOUT = 0A
0.520650
0.520813
V
4
DC Output Voltage Accuracy
VOUT = 0.52V; VIN = 3.6V; IOUT = 3A
0.519963
0.520113
V
5
DC Output Voltage Accuracy
VOUT = 1.5V; VIN = 2.2V; IOUT = 0A
1.500813
1.501325
V
6
DC Output Voltage Accuracy
VOUT = 1.5V; VIN = 2.2V; IOUT = 3A
1.499250
1.499800
V
7
DC Output Voltage Accuracy
VOUT = 1.5V; VIN = 3.6V; IOUT = 0A
1.500550
1.500938
V
8
DC Output Voltage Accuracy
VOUT = 1.5V; VIN = 3.6V; IOUT = 3A
1.499075
1.499388
V
9
DC Output Voltage Accuracy
VOUT = 1.8V; VIN = 2.2V; IOUT = 0A
1.802288
1.803613
V
10
DC Output Voltage Accuracy
VOUT = 1.8V; VIN = 2.2V; IOUT = 3A
1.800900
1.801825
V
11
DC Output Voltage Accuracy
VOUT = 1.8V; VIN = 3.6V; IOUT = 0A
1.802900
1.803338
V
12
DC Output Voltage Accuracy
VOUT = 1.8V; VIN = 3.6V; IOUT = 3A
1.801175
1.801550
V
13
DC Output Voltage Accuracy
VOUT = 5.0V; VIN = 5.4V; IOUT = 0A
5.018250
5.018850
V
14
DC Output Voltage Accuracy
VOUT = 5.0V; VIN = 5.4V; IOUT = 3A
5.013050
5.013450
V
15
DC Output Voltage Accuracy
VOUT = 5.0V; VIN = 6.0V; IOUT = 0A
5.023838
5.024188
V
16
DC Output Voltage Accuracy
VOUT = 5.0V; VIN = 6.0V; IOUT = 3A
5.016550
5.016763
V
17
VADJ Pin Voltage
VOUT = 0.52V; VIN = 2.2V
0.520625
0.521000
V
18
VADJ Pin Voltage
VOUT = 0.52V; VIN = 3.6V
0.520700
0.520863
V
19
VADJ Pin Voltage
VOUT = 0.52V; VIN = 5.5V
0.521125
0.521200
V
20
VADJ Pin Voltage
VOUT = 1.5V; VIN = 2.2V
0.520800
0.521013
V
21
VADJ Pin Voltage
VOUT = 1.5V; VIN = 3.6V
0.520688
0.520838
V
22
VADJ Pin Voltage
VOUT = 1.5V; VIN = 5.5V
0.521025
0.521113
V
23
VADJ Pin Voltage
VOUT = 1.8V; VIN = 2.2V
0.520563
0.520925
V
24
VADJ Pin Voltage
VOUT = 1.8V; VIN = 3.6V
0.520688
0.520838
V
25
VADJ Pin Voltage
VOUT = 1.8V; VIN = 5.5V
0.521038
0.521100
V
26
VADJ Pin Voltage
VOUT = 5.0V; VIN = 5.4V
0.521000
0.521088
V
27
VADJ Pin Voltage
VOUT = 5.0V; VIN = 6.0V
0.521575
0.521625
V
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High Dose Rate Post Radiation Characteristics TA = +25°C, unless otherwise noted. This data is typical test data post
radiation exposure at a rate of 50 to 300rad(Si)/s. This data is intended to show typical parameter shifts due to high dose rate radiation (see Note 14).
These are not limits nor are they guaranteed. (Continued)
ITEM #
DESCRIPTION
CONDITION
0k RAD
100k RAD
UNITS
28
DC Input Line Regulation
2.2V < VIN < 3.6V, VOUT = 1.5V
-0.257100
-0.408960
mV
29
DC Input Line Regulation
2.2V < VIN < 3.6V, VOUT = 1.8V
0.611613
-0.281990
mV
30
DC Input Line Regulation
VOUT + 0.4V < VIN < 6.0V, VOUT = 5.0V
5.600700
5.313688
mV
31
DC Output Load Regulation
VOUT = 1.5V; 0A < ILOAD < 3.0A, VIN = VOUT + 0.4V
-1.559875
-1.549760
mV
32
DC Output Load Regulation
VOUT = 1.8V; 0A < ILOAD < 3.0A, VIN = VOUT + 0.4V
-1.390263
-1.784640
mV
33
DC Output Load Regulation
VOUT = 5.0V; 0A < ILOAD < 3.0A, VIN = VOUT + 0.4V
-5.201513
-5.418710
mV
34
Feedback Input Current
VADJ = 0.5V
-0.036650
-0.040980
µA
35
Ground Pin Current
VOUT = 1.5V; ILOAD = 0A, VIN = 2.2V
10.715763
10.758810
mA
36
Ground Pin Current
VOUT = 1.5V; ILOAD = 3.0A, VIN = 2.2V
12.016163
12.067510
mA
37
Ground Pin Current
VOUT = 5.0V; ILOAD = 0A, VIN = 6.0V
15.796488
15.781190
mA
38
Ground Pin Current
VOUT = 5.0V; ILOAD = 3.0A, VIN = 6.0V
17.178913
17.166440
mA
39
Ground Pin Current in Shutdown
ENABLE Pin = 0V, VIN = 6.0V
0.811625
0.752100
µA
40
Dropout Voltage
ILOAD = 1.0A, VOUT = 2.5V
62.588600
63.660340
mV
41
Dropout Voltage
ILOAD = 2.0A, VOUT = 2.5V
134.520040
135.703500
mV
42
Dropout Voltage
ILOAD = 3.0A, VOUT = 2.5V
215.603360
216.651900
mV
43
Output Short Circuit Current
VOUT = 0V, VIN = 2.2V, RSET = 5.11k
1.204063
1.323238
A
44
Output Short Circuit Current
VOUT = 0V, VIN = 2.2V, RSET = 511Ω
5.903613
6.058613
A
45
Output Short Circuit Current
VOUT = 0V, VIN = 6.0V, RSET = 5.11k
1.333325
1.439638
A
46
Output Short Circuit Current
VOUT = 0V, VIN = 6.0V, RSET = 511Ω
6.389913
6.635563
A
47
PSRR
VP-P = 300mV, f = 1kHz, ILOAD = 3A; VIN = 2.5V, VOUT = 1.8V
65.428638
66.410750
dB
48
Enable Rising Threshold
VIN = 2.2V
0.863700
0.824150
V
49
Enable Rising Threshold
VIN = 6.0V
0.911300
0.875263
V
50
Enable Falling Threshold
VIN = 2.2V
0.678400
0.636800
V
51
Enable Falling Threshold
VIN = 6.0V
0.724475
0.684400
V
52
Enable Pin Leakage Current
VIN = 6.0V, EN = 0V
-0.028513
-0.029950
µA
53
Enable Pin Leakage Current
VIN = 6.0V, EN = 6.0V
-0.030638
-0.038110
µA
54
Enable Hysterisis
VIN = 2.2V
185.370000
187.374000
mV
55
Enable Hysterisis
VIN = 6.0V
186.874000
190.881600
mV
56
Enable Pin Propagation Delay
VIN = 2.2V, EN rise to IOUT rise
305.015280
290.839200
µs
57
PG Rising Threshold
VIN = 2.2V
89.542938
88.811230
%
58
PG Rising Threshold
VIN = 6.0V
91.083838
90.396230
%
59
PG Falling Threshold
VIN = 2.2V
86.793125
86.074360
%
60
PG Falling Threshold
VIN = 6.0V
87.840925
87.165790
%
61
PG Hysteresis
VIN = 2.2V
2.749825
2.736875
%
62
PG Hysteresis
VIN = 6.0V
3.242925
3.230450
%
63
PG Low Voltage
ISINK = 1mA
31.426938
31.570940
mV
64
PG Low Voltage
ISINK = 6mA
177.107950
178.578800
mV
65
PG Leakage Current
VIN = 6.0V, PG = 6.0V
-0.001550
-0.001560
µA
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7
FN8294.5
December 15, 2014
ISL75051SEH
Low Dose Rate Post Radiation Characteristics TA = +25°C, unless otherwise noted. This data is typical test data post
radiation exposure at a rate of 10mrad(Si)/s. This data is intended to show typical parameter shifts due to low dose rate radiation (see Note 14). These are
not limits nor are they guaranteed.
ITEM #
DESCRIPTION
CONDITION
0k RAD
50k RAD
100k RAD
UNITS
1
DC Output Voltage Accuracy
VOUT = 0.52V; VIN = 2.2V; IOUT = 0A
0.521050
0.521150
0.521600
V
2
DC Output Voltage Accuracy
VOUT = 0.52V; VIN = 2.2V; IOUT = 3A
0.520500
0.520600
0.520950
V
3
DC Output Voltage Accuracy
VOUT = 0.52V; VIN = 3.6V; IOUT = 0A
0.521050
0.521350
0.521750
V
4
DC Output Voltage Accuracy
VOUT = 0.52V; VIN = 3.6V; IOUT = 3A
0.520450
0.520600
0.521000
V
5
DC Output Voltage Accuracy
VOUT = 1.5V; VIN = 2.2V; IOUT = 0A
1.502450
1.503050
1.503200
V
6
DC Output Voltage Accuracy
VOUT = 1.5V; VIN = 2.2V; IOUT = 3A
1.500950
1.501400
1.502100
V
7
DC Output Voltage Accuracy
VOUT = 1.5V; VIN = 3.6V; IOUT = 0A
1.501950
1.502900
1.503650
V
8
DC Output Voltage Accuracy
VOUT = 1.5V; VIN = 3.6V; IOUT = 3A
1.500500
1.501400
1.502150
V
9
DC Output Voltage Accuracy
VOUT = 1.8V; VIN = 2.2V; IOUT = 0A
1.804150
1.805050
1.806100
V
10
DC Output Voltage Accuracy
VOUT = 1.8V; VIN = 2.2V; IOUT = 3A
1.802850
1.803650
1.804800
V
11
DC Output Voltage Accuracy
VOUT = 1.8V; VIN = 3.6V; IOUT = 0A
1.804450
1.805850
1.806600
V
12
DC Output Voltage Accuracy
VOUT = 1.8V; VIN = 3.6V; IOUT = 3A
1.802850
1.804100
1.804900
V
13
DC Output Voltage Accuracy
VOUT = 5.0V; VIN = 5.4V; IOUT = 0A
5.022600
5.027250
5.028500
V
14
DC Output Voltage Accuracy
VOUT = 5.0V; VIN = 5.4V; IOUT = 3A
5.017200
5.022200
5.023350
V
15
DC Output Voltage Accuracy
VOUT = 5.0V; VIN = 6.0V; IOUT = 0A
5.028050
5.032500
5.034350
V
16
DC Output Voltage Accuracy
VOUT = 5.0V; VIN = 6.0V; IOUT = 3A
5.020950
5.025500
5.027050
V
17
VADJ Pin Voltage
VOUT = 0.52V; VIN = 2.2V
0.521150
0.521300
0.521600
V
18
VADJ Pin Voltage
VOUT = 0.52V; VIN = 3.6V
0.521150
0.521400
0.521700
V
19
VADJ Pin Voltage
VOUT = 0.52V; VIN = 5.5V
0.521550
0.521800
0.522150
V
20
VADJ Pin Voltage
VOUT = 1.5V; VIN = 2.2V
0.521400
0.521500
0.521550
V
21
VADJ Pin Voltage
VOUT = 1.5V; VIN = 3.6V
0.521150
0.521400
0.521700
V
22
VADJ Pin Voltage
VOUT = 1.5V; VIN = 5.5V
0.521450
0.521800
0.522050
V
23
VADJ Pin Voltage
VOUT = 1.8V; VIN = 2.2V
0.521050
0.521200
0.521550
V
24
VADJ Pin Voltage
VOUT = 1.8V; VIN = 3.6V
0.521150
0.521400
0.521750
V
25
VADJ Pin Voltage
VOUT = 1.8V; VIN = 5.5V
0.521450
0.521800
0.522000
V
26
VADJ Pin Voltage
VOUT = 5.0V; VIN = 5.4V
0.521400
0.521800
0.521950
V
27
VADJ Pin Voltage
VOUT = 5.0V; VIN = 6.0V
0.522000
0.522250
0.522600
V
28
DC Input Line Regulation
2.2V < VIN < 3.6V, VOUT = 1.5V
-0.284500
-0.176150
0.158400
mV
29
DC Input Line Regulation
2.2V < VIN < 3.6V, VOUT = 1.8V
0.520000
0.551100
0.356200
mV
30
DC Input Line Regulation
VOUT + 0.4V < VIN < 6.0V, VOUT = 5.0V
5.792850
5.296750
5.315300
mV
31
DC Output Load Regulation
VOUT = 1.5V; 0A < ILOAD < 3.0A, VIN = VOUT + 0.4V
-1.525700
-1.571300
-1.219950
mV
32
DC Output Load Regulation
VOUT = 1.8V; 0A < ILOAD < 3.0A, VIN = VOUT + 0.4V
-1.314200
-1.447200
-1.372050
mV
33
DC Output Load Regulation
VOUT = 5.0V; 0A < ILOAD < 3.0A, VIN = VOUT + 0.4V
-5.026850
-5.007050
-4.816750
mV
34
Feedback Input Current
VADJ = 0.5V
-0.011650
-0.030300
-0.036550
µA
35
Ground Pin Current
VOUT = 1.5V; ILOAD = 0A, VIN = 2.2V
10.665000
10.658900
10.621750
mA
36
Ground Pin Current
VOUT = 1.5V; ILOAD = 3.0A, VIN = 2.2V
11.977100
12.015600
11.948450
mA
37
Ground Pin Current
VOUT = 5.0V; ILOAD = 0A, VIN = 6.0V
15.814550
15.840150
15.771750
mA
38
Ground Pin Current
VOUT = 5.0V; ILOAD = 3.0A, VIN = 6.0V
17.223200
17.224650
17.189200
mA
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8
FN8294.5
December 15, 2014
ISL75051SEH
Low Dose Rate Post Radiation Characteristics TA = +25°C, unless otherwise noted. This data is typical test data post
radiation exposure at a rate of 10mrad(Si)/s. This data is intended to show typical parameter shifts due to low dose rate radiation (see Note 14). These are
not limits nor are they guaranteed. (Continued)
ITEM #
DESCRIPTION
CONDITION
0k RAD
50k RAD
100k RAD
UNITS
39
Ground Pin Current in Shutdown
ENABLE Pin = 0V, VIN = 6.0V
0.430300
0.601500
0.707900
µA
40
Dropout Voltage
ILOAD = 1.0A, VOUT = 2.5V
62.801250
62.431600
65.466000
mV
41
Dropout Voltage
ILOAD = 2.0A, VOUT = 2.5V
132.799650 133.294300 138.742500
mV
42
Dropout Voltage
ILOAD = 3.0A, VOUT = 2.5V
214.477050
mV
43
Output Short Circuit Current
VOUT = 0V, VIN = 2.2V, RSET = 5.11k
1.178050
1.199850
1.224300
A
44
Output Short Circuit Current
VOUT = 0V, VIN = 2.2V, RSET = 511Ω
5.838350
5.898050
5.750950
A
45
Output Short Circuit Current
VOUT = 0V, VIN = 6.0V, RSET = 5.11k
1.317450
1.338450
1.361150
A
46
Output Short Circuit Current
VOUT = 0V, VIN = 6.0V, RSET = 511Ω
6.375650
6.464150
6.539300
A
47
PSRR
VP-P = 300mV, f = 1kHz, ILOAD = 3A; VIN = 2.5V,
VOUT = 1.8V
64.103100
67.373400
65.407000
dB
48
Enable Rising Threshold
VIN = 2.2V
0.867700
0.835700
0.827700
V
49
Enable Rising Threshold
VIN = 6.0V
0.915800
0.905800
0.893800
V
50
Enable Falling Threshold
VIN = 2.2V
0.681400
0.671300
0.661300
V
51
Enable Falling Threshold
VIN = 6.0V
0.727500
0.715400
0.707400
V
52
Enable Pin Leakage Current
VIN = 6.0V, EN = 0V
-0.004900
-0.025200
-0.030100
µA
53
Enable Pin Leakage Current
VIN = 6.0V, EN = 6.0V
-0.009750
-0.024850
-0.029650
µA
54
Enable Hysterisis
VIN = 2.2V
184.368000 166.332000 168.336000
mV
55
Enable Hysterisis
VIN = 6.0V
188.377000 190.381000 188.377000
mV
56
Enable Pin Propagation Delay
VIN = 2.2V, EN rise to IOUT rise
304.015700
299.771700 296.604250
µs
57
PG Rising Threshold
VIN = 2.2V
88.455750
88.057850
88.741300
%
58
PG Rising Threshold
VIN = 6.0V
89.994350
89.499600
90.142250
%
59
PG Falling Threshold
VIN = 2.2V
85.755650
85.356800
85.996150
%
60
PG Falling Threshold
VIN = 6.0V
86.812350
86.316300
86.870500
%
61
PG Hysteresis
VIN = 2.2V
2.701500
2.699650
2.745150
%
62
PG Hysteresis
VIN = 6.0V
3.182050
3.183350
3.271700
%
63
PG Low Voltage
ISINK = 1mA
31.560800
31.295600
31.212750
mV
64
PG Low Voltage
ISINK = 6mA
177.500500
177.572900
175.997050
mV
65
PG Leakage Current
VIN = 6.0V, PG = 6.0V
0.017550
-0.000750
-0.002400
µA
213.033000 221.517950
NOTE:
14. See the Radiation report.
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9
FN8294.5
December 15, 2014
ISL75051SEH
Post Radiation Characteristics for High Dose and Low Dose TA = +25°C, unless otherwise noted. This data is typical
test data post radiation exposure at a rate of 10mrad(Si)/s for low dose rate and 50-300rad(Si)/s for high dose rate. This data is intended to show typical
parameter shifts due to HDR (High Dose Rate) or LDR (Low Dose Rate) radiation. These are not limits nor are they guaranteed.
1.525
1.525
SPEC LIMIT
1.515
1.510
HDR BIAS
LDR BIAS
1.505
1.500
1.495
HDR GROUND
LDR GROUND
1.490
1.485
1.480
1.475
1.515
1.510
50
100
150
TOTAL DOSE, krad(Si)
1.500
1.495
1.485
1.480
1.475
HDR BIAS
HDR GROUND
LDR GROUND
12
10
8
SPEC LIMIT
0
50
100
150
TOTAL DOSE, krad(Si)
100
LDR BIAS
250
200
100
SPEC LIMIT
50
0
50
LDR BIAS
CONTROL
LDR GROUND
5
POST
ANNEAL
100
150
TOTAL DOSE, krad(Si)
SPEC LIMIT
1.6
SC CURRENT (A)
HDR BIAS
HDR BIAS
LDR GROUND
150
1.8
SPEC LIMIT
7
HDR GROUND
CONTROL
FIGURE 6. DROPOUT VOLTAGE, 2.5VOUT, 3A LOAD CURRENT
8
6
POST
ANNEAL
150
SPEC LIMIT
300
0
POST
ANNEAL
FIGURE 5. GROUND PIN CURRENT, 5.0VOUT, 5.5VIN, NO LOAD
SC CURRENT (A)
50
FIGURE 4. DC OUTPUT VOLTAGE, 1.5VOUT, 3.6VIN, 3A LOAD
DROPOUT VOLTAGE, 3A (mV)
GROUND PIN CURRENT (mA)
SPEC LIMIT
CONTROL
LDR BIAS
14
LDR BIAS
CONTROL
HDR BIAS
1.4
1.2
LDR GROUND
1.0
HDR GROUND
0.8
HDR GROUND
0.6
SPEC LIMIT
4
0
350
16
6
SPEC LIMIT
TOTAL DOSE, krad(Si)
20
18
HDR GROUND
LDR GROUND
1.490
POST
ANNEAL
FIGURE 3. DC OUTPUT VOLTAGE, 1.5VOUT, 3.6VIN NO LOAD
HDR BIAS
LDR BIAS
1.505
SPEC LIMIT
0
SPEC LIMIT
1.520
DC OUTPUT VOLTAGE (V)
DC OUTPUT VOLTAGE (V)
1.520
0
50
100
150
TOTAL DOSE, krad(Si)
POST
ANNEAL
FIGURE 7. OUTPUT SHORT CIRCUIT CURRENT, RSET = 511Ω, 2.2VIN
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10
0.4
0
50
SPEC LIMIT
100
TOTAL DOSE, krad(Si)
150
POST
ANNEAL
FIGURE 8. OUTPUT SHORT CIRCUIT CURRENT, RSET = 5.11kΩ, 5.5VIN
FN8294.5
December 15, 2014
ISL75051SEH
Typical Operating Performance
1.528
+25°C, VADJ
0.521
1.524
-58°C, VOUT
0.520
VADJ (V)
1.522
VOUT (V)
0.522
+25°C, VOUT
1.526
1.520
1.518
+128°C, VOUT
1.516
-58°C, VADJ
0.519
0.518
+128°C, VADJ
0.517
1.514
1.512 VIN = 2.5V
= 1.5V
V
1.510 OUT
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.516 V = 2.5V
IN
V
= 1.5V
0.515 OUT
0.0
0.5
1.0
3.5
1.5
IOUT (A)
FIGURE 9. LOAD REGULATION, VOUT vs IOUT
0.5210
-58°C, VOUT
2.515
3.5
+25°C, VADJ
0.5205
-58°C, VADJ
0.5200
+25°C, VOUT
2.510
VADJ (V)
VOUT (V)
3.0
0.5215
2.520
2.505
2.500
+128°C, VOUT
2.490 VIN = 3.3V
V
= 2.5V
2.485 OUT
0.0
0.5
1.0
0.5195
0.5190
0.5185
0.5180
0.5170
0.5165
1.5
2.0
2.5
+128°C, VADJ
0.5175
2.495
3.0
VIN = 3.3V
VOUT = 2.5V
0.5160
0.0
3.5
0.5
1.0
IOUT (A)
0.5215
0.5210
0.5200
VADJ (V)
4.080
+25°C, VOUT
4.075
4.070
1.5
2.0
2.5
3.0
IOUT (A)
FIGURE 13. LOAD REGULATION, VOUT vs IOUT
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11
3.5
+25°C, VADJ
-58°C, VADJ
0.5195
0.5190
0.5185
+128°C, VADJ
0.5180
0.5170
VIN = 5V
VOUT = 4V
1.0
3.0
0.5175
-58°C, VOUT
0.5
2.5
0.5205
+128°C, VOUT
4.060
0.0
2.0
FIGURE 12. LOAD REGULATION, VADJ vs IOUT
4.090
4.085
1.5
IOUT (A)
FIGURE 11. LOAD REGULATION, VOUT vs IOUT
VOUT (V)
2.5
FIGURE 10. LOAD REGULATION, VADJ vs IOUT
2.525
4.065
2.0
IOUT (A)
3.5
0.5165 VIN = 5V
V
= 4V
0.5160 OUT
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
IOUT (A)
FIGURE 14. LOAD REGULATION, VADJ vs IOUT
FN8294.5
December 15, 2014
ISL75051SEH
Typical Operating Performance
(Continued)
8
0.525
ROCP = 0.511k
7
6
+25°C, VADJ
0.521
0.519
OCP (A)
VADJ (V)
0.523
-58°C, VADJ
+128°C, VADJ
ROCP = 0.681k
5
ROCP = 0.75k
4
ROCP = 1.47k
3
ROCP = 1.00k
ROCP = 2.00k
2
0.517
1
0.515
2.0
ROCP = 2.61k
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
2.0
2.5
3.0
3.5
ROCP = 3.83
4.0
VIN (V)
8
ROCP = 0.511k
6
3
ROCP = 0.75k
ROCP = 1.00k
ROCP = 1.47k
ROCP = 2.00k
OCP (A)
OCP (A)
4
6.0
6.5
7.0
ROCP = 0.511k
7
ROCP = 0.681k
5
5.5
FIGURE 16. ROCP vs OCP AT +25°C, VOUT = 1.5V
8
6
ROCP = 5.11k
5.0
VIN (V)
FIGURE 15. VIN vs VADJ OVER-TEMPERATURE
7
4.5
2
ROCP = 0.681k
5
ROCP = 1.00k
ROCP = 0.75k
4
ROCP = 2.00k
ROCP = 1.47k
3
2
1
1
0
2.0
ROCP = 3.83
ROCP = 2.61k
2.5
3.0
3.5
4.0
4.5 5.0
VIN (V)
5.5
ROCP = 5.11k
6.0
6.5
7.0
0
2.0
ROCP = 3.83
ROCP = 2.61k
2.5
3.0
3.5
4.0
4.5 5.0
VIN (V)
5.5
ROCP = 5.11k
6.0
6.5
7.0
FIGURE 17. ROCP vs OCP AT +128°C, VOUT = 1.5V
FIGURE 18. ROCP vs OCP AT -58°C, VOUT = 1.5V
FIGURE 19. TRANSIENT LOAD RESPONSE, VIN = 3.3V, VOUT = 2.5V,
COUT = 47µF, 35mΩ
FIGURE 20. TRANSIENT LOAD RESPONSE, VIN = 3.3V, VOUT = 2.5V,
COUT = 220µF, 25mΩ
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12
FN8294.5
December 15, 2014
ISL75051SEH
Typical Operating Performance
(Continued)
FIGURE 21. POWER-ON AND POWER-OFF, EN = 0 TO 1, +25°C,
VIN = 6V, VOUT = 0.8V, IOUT = 0.5A, PGOOD TURN-ON
FIGURE 22. POWER-ON AND POWER-OFF, EN = 0 TO 1, +25°C,
VIN = 2.2V, VOUT = 0.8V, IOUT = 0.5A, PGOOD TURN-ON
FIGURE 23. POWER-ON AND POWER-OFF, EN = 1 TO 0, +25°C,
VIN = 6V, VOUT = 0.8V, IOUT = 0.5A, PGOOD TURN-OFF
FIGURE 24. POWER-ON AND POWER-OFF, EN = 1 TO 0, +25°C,
VIN = 2.2V, VOUT = 0.8V, IOUT = 0.5A, PGOOD TURN-OFF
80
1000
64.96dB
PSRR dB AT -58°C
60
100
GAIN (dB)
NOISE (µV/√Hz)
70
10
1
0.1
300
3k
30k
FREQUENCY (Hz)
FIGURE 25. NOISE (µV/√Hz)
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13
300k
50
40
30
PSRR dB AT +25°C
PSRR dB AT +128°C
20 VIN = 2.5V, VOUT = 1.8V,
IOUT = 3A, SIGNAL = 300mVP-P,
10 CIN = 220µF TANT,
COUT = 220µF TANT, CBYP = 0.2µF
0
10
100
1k
10k
FREQUENCY (Hz)
27.61dB
100k
FIGURE 26. PSRR
FN8294.5
December 15, 2014
ISL75051SEH
Applications Information
TABLE 2. TYPICAL GM/PM WITH VARIOUS CAPACITORS
Input Voltage Requirements
This RH LDO will work from a VIN in the range of 2.2V to 6.0V. The
input supply can have a tolerance of as much as ±10% for
conditions noted in the “Electrical Specifications”. The minimum
guaranteed input voltage is 2.2V. However, due to the nature of
an LDO, VIN must be some margin higher than the output
voltage, plus dropout at the maximum rated current of the
application, if active filtering (PSRR) is expected from VIN to
VOUT. The dropout spec of this family of LDOs has been
generously specified to allow applications to design for efficient
operation.
CAPACITANCE
(µF)
ESR
(mΩ)
GAIN MARGIN
(dB)
PHASE MARGIN
(°)
47
35
14
55
100
25
16
57
220
6
19
51
220
25
16
69
100
100
10
62
Type numbers of KEMET capacitors used in the device are shown
in Table 3.
Adjustable Output Voltage
TABLE 3. KEMET CAPACITORS USED IN DEVICE
The output voltage of the RH LDO can be set to any user
programmable level between 0.8V to 5.0V. This is achieved with
a resistor divider connected between the OUT, ADJ and GND pins.
With the internal reference at 0.52V, the divider ratio should be
fixed such that when the desired VOUT level is reached, the
voltage presented to the ADJ pin is 0.52V. Resistor values for
typical voltages are shown in Table 1.
TABLE 1. RESISTOR VALUES FOR TYPICAL VOLTAGES
RTOP
(k)
0.8
7.87k
4.32
1.5
2.26k
4.32
1.8
1.74k
4.32
2.5
1.13k
4.32
4.0
634
4.32
5.0
499
4.32
R TOP
--------------------------BOTTOM =
 V OUT
(EQ. 1)
 ------------- – 1
 V ADJ
Input and Output Capacitor Selection
The RH operation requires the use of a combination of tantalum
and ceramic capacitors to achieve a good volume-to-capacitance
ratio. The recommended combination is a 220µF, 10V, 25mΩ
rated DSSC 04051-032 series tantalum capacitor, in parallel
with a 0.1µF MIL-PRF-49470 CDR04 ceramic capacitor to be
connected between VIN to GND pins and VOUT to GND pins of the
LDO, with PCB traces no longer than 0.5cm.
The stability of the device depends on the capacitance and ESR
of the output capacitor. The usable ESR range for the device is
6mΩ to 100mΩ. At the lower limit of ESR = 6mΩ, the phase
margin is about 51°C. On the high-side, an ESR of 100mΩ is
found to limit the gain margin at around 10dB. The typical
GM/PM seen with capacitors are shown in Table 2.
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14
T525D476M016ATE035
47µF, 10V, 35mΩ
T525D107M010ATE025
100µF, 10V, 25mΩ
T530D227M010ATE006
220µF, 10V, 6mΩ
T525D227M010ATE025
220µF, 10V, 25mΩ
T495X107K016ATE100
100µF, 16V, 100mΩ
A typical gain phase plot measured on the ISL75051SRHEVAL1Z
evaluation board for VIN = 3.3V, VOUT = 1.8V and IOUT = 3A with a
220µF, 10V, 25mΩ capacitor is shown in Figure 27 and is
measured at GM = 16.3dB and PM = 69.16°.
GAIN (dB)
RBOTTOM
CAPACITOR DETAILS
60
50
40
30
20
10
0
-10 3.3V
-20 1.8V
-30 3.0A
-40 1x220µF
-50
T525D
-60
500
180
150
120
90
60
30
0
-30
-60
-90
-120
-150
-180
PHASE
GAIN
5k
50k
500k
PHASE (°)
VOUT
(V)
KEMET TYPE NUMBER
5M
FREQUENCY (Hz)
FIGURE 27. TYPICAL GAIN PHASE PLOT
Enable
The device can be enabled by applying a logic high on the EN pin.
The enable threshold is typically 0.9V. A soft-start cycle is
initiated when the device is enabled using this pin. Taking this pin
to logic low disables the device.
The EN can be driven from either an open drain or a totem pole
logic drive between EN pin and GND. Assuming an open-drain
configuration, M1 will actively pull-down the EN line, as shown in
Figure 28, and thereby discharge the input capacitance, shutting
off the device immediately.
FN8294.5
December 15, 2014
ISL75051SEH
VIN
ADJ PIN
R1
10k
VIN
INT EN GATE
EN PIN
VIN
I1
90µA DC
I2
0.5µA DC
INT EN BUS
INT SS NODE -IN
OUT
C1
0.1µF
0
0
FIGURE 29. SOFT-START
The Power-Good pin is asserted high when the voltage on the ADJ
pin crosses the rising threshold of 0.9 x VADJ (typ). On the falling
threshold, Power-Good is asserted low when the voltage on the
ADJ pin crosses the falling threshold of 0.88 x VADJ. The
power-good output is an open-drain output rated for a continuous
sink current of 1mA.
Soft-start
Soft-start is achieved by means of the charging time constant of
the BYP pin. The capacitor value on the pin determines the time
constant and can be calculated using Equations 2 through 4
based on VIN range:
If VIN range is 2.2V ≤ VIN < 2.7V:
t SS =  – 4.8376  V IN  +  0.0254  T A  +  0.0522  C BYP  + 11.8526
(EQ. 2)
If VIN range is 2.7V ≤ VIN < 4.0V:
t SS =  – 1.4711  V IN  +  0.0179  T A  +  0.0377  C BYP  + 4.7430
(EQ. 3)
Current Limit Protection
The RH LDO incorporates protection against overcurrent due to
any short or overload condition applied to the output pin. The
current limit circuit becomes a constant current source when the
output current exceeds the current limit threshold, which can be
adjusted by means of a resistor connected between the OCP pin
and GND. If the short or overload condition is removed from VOUT,
then the output returns to normal voltage mode regulation. The
OCP can be calculated with Equation 5:
OCP = 4.1115  ROCP
– 0.75
(EQ. 5)
where OCP = Overcurrent Threshold in amps, and ROCP = OCP
resistor in kΩ.
In the event of an overload condition based on the set OCP limit,
the die temperature may exceed the internal over-temperature
limit, and the LDO begins to cycle on and off due to the fault
condition (Figure 30). However, thermal cycling may never occur
if the heatsink used for the package can keep the die
temperature below the limits specified for thermal shutdown.
8
If VIN range is 4.0V ≤ VIN < 6.0V:
7
t SS =  – 0.4458  V IN  +  0.0130  T A  +  0.0295  C BYP  + 1.8527
6
where tSS = soft-start time (ms), VIN = Input supply (V),
TA = Ambient Temperature and CBYP = BYPASS capacitor (nF).
The BYPASS capacitor, C1, charges with a current source and
provides an EA reference, -IN, with an SS ramp. VOUT, in turn,
follows this ramp. The ramp rate can be calculated based on the
C1 value. For conditions in which C1 is opened, or for small
values of C1, the ramp is provided by C2 = 50pF, with a source of
0.5µA. Connecting C1 min = 0.1µF to the BYPASS pin is
recommended for normal operation.
OCP (A)
(EQ. 4)
15
VOUT
ISL75051SEH EA
C2
50pF
0
Power-Good
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75051_PMOS
M1
-IN
M1
FIGURE 28. ENABLE
VIN
+IN
BYPASS
EXT PIN
EN
U1
5
4
OCP = +25°C
3
2
1
0
0
1
2
3
4
5
6
ROCP (kΩ)
FIGURE 30. OCP vs ROCP
FN8294.5
December 15, 2014
ISL75051SEH
Thermal Guidelines
If the die temperature exceeds typically +175°C, then the LDO
output shuts down to zero until the die temperature cools to
typically +155°C. The level of power combined with the thermal
impedance of the package (JC of 4°C/W for the 18 Ld CDFP
package) determines whether the junction temperature exceeds
the thermal shutdown temperature specified in the “Electrical
Specifications” table on page 5.
The device should be mounted on a high effective thermal
conductivity PCB with thermal vias, per JESD51-7 and JESD51-5.
Place a silpad between package base and PCB copper plane. The
VIN and VOUT ratios should be selected to ensure that dissipation
for the selected VIN range keeps TJ within the recommended
operating level of +150°C for normal operation.
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16
FN8294.5
December 15, 2014
ISL75051SEH
Weight Characteristics
Weight of Packaged Device
K18.D: 1.07 Grams typical with leads clipped
K18.E: 1.07 Grams typical with leads clipped
Die Characteristics
Die Dimensions
4555µm x 4555µm (179.3 mils x 179.3 mils)
Thickness: 304.8µm ± 25.4µm (12.0 mils ± 1 mil)
SUBSTRATE
Type: Silicon
BACKSIDE FINISH
Silicon
PROCESS
0.6µM BiCMOS Junction Isolated
ASSEMBLY RELATED INFORMATION
Substrate Potential
Unbiased
Interface Materials
ADDITIONAL INFORMATION
GLASSIVATION
Type: Silicon Oxide and Silicon Nitride
Thickness: 0.3µm ± 0.03µm to 1.2µm ± 0.12µm
Worst Case Current Density
< 2 x 105 A/cm2
Transistor Count
TOP METALLIZATION
2932
Type: AlCu (99.5%/0.5%)
Thickness: 2.7µm ±0.4µm
Layout Characteristics
BACKSIDE METALLIZATION
None
Step and Repeat
4555µm x 4555µm
Metallization Mask Layout
P A D X Y C O O R D IN A TES
X
( µ m)
Y
( µ m)
GND
0
0
GND
-393
0
PAD
N AM E
1
2
3
VOUT
-711
-710
4
VOUT
-711
-1858
5
VOUT
-711
-2964
6
ADJ
-1680
-3070
7
BYP
-1621
-3879
8
EN
2164
-3879
9
OCP
2222
-3131
10
VIN
1078
-2965
11
VIN
1078
-1853
12
VIN
1078
-711
13
PG
420
-25
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17
FN8294.5
December 15, 2014
ISL75051SEH
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
CHANGE
December 15, 2014
FN8294.5
Made correction to Charged Device Model testing information from Tested per CDM-22CI0ID to JESD22-C101D
October 27, 2014
Added Related Literature section on page 1.
Added ESD ratings under the Abs Max section on page 4.
Human Body Model (Tested per MIL-PRF-883 3015.7). . . . . . . . . .2.5kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 250V
Charged Device Model (Tested per CDM-22CI0ID).............................1kV
September 15, 2014
FN8294.4
Replaced Equation 2 and added Equations 3 and 4 on page 15.
Removed second line of Yaxis title for Figures 3, 4, 5,7 and 8 as it was redudant information that was already
in the Figure titles.
March 28, 2014
FN8294.3
Thermal Information, page 4:
Updated JC (°C/W) for the 18 Ld CDFP Package with Bottom Metal and Solder Mount from “4” to “3.3”.
Removed both “Enable Pin Turn-on Delay” rows from“Electrical Specifications” on page 5.
Added EQ1 to page 14.
February 11, 2014
FN8294.2
Soft-Start section, page 15:
1) EQ1 Changed From: Trise (ms)=0.00577xCss (nF) To: Trise (ms)=0.0326xCss (nF)
2) Changed From: "a 90µA source current " To: " a current source"
September 12, 2013
FN8294.1
Updated Equation 2 on page 15.
September 6, 2013
Weight Characteristics on page 17: Added K18.E: 1.07 Grams typical with leads clipped.
Updated Equation 2 on page 15.
August 30, 2013
Added a note to the pin configuration figure on page 3.
Ordering information table on page 3: Added part number ISL75051SRHX/SAMPLE.
Updated Equation 2 on page 15.
August 27, 2013
Added part numbers ISL75051SEHVFE and ISL75051SEHFE/PROTO (18 Ld CDFP with bottom metal) to
ordering information table on page 3.
Added 18 Ld CDFP Package theta ja= 28 and theta jc = 4 to thermal information table on page 4.
Updated POD for k18.D from Rev3 to Rev5: Added bottom of lead to bottom of package.
Added POD k18.E: 18 Ld ceramic metal seal flatpack package with bottom metal.
August 28, 2012
FN8294.0
Initial Release.
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18
FN8294.5
December 15, 2014
ISL75051SEH
Package Outline Drawing
K18.D
18 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
Rev 5, 3/13
PIN NO. 1
ID OPTIONAL 1
0.015(0.381)
0.005(0.127)
2
A
0.040(1.016 BSC)
A
0.476(12.09)
0.456(11.58)
PIN NO. 1
ID AREA
0.020(0.508)
0.013(0.330)
0.122(3.10)
0.100(2.54)
0.005(0.127)
MIN.
4
TOP VIEW
0.036(0.92)
0.026(0.66)
6
0.397(10.084)
0.377(9.576)
-D0.010(0.254)
0.004(0.102)
-C0.303(7.70)
0.283(7.19)
SEATING AND
BASE PLANE
SIDE VIEW
0.295(7.49)
0.250(6.35)
-H-
0.03(0.76) MIN.
BOTTOM VIEW
NOTES:
0.007(0.178)
0.004(0.102)
1. Index area: A notch or a pin one identification mark shall be located
adjacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one
identification mark. Alternately, a tab may be used to identify pin one.
LEAD FINISH
2. If a pin one identification mark is used in addition to a tab, the limits
of the tab dimension do not apply.
~
BASE
METAL
0.010(0.254)
0.004(0.102)
0.017(0.432)
0.013(0.330)
0.020(0.508)
0.013(0.330)
SECTION A-A
3. The maximum limits of lead dimensions (section A-A) shall be
measured at the centroid of the finished lead surfaces, when solder
dip or tin plate lead finish is applied.
4. Measure dimension at all four corners.
0.0015(0.04)
MAX
3
5. For bottom-brazed lead packages, no organic or polymeric materials
shall be molded to the bottom of the package to cover the leads.
6. Dimension shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension minimum shall
be reduced by 0.0015 inch (0.038mm) maximum when solder dip
lead finish is applied.
7. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
8. Dimensions = INCH (mm). Controlling dimension: INCH.
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19
FN8294.5
December 15, 2014
ISL75051SEH
Package Outline Drawing
K18.E
18 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE WITH BOTTOM METAL
Rev 1, 3/13
PIN NO. 1
ID OPTIONAL 1
0.015(0.381)
0.005(0.127)
2
A
0.040(1.016 BSC)
A
0.476(12.09)
0.456(11.58)
PIN NO. 1
ID AREA
0.020(0.508)
0.013(0.330)
0.122(3.10)
0.100(2.54)
0.005(0.127)
MIN.
4
TOP VIEW
0.036(0.92)
0.026(0.66)
6
0.397(10.084)
0.377(9.576)
-D0.010(0.254)
0.004(0.102)
-CSEATING AND
BASE PLANE
BOTTOM METAL
7
0.303(7.70)
0.283(7.19)
SIDE VIEW
0.295(7.49)
0.250(6.35)
-H-
0.03(0.76) MIN.
BOTTOM METAL
0.005(0.127) REF
OFFSET FROM
CERAMIC EDGE
BOTTOM VIEW
NOTES:
0.007(0.178)
0.004(0.102)
1. Index area: A notch or a pin one identification mark shall be located
adjacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one
identification mark. Alternately, a tab may be used to identify pin one.
LEAD FINISH
2. If a pin one identification mark is used in addition to a tab, the limits
of the tab dimension do not apply.
~
BASE
METAL
0.010(0.254)
0.004(0.102)
4. Measure dimension at all four corners.
0.017(0.432)
0.013(0.330)
0.020(0.508)
0.013(0.330)
SECTION A-A
3. The maximum limits of lead dimensions (section A-A) shall be
measured at the centroid of the finished lead surfaces, when solder
dip or tin plate lead finish is applied.
0.0015(0.04)
MAX
3
5. For bottom-brazed lead packages, no organic or polymeric materials
shall be molded to the bottom of the package to cover the leads.
6. Dimension shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension minimum shall
be reduced by 0.0015 inch (0.038mm) maximum when solder dip
lead finish is applied.
7. The bottom of the package is a solderable metal surface.
8. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
9. Dimensions = INCH (mm). Controlling dimension: INCH.
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20
FN8294.5
December 15, 2014