19MHz Rad Hard 40V Quad Rail-to-Rail Input-Output, Low-Power Operational Amplifiers ISL70444SEH Features The ISL70444SEH features four low-power amplifiers optimized to provide maximum dynamic range. These op amps feature a unique combination of rail to rail operation on the input and output as well as a slew enhanced front end that provides ultra fast slew rates positively proportional to a given step size; thereby increasing accuracy under transient conditions, whether it’s periodic or momentary. They also offer low power, low offset voltage, and low temperature drift, making it ideal for applications requiring both high DC accuracy and AC performance. With <5µs recovery for Single Event Transients (SET) (LETTH = 86.4MeV•cm2/mg), the number of filtering components needed is drastically reduced. The ISL70444SEH is also immune to Single Event Latch-up as it is fabricated in Intersil’s Proprietary PR40 Silicon On Insulator (SOI) process. • Electrically screened to DLA SMD# 5962-13214 They are designed to operate over a single supply range of 2.7V to 40V or a split supply voltage range of ±1.35V to ±20V. Applications for these amplifiers include precision instrumentation, data acquisition, precision power supply controls, and process controls. The ISL70444SEH is available in a 14 Ld Hermetic Ceramic Flatpack and die forms that operate over the temperature range of -55°C to +125°C. • Acceptance tested to 50krad(Si) (LDR) wafer-by-wafer • <5µs recovery from SEE (LETTH = 86.4MeV•cm2/mg) • Unity gain stable • Rail-to-rail input and output • Wide gain·bandwidth product . . . . . . . . . . . . . . . . . . . . 19MHz • • • • • Wide single and dual supply range. . . . . . . . 2.7V to 40V Max Low input offset voltage . . . . . . . . . . . . . . . . . . . . . . . . . 300µV Low current consumption (per amplifier) . . . . . . . 1.1mA, Typ No phase reversal with input overdrive Slew rate - Large signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60V/µs • Operating temperature range. . . . . . . . . . . .-55°C to +125°C • Radiation tolerance - High dose rate (50-300rad(Si)/s). . . . . . . . . . . 300krad(Si) - Low dose rate (0.01rad(Si)/s) . . . . . . . . . . . . 100krad(Si)* - SEL/SEB LETTH . . . . . . . . . . . . . . . . . . . . 86.4MeV•cm2/mg * Product capability established by initial characterization. Applications Related Literature • Precision instruments • ISL70444SEH Evaluation Board User’s Guide AN1824 • Active filter blocks • ISL70444SEH Single Event Effects Report AN1838 • Data acquisition • ISL70444SEH SMD 5962-13214 • Power supply control • ISL70444SEH Radiation Test Report • Process control RF 30 100kΩ + -IN 10kΩ RSENSE RIN+ +IN 10kΩ V+ ISL70444 V- + Vs = ±18V 20 VOUT 10 VOUT = 10 (ILOAD * RSENSE) RREF+ LOAD VOS (µV) RIN- +2.7V to 40V 0 GROUNDED -10 BIASED 100kΩ -20 VREF -30 0 50 100 150 200 250 300 krad (Si) FIGURE 1. TYPICAL APPLICATION: SINGLE-SUPPLY, HIGH-SIDE CURRENT SENSE AMPLIFIER June 14, 2013 FN8411.1 1 FIGURE 2. VOS SHIFT vs HIGH DOSE RATE RADIATION CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2013. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL70444SEH Pin Configuration ISL70444SEH (14 LD FLATPACK) TOP VIEW 14 OUTD 13 -IND 3 12 +IND V+ 4 11 V- +INB 5 10 +INC 9 -INC 8 OUTC OUTA 1 -INA 2 +INA -INB 6 OUTB 7 A - + - + B D + - + C Pin Descriptions PIN NUMBER PIN NAME EQUIVALENT ESD CIRCUIT 1 OUTA Circuit 2 Amplifier A output 2 -INA Circuit 1 Amplifier A inverting input 3 +INA Circuit 1 Amplifier A non-inverting input 4 V+ Circuit 3 Positive power supply 5 +INB Circuit 1 Amplifier B non-inverting input 6 -INB Circuit 1 Amplifier B inverting input 7 OUTB Circuit 2 Amplifier B output 8 OUTC Circuit 2 Amplifier C output 9 -INC Circuit 1 Amplifier C inverting input 10 +INC Circuit 1 Amplifier C non-inverting input 11 V- Circuit 3 Negative power supply 12 +IND Circuit 1 Amplifier D non-inverting input 13 -IND Circuit 1 Amplifier D inverting input 14 OUTD Circuit 2 Amplifier D output - E-Pad None V+ 600Ω E-Pad under Package (Unbiased, tied to package lid) V+ 600Ω IN- V- CIRCUIT 1 2 V+ CAPACITIVELY TRIGGERED ESD CLAMP OUT IN+ V- DESCRIPTION CIRCUIT 2 VCIRCUIT 3 FN8411.1 June 14, 2013 ISL70444SEH Ordering Information PART NUMBER ORDERING/SMD NUMBER TEMP RANGE (°C) PACKAGE (RoHS Compliant) PKG. DWG. # 5962F1321401VXC ISL70444SEHVF -55 to +125 14 Ld Flatpack K14.C ISL70444SEHF/PROTO ISL70444SEHF/PROTO -55 to +125 14 Ld Flatpack K14.C 5962F1321401V9A ISL70444SEHVX -55 to +125 DIE ISL70444SEHX/SAMPLE ISL70444SEHX/SAMPLE -55 to +125 DIE ISL70444SEHEVAL1Z ISL70444SEHEVAL1Z Evaluation Board NOTES: 1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. 2. For Moisture Sensitivity Level (MSL), please see device information page for ISL70444SEH. For more information on MSL please see Tech Brief TB363. 3. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in the “Ordering Information” table must be used when ordering. 3 FN8411.1 June 14, 2013 ISL70444SEH Absolute Maximum Ratings Thermal Information Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42V Maximum Supply Voltage (Note 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42V Maximum Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Maximum Differential Input Voltage . . . . . . . . 42V or V- - 0.5V to V+ + 0.5V Min/Max Input Voltage . . . . . . . . . . . . . . . . . . . . 42V or V- - 0.5V to V+ + 0.5V Max/Min Input Current for Input Voltage >V+ or <V- . . . . . . . . . . . . . . . . . ±20mA ESD Tolerance Human Body Model (Tested per MIL-PRF-883 3015.7). . . . . . . . . . . 2kV Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . . 200V Charged Device Model (Tested per CDM-22CI0ID) . . . . . . . . . . . . . . 750V Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 14 Ld Flatpack Package (Notes 4, 5). . . . . 35 9 Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Recommended Operating Conditions Ambient Operating Temperature Range . . . . . . . . . . . . . .-55°C to +125°C Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . .+150°C Single Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . 3V ±10% to 36V ±10% Split Rail Supply Voltage . . . . . . . . . . . . . . . . . . ±1.5V ±10% to ±18V ±10% CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. Theta-ja is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379 for details. 5. For θJC, the “case temp” location is the center of the package underside. 6. Tested in a heavy ion environment at LET = 86.4MeV•cm2/mg at +125°C (TC) for SEB. Refer to Single Event Effects Test Report for more information. Electrical Specifications VS = ±18V, VCM = VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply over the operating temperature range, -55°C to +125°C. PARAMETER VOS DESCRIPTION CONDITIONS Offset Voltage VCM = 0V VCM = V+ V+ to VV- + MIN (Note 7) TYP MAX (Note 7) UNIT - 20 300 µV - 80 400 µV - 0.5 - µV/°C TCVOS Offset Voltage Temperature Coefficient VCM = ΔVOS Input Offset Channel-to-Channel Match VCM = V+ - 77 800 µV V- - 117 800 µV VCM = 0V - 189 370 nA VCM = V+ - 200 370 nA VCM = V- - 262 650 nA VCM = V+ - 200 370 nA VCM = V- + IB IOS Input Bias Current Common Mode Input Voltage Range CMRR Common-Mode Rejection Ratio AVOL VOH VOL Power Supply Rejection Ratio Open-Loop Gain - 0.5V 0.5V VCM = V- to V+ VCM = V- VCM = V+ VCM = V+ to V+ Output Voltage High (VOUT to Output Voltage Low (VOUT to V -) - 257 650 nA -17 0 17 nA V- - V+ V - 112 - dB 70 - - dB 111 - dB - 0.5V to V- + 0.5V - - 0.5V to V- + 0.5V 80 - - dB - 128 - dB 88 - - dB - 125 - dB 96 - - dB RL = No Load - 78 160 mV RL = 10kΩ - 118 175 mV RL = No Load - 73 160 mV RL = 10kΩ - 110 175 mV V- = -18V; V+ = 0.5V to 18V; V+ = 18V; V- = -0.5V to -18V RL = 10kΩ to ground V+ ) 4 2V VCM = V+ to V- Input Offset Current VCMIR PSRR VCM = - 2V to FN8411.1 June 14, 2013 ISL70444SEH Electrical Specifications VS = ±18V, VCM = VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply over the operating temperature range, -55°C to +125°C. (Continued) PARAMETER DESCRIPTION CONDITIONS MIN (Note 7) TYP MAX (Note 7) UNIT ISRC Output Short Circuit Current Sourcing; VIN = 0V, VOUT = -18V 10 - - mA ISNK Output Short Circuit Current Sinking; VIN = 0V, VOUT = +18V 10 - - mA Supply Current/Amplifier Unity gain - 1.5 1.75 mA - 1.95 2.4 mA 19 - MHz IS AC SPECIFICATIONS GBW Gain Bandwidth Product ACL = 101, RL = 10k - en Voltage Noise Density f = 10kHz - 11.3 - nV/√Hz in Current Noise Density f = 10kHz - 0.312 - pA/√Hz SR Large Signal Slew Rate AV = 1, RL = 10kΩ, VO = 10VP-P 60 - - V/µs Electrical Specifications VS = ±2.5V, VCM = VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply over the operating temperature range, -55°C to +125°C. PARAMETER VOS DESCRIPTION CONDITIONS Offset Voltage VCM = 0V VCM = V+ to V- MIN (Note 7) TYP MAX (Note 7) UNIT - 20 300 µV - 80 400 µV TCVOS Offset Voltage Temperature Coefficient VCM = V+ - 2V to V- + 2V - 0.5 - µV/°C ΔVOS Input Offset Channel-to-Channel Match VCM = V+ - 79 800 µV VCM = V- - 119 800 µV Input Bias Current VCM = 0V - 202 340 nA VCM = V+ - 182 340 nA VCM = V- - 229 580 nA - 181 340 nA - 224 580 nA -17 IB IOS VCMIR CMRR PSRR AVOL VOH Input Offset Current VCM = V+ VCM = V- + VCM = V+ to V- - 0.5V 0.5V 0 17 nA V- - V+ V to V+ - 92 - dB to V+ Common Mode Input Voltage Range Common-Mode Rejection Ratio Power Supply Rejection Ratio Open-Loop Gain Output Voltage High (VOUT to 5 VCM = V- VCM = V- 70 - - dB VCM = V+ - 0.5V to V- + 0.5V - 91 - dB VCM = V+ - 0.5V to V- + 0.5V 74 - - dB - 123 - dB 80 - - dB - 118 - dB 90 - - dB RL = No Load - 53 85 mV RL = 10kΩ - 53 105 mV RL = 600Ω - - 400 mV V- = V+ = -2.5V; 0.5V to 2.5V; V+ = 2.5V; V- = -0.5V to -2.5V RL = 10kΩ to ground V+ ) FN8411.1 June 14, 2013 ISL70444SEH Electrical Specifications VS = ±2.5V, VCM = VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply over the operating temperature range, -55°C to +125°C. (Continued) PARAMETER VOL IS MIN (Note 7) TYP MAX (Note 7) UNIT RL = No Load - 53 85 mV RL = 10kΩ - 53 105 mV RL = 600Ω - - 400 mV Unity gain - 1.1 1.25 mA - 1.6 1.8 mA DESCRIPTION CONDITIONS Output Voltage Low (VOUT to V-) Supply Current/Amplifier AC SPECIFICATIONS GBW Gain Bandwidth Product ACL = 101, RL = 10k - 17 - MHz en Voltage Noise Density f = 10kHz - 12.3 - nV/√Hz in Current Noise Density f = 10kHz - 0.313 - pA/√Hz SR Large Signal Slew Rate AV = 1, RL = 10kΩ, VO = 3VP-P - 35 - V/µs Electrical Specifications VS = ±1.5V, VCM = VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply over the operating temperature range, -55°C to +125°C. PARAMETER VOS DESCRIPTION CONDITIONS Offset Voltage VCM = 0V VCM = V+ to ΔVOS IB IOS VCMIR VOH VOL IS V- MIN (Note 7) TYP MAX (Note 7) UNIT - 51 300 µV - 80 400 µV - 79 800 µV Input Offset Channel-to-Channel Match VCM = V+ VCM = V- 119 800 µV Input Bias Current VCM = 0V - 220 330 nA VCM = V+ - 180 330 nA VCM = V- - 225 565 nA VCM = V+ - 0.5V - 180 330 nA VCM = V- + 0.5V - 223 565 nA -17 VCM = V+ to V- Input Offset Current 0 17 nA V- - V+ V RL = No Load - 26 39 mV RL = 10kΩ - 30 60 mV RL = No Load - 26 39 mV RL = 10kΩ - 42 60 mV Unity Gain - 1.1 1.24 mA - 1.57 1.8 mA Common Mode Input Voltage Range Output Voltage High (VOUT to V+ ) Output Voltage Low (VOUT to V-) Supply Current/Amplifier AC SPECIFICATIONS GBW Gain Bandwidth Product ACL = 101, RL = 10k - 16 - MHz en Voltage Noise Density f = 10kHz - 12 - nV/√Hz in Current Noise Density f = 10kHz - 0.312 - pA/√Hz 6 FN8411.1 June 14, 2013 ISL70444SEH Electrical Specifications VS = ±18V, VCM = VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply over a total ionizing dose of 300krad(Si) with exposure of a high dose rate of 50 to 300rad(Si)/s and over a total ionizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. PARAMETER VOS ΔVOS IB IOS Offset Voltage Input Offset Channel-to-Channel Match Input Bias Current Input Offset Current Common Mode Input Voltage Range CMRR Common-Mode Rejection Ratio AVOL VOH VOL TYP MAX (Note 7) UNIT VCM = V+ to V- - - 400 µV VCM = V+ - - 800 µV VCM = V- - - 800 µV VCM = V+ - - 650 nA VCM = V- -650 - - nA VCM = V+ to V- -17 - 17 nA V- - V+ V - - - dB 70 - - dB CONDITIONS VCMIR PSRR MIN (Note 7) DESCRIPTION Power Supply Rejection Ratio Open-Loop Gain VCM = V- to V+ VCM = V- VCM= V+ VCM= V+ - to V+ V- + 0.5V - - - dB V- + 0.5V 80 - - dB - - - dB 88 - - dB - - - dB 96 - - dB RL = No Load - - 160 mV RL = 10kΩ - - 175 mV RL = No Load - - 150 mV RL = 10kΩ - - 165 mV - 0.5V to 0.5V to V- = -18V; V+ = 0.5V to 18V; V+ = 18V; V- = -0.5V to -18V RL = 10kΩ to ground Output Voltage High (VOUT to V+ ) Output Voltage Low (VOUT to V-) ISRC Output Short Circuit Current Sourcing; VIN = 0V, VOUT = -18V 10 - - mA ISNK Output Short Circuit Current Sinking; VIN = 0V, VOUT = +18V 10 - - mA IS Supply Current/Amplifier Unity gain - - 2.4 mA SR Large Signal Slew Rate AV = 1, RL = 10kΩ, VO = 10VP-P 60 V/µs Electrical Specifications VS = ±2.5V, VCM = VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply a total ionizing dose of 300krad(Si) with exposure of a high dose rate of 50 to 300rad(Si)/s and over a total ionizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. PARAMETER VOS ΔVOS IB MIN (Note 7) TYP MAX (Note 7) UNIT VCM = V+ to V- - - 400 µV Input Offset Channel-to-Channel Match VCM = V+ - - 800 µV VCM = V- - - 800 µV Input Bias Current VCM = V+ - - 650 nA -650 - - nA -17 DESCRIPTION Offset Voltage CONDITIONS VCM = VIOS VCMIR CMRR Input Offset Current VCM = V+ to V- - 17 nA V- - V+ V to V+ - - - dB to V+ Common Mode Input Voltage Range Common-Mode Rejection Ratio 7 VCM = V- VCM = V- 70 - - dB VCM= V+ - 0.5V to V- + 0.5V - - - dB VCM= V+ - 0.5V to V- + 0.5V 74 - - dB FN8411.1 June 14, 2013 ISL70444SEH Electrical Specifications VS = ±2.5V, VCM = VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply a total ionizing dose of 300krad(Si) with exposure of a high dose rate of 50 to 300rad(Si)/s and over a total ionizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. (Continued) PARAMETER MIN (Note 7) TYP MAX (Note 7) UNIT - - - dB 80 - - dB - - - dB 90 - - dB RL = No Load - - 85 mV RL = 10kΩ - - 105 mV RL = 600Ω - - 400 mV RL = No Load - - 85 mV RL = 10kΩ - - 105 mV RL = 600Ω - - 400 mV Unity gain - - 1.8 mA DESCRIPTION CONDITIONS V- = V+ = PSRR Power Supply Rejection Ratio -2.5V; 0.5V to 2.5V; V+ = 2.5V; V- = -0.5V to -2.5V AVOL Open-Loop Gain RL = 10kΩ to ground VOH VOL IS Output Voltage High (VOUT to V+) Output Voltage Low (VOUT to V-) Supply Current/Amplifier Electrical Specifications VS = ±1.5V, VCM = VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply a total ionizing dose of 300krad(Si) with exposure of a high dose rate of 50-300rad(Si)/s and over a total ionizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. PARAMETER VOS ΔVOS IB IOS VCMIR VOH VOL IS MIN (Note 7) TYP MAX (Note 7) UNIT VCM = V+ to V- - - 400 µV VCM = V+ - - 800 µV VCM = V- - - 800 µV VCM = V+ - - 650 nA VCM = V- -650 - - nA VCM = V+ -17 DESCRIPTION CONDITIONS Offset Voltage Input Offset Channel-to-Channel Match Input Bias Current Input Offset Current to V- - 17 nA V- - V+ V RL = No Load - - 160 mV RL = 10kΩ - - 175 mV RL = No Load - - 150 mV RL = 10kΩ - - 165 mV Unity gain - - 1.8 mA Common Mode Input Voltage Range Output Voltage High (VOUT to V+ ) Output Voltage Low (VOUT to V-) Supply Current/Amplifier NOTE: 7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 8 FN8411.1 June 14, 2013 ISL70444SEH Typical Performance Curves Unless otherwise specified, VS ± 18V, VCM = 0, VO = 0V, TA = +25°C. 120 300 200 80 60 100 IBIAS (nA) OFFSET VOLTAGE (µV) 100 40 20 0 0 -100 -20 -200 -40 -60 -20 -15 -10 -5 0 5 10 15 -300 -20 20 -15 -10 COMMON MODE VOLTAGE (V) FIGURE 3. OFFSET VOLTAGE vs COMMON MODE VOLTAGE 0 5 10 15 20 FIGURE 4. IBIAS vs COMMON MODE VOLTAGE 300 250 250 IB+ 200 IB+ 200 CURRENT (nA) CURRENT (nA) -5 COMMON MODE VOLTAGE (V) 150 IB- 100 IB- 150 100 50 50 0 -100 -50 0 50 TEMPERATURE (°C) 100 0 -100 150 -50 0 50 100 150 TEMPERATURE (°C) FIGURE 6. IBIAS vs TEMPERATURE (VS = ±2.5V) FIGURE 5. IBIAS vs TEMPERATURE (VS = ±18V) 2.5 300 IB+ 2.0 200 CURRENT (nA) CURRENT (nA) 250 IB150 100 1.5 IOS 1.0 0.5 50 0 -100 -50 0 50 100 TEMPERATURE (°C) FIGURE 7. IBIAS vs TEMPERATURE, (VS = ±1.5V) 9 150 0 -100 -50 0 50 100 150 TEMPERATURE (°C) FIGURE 8. IOS vs TEMPERATURE (VS = ±18V) FN8411.1 June 14, 2013 ISL70444SEH Typical Performance Curves Unless otherwise specified, VS ± 18V, VCM = 0, VO = 0V, TA = +25°C. (Continued) 3.5 2.5 3.0 CURRENT (nA) CURRENT (nA) 2.0 1.5 IOS 1.0 0.5 0 -100 2.5 2.0 IOS 1.5 1.0 0.5 -50 0 50 100 0 -100 150 -50 TEMPERATURE (°C) 70 70 60 60 50 50 40 VOS 20 10 0 -100 50 100 150 FIGURE 10. IOS vs TEMPERATURE (VS = ±1.5V) VOLTAGE (µV) VOLTAGE (µV) FIGURE 9. IOS vs TEMPERATURE (VS = ±2.5V) 30 0 TEMPERATURE (°C) 40 VOS 30 20 10 -50 0 50 100 0 -100 150 -50 TEMPERATURE (°C) 0 50 100 150 TEMPERATURE (°C) FIGURE 11. VOS vs TEMPERATURE (VS = ±18V) FIGURE 12. VOS vs TEMPERATURE (VS = ±2.5V) 135 50 ±18V 130 40 GAIN (dB) VOLTAGE (µV) 125 30 VOS 20 ±2.5V 120 ±1.5V 115 110 10 0 -100 105 -50 0 50 100 TEMPERATURE (°C) FIGURE 13. VOS vs TEMPERATURE (VS = ±1.5V) 10 150 100 -75 -25 25 75 TEMPERATURE (°C) 125 FIGURE 14. AVOL vs TEMPERATURE vs SUPPLY VOLTAGE FN8411.1 June 14, 2013 ISL70444SEH Typical Performance Curves Unless otherwise specified, VS ± 18V, VCM = 0, VO = 0V, TA = +25°C. (Continued) 0.0 +25°C +125°C 2.0 -55°C CURRENT (mA) CURRENT (mA) -0.5 2.5 -1.0 -1.5 -2.0 +25°C 1.5 1.0 -55°C 0.5 +125°C -2.5 0 10 20 SUPPLY DIFFERENTIAL 30 (V+ TO V -) 0.0 40 0 (V) 10 20 30 SUPPLY DIFFERENTIAL (V+ TO V-) (V) 40 FIGURE 16. POSITIVE SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 15. NEGATIVE SUPPLY CURRENT vs SUPPLY VOLTAGE 135 135 130 130 ±18V 125 ±2.5V 120 ±1.5V 115 ±18V GAIN (dB) GAIN (dB) 125 120 115 110 110 105 105 100 -75 -25 25 75 100 -75 125 ±2.5V ±1.5V -25 75 125 FIGURE 17. PSRR+ vs TEMPERATURE vs SUPPLY VOLTAGE FIGURE 18. PSRR- vs TEMPERATURE vs SUPPLY VOLTAGE 120 70 100 90 ±18V 60 ±2.5V 50 ±1.5V 80 CURRENT (mA) 110 GAIN (dB) 25 TEMPERATURE (°C) TEMPERATURE (°C) ±18V ±15V ±5V 40 30 ±2.5V 60 20 ±1.5V 50 10 70 40 -75 -25 25 75 125 TEMPERATURE (°C) FIGURE 19. CMRR vs TEMPERATURE vs SUPPLY VOLTAGE 11 0 -75 -25 25 75 TEMPERATURE (°C) 125 FIGURE 20. SHORT CIRCUIT CURRENT vs TEMPERATURE FN8411.1 June 14, 2013 ISL70444SEH Typical Performance Curves Unless otherwise specified, VS ± 18V, VCM = 0, VO = 0V, TA = +25°C. (Continued) 50 70 RL = 2kΩ 60 30 (VS+ - VOUT) (mV) (VS+ - VOUT) (mV) 40 RL = 10kΩ 20 RL = OPEN 10 RL = 2kΩ 50 40 RL = 10kΩ 30 20 RL = OPEN 10 0 -75 -25 25 75 TEMPERATURE (°C) 125 0 -75 175 -25 25 75 TEMPERATURE (°C) 125 175 FIGURE 22. (VS = ±2.5V) VOH vs TEMPERATURE FIGURE 21. (VS = ±1.5V) VOH vs TEMPERATURE 350 50 300 200 (VS- + VOUT) (mV) (VS+ - VOUT) (mV) 40 250 RL = 2kΩ 150 100 RL = 10kΩ RL = OPEN 30 RL = 10kΩ 20 10 50 0 -75 RL = 2kΩ RL = OPEN -25 25 75 125 0 -75 175 -25 TEMPERATURE (°C) 70 350 60 300 RL = 2kΩ 50 40 RL = 10kΩ 30 125 175 FIGURE 24. (VS = ±1.5V) VOL vs TEMPERATURE (VS- - VOUT) (mV) (VS- + VOUT) (mV) FIGURE 23. (VS = ±18V) VOH vs TEMPERATURE 25 75 TEMPERATURE (°C) 20 10 RL = 2kΩ 250 200 150 100 RL = 10kΩ RL = OPEN 50 RL = OPEN 0 -75 -25 25 75 TEMPERATURE (°C) 125 FIGURE 25. (VS = ±2.5V) VOL vs TEMPERATURE 12 175 0 -75 -25 25 75 TEMPERATURE (°C) 125 175 FIGURE 26. (VS = ±18V) VOL vs TEMPERATURE FN8411.1 June 14, 2013 ISL70444SEH Typical Performance Curves Unless otherwise specified, VS ± 18V, VCM = 0, VO = 0V, TA = +25°C. (Continued) 10 INPUT NOISE CURRENT (pA/√Hz) INPUT NOISE VOLTAGE (nV/√Hz) 10,000 1,000 100 10 1 0.01 0.1 1 10 100 FREQUENCY (Hz) 1k 10k 1 0.1 0.1 100k 1 10 100 1k FREQUENCY (Hz) 10k 100k FIGURE 27. INPUT NOISE VOLTAGE SPECTRAL DENSITY (VS = ±18V) FIGURE 28. INPUT NOISE CURRENT SPECTRAL DENSITY (VS = ±18V) 150 150 150 100 100 -50 GAIN -100 -50 -150 -100 -200 SIMULATION 10 1k 100k 10M 100 -250 1G 50 0 0 -50 GAIN -50 -100 -150 -200 -100 -250 SIMULATION -150 0 10 1k 100k 10M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 30. OPEN LOOP FREQUENCY RESPONSE (CL = 10pF) FIGURE 29. OPEN LOOP FREQUENCY RESPONSE (CL = 0.01pF) 150 250 250 150 200 PHASE 100 0 0 -50 GAIN 100 -100 -50 -150 -150 150 50 -200 SIMULATION 0 10 GAIN (dB) 50 PHASE (°) 50 GAIN (dB) 200 PHASE 100 150 100 -100 50 0 0 10M -300 1G FIGURE 31. OPEN LOOP FREQUENCY RESPONSE (CL = 22pF) 13 -50 GAIN -100 -50 -150 -200 -100 -250 1k 100k FREQUENCY (Hz) -300 1G PHASE (°) 0 150 50 GAIN (dB) 0 0 -150 200 PHASE 100 50 PHASE (°) GAIN (dB) 50 250 PHASE (°) 200 PHASE -250 SIMULATION -150 0 10 1k 100k 10M -300 1G FREQUENCY (Hz) FIGURE 32. OPEN LOOP FREQUENCY RESPONSE (CL = 47pF) FN8411.1 June 14, 2013 ISL70444SEH Typical Performance Curves Unless otherwise specified, VS ± 18V, VCM = 0, VO = 0V, TA = +25°C. (Continued) 250 150 200 PHASE 100 150 0 0 -50 GAIN -50 -100 GAIN (dB) GAIN (dB) 50 PHASE (°) 100 50 -150 -200 -100 SIMULATION -150 0 10 -250 1k 100k FREQUENCY (Hz) -300 1G 10M 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 -10 100 ±2.5V 1k 1M 10M 100M 60 50 G = 1000 40 ±1.5V 30 ±18V G = 100 20 G = 10 10 0 -10 G=1 -20 -30 -40 ±2.5V 1k 10k 100k 1M 10M -50 100 100M 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 35. PSRR vs FREQUENCY FIGURE 36. FREQUENCY RESPONSE vs CLOSED LOOP GAIN 20 10 RF = 10kΩ 0 0 -10 RF = 100Ω -20 GAIN (dB) GAIN (dB) 100k 70 FREQUENCY (Hz) 10 10k FIGURE 34. CMRR vs FREQUENCY GAIN (dB) GAIN (dB) ±18V FREQUENCY (Hz) FIGURE 33. OPEN LOOP FREQUENCY RESPONSE (CL = 100pF) 120 110 100 90 80 70 60 50 40 30 20 10 0 -10 100 ±1.5V RF = 1kΩ -30 -40 RL = 5kΩ RL = 2kΩ RL = 10kΩ -10 RL = 1kΩ -20 -50 -60 -70 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 37. FREQUENCY RESPONSE vs FEEDBACK RESISTANCE (RF) 14 -30 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 38. FREQUENCY RESPONSE vs LOAD RESISTANCE FN8411.1 June 14, 2013 ISL70444SEH Typical Performance Curves Unless otherwise specified, VS ± 18V, VCM = 0, VO = 0V, TA = +25°C. (Continued) 10 10 0 0 12pF 27pF -20 GAIN (dB) GAIN (dB) -10 47pF 68pF -30 -50 100 ±2.5V ±18V -20 -30 ACL = 1 RL = 10kΩ VS= ±18V -40 ±1.5V -10 1k 10k 100k 1M 10M -40 100M 100 1k 10k ±1.5V 25 15 +25°C 10 1k 10k 100k 1M FREQUENCY (Hz) 10M 0 0.0 100M 70 400 60 350 +125°C 40 -55°C +25°C 20 0.5 1.0 1.5 2.0 STEP SIZE (V) 2.5 3.0 3.5 FIGURE 42. SLEW RATE vs STEP SIZE vs TEMPERATURE (VS = ±1.5V) 450 50 +125°C 20 5 SLEW RATE (V/µs) SLEW RATE (V/µs) 100M -55°C 30 ±2.5V SLEW RATE (V/µs) GAIN (dB) ±18V 80 -55°C 300 250 +25°C +125°C 200 150 100 10 0 10M 35 FIGURE 41. CROSSTALK REJECTION 30 1M FIGURE 40. FREQUENCY RESPONSE vs SUPPLY VOLTAGE FIGURE 39. UNITY GAIN RESPONSE vs LOAD CAPACITANCE 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 100 100k FREQUENCY (Hz) FREQUENCY (Hz) 50 0 1 2 3 STEP SIZE (V) 4 5 6 FIGURE 43. SLEW RATE vs STEP SIZE vs TEMPERATURE (VS = ±2.5V) 15 0 0 5 10 15 STEP SIZE (V) 20 25 FIGURE 44. SLEW RATE vs STEP SIZE vs TEMPERATURE (VS = ±18V) FN8411.1 June 14, 2013 ISL70444SEH Typical Performance Curves Unless otherwise specified, VS ± 18V, VCM = 0, VO = 0V, TA = +25°C. (Continued) (INPUT) 200mV/DIV (INPUT) 200mV/DIV (OUTPUT) AV = -100 RL = 2kΩ RF = 100kΩ, RG = 1kΩ VIN = 400mVP-P (OUTPUT) AV = -100 RL = 1kΩ RF = 100kΩ, RG = 1kΩ VIN = 400mVP-P VS = ±18V 1µs/DIV VS = ±5V 1µs/DIV FIGURE 46. SATURATION RECOVERY (VS = ±5V) FIGURE 45. SATURATION RECOVERY (VS = ±18V) 40 VS = ±18V 35 (INPUT) 200mV/DIV RL = 10kΩ OVERSHOOT (%) 30 AV = -100 RL = 2kΩ RF = 100kΩ, RG = 1kΩ VIN = 400mVP-P AV = 1 OS- VOUT = 25mVP-P 25 20 OS+ 15 (OUTPUT) 10 VS = ±2.5V 5 0 1 10 CAPACITANCE (pF) 1µs/DIV FIGURE 47. SATURATION RECOVERY (VS = ±2.5V) 100 FIGURE 48. OVERSHOOT (%) vs LOAD CAPACITANCE 2V/DIV, INPUT 2V/DIV, OUTPUT VS = ±5V VIN = 12VP-P No Output Phase Reversal 10µs/DIV FIGURE 49. INPUT OVERDRIVE RESPONSE 16 FN8411.1 June 14, 2013 ISL70444SEH Post High Dose Rate Radiation Characteristics Unless otherwise specified, VS ± 18V, VCM = 0, VO = 0V, TA = +25°C. This data is typical mean test data post radiation exposure at a high dose rate of 50 to 300rad(Si)/s. This data is intended to show typical parameter shifts due to high dose rate radiation. These are not limits nor are they guaranteed. 30 30 Vs = ±18V Vs = ±18V 20 20 10 10 0 CURRENT (nA) VOS (µV) GROUNDED GROUNDED -10 0 BIASED -10 BIASED -20 -20 -30 0 50 100 150 200 250 -30 300 0 50 100 krad (Si) 0.8 300 Vs = ±18V 0.6 0.4 0.4 CURRENT (mA) BIASED GROUNDED 0 -0.2 0.2 0 -0.4 -0.6 -0.6 50 100 150 200 250 -0.8 300 GROUNDED -0.2 -0.4 BIASED 0 50 100 krad (Si) FIGURE 52. I- SHIFT vs HIGH DOSE RATE RADIATION 150 krad (Si) 200 250 300 FIGURE 53. I+ SHIFT vs HIGH DOSE RATE RADIATION 2.0 Vs = ±18V 1.5 1.0 CURRENT (nA) CURRENT (mA) 250 0.8 Vs = ±18V 0.6 -0.8 0 200 FIGURE 51. IBIAS SHIFT vs HIGH DOSE RATE RADIATION FIGURE 50. VOS SHIFT vs HIGH DOSE RATE RADIATION 0.2 150 krad (Si) 0.5 BIASED 0 GROUNDED -0.5 -1.0 -1.5 -2.0 0 50 100 150 200 250 300 krad(Si) FIGURE 54. IOS SHIFT vs HIGH DOSE RATE RADIATION 17 FN8411.1 June 14, 2013 ISL70444SEH Post Low Dose Rate Radiation Characteristics Unless otherwise specified, VS ± 18V, VCM = 0, VO = 0V, TA = +25°C. This data is typical mean test data post radiation exposure at a low dose rate of <10mrad(Si)/s. This data is intended to show typical parameter shifts due to high dose rate radiation. These are not limits nor are they guaranteed. 30 30 Vs = ±18V Vs = ±18V 20 20 GROUNDED VOS (µV) 10 CURRENT (nA) BIASED 0 -10 GROUNDED 10 0 -20 -20 -30 0 10 20 30 40 50 60 krad (Si) 70 80 90 -30 0 100 10 30 40 50 60 krad (Si) 70 80 90 100 0.8 6 Vs = ±18V Vs = ±18V 0.6 4 0.4 CURRENT (mA) BIASED 2 0 -2 GROUNDED 0.2 GROUNDED 0 -0.2 -0.4 -4 BIASED -0.6 0 10 20 30 40 50 60 krad (Si) 70 80 90 -0.8 100 0 10 20 30 40 50 60 krad (Si) 70 80 90 100 FIGURE 58. I+ SHIFT vs LOW DOSE RATE RADIATION FIGURE 57. IOS SHIFT vs LOW DOSE RATE RADIATION 0.8 Vs = ±18V 0.6 BIASED 0.4 CURRENT (mA) -6 20 FIGURE 56. IBIAS SHIFT vs LOW DOSE RATE RADIATION FIGURE 55. VOS SHIFT vs LOW DOSE RATE RADIATION CURRENT (nA) BIASED -10 0.2 0 GROUNDED -0.2 -0.4 -0.6 -0.8 0 10 20 30 40 50 60 krad (Si) 70 80 90 100 FIGURE 59. I- SHIFT vs LOW DOSE RATE RADIATION 18 FN8411.1 June 14, 2013 ISL70444SEH Applications Information Output Short Circuit Current Limiting Functional Description The ISL70444SEH contains four high speed and low power op amps designed to take advantage of its full dynamic input and output voltage range with rail to rail operation. By offering low power, low offset voltage, and low temperature drift coupled with its high bandwidth and enhanced slew rates upwards of 50V/µs, these op amps are ideal for applications requiring both high DC accuracy and AC performance. The ISL70444SEH is manufactured in Intersil’s PR40 silicon-on-insulator process, which makes this device immune to Single Event Latch-up and provides excellent radiation tolerance. This makes it the ideal choice for high reliability applications in harsh radiation-prone environments. The output current limit has a worst case minimum limit of ±8mA but may reach as high as ±100mA. The op amp can withstand a short circuit to either rail for a short duration (<1 second) as long as the maximum operating junction temperature is not violated. This applies to only one amplifier at a given time. Continued use of the device in these conditions may degrade the long term reliability of the part and is not recommended. Figure 20 shows the typical short circuit currents that can be expected. The ISL70444SEH’s current limiting circuitry will automatically lower the current limit of the device if short circuit conditions carry on for extended periods in time in an effort to protect itself from malfunction, however extended operation in this mode will degrade the output rail-to-rail performance by increasing the VOH/VOL levels. Operating Voltage Range Output Phase Reversal The devices are designed to operate with a split supply rail from ±1.35V to ±20V or a single supply rail from 2.7V to 40V. The ISL70444SEH is fully characterized in production for supply rails of 5V (±2.5V) and 36V (±18V). The Power Supply Rejection Ratio is typically 120dB over the full operating voltage range. The worst case common mode rejection ratio over temperature is within 1.5V to 2V of each rail. When VCM is inside that range, the CMRR performance is typically >110dB with ±18V supplies. The minimum CMRR performance over the -55°C to +125°C temperature range and radiation is >70dB over the full common mode input range for power supply voltages from ±2.5V (5V) to ±18V (36V). Output phase reversal is a change of polarity in the amplifier transfer function when the input voltage exceeds the supply voltage. The ISL70444SEH is immune to output phase reversal, even when the input voltage is 1V beyond the supplies. This is illustrated in Figure 49. Input Performance The slew enhanced front end is a block that is placed in parallel with the main input stage and functions based on the input differential. Input ESD Diode Protection The input terminals (IN+ and IN-) have internal ESD protection diodes to the positive and negative supply rails, series connected 600Ω current limiting resistors and an anti-parallel diode pair across the inputs. Power Dissipation It is possible to exceed the +150°C maximum junction temperatures under certain load and power supply conditions. It is therefore important to calculate the maximum junction temperature (TJMAX) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related using Equation 1: (EQ. 1) T JMAX = T MAX + θ JA x PD MAXTOTAL where: • PDMAXTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PDMAX) • PDMAX for each amplifier can be calculated using Equation 2: V OUTMAX PD MAX = V S × I qMAX + ( V S - V OUTMAX ) × ---------------------------R (EQ. 2) L where: V+ • TMAX = Maximum ambient temperature • θJA = Thermal resistance of the package - 600Ω VIN VOUT + 600Ω RL • PDMAX = Maximum power dissipation of 1 amplifier • VS = Total supply voltage • IqMAX = Maximum quiescent supply current of 1 amplifier • VOUTMAX = Maximum output voltage swing of the application V- FIGURE 60. INPUT ESD DIODE CURRENT LIMITING, UNITY GAIN 19 FN8411.1 June 14, 2013 ISL70444SEH Unused Channel Configuration The ISL70444SEH is a quad op amp. If the application does not require the use of all four op amps, the user must configure the unused channels to prevent it from oscillating. Any unused channels will oscillate if the input and output pins are floating. This results in higher-than-expected supply currents and possible noise injection into any active channels being used. The proper way to prevent oscillation is to short the output to the inverting input, and ground the positive input (Figure 61). + FIGURE 61. PREVENTING OSCILLATIONS IN UNUSED CHANNELS 20 FN8411.1 June 14, 2013 ISL70444SEH Die Characteristics Die Dimensions Assembly Related Information SUBSTRATE POTENTIAL 2410µm x 3175µm (80mils x 101mils) Thickness: 483µm ± 25µm (19mils ± 1 mil) Interface Materials Floating ADDITIONAL INFORMATION WORST CASE CURRENT DENSITY GLASSIVATION < 2 x 105 A/cm2 Type: Nitrox Thickness: 15kÅ TRANSISTOR COUNT 730 TOP METALLIZATION Weight of Packaged Device Type: AlCu (99.5%/0.5%) Thickness: 30kÅ 0. 5952 Grams (Typical) Lid Characteristics BACKSIDE FINISH Silicon Finish: Gold Potential: Unbiased, tied to E-pad under package Case Isolation to Any Lead: 20 x 109 Ω (min) PROCESS PR40 Metallization Mask Layout 21 FN8411.1 June 14, 2013 ISL70444SEH TABLE 1. DIE LAYOUT X-Y COORDINATES PAD NAME PAD NUMBER X (µm) Y (µm) dX (µm) dY (µm) BOND WIRES PER PAD OUTB 2 599.0 -11.5 70 70 1 OUTC 3 1472.0 -11.5 70 70 1 -INC 4 2071.0 0.0 70 70 1 +INC 12 2071.0 347.5 70 70 1 V- 20 2071.0 1406.5 70 70 1 +IND 21 2071.0 2465.5 70 70 1 -IND 22 2071.0 2813.0 70 70 1 OUTD 23 1472.0 2824.5 70 70 1 OUTA 24 599.0 2824.5 70 70 1 -INA 25 0.0 2813.0 70 70 1 +INA 33 0.0 2465.5 70 70 1 V+ 41 0.0 1406.5 70 70 1 +INB 42 0.0 347.5 70 70 1 -INB 1 0.0 0.0 70 70 1 NOTE: 8. Origin of coordinates is the centroid of pad 42, “IN-B”. Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE June 14, 2013 FN8411.1 Changed Radiation tolerance High dose rate from 100krad(Si) to 300krad(Si) on page 1 features and in Electrical Spec Table conditions on pages 7 and 8. Added SR spec for VS = ±18V to Electrical Spec Table on page 7. Removed Max limit of 300 for VOS Offset Voltage in VS = ±18V, VS = ±2.5V and VS = ±1.5V Spec tables. May 23, 2013 FN8411.0 Initial Release. About Intersil Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at http://www.intersil.com/en/support/qualandreliability.html#reliability For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 22 FN8411.1 June 14, 2013 ISL70444SEH Package Outline Drawing K14.C 14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE Rev 0, 9/12 A A 0.050 (1.27 BSC) PIN NO. 1 ID AREA 0.390 (9.91) 0.376 (9.55) 1 TOP VIEW 0.022 (0.56) 0.005 (0.13) MIN 3 0.015 (0.38) 0.115 (2.92) 0.009 (0.23) 0.045 (1.14) 0.085 (2.16) 0.026 (0.66) 5 0.260 (6.60) 0.248 (6.30) -C- BOTTOM METAL 0.183 (4.65) 0.370 (9.40) 0.167 (4.24) 0.270 (6.86) -H- 0.03 (0.76) MIN 6 SEATING AND BASE PLANE 0.004 (0.10) -D- SIDE VIEW BOTTOM METAL 0.005 (0.127) REF. OFFSET FROM CERAMIC EDGE OPTIONAL PIN 1 INDEX BOTTOM VIEW NOTES: 0.006 (0.15) 0.004 (0.10) 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. LEAD FINISH 2. The maximum limits of lead dimensions (section A-A) shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. BASE METAL 0.019 (0.48) 0.015 (0.38) 0.0015 (0.04) MAX 4. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 6. The bottom of the package is a solderable metal surface. 2 23 3. Measure dimension at all four corners. 5. Dimension shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 0.022 (0.56) 0.015 (0.38) SECTION A-A 0.009 (0.23) 0.004 (0.10) 7. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 8. Dimensions: INCH (mm). Controlling dimension: INCH. FN8411.1 June 14, 2013