5962-15247

REVISIONS
LTR
DESCRIPTION
DATE (YR-MO-DA)
APPROVED
REV
SHEET
REV
SHEET
15
16
17
18
19
20
REV STATUS
REV
OF SHEETS
SHEET
PMIC N/A
PREPARED BY
21
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28
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30
1
2
3
4
5
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9
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RODNEY D. CHAMBERS
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
12
13
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil
CHECKED BY
RAJESH PITHADIA
APPROVED BY
CHARLES F. SAFFLE
DRAWING APPROVAL DATE
16-03-14
REVISION LEVEL
MICROCIRCUIT, DIGITAL-LINEAR, BiCMOS,
SINGLE 16-CHANNEL ANALOG MUX WITH
OVERVOLTAGE PROTECTION, MONOLITHIC
SILICON
SIZE
CAGE CODE
A
67268
SHEET
DSCC FORM 2233
APR 97
11
5962-15247
1 OF 30
5962-E492-15
14
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q) and
space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or
Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
L
Federal
stock class
designator
\
15247
RHA
designator
(see 1.2.1)
01
V
X
C
Device
type
(see 1.2.2)
Device
class
designator
(see 1.2.3)
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
/
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type. This device type identifies the circuit function as follows:
Device type
01
Generic number
Circuit function
ISL71830SEH
Radiation hardened, dielectrically isolated (DI),
BICMOS, single 16-channel analog
MUX with high impedance analog
Input overvoltage protection
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class
Device requirements documentation
Q, V
Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
X
Descriptive designator
Terminals
CDFP3-F28
28
Package style
Flat pack with grounded lid
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-15247
A
REVISION LEVEL
SHEET
2
1.3 Absolute maximum ratings. 1/
Supply voltage between VS and GND ....................................................................................... 7 V
VREF to GND ............................................................................................................................. 7 V
Digital input overvoltage range ................................................................................................. VREF to GND
Maximum current through a selected switch ............................................................................. 10mA
Analog input overvoltage range (power on/off) ......................................................................... -0.4 V to 7 V
Storage temperature range ....................................................................................................... -65°C to +150°C
Junction temperature (TJ) ......................................................................................................... +150°C
Lead temperature (soldering, 10 seconds) ............................................................................... +275°C
Thermal resistance, junction-to-case (θJC) ................................................................................ 4°C/W
Thermal resistance, junction-to-ambient (θJA) ........................................................................... 48°C/W
1.4 Recommended operating conditions.
Supply voltage (VS) ................................................................................................................... 3.0 V to 5.5 V
VREF .......................................................................................................................................... 3.0 V to 5.5 V dc
Ambient operating temperature range (TA) ............................................................................... -55°C to +125°C
1.5 Radiation features.
Maximum total dose available (low dose rate ≤ 10 mrad(Si)/s): .............................................. 50 krad(Si) 2/
Single event phenomena (SEP):
2
No SEL occurs at effective linear energy threshold (LET): ...................................................≤ 60 MeV·cm /mg 3/ 4/
2
No SEB occurs at effective linear energy threshold (LET): ...................................................≤ 60 MeV·cm /mg 4/
Single event transients (SET) observed at an effective LET (see 4.4.4.3)
-5
2
2
(SET magnitude of ±20 mV at a cross section 2X10 cm ) ................ .................................= 43 MeV cm /mg 4/
______
1/
Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
2/ Device type 01 has been tested at low dose rate only. The radiation end point limits for the noted parameters are
guaranteed only for the conditions as specified in MIL-STD-883, method 1019, condition D to a maximum total ionizing dose
(TID) level of 75 krads(Si). Device type 01 is wafer acceptance tested to 75 krads(Si) total ionizing dose per MIL-STD-883,
method 1019, condition D, per customer request, and are marked at the standard 50 krads(Si) level.
3/
Device type 01 use silicon on insulator (SOI) technology. No single-event burnout (SEB) or single-event latchup (SEL)
2
was observed when irradiated with Pr ions at normal incidence, corresponding to a surface LET of 60 MeV·cm /mg.
The normal particle range into silicon for Pr ions after 30 mm of air is about 110 µm and the Bragg peak range is 37µm,
resulting in ion penetration well beyond the sensitive volume of the devices.
4/
Limits are characterized at initial qualification and after any design or process changes which may affect the SEP
characteristics, but are not production tested unless specified by the customer through the purchase order or contract.
For more information on SEP test results, customers are requested to contact the manufacturer.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-15247
A
REVISION LEVEL
SHEET
3
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 MIL-STD-1835 -
Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 MIL-HDBK-780 -
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Copies of these documents are available online at http://quicksearch.dla.mil or from the Standardization Document Order
Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.
Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract.
ASTM INTERNATIONAL (ASTM)
ASTM F1192 - Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irradiation
of semiconductor Devices.
(Copies of these documents are available online at http://www.astm.org or from ASTM International, 100 Barr Harbor Drive,
P.O. Box C700, West Conshohocken, PA, 19428-2959).
2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 as specified herein, or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein.
3.1.1 Microcircuit die. For the requirements of microcircuit die, see appendix A to this document.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and herein for device classes Q and V.
3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.3 Truth table. The truth table shall be as specified on figure 2.
3.2.4 Logic diagrams. The logic diagrams shall be as specified on figure 3.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-15247
A
REVISION LEVEL
SHEET
4
3.2.5 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document
revision level control and shall be made available to the preparing and acquiring activity upon request.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the
full ambient operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical
tests for each subgroup are defined in table IA.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance
submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the
manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall
be provided with each lot of microcircuits delivered to this drawing.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-15247
A
REVISION LEVEL
SHEET
5
TABLE IA. Electrical performance characteristics.
Test
Symbol
Conditions 1/
-55°C ≤ TA ≤ +125°C
Group A
subgroups
Device
type
VS = 5 V, VREF = 3.3V
unless otherwise specified
Channel on
resistance
RON
VS = 4.5 V, VIN = 0 V to VS
ΔRON
ΔRON-FL
VS = 4.5 V,
VIN = 0 V, 2.25V, 4.5V,
IOUT = 1 mA
IIN(OFF)
VS = 4.5 V, VIN = 0 V to VS
IOUT = 1 mA
VS = 5.5 V, VIN = 5 V,
all unused inputs and output
equal = 0.5V, see figure 4 2/
M, D, P, L
M, D, P, L
Switch off leakage
into the input of an
unselected
channel with
supplies grounded
IIN(OFF-OV)
IIN(PWR-OFF)
VS = 5.5 V, VIN = +7 V,
VOUT = 0 V,
unused inputs =0V,
see figure 4
M, D, P, L
VIN = +7 V,
VREF = VEN = VA = ±VS = 0 V,
unused inputs = 0 V,
see figure 4
IIN(PWR-OFF)
VIN = +7 V,
VREF = VEN = VA = ±VS = 0 V,
unused inputs = 0 V,
see figure 4
1, 2, 3
5
01
Ω
40
40
30
1 3/
-30
30
1, 2, 3
-30
30
1 3/
-30
30
-30
30
2
-30
120
1 3/
-30
30
-20
20
2
-20
50
1 3/
-20
20
-20
20
2
-20
50
1 3/
-20
20
1, 3
Ω
5
-30
1,3
M, D, P, L
01
1 3/
1,3
M, D, P, L
Switch off leakage
into the input of an
unselected
channel with
supplies open
Ω
120
1 3/
1,2,3
VS = 5.5 V, VIN = 0.5 V,
all unused inputs and output
equal = 5V, see figure 4 2/
Switch Input Off
Over Voltage
Max
120
1 3/
1,2,3
M, D, P, L
Switch Input Off
Leakage
Unit
01
M, D, P, L
RON flatness
Min
1,2,3
IOUT = 1 mA
M, D, P, L
RON match between
channels
Limits
01
01
01
01
nA
nA
nA
nA
nA
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-15247
A
REVISION LEVEL
SHEET
6
TABLE IA. Electrical performance characteristics - Continued.
Test
Symbol
Switch on leakage
into the input of a
selected channel
(over voltage)
Switch off leakage
into the output with
the part disabled
IIN(ON-OV)
IOUT(OFF)
Conditions 1/
-55°C ≤ TA ≤ +125°C
VS = 5 V, VREF = 3.3V
unless otherwise specified
VS = 5.5V, VIN = +7V,
VOUT = OPEN,
unused inputs = 0 V,
see figure 4
M, D, P, L
VS = 5.5V, VIN = 0.5 V,
VOUT = 5.0 V,
see figure 4 2/
VS = 5.5V, VIN = 5.0 V,
VOUT = 0.5 V,
see figure 4 2/
M, D, P, L
IOUT (ON)
VS = 5.5V, VIN = VOUT = 5.0 V,
unused inputs = 0.5 V,
see figure 4 2/
M, D, P, L
VS = 5.5V, VIN = VOUT = 0.5 V,
unused inputs = 5.0 V,
see figure 4 2/
M, D, P, L
Device
type
Limits
Unit
Min
Max
2.75
5.5
2.75
5.5
-30
30
2
0
150
1 3/
-30
30
1, 3
-30
30
2
-60
0
1 3/
-30
30
-30
30
2
0
150
1 3/
-30
30
1, 3
-30
30
2
-60
0
1 3/
-30
30
1, 2, 3
01
1 3/
1, 3
M, D, P, L
Switch on leakage
into the
input/output for a
selected switch
Group A
subgroups
1, 3
01
01
µA
nA
nA
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-15247
A
REVISION LEVEL
SHEET
7
TABLE IA. Electrical performance characteristics - Continued.
Test
Logic input high/low
voltage
Symbol
VIH/VIL
Conditions 1/
-55°C ≤ TA ≤ +125°C
VS = 5 V, VREF = 3.3V
unless otherwise specified
Group A
subgroups
VS = 5.5V, VREF = 3.3V
level
1, 2, 3
M, D, P, L
Input Current Into VA
and
IIH/IIL
Quiescent supply
current
Supply current in VREF
ISUPPLY
IREF
Capacitance:
channel input
CIN(OFF)
Capacitance:
channel output
COUT(OFF)
Off isolation
VISO
Crosstalk rejection
VCT
Charge injection
VCTE
01
1 3/
VS = 5.5V,
VREF = VEN = VA = 3.3V
VEN
Device
type
1, 2, 3
M, D, P, L
1 3/
VS = VREF = VEN = 5.5V,
VA = 0 V 2/
1,3
01
Limits
Unit
Min
Max
1.3
1.6
1.3
1.6
-100
100
-100
100
01
100
2
300
M, D, P, L
1 3/
300
VS = VREF = VEN = 5.5V,
VA = 0 V 2/
1,2,3
M, D, P, L
1 3/
+VS = - VS = 0 V,
f = 1 MHz, TA = +25°C,
see 4.4.1c
+VS = - VS = 0 V,
f = 1 MHz, TA = +25°C,
see 4.4.1c
VEN = VREF, f = 1 kHz,
RL = OPEN,
VS = 1 VRMS,
TA = +25°C, see 4.4.1c
VEN = 0.8 V, f = 1 kHz,
RL = OPEN,
VS = 1 VRMS,
TA = +25°C, see 4.4.1c
CL = 100 pF, VIN = 0 V,
see 4.4.1c
01
200
V
nA
nA
nA
200
4
01
5
pF
4
01
25
pF
4
01
60
dB
4
01
73
dB
4
01
5
pC
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-15247
A
REVISION LEVEL
SHEET
8
TABLE IA. Electrical performance characteristics - Continued.
Test
Symbol
Functional test
Transition time from
address inputs to output
tTRANS
Conditions 1/
-55°C ≤ TA ≤ +125°C
VS = 5 V, VREF = 3.3V
unless otherwise specified
Group A
subgroups
See 4.4.1d
7,8A,8B
01
CL = 50 pF RL = 10 kΩ,
VS = 4.5 V
9, 10,11
01
9 3/
M, D, P, L
Break-before-make
time delay
tBBM
CL = 50 pF RL = 100 Ω,
VS = 4.5 V
See figure 5
9, 10,11
tON(EN)
CL = 50 pF RL = 1 kΩ,
VS = 4.5 V
9, 10,11
M, D, P, L
Propagation delay
time disable to I/O
channels
tOFF(EN)
01
9 3/
M, D, P, L
Propagation delay
time enable to I/O
channels
Device
type
01
9 3/
CL = 50 pF RL = 1 kΩ,
VS = 4.5 V
Unit
Min
Max
10
70
10
70
5
40
5
40
40
ns
ns
ns
40
9, 10,11
M, D, P, L
Limits
01
9 3/
40
ns
40
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-15247
A
REVISION LEVEL
SHEET
9
TABLE IA. Electrical performance characteristics - Continued.
Test
Symbol
Channel on
resistance
RON
Conditions 4/
-55°C ≤ TA ≤ +125°C
VS = 3.3 V, VREF = 3.3V
unless otherwise specified
VS = 3.0 V, VIN = 0 V to VS
IOUT = 1 mA
ΔRON
VS = 3.0 V,
VIN = 0.5 V, 2.5V
IOUT = 1 mA
ΔRON-FL
VS = 3.0 V, VIN = 0 V to VS
IOUT = 1 mA
IIN(OFF)
VS = 3.6 V, VIN = 3.1 V,
all unused inputs and output
equal = 0.5V, see figure 4 5/
M, D, P, L
M, D, P, L
IIN(OFF-OV)
Unit
Max
Ω
200
1 3/
VS = 3.6 V, VIN = +7 V,
VOUT = 0 V,
unused inputs =0 V,
see figure 4
M, D, P, L
200
01
5
01
50
-30
30
1 3/
-30
30
1, 2, 3
-30
30
1 3/
-30
30
-30
30
2
-30
100
1 3/
-30
30
1, 3
Ω
50
1 3/
1, 2, 3
Ω
5
1 3/
1,2,3
VS = 3.6 V, VIN = 0.5 V,
all unused inputs and output
equal = 3.1V, see figure 4 5/
Switch Input Off
Over Voltage
Min
1,2,3
M, D, P, L
Switch Input Off
Leakage
Limits
01
M, D, P, L
RON flatness
Device
type
1,2,3
M, D, P, L
RON match between
channels
Group A
subgroups
01
01
nA
nA
nA
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-15247
A
REVISION LEVEL
SHEET
10
TABLE IA. Electrical performance characteristics - Continued.
Test
Symbol
Switch on leakage
into the input of a
selected channel
(over voltage)
Switch off leakage
into the output with
the part disabled
IIN(ON-OV)
IOUT(OFF)
Conditions 4/
-55°C ≤ TA ≤ +125°C
VS = 3.3 V, VREF = 3.3V
unless otherwise specified
VS = 3.6 V, VIN = +7 V,
VOUT = OPEN,
unused inputs = 0 V,
see figure 4
M, D, P, L
VS = 3.6 V, VIN = 0.5 V,
VOUT = 3.1 V,
see figure 4 5/
VS = 3.6 V, VIN = 3.1 V,
VOUT = 0.5 V,
see figure 4 5/
M, D, P, L
IOUT(ON)
VS = 3.6V, VIN = VOUT = 3.1 V,
unused inputs = 0.5 V,
see figure 4 5/
M, D, P, L
VS = 3.6V, VIN = VOUT = 0.5 V,
unused inputs = 3.1 V,
see figure 4 5/
M, D, P, L
Device
type
Limits
Unit
Min
Max
1.8
3.6
1.8
3.6
-30
30
2
0
60
1 3/
-30
30
1, 3
-30
30
2
0
30
1 3/
-30
30
-30
30
2
0
30
1 3/
-30
30
1, 3
-30
30
2
0
30
1 3/
-30
30
1, 2, 3
01
1 3/
1, 3
M, D, P, L
Switch on leakage
into the
input/output for a
selected switch
Group A
subgroups
1, 3
01
01
µA
nA
nA
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-15247
A
REVISION LEVEL
SHEET
11
TABLE IA. Electrical performance characteristics - Continued.
Test
Quiescent supply
current
Symbol
ISUPPLY
Conditions 4/
-55°C ≤ TA ≤ +125°C
VS = 3.3V, VREF = 3.3V
unless otherwise specified
VS = VREF = VEN = 3.6V, VA
= 0 V 5/
Group A
subgroups
IREF
1,3
VS = VREF = VEN = 3.6V, VA
= 0 V 5/
Transition time from
address inputs to output
tTRANS
tBBM
Propagation delay
time enable to I/O
channels
tON(EN)
tOFF(EN)
1 3/
300
01
200
CL = 50 pF RL = 10 kΩ,
VS = 3.0V
9, 10,11
01
9 3/
9, 10,11
01
9 3/
CL = 50 pF RL = 1 kΩ,
VS = 3.0V
9, 10,11
10
100
10
100
5
50
5
50
01
9 3/
CL = 50 pF RL = 1 kΩ,
VS = 3.0V
nA
ns
ns
50
ns
50
9, 10,11
M, D, P, L
nA
200
01
M, D, P, L
Propagation delay
time disable to I/O
channels
300
7,8A,8B
M, D, P, L
Max
2
See 4.4.1d
CL = 50 pF RL = 100 Ω,
VS = 3.0V
See figure 5
Unit
100
1 3/
M, D, P, L
Break-before-make
time delay
01
1,2,3
M, D, P, L
Functional test
Limits
Min
M, D, P, L
Supply current in VREF
Device
type
01
9 3/
50
ns
50
1/
Unless otherwise specified, VAH (logic level high) = 3.3 V dc, VAL (logic level low) = 0 V dc, VEN = 3.3 V, and
VREF = 3.3 V dc. VS = 5.0 V dc.
2/
VS = 5.5V dc. VAH (logic level high) = 3.3 V dc, VAL (logic level low) = 0 V dc and VREF = 3.3 V dc.
3/
RHA device type 01 supplied to this drawing will meet all levels M, D, P and L of irradiation for condition D. However,
device type 01 is only tested in accordance with MIL-STD-883, method 1019, condition D (see 1.5 herein) at a total ionizing
dose of 75 krads(Si). Device type 01 is wafer acceptance tested 75 krads(Si) total ionizing dose per MIL-STD-883, method
1019, condition D, per customer request, and are marked at the standard 50 krads(Si) level.
Pre and Post irradiation values and parameters are as specified in Table IA. When performing post irradiation electrical
measurements for any RHA level, TA = +25°C.
4/
Unless otherwise specified, VAH (logic level high) = 3.3 V dc, VAL (logic level low) = 0 V dc, VEN = 3.3 V, and
VREF = 3.3 V dc. VS = 3.3 V dc.
5/
VS = 3.6 V dc. VAH (logic level high) = 3.3 V dc, VAL (logic level low) = 0 V dc and VREF = 3.3 V dc.
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TABLE IB. SEP test limits. 1/ 2/
Device type
SEP
Temperature (TC)
Linear energy transfer (LET)
01
No SEL
125°C
Effective LET= 60 MeV-cm /mg
3/ 4/
No SEB
125°C
Effective LET=60 MeV-cm /mg
4/
SET Observed
25°C
LET= 43 MeV-cm /mg 5/
2
2
2
1/ For SEP test conditions, see 4.4.4.5 herein.
2/ Technology characterization and model verification supplemented by in-line data may be
used in lieu of end of line testing. Test plan must be approved by the technical review board
and qualifying activity.
3/ Device type 01 uses silicon on insulator (SOI) technology. No single-event burnout (SEB) or
single-event latchup (SEL) was observed when irradiated with Pr ions at normal incidence,
2
corresponding to a surface LET of 60 MeV·cm /mg. The normal particle range into silicon for Pr ions
after 30 mm of air is about 110 µm and the Bragg peak range is 37 µm, resulting in ion penetration
well beyond the sensitive volume of the devices.
4/ SEL and SEB testing was performed at a supply voltage of VS = 6.3 V, VREF = 6.3 V
5/ SET testing was performed at supply voltages of VS = 3.0V and VS = 5.5 V. VREF = 3 V for both supplies
-5 2
tested. SET magnitude of ±20 mV at a cross section 2X10 cm was observed
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Device type
01
Case outline
X
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
1
Vs
15
A2
2
NC
16
A1
3
NC
17
A0
4
IN 16
18
EN
5
IN 15
19
IN 1
6
IN 14
20
IN 2
7
IN 13
21
IN 3
8
IN 12
22
IN 4
9
IN 11
23
IN 5
10
IN 10
24
IN 6
11
IN 9
25
IN 7
12
GND
26
IN 8
13
VREF
27
NC
14
A3
28
OUT
Package lid
Tied internally to terminal 12 (GND).
NC = No connection
FIGURE 1. Terminal connections.
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Truth table
A3
A2
A1
A0
EN
On channel
X
X
X
X
H
None
L
L
L
L
L
1
L
L
L
H
L
2
L
L
H
L
L
3
L
L
H
H
L
4
L
H
L
L
L
5
L
H
L
H
L
6
L
H
H
L
L
7
L
H
H
H
L
8
H
L
L
L
L
9
H
L
L
H
L
10
H
L
H
L
L
11
H
L
H
H
L
12
H
H
L
L
L
13
H
H
L
H
L
14
H
H
H
L
L
15
H
H
H
H
L
16
FIGURE 2. Truth table.
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FIGURE 3. Logic diagram.
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FIGURE 4. Test circuits for dc levels.
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FIGURE 5. Test circuits and waveforms for ac levels.
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FIGURE 5. Test circuits and waveforms for ac levels – cont.
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4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection.
4.2.1 Additional criteria for device classes Q and V.
a.
The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
b.
Interim and final electrical test parameters shall be as specified in table IIA herein.
c.
Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, Appendix B.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections, and as specified herein.
4.4.1 Group A inspection.
a.
Tests shall be as specified in table IIA herein.
b.
Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted.
c.
Subgroup 4 (CIN(OFF), COUT(OFF), VCT, VCTE, and VISO measurements) should be measured for initial qualification and
after any process or design changes which may affect input or output capacitance.
d.
For device classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device.
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.2.1 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with MILPRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MILSTD-883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
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TABLE IIA. Electrical test requirements.
Test requirements
Subgroups
(in accordance with
MIL-PRF-38535, table III)
Device
class Q
Device
class V
Interim electrical
parameters (see 4.2)
1,7,9
1,7,9
Final electrical
parameters (see 4.2)
1,2,3,7,8A, 1/
8B,9,10,11
1,2,3, 1/ 2/
7,8A,8B,9,
10,11
Group A test
requirements (see 4.4)
1,2,3,7,8A,
8B,9,10,11
Group C end-point electrical
parameters (see 4.4)
1,2,3,4,7,8A,
8B,9,10,11
1,2,3,4,7, 2/
8A,8B,9,10,11
Group D end-point electrical
parameters (see 4.4)
1,7,9
1,7,9
Group E end-point electrical
parameters (see 4.4)
1,7,9
1,7,9
1,2,3,7,8A,
8B,9,10,11
1/ For device class Q, PDA applies to subgroup 1.
For device class V, PDA applies to subgroups 1, 7, and ∆.
2/ Delta limits (see table IIB) shall be required and the delta values shall be computed
with reference to the zero hour electrical parameters (see table IA).
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TABLE IIB. Burn-in and operating life test delta parameters. TA = +25°C.
Parameters
Supply Current
+5.5v, +3.6v
Symbol
Conditions
Delta limits
ISUPPLY
Vref and Ven = V+
±60 nA
IREF
V+ and Ven = Vref
±70 nA
RON
VS = +3.0 V
ID = 1 mA
±20 Ω
RON
VS = +4.5 V
ID = 1 mA
±15 Ω
IIH/IIL
Measure inputs sequentially,
ground all unbiased pins
±20 nA
Switch Off Leakage Into the
Source of an Unselected Channel
IiN(OFF)
VS = +5.5 V
VIN = +5V
Measure inputs sequentially
±5 nA
Switch Off Leakage Into the Drain
with the Part Disabled
IOUT(OFF)
VS = +5.5 V
VOUT = +5V
±5 nA
Switch On Leakage Into the
Source/Drain for a Selected
Switch
IOUT(ON)
VS = +5.5 V
VIN=VOUT= +5V
±5 nA
Reference Current
+5.5v, +3.6v
Switch on resistance
Switch on resistance
Input leakage current,
Address and Enable pin(s)
VS = 5.5 V
VIN = +.5V
Measure inputs sequentially
±5 nA
IOUT(OFF)
VS = +5.5 V
VOUT = +.5V
±5 nA
IOUT(ON)
VS = +5.5 V
VIN=VOUT= +.5V
±5 nA
Switch Off Leakage Into the
Source of an Unselected Channel
IIN(OFF)
Switch Off Leakage Into the Drain
with the Part Disabled
Switch On Leakage Into the
Source/Drain for a Selected Switch
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4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured
(see 3.5 herein).
a.
End-point electrical parameters shall be as specified in table IIA herein.
b.
For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. All device classes must meet the postirradiation end-point
electrical parameter limits as defined in table IA at TA = +25°C ±5°C, after exposure, to the subgroups specified in table
IIA herein.
4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883
method 1019, condition D, as specified herein.
4.4.4.1.1 Accelerated annealing test. Accelerated annealing tests shall be performed on all devices requiring a RHA level
greater than 5 krads(Si). The post-anneal end-point electrical parameter limits shall be as specified in table IA herein and shall
be the pre-irradiation end-point electrical parameter limit at +25°C ±5°C. Testing shall be performed at initial qualification and
after any process or design changes which may affect the RHA response of the device.
4.4.4.2 Single event phenomena (SEP). When specified in the purchase order or contract, SEP testing shall be performed on
class V devices. SEP testing shall be performed on the Standard Evaluation Circuit (SEC) or alternate SEP test vehicle as
approved by the qualifying activity at initial qualification and after any design or process changes which may affect the upset or
latchup characteristics. Test four devices with zero failures. ASTM F1192 may be used as a guideline when performing SEP
testing. The test conditions for SEP are as follows:
a. The ion beam angle of incidence shall be between normal to the die surface and 60° to the normal, inclusive
(i.e. 0° ≤ angle ≤ 60°). No shadowing of the ion beam due to fixturing or package related effects is allowed.
7
2
b. The fluence shall be ≥ 100 errors or ≥ 10 ions/cm .
2
5
2
c. The flux shall be between 10 and 10 ions/cm /s. The cross-section shall be verified to be flux independent by
measuring the cross-section at two flux rates which differ by at least an order of magnitude.
d. The particle range shall be ≥ 20 micron in silicon.
e. The test temperature shall be +25°C and the maximum rated operating temperature ±10°C.
f. Bias conditions shall be defined by the manufacturer for the latchup measurements.
g. For SEL test limits, see Table IB herein.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q and V.
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6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor
prepared specification or drawing.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform DLA Land and Maritime when a system application requires
configuration control and which SMD's are applicable to that system. DLA Land and Maritime will maintain a record of users and
this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic
devices (FSC 5962) should contact DLA Land and Maritime-VA, telephone (614) 692-8108.
6.4 Comments. Comments on this drawing should be directed to DLA Land and Maritime-VA, Columbus, Ohio 43218-3990,
or telephone (614) 692-0540.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in
MIL-HDBK-103 and QML-38535. The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein)
to DLA Land and Maritime-VA and have agreed to this drawing.
6.7 Additional information. When specified in the purchase order or contract, a copy of the following additional data shall be
supplied:
a. RHA test conditions (SEP).
b. Occurrence of latchup (SEL).
c. Occurrence of single event burn-out (SEB).
d. Observance of single event transient (SET).
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-15247
A.1 SCOPE
A.1.1 Scope. This appendix establishes minimum requirements for microcircuit die to be supplied under the Qualified
Manufacturers List (QML) Program. QML microcircuit die meeting the requirements of MIL-PRF-38535 and the manufacturers
approved QM plan for use in monolithic microcircuits, multi-chip modules (MCMs), hybrids, electronic modules, or devices using
chip and wire designs in accordance with MIL-PRF-38534 are specified herein. Two product assurance classes consisting of
military high reliability (device class Q) and space application (device class V) are reflected in the Part or Identification Number
(PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.
A.1.2 PIN. The PIN is as shown in the following example:
5962
L
Federal
stock class
designator
\
RHA
designator
(see A.1.2.1)
15247
01
V
9
A
Device
type
(see A.1.2.2)
Device
class
designator
(see A.1.2.3)
Die
code
Die
details
(see A.1.2.4)
/
\/
Drawing number
A.1.2.1 RHA designator. Device classes Q and V RHA identified die meet the MIL-PRF-38535 specified RHA levels. A dash
(-) indicates a non-RHA die.
A.1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
Generic number
Circuit function
01
ISL71830SEH
Radiation hardened dielectrically isolated (DI)
BICMOS single 16-channel analog
MUX with high impedance analog
input overvoltage protection
A.1.2.3 Device class designator.
Device class
Q or V
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-15247
A.1.2.4 Die details. The die details designation is a unique letter which designates the die's physical dimensions, bonding
pad location(s) and related electrical function(s), interface materials, and other assembly related information, for each product
and variant supplied to this appendix.
A.1.2.4.1 Die physical dimensions.
Die type
Figure number
01
A-1
A.1.2.4.2 Die bonding pad locations and electrical functions.
Die type
Figure number
01
A-1
A.1.2.4.3 Interface materials.
Die type
Figure number
01
A-1
A.1.2.4.4 Assembly related information.
Die type
Figure number
01
A-1
A.1.3 Absolute maximum ratings. See paragraph 1.3 herein for details.
A.1.4 Recommended operating conditions. See paragraph 1.4 herein for details.
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-15247
A.2 APPLICABLE DOCUMENTS.
A.2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a
part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in
the solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARD
MIL-STD-883 - Test Method Standard Microcircuits.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Copies of these documents are available online at http://quicksearch.dla.mil or from the Standardization Document Order
Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
A.2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the
text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
A.3 REQUIREMENTS
A.3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer’s Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein.
A.3.2 Design, construction and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and herein and the manufacturer’s QM plan for device classes Q and V.
A.3.2.1 Die physical dimensions. The die physical dimensions shall be as specified in A.1.2.4.1 and on figure A-1.
A.3.2.2 Die bonding pad locations and electrical functions. The die bonding pad locations and electrical functions shall be as
specified in A.1.2.4.2 and on figure A-1.
A.3.2.3 Interface materials. The interface materials for the die shall be as specified in A.1.2.4.3 and on figure A-1.
A.3.2.4 Assembly related information. The assembly related information shall be as specified in A.1.2.4.4 and on figure A-1.
A.3.2.5 Truth table. The truth table shall be as defined in paragraph 3.2.3 herein.
A.3.2.6 Radiation exposure circuit. The radiation exposure circuit shall be as defined in paragraph 3.2.5 herein.
A.3.3 Electrical performance characteristics and post-irradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and post-irradiation parameter limits are as specified in table IA of the body of this
document.
A.3.4 Electrical test requirements. The wafer probe test requirements shall include functional and parametric testing
sufficient to make the packaged die capable of meeting the electrical performance requirements in table IA.
A.3.5 Marking. As a minimum, each unique lot of die, loaded in single or multiple stack of carriers, for shipment to a
customer, shall be identified with the wafer lot number, the certification mark, the manufacturer’s identification and the PIN listed
in A.1.2 herein. The certification mark shall be a “QML” or “Q” as required by MIL-PRF-38535.
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-15247
A.3.6 Certification of compliance. For device classes Q and V, a certificate of compliance shall be required from a
QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see A.6.4 herein). The certificate of
compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply for this appendix shall
affirm that the manufacturer’s product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and the
requirements herein.
A.3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535
shall be provided with each lot of microcircuit die delivered to this drawing.
A.4 VERIFICATION
A.4.1 Sampling and inspection. For device classes Q and V, die sampling and inspection procedures shall be in accordance
with MIL-PRF-38535 or as modified in the device manufacturer’s Quality Management (QM) plan. The modifications in the QM
plan shall not affect the form, fit, or function as described herein.
A.4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and as defined in the
manufacturer’s QM plan. As a minimum, it shall consist of:
a.
Wafer lot acceptance for class V product using the criteria defined in MIL-STD-883, method 5007.
b.
100% wafer probe (see paragraph A.3.4 herein).
c.
100% internal visual inspection to the applicable class Q or V criteria defined in MIL-STD-883, method 2010 or the
alternate procedures allowed in MIL-STD-883, method 5004.
A.4.3 Conformance inspection.
A.4.3.1 Group E inspection. Group E inspection is required only for parts intended to be identified as radiation assured (see
A.3.5 herein). RHA levels for device classes Q and V shall be as specified in MIL-PRF-38535. End point electrical testing of
packaged die shall be as specified in table II herein. Group E tests and conditions are as specified in paragraphs 4.4.4, 4.4.4.1,
4.4.4.2, and 4.4.4.3 herein.
A.5 DIE CARRIER
A.5.1 Die carrier requirements. The requirements for the die carrier shall be accordance with the manufacturer’s QM plan or
as specified in the purchase order by the acquiring activity. The die carrier shall provide adequate physical, mechanical and
electrostatic protection.
A.6 NOTES
A.6.1 Intended use. Microcircuit die conforming to this drawing are intended for use in microcircuits built in accordance with
MIL-PRF-38535 or MIL-PRF-38534 for government microcircuit applications (original equipment), design applications, and
logistics purposes.
A.6.2 Comments. Comments on this appendix should be directed to DLA Land and Maritime -VA, Columbus, Ohio,
43218-3990 or telephone (614)-692-0540.
A.6.3 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
A.6.4 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in MIL-HDBK103 and QML-38535. The vendors listed within MIL-HDBK-103 and QML-38535 have submitted a certificate of compliance (see
A.3.6 herein) to DLA Land and Maritime -VA and have agreed to this drawing.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-15247
A
REVISION LEVEL
SHEET
28
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-15247
NOTE: Pad numbers reflect terminal numbers when placed in case outline X.
FIGURE A-1. Die bonding pad locations and electrical functions.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-15247
A
REVISION LEVEL
SHEET
29
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-15247
Die physical dimensions.
Die size:
2026 μm x 2240 μm (80 mils x 88 mils).
Die thickness:
483 microns ± 25.4 microns.
Interface materials.
Top metallization:
300Å TiN on 2.8μm AlCu, TiN removed from bond pads
Backside metallization:
Silicon
Glassivation.
Type:
Silicon Nitride on Oxide
Thickness:
12kÅ Silicon Nitride on 3kÅ Oxide
Substrate.
Bonded wafer dielectrically isolated.
Assembly related information.
Substrate potential:
Floating
Special assembly instructions:
None
FIGURE A-1. Die bonding pad locations and electrical functions - continued.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-15247
A
REVISION LEVEL
SHEET
30
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 16-03-14
Approved sources of supply for SMD 5962-15247 are listed below for immediate acquisition information only and
shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be
revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a
certificate of compliance has been submitted to and accepted by DLA Land and Maritime-VA. This information
bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DLA Land and Maritime
maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962L1524701VXC
34371
ISL71830SEHVF
5962L1524701V9A
34371
ISL71830SEHVX
1/ The lead finish shown for each PIN representing
a hermetic package is the most readily available
from the manufacturer listed for that part. If the
desired lead finish is not listed contact the vendor
to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number may not
satisfy the performance requirements of this drawing.
Vendor CAGE
number
34371
Vendor name
and address
Intersil Corporation
1650 Robert J. Conlan Blvd. NE
Palm Bay, FL 32905-3406
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.