92312

REVISIONS
LTR
DESCRIPTION
DATE (YR-MO-DA)
APPROVED
A
Boilerplate update and part of five year review. tcr
06-07-05
Raymond Monnin
B
Update drawing to meet current MIL-PRF-38535 requirements. - glg
15-02-19
Charles Saffle
REV
SHEET
REV
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
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B
SHEET
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
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34
REV STATUS
REV
B
B
B
B
B
B
B
B
B
B
B
B
B
B
OF SHEETS
SHEET
1
2
3
4
5
6
7
8
9
10
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PMIC N/A
PREPARED BY
Jeff Bowling
STANDARD MICROCIRCUIT
DRAWING
THIS DRAWING IS
AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil
CHECKED BY
Jeff Bowling
APPROVED BY
Michael A. Frye
MICROCIRCUIT, MEMORY, DIGITAL, CMOS
4MEG X 4 DRAM, MONOLITHIC SILICON
DRAWING APPROVAL DATE
94-10-18
REVISION LEVEL
B
SIZE
A
SHEET
DSCC FORM 2233
APR 97
CAGE CODE
67268
1 OF
5962-92312
34
5962-E161-15
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and
M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part
or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
-
92312
Federal
stock class
designator
\
RHA
designator
(see 1.2.1)
01
M
X
A
Device
type
(see 1.2.2)
Device
class
designator
(see 1.2.3)
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
/
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
01
02
03
Generic number 1/
416400-10
416400-80
416400-70
Circuit function
Access time
4 M x 4 DYNAMIC RAM, 32 ms refresh
4 M x 4 DYNAMIC RAM, 32 ms refresh
4 M x 4 DYNAMIC RAM, 32 ms refresh
100 ns
80 ns
70 ns
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class
Device requirements documentation
M
Vendor self-certification to the requirements for MIL-STD-883 compliant, nonJAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A
Q or V
Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
X
Y
Z
Descriptive designator
See figure 1
See figure 1
See figure 1
Terminals
Package style
28
28
24
flat pack
leadless chip carrier
zig-zag in-line
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
_______
1/ Generic numbers are also listed on the Standard Microcircuit Drawing Source Approval Bulletin at the end of this document
and will also be listed in MIL-HDBK-103 and QML-38535 (see 6.6.2 herein).
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-92312
A
REVISION LEVEL
B
SHEET
2
1.3 Absolute maximum ratings. 2/
Voltage range on any pin ........................................................... -1 V dc to 7 V dc
Voltage range on VCC ................................................................. -1 V dc to 7 V dc
Short circuit output current ......................................................... 50 mA
Maximum power dissipation (PD) ............................................... 1 W
Storage temperature range ...................................................... -65°C to +150°C
Lead temperature (soldering, 10 seconds) ................................ +300°C
Thermal resistance, junction-to-case (θJC)
Case outlines X, Y, Z .......................................................... 15°C/W 3/
Junction temperature (TJ) 4/...................................................... +175°C
1.4 Recommended operating conditions.
Supply voltage range (VCC) 5/ ................................................... +4.5 V dc to +5.5 V dc
High-level input voltage (VIH)...................................................... 2.4 V dc minimum to 6.5 V dc maximum
Low-level input voltage (VIL) 6/ .................................................. -1.0 V dc minimum to 0.8 V dc maximum
Case operating temperature range (TC) ................................... -55°C to +125°C
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 MIL-STD-1835 -
Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 MIL-HDBK-780 -
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Copies of these documents are available online at http://quicksearch.dla.mil or from the Standardization Document Order
Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
_______
2/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
3/ When the thermal resistance for this case is specified in MIL-STD-1835 that value shall supersede the value indicated
herein.
4/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in
accordance with method 5004 of MIL-STD-883.
5/ All voltage values in this drawing are with respect to VSS.
6/ The algebraic convention, where the more negative (less positive) limit is designated as a minimum, is used in this drawing
for logic voltage levels only.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-92312
A
REVISION LEVEL
B
SHEET
3
2.2 Non-Government publications. The following documents form a part of this document to the extent specified herein.
Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation.
JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC)
JESD 78
-
IC Latch-Up Test.
(Copies of this document are available on line at http://www.jedec.org or from JEDEC - Solid State Technology
th
Association, 3103 North 10 Street, Suite 247, Arlington, VA 22201).
AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM)
ASTM Standard F1192
-
Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by
Heavy Ion Irradiation of Semiconductor Devices.
(Applications for copies of ASTM publications should be addressed to: ASTM International, PO Box C700, 100 Barr Harbor
Drive, West Conshohocken, PA 19428-2959; http://www.astm.org.)
(Non-Government standards and other publications are normally available from the organizations that prepare or distribute
the documents. These documents also may be available in or through libraries or other informational services.)
2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.
3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein and figure 1.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.
3.2.3 Truth table. The truth table shall be as specified on figure 3.
3.2.4 Timing waveforms. The timing waveforms are as specified on figure 4.
3.2.5 Test load circuit. The test load circuit is as specified on figure 5.
3.2.6 Radiation exposure circuit. The radiation exposure circuit will be provided when RHA product becomes available.
3.2.5 Functional tests. Various functional tests used to test this device are contained in the appendix. If the test patterns
cannot be implemented due to test equipment limitations, alternate test patterns to accomplish the same results shall be
allowed. For device class M, alternate test patterns shall be maintained under document revision level control by the
manufacturer and shall be made available to the preparing or acquiring activity upon request. For device classes Q and V,
alternate test patterns shall be under the control of the device manufacturer's Technology Review Board (TRB) in accordance
with MIL-PRF-38535 and shall be made available to the preparing or acquiring activity upon request
3.2.6 Die overcoat. Polyimide and silicone coatings are allowable as an overcoat on the die for alpha particle protection only.
Each coated microcircuit inspection lot (see inspection lot as defined in MIL-PRF-38535) shall be subjected to and pass the
internal moisture content test at 5000 ppm (method 1018 of MIL-STD-883). The frequency of the internal water vapor testing
shall not be decreased unless approved by the preparing activity for class M. The TRB will ascertain the requirements as
provided by MIL-PRF-38535 for classes Q and V. Samples may be pulled any time after seal.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
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A
REVISION LEVEL
B
SHEET
4
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full
case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical
tests for each subgroup are defined in table I.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be
in accordance with MIL-PRF-38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see
6.6.2 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of
supply for this drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MILPRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for
device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.
3.8 Notification of change for device class M. For device class M, notification to DLA Land and Maritime-VA of change of
product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing.
3.9 Verification and review for device class M. For device class M, DLA Land and Maritime, DLA Land and Maritime's agent,
and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore
documentation shall be made available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 41 (see MIL-PRF-38535, appendix A).
4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in
accordance with MIL-PRF-38535, appendix A.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
a. Delete the sequence specified as initial (preburn-in) electrical parameters through interim (postburn-in)
electrical parameters of method 5004 and substitute lines 1 through 6 of table IIA herein.
b. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made
available to the preparing or acquiring activity upon request. For device class M, the test circuit shall specify the inputs,
outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015.
(1) Dynamic burn-in for device class M (method 1015 of MIL-STD-883, test condition D; for circuit, see 4.2.1b herein).
c. Interim and final electrical parameters shall be as specified in table IIA herein.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
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A
REVISION LEVEL
B
SHEET
5
TABLE I. Electrical performance characteristics.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +125°C
4.5 V ≤ VCC ≤ 5.5 V
unless otherwise specified
IOH = -5 mA, VIL = 0.8 V
VIH = 2.4 V
Group A
subgroups
Device
type
1, 2, 3
All
Limits
Min
2.4
Unit
Max
High-level output
voltage
VOH
V
Low-level output
voltage
VOL
IOL = 4.2 mA, VIL = 0.8 V
VIH = 2.4 V
1, 2, 3
All
0.4
V
Input leakage current
II
VI = 0 V to 6.5 V,
VCC = 5.5 V,
All other pins = 0 V to VCC
1, 2, 3
All
±10
µA
Output leakage current
IO
VCC = 5.5 V, CAS = 2.4 V,
VO = VCC to 0 V
1, 2, 3
All
±10
µA
Average operating power
supply current (Random
read or write cycle)
ICC1
Minimum cycle time,
VCC = 5.5 V,
Measured with a maximum
of one address change
1, 2, 3
01
60
mA
02
70
03
80
while RAS = 0.8 V
Standby power supply
current
ICC2
TTL
VIH = 2.4 V
CMOS
VIH = VCC
- 0.05 V
1, 2, 3
All
2
1, 2, 3
All
1
VCC = 5.5 V, Minimum cycle,
1, 2, 3
01
60
02
70
03
80
01
55
02
60
03
65
All
5
VCC = 5.5 V
After one
memory cycle
RAS and
CAS = 2.4 V
Average operating power
ICC3
supply current ( RAS only refresh, or CBR
refresh)
mA
RAS cycling, CAS = 2.4 V
( RAS only refresh)
RAS low after CAS low
(CBR refresh)
Average operating power
supply current (Page
mode)
mA
ICC4
1, 2, 3
RAS = 0.8 V, CAS cycling,
tPC = minimum, VCC = 5.5 V
Measured with a maximum
of one address change
mA
while CAS = 2.4 V
Standby power
supply current
(output enable)
ICC5
1, 2, 3
RAS = 2.4 V, CAS = 0.8 V,
VCC = 5.5 V, Minimum cycle
time, Data out is enabled,
following a normal read cycle
mA
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
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DSCC FORM 2234
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REVISION LEVEL
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SHEET
6
TABLE I. Electrical performance characteristics – continued.
Test
Symbol
Input capacitance
address inputs
CI(A)
Input capacitance
CI(S)
RAS , CAS , W , OE
I/O capacitance,
DQ's
Access time from
Group A
subgroups
Device
type
4
All
tAA
Max
12
pF
4
All
12
pF
4
All
14
pf
See 4.4.1.c
7, 8A, 8B
All
See figures 4 and 5
1/ 2/
9, 10, 11
01
45
ns
02
40
03
35
01
02
25
20
03
18
01
50
02
45
03
40
01
100
02
80
03
70
01
25
02
20
03
01
02
03
18
25
20
18
01
02
03
25
20
18
tCAC
9, 10, 11
CAS low
Access time from
column precharge
Access time from
tCPA
9, 10, 11
tRAC
9, 10, 11
RAS low
Access time from OE low
Output disable time
after CAS high
3/
Output disable time
after OE high
3/
Limits
Min
CDQ
Functional tests
Access time from
column address
Conditions
-55°C ≤ TC ≤ +125°C
4.5 V ≤ VCC ≤ 5.5 V
unless otherwise specified
f = 1 MHz, See 4.4.1e,
Bias on pins under test =0 V,
all other pins are open
TA = 25°C
tOEA
or
tOE
9, 10, 11
tOFF
9, 10, 11
tOEZ
or
tOD
9, 10, 11
Unit
ns
ns
ns
ns
ns
ns
See footnotes at end of table.
STANDARD
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REVISION LEVEL
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SHEET
7
TABLE I. Electrical performance characteristics – continued.
Test
Cycle time, random
read or write
Cycle time, read-write
Cycle time, pagemode read or write
4/
Cycle time, pagemode read-write
Pulse duration,
Symbol
tRC
Conditions
-55°C ≤ TC ≤ +125°C
4.5 V ≤ VCC ≤ 5.5 V
unless otherwise specified
See figures 4 and 5
1/ 2/
tRWC
Group A
subgroups
Device
type
9, 10, 11
01
Min
180
02
150
03
130
01
02
245
205
03
181
01
55
02
50
03
45
01
120
02
105
03
96
01
100
02
80
03
All
70
01
02
03
All
100
80
70
9, 10, 11
tPC
9, 10, 11
tPRWC
9, 10, 11
tRASP
9, 10, 11
page-mode, RAS
low
5/
Pulse duration,
non-page-mode,
RAS low
5/
Pulse duration,
tRAS
9, 10, 11
tCAS
9, 10, 11
01
02
03
All
25
20
18
tCP
tCPN
9, 10, 11
All
10
CAS low
6/
Pulse duration,
CAS high
Limits
Unit
Max
ns
ns
ns
ns
ns
100
µs
ns
10
µs
ns
µs
ns
10
See footnotes at end of table.
STANDARD
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TABLE I. Electrical performance characteristics – continued.
Test
Pulse duration, RAS high
(precharge)
Pulse duration, write
Setup time, column-
Symbol
tRP
Conditions
-55°C ≤ TC ≤ +125°C
4.5 V ≤ VCC ≤ 5.5 V
unless otherwise specified
See figures 4 and 5
1/ 2/
Group A
subgroups
Device
type
Limits
9, 10, 11
01
Min
70
02
60
03
50
Unit
Max
ns
tWP
tASC
9, 10, 11
9, 10, 11
All
All
10
0
ns
ns
tASR
9, 10, 11
All
0
ns
Setup time, data 7/
tDS
9, 10, 11
All
0
ns
Setup time, read before
tRCS
9, 10, 11
All
0
ns
tCWL
9, 10, 11
9, 10, 11
25
20
18
25
20
18
ns
tRWL
01
02
03
01
02
03
tWCS
9, 10, 11
All
0
ns
tWSR
tWRP
9, 10, 11
All
10
ns
tCAH
9, 10, 11
All
15
ns
tDH
tRAH
9, 10, 11
9, 10, 11
All
All
15
10
ns
ns
tRCH
9, 10, 11
All
0
ns
address before CAS low
Setup time, row-address
before RAS low
CAS low
Setup time, W low before
CAS high
Setup time,
W low before
RAS high
Setup time, W low before
ns
CAS low (Early write
operation only)
Setup time, W high ( CAS
before RAS refresh
only)
Hold time, column-address
after CAS low
Hold time, data 7/
Hold time, row-address
after RAS low
Hold time, read after
CAS high
8/
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
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REVISION LEVEL
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TABLE I. Electrical performance characteristics – continued.
Test
Hold time, read after
RAS high
Symbol
tRRH
8/
Hold time, write after
Conditions
-55°C ≤ TC ≤ +125°C
4.5 V ≤ VCC ≤ 5.5 V
unless otherwise specified
See figures 4 and 5
1/ 2/
Group A
subgroups
Device
type
Limits
9, 10, 11
01
Min
5
02, 03
0
Unit
Max
ns
tWCH
9, 10, 11
All
15
ns
tWHR
tWRH
9, 10, 11
All
10
ns
tAWD
9, 10, 11
01
80
ns
02
70
03
63
01
20
02, 03
10
CAS low (Early write
operation only)
Hold time, W high ( CAS before- RAS refresh only)
Delay time, column
address to W low
(Read-write operation only)
Delay time, RAS low to
tCHR
9, 10, 11
CAS high ( CAS -before-
ns
RAS refresh only)
Delay time, CAS high to
tCRP
9, 10, 11
All
5
ns
tCSH
9, 10, 11
9, 10, 11
100
80
70
10
5
ns
tCSR
01
02
03
01
02, 03
tCWD
9, 10, 11
01
02
03
60
50
46
ns
tOEH
9, 10, 11
9, 10, 11
tROH
9, 10, 11
25
20
18
25
20
18
10
ns
tOED
01
02
03
01
02
03
All
RAS low
Delay time, RAS low to
CAS high
Delay time, CAS low to
RAS low ( CAS -before- RAS
refresh only)
Delay time, CAS low to W
low (Read-write operation
only)
Hold time,
OE command
Delay time,
OE to data
Hold time, RAS
ns
ns
ns
referenced to OE
See footnotes at end of table.
STANDARD
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TABLE I. Electrical performance characteristics – continued.
Test
Delay time, RAS low to
column-address 9/
Delay time, column-address
Symbol
tRAD
Conditions
-55°C ≤ TC ≤ +125°C
4.5 V ≤ VCC ≤ 5.5 V
unless otherwise specified
See figures 4 and 5
1/ 2/
tRAL
Group A
subgroups
Device
type
9, 10, 11
01
Min
15
Max
55
02
15
40
03
15
35
01
02
45
40
03
35
01
45
02
40
03
35
01
20
75
02
20
60
03
20
52
9, 10, 11
to RAS high
Delay time, column-address
tCAL
9, 10, 11
to CAS high
Delay time, RAS low to
CAS low
tRCD
9, 10, 11
9/
Limits
Unit
ns
ns
ns
ns
tRPC
9, 10, 11
All
0
ns
tRSH
9, 10, 11
01
25
ns
CAS low to RAS high
02
20
Delay time RAS low to W
low (Read-write operation
only)
03
01
02
03
18
135
110
98
Delay time, RAS
high to CAS low
Delay time,
tRWD
9, 10, 11
ns
01
50
ns
02
45
03
40
9,
10,
11
01
80
ns
t
CPW
Delay time, W from CAS
02
70
precharge
03
63
Refresh time interval
tREF
9, 10, 11
All
32
ms
1/ An initial pause of 200 μs is required after power-up followed by a minimum of 8 initialization cycles after full VCC level is
Hold time, RAS from CAS
precharge
9, 10, 11
tCPRH
achieved. The 8 initialization cycles need to be RAS only refresh or CBR with W high to assure proper device operation.
The 8 initialization cycles should be repeated any time the refresh requirement is exceeded.
2/ All cycle times assume transition time tT = 5 ns, referenced to VIH (min) and VIL (max).
3/ tOFF and tOEZ are specified when the output is no longer driven. The outputs are disabled (high impedance) by bringing
either OE or CAS high.
4/ To guarantee tPC min, tASC should be greater than or equal to tCP.
5/ In a read-write cycle, tRWD and tRWL must be observed.
6/ In a read-write cycle, tCWD and tCWL must be observed.
7/ Referenced to the later of CAS or W in write operations.
8/ Either tRRH or tRCH must be satisfied for a read cycle.
9/ Maximum value specified only to guarantee access time.
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Case X (see note)
Symbol
A
b
C
D
e
E
E2
E3
L
Q
S1
Millimeters
Min
Max
2.29
3.32
.38
.53
.10
.23
19.43 19.94
1.27 BSC
11.18 11.68
5.08
----0.76
----6.35
9.4
.66
----1.14
1.65
Inches
Min
Max
.090
.130
.015
.021
.004
.009
.765
.785
.050 BSC
.440
.460
.200
----.030
----.250
.370
.026
----.045
.065
Note: The U.S. Government preferred system of measurement is the metric SI system. However, since this item was
originally designed using inch-pound units of measurement, in the event of conflict between the metric and
inch-pound units, the inch-pound units shall take precedence.
FIGURE 1. Case outlines.
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Case Y (see note)
Symbol
A
A1
B1
B3
D
e
E
J
L1
L2
Millimeters
Min
Max
2.67
3.18
0.89
1.4
0.56
0.71
0.20R TYP
19.43 19.95
1.27 BSC
11.18 11.68
0.25 REF
1.78
2.03
2.67
3.18
Inches
Min
Max
.105
.125
.035
.055
.022
.028
.008R TYP
.765
.785
.050 BSC
.440
.460
.010 REF
.070
.080
.105
.125
Note: The U.S. Government preferred system of measurement is the metric SI system. However, since this item was
originally designed using inch-pound units of measurement, in the event of conflict between the metric and
inch-pound units, the inch-pound units shall take precedence.
FIGURE 1. Case outlines - Continued.
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Case Z (see note)
Symbol
A1
A2
b
c
D
D1
e
eA
E
L
S
Millimeters
Min
Max
0.38
1.27
11.18
11.81
0.41
0.58
0.20
0.39
31.37
32.13
27.69
28.19
2.54 BSC
2.16
2.92
2.54
3.30
3.18
5.08
0.88
1.65
Inches
Min
Max
.015
.050
.440
.465
.016
.023
.008
.015
1.235
1.265
1.090
1.110
.100 BSC
.085
.115
.100
.130
.125
.200
.035
.065
Note: The U.S. Government preferred system of measurement is the metric SI system. However, since this item was
originally designed using inch-pound units of measurement, in the event of conflict between the metric and
inch-pound units, the inch-pound units shall take precedence.
FIGURE 1. Case outlines - Continued.
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Device types
Case outlines
Terminal number
1
All
X, Y
Z
Terminal symbol
VCC
A9
2
DQ1
OE
3
DQ2
CAS
4
W
DQ3
5
DQ4
6
7
8
9
RAS
A11
NC
NC
A10
VSS
VCC
DQ1
DQ2
10
A0
W
11
A1
12
13
14
15
16
17
18
19
20
21
22
23
A2
A3
VCC
VSS
A4
A5
A6
A7
A8
NC
NC
A9
RAS
A11
A10
A0
A1
A2
A3
VCC
VSS
A4
A5
A6
A7
24
OE
A8
25
CAS
DQ3
DQ4
VSS
----
26
27
28
----------
NC = NO CONNECT
FIGURE 2. Terminal connections.
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Inputs
Operation
Input/Output
RAS
CAS
W
OE
Row
address
Column
address
D
Q
Read
ACT
ACT
NAC
ACT
APD
APD
NAC
VLD
Write (early write)
ACT
ACT
ACT
DNC
APD
APD
APD
ILD
Write (late write)
ACT
ACT
ACT
NAC
APD
APD
APD
ILD
Read-modify-write
ACT
ACT
ACT
ACT
APD
APD
APD
VLD
RAS - only refresh
ACT
NAC
DNC
DNC
APD
DNC
DNC
OPN
Hidden refresh (read)
ACT
ACT
NAC
ACT
APD
APD
NAC
VLD
Hidden refresh (write)
ACT
ACT
ACT
DNC
APD
APD
APD
DNC
CAS before RAS refresh
ACT
ACT
NAC
DNC
DNC
DNC
DNC
OPN
Standby
NAC
NAC
DNC
DNC
DNC
DNC
DNC
OPN
ACT = active
NAC = nonactive
DNC = don’t care
VLD = valid
ILD = invalid
APD = applied
OPN = open
FIGURE 3. Truth table.
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Read cycle (see note)
Note: Output may go from three-state to an invalid state prior to the specified access time.
FIGURE 4. Timing waveform diagrams.
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Early write cycle
FIGURE 4. Timing waveform diagrams - Continued.
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Write cycle
FIGURE 4. Timing waveform diagrams - Continued.
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Read-write cycle (see note)
Note: Output may go from three-state to an invalid data state prior to the specified access time.
FIGURE 4. Timing waveform diagrams - Continued.
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Enhanced page-mode read cycle (see notes 1 and 2)
Notes: 1. Output may go from three-state to an invalid state prior to the specified access time.
2. Access time is tCPA or tAA dependent.
FIGURE 4. Timing waveform diagrams - Continued.
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Enhanced page-mode write cycle (see notes 1 and 2)
Notes: 1. tDS and tDH are referenced to CAS or W , whichever occurs last.
2. A read cycle or a read-write cycle can be intermixed with a write cycle
as long as read and read-write timing specifications are not violated.
FIGURE 4. Timing waveform diagrams - Continued.
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Enhanced page-mode read-write cycle (see note 1)
Notes:
1. A read or write cycle can be intermixed with read-write cycles as long as the read
and write timing specifications are not violated.
2. Output may go from three-state to an invalid data state prior to the specified time.
FIGURE 4. Timing waveform diagrams - Continued.
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RAS -only refresh cycle
FIGURE 4. Timing waveform diagrams - Continued.
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Automatic ( CAS -before- RAS ) refresh cycle
FIGURE 4. Timing waveform diagrams - Continued.
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Hidden refresh cycle (read)
FIGURE 4. Timing waveform diagrams - Continued.
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AC test conditions
Input pulse levels
GND to 3.0 V
Input rise and fall times
5 ns
Input timing reference levels
VIL, VIH
Output reference levels
VOL, VOH
FIGURE 5. Load circuits.
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TABLE IIA. Electrical test requirements. 1/ 2/ 3/ 4/ 5/ 6/ 7/
Line
no.
Test
requirements
1
Interim electrical
parameters (see 4.2)
2
Static burn-in I and
II (method 1015)
3
Same as line 1
4
Dynamic burn-in
(method 1015)
5
Same as line 1
6
Subgroups
(in accordance with
MIL-STD-883,
method 5005, table I)
Device
class M
Subgroups
(per MIL-PRF-38535,
table III)
Device
class Q
1, 7, 9
Device
class V
1, 7, 9
Not Required
Not Required
Required
Required
Required
1*, 7* ∆
Required
Final electrical
parameters
1*, 2, 3, 7*,
8A, 8B, 9, 10, 11
1*, 2, 3, 7*,
8A, 8B, 9, 10, 11
1*, 7* ∆
1*, 2, 3, 7*,
8A, 8B, 9, 10, 11
7
Group A test
requirements
1, 2, 3, 4**, 7,
8A, 8B, 9, 10, 11
1, 2, 3, 4**, 7,
8A, 8B, 9, 10, 11
1, 2, 3, 4**, 7,
8A, 8B, 9, 10, 11
8
Group C end-point
electrical parameters
2, 3, 7, 8A, 8B
1, 2, 3, 7, 8A,
8B ∆
1, 2, 3, 7,
8A, 8B, 9,
9
Group D end-point
electrical parameters
2, 3, 8A, 8B
2, 3, 8A, 8B
10, 11 ∆
2, 3, 8A, 8B
10
Group E end-point
electrical parameters
1, 7, 9
1, 7, 9
1, 7, 9
1/
2/
3/
4/
5/
6/
Blank spaces indicate tests are not applicable.
Any or all subgroups may be combined when using high-speed testers.
Subgroups 7 and 8 functional tests shall verify the truth table.
* indicates PDA applies to subgroup 1 and 7.
** see 4.4.1e.
∆ indicates delta limit (see table IIB) shall be required where specified, and the delta values shall be
computed with reference to the previous interim electrical parameters (see line 1). For device classes Q
and V, performance of delta limits shall be as specified in the manufacturer’s QM plan.
7/ See 4.4.1d.
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TABLE IIB. Delta limits at +25°C.
Parameter1/
ICC2 standby
IIH, IIL
IOHZ, IOLZ
All device types
±10% of before
value
±10% of before
value
±10% of before
value
1/ The above parameters shall be recorded
before and after the required burn-in and
life tests to determine the delta.
4.2.2 Additional criteria for device classes Q and V.
a.
The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
b.
Interim and final electrical test parameters shall be as specified in table IIA herein.
c.
Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein except where option 2 of MIL-PRF38535 permits alternate in-line control testing. Quality conformance inspection for device class M shall be in accordance with
MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed for device class M shall be those specified in
method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4.1 Group A inspection.
a.
Tests shall be as specified in table IIA herein.
b.
Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted.
c. For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table. For device classes Q and V,
subgroups 7 and 8 shall include verifying the functionality of the device.
d. O/V (latch-up) tests shall be measured only for initial qualification and after any design or process changes which may
affect the performance of the device. For device class M, procedures and circuits shall be maintained under document
revision level control by the manufacturer and shall be made available to the preparing activity or acquiring activity upon
request. For device classes Q and V, the procedures and circuits shall be under the control of the device
manufacturer's TRB in accordance with MIL-PRF-38535 and shall be made available to the preparing activity or
acquiring activity upon request. Testing shall be on all pins, on five devices with zero failures. Latch-up test shall be
considered destructive. Information contained in JESD 78 may be used for reference.
e.
Subgroup 4 (CIN and COUT measurements) shall be measured only for initial qualification and after any process or
design changes which may affect input or output capacitance. Capacitance shall be measured between the designated
terminal and GND at a frequency of 1 MHz. Sample size is 15 devices with no failures, and all input and output
terminals tested.
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4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
Delta limits shall apply to group C inspection and shall consist of tests specified in table IIB herein.
4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
a.
Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control and
shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs,
outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MILSTD-883.
b.
TA = +125°C, minimum.
c.
Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MILSTD-883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured
(see 3.5 herein).
a.
End-point electrical parameters shall be as specified in table IIA herein.
b.
For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to
radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device
classes must meet the postirradiation end-point electrical parameter limits as defined in table I at TA = +25°C ±5°C,
after exposure, to the subgroups specified in table IIA herein.
4.5 Delta measurements for device class Q and V. Delta measurements, as specified in table IIA, shall be made and
recorded before and after the required burn-in screens and steady-state life tests to determine delta compliance. The electrical
parameters to be measured, with associated delta limits are listed in table IIB. The device manufacturer may, at his option,
either perform delta measurements or within 24 hours after burn-in perform final electrical parameter tests, subgroups 1, 7, and
9.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q and V or MIL-PRF-38535, appendix A for device class M.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor
prepared specification or drawing.
6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
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6.3 Record of users. Military and industrial users should inform DLA Land and Maritime when a system application requires
configuration control and which SMD's are applicable to that system. DLA Land and Maritime will maintain a record of users and
this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic
devices (FSC 5962) should contact DLA Land and Maritime-VA, telephone (614) 692-8108.
6.4 Comments. Comments on this drawing should be directed to DLA Land and Maritime-VA, Columbus, Ohio 43218-3990,
or telephone (614) 692-0540.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
CIN COUT ................................. Input and bidirectional output, terminal-to-GND capacitance.
GND ....................................... Ground zero voltage potential.
ICC .......................................... Supply current.
IIL ............................................ Input current low.
IIH ........................................... Input current high.
TC ........................................... Case temperature.
TA ........................................... Ambient temperature.
VCC ......................................... Positive supply voltage.
VIC ................................................................ Positive input clamp voltage
O/V ......................................... Latch-up over-voltage
O/I .......................................... Latch-up over-current
6.5.1 Timing limits. The table of timing values shows either a minimum or a maximum limit for each parameter. Input
requirements are specified from the external system point of view. For example, address setup time would be shown as a
minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand,
responses from the memory are specified from the device point of view. For example, the access time would be shown as a
maximum since the device never provides data later than that time.
6.5.2 Waveforms.
WAVEFORM
SYMBOL
INPUT
OUTPUT
MUST BE VALID
WILL BE VALID
CHANGE FROM
H TO L
WILL CHANGE FROM
H TO L
CHANGE FROM
L TO H
WILL CHANGE FROM
L TO H
DON'T CARE ANY
CHANGE
PERMITTED
CHANGING STATE
UNKNOWN
HIGH IMPEDANCE
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DLA Land and Maritime-VA and
have agreed to this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been
submitted to and accepted by DLA Land and Maritime-VA.
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APPENDIX A
Appendix A forms a part of SMD 5962-92312
FUNCTIONAL ALGORITHMS
A.1 SCOPE
A.1.1 Scope. Functional algorithms are test patterns which define the exact sequence of events used to verify proper
operation of a random access memory (RAM). Each algorithm serves a specific purpose for the testing of the device. It is
understood that all manufacturers do not have the same test equipment; therefore, it becomes the responsibility of each
manufacturer to guarantee that the test patterns described herein are followed as closely as possible, or equivalent patterns be
used that serve the same purpose. Each manufacturer should demonstrate that this condition will be met. Algorithms shall be
applied to the device in a topologically pure fashion. This appendix is a mandatory part of the specification. The information
contained herein is intended for compliance.
A.2 APPLICABLE DOCUMENTS. This section is not applicable to this appendix.
A.3 ALGORITHMS
A.3.1 Algorithm A (pattern 1).
A.3.1.1 Output high impedance (tOFF). This pattern verifies the output buffer switches to high impedance
(three-state) within the specified tOFF after the rise of CAS. It is performed in the following manner:
Step 1:
Step 2:
Step 3:
Perform 8 pump cycles.
Load address location with data.
Raise CAS and read address location and guarantee VOL < VOUT < VOH after tOFF delay.
A.3.2 Algorithm B (pattern 2).
A.3.2.1 VCC slew. This pattern indicates sense amplifier margin by slewing the supply voltage between memory
writing and reading. It is performed in the following manner:
Step 1:
Step 2:
Step 3:
Step 4:
Step 5:
Step 6:
Step 7:
Perform 8 pump cycles.
Load memory with background data with VCC at 5.0 V.
Change VCC to 5.5 V.
Read memory with background data.
Load memory with background data complement.
Change VCC to 4.5 V.
Read memory with background data complement.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-92312
A
REVISION LEVEL
B
SHEET
32
APPENDIX A – continued.
Appendix A forms a part of SMD 5962-92312
A.3.3 Algorithm C (pattern 3).
A.3.3.1 March data. This pattern tests for address uniqueness and multiple selection. It is performed in the following
manner:
Step 1: Perform 8 pump cycles.
Step 2: Load memory with background data.
Step 3: Read location 0.
Step 4: Write data complement in location 0.
Step 5: Repeat steps 3 and 4 for all other locations in the memory (sequentially).
Step 6: Read data complement in maximum address location.
Step 7: Write data in maximum address location.
Step 8: Repeat steps 6 and 7 for all other locations in the memory from maximum to minimum address.
Step 9: Read data in maximum address location.
Step 10: Write data complement in maximum address location.
Step 11: Repeat steps 6 and 7 for all other locations in the memory from maximum to minimum address.
Step 12: Read memory with data complement.
A.3.4 Algorithm D (pattern 4).
A.3.4.1 Refresh test (cell retention) +125°C only. This test is used to check the retention time of the memory cells. It is
performed in the following manner:
Step 1:
Step 2:
Step 3:
Step 4:
Step 5:
Perform 8 pump cycles.
Load memory with background data.
Pause tREF (stop all clocks).
Read memory with background data.
Repeat steps 2 through 4 with data complement.
A.3.5 Algorithm E (pattern 5).
A.3.5.1 Read-modify-write (RMW). This pattern verifies the Read-modify-write mode for the memory. It is performed in the
following manner:
Step 1:
Step 2:
Step 3:
Step 4:
Step 5:
Perform 8 pump cycles.
Load memory with background data.
Read memory with data and load with data complement using RMW cycle.
Repeat step 3 for all address locations.
Repeat steps 2 and 3 using data complement.
A.3.6 Algorithm F (pattern 6).
A.3.6.1 Page mode. This pattern verifies the Page mode for the memory. It is performed in the following manner:
Step 1:
Step 2:
Step 3:
Step 4:
Step 5:
Perform 8 pump cycles.
Load first page of memory with background data using Page mode cycle.
Read first page of memory with data and load with data complement using Page mode cycle.
Read first page of memory with data complement and load with data using Page mode cycle.
Repeat steps 2 through 4 for remaining memory locations.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-92312
A
REVISION LEVEL
B
SHEET
33
APPENDIX A – continued.
Appendix A forms a part of SMD 5962-92312
A.3.7 Algorithm G (pattern 7).
A.3.7.1 CAS-before-RAS refresh test. This test is used to verify the functionality of the CAS-before-RAS mode of cell
refreshing. It is done at +125°C only and is performed in the following manner:
Step 1:
Step 2:
Step 3:
Step 4:
Perform 8 pump cycles.
Load memory with background data.
Perform 1024 CAS-before-RAS cycles while attempting to modify data.
Read memory with background data.
A.3.8 Algorithm H (pattern 8).
A.3.8.1 RAS-only refresh test. This test is used to verify the functionality of the RAS-only mode of cell refreshing. It is done
at +125°C only and is performed in the following manner:
Step 1:
Step 2:
Step 3:
Step 4:
Step 5:
Perform 8 pump cycles.
Load memory with background data.
Perform 1024 RAS-only cycles while attempting to modify data.
Repeat step 3 for 1 second.
Read memory with background data.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-92312
A
REVISION LEVEL
B
SHEET
34
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 15-02-19
Approved sources of supply for SMD 5962-92312 are listed below for immediate acquisition information only and
shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be
revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a
certificate of compliance has been submitted to and accepted by DLA Land and Maritime-VA. This information
bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DLA Land and Maritime
maintains an online database of all current sources of supply at http://www.landandmaritme.dla.mil/Programs/Smcr/.
Standard microcircuit
drawing PIN 1/
Vendor
CAGE number
Vendor
Similar PIN 2/
5962-9231201MXA
57300
SMJ416400-10HKBM
3/
SMJ416400-10HKB
57300
SMJ416400-10FNCM
3/
SMJ416400-10FNC
57300
SMJ416400-10SVM
3/
SMJ416400-10SV
57300
SMJ416400-80HKBM
3/
SMJ416400-80HKB
57300
SMJ416400-80FNCM
3/
SMJ416400-80FNC
57300
SMJ416400-80SVM
3/
SMJ416400-80SV
57300
SMJ416400-70HKBM
3/
SMJ416400-70HKB
57300
SMJ416400-70FNCM
3/
SMJ416400-70FNC
57300
SMJ416400-70SVM
3/
SMJ416400-70SV
5962-9231201MYA
5962-9231201MZA
5962-9231202MXA
5962-9231202MYA
5962-9231202MZA
5962-9231203MXA
5962-9231203MYA
5962-9231203MZA
1/ The lead finish shown for each PIN representing a hermetic package
is the most readily available from the manufacturer listed for that part.
If the desired lead finish is not listed contact the vendor to determine
its availability.
2/ Caution. Do not use this number for item acquisition. Items acquired to
this number may not satisfy the performance requirements of this drawing.
3/ Not available from an approved source of supply.
Vendor CAGE
number
57300
Vendor name
and address
Micross Components
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.