LTM4630A - Dual 18A or Single 36A DC/DC μModule Regulator

LTM4630A
Dual 18A or Single 36A
DC/DC µModule Regulator
Description
Features
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Dual 18A or Single 36A Output
Input Voltage Range: 4.5V to 15V
Output Voltage Range: 0.6V to 5.3V
±1.5% Maximum Total DC Output Error Over Line,
Load and Temperature
Higher Light Load Efficiency and Wider VOUT Range
Than LTM4630
Differential Remote Sense Amplifier
Current Mode Control/Fast Transient Response
Multiphase Parallel Current Sharing Up to 144A
Internal Temperature Monitor
Pin Compatible with the LTM4620A (Dual 13A,
Single 26A) and LTM4630 (Dual 18A, Single 36A)
Adjustable Switching Frequency or Synchronization
Overcurrent Foldback Protection
Selectable Burst Mode® Operation, Pulse Skipping
Mode Operation
Soft-Start/Voltage Tracking
Output Overvoltage Protection
16mm × 16mm × 4.41mm LGA Package
Applications
Telecom and Networking Equipment
Storage and ATCA Cards
n Industrial Equipment
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The LTM®4630A is a dual 18A or single 36A output switching mode step-down DC/DC µModule® (micromodule)
regulator with wider VOUT range and higher efficiency
than LTM4630. Included in the package are the switching controllers, power FETs, inductors and all supporting
components. Operating from an input voltage range of
4.5V to 15V, the LTM4630A supports two outputs each
with an output voltage range of 0.6V to 5.3V, each set by a
single external resistor. Its high efficiency design delivers
up to 18A continuous current for each output. Only a few
input and output capacitors are needed. The LTM4630A
is pin compatible with the LTM4620 and LTM4620A (dual
13A, single 26A) and the LTM4630 (dual 18A, single 36A).
The device supports frequency synchronization, multiphase operation, Burst Mode operation and output voltage
tracking for supply rail sequencing and has an onboard
temperature diode for device temperature monitoring. High
switching frequency and a current mode architecture enable
a very fast transient response to line and load changes
without sacrificing stability.
Fault protection features include overvoltage and
overcurrent protection. The LTM4630A is offered in 16mm
× 16mm × 4.41mm LGA package.
L, LT, LTC, LTM, Linear Technology, the Linear logo, µModule, Burst Mode and PolyPhase are
registered trademarks of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents, including 5481178, 5705919, 5929620,
6100678, 6144194, 6177787, 6304066 and 6580258. Other patents pending.
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Typical Application
36A, 1.2V Output DC/DC µModule Regulator
10k
PGOOD
4.7µF
VIN
4.5V TO 15V
22µF
25V
×4
VIN
INTVCC
PGOOD1
VOUT1
VOUTS1
120k
0.1µF
TEMP
TRACK1
DIFFOUT
VFB1
TRACK2
VFB2
LTM4630A
f SET
100µF
6.3V
+
90
60.4k
COMP1
RUN1
VOUT2
RUN2
PHASMD
DIFFN
DIFFP
SGND
GND
95
VOUT
470µF
6.3V
COMP2
75k
PINS UNUSED IN
THIS APPLICATION:
CLKOUT
EXTVCC
SW1
SW2
VOUTS2
100
PGOOD2
EFFICIENCY (%)
INTVCC
1.2VOUT and 3.3VOUT
Efficiency vs IOUT
85
80
75
100µF
6.3V
+
470µF
6.3V
MODE_PLLIN
4630A TA01a
12 VIN, 1.2VOUT, 300kHz
12 VIN, 3.3VOUT, 600kHz
5 VIN, 1.2VOUT, 300kHz
5 VIN, 3.3VOUT, 500kHz
70
65
0
2
4
8 10 12 14
6
LOAD CURRENT (A)
16
18
4630A TA01b
4630af
For more information www.linear.com/LTM4630A
1
LTM4630A
Absolute Maximum Ratings
Pin Configuration
(Note 1)
TOP VIEW
VIN (Note 8)..................................................–0.3V to 16V
VSW1, VSW2.....................................................–1V to 16V
PGOOD1, PGOOD2, RUN1, RUN2,
INTVCC , EXTVCC........................................... –0.3V to 6V
MODE_PLLIN, fSET, TRACK1, TRACK2,
DIFFOUT, PHASMD................................ –0.3V to INTVCC
VOUT1, VOUT2, VOUTS1, VOUTS2 (Note 6)......... –0.3V to 6V
DIFFP, DIFFN.......................................... –0.3V to INTVCC
COMP1, COMP2, VFB1, VFB2 (Note 6)......... –0.3V to 2.7V
INTVCC Peak Output Current.................................100mA
Internal Operating Temperature Range
(Note 2).............................................. –40°C to 125°C
Storage Temperature Range................... –55°C to 125°C
Peak Package Body Temperature........................... 245°C
TEMP
EXTVCC
M
L
VIN
K
J
CLKOUT
SW1
PHASMD
MODE_PLLIN
TRACK1
VFB1
VOUTS1
INTVCC
SW2
PGOOD1
PGOOD2
RUN2
DIFFOUT
DIFFP
DIFFN
H
G
RUN1
SGND
F
GND
COMP1 COMP2
E
SGND VFB2 TRACK2
D
GND
fSET SGND VOUTS2
C
B
VOUT1
VOUT2
GND
A
1
2
3
4
5
6
7
8
9
10
11
12
LGA PACKAGE
144-LEAD (16mm × 16mm × 4.41mm)
TJMAX = 125°C, ΘJA = 7°C/W, ΘJCbottom = 1.5°C/W, ΘJCtop = 3.7°C/W, ΘJB + ΘJBA ≅ 7°C/W
Θ VALUES DEFINED PER JESD51-12
WEIGHT = 3.2g
order information
PART NUMBER
PAD OR BALL FINISH
PART MARKING*
DEVICE
FINISH CODE
PACKAGE
TYPE
MSL
RATING
TEMPERATURE RANGE (NOTE 2)
LTM4630AEV#PBF
SAC305 (RoHS)
LTM4630AV
e1
LGA
3
–40°C to 125°C
LTM4630AIV#PBF
SAC305 (RoHS)
LTM4630AV
e1
LGA
3
–40°C to 125°C
Consult Marketing for parts specified with wider operating temperature
ranges. *Device temperature grade is indicated by a label on the shipping
container. Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Pb-free and Non-Pb-free Part Markings:
www.linear.com/leadfree
2
• Recommended LGA PCB Assembly and Manufacturing Procedures:
www.linear.com/umodule/pcbassembly
• LGA and BGA Package and Tray Drawings:
http://www.linear.com/packaging
4630af
For more information www.linear.com/LTM4630A
LTM4630A
Electrical
Characteristics
The l denotes the specifications which apply over the specified internal
operating temperature range. Specified as each individual output channel. TA = 25°C (Note 2), VIN = 12V and VRUN1, VRUN2 at 5V
unless otherwise noted. Per the typical application in Figure 31.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
VIN
Input DC Voltage
l
VOUT
Output Voltage
l
0.6
VOUT1(DC),
VOUT2(DC)
Output Voltage, Total Variation with
Line and Load
CIN = 22µF × 3, COUT = 100µF × 1 Ceramic,
470µF POSCAP
VIN = 12V, VOUT = 1.5V, IOUT = 0A to 18A
l
1.477
1.5
RUN Pin On/Off Threshold
RUN Rising
1.1
1.25
1.40
V
4.5
MAX
UNITS
15
V
5.3
V
1.523
V
Input Specifications
VRUN1, VRUN2
VRUN1HYS , VRUN2HYS RUN Pin On Hysteresis
150
mV
IINRUSH(VIN)
Input Inrush Current at Start-Up
IOUT = 0A, CIN = 22µF ×3, CSS = 0.01µF,
COUT = 100µF ×3, VOUT1 = 1.5V, VOUT2 = 1.5V,
VIN = 12V
1
A
IQ(VIN)
Input Supply Bias Current
VIN = 12V, VOUT = 1.5V, Burst Mode Operation
VIN = 12V, VOUT = 1.5V, Pulse-Skipping Mode
VIN = 12V, VOUT= 1.5V, Switching Continuous
Shutdown, RUN = 0, VIN = 12V
3
15
65
35
mA
mA
mA
µA
IS(VIN)
Input Supply Current
VIN = 5V, VOUT = 1.5V, IOUT = 18A
VIN = 12V, VOUT = 1.5V, IOUT = 18A
6.5
2.6
A
A
IOUT1(DC), IOUT2(DC)
Output Continuous Current Range
VIN = 12V, VOUT = 1.5V (Note 7)
ΔVOUT1(LINE) /VOUT1
ΔVOUT2(LINE) /VOUT2
Line Regulation Accuracy
VOUT = 1.5V, VIN from 4.5V to 15V
IOUT = 0A for Each Output,
l
0.01
0.025
%/V
ΔVOUT1/VOUT1
ΔVOUT2 /VOUT2
Load Regulation Accuracy
For Each Output, VOUT = 1.5V, 0A to 18A
VIN = 12V (Note 7)
l
0.5
0.75
%
Output Specifications
0
18
A
VOUT1(AC), VOUT2(AC) Output Ripple Voltage
For Each Output, IOUT = 0A, COUT = 100µF ×3/
X7R/Ceramic, 470µF POSCAP, VIN = 12V,
VOUT = 1.5V, Frequency = 450kHz
fS (Each Channel)
Output Ripple Voltage Frequency
VIN = 12V, VOUT = 1.5V, fSET = 1.25V (Note 4)
fSYNC
(Each Channel)
SYNC Capture Range
∆VOUTSTART
(Each Channel)
Turn-On Overshoot
COUT = 100µF/X5R/Ceramic, 470µF POSCAP,
VOUT = 1.5V, IOUT = 0A VIN = 12V
10
mV
tSTART
(Each Channel)
Turn-On Time
COUT = 100µF/X5R/Ceramic, 470µF POSCAP,
No Load, TRACK/SS with 0.01µF to GND,
VIN = 12V
5
ms
∆VOUT(LS)
(Each Channel)
Peak Deviation for Dynamic Load
Load: 0% to 50% to 0% of Full Load
COUT = 22µF ×3/X5R/Ceramic, 470µF POSCAP
VIN = 12V, VOUT = 1.5V
30
mV
tSETTLE
(Each Channel)
Settling Time for Dynamic Load
Step
Load: 0% to 50% to 0% of Full Load,
VIN = 12V, COUT = 100µF, 470µF POSCAP
20
µs
IOUT(PK)
(Each Channel)
Output Current Limit
VIN = 12V, VOUT = 1.5V
30
A
Voltage at VFB Pins
IOUT = 0A, VOUT = 1.5V
15
mVP-P
500
400
kHz
780
kHz
Control Section
VFB1, VFB2
l
0.592
0.600
0.606
V
–5
–20
nA
0.64
0.66
0.68
V
1
1.25
1.5
µA
(Note 6)
IFB
VOVL
Feedback Overvoltage Lockout
TRACK1 (I),
TRACK2 (I)
Track Pin Soft-Start Pull-Up Current
l
TRACK1 (I),TRACK2 (I) Start at 0V
4630af
For more information www.linear.com/LTM4630A
3
LTM4630A
Electrical Characteristics
The l denotes the specifications which apply over the specified internal
operating temperature range. Specified as each individual output channel. TA = 25°C (Note 2), VIN = 12V and VRUN1, VRUN2 at 5V
unless otherwise noted. Per the typical application in Figure 31.
SYMBOL
PARAMETER
UVLO
Undervoltage Lockout (Falling)
CONDITIONS
MIN
TYP
MAX
3.3
UVLO Hysteresis
tON(MIN)
Minimum On-Time
(Note 6)
RFBHI1, RFBHI2
Resistor Between VOUTS1, VOUTS2
and VFB1, VFB2 Pins for Each Output
VPGOOD1, VPGOOD2
Low
PGOOD Voltage Low
IPGOOD = 2mA
IPGOOD
PGOOD Leakage Current
VPGOOD = 5V
VPGOOD
PGOOD Trip Level
VFB with Respect to Set Output Voltage
VFB Ramping Negative
VFB Ramping Positive
60.05
UNITS
V
0.6
V
90
ns
60.4
60.75
0.1
0.3
V
±5
µA
–10
10
kΩ
%
%
INTVCC Linear Regulator
VINTVCC
Internal VCC Voltage
6V < VIN < 15V
VINTVCC
Load Regulation
INTVCC Load Regulation
ICC = 0mA to 50mA
VEXTVCC
EXTVCC Switchover Voltage
EXTVCC Ramping Positive
VEXTVCC(DROP)
EXTVCC Dropout
ICC = 20mA, VEXTVCC = 5V
VEXTVCC(HYST)
EXTVCC Hysteresis
4.8
4.5
5
5.2
V
0.5
2
%
100
mV
4.7
50
V
220
mV
Oscillator and Phase-Locked Loop
Frequency Nominal
Nominal Frequency
fSET = 1.2V
450
Frequency Low
Lowest Frequency
fSET = 0V (Note 5)
210
250
290
kHz
Frequency High
Highest Frequency
fSET > 2.4V, Up to INTVCC
700
780
860
kHz
fSET
Frequency Set Current
9
10
11
µA
RMODE_PLLIN
MODE_PLLIN Input Resistance
CLKOUT
Phase (Relative to VOUT1)
CLK High
CLK Low
Clock High Output Voltage
Clock Low Output Voltage
PHASMD = GND
PHASMD = Float
PHASMD = INTVCC
500
550
kHz
250
kΩ
60
90
120
Deg
Deg
Deg
2
0.2
V
V
Differential Amplifier
AV Differential
Amplifier
Gain
RIN
Input Resistance
Measured at DIFFP Input
VOS
Input Offset Voltage
VDIFFP = VDIFFOUT = 1.5V, IDIFFOUT = 100µA
PSRR Differential
Amplifier
Power Supply Rejection Ratio
5V < VIN < 15V
ICL
Maximum Output Current
VOUT(MAX)
Maximum Output Voltage
GBW
Gain Bandwidth Product
VTEMP
Diode Connected PNP
TC
Temperature Coefficient
4
1
V/V
80
kΩ
3
IDIFFOUT = 300µA
90
dB
3
mA
3
MHz
INTVCC – 1.4
I = 100µA
l
mV
V
0.6
V
–2.2
mV/C
4630af
For more information www.linear.com/LTM4630A
LTM4630A
Electrical Characteristics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTM4630A is tested under pulsed load conditions such that
TJ ≈ TA. The LTM4630AE is guaranteed to meet specifications from
0°C to 125°C internal temperature. Specifications over the –40°C to
125°C internal operating temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTM4630AI is guaranteed over the full –40°C to 125°C internal operating
temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
impedance and other environmental factors.
Note 3: Two outputs are tested separately and the same testing condition
is applied to each output.
Note 4: The switching frequency is programmable from 300kHz to 750kHz.
Note 5: LTM4630A device is designed to operate from 300kHz to 750kHz
Note 6: These parameters are tested at wafer sort.
Note 7: See Table 1 for Peak Current and Thermal Design Power (TDP)
current for different VIN and VOUT. See output current derating curve for
different ambient temperature.
Typical Performance Characteristics
0.9VOUT, 300kHz
1.0VOUT, 300kHz
1.2VOUT, 300kHz
1.5VOUT, 300kHz
1.8VOUT, 300kHz
2.5VOUT, 400kHz
3.3VOUT, 500kHz
0
2
4
6
8 10 12 14
LOAD CURRENT (A)
16
18
100
98
96
94
92
90
88
86
84
82
80
78
76
74
72
70
Burst Mode and Pulse-Skip Mode
Efficiency VIN=12V, VOUT = 1.2V,
fS = 300kHz
Efficiency vs Output Current,
VIN = 12V
EFFICIENCY (%)
100
98
96
94
92
90
88
86
84
82
80
78
76
74
72
70
EFFICIENCY (%)
EFFICIENCY (%)
Efficiency vs Output Current,
VIN = 5V
0.9VOUT, 300kHz
1.0VOUT, 300kHz
1.2VOUT, 300kHz
1.5VOUT, 400kHz
1.8VOUT, 400kHz
2.5VOUT, 500kHz
3.3VOUT, 600kHz
5VOUT, 700kHz
0
2
4
6
8 10 12 14
LOAD CURRENT (A)
16
18
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
0.01
Burst Mode OPERATION
PULSE-SKIP MODE
CCM
0.1
1
LOAD CURRENT (A)
4630A G02
4630A G01
1V Dual Phase Single Output
Load Transient Response
10
4630A G04
1.2V Dual Phase Single Output
Load Transient Response
VOUT(AC)
20mV/DIV
VOUT(AC)
20mV/DIV
LOAD STEP
10A/DIV
LOAD STEP
10A/DIV
4630A G05
50µs/DIV
12VIN, 1VOUT, 300kHz, DUAL PHASE SINGLE
OUTPUT SETUP 9A LOAD STEP UP AND STEP
DOWN, 9A/µs SLEW RATE COUT = 2 • 220µF
POSCAP + 4 • 100µF CERAMIC CAPS
4630A G06
50µs/DIV
12VIN, 1.2VOUT, 300kHz, DUAL PHASE SINGLE
OUTPUT SETUP 9A LOAD STEP UP AND STEP
DOWN, 9A/µs SLEW RATE COUT = 2 • 220µF
POSCAP + 4 • 100µF CERAMIC CAPS
4630af
For more information www.linear.com/LTM4630A
5
LTM4630A
Typical Performance Characteristics
1.5V Dual Phase Single Output
Load Transient Response
1.8V Dual Phase Single Output
Load Transient Response
2.5V Dual Phase Single Output
Load Transient Response
VOUT(AC)
20mV/Div
VOUT(AC)
20mV/Div
VOUT(AC)
20mV/Div
LOAD STEP
10A/DIV
LOAD STEP
10A/DIV
LOAD STEP
10A/DIV
4630A G07
4630A G08
4630A G09
50µs/DIV
12VIN, 1.5VOUT, 400kHz, DUAL PHASE SINGLE
OUTPUT SETUP 9A LOAD STEP UP AND STEP
DOWN, 9A/µs SLEW RATE COUT = 2 • 220µF
POSCAP + 4 • 100µF CERAMIC CAPS
50µs/DIV
12VIN, 1.8VOUT, 400kHz, DUAL PHASE SINGLE
OUTPUT SETUP 9A LOAD STEP UP AND STEP
DOWN, 9A/µs SLEW RATE COUT = 2 • 220µF
POSCAP + 4 • 100µF CERAMIC CAPS
50µs/DIV
12VIN, 2.5VOUT, 500kHz, DUAL PHASE SINGLE
OUTPUT SETUP 9A LOAD STEP UP AND STEP
DOWN, 9A/µs SLEW RATE COUT = 2 • 220µF
POSCAP + 4 • 100µF CERAMIC CAPS
3.3V Dual Phase Single Output
Load Transient Response
Single Phase Start-Up with No load
Single Phase Start-up with 18A
VOUT(AC)
20mV/Div
VSW
10V/Div
VSW
10V/Div
LOAD STEP
10A/DIV
VOUT
0.5V/Div
IIN
0.2A/Div
VOUT
0.5V/Div
IIN
1A/Div
4630A G10
4630A G11
50µs/DIV
12VIN, 3.3VOUT, 600kHz, DUAL PHASE SINGLE
OUTPUT SETUP 9A LOAD STEP UP AND STEP
DOWN, 9A/µs SLEW RATE COUT = 2 • 220µF
POSCAP + 4 • 100µF CERAMIC CAPS
20ms/DIV
12VIN, 1.2VOUT, 300kHz
COUT = 1 • 470µF 4V POSCAP + 1 • 100µF
6.3V CERAMIC, CSS = 0.1µF
Single Phase Short Circuit
Protection with 18A
Single Phase Short Circuit
Protection with No load
VSW
10V/Div
VSW
10V/Div
VOUT
0.5V/Div
VOUT
0.5V/Div
IIN
1A/Div
IIN
1A/Div
4630A G13
50µs/DIV
12VIN, 1.2VOUT, 300kHz
COUT = 1 • 470µF 4V POSCAP + 1 • 100µF
6.3V CERAMIC
6
4630A G12
20ms/DIV
12VIN, 1.2VOUT, 300kHz
COUT = 1 • 470µF 4V POSCAP + 1 • 100µF
6.3V CERAMIC, CSS = 0.1µF
4630A G14
50µs/DIV
12VIN, 1.2VOUT, 300kHz
COUT = 1 • 470µF 4V POSCAP + 1 • 100µF
6.3V CERAMIC
4630af
For more information www.linear.com/LTM4630A
LTM4630A
Pin Functions
(Recommended to Use Test Points to Monitor Signal Pin Connections.)
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
VOUT1 (A1-A5, B1-B5, C1-C4): Power Output Pins. Apply
output load between these pins and GND pins. Recommend placing output decoupling capacitance directly
between these pins and GND pins. Review Table 6 for
output capacitance requirement. See Table 1 for output
current guideline.
GND (A6-A7, B6-B7, D1-D4, D9-D12, E1-E4, E10-E12,
F1-F3, F10-F12, G1, G3, G10, G12, H1-H7, H9-H12, J1,
J5, J8, J12, K1, K5-K8, K12, L1, L12, M1 , M12): Power
Ground Pins for Both Input and Output Returns.
VOUT2 (A8-A12, B8-B12, C9-C12): Power Output
Pins. Apply output load between these pins and GND
pins. Recommend placing output decoupling capacitance directly between these pins and GND pins.
Review Table 6 for output capacitance requirement.
See Table 1 for output current guideline.
VOUTS1, VOUTS2 (C5, C8): This pin is connected to the top
of the internal top feedback resistor for each output. The
pin can be directly connected to its specific output, or
connected to DIFFOUT when the remote sense amplifier
is used. In paralleling modules, one of the VOUTS pins is
connected to the DIFFOUT pin in remote sensing or directly
to VOUT with no remote sensing. It is very important to
connect these pins to either the DIFFOUT or VOUT since
this is the feedback path, and cannot be left open. See the
Applications Information section.
fSET (C6): Frequency Set Pin. A 10µA current is sourced
from this pin. A resistor from this pin to ground sets a
voltage that in turn programs the operating frequency.
Alternatively, this pin can be driven with a DC voltage
that can set the operating frequency. See the Applications
Information section.
VFB1, VFB2 (D5, D7): The Negative Input of the Error
Amplifier for each channel. Internally, this pin is connected to VOUTS1 or VOUTS2 with a 60.4kΩ precision
resistor. Different output voltages can be programmed
with an additional resistor between VFB and GND pins. In
PolyPhase® operation, tying the VFB pins together allows
for parallel operation. See the Applications Information
section for details.
TRACK1, TRACK2 (E5, D8): Output Voltage Tracking Pin
and Soft-Start Inputs. Each channel has a 1.3µA pull-up
current source. When one channel is configured to be
master of the two channels, then a capacitor from this pin
to ground will set a soft-start ramp rate. The remaining
channel can be set up as the slave, and have the master’s
output applied through a voltage divider to the slave output’s track pin. This voltage divider is equal to the slave
output’s feedback divider for coincidental tracking. See
the Applications Information section.
COMP1, COMP2 (E6, E7): Current control threshold and
error amplifier compensation point for each channel. The
current comparator threshold increases with this control
voltage. Tie the COMP pins together for parallel operation.
The device is internal compensated.
DIFFP (E8): Positive input of the remote sense amplifier.
This pin is connected to the remote sense point of the
output voltage. Diffamp can be used for ≤ 3.3V outputs.
See the Applications Information section.
DIFFN (E9): Negative input of the remote sense amplifier.
This pin is connected to the remote sense point of the
output GND. Diffamp can be used for ≤ 3.3V outputs. See
the Applications Information section.
SGND (C7, D6, G6-G7, F6-F7): Signal Ground Pin. Return
ground path for all analog and low power circuitry. Tie a
single connection to the output capacitor GND in the application. See layout guidelines in Figure 12.
4630af
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7
LTM4630A
Pin Functions
(Recommended to Use Test Points to Monitor Signal Pin Connections.)
MODE_PLLIN (F4): Force Continuous Mode, Burst Mode
Operation, or Pulse-Skipping Mode Selection Pin and
External Synchronization Input to Phase Detector Pin.
Connect this pin to SGND to force both channels into
force continuous mode of operation. Connect to INTVCC
to enable pulse-skipping mode of operation. Leaving the
pin floating will enable Burst Mode operation. A clock on
the pin will force both channels into continuous mode of
operation and synchronized to the external clock applied
to this pin.
RUN1, RUN2 (F5, F9): Run Control Pin. A voltage above
1.25V will turn on each channel in the module. A voltage
below 1.25V on the RUN pin will turn off the related channel. Each RUN pin has a 1µA pull-up current, once the
RUN pin reaches 1.2V an additional 4.5µA pull-up current
is added to this pin.
DIFFOUT (F8): Internal Remote Sense Amplifier Output.
Connect this pin to VOUTS1 or VOUTS2 depending on which
output is using remote sense. In parallel operation connect one of the VOUTS pin to DIFFOUT for remote sensing.
Diffamp can be used for ≤ 3.3V outputs.
SW1, SW2 (G2, G11): Switching node of each channel
that is used for testing purposes. Also an R-C snubber
network can be applied to reduce or eliminate switch node
ringing, or otherwise leave floating. See the Applications
Information section.
PHASMD (G4): Connect this pin to SGND, INTVCC, or floating this pin to select the phase of CLKOUT to 60 degrees,
120 degrees, and 90 degrees respectively.
8
CLKOUT (G5): Clock output with phase control using the
PHASMD pin to enable multiphase operation between
devices. See the Applications Information section.
PGOOD1, PGOOD2 (G9, G8): Output Voltage Power
Good Indicator. Open drain logic output that is pulled to
ground when the output voltage is not within ±10% of
the regulation point.
INTVCC (H8): Internal 5V Regulator Output. The control
circuits and internal gate drivers are powered from this
voltage. Decouple this pin to PGND with a 4.7µF low ESR
tantalum or ceramic. INTVCC is activated when either RUN1
or RUN2 is activated.
TEMP (J6): Onboard General Purpose Temperature Diode
for Monitoring the VBE Junction Voltage Change with
Temperature. See the Applications Information section.
EXTVCC (J7): External power input that is enabled through
a switch to INTVCC whenever EXTVCC is greater than 4.7V.
Do not exceed 6V on this input, and connect this pin to
VIN when operating VIN on 5V. An efficiency increase will
occur that is a function of the (VIN – INTVCC) multiplied by
power MOSFET driver current. Typical current requirement
is 30mA. VIN must be applied before EXTVCC , and EXTVCC
must be removed before VIN.
VIN (M2-M11, L2-L11, J2-J4, J9-J11, K2-K4, K9-K11):
Power Input Pins. Apply input voltage between these pins
and GND pins. Recommend placing input decoupling
capacitance directly between VIN pins and GND pins.
4630af
For more information www.linear.com/LTM4630A
LTM4630A
simplified block diagram
PGOOD1
TRACK1
SS CAP
VIN
= 100µA VIN
RT
OR TEMP
MONITORS
VIN
4.5V TO 15V
VIN
CIN1
22µF
25V
0.1µF
GND
RT
TEMP
MTOP1
SW1
CLKOUT
0.56µH
RUN1
MODE_PLLIN
VOUT1
1.5V
18A
VOUT1
0.22µF
MBOT1
PHASEMD
CIN2
22µF
25V
+
GND
COUT1
VOUTS1
COMP1
60.4k
VFB1
INTERNAL
COMP
SGND
RFB1
40.2k
POWER
CONTROL
PGOOD2
TRACK2
VIN
INTVCC
SS CAP
CIN3
22µF
25V
0.1µF
4.7µF
GND
EXTVCC
MTOP2
SW2
0.56µH
RUN2
CIN4
22µF
25V
VOUT2
0.22µF
MBOT2
GND
+
VOUT2
1.2V
18A
COUT2
VOUTS2
60.4k
COMP2
fSET
RFSET
SGND
+ –
VFB2
RFB2
60.4k
INTERNAL
COMP
INTERNAL
FILTER
DIFFOUT
DIFFN
DIFFP
4630A BD
Figure 1. Simplified LTM4630A Block Diagram
decoupling requirements
TA = 25°C. Use Figure 1 configuration.
SYMBOL
PARAMETER
CONDITIONS
CIN1, CIN2
CIN3, CIN4
External Input Capacitor Requirement
(VIN1 = 4.5V to 15V, VOUT1 = 1.5V)
(VIN2 = 4.5V to 15V, VOUT2 = 1.2V)
MIN
TYP
MAX
UNITS
IOUT1 = 18A
IOUT2 = 18A
44
44
µF
µF
COUT1
COUT2
External Output Capacitor Requirement
(VIN1 = 4.5V to 15V, VOUT1 = 1.5V)
(VIN2 = 4.5V to 15V, VOUT2 = 1.2V)
IOUT1 = 18A
IOUT2 = 18A
400
400
µF
µF
4630af
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9
LTM4630A
Operation
Power Module Description
The LTM4630A is a dual-output standalone nonisolated
switching mode DC/DC power supply. It can provide two
18A outputs with few external input and output capacitors
and setup components. This module provides precisely
regulated output voltages programmable via external
resistors from 0.6VDC to 5.3VDC over 4.5V to 15V input
voltages. The typical application schematic is shown in
Figure 31. See Table 1 for different output current and
frequency guideline.
The LTM4630A has dual integrated constant-frequency
current mode regulators and built-in power MOSFET
devices with fast switching speed. For switching-noise
sensitive applications, it can be externally synchronized
from 300kHz to 780kHz. A resistor can be used to program
a free run frequency on the FSET pin. See the Applications
Information section.
With current mode control and internal feedback loop
compensation, the LTM4630A module has sufficient
stability margins and good transient performance with
a wide range of output capacitors, even with all ceramic
output capacitors.
Current mode control provides cycle-by-cycle fast current
limit and foldback current limit in an overcurrent condition.
Internal overvoltage and undervoltage comparators pull
the open-drain PGOOD outputs low if the output feedback
voltage exits a ±10% window around the regulation point.
As the output voltage exceeds 10% above regulation, the
bottom MOSFET will turn on to clamp the output voltage.
The top MOSFET will be turned off. This overvoltage protect
is feedback voltage referred.
Pulling the RUN pins below 1.1V forces the regulators into
a shutdown state, by turning off both MOSFETs. The TRACK
pins are used for programming the output voltage ramp and
10
voltage tracking during start-up or used for soft-starting
the regulator. See the Applications Information section.
The LTM4630A is internally compensated to be stable
over all operating conditions. Table 6 provides a guide line
for input and output capacitances for several operating
conditions. The Linear Technology µModule Power Design
Tool will be transient and stability analysis. The VFB pin is
used to program the output voltage with a single external
resistor to ground. A differential remote sense amplifier is
available for sensing the output voltage accurately on one
of the outputs at the load point, or in parallel operation
sensing the output voltage at the load point.
Multiphase operation can be easily employed with the
MODE_PLLIN, PHASMD, and CLKOUT pins. Up to 12
phases can be cascaded to run simultaneously with respect to each other by programming the PHASMD pin to
different levels. See the Applications Information section.
High efficiency at light loads can be accomplished with
selectable Burst Mode operation or pulse-skipping
operation using the MODE_PLLIN pin. These light load
features will accommodate battery operation. Efficiency
graphs are provided for light load operation in the Typical
Performance Characteristics section. See the Applications
Information section for details.
A general purpose temperature diode is included inside
the module to monitor the temperature of the module. See
the Applications Information section for details.
The switch pins are available for functional operation
monitoring and a resistor-capacitor snubber circuit can
be careful placed on the switch pin to ground to dampen
any high frequency ringing on the transition edges. See
the Applications Information section for details.
4630af
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LTM4630A
Applications Information
The typical LTM4630A application circuit is shown in
Figure 31. External component selection is primarily
determined by the maximum load current and output
voltage. Refer to Table 6 for specific external capacitor
requirements for particular applications.
VIN to VOUT Step-Down Ratios
There are restrictions in the maximum VIN and VOUT stepdown ratio that can be achieved for a given input voltage.
Each output of the LTM4630A is capable of 98% duty
cycle, but the VIN to VOUT minimum dropout is still shown
as a function of its load current and will limit output current capability related to high duty cycle on the top side
switch. Minimum on-time tON(MIN) is another consideration
in operating at a specified duty cycle while operating at
a certain frequency due to the fact that tON(MIN) < D/fSW,
where D is duty cycle and fSW is the switching frequency.
tON(MIN) is specified in the electrical parameters as 90ns.
either VFB1 or VFB2. Adding a resistor RFB from VFB pin to
GND programs the output voltage:
60.4k +RFB
VOUT = 0.6V •
RFB
For parallel operation of multiple channels the same feedback setting resistor can be used for the parallel design.
This is done by connecting the VOUTS1 to the output as
shown in Figure 2, thus tying one of the internal 60.4k
resistors to the output. All of the VFB pins tie together with
one programming resistor as shown in Figure 2.
COMP1 LTM4630A
VOUT1
COMP2
VOUT2
60.4k
VOUTS1
VOUTS2
OPTIONAL CONNECTION
VFB1
TRACK1
60.4k
VFB2
TRACK2
Output Voltage Programming
The PWM controller has an internal 0.6V reference voltage.
As shown in the Block Diagram, a 60.4kΩ internal feedback
resistor connects between the VOUTS1 to VFB1 and VOUTS2
to VFB2. It is very important that these pins be connected
to their respective outputs for proper feedback regulation.
Overvoltage can occur if these VOUTS1 and VOUTS2 pins are
left floating when used as individual regulators, or at least
one of them is used in paralleled regulators. The output
voltage will default to 0.6V with no feedback resistor on
4 PARALLELED OUTPUTS
FOR 1.2V AT 70A
COMP1 LTM4630A
VOUT1
COMP2
VOUT2
60.4k
OPTIONAL
RFB
60.4k
USE TO LOWER
TOTAL EQUIVALENT
RESISTANCE TO LOWER
IFB VOLTAGE ERROR
VOUTS1
VOUTS2
VFB1
TRACK1
0.1µF
TRACK2
60.4k
VFB2
4630A F02
RFB
60.4k
Figure 2. 4-Phase Parallel Configurations
Table 1. FREQ Resistor, VFB Resistor, Output Current vs Various Output Voltages
VOUT
RFB
VIN
0.9V
1V
1.2V
1.5V
1.8V
2.5V
3.3V
5V
121k
90.9k
60.4k
40.2k
30.2k
19.1k
13.3k
8.25k
4.5V to 4.5V to 4.5V to 4.5V to 10V to 4.5V to 10V to 4.5V to 10V to 4.5V to 10V to 7V to 10V to
15V
15V
15V
9V
15V
9V
15V
9V
15V
9V
15V
9V
15V
FREQ
300kHz 300kHz 300kHz 300kHz 400kHz 300kHz 400kHz 400kHz 500kHz 500kHz 600kHz 600kHz 700kHz
75k
75k
75k
75k
90.9k
75k
90.9k
90.9k
121k
121k
140k
140k
162k
RFREQ
Peak Output Current
18A
18A
18A
18A
18A
18A
18A
18A
18A
18A
18A
18A
18A
TDP Output Current (0 LFM)
18A
18A
18A
18A
16A
18A
16A
17A
15A
16A
14A
15A
13A
18A
18A
18A
18A
18A
18A
18A
18A
18A
18A
18A
18A
18A
TDP Output Current
(200LFM or 400LPM)
*TDP is Thermal Design Power at no airflow and no heat sink. Any design beyond TDP current may consider airflow or heat sink. See Current Derating
curve for different TA and airflow.
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11
LTM4630A
Applications Information
In parallel operation, the VFB pins have an IFB current of 20nA
maximum each channel. To reduce output voltage error due
to this current, an additional VOUTS pin can be tied to VOUT,
and an additional RFB resistor can be used to lower the total
Thevenin equivalent resistance seen by this current. For
example in Figure 2, the total Thevenin equivalent resistance
of the VFB pin is (60.4k//RFB), which is 30.2k where RFB is
equal to 60.4k for a 1.2V output. Four phases connected
in parallel equates to a worse case feedback current of
4 • IFB = 80nA maximum. The voltage error is 80nA • 30.2k
= 2.4mV. If VOUTS2 is connected, as shown in Figure 2, to
VOUT, and another 60.4k resistor is connected from VFB2 to
ground, then the voltage error is reduced to 1.2mV. If the
voltage error is acceptable then no additional connections
are necessary. The onboard 60.4k resistor is 0.5% accurate
and the VFB resistor can be chosen by the user to be as accurate as needed. All COMP pins are tied together for current
sharing between the phases. The TRACK/SS pins can be tied
together and a single soft-start capacitor can be used to softstart the regulator. The soft-start equation will need to have
the soft-start current parameter increased by the number
of paralleled channels. See Output Voltage Tracking section.
Input Capacitors
The LTM4630A module should be connected to a low acimpedance DC source. For each regulator input two 22µF
input ceramic capacitors are used for RMS ripple current.
A 47µF to 100µF surface mount aluminum electrolytic bulk
capacitor can be used for more input bulk capacitance.
This bulk input capacitor is only needed if the input source
impedance is compromised by long inductive leads, traces
or not enough source capacitance. If low impedance power
planes are used, then this bulk capacitor is not needed.
For a buck converter, the switching duty-cycle can be
estimated as:
D=
VOUT
VIN
Without considering the inductor current ripple, for each
output, the RMS current of the input capacitor can be
estimated as:
IOUT(MAX)
ICIN(RMS) =
• D • (1−D)
η%
12
In the above equation, η% is the estimated efficiency of
the power module. The bulk capacitor can be a switcherrated electrolytic aluminum capacitor, Polymer capacitor.
Output Capacitors
The LTM4630A is designed for low output voltage ripple
noise and good transient response. The bulk output
capacitors defined as COUT are chosen with low enough
effective series resistance (ESR) to meet the output voltage ripple and transient requirements. COUT can be a low
ESR tantalum capacitor, the low ESR polymer capacitor
or ceramic capacitor. The typical output capacitance range
for each output is from 200µF to 470µF. Additional output
filtering may be required by the system designer, if further
reduction of output ripples or dynamic transient spikes is
required. Table 6 shows a matrix of different output voltages
and output capacitors to minimize the voltage droop and
overshoot for each output channel running a 4.5A load
step. The table optimizes total equivalent ESR and total
bulk capacitance to optimize the transient performance.
Stability criteria are considered in the Table 6 matrix, and
the Linear Technology µModule Power Design Tool will be
provided for stability analysis. Multiphase operation will
reduce effective output ripple as a function of the number of phases. Application Note 77 discusses this noise
reduction versus output ripple current cancellation, but
the output capacitance should be considered carefully as
a function of stability and transient response. The Linear
Technology µModule Power Design Tool can calculate the
output ripple reduction as the number of implemented
phases increases by N times. A small value 10Ω to 50Ω
resistor can be place in series from VOUT to the VOUTS pin
to allow for a bode plot analyzer to inject a signal into the
control loop and validate the regulator stability. The same
resistor could be place in series from VOUT to DIFFP and
a bode plot analyzer could inject a signal into the control
loop and validate the regulator stability.
Burst Mode Operation
The LTM4630A is capable of Burst Mode operation on
each regulator in which the power MOSFETs operate
intermittently based on load demand, thus saving quiescent
current. For applications where maximizing the efficiency
at very light loads is a high priority, Burst Mode operation
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4630af
LTM4630A
Applications Information
should be applied. Burst Mode operation is enabled with
the MODE_PLLIN pin floating. During this operation, the
peak current of the inductor is set to approximately one
third of the maximum peak current value in normal operation even though the voltage at the COMP pin indicates
a lower value. The voltage at the COMP pin drops when
the inductor’s average current is greater than the load
requirement. As the COMP voltage drops below 0.5V, the
BURST comparator trips, causing the internal sleep line
to go high and turn off both power MOSFETs.
In sleep mode, the internal circuitry is partially turned off,
reducing the quiescent current to about 450µA for each
output. The load current is now being supplied from the
output capacitors. When the output voltage drops, causing COMP to rise above 0.5V, the internal sleep line goes
low, and the LTM4630A resumes normal operation. The
next oscillator cycle will turn on the top power MOSFET
and the switching cycle repeats. Either regulator can be
configured for Burst Mode operation.
Pulse-Skipping Mode Operation
In applications where low output ripple and high efficiency
at intermediate currents are desired, pulse-skipping
mode should be used. Pulse-skipping operation allows
the LTM4630A to skip cycles at low output loads, thus
increasing efficiency by reducing switching loss. Tying
the MODE_PLLIN pin to INTVCC enables pulse-skipping
operation. At light loads the internal current comparator
may remain tripped for several cycles and force the top
MOSFET to stay off for several cycles, thus skipping cycles.
The inductor current does not reverse in this mode. This
mode will maintain higher effective frequencies thus lower
output ripple and lower noise than Burst Mode operation.
Either regulator can be configured for pulse-skipping mode.
Forced Continuous Operation
In applications where fixed frequency operation is more
critical than low current efficiency, and where the lowest
output ripple is desired, forced continuous operation
should be used. Forced continuous operation can be
enabled by tying the MODE_PLLIN pin to GND. In this
mode, inductor current is allowed to reverse during low
output loads, the COMP voltage is in control of the current
comparator threshold throughout, and the top MOSFET
always turns on with each oscillator pulse. During start-up,
forced continuous mode is disabled and inductor current
is prevented from reversing until the LTM4630A’s output
voltage is in regulation. Either regulator can be configured
for force continuous mode.
Multiphase Operation
For output loads that demand more than 18A of current,
two outputs in LTM4630A or even multiple LTM4630As can
be paralleled to run out of phase to provide more output
current without increasing input and output voltage ripples.
The MODE_PLLIN pin allows the LTM4630A to synchronize
to an external clock (between 300kHz and 780kHz) and the
internal phase-locked-loop allows the LTM4630A to lock
onto incoming clock phase as well. The CLKOUT signal
can be connected to the MODE_PLLIN pin of the following
stage to line up both the frequency and the phase of the
entire system. Tying the PHASMD pin to INTVCC, SGND, or
(floating) generates a phase difference (between
MODE_PLLIN and CLKOUT) of 120 degrees, 60 degrees,
or 90 degrees respectively. A total of 12 phases can be
cascaded to run simultaneously with respect to each other
by programming the PHASMD pin of each LTM4630A channel to different levels. Figure 3 shows a 2-phase design,
4-phase design and a 6-phase design example for clock
phasing with the PHASMD table.
A multiphase power supply significantly reduces the
amount of ripple current in both the input and output capacitors. The RMS input ripple current is reduced by, and
the effective ripple frequency is multiplied by, the number
of phases used (assuming that the input voltage is greater
than the number of phases used times the output voltage).
The output ripple amplitude is also reduced by the number
of phases used when all of the outputs are tied together
to achieve a single high output current design.
The LTM4630A device is an inherently current mode
controlled device, so parallel modules will have very good
current sharing. This will balance the thermals on the
design. Figure 32 shows an example of parallel operation
and pin connection.
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13
LTM4630A
Applications Information
2-PHASE DESIGN
PHASMD
FLOAT
CLKOUT
0 PHASE
MODE_PLLIN
VOUT1
VOUT2
SGND
FLOAT
CONTROLLER1
0
0
0
CONTROLLER2
180
180
240
CLKOUT
60
90
120
180 PHASE
INTVCC
PHASMD
4-PHASE DESIGN
90 DEGREE
CLKOUT
0 PHASE
FLOAT
CLKOUT
MODE_PLLIN
VOUT1
VOUT2
180 PHASE
90 PHASE
FLOAT
PHASMD
MODE_PLLIN
VOUT1
VOUT2
270 PHASE
PHASMD
6-PHASE DESIGN
60 DEGREE
60 DEGREE
CLKOUT
0 PHASE
SGND
CLKOUT
MODE_PLLIN
VOUT1
VOUT2
180 PHASE
60 PHASE
SGND
PHASMD
CLKOUT
MODE_PLLIN
VOUT1
VOUT2
240 PHASE
PHASMD
120 PHASE
FLOAT
MODE_PLLIN
VOUT1
VOUT2
300 PHASE
PHASMD
4630A F03
Figure 3. Examples of 2-Phase, 4-Phase, and 6-Phase Operation with PHASMD Table
0.60
1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE
0.55
0.50
RMS INPUT RIPPLE CURRENT
DC LOAD CURRENT
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.1 0.15
0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY FACTOR (VOUT/VIN)
4630A F04
Figure 4. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle
14
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LTM4630A
Applications Information
Input RMS Ripple Current Cancellation
900
800
Application Note 77 provides a detailed explanation of
multiphase operation. The input RMS ripple current cancellation mathematical derivations are presented, and a graph
is displayed representing the RMS ripple current reduction
as a function of the number of interleaved phases. Figure 4
shows this graph.
FREQUENCY (kHz)
700
The LTM4630A switching frequency can be set with an
external resistor from the fSET pin to SGND. An accurate
10µA current source into the resistor will set a voltage
that programs the frequency or a DC voltage can be
applied. Figure 5 shows a graph of frequency setting
verses programming voltage. An external clock can be
applied to the MODE_PLLIN pin from 0V to INTVCC over
a frequency range of 300kHz to 780kHz. The clock input
high threshold is 1.6V and the clock input low threshold
is 1V. The LTM4630A has the PLL loop filter components
on board. The frequency setting resistor should always
be present to set the initial switching frequency before
locking to an external clock. Both regulators will operate
in continuous mode while being externally clock.
The output of the PLL phase detector has a pair of complementary current sources that charge and discharge the
internal filter network. When the external clock is applied
then the fSET frequency resistor is disconnected with
an internal switch, and the current sources control the
frequency adjustment to lock to the incoming external
clock. When no external clock is applied, then the internal
500
400
300
200
Frequency Selection and Phase-Lock Loop
(MODE/PLLIN and fSET Pins)
The LTM4630A device is operated over a range of frequencies to improve power conversion efficiency. It is recommended to operate the lower output voltages or lower
duty cycle conversions at lower frequencies to improve
efficiency by lowering power MOSFET switching losses.
Higher output voltages or higher duty cycle conversions
can be operated at higher frequencies to limit inductor
ripple current. The efficiency graphs will show an operating frequency chosen for that condition. See Table 1 for
optimized frequency for various output voltages. Select
frequency in reference to the highest output voltage.
600
100
0
0
0.5
1
1.5
fSET PIN VOLTAGE (V)
2
2.5
4630A F05
Figure 5. Operating Frequency vs fSET Pin Voltage
switch is on, thus connecting the external fSET frequency
set resistor for free run operation.
Minimum On-Time
Minimum on-time tON is the smallest time duration that
the LTM4630A is capable of turning on the top MOSFET on
either channel. It is determined by internal timing delays,
and the gate charge required turning on the top MOSFET.
Low duty cycle applications may approach this minimum
on-time limit and care should be taken to ensure that:
VOUT
> tON(MIN)
VIN • FREQ
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the output ripple and current will increase. The on-time
can be increased by lowering the switching frequency. A
good rule of thumb is to keep on-time longer than 110ns.
Output Voltage Tracking
Output voltage tracking can be programmed externally
using the TRACK/SS pins. The output can be tracked up
and down with another regulator. The master regulator’s
output is divided down with an external resistor divider
that is the same as the slave regulator’s feedback divider
to implement coincident tracking. The LTM4630A uses
an accurate 60.4k resistor internally for the top feedback
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15
LTM4630A
Applications Information
INTVCC
C10
4.7µF
R2
10k
PGOOD
MODE_PLLIN
4V TO 15V INTERMEDIATE BUS
C4
22µF
25V
C3
22µF
25V
C2
22µF
25V
C1
22µF
25V
R6
100k
TEMP
VOUTS1
RUN1
SW1
RUN2
VFB1
RTA
90.9k
VOUT1
1.5V
C6
100µF
6.3V
VFB2
LTM4630A
TRACK2
RTB
60.4k
PGOOD1
VOUT1
TRACK1
MASTER
CSS
0.1µF
CLKOUT INTVCC EXTVCC
VIN
RFB
60.4k
COMP1
f SET
COMP2
PHASMD
VOUTS2
VOUT2
R4
90.9k
VOUT2
1.2V AT 18A
C5
100µF
6.3V
PGOOD2
GND
DIFFP
DIFFN
40.2k
SLAVE
SW2 PGOOD
SGND
C8
470µF
6.3V
DIFFOUT
VOUT1
1.5V AT 18A
C7
470µF
6.3V
INTVCC
R9
10k
RAMP TIME
tSOFTSTART = (CSS /1.3µA) • 0.6
4630A F06
Figure 6. Example of Output Tracking Application Circuit
resistor for each channel. Figure 6 shows an example of
coincident tracking. Equations:
 60.4k 
SLAVE = 1+
 • VTRACK
RTA 

VTRACK is the track ramp applied to the slave’s track pin.
VTRACK has a control range of 0V to 0.6V, or the internal
reference voltage. When the master’s output is divided
down with the same resistor values used to set the slave’s
output, then the slave will coincident track with the master
until it reaches its final value. The master will continue to
its final value from the slave’s regulation point. Voltage
tracking is disabled when VTRACK is more than 0.6V. RTA
in Figure 6 will be equal to the RFB for coincident tracking.
Figure 7 shows the coincident tracking waveforms.
The TRACK pin of the master can be controlled by a
capacitor placed on the master regulator TRACK pin to
ground. A 1.3µA current source will charge the TRACK
pin up to the reference voltage and then proceed up
to INTVCC. After the 0.6V ramp, the TRACK pin will no
longer be in control, and the internal voltage reference
will control output regulation from the feedback divider.
Foldback current limit is disabled during this sequence
16
OUTPUT VOLTAGE
MASTER OUTPUT
SLAVE OUTPUT
TIME
4630A F07
Figure 7. Output Coincident Tracking Waveform
of turn-on during tracking or soft-starting. The TRACK
pins are pulled low when the RUN pin is below 1.2V. The
total soft-start time can be calculated as:
 C 
tSOFT-START =  SS  • 0.6
 1.3µA 
Regardless of the mode selected by the MODE_PLLIN pin,
the regulator channels will always start in pulse-skipping
mode up to TRACK = 0.5V. Between TRACK = 0.5V and
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0.54V, it will operate in forced continuous mode and revert
to the selected mode once TRACK > 0.54V. In order to
track with another channel once in steady state operation,
the LTM4630A is forced into continuous mode operation
as soon as VFB is below 0.54V regardless of the setting
on the MODE_PLLIN pin.
Ratiometric tracking can be achieved by a few simple calculations and the slew rate value applied to the master’s
TRACK pin. As mentioned above, the TRACK pin has a
control range from 0 to 0.6V. The master’s TRACK pin
slew rate is directly equal to the master’s output slew rate
in Volts/Time. The equation:
MR
• 60.4k = RTB
SR
where MR is the master’s output slew rate and SR is the
slave’s output slew rate in Volts/Time. When coincident
tracking is desired, then MR and SR are equal, thus RTB
is equal the 60.4k. RTA is derived from equation:
RTA
0.6V
=
V
V
VFB
+ FB − TRACK
60.4k RFB
RTB
where VFB is the feedback voltage reference of the regulator, and VTRACK is 0.6V. Since RTB is equal to the 60.4k
top feedback resistor of the slave regulator in equal slew
rate or coincident tracking, then RTA is equal to RFB with
VFB = VTRACK. Therefore RTB = 60.4k, and RTA = 60.4k in
Figure 6.
In ratiometric tracking, a different slew rate maybe desired
for the slave regulator. RTB can be solved for when SR
is slower than MR. Make sure that the slave supply slew
rate is chosen to be fast enough so that the slave output
voltage will reach it final value before the master output.
For example, MR = 1.5V/1ms, and SR = 1.2V/1ms. Then
RTB = 76.8k. Solve for RTA to equal to 49.9k.
Each of the TRACK pins will have the 1.3µA current source
on when a resistive divider is used to implement tracking
on that specific channel. This will impose an offset on the
TRACK pin input. Smaller values resistors with the same
ratios as the resistor values calculated from the above
equation can be used. For example, where the 60.4k is
used then a 6.04k can be used to reduce the TRACK pin
offset to a negligible value.
Power Good
The PGOOD pins are open drain pins that can be used to
monitor valid output voltage regulation. This pin monitors
a 10% window around the regulation point. A resistor can
be pulled up to a particular supply voltage no greater than
6V maximum for monitoring.
Stability Compensation
The module has already been internally compensated
for all output voltages. Table 6 is provided for most application requirements. The Linear Technology µModule
Power Design Tool will be provided for other control loop
optimization.
Run Enable
The RUN pins have an enable threshold of 1.4V maximum,
typically 1.25V with 150mV of hysteresis. They control the
turn on each of the channels and INTVCC. These pins can be
pulled up to VIN for 5V operation, or a 5V Zener diode can be
placed on the pins and a 10k to 100k resistor can be placed
up to higher than 5V input for enabling the channels. The
RUN pins can also be used for output voltage sequencing.
In parallel operation the RUN pins can be tie together and
controlled from a single control. See the Typical Application circuits in Figure 31.
INTVCC and EXTVCC
The LTM4630A module has an internal 5V low dropout
regulator that is derived from the input voltage. This regulator is used to power the control circuitry and the power
MOSFET drivers. This regulator can source up to 70mA,
and typically uses ~30mA for powering the device at the
maximum frequency. This internal 5V supply is enabled
by either RUN1 or RUN2.
EXTVCC allows an external 5V supply to power the LTM4630A
and reduce power dissipation from the internal low dropout
5V regulator. The power loss savings can be calculated by:
(VIN – 5V) • 30mA = PLOSS
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LTM4630A
Applications Information
EXTVCC has a threshold of 4.7V for activation, and a
maximum rating of 6V. When using a 5V input, connect
this 5V input to EXTVCC also to maintain a 5V gate drive
level. EXTVCC must sequence on after VIN, and EXTVCC
must sequence off before VIN.
Differential Remote Sense Amplifier
An accurate differential remote sense amplifier is provided
to sense low output voltages accurately at the remote
load points. This is especially true for high current loads.
The amplifier can be used on one of the two channels, or
on a single parallel output. It is very important that the
DIFFP and DIFFN are connected properly at the output,
and DIFFOUT is connected to either VOUTS1 or VOUTS2.
In parallel operation, the DIFFP and DIFFN are connected
properly at the output, and DIFFOUT is connected to
one of the VOUTS pins. Review the parallel schematics in
Figure 32 and review Figure 2. The diffamp can only be
used for output voltage ≤ 3.3V.
SW Pins
The SW pins are generally for testing purposes by monitoring these pins. These pins can also be used to dampen
out switch node ringing caused by LC parasitic in the
switched current paths. Usually a series R-C combination is used called a snubber circuit. The resistor will
dampen the resonance and the capacitor is chosen to
only affect the high frequency ringing across the resistor.
If the stray inductance or capacitance can be measured or
approximated then a somewhat analytical technique can
be used to select the snubber values. The inductance is
usually easier to predict. It combines the power path board
inductance in combination with the MOSFET interconnect
bond wire inductance.
First the SW pin can be monitored with a wide bandwidth
scope with a high frequency scope probe. The ring frequency can be measured for its value. The impedance Z
can be calculated:
ZL = 2πfL,
where f is the resonant frequency of the ring, and L is the
total parasitic inductance in the switch path. If a resistor
is selected that is equal to Z, then the ringing should be
dampened. The snubber capacitor value is chosen so that
18
its impedance is equal to the resistor at the ring frequency.
Calculated by: ZC = 1/(2πfC). These values are a good place to
start with. Modification to these components should be made
to attenuate the ringing with the least amount of power loss.
Temperature Monitoring
A diode connected PNP transistor is used for the TEMP
monitor function by monitoring its voltage over temperature. The temperature dependence of this diode voltage
can be understood in the equation:
I 
VD =nVT ln  D 
 IS 
where VT is the thermal voltage (kT/q), and n, the ideality
factor, is 1 for the diode connected PNP transistor being
used in the LTM4630A. IS is expressed by the typical
empirical equation:
 –V 
IS =I0 exp  G0 
 VT 
where I0 is a process and geometry dependent current, (I0
is typically around 20k orders of magnitude larger than IS
at room temperature) and VG0 is the band gap voltage of
1.2V extrapolated to absolute zero or –273°C.
If we take the IS equation and substitute into the VD equation, then we get:
⎛ kT ⎞ ⎛ I ⎞
kT
VD = VG0 – ⎜ ⎟ ln ⎜ 0 ⎟ , VT =
⎝ q ⎠ ⎝ ID ⎠
q
The expression shows that the diode voltage decreases
(linearly if I0 were constant) with increasing temperature
and constant diode current. Figure 8 shows a plot of VD
vs Temperature over the operating temperature range of
the LTM4630A.
If we take this equation and differentiate it with respect to
temperature T, then:
V –V
dVD
= – G0 D
T
dT
This dVD/dT term is the temperature coefficient equal to
about –2mV/K or –2mV/°C. The equation is simplified for
the first order derivation.
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Solving for T, T = –(VG0 – VD)/(dVD/dT) provides the
temperature.
1st Example: Figure 8 for 27°C, or 300K the diode
voltage is 0.598V, thus, 300K = –(1200mV – 598mV)/
–2.0 mV/K)
2nd Example: Figure 8 for 75°C, or 350K the diode
voltage is 0.50V, thus, 350K = –(1200mV – 500mV)/
–2.0mV/K)
Converting the Kelvin scale to Celsius is simply taking the
Kelvin temp and subtracting 273 from it.
A typical forward voltage is given in the electrical characteristics section of the data sheet, and Figure 8 is the plot
of this forward voltage. Measure this forward voltage at
27°C to establish a reference point. Then using the above
expression while measuring the forward voltage over
temperature will provide a general temperature monitor.
Connect a resistor between TEMP and VIN to set the current to 100µA. See Figure 32 for an example.
0.8
ID = 100µA
DIODE VOLTAGE (V)
0.7
0.6
0.5
0.4
0.3
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
125
4630A F08
Figure 8. Diode Voltage VD vs Temperature T(K)
for Different Bias Currents
Thermal Considerations and Output Current Derating
The thermal resistances reported in the Pin Configuration
section of the data sheet are consistent with those parameters defined by JESD51-9 and are intended for use with
finite element analysis (FEA) software modeling tools that
leverage the outcome of thermal modeling, simulation, and
correlation to hardware evaluation performed on a µModule
package mounted to a hardware test board—also defined
by JESD51-9 (“Test Boards for Area Array Surface Mount
Package Thermal Measurements”). The motivation for
providing these thermal coefficients is found in JESD51-12
(“Guidelines for Reporting and Using Electronic Package
Thermal Information”).
Many designers may opt to use laboratory equipment
and a test vehicle such as the demo board to anticipate
the µModule regulator’s thermal performance in their application at various electrical and environmental operating
conditions to compliment any FEA activities. Without FEA
software, the thermal resistances reported in the Pin Configuration section are in-and-of themselves not relevant to
providing guidance of thermal performance; instead, the
derating curves provided in the data sheet can be used in
a manner that yields insight and guidance pertaining to
one’s application-usage, and can be adapted to correlate
thermal performance to one’s own application.
The Pin Configuration section typically gives four thermal
coefficients explicitly defined in JESD51-12; these coefficients are quoted or paraphrased below:
1.θJA, the thermal resistance from junction to ambient, is
the natural convection junction-to-ambient air thermal
resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as
“still air” although natural convection causes the air to
move. This value is determined with the part mounted
to a JESD51-9 defined test board, which does not reflect
an actual application or viable operating condition.
2.θJCbottom, the thermal resistance from junction to the
bottom of the product case, is the junction-to-board
thermal resistance with all of the component power
dissipation flowing through the bottom of the package.
In the typical µModule, the bulk of the heat flows out
the bottom of the package, but there is always heat
flow out into the ambient environment. As a result, this
thermal resistance value may be useful for comparing
packages but the test conditions don’t generally match
the user’s application.
3.θJCTOP, the thermal resistance from junction to top of
the product case, is determined with nearly all of the
component power dissipation flowing through the top
of the package. As the electrical connections of the
typical µModule are on the bottom of the package, it
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LTM4630A
Applications Information
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
As in the case of θJCBOTTOM, this value may be useful
for comparing packages but the test conditions don’t
generally match the user’s application.
4.θJB, the thermal resistance from junction to the printed
circuit board, is the junction-to-board thermal resistance
where almost all of the heat flows through the bottom of
the µModule and into the board, and is really the sum of
the θJCbottom and the thermal resistance of the bottom
of the part through the solder joints and through a portion of the board. The board temperature is measured a
specified distance from the package, using a two sided,
two layer board. This board is described in JESD51-9.
A graphical representation of the aforementioned thermal resistances is given in Figure 9; blue resistances are
contained within the µModule regulator, whereas green
resistances are external to the µModule.
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD51-12 or provided in the Pin
Configuration section replicates or conveys normal operating conditions of a µModule. For example, in normal
board-mounted applications, never does 100% of the
device’s total power loss (heat) thermally conduct exclusively through the top or exclusively through bottom of the
µModule—as the standard defines for θJCtop and θJCbottom,
respectively. In practice, power loss is thermally dissipated
in both directions away from the package—granted, in the
absence of a heat sink and airflow, a majority of the heat
flow is into the board.
Within a SIP (system-in-package) module, be aware there
are multiple power devices and components dissipating
power, with a consequence that the thermal resistances
relative to different junctions of components or die are not
exactly linear with respect to total package power loss. To
reconcile this complication without sacrificing modeling
simplicity—but also, not ignoring practical realities—an
approach has been taken using FEA software modeling
along with laboratory testing in a controlled-environment
chamber to reasonably define and correlate the thermal
resistance values supplied in this data sheet: (1) Initially,
FEA software is used to accurately build the mechanical
geometry of the µModule and the specified PCB with all
of the correct material coefficients along with accurate
power loss source definitions; (2) this model simulates
a software-defined JEDEC environment consistent with
JESD51-9 to predict power loss heat flow and temperature
readings at different interfaces that enable the calculation of
the JEDEC-defined thermal resistance values; (3) the model
and FEA software is used to evaluate the µModule with
heat sink and airflow; (4) having solved for and analyzed
these thermal resistance values and simulated various
operating conditions in the software model, a thorough
laboratory evaluation replicates the simulated conditions
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
JUNCTION-TO-CASE (TOP)
RESISTANCE
JUNCTION
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION-TO-CASE
CASE (BOTTOM)-TO-BOARD
(BOTTOM) RESISTANCE
RESISTANCE
AMBIENT
BOARD-TO-AMBIENT
RESISTANCE
4630A F09
µMODULE DEVICE
Figure 9. Graphical Representation of JESD51-12 Thermal Coefficients
20
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with thermocouples within a controlled-environment
chamber while operating the device at the same power loss
as that which was simulated. An outcome of this process
and due-diligence yields a set of derating curves provided
in other sections of this data sheet. After these laboratory
test have been performed and correlated to the µModule
model, then the θJB and θBA are summed together to correlate quite well with the µModule model with no airflow or
heat sinking in a properly define chamber. This θJB + θBA
value is shown in the Pin Configuration section and should
accurately equal the θJA value because approximately
100% of power loss flows from the junction through the
board into ambient with no airflow or top mounted heat
sink. Each system has its own thermal characteristics,
therefore thermal analysis must be performed by the user
in a particular system.
The LTM4630A module has been designed to effectively
remove heat from both the top and bottom of the package. The bottom substrate material has very low thermal
resistance to the printed circuit board. An external heat
sink can be applied to the top of the device for excellent
heat sinking with airflow.
Figures 10 and 11 show temperature plots of the LTM4630A
with no heat sink and 200LFM airflow.
These plots equate to a paralleled 12V to 1.0V at 36A
design operating at 84.5% efficiency, and 12V to 3.3V at
36A design operating at 92.5% efficiency.
Safety Considerations
The LTM4630A modules do not provide isolation from
VIN to VOUT. There is no internal fuse. If required, a slow
blow fuse with a rating twice the maximum input current
needs to be provided to protect each unit from catastrophic
failure. The device does support over current protection.
A temperature diode is provided for monitoring internal
temperature, and can be used to detect the need for thermal
shutdown that can be done by controlling the RUN pin.
Power Derating
The 1.0V, 1.8V, 3.3V and 5V power loss curves in Figures
13 to 16 can be used in coordination with the load current
derating curves in Figures 17 to 30 for calculating an approximate ΘJA thermal resistance for the LTM4630A with
various heat sinking and airflow conditions. The power loss
curves are taken at room temperature, and are increased
with a 1.35 to 1.4 multiplicative factor at 125°C. These
factors come from the fact that the power loss of the
regulator increases about 45% from 25°C to 150°C, thus
a 50% spread over 125°C delta equates to ~0.35%/°C loss
increase. A 125°C maximum junction minus 25°C room
temperature equates to a 100°C increase. This 100°C
increase multiplied by 0.35%/°C equals a 35% power loss
increase at the 125°C junction, thus the 1.35 multiplier.
The derating curves are plotted with CH1 and CH2 in parallel
single output operation starting at 36A of load with low
ambient temperature. The output voltages are 1.0V, 1.8V,
3.3V and 5V. These are chosen to include the lower and
higher output voltage ranges for correlating the thermal
resistance. Thermal models are derived from several
temperature measurements in a controlled temperature
chamber along with thermal modeling analysis.
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LTM4630A
Applications Information
Figure 10. Thermal Image 12V to 1.0V,
36A with 200LFM without Heat Sink
Figure 11. Thermal Image 12V to 3.3V,
36A with 200LFM without Heat Sink
22
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The junction temperatures are monitored while ambient
temperature is increased with and without airflow. The
power loss increase with ambient temperature change
is factored into the derating curves. The junctions are
maintained at ~120°C maximum while lowering output
current or power while increasing ambient temperature.
The decreased output current will decrease the internal
module loss as ambient temperature is increased.
The monitored junction temperature of 120°C minus
the ambient operating temperature specifies how much
module temperature rise can be allowed. As an example in
Figure 17, the load current is derated to ~25A at ~81°C with
no air or heat sink and the power loss for the 12V to 1.0V
at 25A output is a ~4.8W loss. The 5.5W loss is calculated
with the ~3.6W room temperature loss from the 12V to
1.0V power loss curve at 25A, and the 1.35 multiplying
factor at 125°C ambient. If the 81°C ambient temperature
is subtracted from the 120°C junction temperature, then
the difference of 39°C divided 4.8W equals a 8.2°C/W
ΘJA thermal resistance. Table 2 specifies a 8.5°C/W value
which is pretty close. The airflow graphs are more accurate
due to the fact that the ambient temperature environment
is controlled better with airflow. Tables 2 to 5 provide
equivalent thermal resistances for 1.0V to 5V outputs with
and without airflow and heat sinking.
The derived thermal resistances in Tables 2 to 5 for the
various conditions can be multiplied by the calculated
power loss as a function of ambient temperature to derive
temperature rise above ambient, thus maximum junction
temperature. Room temperature power loss can be derived
from the efficiency curves and adjusted with the above
ambient temperature multiplicative factors. The printed
circuit board is a 1.6mm thick four layer board with two
ounce copper for the two outer layers and one ounce
copper for the two inner layers. The PCB dimensions are
101mm × 114mm. The heat sinks are listed in Table 3.
Layout Checklist/Example
The high integration of LTM4630A makes the PCB board
layout very simple and easy. However, to optimize its
electrical and thermal performance, some layout considerations are still necessary.
• Use large PCB copper areas for high current paths,
including VIN, GND, VOUT1 and VOUT2. It helps to minimize the PCB conduction loss and thermal stress.
• Place high frequency ceramic input and output capacitors next to the VIN, PGND and VOUT pins to minimize
high frequency noise.
• Place a dedicated power ground layer underneath the
unit.
• To minimize the via conduction loss and reduce module
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
• Do not put via directly on the pad, unless they are
capped or plated over.
• Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND
to GND underneath the unit.
• For parallel modules, tie the VOUT, VFB, and COMP pins
together. Use an internal layer to closely connect these
pins together. The TRACK pin can be tied a common
capacitor for regulator soft-start.
• Bring out test points on the signal pins for monitoring.
Figure 12 gives a good example of the recommended layout.
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LTM4630A
Applications Information
CIN1
CIN2
VIN
M
L
K
GND
GND
J
H
G
COUT1
SGND
F
COUT2
E
D
C
B
A
1
2
3
4
5
VOUT1
6
7
8
9
10
11
GND
12
VOUT2
4630A F12
CNTRL
CNTRL
Figure 12. Recommended PCB Layout
Table 2. 1.0V Output
DERATING CURVE
Figures 17, 18
Figures 17, 18
Figures 17, 18
Figures 19, 20
Figures 19, 20
Figures 19, 20
VIN (V)
5, 12
5, 12
5, 12
5, 12
5, 12
5, 12
POWER LOSS CURVE
Figure 13
Figure 13
Figure 13
Figure 13
Figure 13
Figure 13
AIRFLOW (LFM)
0
200
400
0
200
400
HEAT SINK
None
None
None
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
θJA (°C/W)
8.5
7
6
8
6
5
VIN (V)
5, 12
5, 12
5, 12
5, 12
5, 12
5, 12
POWER LOSS CURVE
Figure 14
Figure 14
Figure 14
Figure 14
Figure 14
Figure 14
AIRFLOW (LFM)
0
200
400
0
200
400
HEAT SINK
None
None
None
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
θJA (°C/W)
8.5
7
6
8
6
5
Table 3. 1.8V Output
DERATING CURVE
Figures 21, 22
Figures 21, 22
Figures 21, 22
Figures 23, 24
Figures 23, 24
Figures 23, 24
24
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Table 4. 3.3V Output
VIN (V)
5, 12
5, 12
5, 12
5, 12
5, 12
5, 12
POWER LOSS CURVE
Figure 15
Figure 15
Figure 15
Figure 15
Figure 15
Figure 15
AIRFLOW (LFM)
0
200
400
0
200
400
HEAT SINK
None
None
None
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
θJA (°C/W)
8.5
7
6
8
6
5
VIN (V)
12
12
12
12
12
12
POWER LOSS CURVE
Figure 16
Figure 16
Figure 16
Figure 16
Figure 16
Figure 16
AIRFLOW (LFM)
0
200
400
0
200
400
HEAT SINK
None
None
None
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
θJA (°C/W)
8.5
7
6
8
6
5
DERATING CURVE
Figures 25, 26
Figures 25, 26
Figures 25, 26
Figures 27, 28
Figures 27, 28
Figures 27, 28
Table 5. 5V Output
DERATING CURVE
Figures 29
Figures 29
Figures 29
Figures 30
Figures 30
Figures 30
HEAT SINK MANUFACTURER
PART NUMBER
WEBSITE
Aavid Thermalloy
375424B00034G
www.aavid.com
Table 6. Dual Channel Single Output Voltage Response vs Component Matrix (Refer to Figure 32, 0A to 9A, ±25% Load Step Typical
Measured Values)
CIN (BULK)*
PART NUMBER
SUN Electronic 25CE150AX
Panasonic
EEH-ZC1E101XP
VALUE
150µF, 25V
100µF, 25V
CIN (CERAMIC)
Murata
Taiyo Yuden
Murata
PART NUMBER
GRM219R61C226ME15L
EMK212BBJ226MG-T
GRM31CR61E226KE15L
VALUE
22µF, 16V, 0805, X5R
22µF, 16V, 0805, X5R
22µF, 25V, 1206, X5R
Taiyo Yuden
TMK316BBJ226ML-T
22µF, 25V, 1206, X5R
COUT (BULK)
PART NUMBER
VALUE
COUT (CERAMIC)
PART NUMBER
VALUE
Panasonic
6TPF220M5L
220µF, POSCAP, 6.3V, 5mΩ ESR
Murata
GRM31CR60J107ME39L
100µF, 6.3V, 1206, X5R
Panasonic
6TPF330M5EL
330µF, POSCAP, 6.3V, 5mΩ ESR
Murata
GRM31CR60G227ME11#
220µF, 4V, 1206, X5R
Panasonic
6TPE470MI
470µF, POSCAP, 6.3V, 18mΩ ESR Taiyo Yuden
JMK316BJ107ML-T
100µF, 6.3V, 1206, X5R
Panasonic
4TPF470M5EL
470µF, POSCAP, 4V, 5mΩ ESR
JMK325ABJ227MM-T
220µF, 6.3V, 1210, X5R
Taiyo Yuden
P-P
RECOVERY
COUT
CFF
VIN
DROOP DEVIATION TIME
CIN
COUT
(pF)
(V)
(mV)
VOUT (V) (CERAMIC) CIN (BULK) (CERAMIC) (BULK)
(mV)
(µs)
1
150µF 100µF × 4 220µF × 2
N/A
5, 12
0
68
20
22µF × 4
1.2
150µF 100µF × 4 220µF × 2
N/A
5, 12
0
74
20
22µF × 4
1.5
150µF 100µF × 4 220µF × 2
N/A
5, 12
0
72
20
22µF × 4
1.8
150µF 100µF × 4 220µF × 2
N/A
5, 12
0
76
30
22µF × 4
2.5
150µF 100µF × 4 220µF × 2
N/A
5, 12
0
74
30
22µF × 4
3.3
150µF 100µF × 4 220µF × 2
N/A
5, 12
0
72
30
22µF × 4
5
150µF 100µF × 4 220µF × 2
N/A
5, 12
0
78
40
22µF × 4
*Bulk input capacitor is only needed if the input source impedance is compromised by long inductive leads.
LOAD
STEP
(A)
9
9
9
9
9
9
9
LOAD
STEP
(A/µs)
9
9
9
9
9
9
9
RFB
(kΩ)
90.9
60.4
40.2
30.2
19.1
13.3
8.25
4630af
For more information www.linear.com/LTM4630A
25
LTM4630A
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36
4630A F13
LOAD CURRENT (A)
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
10
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
12VIN
40
35
35
30
30
25
20
15
0LFM
200LFM
400LFM
5
25
20
15
0
30
40
0
30
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C) 4630A F17
Figure 17. 12V to 1V Derating
Curve, No Heat Sink
35
35
30
30
30
15
LOAD CURRENT (A)
35
LOAD CURRENT (A)
40
20
20
15
10
10
0LFM
200LFM
400LFM
5
0
30
40
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C) 4630A F19
Figure 19. 12V to 1V Derating
Curve, BGA Heat Sink
26
40
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C) 4630A F18
Figure 18. 5V to 1V Derating
Curve, No Heat Sink
40
25
0LFM
200LFM
400LFM
5
40
25
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36
4630A F15
LOAD CURRENT (A)
10
10
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36
4630A F16
LOAD CURRENT (A)
12VIN
5VIN
Figure 15. 3.3VOUT Power
Loss Curve
40
Figure 16. 5VOUT Power Loss
Curve
LOAD CURRENT (A)
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36
4630A F14
LOAD CURRENT (A)
10
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
Figure 14. 1.8VOUT Power Loss
Curve
LOAD CURRENT (A)
POWER LOSS (W)
Figure 13. 1.0VOUT Power Loss
Curve
12VIN
5VIN
POWER LOSS (W)
12VIN
5VIN
LOAD CURRENT (A)
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
POWER LOSS (W)
POWER LOSS (W)
Applications Information
25
20
15
10
0LFM
200LFM
400LFM
5
0
30
40
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C) 4630A F20
Figure 20. 5V to 1V Derating
Curve, BGA Heat Sink
0LFM
200LFM
400LFM
5
0
30
40
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C) 4630A F21
Figure 21. 12V to 1.8V
Derating Curve, No Heat Sink
4630af
For more information www.linear.com/LTM4630A
LTM4630A
40
40
35
35
35
30
30
30
25
20
15
10
5
25
20
15
10
0LFM
200LFM
400LFM
5
0
30 40 50 60 70 80 90 100 110 120 130
AMBIENT TEMPERATURE (°C) 4630A F22
20
15
5
Figure 24. 5V to 1.8V Derating
Curve, BGA Heat Sink
40
40
35
35
35
30
30
30
20
15
10
5
LOAD CURRENT (A)
40
25
25
20
15
10
0LFM
200LFM
400LFM
5
0
30 40 50 60 70 80 90 100 110 120 130
AMBIENT TEMPERATURE (°C) 4630A F25
25
20
15
10
0LFM
200LFM
400LFM
5
0
30 40 50 60 70 80 90 100 110 120 130
AMBIENT TEMPERATURE (°C) 4630A F26
Figure 25. 12V to 3.3V Derating
Curve, No Heat Sink
Figure 26. 5V to 3.3V Derating
Curve, No Heat Sink
Figure 27. 12V to 3.3V Derating
Curve, BGA Heat Sink
35
35
35
30
30
30
20
15
20
15
10
10
5
LOAD CURRENT (A)
40
LOAD CURRENT (A)
40
25
0LFM
200LFM
400LFM
0
30 40 50 60 70 80 90 100 110 120 130
AMBIENT TEMPERATURE (°C) 4630A F28
Figure 28. 5V to 3.3V Derating
Curve, BGA Heat Sink
5
0LFM
200LFM
400LFM
0
30 40 50 60 70 80 90 100 110 120 130
AMBIENT TEMPERATURE (°C) 4630A F27
40
25
0LFM
200LFM
400LFM
0
30 40 50 60 70 80 90 100 110 120 130
AMBIENT TEMPERATURE (°C) 4630A F24
Figure 23. 12V to 1.8V Derating
Curve, BGA Heat Sink
LOAD CURRENT (A)
LOAD CURRENT (A)
25
10
0LFM
200LFM
400LFM
0
30 40 50 60 70 80 90 100 110 120 130
AMBIENT TEMPERATURE (°C) 4630A F23
Figure 22. 5V to 1.8V Derating
Curve, No Heat Sink
LOAD CURRENT (A)
LOAD CURRENT (A)
40
LOAD CURRENT (A)
LOAD CURRENT (A)
Applications Information
25
20
15
10
0LFM
200LFM
400LFM
0
30 40 50 60 70 80 90 100 110 120 130
AMBIENT TEMPERATURE (°C) 4630A F29
Figure 29. 12V to 5V Derating
Curve, No Heat Sink
5
0LFM
200LFM
400LFM
0
30 40 50 60 70 80 90 100 110 120 130
AMBIENT TEMPERATURE (°C) 4630A F30
Figure 30. 12V to 5V Derating
Curve, BGA Heat Sink
4630af
For more information www.linear.com/LTM4630A
27
VIN
4.5V TO 15V
+
CIN
(OPT)
28
For more information www.linear.com/LTM4630A
C3
22µF
25V
*SEE TABLE 6
C4
22µF
25V
C9
0.1µF
TRACK2
C1
22µF
25V
R4
75k
R7
100k
SGND
DIFFP
VOUTS2
PHASMD
PGOOD2
DIFFOUT
SW2
VOUT2
COMP2
fSET
DIFFN
VFB2
TRACK1
GND
VFB1
RUN2
COMP1
SW1
RUN1
LTM4630A
VOUTS1
TEMP
TRACK2
VOUT1
EXTVCC PGOOD1
VIN
MODE_PLLIN CLKOUT INTVCC
R2
10k
INTVCC
INTVCC
R3
10k
PGOOD2
CCOMP*
PGOOD1
Figure 31. Typical 4.5VIN to 15VIN, 300kHz, 1.0V and 1.2V at 18A Outputs
C5
0.1µF
TRACK1
C2
22µF
25V
4.5V TO 15V INTERMEDIATE BUS
C10
4.7µF
COUT1
100µF
6.3V
RFB2
60.4k
+
RFB1
90.9k
CFF*
CBOT*
+
COUT2
470µF
6.3V
VOUT1
1.0V AT 18A
COUT2
470µF
6.3V
4630A F31
VOUT2
1.2V AT 18A
COUT1
100µF
6.3V
LTM4630A
Applications Information
4630af
VIN
4.5V TO 15V
C3
22µF
25V
For more information www.linear.com/LTM4630A
C2
22µF
25V
C9
0.1µF
R4
140k
C1
22µF
25V
RT
VIN
VIN
100µA
R2
10k
SGND
PHASMD
fSET
TRACK2
TRACK1
RUN1
RUN2
GND
DIFFP
LTM4630A
DIFFN
DIFFOUT
PGOOD2
SW2
VOUT2
VOUTS2
COMP2
COMP1
VFB2
VFB1
SW1
VOUT1
VOUTS1
EXTVCC PGOOD1
C10
4.7µF
INTVCC
TEMP
CLKOUT INTVCC
INTVCC
VIN
MODE_PLLIN
RT =
PGOOD1
R5
13.3k
PGOOD1
Figure 32. LTM4630A 2-Phase, 600kHz, 3.3V at 28A Design with Temperature Monitoring
TRACK1
C11
22µF
25V
4.5V TO 15V INTERMEDIATE BUS
A/D
µC
COUT1
100µF
6.3V
COUT1
100µF
6.3V
+
+
4630A F32
COUT2
470µF
6.3V
COUT2
470µF
6.3V
VOUT
3.3V
28A
LTM4630A
typical Applications
4630af
29
30
VIN
4.5V TO 15V
C4
22µF
25V
C3
22µF
25V
C5
0.1µF
For more information www.linear.com/LTM4630A
R7
19.1k
C1
22µF
25V
R4
140k
R6
100k
SGND
DIFFN
VOUTS2
DIFFOUT
PGOOD2
SW2
VOUT2
COMP2
fSET
PHASMD
DIFFP
VFB2
TRACK1
GND
VFB1
RUN2
COMP1
SW1
RUN1
LTM4630A
VOUTS1
TEMP
TRACK2
VOUT1
VIN
R8
19.1k
PGOOD1
INTVCC
R3
10k
PGOOD2
Figure 33. LTM4630A 3.3V and 2.5V Output with Tracking Function
VOUT1
3.3V
R9
60.4k
C2
22µF
25V
4.5V TO 15V INTERMEDIATE BUS
R2
10k
INTVCC
MODE_PLLIN CLKOUT INTVCC EXTVCC PGOOD1
C10
4.7µF
COUT1
100µF
6.3V
R5
13.3k
COUT1
100µF
6.3V
+
+
4630A F33
COUT2
470µF
6.3V
VOUT2
2.5V AT 15A
VOUT1
3.3V
COUT2 15A
470µF
6.3V
LTM4630A
typical Applications
4630af
LTM4630A
typical applications
INTVCC
C10
4.7µF
CLK1
VIN
4.5V TO 15V
PGOOD
MODE_PLLIN CLKOUT INTVCC
C3
22µF
25V
RUN
C2
22µF
25V
C1
22µF
25V
R2
5k
EXTVCC PGOOD1
VIN
R6
100k
TRACK
VOUT1
TEMP
VOUTS1
RUN1
RUN2
SW1
VFB1
TRACK1
VFB2
LTM4630A
TRACK2
COMP2
PHASMD
VOUTS2
SGND
GND
DIFFP
DIFFN
COUT1
100µF
6.3V
+
COUT2
470µF
6.3V
COMP
SW2
PGOOD2
COUT2
470µF
6.3V
R5
60.4k
VOUT2
R4
75k
+
VFB
COMP1
fSET
COUT1
100µF
6.3V
PGOOD
DIFFOUT
VOUT
1.2V
70A
C16
4.7µF
CLK1
MODE_PLLIN CLKOUT INTVCC
C12
22µF
25V
C15
22µF
25V
C5
22µF
25V
R9
100k
PGOOD
EXTVCC PGOOD1
VOUT1
VIN
RUN1
TRACK
TEMP
VOUTS1
RUN1
SW1
RUN2
VFB1
TRACK1
VFB2
LTM4630A
TRACK2
C19
0.22µF
COMP2
PHASMD
VOUTS2
SW2
PGOOD2
SGND
GND
DIFFP
DIFFN
COUT2
470µF
6.3V
COUT1
100µF
6.3V
+
COUT2
470µF
6.3V
COMP
VOUT2
R10
75k
+
VFB
COMP1
fSET
COUT1
100µF
6.3V
PGOOD
DIFFOUT
4630A F34
INTVCC
Figure 34. LTM4630A 4-Phase, 1.2V at 70A Output Design
4630af
For more information www.linear.com/LTM4630A
31
LTM4630A
package description
LTM4630A Component LGA Pinout
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
A1
VOUT1
B1
VOUT1
C1
VOUT1
D1
GND
E1
GND
F1
GND
A2
VOUT1
B2
VOUT1
C2
VOUT1
D2
GND
E2
GND
F2
GND
A3
VOUT1
B3
VOUT1
C3
VOUT1
D3
GND
E3
GND
F3
GND
A4
VOUT1
B4
VOUT1
C4
VOUT1
D4
GND
E4
GND
F4
MODE_PLLIN
A5
VOUT1
B5
VOUT1
C5
VOUT1S
D5
VFB1
E5
TRACK1
F5
RUN1
A6
GND
B6
GND
C6
fSET
D6
SGND
E6
COMP1
F6
SGND
A7
GND
B7
GND
C7
SGND
D7
VFB2
E7
COMP2
F7
SGND
A8
VOUT2
B8
VOUT2
C8
VOUT2S
D8
TRACK2
E8
DIFFP
F8
DIFFOUT
A9
VOUT2
B9
VOUT2
C9
VOUT2
D9
GND
E9
DIFFN
F9
RUN2
A10
VOUT2
B10
VOUT2
C10
VOUT2
D10
GND
E10
GND
F10
GND
A11
VOUT2
B11
VOUT2
C11
VOUT2
D11
GND
E11
GND
F11
GND
A12
VOUT2
B12
VOUT2
C12
VOUT2
D12
GND
E12
GND
F12
GND
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
G1
GND
H1
GND
J1
GND
K1
GND
L1
GND
M1
GND
G2
SW1
H2
GND
J2
VIN
K2
VIN
L2
VIN
M2
VIN
G3
GND
H3
GND
J3
VIN
K3
VIN
L3
VIN
M3
VIN
G4
PHASEMD
H4
GND
J4
VIN
K4
VIN
L4
VIN
M4
VIN
G5
CLKOUT
H5
GND
J5
GND
K5
GND
L5
VIN
M5
VIN
G6
SGND
H6
GND
J6
TEMP
K6
GND
L6
VIN
M6
VIN
G7
SGND
H7
GND
J7
EXTVCC
K7
GND
L7
VIN
M7
VIN
G8
PGOOD2
H8
INTVCC
J8
GND
K8
GND
L8
VIN
M8
VIN
G9
PGOOD1
H9
GND
J9
VIN
K9
VIN
L9
VIN
M9
VIN
G10
GND
H10
GND
J10
VIN
K10
VIN
L10
VIN
M10
VIN
G11
SW2
H11
GND
J11
VIN
K11
VIN
L11
VIN
M11
VIN
G12
GND
H12
GND
J12
GND
K12
GND
L12
GND
M12
GND
32
4630af
For more information www.linear.com/LTM4630A
aaa Z
0.630 ±0.025 SQ. 143x
3.1750
3.1750
SUGGESTED PCB LAYOUT
TOP VIEW
1.9050
PACKAGE TOP VIEW
E
0.6350
0.0000
0.6350
4
1.9050
PAD “A1”
CORNER
6.9850
5.7150
4.4450
4.4450
5.7150
6.9850
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representaFor more
www.linear.com/LTM4630A
tion that the interconnection
of itsinformation
circuits as described
herein will not infringe on existing patent rights.
6.9850
5.7150
4.4450
3.1750
1.9050
0.6350
0.0000
0.6350
1.9050
3.1750
4.4450
5.7150
6.9850
Y
X
D
aaa Z
// bbb Z
0.36
3.95
MIN
4.31
0.60
NOM
4.41
0.63
16.0
16.0
1.27
13.97
13.97
0.41
4.00
DIMENSIONS
Ø eee S Z X Y
H1
SUBSTRATE
0.46
4.05
0.15
0.10
0.05
MAX
4.51
0.66
DETAIL B
A
TOTAL NUMBER OF LGA PADS: 144
SYMBOL
A
b
D
E
e
F
G
H1
H2
aaa
bbb
eee
DETAIL A
0.630 ±0.025 SQ. 143x
DETAIL B
H2
MOLD
CAP
Z
NOTES
(Reference LTC DWG # 05-08-1901 Rev B)
LGA Package
144-Lead (16mm × 16mm × 4.41mm)
e
L
b
K
J
G
G
F
E
e
PACKAGE BOTTOM VIEW
H
D
C
B
A
DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
4
TRAY PIN 1
BEVEL
COMPONENT
PIN “A1”
7
!
12
11
10
9
8
7
6
5
4
3
2
1
PACKAGE IN TRAY LOADING ORIENTATION
LTMXXXXXX
µModule
3
SEE NOTES
DIA 0.630
PAD 1
7
SEE NOTES
LGA 144 0213 REV B
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
6. THE TOTAL NUMBER OF PADS: 144
5. PRIMARY DATUM -Z- IS SEATING PLANE
LAND DESIGNATION PER JESD MO-222, SPP-010
3
2. ALL DIMENSIONS ARE IN MILLIMETERS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
3x, C (0.22 x45°)
F
b
M
DETAIL A
LTM4630A
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
4630af
33
LTM4630A
Package PHoto
LGA
Design Resources
SUBJECT
DESCRIPTION
µModule Design and Manufacturing Resources
Design:
• Selector Guides
• Demo Boards and Gerber Files
• Free Simulation Tools
µModule Regulator Products Search
1. Sort table of products by parameters and download the result as a spread sheet.
Manufacturing:
• Quick Start Guide
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability
2. Search using the Quick Power Search parametric table.
TechClip Videos
Quick videos detailing how to bench test electrical and thermal performance of µModule products.
Digital Power System Management
Linear Technology’s family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
LTM4620A
Dual 13A, Single 26A, Pin-Compatible with the LTM4630A 4.5V ≤ VIN ≤ 16V, 0.6V ≤ VOUT ≤ 5.3V, 15mm × 15mm LGA and,
× 5.01mm BGA
LTM4628
Dual 8A, Single 16A, Pin-Compatible with the LTM4630A
4.5V ≤ VIN ≤ 26.5V, 0.6V ≤ VOUT ≤ 5.5V, 15mm × 15mm × 4.32mm LGA
and × 4.92mm BGA
LTM4619
Dual 4A, Single 8A
4.5V ≤ VIN ≤ 26.5V, 0.8V ≤ VOUT ≤ 5V, 15mm × 15mm × 2.82mm LGA
LTM4676
Dual 13A, Single 26A, Programmable with PMBus
Compliant I2C Serial Interface
4.5V ≤ VIN ≤ 26.5V, 0.5V ≤ VOUT1 ≤ 5.4V, 0.5V, VOUT2, 4V, On-Board
EEPROM, 16mm × 16mm × 5.01mm BGA
LTM4644
Quad 4A, Configurable Output Array from Four Outputs
4A Each to One Output 16A
4V ≤ VIN ≤ 14V, 0.6V ≤ VOUT ≤ 5.5V, 9mm × 15mm × 5.01mm BGA
LTM4637
Single 20A
4.5V ≤ VIN ≤ 20V, 0.6V ≤ VOUT ≤ 5.5V, 15mm × 15mm × 4.32mm LGA
and × 4.92mm BGA
LTM4625
Single 5A, Small: <1cm2 Total Solution PCB Area
4V ≤ VIN ≤ 20V, 0.6V ≤ VOUT ≤ 5.5V, 6.25mm × 6.25mm × 5.01mm BGA
LTM4623
Single 3A, Ultrathin 1.82mm, Small
4V ≤ VIN ≤ 20V, 0.6V ≤ VOUT ≤ 5.5V, 6.25mm × 6.25mm × 1.82mm LGA
34 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTM4630A
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTM4630A
4630af
LT 0715 • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2015