SiI8788 Analog Front-end Video Processor with Parallel Video Output

SiI8788 Analog Front-end Video Processor
with Parallel Video Output
Data Sheet
SiI-DS-1123-A
March 2016
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
Contents
1.
General Description ......................................................................................................................................................5
1.1. Features ................................................................................................................................................................5
1.1.1.
Analog (Video) Front-end..............................................................................................................................5
1.1.2.
Multi-format Video Decoder .........................................................................................................................5
1.1.3.
Video Processing ...........................................................................................................................................5
1.1.4.
24-bit Parallel Output ...................................................................................................................................5
1.2. Applications ..........................................................................................................................................................5
1.3. Packaging ..............................................................................................................................................................5
1.4. Temperature Range ..............................................................................................................................................5
2. Product Family ..............................................................................................................................................................6
3. Functional Description ..................................................................................................................................................7
3.1. Analog Front-end ..................................................................................................................................................8
3.1.1.
Input Multiplexer ..........................................................................................................................................8
3.1.2.
Clamp and Offset ..........................................................................................................................................8
3.1.3.
Low Pass Filter...............................................................................................................................................8
3.1.4.
ADC with Programmable Gain Amplifier.......................................................................................................8
3.1.5.
Line Locked PLL .............................................................................................................................................9
3.1.6.
Sync Slicer .....................................................................................................................................................9
3.1.7.
Video Buffer ..................................................................................................................................................9
3.2. Video Decoder ......................................................................................................................................................9
3.2.1.
ADCIF ...........................................................................................................................................................10
3.2.2.
Automatic Gain Control and Offset Calibration ..........................................................................................10
3.2.3.
Antialias Filtering and Decimation ..............................................................................................................10
3.2.4.
Video Decoder ............................................................................................................................................10
3.2.5.
CVBS Processing ..........................................................................................................................................10
3.2.6.
Component Processing ...............................................................................................................................11
3.2.7.
Sync Processor ............................................................................................................................................11
3.2.8.
VBI Decoder ................................................................................................................................................11
3.3. Video Processing .................................................................................................................................................12
3.3.1.
Time Base Corrector ...................................................................................................................................12
3.3.2.
VBI Post Processor ......................................................................................................................................12
3.3.3.
De-interlacer and Edge Smoother...............................................................................................................12
3.3.4.
Color Processing ..........................................................................................................................................12
3.3.5.
Auto Phase Detection .................................................................................................................................13
3.3.6.
Auto Position Calibration ............................................................................................................................13
3.3.7.
Auto Gain Calibration ..................................................................................................................................13
3.4. Video Path ...........................................................................................................................................................13
3.4.1.
Video Data Conversion Logic Block .............................................................................................................13
3.4.2.
Digital Parallel Video Output Interface .......................................................................................................14
3.5. Control Logic .......................................................................................................................................................15
3.5.1.
Internal Microcontroller .............................................................................................................................15
3.5.2.
Registers......................................................................................................................................................17
2
3.5.3.
I C Bus .........................................................................................................................................................17
3.5.4.
Interrupt......................................................................................................................................................18
3.5.5.
GPIOs...........................................................................................................................................................18
4. Electrical Specifications ..............................................................................................................................................19
4.1. Absolute Maximum Ratings ................................................................................................................................19
4.2. Normal Operating Conditions .............................................................................................................................20
4.3. ESD Specifications ...............................................................................................................................................20
4.4. DC Specifications .................................................................................................................................................21
4.5. AC Specifications .................................................................................................................................................22
4.6. Control Signal Timing Specifications ...................................................................................................................23
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2
SiI-DS-1123-A
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
5.
Timing Diagrams ......................................................................................................................................................... 24
2
5.1. I C Bus Timing Diagrams ..................................................................................................................................... 24
5.2. Reset Timing Diagram ......................................................................................................................................... 24
5.3. Digital Video Output Timing Diagrams ............................................................................................................... 25
6. Pin Diagram and Pin Description ................................................................................................................................ 26
6.1. Pin Diagram......................................................................................................................................................... 26
6.2. Pin Descriptions .................................................................................................................................................. 27
6.2.1.
AFE Input/Output Pins ................................................................................................................................ 27
6.2.2.
Configuration and Control Pins ................................................................................................................... 28
6.2.3.
Parallel Video Output Data Pins .................................................................................................................. 29
6.2.4.
SPI Interface Pins ........................................................................................................................................ 30
6.2.5.
Power and Ground Connections ................................................................................................................. 30
6.2.6.
Crystal Pins .................................................................................................................................................. 30
6.2.7.
Reserved Pins .............................................................................................................................................. 31
6.2.8.
Output Pin Mappings .................................................................................................................................. 31
7. Design Guidelines ....................................................................................................................................................... 37
7.1. Power Supplies Decoupling ................................................................................................................................ 37
7.2. ESD Protection .................................................................................................................................................... 38
7.3. EMI Considerations ............................................................................................................................................. 38
7.4. Typical Circuit Connection .................................................................................................................................. 38
8. Packaging .................................................................................................................................................................... 39
8.1. ePad Requirements............................................................................................................................................. 39
8.2. Package Dimensions ........................................................................................................................................... 40
9. Marking Specification ................................................................................................................................................. 41
9.1. Ordering Information .......................................................................................................................................... 41
References .......................................................................................................................................................................... 42
Standards Documents..................................................................................................................................................... 42
Lattice Semiconductor Documents ................................................................................................................................. 42
Revision History .................................................................................................................................................................. 43
Figures
Figure 1.1. Typical Application of the SiI8788 Device ........................................................................................................... 5
Figure 3.1. Functional Block Diagram ................................................................................................................................... 7
Figure 3.2. Clamp and Offset ................................................................................................................................................ 8
Figure 3.3. Sync Slicers.......................................................................................................................................................... 9
Figure 3.4. CVBS Processing Diagram ................................................................................................................................. 10
Figure 3.5. Component Processing Diagram....................................................................................................................... 11
Figure 3.6. Default Video Processing Path .......................................................................................................................... 13
Figure 3.7. External Memory Structure .............................................................................................................................. 16
2
Figure 5.1. I C Data Valid Delay (Driving Read Cycle Data) ................................................................................................. 24
Figure 5.2. Conditions for Use of RESET_N ......................................................................................................................... 24
Figure 5.3. RESET_N Minimum Timings .............................................................................................................................. 24
Figure 5.4. Video Digital Output Transition Times .............................................................................................................. 25
Figure 5.5. Clock-to-Output Delay and Duty Cycle Limits ................................................................................................... 25
Figure 6.1. Pin Diagram....................................................................................................................................................... 26
Figure 7.1. Decoupling and Bypass Schematic .................................................................................................................... 37
Figure 7.2. Decoupling and Bypass Capacitor Placement ................................................................................................... 37
Figure 7.3. Typical Circuit Schematic .................................................................................................................................. 38
Figure 8.1. 88-Pin QFN Package Diagram ........................................................................................................................... 40
Figure 9.1. Marking Diagram .............................................................................................................................................. 41
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1123-A
3
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
Tables
Table 2.1. Product Selection Guide.......................................................................................................................................6
Table 3.1. Supported Standards..........................................................................................................................................12
Table 3.2. Typical Digital Video Output Formats ................................................................................................................15
Table 3.3. Head Flags ..........................................................................................................................................................16
Table 3.4. Info Bytes ...........................................................................................................................................................16
Table 3.5. SPI Parameter .....................................................................................................................................................17
Table 3.6. Calibration Checksum ........................................................................................................................................17
Table 3.7. HW Configuration Data ......................................................................................................................................17
Table 3.8. 8051 Code Size ...................................................................................................................................................17
Table 3.9. HW Configuration Data and Code Checksum.....................................................................................................17
2
Table 3.10. Control of Transmitter I C Address with CI2CA Signal .....................................................................................18
Table 3.11. GPIOs ................................................................................................................................................................18
Table 4.1. Absolute Maximum Ratings ...............................................................................................................................19
Table 4.2. Normal Operating Conditions ............................................................................................................................20
Table 4.3. ESD Specifications ..............................................................................................................................................20
Table 4.4. Digital I/O Specifications ....................................................................................................................................21
Table 4.5. Analog Front-end Electrical Specifications .........................................................................................................22
Table 4.6. Parallel Video Output Timing Specifications ......................................................................................................23
Table 4.7. Control Signal Timing Specifications ..................................................................................................................23
Table 6.1. AFE Input/Output Pins .......................................................................................................................................27
Table 6.2. Configuration and Control Pins ..........................................................................................................................28
Table 6.3. Parallel RGB Output Data Pins ...........................................................................................................................29
Table 6.4. SPI Interface Pins ................................................................................................................................................30
Table 6.5. Power and Ground Connections ........................................................................................................................30
Table 6.6. Crystal Pins .........................................................................................................................................................30
Table 6.7. Reserved Pins .....................................................................................................................................................31
Table 6.8. RGB/YCbCr 4:4:4 Separate Sync Data Mapping .................................................................................................31
Table 6.9. YCbCr 4:2:2 Separate Sync Data Mapping..........................................................................................................32
Table 6.10. YCbCr 4:2:2 Embedded Sync Data Mapping.....................................................................................................33
Table 6.11. YCbCr Mux 4:2:2 Separate Sync Data Mapping ...............................................................................................34
Table 6.12. YCbCr Mux 4:2:2 Embedded Sync Data Mapping ............................................................................................35
Table 6.13. 12-bit RGB and YCbCr 4:4:4 Separate Sync Data Mapping ..............................................................................36
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4
SiI-DS-1123-A
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
1.1.3. Video Processing
1. General Description
The Lattice Semiconductor SiI8788 processor is a high
quality Analog Front-end (AFE) and multistandard
composite or component Video Decoder (VDC). A
microcontroller is integrated to reduce the system
BOM cost.
The SiI8788 processor supports worldwide PAL, NTSC
and SECAM standards, YPbPr video signals up to
1080p @ 60 Hz resolution.
The device contains a Time Base Correction (TBC)
module, a de-interlacer with a post-processor engine
and a VBI decoder.



Time Base Correction
De-interlacer with Edge Smoothing
Automatic Phase/Position Detection
1.1.4. 24-bit Parallel Output




Supports 24-bit RGB/YCbCr 4:4:4 and 12-bit
RGB/YCbCr 4:4:4 Double Data Rate (DDR) modes
Supports 24-bit YCbCr 4:2:2 and 12-bit YCbCr 4:2:2
DDR modes
Supports 8/10/12-bit YC MUX 4:2:2 modes
Supports embedded sync for YCbCr 4:2:2 and YC
MUX 4:2:2 modes
Supports embedded raw VBI data (CC, WSS)
1.1. Features

1.1.1. Analog (Video) Front-end
1.2. Applications



Four 10-bit Analog-to-Digital Converters (ADC)
sampling up to 170 MHz
Flexible input multiplexers to support four
composite and two component video inputs
Support cable plug-in detection and active video
signal detection
The SiI8788 device is targeted at the home theatre and
profession/commercial markets, specifically in A/V
Receiver and Video Switcher / Processor applications
1.3. Packaging
1.1.2. Multi-format Video Decoder




1.4. Temperature Range



Automatic format detection
Supports NTSC, PAL, and SECAM standards of
composite input with adaptive comb filter
Supports 240p/288p, 480i/p, 576i/p, 720p,
1080i/p component video
Supports Macrovision Type I, II, III copy protection
detection
Supports multistandard VBI decoding: WSS, VPS,
CC, CGMS, and V-CHIP

88-pin QFN with exposed pad (ePad)
10 mm × 10 mm × 0.9 mm
0 C to +70 C
A/V Receiver
CVBS Pass Through
Analog
Video
Inputs
SiI8788
Parallel Video Output
HDMI
HDMI
MHL
Video
Processor
HDMI
Port
Processor
Figure 1.1. Typical Application of the SiI8788 Device
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1123-A
5
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
2. Product Family
A comparison of the features between the SiI8788 device and the SiI8784 device is shown in Table 2.1.
Table 2.1. Product Selection Guide
Feature
SiI8784
SiI8788
Analog Video Input
Component Ports
Composite Ports (CVBS)
YES
YES
YES
YES
D-connector Support
YES
NO
VGA Support
YES
NO
SCART (FB/FS) Support
YES
NO
Video Output
Parallel Digital
CVBS
NO
YES
YES
YES
HDMI
MHL
YES
YES
NO
NO
Audio Input
SPDIF Input
2
I S Input
YES
YES
NO
NO
Package
Package Type
QFN
QFN
88
88
Pin Count
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
6
SiI-DS-1123-A
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
3. Functional Description
The SiI8788 device has a multiformat AFE with 4 ADC channels to support multiple analog video inputs. The SiI8788
device offers four CVBS video inputs, two component video inputs and one parallel video output. Figure 3.1 shows the
block diagram of the input processor.
PGA+ADC
Clamp
Offset
LPF
PGA+ADC
RED0
RED1
Clamp
Offset
LPF
PGA+ADC
Clamp
Offset
LPF
PGA+ADC
SYNC SLICER
TBC
APD
Sync Processor
LLPLL
DI
ES
APC
CP
Output
LPF
Video
Decoder
BLU0
BLU1
SOG0
SOG1
VBI
Post
Processor
VBI
Decoder
Clamp
Offset
Video Path
Data Conversion
CVBS0
CVBS1
CVBS2
CVBS3
GRN0
GRN1
Video Processing
ADCIF
CVBS_OUT
VDC
VBUF
AFE
D0..23
ODCK
DE
HSYNC
VSYNC
AGC
WIN
Sliced Sync
Phase
Control Logic
Registers
INT
GPIO
8051 Core
INT
I2C
Slave
I2C
M/S
SPI
Master
Boot
Loader
SCS
SCLK
SDO
SDI
OSC
LSCL
LSDA
24M
128K
Code
RAM
+
3K Data
RAM
RESET
RESET_N
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
Figure 3.1. Functional Block Diagram
Each of the blocks is explained in detail in the following sections.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1123-A
7
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
3.1. Analog Front-end
The Analog Front-end (AFE) provides four input channels for CVBS, R, G and B. Each channel includes an Input
Multiplexer, a Clamp and Offset DAC, a Programmable Low Pass Filter, and a high quality 10-bit ADC with
Programmable Gain Amplifier. In addition, there is a Line Locked PLL to generate sample clocks for ADCs and Sync
Slicers to handle SOG signals.
3.1.1. Input Multiplexer
The SiI8788 device provides four CVBS inputs and two sets of components inputs.
3.1.2. Clamp and Offset
As most of the video signals, such as CVBS, are AC coupled, their DC component is lost during the transmission. A
voltage type clamp circuit is positioned in front of each channel to restore the DC component.
Clamp
DAC
MUX
Clamp_P
X1
Input_P
0.85V
LPF
Cext
Clamp_N
+
Input_N
Cext
X1
Offset
DAC
Figure 3.2. Clamp and Offset
The clamp DAC output voltage is 3-bit programmable from 0 V to 0.85 V, and the AFE provides more accurate 10-bit
±0.5 V or ±0.25 V output offset DAC to keep the input signal within the ADC input range. The offset level can be
controlled automatically by ADCIF block of VDC or manually by software.
3.1.3. Low Pass Filter
The Low Pass Filter (LPF) is a first order analog filter to remove the out-of-band noise from video signal. Its –3 dB
bandwidth can be set to 600 MHz (Bypass), 400 MHz, 200 MHz, 100 MHz, or 50 MHz by software. Combined together
with ADC over-sampling technology and the high order digital AA (Antialias) filter inside VDC, the SiI8788 device can
meet the demand of overall AA performance.
3.1.4. ADC with Programmable Gain Amplifier
The ADC samples the input video signal and converts each sample into 10 bits digital data. It supports sampling rates
from 25 MSPS to 170 MSPS, and the sampling clock of CVBS channel can be independent with R, G, and B channels.
For the formats with lower pixel rate, oversampling is recommended. The SiI8788 device supports 2X, 4X and 8X
oversampling.
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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SiI-DS-1123-A
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
The Programmable Gain Amplifier (PGA) in the front stage of ADC has a nominal gain range from –6 dB to +6 dB, so the
SiI8788 device can adapt to a wide range of input video signal levels, especially, the CVBS signal from RF tuner. The PGA
can be controlled either automatically by the gain control function of VDC or manually by software.
3.1.5. Line Locked PLL
The Line Locked PLL (LLPLL) is designed to generate the ADC sampling clock (pixel clock or oversampled pixel clock). It
can be synchronized with a slower reference HSync pulses or run at a fixed frequency. The allowable input HSync range
is from 15 kHz to 150 kHz, and the output pixel clock range is from 25 MHz to 170 MHz.
The LLPLL contains an high performance programmable digital PLL (DPLL) and an analog PLL (APLL) which generates the
high frequency reference clock needed by DPLL from the 24 MHz crystal frequency.
The relative phase between input sync pulse and output clock of the LLPLL can be adjusted in 32 steps by setting
registers or automatically by Auto Phase Detection (APD) block of the video processing module.
3.1.6. Sync Slicer
MUX
SOG0
SOG1
SOG2*
SOG3*
Clamp
MUX
The Sync Slicer converts SOG and HSYNC signals into core domain digital signals. As shown in Figure 3.3, there are two
sets of SOG slicers, each of which contains an input multiplexer, bottom level (0.5 V) clamp, low pass filter and
comparator. The bandwidth of the low pass filter and the comparator threshold is programmable. There also are two
sets of HS slicers for TTL level syncs. When one of the slicers is configured as an active input, the other in this pair can
be used to detect the activity of other inputs. This feature is helpful to implement active channel detection and
auto-switch function.
Clamp
LPF
0.525V~1V
COMP
SOG_A
0.525V~1V
COMP
SOG_B
LPF
*: Not available on this device
Figure 3.3. Sync Slicers
3.1.7. Video Buffer
The Video Buffer (VBUF) buffers and outputs the selected CVBS input signal. VBUF includes two major subblocks: clamp
and voltage-to-current conversion. Voltage-to-current conversion subblock converts input signal to the output current
which is proportional to signal voltage level. A 75 Ω source termination resistor should be connected to its output pin
CVBS_OUT and signal ground.
3.2. Video Decoder
The SiI8788 device provides a multiformat video decoder. Video Decoder (VDC) includes ADCIF, Sync Processor,
adaptive 2D Comb decoder, and VBI Decoder as shown in Figure 3.1 on page 7.
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1123-A
9
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
3.2.1. ADCIF
The ADCIF logic block contains the Automatic Gain Control and Offset Calibration, Antialias filtering and decimation
subblocks. It also generates clamp pulses for clamp circuits at the proper time so that the ADC is able to digitize the
input analog within the proper range. The main indicator used to determine where the clamping position should be is
the horizontal synchronization pulse coming from the Sync Processor block. Since this filtered HSync pulse may not
always be correct, several layers of logic have been developed to ensure the clamping is not done at an incorrect
position.
3.2.2. Automatic Gain Control and Offset Calibration
Parameters such as Sync Amplitude, Back Porch Levels are measured based on the HSync position, register controls,
and logic executed in the Offset Gain Calculations sub block. These measured values are then used in determining the
offset and gain adjustments. To ensure the stability and accuracy of the digitized video signal, several control loops are
built in the ADCIF block. These loops include Clamp, Coast, Gain, and Offset. The Clamp and Coast pulses, Gain and
Offset parameters are generated by the ADCIF logic and directly connected to the AFE.
3.2.3. Antialias Filtering and Decimation
The Antialiasing (AA) filters remove high frequency noise from the raw digitized signals produced by the front-end
video ADCs, and decimate the over-sampled video signal.
The AA filter has flexibility in the frequency response, sharp transition bandwidth, and good stop band attenuation. The
AA filter allows the software to change the bandwidth of the filters as the signal condition changes.
3.2.4. Video Decoder
The Video Decoder detects and decodes the input video stream from ADCIF. An adaptive comb filter is included to
decode CVBS signals. The Video Decoder also supports component signals.
3.2.5. CVBS Processing
CVBS Processing involves Standard Detection, 2D Video Decoder, and Sync Processor, as shown in Figure 3.4 below.
ADCIF
CVBS Processing
Standard
Detection
AA Filter
PAL/NTSC/
SECAM
Video Decoder
Hs,Vs
10 bit
CVBS
Data
Sync Processor
Figure 3.4. CVBS Processing Diagram
The SiI8788 device automatically detects NTSC (M/J/4.43), PAL (B/D/I/G/H/60/M/N/Nc), and SECAM (B/D/G/L/K)
standards, and decodes them properly.
An adaptive 2D comb filter is used in the video decoder. The 2D comb filter has three output options, only horizontal
filter, only vertical filter and blending of horizontal and vertical filter. When current sample is on a horizontal transition
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
10
SiI-DS-1123-A
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
edge, the vertical filter is selected. When current sample is on a vertical transition edge, the horizontal filter is selected.
When it is not one of the above two phenomenon, the blending output is selected.
When the input signal is lost, the SiI8788 device supports a free-running mode to provide a stable output.
3.2.6. Component Processing
Component Processing processes Component Video inputs. The SiI8788 device supports 240p/288p, 480i/576i,
480p/576p, 720p, 1080i and 1080p for standard and high definition resolutions. Figure 3.5 shows the block diagram of
the component video processing block.
ADCIF
10 bit
Y
Data
AA Filter
10 bit
U
Data
AA Filter
10 bit
V
Data
AA Filter
SOG0/1
Component Processing
AFE
SYNC SLICER
sliced sync
Sync Processor
hsync reference
LLPLL
Figure 3.5. Component Processing Diagram
3.2.7. Sync Processor
The Sync Processor block contains sophisticated digital circuitry that analyzes and extracts synchronization pulses from
the incoming video stream. It generates filtered vertical and horizontal sync pulses. The Sync Processor includes Sync
separation, format detection and Sync stabilization.

Sync Separation
The Sync Separation separates the HSync and VSync from the composite sync sliced from video decoder or SOG slicer.
 Format Detection
The format detection detects vertical period and horizontal period and total line number per field.
 Sync Stabilization
Sync Stabilization does de-glitch, removes serration and equalizes pulses from the sync signal. It also detects
Macrovision protection status.
3.2.8. VBI Decoder
The VBI Processing block slices and processes digitized VBI data from the video. Following are some of the features of
the VBI block:



108 MHz operating with programmable down sampling
Supports PAL standards
Supports NTSC standards
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1123-A
11
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
Table 3.1 shows the supported VBI standards.
Table 3.1. Supported Standards
VBI
Standard
Video
Standard
Data Rate
Scan
Lines
Data per
Line
WSS 625
PAL
SECAM
5 MHz
23
336
14 Bits
VPS
PAL
SECAM
5 MHz
16
CC
NTSC
0.5030 MHz
XDS
VChip
NTSC
0.5035 MHz
WSS 525
ID-1
CGMS
NTSC
0.4474 MHz
Encoding
Description
Phase Encoding.
Each bit is transmitted using
6 bits of encoded data.
Wide Screen Signaling.
Used for aspect ratio settings.
13 Bytes
Biphase Encoding.
Each bit is effectively
represented by 2 bits.
Video Programming System.
Used in Germany for
program/broadcast info.
21
2 Bytes
Parity.
Closed Captioning for the hearing
impaired.
284
2 Bytes
Parity.
Extended Data Service.
Used for MISC. NTSC services
CRC.
Copy Guard Management
System.
Used for copy protection and
aspect ratio.
20
14 Bits
3.3. Video Processing
The Video Processing block performs some necessary processes to the decoded video streams before they are
outputted. There are also some measurement blocks inside this block to implement automatic Phase/Position/Gain
adjustment functions.
3.3.1. Time Base Corrector
The Time Base Corrector (TBC) is designed to provide stable clock and video data for parallel video output. It uses a line
buffer based architecture in-lieu of a frame buffer to save cost and power. To keep the video output clock jitter in a
safe range, the TBC output field frequency is limited to 50 Hz ±0.5% or 59.94 Hz/60 Hz ±0.5% as default. If the field
frequency of input video is beyond this range, the display will be scrolling.
Composite video formats are supported by the TBC. 480i/576i component formats can be supported by the TBC if
needed.
3.3.2. VBI Post Processor
VBI Post Processor is used to transmit raw VBI data over TTL output.
3.3.3. De-interlacer and Edge Smoother
De-interlacing is designed to convert interlaced (480i/576i) video to progressive (480p/576p) video. BOB de-interlace
method is adopted to reduce cost and power consumption. An edge smoother is included to reduce the saw tooth
artifacts generated by de-interlacing and improve the picture quality.
3.3.4. Color Processing
Color Processing (CP) enables brightness, contrast, saturation and hue controls for end users. It supports YCbCr color
space only.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
12
SiI-DS-1123-A
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
3.3.5. Auto Phase Detection
Auto Phase Detection (APD) is a module used to search for the phases that can generate the best display quality. The
desired phases, in general, can generate sharp and stable images, if the input image meets certain criteria during phase
detection period. APD is an automatic algorithm can be enabled or disabled by software. It can be applied to
Component inputs.
3.3.6. Auto Position Calibration
Auto Position Calibration (APC) detects the active picture area of input video signal and adjusts the output timing so
that the final picture can fit to the display properly.
3.3.7. Auto Gain Calibration
Slight mismatch of analog input channels, including offset and gain may impact the picture quality. The SiI8788 device
has been well designed to keep the mismatches in acceptable range (<0.5 dB). It is still important to calibrate these
mismatches in some cases to achieve the most accurate picture. To help manufacturers complete this process in a
short time, an Auto Gain Calibration (AGCWIN) mechanism is designed in SiI8788 device. This mechanism will
automatically measure the digitalized signal levels through AGCWIN module, calculate the correction values. These
values can be used by firmware in user mode to compensate the analog mismatches.
3.4. Video Path
3.4.1. Video Data Conversion Logic Block
The video data conversion logic block receives the output data from the video processing block. Figure 3.6 shows the
video data processing stages. Each of the processing blocks can be bypassed by setting the appropriate register bits.
RGB to
YCbCr
Color Space
Converter
bypass
YCbCr
Range
Compression
4:4:4 to
4:2:2
Downsampler
bypass
bypass
4:2:2 to
4:4:4
Upsampler
bypass
DE
YCbCr to RGB
Color Space
Converter
RGB
Range
Expansion
10 to 8 Bit
Dither
Mux
656
bypass
bypass
bypass
bypass
Video
Timing
HSYNC
VSYNC
ODCK
Q[23:0]
Figure 3.6. Default Video Processing Path
3.4.1.1. Color Space Converters
Color Space Converters (CSCs) are provided to convert RGB data to the Standard-definition (ITU.601) or High-definition
(ITU.709) YCbCr formats, and vice-versa. The CSC can be adjusted to perform standard-definition conversions (ITU.601)
or high-definition conversions (ITU.709) by setting the appropriate registers.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1123-A
13
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
3.4.1.2. YCbCr Range Compression
When enabled by itself, the Range Compression Block compresses 0–255 full-range data into 16–235 limited-range
data for each video channel, and compresses to 16–240 for the Cb and Cr channels. The color range scaling is linear.
3.4.1.3. 4:4:4 to 4:2:2 Downsampler
Downsampling reduces the number of chrominance samples in each line by half, converting 4:4:4 sampled video to
4:2:2 video.
3.4.1.4. 4:2:2 to 4:4:4 Up-sampler
Chrominance upsampling and downsampling increase or decrease the number of chrominance samples in each line of
the video. Upsampling doubles the number of chrominance samples in each line, converting 4:2:2 sampled video to
4:4:4 sampled video.
3.4.1.5. RGB Range Expansion
The SiI8788 device can scale the input color from limited-range into full-range using the range expansion block. When
enabled by itself, the range expansion block expands 16 – 235 limited-range data into 0 – 255 for each video channel.
When the range expansion and the YCbCr to RGB color space converter are both enabled, the input conversion range
for the Cb and Cr channels is 16 – 240.
3.4.1.6. 10 to 8 Bit Dither
The 10 to 8 Bit Dither block dithers internally processed 10-bit data to 8-bit data for output.
3.4.1.7. Mux 656
The Mux 656 block multiplexes the video data into YC Mux (ITU.656) format.
3.4.1.8. Video Timing
The video timing block is used to control the timing of the digital parallel video output automatically according to the
output format setting, such as controlling the output frequency of the ODCK, and disabling the HSYNC, VSYNC and DE
signals output when the output format is set as embedded syncs.
3.4.2. Digital Parallel Video Output Interface
The SiI8788 input processor outputs the uncompressed digital video with a data width of 8 to 24 bits from the digital
parallel video output interface. The data path has three 8-bit data channels, which can be configured in many different
video formats. The supported typical formats are listed in Table 3.2.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
14
SiI-DS-1123-A
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
Table 3.2. Typical Digital Video Output Formats
Color
Space
Video
Format
Bus Width
HSYNC/VSYNC
RGB
4:4:4
24
12
Separate
Separate
4:4:4
24
12
Separate
Separate
16/20/24
16/20/24
8/10/12
8/10/12
YCbCr
4:2:2
Output Clock (MHz)
480i/576i
27
27
2, 3
Notes
480p
27
27
720p
74.25
74.25
1080i
74.25
74.25
1080p
148.5
—
27
27
27
27
74.25
74.25
74.25
74.25
148.5
—
—
4
Separate
Embedded
27
27
27
27
74.25
74.25
74.25
74.25
148.5
148.5
—
1
Separate
Embedded
27
27
54
54
148.5
148.5
148.5
148.5
—
—
—
1
—
4
Notes:
1.
Embedded syncs use SAV/EAV coding.
2.
480i and 576i modes can output a 13.25 MHz clock using the internal clock divider.
3.
Output clock frequency depends on programming of internal registers.
4.
Output clock supports 12-bit mode by using DDR mode.
3.5. Control Logic
3.5.1. Internal Microcontroller
As shown in Figure 3.1 page 7, an 8-bit 8051 compatible micro-controller is integrated in the SiI8788 device. It contains
3 KB data RAM and 128 KB code RAM. The code can be loaded into code RAM from an external SPI Flash or EEPROM
memory automatically after power on. If the check sum of the code data is correct, the code will be executed.
2
Otherwise the internal microcontroller is disabled and the chip can be controlled by an external controller through I C
bus. The internal controller can access all the internal registers directly over the internal bus. The 8051 microcontroller
runs at the crystal clock of 24 MHz.
When the booting procedure is finished, the SPI interface is handed over to the 8051 SPI module so that firmware can
read/write the external memory if needed.
2
The internal controller can also operate other peripherals through the I C bus of the SiI8788 device by setting it to the
master mode.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1123-A
15
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
3.5.1.1. Data Structure of External SPI Memory
Figure 3.7 shows the memory structure which is required for the internal microcontroller to load the code correctly.
HW and CODE
Checksum
scope
FFFFH
HW Config Data and 8051
Code Checksum 4bytes
17FFFH
RSVD
8BFFH
System Calibration Data
8051 Code Content
96Kbytes SRAM
8B00H
3Kbytes SRAM DATA
8000H
RSVD
8051 Code Length 3bytes
Internal registers
HW Config Data 32bytes
29FFH
Calibration Checksum
2bytes
Calibration
Checksum
scope
HDMI/MHL Registers
2000H
RSVD
System Calibration Data
254bytes
0EFFH
VDC/VPP/AFE Registers
0200H
Info 12bytes
RSVD
Head Flag 4bytes
00000H
0100H
System Registers
0000H
8051 Code Memory
8051 Data Memory
Figure 3.7. External Memory Structure
Table 3.3. Head Flags
EEPROM/Flash Address
00000H
EEPROM/Flash Content
Head0 ‘S’
00001H
00002H
00003H
Head1 ‘I’
Head2 ‘M’
Head3 ‘G’
Note: The head flag will be four bytes ASCII code of ‘S’, ‘I’, ‘M’, ‘G’.
Table 3.4. Info Bytes
EEPROM/Flash Address
EEPROM/Flash Content
00004H
00005H
SPI PARAMETER.
Calibration Version (low byte).
00006H
00007H
00008H
Calibration Version.
Calibration Version (high byte).
Code Version (low byte).
00009H
0000AH
Code Version.
Code Version (high byte).
0000BH
0000CH
0000DH
Reserved.
Reserved.
Reserved.
0000EH
Reserved.
0000FH
Reserved.
Note: The info bytes will contain the information about the feature of Max read frequency of external EEPROM/Flash, the calibration
version, and the code version. It will occupy 12 bytes.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
16
SiI-DS-1123-A
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
Table 3.5. SPI Parameter
SPI Parameter
Description
0x00
2 MHz baud rate to access SPI Flash/EEPROM.
0x01
24 MHz baud rate to access SPI Flash/EEPROM.
Table 3.6. Calibration Checksum
EEPROM/Flash Address
EEPROM/Flash Content
0010EH
0010FH
Calibration Checksum (low byte).
Calibration Checksum (high byte).
Note: The calibration checksum will be two bytes which locates at the last site of 256 size calibration data.
Table 3.7. HW Configuration Data
EEPROM/Flash Address
EEPROM/Flash Content
00110H
BT_SPI_PINMUX_SEL.
00H – SPI function
01H – Reserved. Don’t use
02H – Reserved. Don’t use
00111H..0012FH
Reserved.
Table 3.8. 8051 Code Size
EEPROM/Flash Address
00130H
00131H
EEPROM/Flash Content
Code Size (low byte).
Code Size.
00132H
Code Size (high byte).
Table 3.9. HW Configuration Data and Code Checksum
EEPROM/Flash Address
00133H + code size
EEPROM/Flash Content
Code Checksum0 (lowest byte).
00134H + code size
00135H + code size
00136H + code size
Code Checksum1.
Code Checksum2.
Code Checksum3 (highest byte).
The boot module =tries to read data from external device and write into chip SRAM. The 8051 code content will be
written into the 96 K bytes SRAM of 8051. The 256 system calibration will be written into the high 3K bytes SRAM in
data memory.
For details on the selection of the SPI Flash memory, refer to the relevant Application Note (SiI-AN-1108).
3.5.2. Registers
The register block incorporates all the registers required for configuring and managing the SiI8788 device. These
registers are used to perform AFE processing, VDC processing, and all other control functions. Refer to the associated
Programmer Reference for the information on these registers. The Programmer’s Reference requires an NDA with
Lattice Semiconductor.
3.5.3. I2C Bus
2
2
The local I C slave bus provides the host with communication to the entire system. The controller I C interface on the
SiI8788 device (signals CSCL and CSDA) is a slave interface, which is capable of running up to 400 kHz.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1123-A
17
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
2
All functions of the SiI8788 device are controlled and observed with I C registers. Device addresses can be altered with
the level of the CI2CA signal. Table 3.10 shows the device addresses as altered by the level of the CI2CA signal.
2
Table 3.10. Control of Transmitter I C Address with CI2CA Signal
CI2CA = 0
0x8C
CI2CA = 1
0x8E
0x84
0x84
0x86
0x86
0x8A
0x8A
0x92
0x92
Purpose
System Control and Status
VD_DPGA
VD_SIGNALROUTING
VD_VBI
VD_VDREG
VD_ADCIF
VD_SYNCPROC
0x96
0x96
VD_ADCSTATUS
VD_VPP
Edge Smooth
INT
0xDA
0xDA
FPGA
APD
ADC Win
Vidpath
Calibration
0xD8
0xD8
AFE
2
Note: When the internal microcontroller is enabled, the I C bus will be taken over by the firmware and it can work as both master
and slave mode, and the addresses are alterable.
0x9C
0x9C
3.5.4. Interrupt
The SiI8788 device contains a configurable interrupt generator with an open-drain type output pin. It can be used to
notify application processor (if there is application processor) to handle some events. Refer to the associated
Programmer Reference for the information on these registers.
3.5.5. GPIOs
There are five general purpose IO pins on the SiI8788 device. Generally they can be used to detect the cable plug-in
status, but they can be used for other purposes as well.
Table 3.11. GPIOs
2
Name
1
GPIO0
Type
IO
Pull up/down
Pull down
Reset Status
I
GPIO1
GPIO2
GPIO3
IO
IO
IO
Pull up
Pull up
Pull up
I
I
I
GPIO4
IO
Pull up
I
Notes:
2
1.
GPIO0 is also used as CI2CA pin to decide the I C slave address during reset.
2.
The internal Pull up/down resistors are fixed and weak just to avoid floating input level when they are left unconnected.
Peripheral circuits should not rely on them. 10 K or smaller resistors are recommended for external pull up/down circuit to
override them if needed.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
18
SiI-DS-1123-A
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
4. Electrical Specifications
4.1. Absolute Maximum Ratings
Table 4.1. Absolute Maximum Ratings
Symbol
Parameter
Min
Typ
Max
Units
Notes
VP2V5A
Analog Power for AFE
–0.3
—
3.0
V
1, 2
VP2V5D
Digital Power for AFE
–0.3
—
3.0
V
1, 2
VP2V5_SLICER
Analog Power for SOG Slicer
–0.3
—
3.0
V
1, 2
VP1V0_PLL
Power for APLL and LLPLL
–0.3
—
1.2
V
1, 2
VCC10_TPLL
TCI PLL Power
–0.3
—
1.2
V
1, 2
CVCC10
Power for Digital Core
–0.3
—
1.2
V
1, 2
VDDIO33
Power for Digital I/O
–0.3
—
4.0
V
1, 2
XTALVCC33
Power for XTAL
–0.3
—
4.0
V
1, 2
VI
Digital Input Voltage
–0.3
—
VDDIO + 0.3
V
1, 2
VO
Digital Output Voltage
–0.3
—
VDDIO + 0.3
V
1, 2
AVI
Analog Input Voltage
-0.3
—
VP2V5A + 0.3
V
1, 2
V5V-Tolerant
Input Voltage on 5 V Tolerant Pins
–0.3
—
5.5
V
—
TJ
Junction Temperature
—
—
125
C
—
TSTG
Storage Temperature
–65
—
150
C
—
Notes:
1.
Permanent device damage can occur if absolute maximum conditions are exceeded.
2.
Functional operation should be restricted to the conditions described under normal operating conditions.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1123-A
19
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
4.2. Normal Operating Conditions
Table 4.2. Normal Operating Conditions
Symbol
Parameter
VP2V5A
Analog Power for AFE
IVP2V5A
Total Current Consumption of VP2V5A
VP2V5D
Digital Power for AFE
IVP2V5D
Total Current Consumption of VP2V5D
VP2V5_SLICER
Analog Power for SOG slicer
IVP2V5_SLICER
Current Consumption of VP2V5_SLICER
VP1V0_PLL
Power for APLL and LLPLL
IVP1V0_PLL
Current Consumption of VP1V0_PLL
VCC10_TPLL
TCI PLL Power
IVCC10_TPLL
Current Consumption of VCC10_TPLL
CVCC10
Power for Digital Core
ICVCC10
Total Current Consumption of CVCC10
VDDIO33
Power for Digital I/O
Min
Typ
Max
Units
Notes
2.375
2.50
—
—
95
260
2.625
V
—
—
—
mA
mA
4
5
2.375
2.50
—
30
2.625
V
—
—
mA
—
2.375
2.50
—
—
0
5
2.625
V
—
—
—
mA
mA
4
5
0.95
1.00
—
20
1.05
V
—
—
mA
—
0.95
1.00
—
3.5
1.05
V
—
—
mA
0.95
—
1.00
1.05
V
—
—
—
70
20
—
—
mA
mA
4
5
3.135
3.30
3.465
V
—
—
—
5
20
—
—
mA
mA
4
5
3.135
3.30
3.465
V
—
—
5
—
mA
—
IVDDIO3V3
Current Consumption of VDDIO3V3
XTALVCC33
Power for XTAL
IXTALVCC33
Current Consumption of XTALVCC33
TA
Ambient Temperature (with power applied)
0
25
70
C
—
ja
Ambient Thermal Resistance (Theta JA)
—
—
25.6
C/W
1
jc
Case Thermal Resistance (Theta JC)
—
—
11.9
—
—
Notes:
1.
Airflow at 0 m/s. Package ePad soldered to PCB.
2.
The power ripple must be below 60mVpp to avoid video quality detrition.
3.
Avoid any noise coupling to PLL power rails.
4.
Measured with CVBS input.
5.
Measured with YPbPr 1080p60 input.
4.3. ESD Specifications
Table 4.3. ESD Specifications
Symbol
Parameter
Min
Typ
Max
Units
Notes
Latch up
HBM
MM
ESD Latch up
Human Body Model
Machine Model
± 200
2000
200
—
—
—
—
—
—
mA
V
V
1, 2
3
4
500
—
—
V
5
CDM
Charged Device Model
Notes:
1.
At 70 °C.
2.
Measured as per JESD78B standard.
3.
Measured as per JESD22-A114 standard.
4.
Measured as per JESD22-A115 standard.
5.
Measured as per JESD22-C101 standard.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
20
SiI-DS-1123-A
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
4.4. DC Specifications
Table 4.4. Digital I/O Specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Note
Digital Inputs
VIL
Input Low Voltage
—
—
—
0.8
V
1
VIH
Input High Voltage
—
2.0
—
—
V
1
VTH+
Schmitt Trigger LOW to HIGH Threshold
—
1.61
1.69
1.77
V
1
VTH-
Schmitt Trigger HIGH to LOW threshold
—
1.18
1.27
1.35
V
1
IIL
Input Leakage Current
—
–10
—
10
A
1
RPU
Pull-up Resistor
—
27
38
59
KΩ
1
RPD
Pull-down Resistor
—
31
46
80
KΩ
1
VTH+I2C
Schmitt Trigger LOW to HIGH Threshold of
LSCL, LSDA
—
2.0
—
—
V
—
VTH-I2C
Schmitt Trigger HIGH to LOW Threshold of
LSCL, LSDA
—
—
—
0.8
V
—
Digital Outputs
VOH
HIGH-level Output Voltage
IOL = -8mA
2.4
—
—
V
1
VOL
LOW-level Output Voltage
IOH = 8mA
—
—
0.4
V
1
IOZ
Tri-state Output Leakage Current
—
–10
—
10
A
1
Note: Applies to general digital IOs.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1123-A
21
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
4.5. AC Specifications
Table 4.5. Analog Front-end Electrical Specifications
Analog Input
Symbol
Parameter
—
VFSR
—
VOAR
—
Conditions
Min
Typ
Max
Units
Input capacitance
Analog Input Range
Clamp Level
—
—
—
—
0.3
0.25
5
—
—
—
1.2
0.85
pF
Vpp
V
Offset Adjustment Range
Offset Adjustment Resolution
—
—
–0.5
—
—
10
+ 0.5
—
%FS
Bits
BW
Input Analog Filter Bandwidth
—
Gain Adjustment Range
A/D Converters
—
—
50
–6
—
—
600
+6
MHz
dB
—
N
Conversion Rate
ADC Resolution
—
—
25
—
—
10
170
—
MHz
Bits
INL
Integral Nonlinearity
—
4
—
LSB
DNL
Differential Nonlinearity
580 mVpp, 2.8 kHz Ramp Wave
Sampling Rate: 55 MHz
PGA Gain: 0 dB
LPF Bandwidth: 50 MHz
—
1
—
LSB
NMC
No Missing Codes
ENOB
Effective Number Of Bits
—
300 mVpp, 1.1 MHz Sine Wave
Sampling Rate: 165 MHz
PGA Gain: 0 dB
LPF Bandwidth: 400 MHz
Guaranteed
—
—
7.5
—
Bits
PLL
—
—
Clock Frequency Range
Period Jitter
—
—
25
—
—
—
170
450
MHz
ps
—
—
Video Buffer
Phase Adjustment
Duty Cycle
—
—
—
45
11.25
50
—
55
Degrees
%
DP
DG
Differential Phase
Differential Gain
—
—
—
—
—
—
4
4
Degrees
%
THD
Total Harmonic Distortion
700 mVpp, 4 MHz Sine Wave
Load = 37.5 Ω
Internal Clamp: OFF
—
-48
—
dB
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
22
SiI-DS-1123-A
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
Table 4.6. Parallel Video Output Timing Specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Figure
DLHT_C
LOW-to-HIGH Rise Time Transition,
ODCK pin
HIGH-to-LOW Fall Time Transition,
ODCK pin
LOW-to-HIGH Rise Time Transition,
data and control pins
CL = 10pF
—
—
0.74
ns
Figure 5.4
CL = 10pF
—
—
0.81
ns
Figure 5.4
CL = 10pF
—
—
1.15
ns
Figure 5.4
CL = 10pF
—
—
1.45
ns
Figure 5.4
TCIP
HIGH-to-LOW Fall Time Transition,
data and control pins
ODCK Cycle Time
CL = 10pF
40
—
6
ns
Figure 5.5
FCIP
TDUTY
TCK2OUT
ODCK Frequency
ODCK Duty Cycle
Clock-to-Output Delay
CL = 10pF
CL = 10pF
CL = 10pF
25
45%
0.2
—
—
—
165
55%
1
MHz
—
ns
Figure 5.5
Figure 5.5
Figure 5.5
DHLT_C
DLHT_D
DHLT_D
Notes:
1. The timings above apply to ODCK, HSYNC, VSYNC, DE, and Q[23:0].
4.6. Control Signal Timing Specifications
Table 4.7. Control Signal Timing Specifications
Symbol
TI2CDVD
TRESET
Parameter
SDA Data Valid Delay from SCL falling
edge on READ command
RESET_N Signal LOW Time required
for reset
Conditions
Min
Typ
Max
Units
Figure
Notes
CL = 400pF
—
—
700
ns
Figure 5.1
1, 2
—
5000
—
—
ns
Figure 5.2,
Figure 5.3
3
Notes:
2
2
1. All standard-mode (100 kHz) I C timing requirements are guaranteed by design. These timings apply to the slave I C port
(signals LSDA and LSCL).
2
2. Operation of I C signals above 100 kHz is defined by LVTTL levels VIH, VIL, VOH, and VOL (see Table 4.4 on page 21). For these
2
levels, I C speeds up to 400 kHz are supported.
3. Reset on RESET_N signal can be LOW as CVCC10 and VDDIO33 become stable, or pulled LOW for at least T RESET.
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SiI-DS-1123-A
23
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
5. Timing Diagrams
5.1. I2C Bus Timing Diagrams
LSDA
TI2CDVD
LSCL
2
Figure 5.1. I C Data Valid Delay (Driving Read Cycle Data)
5.2. Reset Timing Diagram
VDDIO33 must be stable between its limits for Normal Operating Conditions for TRESET before RESET_N is HIGH.
RESET_N must be pulled LOW for TRESET before accessing registers. This can be done by holding RESET_N LOW until
TRESET after stable power (Figure 5.2) or by pulling RESET_N LOW from a HIGH state (Figure 5.3) for at least TRESET.
VCCmax
VCCmin
VCC
RESET_N
TRESET
Figure 5.2. Conditions for Use of RESET_N
RESET_N
TRESET
Figure 5.3. RESET_N Minimum Timings
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
24
SiI-DS-1123-A
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
5.3. Digital Video Output Timing Diagrams
VOH
2.0 V
Q[ ]
HSYNC
VSYNC
ODCK
DE
0.8 V
VOL
DHLT
DLHT
Figure 5.4. Video Digital Output Transition Times
RCIP
OCLKINV=0
ODCK
OCLKINV=1
TDUTY
ODCK
TCK2OUT {Max}
TCK2OUT( {Min}
Q[35:0]
TCK2OUT {Max}
TCK2OUT {Min}
DE
HSYNC
VSYNC
Figure 5.5. Clock-to-Output Delay and Duty Cycle Limits
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1123-A
25
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
6. Pin Diagram and Pin Description
6.1. Pin Diagram
VP1V0_PLL
VP2V5_SLICER
CVBS_OUT
SOG1
47
46
45
VCC10_TPLL
49
48
XTALIN
XTALVCC33
SDI
56
50
SDO
57
51
SCS
58
XTALOUT
CVCC10
59
XTALGND
D23
60
52
VDDIO33
61
53
D22
62
SCLK
D21
63
CVCC10
D20
64
54
D19
65
55
D18
66
Figure 6.1 shows the pin assignments for the SiI8788 processor. Individual pin functions are described in the Pin
Descriptions section on the next page. The package is a 10 mm × 10 mm × 0.9 mm 88-pin QFN with an ePad, which
must be connected to ground.
CVCC10
67
44
SOG0
D17
68
43
AFE_REXT
VDDIO33
69
42
CVBSN
IOGND
70
41
CVBS3
D16
71
40
CVBS2
D15
72
39
VP2V5A
D14
73
38
CVBS1
D13
74
37
CVBS0
D12
75
36
VP2V5D
VDDIO33
76
35
GRNN
D11
77
34
VP2V5A
D10
78
33
GRN1
D9
79
32
GRN0
D8
80
31
BLUN
D7
81
30
VP2V5A
SiI8788
(Top View)
D6
82
29
BLU1
VDDIO33
83
28
BLU0
CVCC10
84
27
VP2V5D
D5
85
26
REDN
TMODE
86
25
VP2V5A
87
24
RED1
88
23
RED0
20
GPIO3
22
19
GPIO2
21
18
LSDA
GPIO4
17
SCAN_RSV
16
11
DE
INT
10
HSYNC
LSCL
9
VSYNC
15
8
CVCC10
14
7
D0
IOGND
6
D1
RESET_N
5
D2
13
4
VDDIO33
12
3
D3
ODCK
2
D4
VDDIO33
1
NC
GPIO1
GPIO0_CI2CA
ePad (GND)
Figure 6.1. Pin Diagram
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26
SiI-DS-1123-A
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
6.2. Pin Descriptions
The following tables provide the pin descriptions for the SiI8788 input processor.
6.2.1. AFE Input/Output Pins
Table 6.1. AFE Input/Output Pins
Pin Name
Pin
Type
Direction
Description
Notes
RED0
23
Analog
Input
Pr Input 0.
1
RED1
24
Analog
Input
Pr Input 1.
1
REDN
26
Analog
Input
Pr Negative Input.
2
BLU0
28
Analog
Input
Pb Input 0.
1
BLU1
29
Analog
Input
Pb Input 1.
1
BLUN
31
Analog
Input
Pb Negative Input.
2
GRN0
32
Analog
Input
Y Input 0.
1
GRN1
33
Analog
Input
Y Input 1.
1
GRNN
35
Analog
Input
Y Negative Input.
2
CVBS0
37
Analog
Input
CVBS INPUT 0.
1
CVBS1
38
Analog
Input
CVBS INPUT 1.
1
CVBS2
40
Analog
Input
CVBS INPUT 2.
1
CVBS3
41
Analog
Input
CVBS INPUT 3.
1
CVBSN
42
Analog
Input
CVBS Negative Input.
2
AFE_REXT
43
Analog
Passive
External Bias Resistor. Must connect a 12 K, 1% resistor to
ground.
—
SOG0
44
Analog
Input
SOG INPUT 0.
—
SOG1
45
Analog
Input
SOG INPUT 1.
—
CVBS Output. Connect a 75 Ω resistor to ground when CVBS
output is enabled.
—
CVBS_OUT
46
Analog
Output
Notes:
1.
A 47 nF couple capacitor is required when this pin is used.
2.
Must connect a 0.1µF capacitor to ground when the corresponding input channel is used.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1123-A
27
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
6.2.2. Configuration and Control Pins
Table 6.2. Configuration and Control Pins
Pin Name
Pin
Type
Direction
INT
16
LVTTL
Open Drain
5 V Tolerant
Output
RESET_N
15
LVTTL
Schmitt Trigger
5 V Tolerant
Input
LSCL
17
Open Drain
Schmitt Trigger
5 V Tolerant
IO
Local I C Bus Clock.
LSDA
18
Open Drain
Schmitt Trigger
5 V Tolerant
IO
Local I C Bus Data.
TMODE
86
Test Pin
Input
87
LVTTL
Schmitt Trigger
5 V Tolerant
Pull-down
IO
General GPIOs. It is also used to select local I C
slave address during reset when the internal
8051 is not used.
1
LVTTL
Schmitt Trigger
5 V Tolerant
Pull-up
IO
General GPIOs.
19
LVTTL
Schmitt Trigger
5 V Tolerant
Pull-up
IO
General GPIOs.
20
LVTTL
Schmitt Trigger
5 V Tolerant
Pull-up
IO
General GPIOs.
21
LVTTL
Schmitt Trigger
5 V Tolerant
Pull-up
IO
General GPIOs.
GPIO0_CI2CA
GPIO1
GPIO2
GPIO3
GPIO4
Description
Interrupt Pin.
External Reset Signal. Active LOW.
2
2
Reserved for test. This pin must be tied low
during the normal operation.
2
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28
SiI-DS-1123-A
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
6.2.3. Parallel Video Output Data Pins
Table 6.3. Parallel RGB Output Data Pins
Pin Name
Pin
Type
Direction
ODCK
12
LVTTL
Output
Description
Output Pixel Clock.
VSYNC
9
LVTTL
Output
Vertical Sync.
HSYNC
10
LVTTL
Output
Horizontal Sync.
DE
11
LVTTL
Output
Pixel Data Enable.
D0
7
LVTTL
Output
Output Pixel Data Bit 0.
D1
6
LVTTL
Output
Output Pixel Data Bit 1.
D2
5
LVTTL
Output
Output Pixel Data Bit 2.
D3
3
LVTTL
Output
Output Pixel Data Bit 3.
D4
2
LVTTL
Output
Output Pixel Data Bit 4.
D5
85
LVTTL
Output
Output Pixel Data Bit 5.
D6
82
LVTTL
Output
Output Pixel Data Bit 6.
D7
81
LVTTL
Output
Output Pixel Data Bit 7.
D8
80
LVTTL
Output
Output Pixel Data Bit 8.
D9
79
LVTTL
Output
Output Pixel Data Bit 9.
D10
78
LVTTL
Output
Output Pixel Data Bit 10.
D11
77
LVTTL
Output
Output Pixel Data Bit 11.
D12
75
LVTTL
Output
Output Pixel Data Bit 12.
D13
74
LVTTL
Output
Output Pixel Data Bit 13.
D14
73
LVTTL
Output
Output Pixel Data Bit 14.
D15
72
LVTTL
Output
Output Pixel Data Bit 15.
D16
71
LVTTL
Output
Output Pixel Data Bit 16.
D17
68
LVTTL
Output
Output Pixel Data Bit 17.
D18
66
LVTTL
Output
Output Pixel Data Bit 18.
D19
65
LVTTL
Output
Output Pixel Data Bit 19.
D20
64
LVTTL
Output
Output Pixel Data Bit 20.
D21
63
LVTTL
Output
Output Pixel Data Bit 21.
D22
62
LVTTL
Output
Output Pixel Data Bit 22.
D23
60
LVTTL
Output
Output Pixel Data Bit 23.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1123-A
29
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
6.2.4. SPI Interface Pins
Table 6.4. SPI Interface Pins
Pin Name
SCLK
SDI
SDO
SCS
Pin
Type
Direction
55
LVTTL
Schmitt Trigger
5 V Tolerant
Pull-down
Description
Output
56
LVTTL
Schmitt Trigger
5 V Tolerant
Pull-down
Input
57
LVTTL
Schmitt Trigger
5 V Tolerant
Pull-down
Output
SPI Data Output. Keep HiZ when RESET_N is low.
58
LVTTL
Schmitt Trigger
5 V Tolerant
Pull-down
Output
SPI Chip Enable. Keep HiZ when RESET_N is low.
SPI clock output. Keep HiZ when RESET_N is low.
SPI Data Input.
6.2.5. Power and Ground Connections
Table 6.5. Power and Ground Connections
Pin Name
Pin
Type
Description
VP2V5A
25, 30, 34, 39
Power
Analog power.
Supply
2.5 V
VP2V5D
27, 36
Power
Digital power for AFE.
2.5 V
VP2V5_SLICER
47
Power
Analog power for SOG Slicer.
2.5 V
VP1V0_PLL
48
Power
Power for LLPLL.
1.0 V
CVCC10
8, 54, 59, 67, 84
Power
Power for Digital Core.
1.0 V
VDDIO33
4, 13, 61, 69, 76, 83
Power
Power for Digital I/O.
3.3 V
VCC10_TPLL
49
Power
Power for TCI PLL.
1.0 V
XTALVCC33
50
Power
Power for XTAL.
3.3 V
IOGND
14, 70
Ground
Digital I/O Ground.
Ground
XTALGND
53
Ground
Ground for XTAL.
Ground
6.2.6. Crystal Pins
Table 6.6. Crystal Pins
Pin Name
Pin
Type
Direction
Description
XTALIN
51
Analog
I
Input for Crystal.
XTALOUT
52
Analog
O
Output for Crystal.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
30
SiI-DS-1123-A
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
6.2.7. Reserved Pins
Table 6.7. Reserved Pins
Pin Name
Pin
Type
Description
SCAN_RSV
22
RSVD
Reserved.
NC
88
RSVD
No Connection.
6.2.8. Output Pin Mappings
6.2.8.1. RGB and YCbCr 4:4:4 Separate Sync
The pixel clock runs at the pixel rate and a complete definition of each pixel is input on each clock. The same timing
format is used for YCbCr 4:4:4 as listed in column three of Table 6.8.
Table 6.8. RGB/YCbCr 4:4:4 Separate Sync Data Mapping
Pin Name
24-bit
RGB
24-bit
YCbCr
D0
D1
D2
B0
B1
B2
Cb0
Cb1
Cb2
D3
D4
B3
B4
Cb3
Cb4
D5
D6
D7
B5
B6
B7
Cb5
Cb6
Cb7
D8
D9
G0
G1
Y0
Y1
D10
D11
D12
G2
G3
G4
Y2
Y3
Y4
D13
D14
G5
G6
Y5
Y6
D15
D16
G7
R0
Y7
Cr0
D17
D18
D19
R1
R2
R3
Cr1
Cr2
Cr3
D20
D21
R4
R5
Cr4
Cr5
D22
D23
Hsync
R6
R7
Hsync
Cr6
Cr7
Hsync
Vsync
DE
Vsync
DE
Vsync
DE
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1123-A
31
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
6.2.8.2. YCbCr 4:2:2 Separate Sync Formats
The YCbCr 4:2:2 formats output one pixel for every pixel clock period. A luminance(Y) value is sent for every pixel, but
the chrominance values (Cb and Cr) are sent over two pixels. Pixel data can be 24-bit, 20-bit or 16-bit. HSYNC and
VSYNC are output separately on their own pins. The DE HIGH time must contain an even number of pixel clocks.
Table 6.9. YCbCr 4:2:2 Separate Sync Data Mapping
Pin Name
16-bit YCbCr
20-bit YCbCr
24-bit YCbCr
Pixel 0
Pixel 1
Pixel 0
Pixel 1
Pixel 0
Pixel 1
D0
NC
NC
NC
NC
Y0
Y0
D1
NC
NC
NC
NC
Y1
Y1
D2
NC
NC
Y0
Y0
Y2
Y2
D3
NC
NC
Y1
Y1
Y3
Y3
D4
Y0
Y0
Y2
Y2
Y4
Y4
D5
Y1
Y1
Y3
Y3
Y5
Y5
D6
Y2
Y2
Y4
Y4
Y6
Y6
D7
Y3
Y3
Y5
Y5
Y7
Y7
D8
Y4
Y4
Y6
Y6
Y8
Y8
D9
Y5
Y5
Y7
Y7
Y9
Y9
D10
Y6
Y6
Y8
Y8
Y10
Y10
D11
Y7
Y7
Y9
Y9
Y11
Y11
D12
NC
NC
NC
NC
Cb0
Cr0
D13
NC
NC
NC
NC
Cb1
Cr1
D14
NC
NC
Cb0
Cr0
Cb2
Cr2
D15
NC
NC
Cb1
Cr1
Cb3
Cr3
D16
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
D17
Cb1
Cr1
Cb3
Cr3
Cb5
Cr5
D18
Cb2
Cr2
Cb4
Cr4
Cb6
Cr6
D19
Cb3
Cr3
Cb5
Cr5
Cb7
Cr7
D20
Cb4
Cr4
Cb6
Cr6
Cb8
Cr8
D21
Cb5
Cr5
Cb7
Cr7
Cb9
Cr9
D22
Cb6
Cr6
Cb8
Cr8
Cb10
Cr10
D23
Cb7
Cr7
Cb9
Cr9
Cb11
Cr11
Hsync
Hsync
Hsync
Hsync
Hsync
Hsync
Hsync
Vsync
DE
Vsync
DE
Vsync
DE
Vsync
DE
Vsync
DE
Vsync
DE
Vsync
DE
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
32
SiI-DS-1123-A
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
6.2.8.3. YCbCr 4:2:2 Embedded Syncs Formats
The YCbCr 4:2:2 embedded sync format is identical to the previous format (YCbCr 4:2:2), except that the syncs are
embedded and not separate. Pixel data can be 24-bit, 20-bit, or 16-bit. DE is always output.
Table 6.10. YCbCr 4:2:2 Embedded Sync Data Mapping
Pin Name
16-bit YCbCr
20-bit YCbCr
24-bit YCbCr
Pixel 0
Pixel 1
Pixel 0
Pixel 1
Pixel 0
Pixel 1
D0
NC
NC
NC
NC
Y0
Y0
D1
NC
NC
NC
NC
Y1
Y1
D2
NC
NC
Y0
Y0
Y2
Y2
D3
NC
NC
Y1
Y1
Y3
Y3
D4
Y0
Y0
Y2
Y2
Y4
Y4
D5
Y1
Y1
Y3
Y3
Y5
Y5
D6
Y2
Y2
Y4
Y4
Y6
Y6
D7
Y3
Y3
Y5
Y5
Y7
Y7
D8
Y4
Y4
Y6
Y6
Y8
Y8
D9
Y5
Y5
Y7
Y7
Y9
Y9
D10
Y6
Y6
Y8
Y8
Y10
Y10
D11
Y7
Y7
Y9
Y9
Y11
Y11
D12
NC
NC
NC
NC
Cb0
Cr0
D13
NC
NC
NC
NC
Cb1
Cr1
D14
NC
NC
Cb0
Cr0
Cb2
Cr2
D15
NC
NC
Cb1
Cr1
Cb3
Cr3
D16
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
D17
Cb1
Cr1
Cb3
Cr3
Cb5
Cr5
D18
Cb2
Cr2
Cb4
Cr4
Cb6
Cr6
D19
Cb3
Cr3
Cb5
Cr5
Cb7
Cr7
D20
Cb4
Cr4
Cb6
Cr6
Cb8
Cr8
D21
Cb5
Cr5
Cb7
Cr7
Cb9
Cr9
D22
Cb6
Cr6
Cb8
Cr8
Cb10
Cr10
D23
Cb7
Cr7
Cb9
Cr9
Cb11
Cr11
Hsync
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Vsync
DE
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1123-A
33
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
6.2.8.4. YCbCr Mux 4:2:2 Separate Sync Formats
The video data is multiplexed onto fewer signals than the mapping in Table 6.11, but complete luminance (Y) and
chrominance (Cb and Cr) data is still provided for each pixel.
Table 6.11. YCbCr Mux 4:2:2 Separate Sync Data Mapping
Pin Name
8-bit
st
10-bit
nd
st
12-bit
nd
st
nd
1 Clk
2 Clk
1 Clk
2 Clk
1 Clk
2 Clk
D0
D1
NC
NC
NC
NC
NC
NC
NC
NC
C0
C1
Y0
Y1
D2
D3
D4
NC
NC
C0
NC
NC
Y0
C0
C1
C2
Y0
Y1
Y2
C2
C3
C4
Y2
Y3
Y4
D5
D6
C1
C2
Y1
Y2
C3
C4
Y3
Y4
C5
C6
Y5
Y6
D7
D8
D9
C3
C4
C5
Y3
Y4
Y5
C5
C6
C7
Y5
Y6
Y7
C7
C8
C9
Y7
Y8
Y9
D10
D11
C6
C7
Y6
Y7
C8
C9
Y8
Y9
C10
C11
Y10
Y11
D12
D13
D14
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
D15
D16
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
D17
D18
D19
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
D20
D21
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
D22
D23
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
34
SiI-DS-1123-A
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
6.2.8.5. YCbCr Mux 4:2:2 Embedded Sync Formats
This mode is similar to YCbCr 4:2:2 with embedded syncs, but also multiplexes the luminance(Y) and chrominance (Cb
and Cr) onto the same pins on alternating pixel clock cycles. Normally this mode is used only for 480i, 480p, 576i, and
576p modes. SAV code is shown before rise of DE. EAV follows the falling edge of DE.
Table 6.12. YCbCr Mux 4:2:2 Embedded Sync Data Mapping
Pin Name
8-bit
st
10-bit
nd
st
12-bit
nd
st
nd
D0
1 Clk
NC
2 Clk
NC
1 Clk
NC
2 Clk
NC
1 Clk
C0
2 Clk
Y0
D1
D2
D3
NC
NC
NC
NC
NC
NC
NC
C0
C1
NC
Y0
Y1
C1
C2
C3
Y1
Y2
Y3
D4
D5
C0
C1
Y0
Y1
C2
C3
Y2
Y3
C4
C5
Y4
Y5
D6
D7
D8
C2
C3
C4
Y2
Y3
Y4
C4
C5
C6
Y4
Y5
Y6
C6
C7
C8
Y6
Y7
Y8
D9
D10
C5
C6
Y5
Y6
C7
C8
Y7
Y8
C9
C10
Y9
Y10
D11
D12
D13
C7
NC
NC
Y7
NC
NC
C9
NC
NC
Y9
NC
NC
C11
NC
NC
Y11
NC
NC
D14
D15
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
D16
D17
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
D18
D19
D20
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
D21
D22
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
D23
HSYNC
VSYNC
NC
NC
NC
NC
NC
NC
DE
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1123-A
35
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
6.2.8.6. 12-bit RGB AND YCbCr 4:4:4 Formats with Separate Syncs
The output clock runs at the pixel rate and a complete definition of each pixel is output on each clock. One clock edge
drives out half the pixel data on 12 pins. The opposite clock edge drives out the remaining half of the pixel data on the
same 12 pins. Control signals (DE, Hsync, Vsync) change state with respect to the first edge of ODCK.
Table 6.13. 12-bit RGB and YCbCr 4:4:4 Separate Sync Data Mapping
24-bit
Pin Name
RGB
YCbCr
First Edge
Second Edge
First Edge
Second Edge
D0
B0
G4
Cb0
Y4
D1
B1
G5
Cb1
Y5
D2
B2
G6
Cb2
Y6
D3
B3
G7
Cb3
Y7
D4
B4
R0
Cb4
Cr0
D5
B5
R1
Cb5
Cr1
D6
B6
R2
Cb6
Cr2
D7
B7
R3
Cb7
Cr3
D8
G0
R4
Y0
Cr4
D9
G1
R5
Y1
Cr5
D10
G2
R6
Y2
Cr6
D11
G3
R7
Y3
Cr7
D12
NC
NC
NC
NC
D13
NC
NC
NC
NC
D14
NC
NC
NC
NC
D15
NC
NC
NC
NC
D16
NC
NC
NC
NC
D17
NC
NC
NC
NC
D18
NC
NC
NC
NC
D19
NC
NC
NC
NC
D20
NC
NC
NC
NC
D21
NC
NC
NC
NC
D22
NC
NC
NC
NC
D23
NC
NC
NC
NC
Hsync
Hsync
Hsync
Hsync
Hsync
Vsync
DE
Vsync
DE
Vsync
DE
Vsync
DE
Vsync
DE
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
36
SiI-DS-1123-A
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
7. Design Guidelines
7.1. Power Supplies Decoupling
Designers should include the decoupling and bypass capacitors at each power signal in the layout. These are shown
schematically in Figure 7.1. Place these components as close as possible to the input processor differential signals, and
avoid routing the differential signals through vias. Figure 7.2 is the representative of the various types of power
connections on the input processor.
VDD
L1
VCC Pin
C1
C2
C3
GND
Figure 7.1. Decoupling and Bypass Schematic
VCC
CVCC10
GND
C1
C2
L1
Ferrite
C3
Via to GND
Figure 7.2. Decoupling and Bypass Capacitor Placement
Connections in one group, such as CVCC10, can share C2, C3, and the ferrite, with each ball having a separate C1 placed
as close to the ball as possible.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1123-A
37
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
7.2. ESD Protection
The SiI8788 input processor chip is designed to withstand electrostatic discharge during manufacturing. In applications
where higher protection levels are required in the finished product, proper ESD precautions are recommended to avoid
performance degradation or loss of functionality.
7.3. EMI Considerations
Electromagnetic interference is a function of board layout, shielding, receiver component operating voltage, frequency
of operation, and so on. When attempting to control emissions, do not place any passive components on the
differential signal lines (except for the ESD protection and common mode choke described earlier). Lattice
Semiconductor recommends the use of a metal shielding can over the SiI8788 chip and the traces going to the
connector. The PCB ground plane should extend unbroken under as much of the input processor chip and associated
circuitry as possible, with all ground signals of the chip using a common ground.
7.4. Typical Circuit Connection
Representative circuits for applications of the SiI8788 chip are shown in Figure 7.3. For a detailed review of your
intended circuit implementation, contact your Lattice Semiconductor representative circuits. Figure 7.3 shows the
general bus interconnection between the host processor and the SiI8788 device. Either the INT output can be
connected as a hardware interrupt signal to the processor, or the processor can poll the registers to determine if any of
the interrupts have been triggered.
CVBS x 4
YPbPr x 2
/
/
/
/
CVBS0..3
RED0..1
GRN0..1
BLU0..1
D0..23
CVBSN
8/10/12/16/20/24-bit
Port
Processor
REDN
/
Analog Video
Interfaces
GRNN
VSYNC
BLUN
HSYNC
DE
ODCK
SOG0..1
+3.3V
SiI8788
Plug-in Detection
GPIO1..4
AFE_REXT
INT
12K
SOC
LSDA
LSCL
GPIO0_CI2CA
TMODE
XTALIN
RESET_N
XTALOUT
SCS
+3.3V
SCLK
SDO
SDI
SPI FLASH
24MHz
Figure 7.3. Typical Circuit Schematic
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
38
SiI-DS-1123-A
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
8. Packaging
8.1. ePad Requirements
The SiI8788 input processor chip is packaged in 88-pin QFN package with an exposed pad (ePad) that is used for the
electrical ground of the device and for improved thermal transfer characteristics. The ePad dimensions are
5.60 mm × 5.60 mm ± 0.15 mm. Soldering the ePad to the ground plane of the PCB is required to meet package power
dissipation requirements at full speed operation, and to correctly connect the chip circuitry to electrical ground. A
clearance of at least 0.25 mm should be designed on the PCB between the edge of the ePad and the inner edges of the
lead pads to avoid the possibility of electrical shorts.
The thermal land area on the PCB may use thermal vias to improve heat removal from the package. These thermal vias
also double as the ground connections of the chip and must attach internally in the PCB to the ground plane. An array
of vias should be designed into the PCB beneath the package. For optimum thermal performance, the via diameter
should be 12 mils to 13 mils (0.30 mm to 0.33 mm) and the via barrel should be plated with 1-ounce copper to plug the
via. This design helps to avoid any solder wicking inside the via during the soldering process, which may result in voids
in solder between the pad and the thermal land. If the copper plating does not plug the vias, the thermal vias can be
tented with solder mask on the top surface of the PCB to avoid solder wicking inside the via during assembly. The
solder mask diameter should be at least 4 mils (0.1 mm) larger than the via diameter.
Package stand-off when mounting the device also needs to be considered. For a nominal stand-off of approximately 0.1
mm the stencil thickness of 5 mils to 8 mils should provide a good solder joint between the ePad and the thermal land.
Figure 8.1 on the next page shows the dimensions of the SiI8788 package.
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1123-A
39
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
8.2. Package Dimensions
0.10 C
A
B
D
D1
0.10 M C A B
D2
88
88
1
2
3
1
2
3
0.10 M C A B
E2
E1 E
A
L
0.10 C
e
Top View
Bottom View
K
A2
Side View
C
0.10 M C A B
0.05 M C
// 0.10 C
A1 A3
A
b
0.08 C
R
Seating Plane
0.6 max
0.6 max
Detail A
JEDEC Package Code MO-2206
Description
Min
Typ
Max
Item
Description
Min
Typ
Max
A
A1
A2
Thickness
Stand-off
Body thickness
0.80
0.00
0.60
0.85
0.02
0.65
0.90
0.05
0.70
D2
E2
b
ePad
ePad
Lead width
5.45
5.45
0.15
5.60
5.60
0.20
5.75
5.75
0.25
A3
D
Base thickness
Footprint
9.90
0.20 REF
10.00
10.10
e
L
Lead pitch
Lead foot length
0.30
0.40 BSC
0.40
0.50
E
D1
E1
Footprint
Body size
Body size
Θ
R
K
Mold angle
Lead radius, inside
ePad clearance
0°
0.075
0.20
—
—
—
14°
—
—
Item
9.90
10.00
9.75 BSC
9.75 BSC
10.10
Note: Dimensions in mm.
Figure 8.1. 88-Pin QFN Package Diagram
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
40
SiI-DS-1123-A
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
9. Marking Specification
Figure 9.1 shows the markings of the SiI8788 package. This drawing is not to scale.
Pin 1
Location
Logo
SiI8788 CNUC
LLLLLL.LL-L
YYWW
XXXXXXX
Silicon Image Part Number
Lot # (= Job#)
Date code
Trace code
SiIxxxxrpppp-sXXXX
Product
Designation
Special
Designation
Revision
Speed
Package Type
Figure 9.1. Marking Diagram
9.1. Ordering Information
Production Part Numbers:
Device
Part Number
Analog Front End Video Processor with Parallel Video Output
SiI8788CNUC
The universal package can be used in lead-free and ordinary process lines.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1123-A
41
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
References
Standards Documents
This is a list of the standards abbreviations appearing in this document.
Abbreviation
HDMI
HCTS
Standards publication, organization, and date
High Definition Multimedia Interface, Revision 1.4, HDMI Consortium
HDMI Compliance Test Specification, Revision 1.4, HDMI Consortium
MHL
HDCP
MHL (Mobile High-definition Link) Specification, Revision 2.1, MHL, LLC
High-bandwidth Digital Content Protection, Revision 1.4, Digital-Content Protection, LLC
DVI
E-EDID
CEA-861-D
Digital Visual Interface, Revision 1.0, Digital Display Working Group; April 1999
Enhanced Extended Display Identification Data Standard, Release A Revision 1, VESA; Feb. 2000
A DTV Profile For Uncompressed High Speed Digital Interfaces, EIA/CEA; July 2006
EDDC
2
IC
Enhanced Display Data Channel Standard, Version 1, VESA; September 1999
2
The I C Bus Specification, Version 2.1, Philips Semiconductors, January 2000
For information on the specifications that apply to this document, contact the responsible standards groups appearing
on this list.
Standards Group
ANSI/EIA/CEA
VESA
Web URL
http://global.ihs.com
http://www.vesa.org
DVI
HDCP
http://www.ddwg.org
http://www.digital-cp.com
HDMI
MHL
http://www.hdmi.org
http://www.mhlconsortium.org
Lattice Semiconductor Documents
This is a list of the related documents that are available from your Lattice Semiconductor sales representative. The
Programmer Reference requires an NDA with Lattice Semiconductor.
Document
SiI-PR-1093
Title
SiI8788 Analog Video Processor Programmer Reference
SiI-AN-0129
SiI-PR-0041
SiI-AN-1108
PCB Layout Guidelines: Designing with Exposed Pads
CEC Programming Interface (CPI) Programmer's Reference
SiI8784 and SiI8788 Supported SPI Flash Memories
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
42
SiI-DS-1123-A
SiI8788 Analog Front-end Video Processor with Parallel Video Output
Data Sheet
Revision History
Revision A, March 2016
Updated to latest template.
Revision A, September 2014
First production release.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1123-A
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