SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter

SiI8784 Multi-format Analog Video
Front-end with HDMI/MHL Transmitter
Data Sheet
SiI-DS-1122-B
March 2016
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
Contents
1.
General Description ......................................................................................................................................................5
1.1. Features ................................................................................................................................................................5
1.1.1.
Analog Video Front-end ................................................................................................................................5
1.1.2.
Multi-format Video Decoder .........................................................................................................................5
1.1.3.
Video Processing ...........................................................................................................................................5
1.1.4.
HDMI/MHL Transmitter ................................................................................................................................5
1.2. Applications ..........................................................................................................................................................5
1.3. Packaging ..............................................................................................................................................................5
1.4. Temperature Range ..............................................................................................................................................5
2. Product Family ..............................................................................................................................................................6
3. Functional Description ..................................................................................................................................................7
3.1. Analog Front-end ..................................................................................................................................................8
3.1.1.
Input Multiplexer ..........................................................................................................................................8
3.1.2.
Clamp and Offset ..........................................................................................................................................9
3.1.3.
Low-pass Filter ..............................................................................................................................................9
3.1.4.
ADC with Programmable Gain Amplifier.......................................................................................................9
3.1.5.
Line Locked PLL (LLPLL) ...............................................................................................................................10
3.1.6.
Sync Slicer ...................................................................................................................................................10
3.1.7.
Video Buffer (VBUF) ....................................................................................................................................10
3.2. Video Decoder (VDC) ..........................................................................................................................................11
3.2.1.
ADCIF ...........................................................................................................................................................11
3.2.2.
Sync Processor ............................................................................................................................................13
3.2.3.
VBI Decoder ................................................................................................................................................13
3.3. Video Processing .................................................................................................................................................14
3.3.1.
Time Base Corrector ...................................................................................................................................14
3.3.2.
VBI Post Processor ......................................................................................................................................14
3.3.3.
De-interlacer and Edge Smoother...............................................................................................................14
3.3.4.
Color Processing ..........................................................................................................................................14
3.3.5.
Auto Phase Detection .................................................................................................................................14
3.3.6.
Auto Position Calibration ............................................................................................................................14
3.3.7.
Auto Gain Calibration ..................................................................................................................................14
3.4. Dual-mode HDMI/MHL Transmitter ...................................................................................................................15
3.4.1.
Video Data Capture Logic ............................................................................................................................15
3.4.2.
Video Processing Path .................................................................................................................................15
3.4.3.
Audio Data Capture and Processing Logic ..................................................................................................18
3.5. Control Logic .......................................................................................................................................................19
3.5.1.
Internal Microcontroller .............................................................................................................................19
3.5.2.
Registers......................................................................................................................................................21
2
3.5.3.
I C Bus .........................................................................................................................................................21
3.5.4.
Interrupt......................................................................................................................................................21
3.5.5.
GPIOs...........................................................................................................................................................21
4. Electrical Specifications ..............................................................................................................................................23
4.1. Absolute Maximum Conditions ..........................................................................................................................23
4.2. Normal Operating Conditions .............................................................................................................................24
4.3. ESD Specifications ...............................................................................................................................................25
4.4. DC Specifications .................................................................................................................................................26
4.5. AC Specifications .................................................................................................................................................28
4.6. Control Signal Timing Specifications ...................................................................................................................30
5. Timing Diagrams .........................................................................................................................................................31
2
5.1. I C Bus Timing Diagrams .....................................................................................................................................31
5.2. Reset Timing Diagram .........................................................................................................................................31
5.3. Audio Timing Diagrams .......................................................................................................................................32
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2
SiI-DS-1122-B
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
6.
Pin Diagram and Description ...................................................................................................................................... 33
6.1. Pin Diagram......................................................................................................................................................... 33
6.2. Pin Descriptions .................................................................................................................................................. 34
6.2.1.
AFE Pins....................................................................................................................................................... 34
6.2.2.
Audio Input Pins .......................................................................................................................................... 35
6.2.3.
Configuration and Control Pins ................................................................................................................... 36
6.2.4.
HDMI/MHL Data Pins .................................................................................................................................. 37
6.2.5.
SPI Interface Pins ........................................................................................................................................ 37
6.2.6.
Power and Ground Connections ................................................................................................................. 38
6.2.7.
Crystal Pins .................................................................................................................................................. 38
6.2.8.
Reserved Pins .............................................................................................................................................. 38
7. Design Recommendations .......................................................................................................................................... 39
7.1. Typical Connections ............................................................................................................................................ 39
7.2. Power Supplies Decoupling ................................................................................................................................ 41
7.3. High-speed HDMI/MHL TMDS Signals ................................................................................................................ 42
7.3.1.
Source Termination .................................................................................................................................... 42
7.3.2.
ESD Protection ............................................................................................................................................ 42
7.3.3.
Layout Guidelines ....................................................................................................................................... 42
7.4. EMI Considerations ............................................................................................................................................. 42
8. Packaging .................................................................................................................................................................... 43
8.1. ePad Requirements............................................................................................................................................. 43
8.2. Package Dimensions ........................................................................................................................................... 44
9. Marking Specification ................................................................................................................................................. 45
9.1. Ordering Information .......................................................................................................................................... 45
References .......................................................................................................................................................................... 46
Standards Documents..................................................................................................................................................... 46
Lattice Semiconductor Documents ................................................................................................................................. 46
Revision History .................................................................................................................................................................. 47
Figures
Figure 1.1. Typical Application of the SiI8784 Device ........................................................................................................... 5
Figure 3.1. Functional Block Diagram ................................................................................................................................... 7
Figure 3.2. Clamp and Offset ................................................................................................................................................ 9
Figure 3.3. Sync Slicers........................................................................................................................................................ 10
Figure 3.4. CVBS Processing Diagram ................................................................................................................................. 11
Figure 3.5. Component/RGB Processing Diagram .............................................................................................................. 12
Figure 3.6. Dual-mode HDMI/MHL Transmitter Diagram ................................................................................................... 15
Figure 3.7. Transmitter Video Data Processing Path Embedded Sync Decoder ................................................................. 16
Figure 3.8. External Memory Structure .............................................................................................................................. 19
2
Figure 5.1. I C Data Valid Delay (Driving Read Cycle Data) ................................................................................................. 31
Figure 5.2. Conditions for Use of RESET_N ......................................................................................................................... 31
Figure 5.3. RESET_N Minimum Timings .............................................................................................................................. 31
2
Figure 5.4. I S Timings ......................................................................................................................................................... 32
Figure 5.5. S/PDIF Timings .................................................................................................................................................. 32
Figure 6.1. Pin Diagram....................................................................................................................................................... 33
Figure 7.1.Typical Connection Diagram (MHL Output) ....................................................................................................... 39
Figure 7.2.Typical Connection Diagram (HDMI Output) ..................................................................................................... 40
Figure 7.3. Decoupling and Bypass Schematic .................................................................................................................... 41
Figure 7.4. Decoupling and Bypass Capacitor Placement ................................................................................................... 41
Figure 8.1. 88-Pin QFN Package Diagram ........................................................................................................................... 44
Figure 9.1. Marking Diagram .............................................................................................................................................. 45
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1122-B
3
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
Tables
Table 2.1. Product Selection Guide .......................................................................................................................................6
Table 3.1. Inputs Configuration with SCART Interface ..........................................................................................................8
Table 3.2. Inputs Configuration with D-Terminal Interface ..................................................................................................8
Table 3.3. Supported Standards..........................................................................................................................................13
Table 3.4. Color Space Versus Video Format ......................................................................................................................17
Table 3.5. YCbCr-to-RGB Color Space Conversion Formula ................................................................................................17
Table 3.6. Supported MCLK Frequencies ............................................................................................................................18
Table 3.7. Head Flags ..........................................................................................................................................................19
Table 3.8. Info Bytes ...........................................................................................................................................................20
Table 3.9. SPI Parameter .....................................................................................................................................................20
Table 3.10. Calibration Checksum ......................................................................................................................................20
Table 3.11. HW Configuration Data ....................................................................................................................................20
Table 3.12. 8051 Code Size .................................................................................................................................................20
Table 3.13. HW Configuration Data and Code Checksum...................................................................................................20
2
Table 3.14. Control of Transmitter I C Address with CI2CA Signal .....................................................................................21
Table 3.15. List of GPIOs .....................................................................................................................................................22
Table 4.1. Absolute Maximum Ratings ...............................................................................................................................23
Table 4.2. Normal Operating Conditions ............................................................................................................................24
Table 4.3. ESD Specifications ..............................................................................................................................................25
Table 4.4. Digital I/O Specifications ....................................................................................................................................26
Table 4.5. HDMI TMDS Output DC Specifications ...............................................................................................................26
Table 4.6. MHL TMDS Output DC Specifications.................................................................................................................27
Table 4.7. CBUS DC Specifications ......................................................................................................................................27
Table 4.8. Analog Front-end Electrical Specifications .........................................................................................................28
Table 4.9. HDMI/MHL Output AC Timing Specifications.....................................................................................................29
Table 4.10. CBUS Timing Specifications ..............................................................................................................................29
2
Table 4.11. I S Audio Input Port Timing Specifications .......................................................................................................30
Table 4.12. S/PDIF Input Port Timing Specifications ...........................................................................................................30
Table 4.13. Control Signal Timing Specifications ................................................................................................................30
Table 6.1. AFE Input/Output Pins .......................................................................................................................................34
Table 6.2. Audio Input Pins .................................................................................................................................................35
Table 6.3. Configuration and Control Pins ..........................................................................................................................36
Table 6.4. HDMI/MHL Data Pins .........................................................................................................................................37
Table 6.5. SPI Interface Pins ................................................................................................................................................37
Table 6.6. Power and Ground Connections ........................................................................................................................38
Table 6.7. Reserved Pins .....................................................................................................................................................38
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4
SiI-DS-1122-B
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet


1. General Description
The Lattice Semiconductor SiI8784 device is a high
quality, multi-format analog video decoder and
processor with an integrated dual-mode High
Definition Multimedia Interface (HDMI®)/Mobil
High-definition Link (MHL®) transmitter. A
microcontroller is integrated to reduce the system Bill
Of Materials (BOM) cost.
The SiI8784 device supports worldwide PAL, NTSC and
SECAM standards, YPbPr video signals up to 1080p @
60 Hz resolution, and RGB graphics signals from VGA
to UXGA resolutions. It also supports the SCART
interface with Fast Blanking and the D-Terminal.
This device contains a Time Base Correction (TBC)
module, a de-interlacer with a post-processor engine,
and a VBI decoder. For content protected analog
videos, HDCP will automatically be enabled on the
HDMI or MHL output.
1.1. Features
1.1.1. Analog Video Front-end



Four 10-bit Analog to Digital Convertors (ADC)
sampling up to 170 MHz
Flexible input multiplexers to support composite,
component, VGA, SCART with Fast Blanking and
D-Terminal interfaces
Supports cable plug-in detection and active video
signal detection

Supports RGB graphics from VGA to UXGA
Supports Macrovision Type I, II, III copy protection
detection
Supports multi-standard VBI decoding: Teletext,
WSS, VPS, CC, CGMS, and V-CHIP
1.1.3. Video Processing



Time Base Correction
De-interlacer with Edge Smoothing
Automatic Phase/Position Detection
1.1.4. HDMI/MHL Transmitter







Selectable HDMI/MHL Dual-mode
Compliant with HDMI 1.4b and MHL 2.1
specifications
HDMI output up to 1080p @ 60 Hz or
UXGA @ 60 Hz resolution
MHL output up to 1080p @ 60 Hz resolution
HDCP 1.4
2
Audio insertion with I S/ SPDIF input
VBI data forwarding over HDMI/MHL
1.2. Applications
The SiI8784 device is targeted for the Digital TV (DTV)
market.
1.3. Packaging


88-pin QFN with exposed pad (ePad)
10 mm × 10 mm × 0.9 mm
1.1.2. Multi-format Video Decoder



Automatic format detection
Supports NTSC, PAL, and SECAM standards of
composite input with adaptive comb filter
Supports 240p, 480i/p, 576i/p, 720p, 1080i/p
component video
1.4. Temperature Range

0 C to +70 C
CVBS
YPbPr
VGA
HDMI/MHL
SiI8784
SCART
D-Terminal
DTV
Audio
Audio
ADC
SPI
Flash
Figure 1.1. Typical Application of the SiI8784 Device
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1122-B
5
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
2. Product Family
A comparison of the features between the SiI8784 device and the SiI8788 device is shown in Table 2.1.
Table 2.1. Product Selection Guide
Feature
SiI8784
Sil8788
Analog Video Input
Component (YPbPr)
Composite (CVBS)
YES
YES
YES
YES
D-Terminal
YES
NO
RGB graphics (VGA)
YES
NO
SCART with Fast Blanking
YES
NO
Digital Video Output
Parallel
HDMI
NO
YES
YES
NO
MHL
Audio Input
YES
NO
SPDIF Input
2
I S Input
Package
YES
YES
NO
NO
Package Type
Pin Count
QFN
88
QFN
88
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
6
SiI-DS-1122-B
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
3. Functional Description
The SiI8784 device has four subblocks in its signal path and one control block: Analog Front-end (AFE), Video Decoder
(VDC), Video Processing, HDMI/MHL transmitter and Control Logic. Figure 3.1 shows the block diagram.
CVBS0
LPF
PGA+ADC
GRN0
GRN1
GRN2
Clamp
Offset
LPF
PGA+ADC
BLU0
BLU1
BLU2
Clamp
Offset
LPF
PGA+ADC
RED0
RED1
RED2
Clamp
Offset
LPF
PGA+ADC
SOG0
SOG1
HS0
SYNC SLICER
Video
Decoder
Sliced Sync
TBC
DI
APD
Sync Processor
LLPLL
VS0
HDMI/MHL
Transmitter
VBI
Post
Processor
VBI
Decoder
Clamp
Offset
CVBS1
Video Processing
ADCIF
CVBS_OUT
VDC
VBUF
AFE
ES
APC
CP
TX
PHY
HDMI
MHL
AGC
WIN
HS0
Phase
FS_LINE1
FB_LINE2
LINE3
Comparators
I2S/SPDIF
Control Logic
Registers
INT
GPIO
8051 Core
INT
I2C
Slave
I2C
M/S
SPI
Master
Boot
Loader
SCS
SCLK
SDO
SDI
OSC
LSCL
LSDA
24M
96K
Code
RAM
+
3K Data
RAM
RESET
RESET_N
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
Figure 3.1. Functional Block Diagram
Each subblock is described in the following sections.
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1122-B
7
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
3.1. Analog Front-end
The Analog Front-end (AFE) provides four input channels for CVBS, R, G, and B. Each channel includes an Input
Multiplexer, a Clamp and Offset DAC, a Programmable Low-pass Filter, and a high quality 10-bit ADC with
Programmable Gain Amplifier. In addition, there is a Line Locked PLL to generate sampling clocks for ADCs, Sync Slicers
to handle SOG signals, a set of input comparators to support SCART and D-terminal interfaces, and a CVBS output
buffer to support SCART.
3.1.1. Input Multiplexer
The SiI8784 device provides two CVBS inputs, and three R/G/B inputs for flexible configurations. Table 3.1 and
Table 3.2 show some examples.
Table 3.1. Inputs Configuration with SCART Interface
—
CVBS0
CVBS1
RED0
RED1
RED2
GRN0
GRN1
GRN2
BLU0
CVBS
BLU1
BLU2
CVBS
—
—
—
—
—
—
—
—
—
—
Component
—
—
—
Pr
—
—
Y
—
—
Pb
—
VGA
—
—
—
—
R
—
—
G
—
—
B
SCART
—
CVBS
R
—
—
G
—
—
B
—
—
Table 3.2. Inputs Configuration with D-Terminal Interface
—
CVBS0
CVBS1
RED0
RED1
RED2
GRN0
GRN1
GRN2
BLU0
BLU1
BLU2
CVBS
CVBS
—
—
—
—
—
—
—
—
—
—
Component
—
—
—
Pr
—
—
Y
—
—
Pb
—
VGA
—
—
—
—
R
—
—
G
—
—
B
D-Terminal
—
—
Pr
—
—
Y
—
—
Pb
—
—
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8
SiI-DS-1122-B
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
3.1.2. Clamp and Offset
As most of the video signals, such as CVBS, are AC coupled, their DC component is lost during the transmission. A
voltage type clamp circuit is positioned in front of each channel to restore the DC component.
Clamp
DAC
MUX
Clamp_P
Input_P
0.85V
LPF
Cext
Clamp_N
+
Input_N
Cext
Offset
DAC
Figure 3.2. Clamp and Offset
The clamp DAC output voltage is 3-bit programmable and AFE provides more accurate 10-bit ±0.5 V output offset DAC
to keep the input signal within the ADC input range. The offset level can be controlled automatically by ADCIF block of
VDC or manually by software.
3.1.3. Low-pass Filter
The Low-pass Filter (LPF) is a first order analog filter to remove the out-of-band noise from video signal. Its –3 dB
bandwidth can be set to 600 MHz (Bypass), 400 MHz, 200 MHz, 100 MHz, or 50 MHz by software. Combined together
with ADC over-sampling technology and the high order digital AA (Anti-alias) filter inside VDC, the SiI8784 device can
meet the demand of overall AA performance.
3.1.4. ADC with Programmable Gain Amplifier
The ADC samples the input video signal and converts each sample into 10 bits digital data. It supports the sampling
rates from 25 MSPS to 170 MSPS, and the sampling clock of CVBS channel can be independent with R, G, and B
channels.
For the formats with lower pixel rate, oversampling is recommended. The SiI8784 device supports 2X, 4X and 8X
oversampling.
The Programmable Gain Amplifier (PGA) in the front stage of ADC has a nominal gain range from –6 dB to +6 dB, so the
SiI8784 device can adapt to a wide range of input video signal levels, especially the CVBS signal from an RF tuner. The
PGA can be controlled either automatically by the gain control function of VDC or manually by software.
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1122-B
9
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
3.1.5. Line Locked PLL (LLPLL)
The Line Locked PLL (LLPLL) is designed to generate the ADC sampling clock, i.e. pixel clock or oversampled pixel clock.
It can be synchronized with a slower reference HSync pulses or run at a fixed frequency. The allowable input HSync
range is from 15 kHz to 150 kHz, and the output pixel clock range is from 25 MHz to 170 MHz.
The LLPLL contains a high performance programmable digital PLL (DPLL) and an analog PLL (APLL) which generates the
high frequency reference clock needed by the DPLL from the 24 MHz crystal frequency.
The relative phase between the input sync pulse and the output clock of LLPLL can be adjusted in 32 steps by setting
registers or automatically by the Auto Phase Detection (APD) block of the video processing module.
3.1.6. Sync Slicer
MUX
Clamp
MUX
HS0
HS1*
HS2*
HS3*
Clamp
MUX
SOG0
SOG1
SOG2*
SOG3*
MUX
The Sync Slicer converts SOG and HSYNC signals into core domain digital signals. As shown in Figure 3.3, there are two
sets of SOG slicers, each of contains an input multiplexer, a bottom level (0.5 V) clamp, a low pass filter, and a
comparator. The comparator threshold is programmable. Also, there are two sets of HS slicers for TTL level syncs.
When one of the slicers is configured as an active input, the other can be used to detect the activity of other inputs.
This feature is helpful to implement the active channel detection and auto-switch functions.
LPF
0.525V~1V
COMP
SOG_
A
0.525V~1V
COMP
SOG
_B
1.25V
COMP
HS_
A
1.25V
COMP
HS_
B
LPF
*: Not available
Figure 3.3. Sync Slicers
3.1.7. Video Buffer (VBUF)
The Video Buffer (VBUF) buffers and outputs the selected CVBS input signal. This feature is useful to implement the
CVBS return channel of the SCART interface. VBUF includes two major subblocks: clamp and voltage-to-current
conversion. The Voltage-to-current conversion subblock converts the input signal to the output current which is
proportional to the signal voltage level. A 75 Ω source termination resistor should be connected to the CVBS_OUT
output pin and signal ground.
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
10
SiI-DS-1122-B
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
3.2. Video Decoder (VDC)
The SiI8784 device provides a multi-format video decoder. VDC includes ADCIF, Sync Processor, adaptive 2D Comb
decoder, and VBI Decoder blocks as shown in Figure 3.1 on page 7.
3.2.1. ADCIF
The ADCIF logic block contains Automatic Gain Control and Offset Calibration, and Anti-alias filtering and decimation
subblocks. It also generates clamp pulses for clamp circuits at the proper time so that ADC is able to digitize the input
analog within the proper range. The main indicator used to determine where the clamping position should be is the
horizontal synchronization pulse coming from the Sync Processor block. Since this filtered HSync pulse may not always
be correct, several layers of logic have been developed to ensure the clamping is not done at an incorrect position.
3.2.1.1. Automatic Gain Control and Offset Calibration
Parameters such as Sync Amplitude, Back Porch Levels are measured based on the HSync position, register controls,
and logic executed in the Offset Gain Calculations sub block. These measured values are then used in determining the
offset and gain adjustments. To ensure the stability and accuracy of digitized video signal, several control loops are
built in the ADCIF block. These loops include Clamp, Coast, Gain, and Offset. The Clamp and Coast pulses, Gain and
Offset parameters are generated by the ADCIF logic and directly connected to the AFE.
3.2.1.2. Anti-alias Filtering and Decimation
The Anti-aliasing (AA) filters remove high frequency noise from the raw digitized signals produced by the front-end
video ADCs, and decimate the over-sampled video signal.
The AA filter has flexibility in the frequency response, sharp transition bandwidth, and good stop band attenuation. The
AA filter allows the software to change the bandwidth of the filters as the signal conditions changes.
3.2.1.3. Video Decoder
Video Decoder block processes both CVBS data stream and component/RGB data stream. It also supports the SCART
Fast Blanking functions.
3.2.1.4. CVBS Processing
CVBS Processing involves the Standard Detection, 2D Video Decoder, and Sync Processor subblocks, as shown in
Figure 3.4 below.
ADCIF
CVBS Processing
Standard
Detection
AA Filter
PAL/NTSC/
SECAM
Video Decoder
Hs,Vs
10 bit
CVBS
Data
Sync Processor
Figure 3.4. CVBS Processing Diagram
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1122-B
11
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
The SiI8784 device can automatically detect NTSC (M/J/4.43), PAL (B/D/I/G/H/60/M/N/Nc), and SECAM (B/D/G/L/K)
standards, and decode them properly.
An adaptive 2D comb filter is used in video decoder. The 2D comb filter has three output options, only horizontal filter,
only vertical filter and blending of horizontal and vertical filter. When the current sample is on a horizontal transition
edge, the vertical filter is selected. When the current sample is on a vertical transition edge, the horizontal filter is
selected. When it is not one of the above two phenomenon, the blending output is selected.
When the input signal is lost, the SiI8784 device can operate in a free-running mode to ensure a stable output.
3.2.1.5. Component/RGB Processing
Component/RGB Processing processes Component Video and RGB Graphics. Component Video Processing includes
Sync Processor. Figure 3.5 shows the block diagram of the component video and RGB Graphics processing. The
following sections explain each of the blocks in detail.
ADCIF
10 bit
YUV/RGB
Data
AA Filter
10 bit
YUV/RGB
Data
AA Filter
10 bit
YUV/RGB
Data
AA Filter
AFE
SOG0/1
HS0
Component/RGB Processing
SYNC SLICER
sliced sync
Sync Processor
hsync reference
LLPLL
Figure 3.5. Component/RGB Processing Diagram
The SiI8784 device supports 480i/576i, 480p/576p, 720p, 1080i, and 1080p for standard and high definition resolutions.
The SiI8784 device supports PC resolutions up to 1600 x 1200 @ 60 Hz (UXGA).
3.2.1.6. SCART Fast Blanking
VDC is designed to support SCART interface: Composite, RGB, and Fast Blanking.
The 4 channel 10-bit ADCs in AFE are mapped to CVBS, RED, GRN, and BLU inputs of SCART interface. A color space
converter converts the digitized RGB data from RGB to YUV (BT601). Then the YUV data are resampled from 108 MHz
to the 8Fsc frequency used in the 2D comb filter, and meanwhile the YUV444 data are converted to YUV422. These
YUV422 data matched the timing of the 2D comb filter output 8Fsc Y/C data, and the two data streams are blended
together according to the FB signal information, which indicates the current display source is from original RGB or
Composite inputs.
The SCART_ASPECT information is from ASPECT0/1 comparator outputs of AFE, and their results are read-only status
registers which can be handled by software.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
12
SiI-DS-1122-B
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
3.2.2. Sync Processor
The Sync Processor block contains sophisticated digital circuitry that analyzes and extracts synchronization pulses from
the incoming video stream. It generates filtered vertical and horizontal sync pulses. The Sync Processor includes Sync
separation, format detection, and Sync stabilization.

Sync Separation
The Sync Separation separates the HSync and VSync from the composite sync sliced from video decoder or SOG slicer.

Sync Stabilization
Sync Stabilization does de-glitch, removes serration, and equalizes pulses from the sync signal. It also detects
Macrovision protection status.
 Format Detection
The format detection detects vertical period and horizontal period and total line number per field.
3.2.3. VBI Decoder
The VBI Processing block slices and processes digitized VBI data from the video. Following are some of the features of
the VBI block:




108 MHz operating with programmable down sampling
Supports PAL standards
Supports NTSC standards
Enhanced Teletext parity and hamming 8/4 correction
Table 3.3 shows the supported VBI standards.
Table 3.3. Supported Standards
VBI Standard
Video
Standard
Data Rate
Scan
Lines
Data per
Line
Encoding
Description
14 Bits
Phase Encoding.
Each bit is transmitted
using 6 bits of
encoded data.
Wide Screen Signaling.
Used for aspect ratio settings.
WSS 625
PAL SECAM
5 MHz
23
336
VPS
PAL SECAM
5 MHz
16
13 Bytes
Biphase Encoding.
Each bit is effectively
represented by 2 bits.
Video Programming System.
Used in Germany for
program/broadcast info.
CC
NTSC
0.5030 MHz
21
2 Bytes
Parity.
Closed Captioning for the hearing
impaired.
XDS
VChip
NTSC
0.5035 MHz
284
2 Bytes
Parity.
Extended Data Service.
Used for MISC. NTSC services.
WSS 525
ID-1
CGMS
NTSC
0.4474 MHz
20
14 Bits
CRC.
Copy Guard Management System.
Used for copy protection and
aspect ratio.
Teletext
PAL
SECAM
6.9375 MHz
6-22
318-334
42 Bytes
Encoded using parity,
hamming 8/4 and
hamming 24/18.
Teletext.
Used for data transmissions in
Europe.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1122-B
13
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
3.3. Video Processing
The video processing block performs some necessary processing functions to the decoded video streams before they
are outputted. There are also some measurement blocks inside to implement automatic Phase/Position/Gain
adjustment functions.
3.3.1. Time Base Corrector
The Time Base Corrector (TBC) is designed to provide stable clock and video data for HDMI/MHL output. It uses a line
buffer based architecture in lieu of a frame buffer to save cost and power. To keep HDMI/MHL output TMDS clock jitter
in a safe range, the TBC output field frequency is limited to 50 Hz ±0.5% or 59.94 Hz/60 Hz ±0.5% as default. If the field
frequency of input video is beyond this range, the display will be scrolling.
Composite video formats are supported by the TBC. 480i/576i component formats can be supported by the TBC if
needed.
3.3.2. VBI Post Processor
The VBI Post Processor is used to transmit VBI data to DTV over the HDMI/MHL connection.
In case the raw VBI data i.e. digitized luma portion of the incoming video signal, or Teletext need to be transmitted to
DTV over HDMI/MHL, they are embedded into the video stream and transmitted. As the decoded VBI data, they can be
transmitted over HDMI or MHL using Vendor Specific Info Frame (VSIF).
3.3.3. De-interlacer and Edge Smoother
De-interlacing is designed to convert an interlaced (480i/576i) video signal to a progressive (480p/576p) video signal.
BOB de-interlacing method is adopted to reduce cost and power consumption. An edge smoother is included to reduce
the saw tooth artifacts generated by de-interlacing and to improve the picture quality.
The de-interlacer and edge smoother must be used together with the TBC.
3.3.4. Color Processing
Color Processing (CP) enables brightness, contrast, saturation, and hue controls for end users. It supports YCbCr color
space only.
3.3.5. Auto Phase Detection
The Auto Phase Detection (APD) is a module used to search for the phases that can generate the best display quality.
The desired phases, in general, can generate sharp and stable images, if the input image meets certain criteria during
phase detection period. APD is an automatic algorithm that can be enabled or disabled by software. It can be applied to
both VGA and Component inputs.
3.3.6. Auto Position Calibration
The Auto Position Calibration (APC) detects the active picture area of input video signal and adjusts the output timing
so that the final picture can fit to the display properly.
3.3.7. Auto Gain Calibration
Slight mismatch of analog input channels including offset and gain may impact the picture quality. The SiI8784 device
has been designed to keep the mismatches in an acceptable range (<0.5 dB). It is still important to calibrate these
mismatches in some cases to achieve the most accurate picture. To help manufacturers finish this process efficiently,
an Auto Gain Calibration (AGCWIN) mechanism is designed in the SiI8784 device. This mechanism automatically
measures the digitalized signal levels through the AGCWIN module, calculates the correct values, and stores them into
the external SPI Flash memory. These values can be used by firmware in user mode to compensate the analog
mismatches.
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
14
SiI-DS-1122-B
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
3.4. Dual-mode HDMI/MHL Transmitter
The SiI8784 device incorporates the latest HDMI 1.4 and MHL 2 dual-mode transmitter. It multiplexes video and audio
data into the HDMI/MHL stream and performs TMDS encoding. It contains digital video data capture and its processing
block, digital audio data capture and its processing block, HDMI/MHL transmitter, and PHY. Figure 3.6 shows the
dual-mode HDMI/MHL transmitter diagram.
DSDA
DDC
DDC Master
Master
Configuration
Configuration
And
And
Control
Control Block
Block
DSCL
INT
Interrupt
Interrupt and
and
Hot
Hot Plug
Plug Logic
Logic
HPD
CBUS
VIDEO
INPUT
Video
Video
Data
Data
Capture
Capture
Video
Video
Processing
Processing
TXC+/-
HDMI/MHL
HDMI/MHL
Tx
Tx PHY
PHY
TX0+/(MHLD, MHLDB)
TX1+/-
AUDIO
INPUT
Audio
Audio
Data
Data
Capture
Capture
Audio
Audio
Processing
Processing
TX2+/-
Figure 3.6. Dual-mode HDMI/MHL Transmitter Diagram
3.4.1. Video Data Capture Logic
The Video Data Capture Logic receives uncompressed digital video with a data width of 8 to 24 bits from the digital
parallel video interface. The bus configurations support most standard video input formats as well as other widely used
non-standard formats.
3.4.2. Video Processing Path
Figure 3.7 shows the video data processing stages. Each of the processing blocks can be bypassed by setting the
appropriate register bits.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1122-B
15
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
IDCK
Clock
Data
Embedded
Sync
Decoder
D[35:0]
Video
Data
Capture
DE
Conbiner
HS,VS
DE
HS,VS
HSYNC
VSYNC
DE
422 to 444
Upsample
YCbCr to
RGB
bypass 422
bypass CSC
DE
Generator
external DE
RGB
Range
Expansion
RGB to
YCbCr
RGB/YCbCr
Range
Compression
444 to 422
Decimation
Clipping
Dither
bypass Expansion
bypass CSC
bypass Compression
bypass 444
bypass Clipping
bypass Dither
HDCP
XOR
Mask
TMDS
Figure 3.7. Transmitter Video Data Processing Path Embedded Sync Decoder
The input processor can create DE, HSYNC, and VSYNC signals using the start of active video (SAV) and end of active
video (EAV) codes within the ITU-R BT.656-format video stream.
3.4.2.1. Data Enable Generator
The transmitter includes logic to construct a DE signal from the incoming HSYNC, VSYNC, and clock. Registers are
programmed to enable the DE signal to define the size of the active display region.
3.4.2.2. Combiner
The clock, data, and sync information is combined into a complete set of signals required for TMDS encoding. From
here, the signals are manipulated by the register-selected video processing blocks.
3.4.2.3. 422 to 444 Up-sampler
Chrominance up-sampling and down-sampling increase or decrease the number of chrominance samples in each line of
video. Up-sampling doubles the number of chrominance samples in each line, converting 4:2:2 sampled video to 4:4:4
sampled video.
3.4.2.4. 444 to 422 Decimation
Decimation reduces the number of chrominance samples in each line by half, converting 4:4:4 sampled video to 4:2:2
video.
3.4.2.5. Color Space Converters (CSC)
Two color space converters (CSCs) (YCbCr to RGB and RGB to YCbCr) are available to interface to the many video
formats supplied by A/V processors and to provide full DVI backward compatibility. The CSC can be adjusted to perform
standard-definition conversions (ITU.601) or high-definition conversions (ITU.709) by setting the appropriate registers.
RGB to YCbCr
The RGBYCbCr color space converter can convert from video data RGB to standard definition or to high definition
YCbCr formats. The HDMI AVI packet defines the color space of the incoming video.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
16
SiI-DS-1122-B
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
Table 3.4. Color Space Versus Video Format
Video Format
Conversion
640 x 480
480i
ITU-R BT.601
ITU-R BT.601
576i
480p
ITU-R BT.601
ITU-R BT.601
576p
240p
ITU-R BT.601
ITU-R BT.601
288p
720p
1080i
ITU-R BT.601
ITU-R BT.709
ITU-R BT.709
1080p
ITU-R BT.709
Formulas
CE Mode 16-235 RGB
Y = 0.299R′ + 0.587G′ + 0.114B′
Cb = –0.172R′ – 0.339G′ + 0.511B′ + 128
Cr = 0.511R′ – 0.428G′ – 0.083B′ + 128
Y = 0.213R′ + 0.715G′ + 0.072B′
Cb = –0.117R′ – 0.394G′ + 0.511B′ + 128
Cr = 0.511R′ – 0.464G′ – 0.047B′ + 128
YCbCr to RGB
The YCbCrRGB color space converter allows MPEG decoders to interface with RGB-only inputs. The CSC can convert
from YCbCr in standard-definition (ITU.601) or high-definition (ITU.709) to RGB. Refer to Table 3.5 for the detailed
formulas. Note the difference between RGB range for CE modes and PC modes.
Table 3.5. YCbCr-to-RGB Color Space Conversion Formula
Format Change
Conversion
1
2, 3
YCbCr 16-235 Input
to
2, 3
RGB 16-235 Output
2, 3
YCbCr 16-235 Input
to
2, 3
RGB 0-255 Output
601
1
709
601
709
YCbCr Input Color Range 2, 3
R′ = Y + 1.371(Cr – 128)
G′ = Y – 0.698(Cr – 128) – 0.336(Cb – 128)
B′ = Y + 1.732(Cb – 128)
R′ = Y + 1.540(Cr – 128)
G′ = Y – 0.459(Cr – 128) – 0.183(Cb – 128)
B′ = Y + 1.816(Cb – 128)
R′ = 1.164((Y-16) + 1.371(Cr – 128))
G′ = 1.164((Y-16) – 0.698(Cr – 128) – 0.336(Cb – 128))
B′ = 1.164((Y-16) + 1.732(Cb – 128))
R′ = 1.164((Y-16) + 1.540(Cr – 128))
G′ = 1.164((Y-16) – 0.459(Cr – 128) – 0.183(Cb – 128))
B′ = 1.164((Y-16) + 1.816(Cb – 128))
Notes:
1. No clipping can be done.
2. For 10-bit deep color, all occurrences of the values 16, 128, 235, and 255 should be multiplied by 4.
3. For 12-bit deep color, all occurrences of the values 16, 128, 235, and 255 should be multiplied by 16.
3.4.2.6. RGB Range Expansion
The SiI8784 input processor can scale the input color from limited-range into full-range using the range expansion
block. When enabled by itself, the range expansion block expands 16 – 235 limited-range data into 0 – 255 for each
video channel. When the range expansion and the YCbCr to RGB color space converter are both enabled, the input
conversion range for the Cb and Cr channels is 16 – 240.
3.4.2.7. RGB/YCbCr Range Compression
When enabled by itself, the Range Compression Block compresses 0 – 255 full-range data into 16 – 235 limited-range
data for each video channel. When enabled with the RGB to YCbCr converter, this block compresses to 16 – 240 for the
Cb and Cr channels. The color range scaling is linear.
3.4.2.8. Clipping
The clipping block, when enabled, clips the values of the output video to 16 – 235 for RGB video or the Y channel, and
to 16 – 240 for the Cb and Cr channels.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1122-B
17
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
3.4.2.9. Dither
The dither block dithers internally processed data to 8, 10, or 12 bits for output on the HDMI link.
3.4.2.10. HDCP Encryption Engine/XOR Mask
The HDCP encryption engine contains the logic necessary to encrypt the incoming audio and video data and includes
support for HDCP authentication and repeater checks. The system microcontroller or microprocessor controls the
encryption process by using a set sequence of register reads and writes. An algorithm uses HDCP keys and a Key
Selector Value (KSV) stored in the on-board ROM to calculate a number that is then applied to an XOR mask. This
process encrypts the audio and video data on a pixel-by-pixel basis during each clock cycle.
3.4.2.11. TMDS Digital Core
The TMDS digital core performs 8-to-10-bit TMDS encoding on the data received from the HDCP XOR mask. This data is
sent to three TMDS differential data lines, along with a TMDS differential clock line. A resistor tied to the EXT_SWING
pin controls the TMDS swing amplitude.
3.4.3. Audio Data Capture and Processing Logic
2
The SiI8784 device accepts digital audio over an S/PDIF interface, four I S inputs, or eight one-bit audio inputs.
3.4.3.1. S/PDIF
The S/PDIF stream can carry 2-channel uncompressed PCM data (IEC 60958) or a compressed bit stream for
multi-channel (IEC 61937) formats. The audio data capture logic forms the audio data into packets described in the
HDMI Specification. The S/PDIF input supports audio sampling (Fs) rates from 32 to 192 kHz. A separate master clock
input (MCLK), coherent with the S/PDIF input, is required for time-stamping purposes. Coherent means that the MCLK
and S/PDIF have been created from the same clock source. This step usually uses the original MCLK to strobe out the
S/PDIF from the sourcing chip. There is no setup or hold timing requirement on an input with respect to MCLK.
2
3.4.3.2. I S
2
Four I S inputs allow transmission of DVD-Audio or decoded Dolby Digital to A/V receivers and high-end displays. The
interface works in slave mode, supports sample rate up to 192 kHz.
Register control allows the audio data to be down-sampled by one-half or one-fourth, so that the transmitter can be
compatible with the attached display that supports lower sample rate audio only. Conversions from 192 to 48 kHz,
from 176.4 to 44.1 kHz, from 96 to 48 kHz, and from 88.2 to 44.1 kHz are supported. Audio data can only be downsampled on 2-channel audio.
The appropriate registers must be configured to describe the audio format provided to the SiI8784 input processor.
This information is passed over the HDMI link in the CEA-861D Audio Info (AI) packets.
Table 3.6 shows the MCLK frequencies that support seven audio sample rates.
Table 3.6. Supported MCLK Frequencies
2
I S and S/PDIF Supported MCLK Rates
Audio Sample Rate, Fs
Multiple of Fs
128
192
32 kHz
4.096 MHz
6.144 MHz
44.1 kHz
5.645 MHz
8.467 MHz
48 kHz
6.144 MHz
9.216 MHz
88.2 kHz
11.290 MHz
16.934 MHz
96 kHz
12.288 MHz
18.432 MHz
176.4 kHz
22.579 MHz
33.868 MHz
192 kHz
24.576 MHz
36.864 MHz
256
384
8.192 MHz
12.288 MHz
11.290 MHz
16.934 MHz
12.288 MHz
18.432 MHz
22.579 MHz
33.864 MHz
24.576 MHz
36.864 MHz
45.158 MHz
67.737 MHz
49.152 MHz
73.728 MHz
512
768
16.384 MHz
24.576 MHz
22.579 MHz
33.869 MHz
24.576 MHz
36.864 MHz
45.158 MHz
67.738 MHz
49.152 MHz
73.728 MHz
—
—
—
—
1024
1152
32.768 MHz
36.864 MHz
45.158 MHz
50.803 MHz
49.152 MHz
55.296 MHz
—
—
—
—
—
—
—
—
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
18
SiI-DS-1122-B
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
3.5. Control Logic
3.5.1. Internal Microcontroller
As shown in Figure 3.1 on page 7, an 8-bit 8051 compatible microcontroller is integrated in the SiI8784 device. It
contains 3 KB data RAM and 96 KB code RAM. The code can be loaded into code RAM from external SPI Flash or
EEPROM memory automatically after power on. If the check sum of the code data is correct, the code will be executed.
2
Otherwise the internal microcontroller is disabled and the chip can be controlled by external controller through I C bus.
The internal controller can access all the internal registers directly over the internal bus. The 8051 microcontroller runs
at the crystal clock of 24 MHz.
When the booting procedure is finished, the SPI interface will be handed over to the 8051 SPI module so that firmware
can read/write the external memory if needed.
2
The internal controller can also operate other peripherals through the I C bus of the SiI8784 device by setting it to the
master mode.
3.5.1.1. Data Structure of External SPI Memory
Figure 3.8 shows the memory structure which is required for the internal microcontroller to load the code correctly.
HW and CODE
Checksum
scope
FFFFH
HW Config Data and 8051
Code Checksum 4bytes
17FFFH
RSVD
8BFFH
System Calibration Data
8051 Code Content
96Kbytes SRAM
8B00H
3Kbytes SRAM DATA
8000H
RSVD
8051 Code Length 3bytes
HW Config Data 32bytes
Internal registers
29FFH
Calibration Checksum
2bytes
Calibration
Checksum
scope
HDMI/MHL Registers
2000H
RSVD
System Calibration Data
254bytes
0EFFH
VDC/VPP/AFE Registers
0200H
Info 12bytes
RSVD
Head Flag 4bytes
00000H
0100H
System Registers
0000H
8051 Code Memory
8051 Data Memory
Figure 3.8. External Memory Structure
Table 3.7. Head Flags
EEPROM/Flash Address
00000H
EEPROM/Flash Content
Head0 ‘S’
00001H
00002H
00003H
Head1 ‘I’
Head2 ‘M’
Head3 ‘G’
Note: The head flag will be four bytes ASCII code of ‘S’, ‘I’, ‘M’, ‘G’.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1122-B
19
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
Table 3.8. Info Bytes
EEPROM/Flash Address
EEPROM/Flash Content
00004H
00005H
00006H
SPI PARAMETER.
Calibration Version (low byte)
Calibration Version.
00007H
00008H
Calibration Version (high byte).
Code Version (low byte).
00009H
0000AH
Code Version.
Code Version (high byte).
0000BH
0000CH
0000DH
Reserved.
Reserved.
Reserved.
0000EH
Reserved.
0000FH
Reserved.
Note: The info bytes contain the information about the feature of Max read frequency of external EEPROM/Flash, the calibration
version, and the code version. It occupies 12 bytes.
Table 3.9. SPI Parameter
SPI Parameter
0x00
0x01
Description
2 MHz baud rate to access SPI Flash/EEPROM.
24 MHz baud rate to access SPI Flash/EEPROM.
Table 3.10. Calibration Checksum
EEPROM/Flash Address
EEPROM/Flash Content
0010EH
0010FH
Calibration Checksum (low byte).
Calibration Checksum (high byte).
Note: The calibration checksum is two bytes which locates at the last site of 256 size calibration data.
Table 3.11. HW Configuration Data
EEPROM/Flash Address
00110H
EEPROM/Flash Content
BT_SPI_PINMUX_SEL.
00H – SPI function
01H – Reserved. Don’t use
02H – Reserved. Don’t use
00111H..0012FH
Reserved.
Table 3.12. 8051 Code Size
EEPROM/Flash Address
00130H
00131H
EEPROM/Flash Content
Code Size (low byte).
Code Size.
00132H
Code Size (high byte).
Table 3.13. HW Configuration Data and Code Checksum
EEPROM/Flash Address
00133H + code size
00134H + code size
EEPROM/Flash Content
Code Checksum0 (lowest byte).
Code Checksum1.
00135H + code size
00136H + code size
Code Checksum2.
Code Checksum3 (highest byte).
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
20
SiI-DS-1122-B
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
The boot module tries to load data from external device and write into chip SRAM. The 8051 code content is written
into the 96K bytes SRAM of 8051. The 256 system calibration is written into the high 3 K bytes SRAM in data memory.
For details on the selection of the SPI Flash memory, refer to the relevant Application Note (SiI-AN-1108).
3.5.2. Registers
The register block incorporates all the registers required for configuring and managing the SiI8784 device. These
registers are used to perform AFE processing, VDC processing, MHL/HDMI processing, and all other control functions.
3.5.3. I2C Bus
2
2
The local I C slave bus provides the host with communication to the entire system. The controller I C interface on the
SiI8784 device (signals CSCL and CSDA) is a slave interface, which is capable of running up to 400 kHz.
2
All functions of the SiI8784 device are controlled and observed with I C registers. Device addresses can be altered with
the level of the CI2CA signal. Table 3.14 shows the device addresses as altered by the level of the CI2CA signal.
2
Table 3.14. Control of Transmitter I C Address with CI2CA Signal
CI2CA = 0
CI2CA = 1
Purpose
0x8C
0x8E
0x84
0x84
0x86
0x86
0x8A
0x8A
0x92
0x92
0x96
0x96
0xDA
0xDA
0x9C
0x9C
0xD8
0xD8
0x72
0x76
0x7A
0x90
0x7E
0x94
TX Page 1
Reserved
0xC0
0x60
0xC4
0x60
CEC 1.6
TX PHY
System Control and Status
VD_DPGA
VD_SIGNALROUTING
VD_VBI
VD_VDREG
VD_ADCIF
VD_SYNCPROC
VD_ADCSTATUS
VD_VPP
Edge Smooth
INT
FPGA
APD
ADC_WIN
VidPath
Calibration
AFE
HW_TPI
TX Page 0/2
0xC8
0xCC
CBUS
2
Note: When the internal microcontroller is enabled, the I C bus is taken over by the firmware. It can work as both master and slave
mode, and the addresses are alterable.
3.5.4. Interrupt
The SiI8784 device contains a configurable interrupt generator with an open-drain type output pin. It can be used to
notify application processor (if there is application processor) to handle some events.
3.5.5. GPIOs
There are five general purpose IO pins on the SiI8784 device. Generally they can be used to detect the cable plug-in
status, but they can be used for other purposes as well.
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1122-B
21
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
Table 3.15. List of GPIOs
Name
2
Type
Pull up/down
Reset Status
1
GPIO0
GPIO1
GPIO2
IO
IO
IO
Pull down
Pull up
Pull up
I
I
I
GPIO3
GPIO4
IO
IO
Pull up
Pull up
I
I
Notes:
2
1. GPIO0 is also used as CI2CA pin to decide the I C slave address during reset.
2. The internal Pull up/down resistors are fixed and weak just to avoid floating input level when they are left unconnected.
Peripheral circuits should not rely on them. 10 K or smaller resistors are recommended for external pull up/down circuit to
override them if needed.
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
22
SiI-DS-1122-B
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
4. Electrical Specifications
4.1. Absolute Maximum Conditions
Table 4.1. Absolute Maximum Ratings
Symbol
Parameter
Min
Typ
Max
Units
Notes
VP2V5A
Analog Power for ADC
–0.3
—
3.0
V
1, 2
VP2V5D
Digital Power for ADC
–0.3
—
3.0
V
1, 2
VP2V5_SLICER
Analog Power for SOG Slicer
–0.3
—
3.0
V
1, 2
VP1V0_PLL
Power for APLL and LLPLL
–0.3
—
1.2
V
1, 2
VCC10_TPLL
TCI PLL Power
–0.3
—
1.2
V
1, 2
AVCC_PLL
Analog PLL Power of HDMI/MHLTX
–0.3
—
1.2
V
1, 2
AVCC
Power for HDMI/MHL TX
–0.3
—
1.2
V
1, 2
AVCC3V3_CBUS
Power for CBUS I/O
–0.3
—
4.0
V
1, 2
CVCC10
Power for Digital Core
–0.3
—
1.2
V
1, 2
VDDIO3V3
Power for Digital I/O
–0.3
—
4.0
V
1, 2
XTALVCC33
Power for XTAL
–0.3
—
4.0
V
1, 2
VI
Digital Input Voltage
–0.3
—
VDDIO + 0.3
V
1, 2
VO
Digital Output Voltage
–0.3
—
VDDIO + 0.3
V
1, 2
AVI
Analog Input Voltage
-0.3
—
VP2V5A + 0.3
V
1, 2
V5V-Tolerant
Input Voltage on 5 V Tolerant Pins
–0.3
—
5.5
V
—
TJ
Junction Temperature
—
—
125
C
—
TSTG
Storage Temperature
–65
—
150
C
—
Notes:
1. Permanent device damage can occur if absolute maximum conditions are exceeded.
2. Functional operation should be restricted to the conditions described under normal operating conditions.
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1122-B
23
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
4.2. Normal Operating Conditions
Table 4.2. Normal Operating Conditions
Symbol
Parameter
VP2V5A
Analog Power for ADC
IVP2V5A
Total Current Consumption of VP2V5A
VP2V5D
Digital Power for ADC
Min
Typ
Max
Units
Notes
2.375
2.50
2.625
V
2
—
—
—
—
350
90
260
260
—
—
—
—
mA
mA
mA
mA
4, 8
5, 8
6, 8
7, 8
2.375
2.50
2.625
V
—
—
—
—
—
9
2.5
9
10
—
—
—
—
mA
mA
mA
mA
4, 8
5, 8
6, 8
7, 8
2.375
2.50
2.625
V
2
—
3
—
mA
6, 8
0.95
1.00
1.05
V
3
—
20
—
mA
7, 8
0.95
1.00
1.05
V
3
—
3.5
—
mA
5, 8
IVP2V5D
Total Current Consumption of VP2V5D
VP2V5_SLICER
Analog Power for SOG Slicer
IVP2V5_SLICER
Current Consumption of VP2V5_SLICER
VP1V0_PLL
Power for APLL and LLPLL
IVP1V0_PLL
Current Consumption of VP1V0_PLL
VCC10_TPLL
TCI PLL Power
IVCC10_TPLL
Current Consumption of VCC10_TPLL
AVCC_PLL
Analog PLL Power of HDMI/MHLTX
0.95
1.00
1.05
V
3
IAVCC_PLL
Current Consumption of AVCC_PLL
—
—
4.5
8.5
—
—
mA
mA
7, 8
6, 9
AVCC
Power for HDMI/MHL TX
0.95
1.00
1.05
V
—
—
—
4.5
10
—
—
mA
mA
7, 8
6, 9
0.95
1.00
1.05
V
—
—
—
—
—
—
—
—
70
65
80
85
85
70
100
—
—
—
—
—
—
—
mA
mA
mA
mA
mA
mA
mA
4, 8
5, 8
6, 8
7, 8
4, 9
5, 9
6, 9
3.135
3.30
3.465
V
—
—
—
—
—
—
—
—
2
2
7
8
40
55
60
—
—
—
—
—
—
—
mA
mA
mA
mA
mA
mA
mA
4, 8
5, 8
6, 8
7, 8
4, 9
5, 9
6, 9
3.135
3.30
3.465
V
—
IAVCC
Current Consumption of AVCC
CVCC10
Power for Digital Core
ICVCC10
Total Current Consumption of CVCC10
VDDIO3V3
Power for Digital I/O
IVDDIO3V3
Current Consumption of VDDIO3V3
AVCC3V3_CBUS
Power for CBUS I/O
IAVCC3V3_CBUS
Current Consumption of AVCC3V3_CBUS
XTALVCC33
Power for XTAL
IXTALVCC33
TA
ja
—
8
—
mA
6, 9
3.135
3.30
3.465
V
—
Current Consumption of XTALVCC33
—
3.5
—
mA
6, 8
Ambient Temperature (with power applied)
0
25
70
C
—
Ambient Thermal Resistance (Theta JA)
—
—
25.6
C/W
1
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
24
SiI-DS-1122-B
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
Table 4.2. Normal Operating Conditions (Continued)
Symbol
Parameter
jc
Case Thermal Resistance (Theta JC)
Min
Typ
Max
Units
Notes
—
—
11.9
—
—
Notes:
1. Airflow at 0 m/s. Package ePad soldered to PCB.
2. The power ripple must be below 60 mVpp to avoid video quality detrition.
3. Avoid any noise coupling to PLL power rails.
4. Measured with SCART input.
5. Measured with CVBS input.
6. Measured with YPbPr 1080p60 input.
7. Measured with UXGA60 input.
8. HDMI output mode.
9. MHL output mode.
4.3. ESD Specifications
Table 4.3. ESD Specifications
Symbol
Parameter
Min
Typ
Max
Units
Notes
Latch up
HBM
ESD Latch up
Human Body Model
± 200
2000
—
—
—
—
mA
V
1, 2
3
200
500
—
—
—
—
V
V
4
5
MM
Machine Model
CDM
Charged Device Model
Notes:
1. At 70 °C.
2. Measured as per JESD78B standard.
3. Measured as per JESD22-A114 standard.
4. Measured as per JESD22-A115 standard.
5. Measured as per JESD22-C101 standard.
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1122-B
25
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
4.4. DC Specifications
Table 4.4. Digital I/O Specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Notes
Digital Inputs
VIL
Input Low Voltage
—
—
—
0.8
V
1
VIH
Input High Voltage
—
2.0
—
—
V
1
VTH+
Schmitt Trigger LOW to HIGH Threshold
—
1.61
1.69
1.77
V
1
VTH-
Schmitt Trigger HIGH to LOW threshold
—
1.18
1.27
1.35
V
1
IIL
Input Leakage Current
—
–10
—
10
A
1
RPU
Pull-up Resistor
—
27
38
59
KΩ
1
RPD
Pull-down Resistor
—
31
46
80
KΩ
1
VTH+DDC
Schmitt Trigger LOW to HIGH Threshold of
DSCL and DSDA Pins
—
3
—
—
V
—
VTH-DDC
Schmitt Trigger HIGH to LOW Threshold of
DSCL and DSDA Pins
—
—
—
1.5
V
—
VTH+CEC
Schmitt Trigger LOW to HIGH Threshold of
CEC Pin
—
2
—
—
V
—
VTH-CEC
Schmitt Trigger HIGH to LOW Threshold of
CEC Pin
—
—
—
0.8
V
—
RPUCEC
Pull-up Resistor on CEC Pin
—
24.3
27
29.7
KΩ
—
VTH+I2C
Schmitt Trigger LOW to HIGH Threshold of
LSCL and LSDA Pins
—
2.0
—
—
V
2
—
3.0
—
—
V
3
VTH-I2C
Schmitt Trigger HIGH to LOW Threshold of
LSCL and LSDA Pins
—
—
—
0.8
V
2
—
—
—
1.5
V
3
Digital Outputs
VOH
HIGH-level Output Voltage
IOH = 8mA
2.4
—
—
V
1
VOL
LOW-level Output Voltage
IOL = –8mA
—
—
0.4
V
1
IOZ
Tri-state Output Leakage Current
—
–10
—
10
A
1
VOH_CEC
HIGH-level Output Voltage of CEC Pin
IOH = 100A
2.5
—
—
V
—
VOL_CEC
LOW-level Output Voltage of CEC Pin
IOL = –100A
—
—
0.4
V
—
Notes:
1. Applies to general digital IOs.
2
2. Compatible to 3.3 V I C level in default.
3. Compatible to 5 V DDC level (need to be configured by register).
Table 4.5. HDMI TMDS Output DC Specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VSWING
Single-ended Output Swing Voltage
RLOAD = 50 Ω
400
—
600
mV
VH
Single-ended High-level Output Voltage
—
AVCC – 200
—
AVCC + 10
mV
VL
Single-ended Low-level Output Voltage
—
AVCC – 700
—
AVCC – 400
mV
IDOS
Differential output short-circuit current
VOUT = 0 V
—
—
5
µA
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
26
SiI-DS-1122-B
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
Table 4.6. MHL TMDS Output DC Specifications
Symbol
Parameter
VSE_HIGH
VSE_LOW
VOFF*
Single-ended HIGH-level Output voltage
Single-ended LOW-level Output voltage
Single-ended Standby (off) Output Voltage
VDFSWING
VCMSWING
Conditions
Min
Typ
Max
Units
—
—
—
VTERM - 540
VTERM - 1760
VTERM -10
—
—
—
VTERM + 10
VTERM - 700
VTERM + 10
mV
mV
mV
Differential Output Swing Amplitude
RLOAD = 50 Ω
600
—
Common Mode Output Swing
360
—
1000
Min (720,
0.85×VDFSWING)
mV
RLOAD = 50 Ω
single-ended
mV
* Note:
VOFF is the source output voltage when terminated to VTERM through RT1, and the source device is in standby mode or power off
mode.
Table 4.7. CBUS DC Specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VTERM_CBUS
VIH_CBUS
VIL_CBUS
CBUS Termination Voltage
HIGH-level Input Voltage
LOW-level Input Voltage
—
—
—
1.7
1.0
—
—
—
—
1.9
—
0.6
V
V
V
VOH_CBUS
VOL_CBUS
HIGH-level Output Voltage
LOW-level Output Voltage
IOVCC18 = 1.8 V, 85 °C
IOVCC18 = 1.8 V, 85 °C
1.5
—
—
—
—
0.2
V
V
IOH_CBUS
IOL_CBUS
HIGH-output Drive Current
LOW-output Drive Current
VOH = 1.5 V
VOL = 0.2 V
2
300
—
—
—
—
mA
μA
IIL/IIH
ZCBUS_SRC_DISCOVER
Input Leakage Current
Pull-up Resistance – Discovery
High-impedance
—
–1.0
9
—
10
1.0
11
μA
kΩ
ZCBUS_SRC_ON
Pull-up Resistance – ON
—
4
5
6
kΩ
ZRID_MHL_ACCEPT
ZRID_MHL_REJECT
R_ID range identified as MHL
—
800
1000
1200
Ω
R_ID identified as not MHL
—
<500
—
>1600
Ω
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1122-B
27
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
4.5. AC Specifications
Table 4.8. Analog Front-end Electrical Specifications
Analog Input
Symbol
Parameter
—
VFSR
—
VOAR
—
Conditions
Min
Typ
Max
Units
Input Capacitance
Analog Input Range
Clamp Level
—
—
—
—
0.3
0.25
5
—
—
—
1.2
0.85
pF
V
V
Offset Adjustment Range
Offset Adjustment Resolution
—
—
–0.5
—
—
10
+ 0.5
—
V
Bits
BW
Input Analog Filter Bandwidth
—
Gain Adjustment Range
A/D Converters
—
—
50
–6
—
—
600
+6
MHz
dB
—
—
580 mVpp, 2.8 kHz Ramp Wave
Sampling Rate: 55 MHz
PGA Gain: 0 dB
LPF Bandwidth: 50 MHz
25
—
—
10
170
—
MHz
Bits
—
4
—
LSB
—
1
—
LSB
—
N
Conversion Rate
ADC Resolution
INL
Integral Nonlinearity
DNL
Differential Nonlinearity
NMC
No Missing Codes
ENOB
Effective Number Of Bits
—
300 mVpp, 1.1 MHz Sine Wave
Sampling Rate: 165 MHz
PGA Gain: 0 dB
LPF Bandwidth: 400 MHz
Guaranteed
—
—
7.5
—
Bits
PLL
—
—
Clock Frequency Range
Period Jitter
—
—
25
—
—
—
170
450
MHz
ps
—
—
Video Buffer
Phase Adjustment
Duty Cycle
—
—
—
45
11.25
50
—
55
Degree/Step
%
DP
DG
Differential Phase
Differential Gain
—
—
—
—
4
4
Degrees
%
THD
Total Harmonic Distortion
—
—
700 mVpp, 4 MHz Sine Wave
Load = 37.5 Ω
Internal Clamp: OFF
—
–48
—
dB
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
28
SiI-DS-1122-B
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
Table 4.9. HDMI/MHL Output AC Timing Specifications
Symbol
Parameter
MHL Mode
FMHL
FPIXEL
Link Clock Frequency
Pixel Clock Frequency
TMHL
TBIT
Link Clock Period
Bit Time on Link
TR_DF
Differential Swing LOW-to-HIGH Transition Time
TF_DF
Differential Swing HIGH-to-LOW Transition Time
TR_CM
TF_CM
Common Mode Clock Swing LOW-to-HIGH
Transition Time
Common Mode Clock Swing HIGH-to-LOW
Transition Time
Conditions
Min
Typ
Max
Units
—
—
25
25
—
—
75
75
MHz
MHz
—
—
RLOAD = 100 Ω
Differential
Mode
13.33
0.444
—
—
40
1.33
ns
ns
75
—
—
ps
75
—
—
ps
600
—
2500
ps
600
—
2500
ps
RLOAD = 30 Ω
Common Mode
TSKEW_DF
Differential Intrapair Skew
—
—
—
50
ps
TSKEW_CM
%TMHL
TMJIT
Common Mode Intrapair Skew
Clock Duty Cycle
MHL Clock Jitter
—
—
—
—
35
—
—
—
—
50
65
0.25TBIT+200
ps
%
ps
HDMI Mode
TTXDPS
Intrapair Differential Output Skew
—
—
0.03
0.15
TBIT
TTXRT
TTXFT
FTXC
Data/Clock Rise Time
Data/Clock Fall Time
Differential Output Clock Frequency
20% – 80%
20% – 80%
—
75
75
25
—
—
—
—
—
165
ps
ps
MHz
TTXC
TDUTY
Differential Output Clock Period
Differential Output Clock Duty Cycle
—
—
6.06
40%
—
—
40
60%
ns
TTXC
TOJIT
Differential Output Clock Jitter
—
—
—
0.25
TBIT
Table 4.10. CBUS Timing Specifications
Symbol
TRISE
TFALL
Parameter
Rise Time
Fall Time
ΔTRF
TBIT
TSRC:PULSE_WIDTH
TSRC:CONN
TCBUS_SRC_ON
TARBITRATE
NSRC_PULSE_COUNT
TBIT_VARY_PACKET
Conditions
CL = 560 pF
CL = 560 pF
Min
5
5
Typ
—
—
Max
200
200
Units
ns
ns
Notes
—
—
Rise-to-Fall Time Difference
Bit Time (1 MHz)
Discovery Pulse Width (High Time,
Float Time)
—
—
—
0.8
—
—
100
1.2
ns
µsec
—
—
—
80
100
120
µsec
—
CBUS HIGH detect to connected state
Connected State to ZCBUS_SRC_ON
enabled
Connected state to First CBUS Packet
allowed
—
—
—
240
µsec
1
—
—
—
120
µsec
—
—
500
—
—
µsec
2
Discovery Pulse Count attempted
Bit Time variation within the packet
—
—
6
–1%
—
—
20
1%
pulses
TBIT
3
4
Notes:
1. This parameter is the length of time from when the source detects a HIGH on CBUS (held HIGH by the sink at the end of a
discovery drive-and-float pulse), to when the source switches CBUS impedance to ZCBUS_SRC_ON and CBUS becomes active.
Active means ready to receive the first packet.
2. Source and sink must wait at least this long before beginning first arbitration on CBUS.
3. A sink that detects at least NSINK_PULSE_COUNT {min} changes its pull-down resistance on CBUS from ZCBUS_SINK_DISCOVER to ZCBUS_SINK_ON.
4. Bits driven by the initiator within one packet should match the mean bit time in the packet by this limit.
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1122-B
29
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
2
Table 4.11. I S Audio Input Port Timing Specifications
Symbol
Parameter
FS_I2S
TSCKCYC
TSCKDUTY
Sample Rate
2
I S Cycle Time
2
I S Duty Cycle
TI2SSU
TI2SHD
I S Setup Time
2
I S Hold Time
Conditions
Min
Typ
Max
Units
Figure
—
—
—
32
—
90
—
1.0
—
192
—
110
kHz
UI
%UI
—
Figure 5.4
Figure 5.4
—
—
15
1
—
—
—
—
ns
ns
Figure 5.4
Figure 5.4
Conditions
Min
Typ
Max
Units
Figure
Notes
—
—
—
32
—
90
—
—
—
192
2.0
110
kHz
UI
%UI
—
Figure 5.5
Figure 5.5
—
1
1
2
Table 4.12. S/PDIF Input Port Timing Specifications
Symbol
Parameter
FS_SPDIF
TSPCYC
TSPDUTY
Sample Rate
S/PDIF Cycle Time
S/PDIF Duty Cycle
TAUDDLY
Audio Pipeline Delay
—
—
30
70
μs
—
Notes:
2
1. Proportional to unit time (UI), according to the sample rate. Refer to the I S or S/PDIF Specifications.
2. Audio pipeline delay measured from transmitter input signals to TMDS output. The video path delay is insignificant.
2
4.6. Control Signal Timing Specifications
Table 4.13. Control Signal Timing Specifications
Symbol
TI2CDVD
TRESET
Parameter
SDA Data Valid Delay from SCL
falling edge on READ command
RESET_N Signal LOW Time
required for reset
Conditions
Min
Typ
Max
Units
Figure
Notes
CL = 400pF
—
—
700
ns
Figure 5.1
1, 2
—
5000
—
—
ns
Figure 5.2,
Figure 5.3
3
Notes:
2
2
1. All standard-mode (100 kHz) I C timing requirements are guaranteed by design. These timings apply to the slave I C port
(signals LSDA and LSCL).
2
2. Operation of I C signals above 100 kHz is defined by LVTTL levels VIH, VIL, VOH, and VOL (see Table 4.4 on page 26). For these
2
levels, I C speeds up to 400 kHz are supported.
3. Reset on RESET_N signal can be LOW as CVCC10 and VDDIO33 become stable, or pulled LOW for at least T RESET.
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
30
SiI-DS-1122-B
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
5. Timing Diagrams
5.1. I2C Bus Timing Diagrams
LSDA
TI2CDVD
LSCL
2
Figure 5.1. I C Data Valid Delay (Driving Read Cycle Data)
5.2. Reset Timing Diagram
All power rails must be stable between its limits for Normal Operating Conditions for TRESET before RESET_N is HIGH.
RESET_N must be pulled LOW for TRESET before accessing registers. This can be done by holding RESET_N LOW until
TRESET after stable power (Figure 5.2) or by pulling RESET_N LOW from a HIGH state (Figure 5.3) for at least TRESET.
VCCmax
VCCmin
VCC
RESET_N
TRESET
Figure 5.2. Conditions for Use of RESET_N
RESET_N
TRESET
Figure 5.3. RESET_N Minimum Timings
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1122-B
31
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
5.3. Audio Timing Diagrams
TSCKCYC
TSCKDUTY
SCK
50 %
TI2SSU
SD0, WS
50 %
TI2SHD
no change allowed
50 %
50 %
Figure 5.4. I2S Timings
TSPCYC
T SPDUTY
50%
SPDIF
Figure 5.5. S/PDIF Timings
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
32
SiI-DS-1122-B
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
6. Pin Diagram and Description
6.1. Pin Diagram
RED2
RED1
RED0
24
23
REDN
27
VP2V5A
VP2V5D
28
25
BLU0
26
BLU1
BLUN
33
29
GRN0
34
30
GRN1
35
BLU2
VP2V5A
36
VP2V5A
GRN2
37
31
GRNN
38
32
CVBS0
CVBS1
41
VP2V5D
VP2V5A
42
39
CVBSN
43
40
AFE_REXT
44
Figure 6.1 shows the pin diagram of the SiI8784 device. Individual pin functions are described in the Pin Descriptions
section on the next page. The package is an 88-pin 10 mm × 10 mm, 0.9 mm pitch QFN with ePad, which must be
connected to ground.
SOG0
45
22
HDMI_MHL_N
SOG1
46
21
GPIO4
FS_LINE1
47
20
GPIO3
CVBS_OUT
48
19
GPIO2
VP2V5_SLICER
49
18
LSDA
LINE3
50
17
LSCL
FB_LINE2
51
16
INT
HS0
52
15
RESET_N
VP1V0_PLL
53
14
VDDIO33
VCC10_TPLL
54
13
CVCC10
12
AVCC_PLL
11
TX2P
XTALVCC33
55
XTALIN
56
SiI8784
(Top View)
XTALOUT
57
10
TX2N
XTALGND
58
9
AVCC
VS0
59
8
TX1P
CVCC10
60
7
TX1N
SCLK
61
6
TX0P_MHLD
SDI
62
5
TX0N_MHLDB
SDO
63
4
AVCC
SCS
64
3
TXCP
CVCC10
65
2
D23_RSV
66
1
83
84
85
86
87
88
CEC
GPIO0_CI2CA
GPIO1
CBUS
AVSS
82
TMODE
81
DSCL
80
CVCC10
79
HPD
78
DSDA
77
VDDIO33
74
WS
D12_RSV
73
SD0_SPDIF
76
72
SCK
75
71
D14_RSV
MCLK
70
D13_RSV
69
CVCC10
68
D15_RSV
67
VDDIO33
D22_RSV
ePad (GND)
TXCN
AVCC3V3_CBUS
Figure 6.1. Pin Diagram
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1122-B
33
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
6.2. Pin Descriptions
The following tables provide the pin descriptions for the SiI8784 device.
6.2.1. AFE Pins
Table 6.1. AFE Input/Output Pins
Pin Name
Pin
Type
Direction
Description
Notes
RED0
23
Analog
Input
RED Input 0.
1
RED1
24
Analog
Input
RED Input 1.
1
RED2
26
Analog
Input
RED Input 2.
1
REDN
27
Analog
Input
RED Negative Input.
2
BLU0
29
Analog
Input
BLUE Input 0.
1
BLU1
30
Analog
Input
BLUE Input 1.
1
BLU2
32
Analog
Input
BLUE Input 2.
1
BLUN
33
Analog
Input
BLUE Negative Input.
2
GRN0
34
Analog
Input
GREEN Input 0.
1
GRN1
35
Analog
Input
GREEN Input 1.
1
GRN2
37
Analog
Input
GREEN Input 2.
1
GRNN
38
Analog
Input
GREEN Negative Input.
2
CVBS0
40
Analog
Input
CVBS Input 0.
1
CVBS1
41
Analog
Input
CVBS Input 1.
1
CVBSN
43
Analog
Input
CVBS Negative Input.
2
External Bias Resistor.
Must connect a 12 K, 1% resistor to ground.
—
AFE_REXT
44
Analog
Passive
SOG0
45
Analog
Input
SOG Input 0.
—
SOG1
46
Analog
Input
SOG Input 1.
—
FS_LINE1
47
Analog
Input
FS (SCART) or LINE1 (D-Terminal) Input.
—
FB_LINE2
51
Analog
Input
FB (SCART) or LINE2 (D-Terminal) Input.
—
LINE3
50
Analog
Input
LINE3 (D-Terminal) Input.
—
HS0
52
Analog
Input
HSync Input.
—
VS0
59
LVTTL
Schmitt
Trigger
5 V Tolerant
Pull-down
Input
VSync Input.
—
CVBS_OUT
48
Analog
Output
CVBS Output.
Connect a 75 Ω resistor to ground when CVBS output is
enabled.
—
Notes:
1. A 47nF couple capacitor is required when this pin is used.
2. Must connect a 0.1uF capacitor to ground when the corresponding input channel is used.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
34
SiI-DS-1122-B
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
6.2.2. Audio Input Pins
Table 6.2. Audio Input Pins
Pin Name
SCK
WS
SD0_SPDIF
MCLK
Pin
Type
Direction
72
LVTTL
Schmitt Trigger
5 V Tolerant
Pull-down
Description
Input
I S Bit Clock Input.
74
LVTTL
Schmitt Trigger
5 V Tolerant
Pull-down
Input
I S Word Select Signal Input.
73
LVTTL
Schmitt Trigger
5 V Tolerant
Pull-down
Input
I S Data Input or SPDIF Input.
75
LVTTL
Schmitt Trigger
5 V Tolerant
Pull-down
Input
Master Clock Input.
2
2
2
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1122-B
35
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
6.2.3. Configuration and Control Pins
Table 6.3. Configuration and Control Pins
Pin Name
Pin
Type
Direction
INT
16
LVTTL
Open Drain
5 V Tolerant
Output
RESET_N
15
LVTTL
Schmitt Trigger
5 V Tolerant
Input
LSCL
17
Open Drain
Schmitt Trigger
5 V Tolerant
IO
Local I C Bus Clock. Compatible with 5V and 3.3V I C standard.
LSDA
18
Open Drain
Schmitt Trigger
5 V Tolerant
IO
Local I C Bus Data. Compatible with 5V and 3.3V I C standard.
TMODE
84
Test Pin
Input
Reserved for test. This pin must be tied low during the normal
operation.
85
LVTTL
Schmitt Trigger
5 V Tolerant
Pull-down
IO
General GPIOs. It also is used to select local I C slave address during
reset when the internal 8051 is not used.
86
LVTTL
Schmitt Trigger
5 V Tolerant
Pull-up
IO
General GPIOs.
19
LVTTL
Schmitt Trigger
5 V Tolerant
Pull-up
IO
General GPIOs.
20
LVTTL
Schmitt Trigger
5 V Tolerant
Pull-up
IO
General GPIOs.
21
LVTTL
Schmitt Trigger
5 V Tolerant
Pull-up
IO
General GPIOs.
22
LVTTL
Schmitt Trigger
5 V Tolerant
Pull-up
Input
GPIO0_CI2CA
GPIO1
GPIO2
GPIO3
GPIO4
HDMI_MHL_N
Description
Interrupt Pin.
External Reset Signal. Active LOW.
2
2
2
2
2
MHL and HDMI Select.
High – HDMI
Low – MHL
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
36
SiI-DS-1122-B
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
6.2.4. HDMI/MHL Data Pins
Table 6.4. HDMI/MHL Data Pins
Pin Name
Pin
Type
Direction
Description
TX0P_MHLD
6
TMDS
Output
TMDS Output Data Pairs for HDMI output. It is also used as MHL data
pairs for MHL output.
TX0N_MHLDB
5
TMDS
Output
TMDS Output Data Pairs for HDMI output.
TX1P
8
TMDS
Output
TMDS Output Data Pairs for HDMI output.
TX1N
7
TMDS
Output
TMDS Output Data Pairs for HDMI output.
TX2P
11
TMDS
Output
TMDS Output Data Pairs for HDMI output.
TX2N
10
TMDS
Output
TMDS Output Data Pairs for HDMI output.
TXCP
3
TMDS
Output
TMDS Output Data Pairs for HDMI output.
TXCN
2
TMDS
Output
TMDS Output Data Pairs for HDMI output.
DSDA
80
DSCL
81
Open Drain
Schmitt
Trigger
5 V Tolerant
IO
DDC Signals for HDMI output. Compatible with 5 V I C standard. Must
connect pullup resistor to make sure DDC functions normal for both of
HDMI and MHL output modes.
Input
Hot Plug Detect Input. It is recommended to connect a 47 K pulldown
resistor to ground for HDMI output.
2
HPD
79
LVTTL
Schmitt
Trigger
5 V Tolerant
CEC
83
CEC
Pull-up
IO
CEC Port.
CBUS
87
Analog
5 V Tolerant
IO
CBUS Port. It can be connected to HPD pin in the case of outputting MHL
over HDMI Type-A connector.
6.2.5. SPI Interface Pins
Table 6.5. SPI Interface Pins
Pin Name
SCLK
SDI
SDO
SCS
Pin
Type
Direction
61
LVTTL
Schmitt
Trigger
5 V Tolerant
Pull-down
Description
Output
62
LVTTL
Schmitt
Trigger
5 V Tolerant
Pull-down
Input
63
LVTTL
Schmitt
Trigger
5 V Tolerant
Pull-down
Output
SPI Data Output. Keep HiZ when RESET_N is low.
64
LVTTL
Schmitt
Trigger
5 V Tolerant
Pull-down
Output
SPI Chip Enable. Keep HiZ when RESET_N is low.
SPI clock output. Keep HiZ when RESET_N is low.
SPI Data Input.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1122-B
37
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
6.2.6. Power and Ground Connections
Table 6.6. Power and Ground Connections
Pin Name
Pin
Type
Description
VP2V5A
25, 31, 36, 42
Power
Analog power for ADC.
Supply
2.5 V
VP2V5D
28, 39
Power
Digital power for ADC.
2.5 V
VP2V5_SLICER
49
Power
Analog power for SOG Slicer.
2.5 V
VP1V0_PLL
53
Power
Power for LLPLL.
1.0 V
VCC10_TPLL
54
Power
Power for TCI PLL.
1.0 V
AVCC_PLL
12
Power
Analog power for HDMI/MHL TX PLL.
1.0 V
AVCC
4, 9
Power
Digital power for HDMI/MHL TX.
1.0 V
AVCC3V3_CBUS
1
Power
Analog power for CBUS.
3.3 V
CVCC10
13, 60, 65, 69, 82
Power
Power for Digital Core.
1.0 V
VDDIO33
14, 67, 78
Power
Power for Digital I/O.
3.3 V
XTALVCC33
55
Power
Power for XTAL.
3.3 V
XTALGND
58
Ground
Ground for XTAL.
0V
AVSS
88
Ground
Ground for CBUS.
0V
6.2.7. Crystal Pins
Pin Name
Pin
Type
Direction
XTALIN
56
Analog
I
Description
Input for Crystal.
XTALOUT
57
Analog
O
Output for Crystal.
6.2.8. Reserved Pins
Table 6.7. Reserved Pins
Pin Name
Pin
Type
Description
D22_RSV
68
RSVD
Reserved.
D23_RSV
66
RSVD
Reserved.
D12_RSV
77
RSVD
Reserved.
D13_RSV
76
RSVD
Reserved.
D14_RSV
71
RSVD
Reserved.
D15_RSV
70
RSVD
Reserved.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
38
SiI-DS-1122-B
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
7. Design Recommendations
7.1. Typical Connections
Representative circuits for applications of the SiI8784 chip are shown in Figure 7.1 and Figure 7.2. For a detailed review
of your intended circuit implementation, contact Lattice Semiconductor.
+5V
D-Terminal
SCART
VGA
CVBS
YPbPr
SCART
YPbPr/VGA
CVBS0..1
HPD
RED0..2
CEC
GRN0..2
DSDA
BLU0..2
DSCL
CVBSN
TX2P
REDN
TX2N
GRNN
TX1P
BLUN
TX1N
CVBS_OUT
Regulators
+3.3V
+5V
+2.5V
+1.0V
MHL
TX0P_MHLD
SOG0..1
+5V
TX0N_MHLDB
VGA
VS0
TXCP
MHLD
VGA
HS0
TXCN
MHLDB
SCART/D-Terminal
FS_LINE1
CBUS
SCART/D-Terminal
FB_LINE2
D-Terminal
Plug-in Detection
Analog Video Interfaces
CBUS
+3.3V
GND
SiI8784
LINE3
HDMI_MHL_N
GPIO1..4
AFE_REXT
INT
12K
Peripherals
(Optional)
LSDA
LSCL
MCLK
Audio
ADC
Audio L
Audio R
SCK
GPIO0_CI2CA
WS
SD0_SPDIF
TMODE
XTALIN
RESET_N
XTALOUT
SCS
+3.3 V
SCLK
SDO
SDI
SPI FLASH
24MHz
Figure 7.1.Typical Connection Diagram (MHL Output)
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1122-B
39
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
+5V
VGA
D-Terminal
CVBS
YPbPr
SCART
CVBS0..1
SCART
YPbPr/VGA
HPD
RED0..2
CEC
GRN0..2
DSDA
BLU0..2
DSCL
CVBSN
TX2P
REDN
TX2N
GRNN
TX1P
BLUN
TX1N
CVBS_OUT
TX0P_MHLD
SOG0..1
TX0N_MHLDB
VGA
VS0
TXCP
VGA
HS0
TXCN
SCART/D-Terminal
FS_LINE1
CBUS
SCART/D-Terminal
FB_LINE2
D-Terminal
Plug-in Detection
Analog Video Interfaces
HDMI
+5V
+3.3V
+3.3V
SiI8784
LINE3
HDMI_MHL_N
GPIO1..4
AFE_REXT
INT
12K
Peripherals
(Optional)
LSDA
LSCL
MCLK
Audio
ADC
Audio L
Audio R
SCK
GPIO0_CI2CA
WS
SD0_SPDIF
Regulators
TMODE
XTALIN
RESET_N
XTALOUT
SCS
+3.3V
SCLK
SDO
SDI
SPI FLASH
+3.3V
DC
JACK
+5V
+2.5V
+1.0V
24MHz
Figure 7.2.Typical Connection Diagram (HDMI Output)
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
40
SiI-DS-1122-B
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
7.2. Power Supplies Decoupling
Designers should include the decoupling and bypass capacitors at each power signal in the layout. These are shown
schematically in Figure 7.3. Place these components as close as possible to the input processor differential signals, and
avoid routing the differential signals through vias. Figure 7.4 is the representative of the various types of power
connections on the input processor.
VDD
L1
VCC Pin
C1
C2
C3
GND
Figure 7.3. Decoupling and Bypass Schematic
VCC
VDD
GND
C1
C2
L1
Ferrite
C3
Via to GND
Figure 7.4. Decoupling and Bypass Capacitor Placement
Connections in one group (such as CVCC10) can share C2, C3, and the ferrite, with each ball having a separate C1 placed
as close to the ball as possible.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1122-B
41
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
7.3. High-speed HDMI/MHL TMDS Signals
7.3.1. Source Termination
Source termination suppresses the signal reflection and overshoot, and at the same time allows strong input processor
drive for longer cable support. The SiI8784 input processor has 100 Ω internal source terminations on the HDMI/MHL
differential signal. The common mode clock signal does not have source termination.
7.3.2. ESD Protection
The SiI8784 input processor chip is designed to withstand electrostatic discharge during manufacturing. In applications
where higher protection levels are required in the finished product, ESD limiting components can be placed on the
differential lines coming out of the chip. These components typically have a capacitive effect, reducing the signal
quality at higher clock frequencies on the link. Use the lowest capacitance devices, if possible. In no case should the
capacitance value exceed 1 pF.
7.3.3. Layout Guidelines
The layout guidelines below help to ensure signal integrity. Lattice Semiconductor strongly encourages the board
designer to follow the guidelines below.


Place the input and output connectors that carry the TMDS signals as close as possible to the chip
Route the differential lines as directly as possible from the connector to the device when using industry-standard
HDMI connectors
Route the two traces of each differential pair together
Minimize the number of VIAs through which the signal lines are routed
Layout the MHL input pin traces with a controlled differential impedance of 100 Ω and a common mode
impedance of 30 Ω. The differential impedance of the HDMI output pins must be designed within ±15% of 100 Ω
Serpentine traces are not recommended to compensate for inter-pair trace skew




7.4. EMI Considerations
Electromagnetic interference is a function of board layout, shielding, receiver component operating voltage, frequency
of operation, and so on. When attempting to control emissions, do not place any passive components on the
differential signal lines (except for the ESD protection and common mode choke described earlier). Lattice
Semiconductor recommends the use of a metal shielding can over the SiI8784 chip and the traces going to the
connector. The PCB ground plane should extend unbroken under as much of the input processor chip and associated
circuitry as possible, with all ground signals of the chip using a common ground.
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
42
SiI-DS-1122-B
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
8. Packaging
8.1. ePad Requirements
The SiI8784 input processor chip is packaged in 88-pin QFN package with an exposed pad (ePad) that is used for the
electrical ground of the device and for improved thermal transfer characteristics. The ePad dimensions are
5.60 mm × 5.60 mm ± 0.15 mm. Soldering the ePad to the ground plane of the PCB is required to meet package power
dissipation requirements at full speed operation, and to correctly connect the chip circuitry to electrical ground. A
clearance of at least 0.25 mm should be designed on the PCB between the edge of the ePad and the inner edges of the
lead pads to avoid the possibility of electrical shorts.
The thermal land area on the PCB may use thermal vias to improve heat removal from the package. These thermal vias
also double as the ground connections of the chip and must attach internally in the PCB to the ground plane. An array
of vias should be designed into the PCB beneath the package. For optimum thermal performance, the via diameter
should be 12 mils to 13 mils (0.30 mm to 0.33 mm) and the via barrel should be plated with 1-ounce copper to plug the
via. This design helps to avoid any solder wicking inside the via during the soldering process, which may result in voids
in solder between the pad and the thermal land. If the copper plating does not plug the vias, the thermal vias can be
tented with solder mask on the top surface of the PCB to avoid solder wicking inside the via during assembly. The
solder mask diameter should be at least 4 mils (0.1 mm) larger than the via diameter.
Package stand-off when mounting the device also needs to be considered. For a nominal stand-off of approximately 0.1
mm the stencil thickness of 5 mils to 8 mils should provide a good solder joint between the ePad and the thermal land.
Figure 8.1 on the next page shows the package dimensions of the SiI8784 device.
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1122-B
43
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
8.2. Package Dimensions
0.10 C
A
B
D
D1
0.10 M C A B
D2
88
88
1
2
3
1
2
3
0.10 M C A B
E1 E
E2
A
L
0.10 C
e
Top View
Bottom View
K
A2
Side View
C
0.10 M C A B
0.05 M C
// 0.10 C
A1 A3
A
b
0.08 C
R
Seating Plane
0.6 max
0.6 max
Detail A
JEDEC Package Code MO-2206
Item
Description
Min
Typ
Max
Item
Description
Min
Typ
Max
A
A1
A2
Thickness
Stand-off
Body thickness
0.80
0.00
0.60
0.85
0.02
0.65
0.90
0.05
0.70
D2
E2
b
ePad
ePad
Lead width
5.45
5.45
0.15
5.60
5.60
0.20
5.75
5.75
0.25
A3
D
Base thickness
Footprint
9.90
0.20 REF
10.00
10.10
e
L
Lead pitch
Lead foot length
0.30
0.40 BSC
0.40
0.50
E
D1
E1
Footprint
Body size
Body size
Θ
R
K
Mold angle
Lead radius, inside
ePad clearance
0°
0.075
0.20
—
—
—
14°
—
—
9.90
10.00
9.75 BSC
9.75 BSC
10.10
Note: Dimensions in mm.
Figure 8.1. 88-Pin QFN Package Diagram
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
44
SiI-DS-1122-B
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
9. Marking Specification
Figure 9.1 shows the markings of the SiI8784 package. This drawing is not to scale.
Pin 1
Location
Logo
SiI8784 CNUC
LLLLLL.LL-L
YYWW
XXXXXXX
Silicon Image Part Number
Lot # (= Job#)
Date code
Trace code
SiIxxxxrpppp-sXXXX
Product
Designation
Special
Designation
Revision
Speed
Package Type
Figure 9.1. Marking Diagram
9.1. Ordering Information
Production Part Numbers:
Device
Part Number
Analog Front End Video Processor with HDMI1.4/MHL2.1
Transmitter
SiI8784CNUC
The universal package can be used in lead-free and ordinary process lines.
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1122-B
45
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
References
Standards Documents
This is a list of the standards abbreviations appearing in this document.
Abbreviation
HDMI
HCTS
Standards publication, organization, and date
High Definition Multimedia Interface, Revision 1.4, HDMI Consortium
HDMI Compliance Test Specification, Revision 1.4, HDMI Consortium.
MHL
HDCP
MHL (Mobile High-definition Link) Specification, Revision 2.1, MHL, LLC.
High-bandwidth Digital Content Protection, Revision 1.4, Digital-Content Protection, LLC.
DVI
E-EDID
CEA-861-D
Digital Visual Interface, Revision 1.0, Digital Display Working Group; April 1999.
Enhanced Extended Display Identification Data Standard, Release A Revision 1, VESA; Feb. 2000.
A DTV Profile For Uncompressed High Speed Digital Interfaces, EIA/CEA; July 2006.
EDDC
2
IC
Enhanced Display Data Channel Standard, Version 1, VESA; September 1999.
2
The I C Bus Specification, Version 2.1, Philips Semiconductors, January 2000.
For information on the specifications that apply to this document, contact the responsible standards groups appearing
on this list.
Standards Group
ANSI/EIA/CEA
VESA
Web URL
http://global.ihs.com
http://www.vesa.org
DVI
HDCP
http://www.ddwg.org
http://www.digital-cp.com
HDMI
MHL
http://www.hdmi.org
http://www.mhlconsortium.org
Lattice Semiconductor Documents
The following are available from your Lattice Semiconductor sales representative. The Programmer’s Reference
requires an NDA with Lattice Semiconductor.
Document
SiI-AN-0129
Title
PCB Layout Guidelines: Designing with Exposed Pads
SiI-PR-0041
SiI-AN-1108
CEC Programming Interface (CPI) Programmer's Reference
SiI8784 and SiI8788 Supported SPI Flash Memories
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
46
SiI-DS-1122-B
SiI8784 Multi-format Analog Video Front-end with HDMI/MHL Transmitter
Data Sheet
Revision History
Revision B, March 2016
Updated to latest template.
Revision B, September 2014
Summary of changes:
Remove the mentioning of SiI8784 and SiI8788 Analog Video Process Programmer Reference.
Details of changes:
Removed the reference to Programmer Reference from Section 3.5.2 Registers, 3.5.4 Interrupt, and Lattice
Semiconductor Documents.
Revision A, September 2014
First production release.
© 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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47
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