RFMD2081 Data Sheet

RFMD2081
RFMD2081
45MHz TO 2700MHz IQ MODULATOR
WITH SYNTHESIZER/VCO
Package: QFN, 32-Pin, 5mm x 5mm
Features









RF Output Frequency Range
45MHz to 2700MHz
Fully Integrated Wideband VCOs
and LO Buffers
Ref.
divider
Integrated Phase Noise
<0.2° rms at 1GHz
-40dBc Unadjusted Carrier
Suppression
-40dBc Unadjusted Sideband
Suppression
100MHz Baseband Input 3dB
Bandwidth
Very Low Noise Floor
-162dBm/Hz Typical
Output P1dB + 4dBm

Output IP3 + 17dBm

2.7V to 3.3V Power Supply

Synth
Typical Step Size 1.5Hz


Phase
det .
Fractional-N Synthesizer with
Very Low Spurious Levels
135mA Typical Current
Consumption
Serial Programming Interface
Applications

Satellite Communications

QPSK/QAM Modulators

Wireless Broadband

Point-to-Point

Software Defined Radios
Functional Block Diagram
Product Description
The RFMD2081 is a low power, wideband, IQ modulator with integrated fractional-N synthesizer
and voltage controlled oscillator (VCO). The modulator features an input 3dB bandwidth of
100MHz, and can generate output frequencies of between 45MHz and 2700MHz, making it
suitable for a wide range of applications.
The fractional-N synthesizer takes advantage of an advanced sigma-delta architecture that
delivers ultra-fine step sizes and low spurious products. The synthesizer/VCO, combined with
an external loop filter, allows the user to generate local oscillator (LO) signals from 90MHz to
5400MHz. The LO signal is buffered and routed to a high accuracy quadrature divider (/2) that
drives the balanced I and Q mixers. The output of the mixers are summed and applied to a differential RF output stage. This device also features a differential input for an external VCO or LO
source.
Device programming is achieved via a simple 3-wire serial interface. In addition, a unique programming mode allows up to four devices to be controlled from a common serial bus. This eliminates the need for separate chip-select control lines between each device and the host
controller. Up to six general purpose outputs are provided, which can be used to access internal
signals (the LOCK signal, for example) or to control front end components. The device is optimized for low power operation, consuming typically only 135mA from a 3V supply.
Optimum Technology Matching® Applied
GaAs HBT
GaAs MESFET
InGaP HBT
SiGe BiCMOS
Si BiCMOS
SiGe HBT
GaAs pHEMT
Si CMOS
Si BJT
GaN HEMT
RF MEMS
LDMOS
RF MICRO DEVICES®, RFMD®, Optimum Technology Matching®, Enabling Wireless Connectivity™, PowerStar®, POLARIS™ TOTAL RADIO™ and UltimateBlue™ are trademarks of RFMD, LLC. BLUETOOTH is a trademark owned by Bluetooth SIG, Inc., U.S.A. and licensed for use by RFMD. All other trade names, trademarks and registered trademarks are the property of their respective owners. ©2011, RF Micro Devices, Inc.
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RFMD2081
Absolute Maximum Ratings
Parameter
Supply Voltage (VDD)
Input Voltage (VIN), any pin
Rating
Unit
-0.5 to +3.6
V
-0.3 to VDD +0.3
V
+15
dBm
Operating Temperature Range
-40 to +85
°C
Storage Temperature Range
-65 to +150
°C
LO Input Power
Caution! ESD sensitive device.
Exceeding any one or a combination of the Absolute Maximum Rating conditions may
cause permanent damage to the device. Extended application of Absolute Maximum
Rating conditions to the device may reduce device reliability. Specified typical performance or functional operation of the device under Absolute Maximum Rating conditions is not implied.
The information in this publication is believed to be accurate and reliable. However, no
responsibility is assumed by RF Micro Devices, Inc. ("RFMD") for its use, nor for any
infringement of patents, or other rights of third parties, resulting from its use. No
license is granted by implication or otherwise under any patent or patent rights of
RFMD. RFMD reserves the right to change component circuitry, recommended application circuitry and specifications at any time without prior notice.
RFMD Green: RoHS compliant per EU Directive 2002/95/EC, halogen free
per IEC 61249-2-21, < 1000ppm each of antimony trioxide in polymeric
materials and red phosphorus as a flame retardant, and <2% antimony in
solder.
Parameter
Min.
Specification
Typ.
Max.
Unit
Condition
ESD Requirements
Human Body Model
Charge Device Model
2000
V
DC Pins
1500
V
All Pins
1000
V
All Pins
Operating Conditions
Supply Voltage (VDD)
2.7
3.3
V
Temperature
-40
+85
°C
Input Low voltage
-0.3
+0.5
V
Input High voltage
VDD / 1.5
VDD
V
Input Low current
-10
+10
A
Input = 0V
Input High current
-10
+10
A
Input = VDD
Output Low voltage
0
0.2*VDD
V
Output High voltage
0.8*VDD
VDD
Logic Inputs/Outputs
(VDD = Supply to DIG_VDD pin)
Load Resistance
10
V
k
Load Capacitance
20
pF
GPO Drive Capability
Sink Current
20
mA
At VOL = +0.6V
Source Current
20
mA
At VOL = +2.4V
Output Impedance
25

Static
Supply Current (IDD)
Standby
Power Down Current
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135
mA
1.3V Input DC Bias
2
mA
Reference Oscillator and Bandgap Only
300
A
ENBL = 0 and REF_STBY = 0
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RFMD2081
Parameter
Min.
Specification
Typ.
Max.
Unit
Condition
Modulator (Output driving 4:1 balun)
I & Q Input 3dB Bandwidth
100
MHz
Differential with 1.3V Input DC Bias
I & Q Input Voltage
1
VP-P
Output Power
-4
dBm
Output Noise Floor
-162
dBm/Hz
Output IP3
+17
dBm
1.3V Input DC Bias
Output P1dB
+4
dBm
1.3V Input DC Bias
Carrier Suppression
-40
dBc
Unadjusted
Carrier Suppression
-50
dBc
Input DC Bias Offset Adjusted
dBc
Unadjusted
Sideband Suppression
-40
Output Port Center Frequency Range
45
2700
MHz
External Reference Frequency
10
104
MHz
Reference Divider Ratio
1
7
At 10MHz Offset with 1.3V Input DC Bias
Reference Oscillator
External Reference Input Level
500
800
1500
mVP-P
5400
MHz
AC-coupled
Synthesizer
(PLL closed loop, 52MHz reference)
Synthesizer Output frequency
90
Phase Detector Frequency
52
Phase Noise, LO=1GHz
Phase Noise, LO=2GHz
MHz
-108
dBc/Hz
10kHz Offset
-108
dBc/Hz
100kHz Offset
-135
dBc/Hz
0.19
Deg
1MHz Offset
RMS Integrated from 1KHz to 40MHz
-102
dBc/Hz
10kHz Offset
-102
dBc/Hz
100kHz Offset
1MHz Offset
-130
dBc/Hz
0.32
Deg
RMS Integrated from 1KHz to 40MHz
-214
dBc/Hz
Measured at 20kHz to 30kHz Offset
2.5GHz LO Frequency
-134
dBc/Hz
VCO3, LO Divide by 2
2.0GHz LO Frequency
-135
dBc/Hz
VCO2, LO Divide by 2
1.5GHz LO Frequency
-136
dBc/Hz
VCO1, LO Divide by 2
Normalized phase noise floor
Voltage Controlled Oscillator
Open Loop Phase Noise at 1MHz Offset
Open loop phase noise at 10MHz offset
2.5GHz LO Frequency
-149
dBc/Hz
VCO3, LO Divide by 2
2.0GHz LO Frequency
-150
dBc/Hz
VCO2, LO Divide by 2
1.5GHz LO Frequency
-151
dBc/Hz
VCO1, LO Divide by 2
External LO Input
LO Input Frequency Range
External LO Input Level
DS140110
90
5400
0
MHz
dBm
Driven from 50 source via a 1:1 balun
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RFMD2081
Pin Names and Descriptions
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Name
ENBL/GPO5
EXT_LO
EXT_LO_DEC
REXT
ANA_VDD1
LFILT1
LFILT2
LFILT3
MODE/GPO6
REF_IN
NC
TM
RF_OUT_N
RF_OUT_P
GPO1/ADD1
GPO2/ADD2
DIG_VDD
MOD_Q_N
MOD_Q_P
NC
NC
MOD_I_N
MOD_I_P
ANA_VDD2
GPO3
GPO4/LD/DO
NC
NC
RESETX
ENX
SCLK
SDATA
Exposed Paddle
Description
Device Enable pin (see note 1 and 2).
External local oscillator input. Use AC coupling capacitor.
Decoupling pin for external local oscillator. Use AC coupling capacitor.
External bandgap bias resistor (see note 3).
Analog supply. Use good RF decoupling.
Phase detector output. Low-frequency noise-sensitive node.
Loop filter op-amp output. Low-frequency noise-sensitive node.
VCO control input. Low-frequency noise-sensitive node.
Mode select pin (see notes 1 and 2).
Reference input. Use AC coupling capacitor.
Connect to ground.
Differential output (see note 5).
Differential output (see note 5).
General purpose output / MultiSlice address bit.
General purpose output / MultiSlice address bit.
Digital supply. Should be decoupled as close to the pin as possible.
Modulator Q differential input (see note 4).
Modulator Q differential input (see note 4).
Modulator I differential input (see note 4).
Modulator I differential input (see note 4).
Analog supply. Use good RF decoupling.
General purpose output
General purpose output / Lock detect output / serial data out.
Chip reset (active low). Connect to DIG_VDD if asynchronous reset is not required.
Serial interface select (active low) (See note 1).
Serial interface clock (See note 1).
Serial interface data (See note 1).
Ground reference, should be connected to PCB ground through a low impedance path.
Notes:
1.
An RC low pass filter may be used on this line to reduce digital noise.
2.
If the device is under software control this input can be configured as a general purpose output (GPO).
3.
Connect a 51K resistor from this pin to ground. This pin is sensitive to low frequency noise injection.
4.
DC bias voltage and modulation should be applied to this pin.
5. This pin must be connected to ANA_VDD2 using an RF choke or center tapped transformer (see application schematic).
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RFMD2081
Theory of Operation
The RFMD2081 is a wideband IQ modulator with integrated fractional-N synthesizer and a low noise VCO core. It features a
high accuracy LO quadrature divider followed by buffer circuits which drive the I and Q mixers of the modulator with the quadrature LO signals. The RFMD2081 has an integrated voltage reference and low drop out regulators supplying critical circuit
blocks such as the VCOs and synthesizer. Synthesizer programming, device configuration and control are achieved through a
mixture of hardware and software controls. All on-chip registers are programmed through a simple three-wire serial interface.
VCO
The VCO core in the RFMD2081 consists of three VCOs which, in conjunction with the integrated LO dividers of /1 to /32, cover
the frequency range of 90MHz to 5400MHz. The modulator quadrature divider provides a further fixed divide by two to give the
center frequency range at the modulator output of 45MHz to 2700MHz.
Each VCO has 128 overlapping bands which are used to achieve low VCO gain and optimal phase noise performance across
the whole tuning range. The chip automatically selects the correct VCO (VCO auto-select) and the correct VCO band (VCO
coarse tuning) to generate the desired LO frequency based on the values programmed into the PLL1 and PLL2 registers banks.
The VCO auto-select and VCO coarse tuning are triggered every time ENBL is taken high, or if the PLL re-lock self clearing bit is
programmed high. Once the correct VCO and band have been selected the PLL will lock onto the correct frequency. During the
band selection process fixed capacitance elements are progressively connected to the VCO resonant circuit until the VCO is
oscillating at approximately the correct frequency. The output of this band selection, CT_CAL, is made available in the readback register. A value of 127 or 0 in this register indicates that the coarse tuning was unsuccessful, and this should also be
indicated by the CT_FAILED flag also available in the read-back register. A value between 1 and 126 indicates a successful calibration, the actual value being dependent on the desired frequency as well as process variation for a particular device.
The band select process will center the VCO tuning voltage at about 0.8V, compensating for manufacturing tolerances and process variation as well as environmental factors including temperature. In applications where the device is left enabled at the
same LO frequency for some time it is recommended that automatic band selection be performed for every 30°C change in
temperature. This assumes an active loop filter.
The RFMD2081 features a differential LO input to allow the mixer to be driven from an external LO source. The fractional-N PLL
can be used with an external VCO driven into this LO input, which may be useful to reduce phase noise in some applications.
This may also require an external op-amp, dependant on the tuning voltage required by the external VCO.
Fractional-N PLL
The RFMD2081 contains a charge-pump based fractional-N phase locked loop (PLL) for controlling the three VCOs. The PLL
includes automatic calibration systems to counteract the effects of process and environmental variations, ensuring repeatable
loop response and phase noise performance. As well as the VCO auto-select and coarse tuning, there is a loop filter calibration
mechanism which can be enabled if required. This operates by adjusting the charge pump current to maintain loop bandwidth.
This can be useful for applications where the LO is tuned over a wide frequency range.
The PLL has been designed to use a reference frequency of between 10MHz and 104MHz from an external source, which is
typically a temperature controlled crystal oscillator (TCXO). A reference divider (divide by 1 to divide by 7) is supplied and
should be programmed to limit the frequency at the phase detector to a maximum of 52MHz.
Two PLL programming banks are provided, the first bank is preceded by the label PLL1 and the second bank is preceded by the
label PLL2. The active register bank is selected by the state of the MODE pin, low for PLL1 and high for PLL2.
The VCO outputs are first divided down in a high frequency prescalar. The output of this high frequency prescalar then enters
the N divider, which is a fractional divider containing a dual-modulus prescalar and a digitally spur-compensated fractional
sequence generator. This allows very fine frequency steps and minimizes fractional spurs. The fractional energy is randomized
and appears as fractional noise at frequency offsets above 100kHz which will be attenuated by the loop filter. An external loop
filter is used, giving flexibility in setting loop bandwidth for optimizing phase noise and lock time for example.
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RFMD2081
The synthesizer step size is typically 1.5Hz when using a 26MHz reference frequency. The exact step size for any reference and
LO frequency can be calculated using the following formula:
(FREF * P) / (R * 224 * LO_DIV*2)
Where FREF is the reference frequency, R is the reference division ratio, P is the prescalar division ratio, and LO_DIV is the LO
divider value.
Pin 26 (GPO4) can be configured as a lock detect pin. The lock status is also available in the read-back register. The lock detect
function is a window detector on the VCO tuning voltage. The lock flag will be high to show PLL lock which corresponds to the
VCO tuning voltage being within the specified range, typically 0.30V to 1.25V.
The lock time of the PLL will depend on a number of factors; including the loop bandwidth and the reference frequency at the
phase detector. This clock frequency determines the speed at which the state machine and internal calibrations run. A 52MHz
phase detector frequency will give fastest lock times, of typically <50secs when using the PLL re-lock bit.
Phase Detector and Charge Pump
The phase detector provides a current output to drive an active loop filter. The charge pump output current is set by the value
contained in the P1_CP_DEF and P2_CP_DEF fields in the loop filter configuration register. The charge pump current is given
by approximately 3A/bit, and the fields are 6 bits long. This gives default value (31) of 93A and maximum value (63) of
189A.
If the automatic loop bandwidth calibration is enabled the charge pump current is set by the calibration algorithm based upon
the VCO gain.
The phase detector will operate with a maximum input frequency of 52MHz.
Loop Filter
The active loop filter is implemented using the on-chip low noise op-amp, with external resistors and capacitors. The op-amp
gives a tuning voltage range of typically +0.1V to +2.4V. The internal configuration of the chip is shown below with the recommended active loop filter. The loop filter shown is designed to give lowest integrated phase noise, for reference frequencies of
between 26MHz and 52MHz. The external loop filter components give the flexibility to optimize the loop response for any particular application and combination of reference and VCO frequencies.
8p2
LFILT1
180p
22K
LFILT2
470R
330p
+1.1V
470R
LFILT3
330p
External Reference
The RFMD2081 have been designed to use an external reference such as a TCXO. The typical input will be a 0.8Vp-p clipped
sine wave, which should be AC-coupled into the reference input. When the PLL is not in use, it may be desirable to turn off the
internal reference circuits, by setting the REFSTBY bit low, to minimize current draw while in standby mode.
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RFMD2081
On cold start, or if REFSTBY is programmed low, the reference circuits will need a warm-up period. This is set by the SU_WAIT
bits. This will allow the clock to be stable and immediately available when the ENBL bit is asserted high, allowing the PLL to
assume normal operation.
If the current consumption of the reference circuits in standby mode, typically 2mA, is not critical, then the REFSTBY bit can be
set high. This allows the fastest startup and lock time after ENBL is taken high.
IQ Modulator
The IQ modulator core of the RFMD2081 is wideband covering from 45MHz to 2700MHz. It has been designed to achieve
exceptional linearity for the amount of DC power consumed.
The modulator mixer cores have four coarse gain/current settings. Each setting steps the gain and linearity by 6dB and can be
used to optimize performance or reduce power consumption.
The differential I and Q baseband inputs have 3dB bandwidth of 100MHz, and their input impedance is dominated by 10K
pull down resistors on each pin, as shown in the diagram below, so presenting a 20K differential impedance. A common
mode DC bias voltage of around +1.3V is required to set the current through the mixer cores for optimal performance. The offset between the common mode voltages on the differential pins can be adjusted to minimize LO leakage at the modulator output. The baseband input signals will be typically of the order of 1Vp-p differential. If required the phase and amplitude of the I
and Q signals can be adjusted to reduce the level of the unwanted sideband signal at the modulator output.
Qp
Q mixer core
(FET gates)
Qn
10K 
10K 
Ip
I mixer core
(FET gates)
In
10K 
10K 
The modulator output is differential and requires a balun and simple matching circuit optimized to the specific application frequencies. The modulator output pins are also used to source current for the modulator mixer circuits, about 20mA on each pin.
This is usually via a center-tapped balun or by RF chokes in the external matching circuitry to the supply.
The modulator output is high impedance, consisting of approximately 2K resistance in parallel with some capacitance,
approximately 1pF. The modulator output does not require a conjugate matching network. It is a constant current output which
will drive a real differential load of typically 200. Since the mixer output is a constant current source, a higher resistance load
will give higher output voltage and gain. A shunt inductor can be used to resonate with the mixer output capacitance at the frequency of interest. This inductor may not be required at lower frequencies where the impedance of the output capacitance is
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RFMD2081
less significant. At higher output frequencies the inductance of the bond wires (about 0.5nH on each pin) becomes more significant. The following diagram is a simple model of the modulator output:
0.5nH
1K 
RFMD2081
RF Output
1pF
1K 
0.5nH
It is recommended to use a 4:1 balun on the modulator output, converting from the single ended 50 system to a 200
differential load. The RFMD2081 evaluation board has an RFXF8553 wideband transmission line transformer.
Serial Interface
All on-chip registers in the RFMD2081 are programmed using a proprietary 3-wire serial bus which supports both write and
read operations. Synthesizer programming, device configuration and control are achieved through a mixture of hardware and
software controls. Certain functions and operations require the use of hardware controls via the ENBL, MODE, and RESETX
pins in addition to programming via the serial bus. Alternatively there is the option to control the chip completely via the serial
bus.
The serial data interface can be configured for 4-wire bus operation, by setting the '4WIRE' bit in the SDI_CTRL register high.
Then pin 26 is used as the data out pin, and pin 32 is the serial data in pin.
Hardware Control
Three hardware control pins are provided: ENBL, MODE, and RESETX.
The ENBL pin has two functions: to enable the analog circuits in the chip and to trigger the VCO auto-selection and coarse tuning mechanisms. The VCO auto-selection and coarse tuning are initiated when the ENBL pin is taken high. Every time the frequency of the synthesizer is reprogrammed, ENBL has to be asserted high to initiate these mechanisms and then to initiate the
PLL locking. Alternatively following the programming of a new frequency the PLL re-lock self clearing bit could be used.
If the device is left in the enabled state for long periods, it is recommended that VCO auto-selection and coarse tuning (band
selection) is performed for every 30°C change in temperature. The lock detect flag can be used to indicate when to perform
the VCO calibration, it shows that the VCO tuning voltage has drifted significantly with changing temperature.
The RESETX pin is a hardware reset control that will reset all digital circuits to their startup state when asserted low. The device
includes a power-on-reset function, so this pin should not normally be required, in which case it should be connected to the
positive supply.
The MODE pin controls which PLL programming register bank is active.
Serial Data Interface Control
The normal mode of operation uses the 3-wire serial data interface to program the device registers, and three extra hardware
control lines; MODE, ENBL and RESETX.
When the device is under software control, achieved by setting the SIPIN bit in the SDI_CTRL register high, then the hardware
can be controlled via the SDI_CTRL register. When this is the case, the three hardware control lines are not required. If the
device is under software control, pins 1 and 9 can be configured as general purpose outputs (GPO).
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RFMD2081
Multi-Slice Mode
ENX
SDATA
SCLK
Slice2
Slice2
Slice2
Slice2
(0)
(1)
(2)
(3)
A1 A2
A1 A2
A1 A2
V DD
V DD
A1 A2
V DD
V DD
The Multi-Slice mode of operation allows up to four chips to be controlled from a common serial bus. The device address pins,
(15 and 16) ADD1 and ADD2, are used to set the address of each part.
On power up, and after a Reset, the devices ignore the address pins ADD1 and ADD2 and any data presented to the serial bus
will be programmed into all the devices. However, once the ADDR bit in the SDI_CTRL register is set each device then adopts
an address according to the state of the address pins on the device.
General Purpose Outputs
The general purpose outputs (GPOs) can be controlled via the GPO register, and will depend on the state of MODE since they
can be set in different states corresponding to either path 1 or 2. The GPOs can be used for example to drive LEDs, or to control external circuitry such as switches or low power LNAs.
Each GPO pin can supply up to and above 20mA load current. The output voltage of the GPO high state will drop with increased
current drive, by approximately 25mV/mA. Similarly the output voltage of the GPO low state will rise with increased current,
again by approximately 25mV/mA.
Programming Information
Please refer to the register map and programming guides which are available for download from
http://rfmd.com/products/IntSynthModulator/.
Evaluation Boards
The evaluation board for the RFMD2081 is provided as part of a design kit, along with the necessary cables and programming
software tool to enable full evaluation of the device. The evaluation board has been configured for wideband operation; the
modulator output is connected to a wideband transmission line transformer balun. Design kits can be ordered from
www.rfmd.com or from local RFMD sales offices and authorized sales channels. For ordering codes please see "Ordering Information" on page 18. For further details on how to set up the design kits please refer to the user guide which can be downloaded from http://rfmd.com/products/IntSynthModulator/.
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RFMD2081
Detailed Functional Block Diagram
Biasing
& LDOs
Ext LO
Mux
/2n
[n=0..5]
I
Prescaler
Sequence
generator
Ndivider
/2 IQ
gen
Charge
pump
Phase
detector
Control
Reference
divider
Q
GPIO
Pin Out
GPO3 25
GPO4/LD/DO 26
NC 27
NC 28
RESETX 29
ENX 30
SCLK 31
SDATA 32
ENBL/GPO5 1
24 ANA_VDD2
23 MOD_I_P
EXT_LO 2
EXT_LO_DEC
3
REXT
4
22 MOD_I_N
ANA_VDD1 5
20 NC
LFILT1 6
19 MOD_Q_P
LFILT2 7
18 MOD_Q_N
LFILT3 8
17 DIG_VDD
16 GPO2/ADD2
15 GPO1/ADD1
14 RF_OUT_P
13 RF_OUT_N
12 TM
11 NC
10 REF_IN
9 MODE/GPO6
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21 NC
Exposed
paddle
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DS140110
RFMD2081
Application Schematic
LFILT1
LFILT2
R3
22K
C9
180pF
RESETX
ENX
SCLK
SDATA
ENBL
VDDA1
C34
10nF
C5
33pF
C35
33pF
51K
R1
R6 470R
Loop Filter
R2 470R
C8
8.2pF
C10
330pF
C15
33pF
7
6
C14
33pF
1
2
3
4
LFILT1
5
LFILT2
8
C13
33pF
C1
33pF
ENBL/GP05
EXT_LO
EXT_LO_DEC
REXT
ANA_VDD1
LFILT1
LFILT2
LFILT3
VCC
GND OUT
Y1
VC
VCTCXO
R9
470R
1
2
LFILT3
LFILT3
C17
330pF
470R
R32
3
4
C44
10nF
C16
1nF
U1
L1
DNI
GPO2
GPO1
GPO3
VDDA2
GREEN
D1
VDDA2
C2
33pF
C18
10nF
MOD_I_P
21
MOD_Q_P
20
MOD_Q_N
C19
10nF
C30
100pF
C29
100pF
50 OHM (0.5mm)
18
17
T1
6
4
19
VDDD
MOD_I_N
C3
33pF
22
RFXF8553
23
24
R13
220R
1
2
3
DIG_VDD
MOD_Q_N
MOD_Q_P
NC
NC
MOD_I_N
MOD_I_P
ANA_VDD2
GPO4
RFMD2081
R31
120R
VDDA2
+2.8V
C33
100pF
RF_OP
1
J4
RF_OP
11 of 18
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
DS140110
VDDA2
C43
10nF
2
26
GPO4/LD/DO
25
GPO3/FM
33
GPO2/ADD2
16
GPO1/ADD1
15
GND
27
NC
28
NC
RF_OUT_P
14
RF_OUT_N
13
30
ENX
29
RESETX
TM
12
31
SCLK
NC
11
32
SDATA
MODE/GP06
9
REF_IN
10
RFMD2081
Typical Performance Characteristics: Synthesizer
VDD = +3V and TA = +27°C unless stated otherwise, as measured on RFMD2081 evaluation board.
Synthesizer Phase Noise
Synthesizer Phase Noise
4000MHz VCO Frequency, 26MHz Crystal Oscillator
4000MHz VCO Frequency, 52MHz Crystal Oscillator
-60.0
-60.0
2000MHz
1000MHz
-70.0
-80.0
-80.0
500MHz
Phase Noise (dBc/Hz)
Phase Noise (dBc/Hz)
500MHz
-90.0
250MHz
125MHz
-100.0
2000MHz
1000MHz
-70.0
-110.0
-120.0
-130.0
-140.0
-150.0
-90.0
250MHz
125MHz
-100.0
-110.0
-120.0
-130.0
-140.0
-150.0
-160.0
-160.0
1.0
10.0
100.0
1000.0
10000.0
100000.0
1.0
10.0
Offset Frequency (KHz)
100.0
1000.0
100000.0
Synthesizer Phase Noise
Synthesizer Phase Noise
5200MHz VCO Frequency, 26MHz Crystal Oscillator
5200MHz VCO Frequency, 52MHz Crystal Oscillator
-60.0
-60.0
1300MHz
-80.0
2600MHz
1300MHz
-70.0
2600MHz
-70.0
-80.0
650MHz
-90.0
Phase Noise (dBc/Hz)
650MHz
Phase Noise (dBc/Hz)
10000.0
Offset Frequency (KHz)
325MHz
162.5MHz
-100.0
-110.0
-120.0
-130.0
-140.0
-90.0
325MHz
162.5MHz
-100.0
-110.0
-120.0
-130.0
-140.0
-150.0
-150.0
-160.0
-160.0
1.0
10.0
100.0
1000.0
10000.0
100000.0
1.0
10.0
100.0
1000.0
10000.0
100000.0
Offset Frequency (KHz)
Offset Frequency (KHz)
Synthesiser RMS Integrated Phase Noise
Integration Bandwidth 1KHz to 40MHz
Note:
• 26 MHz Crystal Oscillator: NDK ENA3523A
• 52 MHz Crystal Oscillator: NDK ENA3560A
RMS Integrated Phase Noise (Degrees)
0.6
26MHz TCXO
52MHz TCXO
0.5
0.4
0.3
0.2
0.1
0.0
0.0
500.0
1000.0
1500.0
2000.0
2500.0
3000.0
LO Frequency (MHz)
12 of 18
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
DS140110
RFMD2081
Typical Performance Characteristics: VCO
VDD = +3V and TA = +27°C unless stated otherwise, as measured on RFMD2081 evaluation board.
VCO1 Frequency versus Kvco
VCO1 Frequency versus CT_CAL
LO Divide by 2
VCO1 with LO Divide by 2
25
1800
-40 Deg C
1700
20
+85 Deg C
Kvco (MHz/V)
VCO Frequency (MHz)
+27 Deg C
1600
1500
VCO1
15
10
1400
5
1300
0
1200
1200
0
20
40
60
80
100
120
1300
1400
1500
1600
1700
1800
VCO Frequency /2 (MHz)
CT_CAL Word
VCO2 Frequency versus Kvco
VCO2 Frequency versus CT_CAL
LO Divide by 2
VCO2 with LO Divide by 2
30
2300
2200
-40 Deg C
25
+85 Deg C
Kvco (MHz/V)
VCO Frequency (MHz)
+27 Deg C
2100
2000
1900
VCO2
20
15
10
1800
5
1700
0
1600
1600
0
20
40
60
80
100
120
1700
1900
2000
2100
2200
2300
2800
2900
VCO3 Frequency versus Kvco
VCO3 Frequency versus CT_CAL
LO Divide by 2
VCO3 with LO Divide by 2
30
2900
2800
-40 Deg C
25
+27 Deg C
2700
+85 Deg C
Kvco (MHz/V)
VCO Frequency (MHz)
1800
VCO Frequency /2 (MHz)
CT_CAL Word
2600
2500
VCO3
20
15
2400
10
2300
5
2200
2100
0
20
40
60
CT_CAL Word
DS140110
80
100
120
0
2200
2300
2400
2500
2600
2700
VCO Frequency /2 (MHz)
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
13 of 18
RFMD2081
Typical Performance Characteristics: VCO
VDD = +3V and TA = +27°C unless stated otherwise, as measured on RFMD2081 evaluation board.
VCO1 Frequency versus Tuning Voltage
VCO2 Frequency versus Tuning Voltage
For the same coarse tune setting, LO divide by two
For the same coarse tune setting, LO divide by two
2020
1505
2015
1500
VCO2 Frequency /2 (MHz)
VCO1 Frequency /2 (MHz)
2010
1495
1490
1485
-40 Deg C
+27 Deg C
1480
+85 Deg C
2005
2000
1995
-40 Deg C
1990
+27 Deg C
+85 Deg C
1985
1980
1475
0.0
0.5
1.0
0.0
1.5
0.5
VCO Phase Noise
With LO Divide by 2
-60.0
2510
-70.0
2505
-80.0
Phase Noise (dBc/Hz)
VCO3 Frequency /2 (MHz)
VCO3 Frequency versus Tuning Voltage
For the same coarse tune setting, LO divide by two
2515
2500
2495
2490
2485
2480
-40 Deg C
2475
+27 Deg C
2470
+85 Deg C
0.0
0.5
1.0
Tuning Voltage (Volts)
1.5
2500MHz VCO3
2000MHz VCO2
1500MHz VCO1
-90.0
-100.0
-110.0
-120.0
-130.0
-140.0
-150.0
2465
14 of 18
1.0
Tuning Voltage (Volts)
Tuning Voltage (Volts)
1.5
-160.0
10.0
100.0
1000.0
10000.0
100000.0
Offset Frequency (KHz)
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
DS140110
RFMD2081
Typical Performance Characteristics: IQ Modulator
VDD = +3V and TA = +27°C unless stated otherwise, as measured on RFMD2081 evaluation board. I and Q input
level 1VP-P differential
Modulator Typical Performance
with +1.3V DC bias.
Modulator Typical Performance
I & Q Unadjusted, Output Unmatched
Wanted Signal
Sideband Suppression
-20.0
20.0
-10.0
15.0
Suppression (dBc)
Wanted Signal Level (dBm)
-10.0
Linearity, Output Unmatched
0.0
-20.0
LO Suppression
-30.0
-30.0
IM3 Product
-40.0
-40.0
-50.0
-50.0
10.0
Output Level (dBm)
0.0
5.0
0.0
-5.0
-10.0
Wanted Signal
-60.0
-60.0
Output P1dB
-15.0
Output IP3
-70.0
0.0
500.0
1000.0
1500.0
2000.0
2500.0
-70.0
3000.0
-20.0
0.0
Output Frequency (MHz)
500.0
1000.0
1500.0
2000.0
2500.0
3000.0
Output Frequency (MHz)
Typical Total Supply Current
Modulator Performance Vs Common Mode Bias Voltage
+3.0V Supply
Output Frequency = 1250 MHz
20.0
165
10.0
160
160.0
1.0V Bias
1.1V Bias
150.0
0.0
155
-10.0
150
1.2V Bias
145
Wanted Signal
Output P1dB
-30.0
140
Output IP3
IM3 Product
-40.0
135
Supply Current
-50.0
130
-60.0
125
Current (mA)
-20.0
Supply Current (mA)
Output Level (dBm)
1.3V Bias
1.4V Bias
140.0
1.5V Bias
130.0
120.0
110.0
-70.0
120
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1
Input Common Mode Bias Voltage (Volts)
100.0
0.0
500.0
1000.0
1500.0
2000.0
2500.0
3000.0
Output Frequency (MHz)
Modulator Output Frequency Response
Versus Shunt Matching Inductor Value
Wanted Signal Level (dBm)
0.0
The modulator output power can be improved
as output frequency increases by using a
shunt inductor (L1 on Application Schematic)
to resonate with the modulator output capacitance, typically 1 pF.
-10.0
Unmatched
-20.0
27nH Shunt
15nH Shunt
8.2nH Shunt
3.9nH Shunt
-30.0
The output transformer used for characterization is the RFXF8553 (T1) which has 3 dB cut
off point at 2500 MHz.
2.7nH Shunt
-40.0
-50.0
0.0
500.0
1000.0
1500.0
2000.0
2500.0
3000.0
Output Frequency (MHz)
DS140110
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
15 of 18
RFMD2081
Typical Performance Characteristics: IQ Modulator
VDD = +3V and TA = +27°C unless stated otherwise, as measured on RFMD2081 evaluation board. I and Q input
level 1VP-P differential with +1.3V DC bias.
Modulator Output Power
Modulator Unadjusted LO Suppression
Vs Temperature & Supply Voltage
Vs Temperature & Supply Voltage
-30.0
-40DegC, +2.7V
-40DegC, +2.7V
-40DegC, +3.0V
-2.0
-40DegC, +3.0V
-40DegC, +3.3V
-40DegC, +3.3V
LO Suppression (dBc)
Wanted Signal Level (dBm)
0.0
+27DegC, +2.7V
+27DegC, +3.0V
-4.0
+27DegC, +3.3V
+85DegC, +2.7V
-6.0
+85DegC, +3.0V
+85DegC, +3.3V
-8.0
-10.0
+27DegC, +2.7V
-35.0
+27DegC, +3.0V
+27DegC, +3.3V
+85DegC, +2.7V
+85DegC, +3.0V
-40.0
+85DegC, +3.3V
-45.0
-12.0
-14.0
0.0
500.0
1000.0
1500.0
2000.0
2500.0
-50.0
3000.0
0.0
500.0
1000.0
Output Frequency (MHz)
1500.0
2000.0
2500.0
Modulator Unadjusted Sideband Suppression
Modulator IM3 Output Tone
Vs Temperature & Supply Voltage
Vs Temperature & Supply Voltage
-30.0
3000.0
Output Frequency (MHz)
-40.0
-40DegC, +2.7V
-40DegC, +3.3V
-35.0
+27DegC, +2.7V
+27DegC, +3.0V
IM3 Product (dBc)
Sideband Suppression (dBc)
-40DegC, +3.0V
+27DegC, +3.3V
-40.0
+85DegC, +2.7V
+85DegC, +3.0V
+85DegC, +3.3V
-45.0
-50.0
-45.0
-50.0
-40DegC, +2.7V
-40DegC, +3.0V
-40DegC, +3.3V
+27DegC, +2.7V
+27DegC, +3.0V
-55.0
+27DegC, +3.3V
-55.0
+85DegC, +2.7V
+85DegC, +3.0V
+85DegC, +3.3V
-60.0
-60.0
0.0
500.0
1000.0
1500.0
2000.0
2500.0
0.0
3000.0
500.0
1000.0
1500.0
2000.0
2500.0
3000.0
Output Frequency (MHz)
Output Frequency (MHz)
Modulator Output Power for 1dB Compression
Modulator Output IP3
Vs Temperature & Supply Voltage
Vs Temperature & Supply Voltage
8.0
20.0
6.0
18.0
4.0
16.0
-40DegC, +2.7V
-40DegC, +3.0V
+27DegC, +2.7V
Output IP3 (dBm)
Output Level (dBm)
-40DegC, +3.3V
2.0
-40DegC, +2.7V
-40DegC, +3.0V
0.0
-40DegC, +3.3V
+27DegC, +2.7V
-2.0
+27DegC, +3.0V
+27DegC, +3.0V
+27DegC, +3.3V
+85DegC, +2.7V
14.0
+85DegC, +3.0V
+85DegC, +3.3V
12.0
10.0
+27DegC, +3.3V
+85DegC, +2.7V
-4.0
8.0
+85DegC, +3.0V
+85DegC, +3.3V
-6.0
0.0
500.0
1000.0
1500.0
2000.0
Output Frequency (MHz)
16 of 18
2500.0
3000.0
6.0
0.0
500.0
1000.0
1500.0
2000.0
2500.0
3000.0
Output Frequency (MHz)
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
DS140110
RFMD2081
Typical Performance Characteristics: IQ Modulator
VDD = +3V and TA = +27°C unless stated otherwise, as measured on RFMD2081 evaluation board. I and Q input
level 1VP-P differential with +1.3V DC bias.
Modulator Input Voltage For 1dB Compression
Vs Temperature & Supply Voltage
-40DegC, +2.7V
2.50
-40DegC, +3.0V
Peak to Peak Differential Voltage
-40DegC, +3.3V
+27DegC, +2.7V
2.25
+27DegC, +3.0V
+27DegC, +3.3V
+85DegC, +2.7V
2.00
+85DegC, +3.0V
+85DegC, +3.3V
1.75
1.50
1.25
1.00
0.0
500.0
1000.0
1500.0
2000.0
2500.0
3000.0
Output Frequency (MHz)
Modulator Output Noise Floor
Modulator Output Noise Floor
1MHz Offset
5MHz Offset
-120.0
-40DegC, +2.7V
-40DegC, +2.7V
Output Noise Floor (dBm/Hz)
-40DegC, +3.0V
-130.0
-40DegC, +3.3V
+27DegC, +2.7V
+27DegC, +3.0V
-140.0
+27DegC, +3.3V
+85DegC, +2.7V
+85DegC, +3.0V
-150.0
+85DegC, +3.3V
-160.0
-170.0
0.0
500.0
1000.0
1500.0
2000.0
2500.0
-40DegC, +3.0V
-130.0
-40DegC, +3.3V
+27DegC, +2.7V
+27DegC, +3.0V
-140.0
+27DegC, +3.3V
+85DegC, +2.7V
+85DegC, +3.0V
-150.0
+85DegC, +3.3V
-160.0
-170.0
3000.0
0.0
Output Frequency (MHz)
1500.0
120.0
-20.0
110.0
-30.0
100.0
-40.0
90.0
80.0
Wanted Signal dBm
Output Level (dBm)
-10.0
Current (mA)
130.0
120.0
5.0
115.0
0.0
110.0
-5.0
105.0
-10.0
100.0
-15.0
95.0
Wanted Signal dBm
-20.0
90.0
Output IP3 dBm
Sideband Suppresion dBc
70.0
IM3 Product dBc
Output P1dB dBm
-25.0
60.0
2
Modulator Attenuator Setting (mod)
DS140110
85.0
Current mA
Current mA
-70.0
1
3000.0
10.0
LO Suppression dBc
0
2500.0
Output Frequency = 1500MHz
0.0
-60.0
2000.0
Effect of Attenuator Setting on Gain & Linearity
Unadjusted, Output Frequency = 1500MHz
Output (dB)
1000.0
Output Frequency (MHz)
Effect of Attenuator Setting on Modulator
-50.0
500.0
Current (mA)
Output Noise Floor (dBm/Hz)
-120.0
3
-30.0
80.0
0
1
2
3
Modulator Attenuator Setting (mod)
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
17 of 18
RFMD2081
.Package Drawing
QFN, 32-pin, 5mm x 5mm
Ordering Information
18 of 18
Ordering Code
Package
Quantity
RFMD2081SB
RFMD2081SQ
RFMD2081SR
RFMD2081TR7
RFMD2081TR13
DKMD2081
32-Pin QFN
32-Pin QFN
32-Pin QFN
32-Pin QFN
32-Pin QFN
Complete Design Kit
5-Piece sample bag
25-Piece sample bag
100-Piece reel
750-Piece reel
2500-Piece reel
1 Box
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
DS140110