RFFC5071/5072

RFFC5071/5072
WIDEBAND SYNTHESIZER/VCO WITH
INTEGRATED 6GHz MIXER
Package: QFN, 32-Pin, 5mm x 5mm
RFFC5071
RFFC5072
Features





85MHz to 4200MHz LO
Frequency Range
Fractional-N Synthesizer with
Very Low Spurious Levels
Phase
det.
Synth
Phase
det.
Synth
Typical Step Size 1.5Hz
Fully Integrated Low Phase Noise
VCO and LO Buffers
Integrated Phase Noise
Ref.
divider
Ref.
divider
• 0.18° rms at 1GHz
• 0.50° rms at 3GHz




High Linearity RF Mixer(s)
30MHz to 6000MHz Mixer
Frequency Range
Input IP3 +23dBm
Mixer Bias Adjustable for Low
Power Operation

Full Duplex Mode (RFFC5071)

2.7V to 3.3V Power Supply

Low Current Consumption

3- or 4-Wire Serial Interface
Applications

Wideband Radios

Distributed Antenna Systems

Diversity Receivers

Software Defined Radios

Frequency Band Shifters

Point-to-Point Radios

WiMax/LTE Infrastructure

Satellite Communications

Wideband Jammers
Functional Block Diagram
Product Description
The RFFC5071 and RFFC5072 are re-configurable frequency conversion devices
with integrated fractional-N phased locked loop (PLL) synthesizer, voltage controlled oscillator (VCO) and either one or two high linearity mixers. The fractional-N
synthesizer takes advantage of an advanced sigma-delta modulator that delivers
ultra-fine step sizes and low spurious products. The PLL/VCO engine combined with
an external loop filter allows the user to generate local oscillator (LO) signals from
85MHz to 4200MHz. The LO signal is buffered and routed to the integrated RF mixers which are used to up/down-convert frequencies ranging from 30MHz to
6000MHz. The mixer bias current is programmable and can be reduced for applications requiring lower power consumption. Both devices can be configured to work
as signal sources by bypassing the integrated mixers. Device programming is
achieved via a simple 3-wire serial interface. In addition, a unique programming
mode allows up to four devices to be controlled from a common serial bus. This
eliminates the need for separate chip-select control lines between each device and
the host controller. Up to six general purpose outputs are provided, which can be
used to access internal signals (the LOCK signal, for example) or to control front
end components. Both devices operate with a 2.7V to 3.3V power supply.
Optimum Technology Matching® Applied
GaAs HBT
GaAs MESFET
InGaP HBT
SiGe BiCMOS
Si BiCMOS
SiGe HBT
GaAs pHEMT
Si CMOS
Si BJT
GaN HEMT
BiFET HBT
LDMOS
RF MICRO DEVICES®, RFMD®, Optimum Technology Matching®, Enabling Wireless Connectivity™, PowerStar®, POLARIS™ TOTAL RADIO™ and UltimateBlue™ are trademarks of RFMD, LLC. BLUETOOTH is a trademark owned by Bluetooth SIG, Inc., U.S.A. and licensed for use by RFMD. All other trade names, trademarks and registered trademarks are the property of their respective owners. ©2012, RF Micro Devices, Inc.
DS140110
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RFFC5071/5072
Absolute Maximum Ratings
Parameter
Supply Voltage (VDD)
Input Voltage (VIN) any pin
Rating
Unit
-0.5 to +3.6
V
-0.3 to VDD + 0.3
V
+15
dBm
Operating Temperature Range
-40 to +85
°C
Storage Temperature Range
-65 to +150
°C
RF/IF mixer input power
Caution! ESD sensitive device.
Exceeding any one or a combination of the Absolute Maximum Rating conditions may
cause permanent damage to the device. Extended application of Absolute Maximum
Rating conditions to the device may reduce device reliability. Specified typical performance or functional operation of the device under Absolute Maximum Rating conditions is not implied.
The information in this publication is believed to be accurate and reliable. However, no
responsibility is assumed by RF Micro Devices, Inc. ("RFMD") for its use, nor for any
infringement of patents, or other rights of third parties, resulting from its use. No
license is granted by implication or otherwise under any patent or patent rights of
RFMD. RFMD reserves the right to change component circuitry, recommended application circuitry and specifications at any time without prior notice.
RFMD Green: RoHS compliant per EU Directive 2002/95/EC, halogen free
per IEC 61249-2-21, < 1000ppm each of antimony trioxide in polymeric
materials and red phosphorus as a flame retardant, and <2% antimony in
solder.
Parameter
Min.
Specification
Typ.
Max.
Unit
Condition
ESD Requirements
Human Body Model
Charge Device Model
2000
V
1500
V
DC Pins
All Pins
500
V
All Pins
Operating Conditions
Supply voltage (VDD)
2.7
Temperature (TOP)
-40
3.0
3.3
V
+85
°C
Logic Inputs/Outputs (VDD = Supply to DIG_VDD pin)
Input low voltage
-0.3
+0.5
V
Input high voltage
VDD / 1.5
VDD
V
Input low current
-10
+10
A
Input = 0V
Input high current
-10
+10
A
Input = VDD
Output low voltage
0
0.2*VDD
V
Output high voltage
0.8*VDD
VDD
Load resistance
10
V
kΩ
Load capacitance
20
pF
GPO Drive Capability
Sink Current
20
mA
At VOL = +0.6V
Source Current
20
mA
At VOL = +2.4V
Output Impedance
25
Ω
100
mA
Low current, MIX_IDD=1, one mixer enabled.
125
mA
High linearity, MIX_IDD=6, one mixer enabled.
2
mA
Reference oscillator and bandgap only.
300
A
ENBL=0 and REF_STBY=0
Static
Supply Current (IDD) with 1GHz LO
Standby
Power Down Current
Mixer 1/2 (Mixer output driving 4:1 balun)
Gain
-2
dB
Not including balun losses
Noise Figure <3000MHz
10
dB
Low current setting
13
dB
High linearity setting
11
dB
Low current setting
15
dB
High linearity setting
Noise Figure <4000MHz
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RFFC5071/5072
Parameter
Min.
Specification
Typ.
Max.
Unit
Condition
Mixer 1/2 (Mixer output driving 4:1 balun) (continued)
IIP3
Input Port Frequency range
+10
dBm
Low current setting
+23
dBm
High linearity setting
30
Mixer input return loss
6000
MHz
4500
MHz
6000
MHz
10
Output port frequency range
30
dB
100Ω differential
Mixer 1/2 (Mixer output driving 1:1 balun)
Output Port Frequency Range
30
Gain
-7
dB
Not including balun losses
Reference Oscillator
External reference frequency
10
104
Reference divider ratio
1
7
External reference input level
500
800
MHz
1500
mVp-p
4200
MHz
AC-coupled
Synthesizer (PLL Closed Loop, 52MHz)
Synthesizer Output Frequency
85
Phase detector frequency
52
Phase noise (LO = 1GHz)
Phase noise (LO = 2GHz)
Phase noise (LO = 3GHz)
Phase noise (LO = 4GHz)
MHz
-108
dBc/Hz
-108
dBc/Hz
10kHz offset
100kHz offset
-135
dBc/Hz
1MHz offset
0.19
°
-102
dBc/Hz
-102
dBc/Hz
100kHz offset
-130
dBc/Hz
1MHz offset
0.32
°
-97
dBc/Hz
RMS integrated from 1kHz to 40MHz
10kHz offset
RMS integrated from 1kHz to 40MHz
10kHz offset
-97
dBc/Hz
100kHz offset
-124
dBc/Hz
1MHz offset
0.50
°
-95
dBc/Hz
10kHz offset
RMS integrated from 1kHz to 40MHz
100kHz offset
-96
dBc/Hz
-124
dBc/Hz
0.61
°
RMS integrated from 1kHz to 40MHz
-214
dBc/Hz
Measured at 20kHz to 30kHz offset
2.5GHz LO frequency
-134
dBc/Hz
VCO3, LO Divide by 2
2.0GHz LO frequency
-135
dBc/Hz
VCO2, LO Divide by 2
1.5GHz LO frequency
-136
dBc/Hz
VCO1, LO Divide by 2
Normalized phase noise floor
1MHz offset
Voltage Controlled Oscillator
Open loop phase noise at 1MHz offset
Open loop phase noise at 10MHz offset
2.5GHz LO frequency
-149
dBc/Hz
VCO3, LO Divide by 2
2.0GHz LO frequency
-150
dBc/Hz
VCO2, LO Divide by 2
1.5GHz LO frequency
-151
dBc/Hz
VCO1, LO Divide by 2
External LO Input
LO Input Frequency Range
85
4200
MHz
LO Input Frequency Range
85
5400
MHz
LO Divide by 2
dBm
Driven from 50 Source Via a 1:1 Balun
External LO Input Level
DS140110
0
LO Divide by 1
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RFFC5071/5072
Pin Names and Descriptions
Pin
Name
Description
1
ENBL/GPO5 Device Enable pin (see note 1 and 2).
External local oscillator input (See note 4).
2
EXT_LO
3
EXT_LO_DEC Decoupling pin for external local oscillator (See note 4).
External bandgap bias resistor (See note 3).
4
REXT
5
ANA_VDD1 Analog supply. Use good RF decoupling.
Phase detector output. Low-frequency noise-sensitive node.
6
LFILT1
Loop filter op-amp output. Low-frequency noise-sensitive node.
7
LFILT2
VCO control input. Low-frequency noise-sensitive node.
8
LFILT3
9
MODE/GPO6 Mode select pin (See note 1 and 2).
Reference input. Use AC coupling capacitor.
10
REF_IN
11
NC
Connect to ground.
12
TM
Differential input 1 (see note 4). On RFFC5072 this pin is NC.
13
MIX1_IPN
Differential input 1 (see note 4). On RFFC5072 this pin is NC.
14
MIX1_IPP
15
GPO1/ADD1 General purpose output / MultiSlice address bit.
16
GPO2/ADD2 General purpose output / MultiSlice address bit.
17
MIX1_OPN Differential output 1 (see note 5). On RFFC5072 this pin is NC.
18
MIX1_OPP Differential output 1 (see note 5). On RFFC5072 this pin is NC.
Digital supply. Should be decoupled as close to the pin as possible.
19
DIG_VDD
20
NC
21
NC
22
ANA_VDD2 Analog supply. Use good RF decoupling.
Differential input 2 (see note 4).
23
MIX2_IPP
Differential input 2 (see note 4).
24
MIX2_IPN
General purpose output / frequency control input.
25
GPO3/FM
26
GPO4/LD/DO General purpose output / Lock detect output / serial data out.
27
MIX2_OPN Differential output 2. (see note 5).
28
MIX2_OPP Differential output 2. (see note 5).
Chip reset (active low). Connect to DIG_VDD if asynchronous reset is not required.
29
RESETX
Serial interface select (active low) (See note 1).
30
ENX
Serial interface clock (see note 1).
31
SCLK
Serial interface data (see note 1).
32
SDATA
Ground reference, should be connected to PCB ground through a low impedance path.
Exposed paddle
Note 1: An RC low-pass filter could be used on this line to reduce digital noise.
Note 2: If the device is under software control this input can be configured as a general purpose output (GPO).
Note 3: Connect a 51K resistor from this pin to ground. This pin is sensitive to low frequency noise injection.
Note 4: DC voltage should not be applied to this pin. Use either an AC coupling capacitor as part of lumped element matching
network or a transformer (see application schematic).
Note 5: This pin must be connected to ANA_VDD2 using an RF choke or transformer (see application schematic).
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RFFC5071/5072
Theory of Operation
The RFFC5071 and RFFC5072 are wideband RF frequency converter chips which include a fractional-N synthesizer and a low
noise VCO core. The RFFC5071 has an LO signal multiplexer, two LO buffer circuits, and two RF mixers. The RFFC5072 has a
single LO buffer circuit and one RF mixer. Both devices have an integrated voltage reference and low drop out regulators supplying critical circuit blocks such as the VCOs and synthesizer. Synthesizer programming, device configuration and control are
achieved through a mixture of hardware and software controls. All on-chip registers are programmed through a simple 3-wire
serial interface.
VCO
The VCO core in the RFFC5071 and RFFC5072 consists of three VCOs which, in conjunction with the integrated LO dividers of
/2 to /32, cover the LO range of 85MHz to 4200MHz. Each VCO has 128 overlapping bands which are used to achieve low VCO
gain and optimal phase noise performance across the whole tuning range. The chip automatically selects the correct VCO (VCO
auto-select) and VCO band (VCO coarse tuning) to generate the desired LO frequency based on the values programmed into
the PLL1 and PLL2 registers banks.
The VCO auto-select and VCO coarse tuning are triggered every time ENBL is taken high, or if the PLL re-lock self clearing bit is
programmed high. Once the correct VCO and band have been selected the PLL will lock onto the correct frequency. During the
band selection process, fixed capacitance elements are progressively connected to the VCO resonant circuit until the VCO is
oscillating approximately at the correct frequency. The output of this band selection, CT_CAL, is made available in the readback register. A value of 127 or 0 in this register indicates that the coarse tuning was unsuccessful, and this will also be indicated by the CT_FAILED flag also available in the read-back register. A CT_CAL value between 1 and 126 indicates a successful calibration, the actual value being dependent on the desired frequency as well as process variation for a particular device.
The band select process will center the VCO tuning voltage at about 1.0V, compensating for manufacturing tolerances and process variation as well as environmental factors including temperature. In applications where the device is left enabled at the
same LO frequency for some time, it is recommended that automatic band selection be performed for every 30°C change in
temperature. This assumes an active loop filter.
The RFFC5071 and RFFC5072 feature a differential LO input to allow the mixer to be driven from an external LO source. The
fractional-N PLL can be used with an external VCO driven into this LO input, which may be useful to reduce phase noise in
some applications. This may also require an external op-amp, dependant on the tuning voltage required by the external VCO.
In the RFFC5071 the LO signal is routed to mixer 1, mixer 2, or both mixers depending on the state of the MODE pin (or MODE
bit if under software control) and the value of the FULLD bit. Setting FULLD high puts the device into Full Duplex mode and both
mixers are enabled.
Fractional-N PLL
The RFFC5071 and RFFC5072 contain a charge pump-based fractional-N phase locked loop (PLL) for controlling the three
VCOs. The PLL includes automatic calibration systems to counteract the effects of process and environmental variations,
ensuring repeatable loop response and phase noise performance. As well as the VCO auto-select and coarse tuning, there is a
loop filter calibration mechanism which can be enabled if required. This operates by adjusting the charge pump current to
maintain loop bandwidth. This can be useful for applications where the LO is tuned over a wide frequency range.
The PLL has been designed to use a reference frequency of between 10MHz and 104MHz from an external source, which is
typically a temperature controlled crystal oscillator (TCXO). A reference divider (divide by 1 to divide by 7) is supplied and
should be programmed to limit the frequency at the phase detector to a maximum of 52MHz.
Two PLL programming banks are provided, the first bank is preceded by the label PLL1 and the second bank is preceded by the
label PLL2. For the RFFC5071 these banks are used to program mixer 1 and mixer 2 respectively, and are selected automatically as the mixer is selected using MODE. For the RFFC5072 mixer 2 and register bank PLL2 are normally used.
The VCO outputs are first divided down in a high frequency prescalar. The output of this high frequency prescalar then enters
the N divider, which is a fractional divider containing a dual-modulus prescaler and a digitally spur-compensated fractional
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RFFC5071/5072
sequence generator. This allows very fine frequency steps and minimizes fractional spurs. The fractional energy is randomized
and appears as fractional noise at frequency offsets above 100kHz which will be attenuated by the loop filter. An external loop
filter is used, giving flexibility in setting loop bandwidth for optimizing phase noise and lock time, for example.
The synthesizer step size is typically 1.5Hz when using a 26MHz reference frequency. The exact step size for any reference and
LO frequency can be calculated using the following formula:
(FREF * P) / (R * 224 * LO_DIV)
Where FREF is the reference frequency, R is the reference division ratio, P is the prescalar division ratio, and LO_DIV is the LO
divider value.
Pin 26 (GPO4) can be configured as a lock detect pin. The lock status is also available in the read-back register. The lock detect
function is a window detector on the VCO tuning voltage. The lock flag will be high to show PLL lock which corresponds to the
VCO tuning voltage being within the specified range, typically 0.30V to 1.25V.
The lock time of the PLL will depend on a number of factors; including the loop bandwidth and the reference frequency at the
phase detector. This clock frequency determines the speed at which the state machine and internal calibrations run. A 52MHz
phase detector frequency will give fastest lock times, of typically <50secs when using the PLL re-lock bit.
Phase Detector and Charge Pump
The phase detector provides a current output to drive an active loop filter. The charge pump output current is set by the value
contained in the P1_CP_DEF and P2_CP_DEF fields in the loop filter configuration register. The charge pump current is given
by approximately 3A/bit, and the fields are 6 bits long. This gives default value (31) of 93A and maximum value (63) of
189A.
If the automatic loop bandwidth calibration is enabled the charge pump current is set by the calibration algorithm based upon
the VCO gain.
The phase detector will operate with a maximum input frequency of 52MHz.
Loop Filter
The active loop filter is implemented using the on-chip low noise op-amp with external resistors and capacitors. The internal
configuration of the chip is shown below with the recommended active loop filter. The op-amp gives a tuning voltage range of
typically +0.1V to +2.4V. The recommended loop filter shown is designed to give the lowest integrated phase noise for reference frequencies of 26MHz and 52MHz. The external loop filter gives the flexibility to optimize the loop response for any particular application and combination of reference and VCO frequencies.
8p2
LFILT1
180p
22K
LFILT2
470R
330p
+1.1V
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470R
LFILT3
330p
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RFFC5071/5072
External Reference
The RFFC5071 and RFFC5072 have been designed to use an external reference such as a TCXO. The typical input will be a
0.8Vp-p clipped sine wave, which should be AC-coupled into the reference input. When the PLL is not in use, it may be desirable to turn off the internal reference circuits, by setting the REFSTBY bit low, to minimize current draw while in standby mode.
On cold start, or if REFSTBY is programmed low, the reference circuits will need a warm-up period. This is set by the SU_WAIT
bits. This will allow the clock to be stable and immediately available when the ENBL bit is asserted high, allowing the PLL to
assume normal operation.
If the current consumption of the reference circuits in standby mode, typically 2mA, is not critical, then the REFSTBY bit can be
set high. This allows the fastest startup and lock time after ENBL is taken high.
Wideband Mixer
The mixers are wideband, double-balanced Gilbert cells. They support RF/IF frequencies from 30MHz up to 6000MHz. Each
mixer has an input port and an output port that can be used for either IF or RF (in other words, for up- or down-conversion). The
mixer current can be programmed to between about 15mA and 45mA depending on linearity requirements. The majority of the
mixer current is sourced through the output pins via either a center-tapped balun or an RF choke in the external matching circuitry to the supply.
The RF mixer input and output ports are differential and require baluns and simple matching circuits optimized to the specific
application frequencies. A conversion gain of approximately -2dB (not including balun losses) is achieved with 100 differential input impedance, and the outputs driving 200 differential load impedance. Increasing the mixer output load increases
the conversion gain.
The mixer has a broadband common gate input. The input impedance is dominated by the resistance set by the mixer 1/gm
term, which is inversely proportional to the mixer current setting. The resistance will be approximately 85 at the default mixer
current setting (100). There is also some shunt capacitance at the mixer input, and the inductance of the bond wires (about
0.5nH on each pin) to consider at higher frequencies. The following diagram is a simple model of the mixer input impedance:
0.5nH
RFFC507x
Mixer Input
0.5pF
Rin
Typ 85
0.5nH
The mixer output is high impedance, consisting of approximately 2k resistance in parallel with some capacitance, approximately 1pF dependent on PCB layout. The mixer output does not require a conjugate matching network. It is a constant current
output which will drive a real differential load of between 50Ω and 500Ω, typically 200Ω. Since the mixer output is a constant
current source, a higher resistance load will give higher output voltage and gain. A shunt inductor can be used to resonate with
the mixer output capacitance at the frequency of interest. This inductor may not be required at lower frequencies where the
impedance of the output capacitance is less significant. At higher output frequencies the inductance of the bond wires (about
0.5nH on each pin) becomes more significant. Above about 4500MHz, it is beneficial to lower the output load to 50 to minimize the effect of the ouput capacitance. The following diagram is a simple model of the mixer output:
0.5nH
1K
RFFC207x
Mixer Output
1pF
1K
DS140110
0.5nH
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RFFC5071/5072
The RFFC5071 mixer layout and pin placement has been optimized for high mixer-to-mixer isolation of greater than 60dB. The
mixers can be set up to operate in half duplex mode (1 mixer active) or full duplex mode (both mixers active). This selection is
done via control of MODE and by setting the FULLD bit. When in full duplex mode, either PLL register bank can be used, the LO
signal is routed to both mixers.
Mode
FULLD
Active PLL
Active
Register Bank Mixer
LOW
0
1
HIGH
0
2
1
2
LOW
1
1
1 and 2
HIGH
1
2
1 and 2
Serial Interface
All on-chip registers in the RFFC5071 and RFFC5072 are programmed using a proprietary 3-wire serial bus which supports
both write and read operations. Synthesizer programming, device configuration, and control are achieved through a mixture of
hardware and software controls. Certain functions and operations require the use of hardware controls via the ENBL, MODE,
and RESETB pins in addition to programming via the serial bus. Alternatively there is the option to control the chip completely
via the serial bus.
The serial data interface can be configured for 4-wire operation by setting the 4WIRE bit in the SDI_CTRL register high. Then
pin 26 is used as the data out pin, and pin 32 is the serial data in pin.
Hardware Control
Three hardware control pins are provided: ENBL, MODE, and RESETB.
The ENBL pin has two functions: to enable the analog circuits in the chip and to trigger the VCO auto-selection and coarse tuning mechanisms. The VCO auto-selection and coarse tuning is initiated when the ENBL pin is taken high. Every time the frequency of the synthesizer is reprogrammed, ENBL has to be asserted high to initiate these mechanisms and then to initiate the
PLL locking. Alternatively following the programming of a new frequency the PLL re-lock self clearing bit could be used.
If the device is left in the enabled state for long periods, it is recommended that VCO auto-selection and coarse tuning (band
selection) is performed for every 30°C change in temperature. The lock detect flag can be used to indicate when to perform
the VCO calibration, it shows that the VCO tuning voltage has drifted significantly with changing temperature.
The RESETB pin is a hardware reset control that will reset all digital circuits to their startup state when asserted low. The device
includes a power-on-reset function, so this pin should not normally be required, in which case it should be connected to the
positive supply.
The MODE pin controls which mixer(s) and PLL programming register bank is active.
Serial Data Interface Control
The normal mode of operation uses the 3-wire serial data interface to program the device registers, and three extra hardware
control lines: MODE, ENBL and RESETB.
When the device is under software control, achieved by setting the SIPIN bit in the SDI_CTRL register high, then the hardware
can be controlled via the SDI_CTRL register. When this is the case, the three hardware control lines are not required. If the
device is under software control, pins 1 and 9 can be configured as general purpose outputs (GPO).
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DS140110
RFFC5071/5072
Multi-Slice Mode
ENX
SDATA
SCLK
Slice2
(0)
Slice2
(1)
A1 A2
A1 A2
Slice2
(2)
Slice2
(3)
A1 A2
Vdd
A1 A2
Vdd
Vdd
Vdd
The Multi-Slice mode of operation allows up to four chips to be controlled from a common serial bus. The device address pins
(15 and 16) ADD1 and ADD2 are used to set the address of each part.
On power up, and after a reset, the devices ignore the address pins ADD1 and ADD2 and any data presented to the serial bus
will be programmed into all the devices. However, once the ADDR bit in the SDI_CTRL register is set, each device then adopts
an address according to the state of the address pins on the device.
General Purpose Outputs
The general purpose outputs (GPOs) can be controlled via the GPO register and will depend on the state of MODE since they
can be set in different states corresponding to either mixer path 1 or 2. For example, the GPOs can be used to drive LEDs or to
control external circuitry such as switches or low power LNAs.
Each GPO pin can supply approximately 20mA load current. The output voltage of the GPO high state will drop with increased
current drive by approximately 25mV/mA. Similarly the output voltage of the GPO low state will rise with increased current,
again by approximately 25mV/mA.
External Modulation
The RFFC5071 and RFFC5072 fractional-N synthesizer can be used to modulate the frequency of the VCO. There are two dedicated registers, EXT_MOD and FMOD, which can be used to configure the device as a modulator. It is possible to modulate the
VCO in two ways:
1.Binary FSK
The MODSETUP bits in the EXT_MOD register are set to 11. GPO3 is then configured as an input and used to control the signal
frequency. The frequency deviation is set by the MODSTEP and MODULATION bits in the EXT_MOD and FMOD registers respectively.
The modulation frequency is calculated according to the following formula:
F MOD = 2
MODSTEP
 F PD   MODULATION   2
16
Where MODULATION is a 2's complement number and FPD is the phase detector frequency.
2.Continuous Modulation
The MODSETUP bits in the EXT_MOD register are set to 01. The frequency deviation is set by the MODSTEP and MODULATION
bits in the EXT_MOD and FMOD registers respectively. The VCO frequency is then changed by writing a new value into the MOD-
DS140110
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support, contact RFMD at (+1) 336-678-5570 or [email protected].
9 of 26
RFFC5071/5072
ULATION bits, the VCO frequency is instantly updated. An arbitrary frequency modulation can then be performed dependant
only on the rate at which values are written into the FMOD register.
The modulation frequency is calculated according to the following formula:
F MOD = 2
MODSTEP
 F PD   MODULATION   2
16
Where MODULATION is a 2's complement number and FPD is the phase detector frequency.
Programming Information
The RFFC5071 and RFFC5072 share a common serial interface and control block. Please refer to the Register Maps and Programming Guide which are available for download from http://rfmd.com/products/IntSynthMixer/.
Evaluation Boards
Evaluation boards for RFFC5071 and RFFC5072 are provided as part of a design kit, along with the necessary cables and programming software tool to enable full evaluation of the device. Design kits can be ordered from www.rfmd.com or from local
RFMD sales offices and authorized sales channels. For ordering codes please see “Ordering Information” on page 26.
For further details on how to set up the design kits go to http://rfmd.com/products/IntSynthMixer/.
The standard evaluation boards are configured with 3.7GHz ceramic baluns on the RF ports and wideband transformers on the
IF ports. On the RFFC5071 evaluation board, mixer 1 is configured for down-conversion and mixer 2 is configured for up-conversion. On the RFFC5072 evaluation board, mixer 2 is configured for down conversion.
10 of 26
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DS140110
RFFC5071/5072
Detailed Functional Block Diagram
+3V
OP2
RFXF8553
4:1 Balun
RFXF9503
1:1 Balun
Ext LO
Mux
Mixer 2
Prescaler
Sequence
generator
N
divider
Charge
pump
ENX
SDATA
SCLK
Control
3-Wire
Serial
Bus
/2n
[n=0...5]
Phase
detector
Reference
divider
MODE
ENBL
RESET
+3V
Biasing
& LDOs
Loop
Filter
Control
Lines
IP2
51K
+3V
OP1
Mixer 1
GPO
RFXF8553
4:1 Balun
Lock
Flag
IP1
XO
RFXF9503
1:1 Balun
RFFC5071 Only
Note: Wideband transmission line transformer baluns shown above for operation to ~2.5GHz. Substitute baluns for higher frequency applications as required.
DS140110
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11 of 26
RFFC5071/5072
RFFC5071 Pin Out
26
GPO3/FM 25
GPO4/LD/DO
MIX2_OPP 28
MIX2_OPN 27
ENX 30
RESETX 29
SCLK 31
SDATA 32
1
24 MIX2_IPN
EXT_LO 2
23 MIX2_IPP
ENBL/GPO5
EXT_LO_DEC 3
22 ANA_VDD2
REXT
4
21 NC
ANA_VDD1
5
LFILT1
6
19 DIG_VDD
LFILT2
7
18 MIX1_OPP
LFILT3
8
17 MIX1_OPN
Exposed
paddle
20 NC
16 GPO2/ADD2
15 GPO1/ADD1
14 MIX1_IPP
13 MIX1_IPN
12 TM
11 NC
9 MODE/GPO6
10 REF_IN
RFFC5072 Pin Out
26
GPO3/FM 25
GPO4/LD/DO
MIX_OPP 28
MIX_OPN 27
ENX 30
RESETX 29
SCLK 31
SDATA 32
1
24 MIX_IPN
EXT_LO 2
23 MIX_IPP
ENBL/GPO5
EXT_LO_DEC 3
22 ANA_VDD2
REXT
4
ANA_VDD1
5
LFILT1
6
19 DIG_VDD
LFILT2
7
18 NC
LFILT3
8
17 NC
20 NC
16 GPO2/ADD2
15 GPO1/ADD1
14 NC
13 NC
12 TM
11 NC
9 MODE/GPO6
10 REF_IN
12 of 26
21 NC
Exposed
paddle
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DS140110
LFILT2
LFILT1
C9
180pF
R3
22K
C10
330pF
R6 470R
Loop Filter
R2 470R
C8
8.2pF
C34
10nF
VDDA1
ENBL
SDATA
SCLK
ENX
RESETX
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support, contact RFMD at (+1) 336-678-5570 or [email protected].
8
LFILT3
470R
R32
VC
C1
33pF
31
LFILT2
LFILT1
ANA_VDD1
REXT
EXT_LO_DEC
EXT_LO
ENBL
LFILT3
VCC
GND OUT
VCTCXO
R9
470R
1
2
U2
C36
33pF
6
7
5
4
3
2
1
C13
33pF
LFILT2
C14
33pF
LFILT1
MODE
VDDA2
C43
10nF
C17
330pF
LFILT3
C5
33pF
51K
R1
C35
33pF
C15
33pF
32
SDATA
C44
10nF
4
3
U1
GPIO4
+2.8V
R31
120R
VDDA2
C16
1nF
D1
MIX1_IF_IO2N
MIX1_IF_IO2P
DIG_VDD
NC
NC
ANA_VDD2
MIX2_IF_IO2P
GPIO2
GPIO1
1
2
3
17
18
19
20
21
22
C3
33pF
3
T3
6
4
RFFC5071 Only
4
6
C23
100pF
C29
100pF
C30
100pF
6
4
50 OHM
C26
100pF
RF_OP1
1
1
1
1
J4
RF_IP1
RF_IP2
RF_OP2
RF_IP1
50 OHM
50 OHM
50 OHM
C27
100pF
C19
10nF
C24
100pF
C20
100pF
C21
100pF
VDDD
6
4
RFXF8553
C28
100pF
1
2
RFXF9503
RF_IP1_P 3 T4
2
RF_IP1_N 1
RF_OP1_N
VDDA2
C18
10nF
VDDA2
RFXF9503
3 T2
2
1
RFXF8553
T1
100pF
RF_OP1_P
C2
33pF
23 RF_IP2_P
24 RF_IP2_N
LOCK DETECT LED
GREEN
MIX2_IF_IO2N
GPIO3
R25 220R
RF_OP2_P
RF_OP2_N
RFFC5071_RFFC5072
XTALP
10
30
ENX
XTALN
11
TM
12
MIX1_IO1N
13
MIX1_IO1P
14
GPIO1
15
MODE
9
SCLK
29
RESETX
28
MIX2_IO1N
27
MIX2_IO1P
25
GPIO3
26
GPIO4
GPIO2
16
GND
33
2
C6
2
J3
RF_OP1
J2
RF_IP2
J1
RF_OP2
2
DS140110
2
VDDA2
RFFC5071/5072
Wideband Application Schematic (<2.5GHz)
13 of 26
LFILT2
LFILT1
C9
180pF
R3
22K
C10
330pF
R6 470R
Loop Filter
R2 470R
C8
8.2pF
C34
10nF
VDDA1
ENBL
SDATA
SCLK
ENX
RESETX
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support, contact RFMD at (+1) 336-678-5570 or [email protected].
8
LFILT3
470R
R32
VC
C1
33pF
31
LFILT2
LFILT1
ANA_VDD1
REXT
EXT_LO_DEC
EXT_LO
ENBL
LFILT3
VCC
GND OUT
Y1
VCTCXO
R9
470R
1
2
C36
33pF
7
LFILT2
5
4
3
2
1
C13
33pF
6
C14
33pF
LFILT1
MODE
VDDA2
C43
10nF
C17
330pF
LFILT3
C5
33pF
51K
R1
C35
33pF
C15
33pF
32
SDATA
C44
10nF
4
3
U1
GPIO4
+2.8V
R31
120R
VDDA2
C16
1nF
D1
MIX1_IF_IO2N
MIX1_IF_IO2P
DIG_VDD
NC
NC
ANA_VDD2
17
18
19
20
21
22
3
2
1
15pF
C30
15pF
3
T3
C23
100pF
6
4
RF_OP2
1
1
1
J4
RF_IP1
IF_OP1
IF_IP2
1
J3
IF_OP1
J2
IF_IP2
J1
RF_OP2
Mixer 1 Down Conversion Circuit
RF_IP1
50 OHM
50 OHM
C26
100pF
C27
100pF
C19
10nF
C24
100pF
50 OHM
U3
JOHANSON
3700BL15B050
VDDD
6
4
RFXF8553
C28
100pF
1
2
RFFC5071 Only
RF_IP1_N
RF_IP1_P
IF_OP1_N
VDDA2
C29
C3
33pF
C18
10nF
VDDA2
50 OHM
Mixer 2 Up Conversion Circuit
U2
JOHANSON
3700BL15B200
RFXF9503
3 T2
2
1
4
5
6
IF_OP1_P
C2
33pF
23 IF_IP2_P
24 IF_IP2_N
LOCK DETECT LED
MIX2_IF_IO2P
GPIO2
GPIO1
L1
2.2nH
GREEN
MIX2_IF_IO2N
GPIO3
R25 220R
RF_OP2_P
RFFC5071_RFFC5072
XTALP
10
30
ENX
XTALN
11
TM
12
MIX1_IO1N
13
MIX1_IO1P
14
GPIO1
15
GPIO2
16
MODE
9
SCLK
29
RESETX
28
MIX2_IO1N
27
MIX2_IO1P
25
GPIO3
26
GPIO4
RF_OP2_N
3
2
1
4
5
6
GND
33
VDDA2
2
2
2
14 of 26
2
C21
15pF
RFFC5071/5072
Narrowband 3.7GHz Application Schematic
DS140110
RFFC5071/5072
Typical Performance Characteristics: Synthesizer
VDD = +3V and TA = +27°C unless stated.
Synthesizer Phase Noise
Synthesizer Phase Noise
3000MHz VCO Frequency, 26MHz Crystal Oscillator
3000MHz VCO Frequency, 52MHz Crystal Oscillator
-60.0
-60.0
3000MHz
-70.0
3000MHz
-70.0
1500MHz
-80.0
1500MHz
-80.0
-90.0
750MHz
Phase Noise (dBc/Hz)
Phase Noise (dBc/Hz)
750MHz
375MHz
187.5MHz
-100.0
93.75MHz
-110.0
-120.0
-130.0
-140.0
-150.0
-90.0
375MHz
187.5MHz
-100.0
93.75MHz
-110.0
-120.0
-130.0
-140.0
-150.0
-160.0
-160.0
1
10
100
1000
10000
100000
1
10
Offset Frequency (KHz)
1000
100000
Synthesizer Phase Noise
Synthesizer Phase Noise
4000MHz VCO Frequency, 52MHz Crystal Oscillator
-60.0
-70.0
2000MHz
Phase Noise (dBc/Hz)
500MHz
250MHz
-100.0
2000MHz
-80.0
1000MHz
-90.0
4000MHz
-70.0
4000MHz
-80.0
125MHz
-110.0
-120.0
-130.0
-140.0
1000MHz
-90.0
500MHz
250MHz
-100.0
125MHz
-110.0
-120.0
-130.0
-140.0
-150.0
-150.0
-160.0
-160.0
1
10
100
1000
10000
1
100000
10
100
1000
10000
100000
Offset Frequency (KHz)
Offset Frequency (KHz)
Synthesizer Phase Noise
Synthesizer Phase Noise
5200MHz VCO Frequency, 26MHz Crystal Oscillator
5200MHz VCO Frequency, 52MHz Crystal Oscillator
-60.0
-60.0
2600MHz
-70.0
2600MHz
-70.0
1300MHz
-80.0
1300MHz
-80.0
-90.0
650MHz
Phase Noise (dBc/Hz)
650MHz
Phase Noise (dBc/Hz)
10000
4000MHz VCO Frequency, 26MHz Crystal Oscillator
-60.0
Phase Noise (dBc/Hz)
100
Offset Frequency (KHz)
325MHz
162.5MHz
-100.0
-110.0
-120.0
-130.0
-140.0
-150.0
-90.0
325MHz
162.5MHz
-100.0
-110.0
-120.0
-130.0
-140.0
-150.0
-160.0
-160.0
1
10
100
1000
10000
Offset Frequency (KHz)
DS140110
100000
1
10
100
1000
10000
100000
Offset Frequency (KHz)
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RFFC5071/5072
Typical Performance Characteristics: Synthesizer and VCO
VDD = +3V and TA = +27°C unless stated.
VCO Phase Noise
VCO Phase Noise
With LO Divide by 1
With LO Divide by 2
-60.0
-60.0
4000MHz VCO2
3500MHz VCO2
3000MHz VCO1
-70.0
2500MHz VCO3
2000MHz VCO2
1500MHz VCO1
-70.0
-80.0
Phase Noise (dBc/Hz)
Phase Noise (dBc/Hz)
-80.0
-90.0
-100.0
-110.0
-120.0
-130.0
-140.0
-150.0
-90.0
-100.0
-110.0
-120.0
-130.0
-140.0
-150.0
-160.0
10.0
100.0
1000.0
10000.0
-160.0
10.0
100000.0
Offset Frequency (KHz)
100.0
1000.0
10000.0
100000.0
Offset Frequency (KHz)
Synthesiser RMS Integrated Phase Noise
Integration Bandwidth 1KHz to 40MHz
RMS Integrated Phase Noise (Degrees)
1.0
0.9
26MHz TCXO
0.8
52MHz TCXO
0.7
0.6
0.5
0.4
0.3
0.2
Note:
0.1
• 26MHz Crystal Oscillator: NDK ENA3523A
0.0
0
600
1200
1800
2400
3000
LO Frequency (MHz)
16 of 26
3600
4200
• 52MHz Crystal Oscillator: NDK ENA3560A
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support, contact RFMD at (+1) 336-678-5570 or [email protected].
DS140110
RFFC5071/5072
Typical Performance Characteristics: VCO
VDD = +3V and TA = +27°C unless stated.
VCO1 Frequency versus Kvco
VCO1 Frequency versus CT_CAL
LO Divide by 2
VCO1 with LO Divide by 2
25
1800
-40 Deg C
1700
20
Kvco (MHz/V)
VCO Frequency (MHz)
+27 Deg C
+85 Deg C
1600
1500
VCO1
15
10
1400
5
1300
0
1200
1200
0
20
40
60
80
100
1300
120
1400
1500
1600
1700
1800
VCO Frequency /2 (MHz)
CT_CAL Word
VCO2 Frequency versus Kvco
VCO2 Frequency versus CT_CAL
LO Divide by 2
VCO2 with LO Divide by 2
30
2300
2200
25
-40 Deg C
2100
Kvco (MHz/V)
VCO Frequency (MHz)
+27 Deg C
+85 Deg C
2000
1900
VCO2
20
15
10
1800
5
1700
0
1600
1600
0
20
40
60
80
100
1700
120
1800
1900
2000
2100
2200
2300
2800
2900
VCO Frequency /2 (MHz)
CT_CAL Word
VCO3 Frequency versus Kvco
VCO3 Frequency versus CT_CAL
LO Divide by 2
VCO3 with LO Divide by 2
30
2900
2800
+27 Deg C
Kvco (MHz/V)
VCO Frequency (MHz)
25
-40 Deg C
2700
+85 Deg C
2600
2500
2400
VCO3
20
15
10
2300
5
2200
0
2200
2100
0
20
40
60
80
CT_CAL Word
DS140110
100
120
2300
2400
2500
2600
2700
VCO Frequency /2 (MHz)
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RFFC5071/5072
Typical Performance Characteristics: VCO
VDD = +3V and TA = +27°C unless stated.
VCO1 Frequency versus Tuning Voltage
VCO2 Frequency versus Tuning Voltage
For the same coarse tune setting, LO divide by two
For the same coarse tune setting, LO divide by two
2020
1505
2015
1500
VCO2 Frequency /2 (MHz)
VCO1 Frequency /2 (MHz)
2010
1495
1490
1485
-40 Deg C
+27 Deg C
1480
+85 Deg C
2005
2000
1995
-40 Deg C
1990
+27 Deg C
+85 Deg C
1985
1475
1980
0.0
0.5
1.0
0.0
1.5
0.5
Tuning Voltage (Volts)
1.0
1.5
Tuning Voltage (Volts)
VCO3 Frequency versus Tuning Voltage
For the same coarse tune setting, LO divide by two
2515
2510
VCO3 Frequency /2 (MHz)
2505
2500
2495
2490
2485
2480
-40 Deg C
2475
+27 Deg C
2470
+85 Deg C
2465
0.0
0.5
1.0
1.5
Tuning Voltage (Volts)
18 of 26
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DS140110
RFFC5071/5072
Typical Performance Characteristics: Supply Current
VDD = +3V and TA = +27°C unless stated.Typical Performance Characteristics: RFMixer 2, RFFC5071 and RFFC5072
Total Supply Current versus Mixer Bias Setting
Total Supply Current versus Mixer Bias Setting
One Mixer Enabled, LO Frequency = 1000MHz
160.0
140.0
150.0
130.0
-40 Deg C, +2.7V
140.0
-40 Deg C, +3.0V
130.0
-40 Deg C, +3.3V
+27 Deg C, +2.7V
120.0
Current (mA)
Current (mA)
One Mixer Enabled, LO Frequency = 3500MHz
-40 Deg C, +2.7V
120.0
-40 Deg C, +3.0V
-40 Deg C, +3.3V
110.0
+27 Deg C, +2.7V
+27 Deg C, +3.0V
+27 Deg C, +3.0V
100.0
+27 Deg C, +3.3V
110.0
+27 Deg C, +3.3V
+85 Deg C, +2.7V
+85 Deg C, +2.7V
90.0
+85 Deg C, +3.0V
100.0
+85 Deg C, +3.0V
+85 Deg C, +3.3V
+85 Deg C, +3.3V
80.0
90.0
1
2
3
4
5
6
1
7
Mixer Bias Current Setting (MIX_IDD)
2
3
4
5
6
7
Mixer Bias Current Setting (MIX_IDD)
Total Supply Current versus LO Frequency
RFFC5071 Typical Operating Current in mA
One Mixer Enabled, +3.0V Supply Voltage
in Full Duplex Mode (both mixers enabled) with +3V supply.
160.0
MIX2_IDD
150.0
Supply Current (mA)
MIX1_IDD
1
2
3
4
5
6
7
130.0
1
121
126
131
136
142
146
151
120.0
2
126
131
136
141
147
151
156
110.0
MIX_IDD = 1
3
131
136
141
147
152
156
161
MIX_IDD = 2
4
136
141
147
152
157
162
167
172
140.0
100.0
MIX_IDD = 3
90.0
80.0
MIX_IDD = 4
5
141
146
152
157
162
167
MIX_IDD = 5
6
146
151
156
161
167
171
176
7
151
156
161
166
171
176
181
MIX_IDD = 6
70.0
MIX_IDD = 7
60.0
100
600
1100 1600 2100 2600 3100 3600 4100
LO Frequency (MHz)
DS140110
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support, contact RFMD at (+1) 336-678-5570 or [email protected].
19 of 26
RFFC5071/5072
Typical Performance Characteristics: RF Mixer 1, RFFC5071 only
VDD = +3V and TA = +27°C unless stated. As measured on RFFC5071 wideband evaluation board.
See application schematic on page 13.
Conversion Gain of Mixer 1
IF Output = 100MHz
-40 Deg C, +2.7V
Mixer 1 Noise Figure versus Bias Current
-40 Deg C, +3.0V
LO Frequency = 1000MHz, IF Output = 100MHz
-40 Deg C, +3.3V
0.0
16.0
+27 Deg C, +2.7V
-1.0
+27 Deg C, +3.3V
+85 Deg C, +2.7V
-3.0
+85 Deg C, +3.0V
-4.0
+85 Deg C, +3.3V
-5.0
-6.0
12.0
Noise Figure (dB)
Conversion Gain (dB)
14.0
+27 Deg C, +3.0V
-2.0
10.0
-40 Deg C, +2.7V
-40 Deg C, +3.0V
8.0
-40 Deg C, +3.3V
+27 Deg C, +2.7V
6.0
+27 Deg C, +3.0V
-7.0
+27 Deg C, +3.3V
4.0
-8.0
+85 Deg C, +2.7V
+85 Deg C, +3.0V
2.0
-9.0
+85 Deg C, +3.3V
0.0
-10.0
400
600
800
1000
1200
1400
1600
1800
1
2000
RF Input Frequency (MHz)
2
3
4
5
6
7
Mixer Bias Current Setting (MIX1_IDD)
Mixer 1 Input IP3 versus Bias Current
Mixer 1 Noise Figure versus Frequency
LO Frequency = 1000MHz, IF Output = 100MHz
IF Output = 100MHz
16.0
30.0
14.0
25.0
Input IP3 (dBm)
Noise Figure (dB)
12.0
10.0
MIX_IDD = 1
8.0
MIX_IDD = 2
MIX_IDD = 3
6.0
MIX_IDD = 4
20.0
-40 Deg C, +2.7V
-40 Deg C, +3.0V
15.0
-40 Deg C, +3.3V
+27 Deg C, +2.7V
10.0
+27 Deg C, +3.0V
MIX_IDD = 5
4.0
+27 Deg C, +3.3V
MIX_IDD = 6
+85 Deg C, +2.7V
5.0
MIX_IDD = 7
2.0
+85 Deg C, +3.0V
+85 Deg C, +3.3V
0.0
500
0.0
750
1000
1250
1500
1750
2000
1
LO Frequency (MHz)
2
3
4
5
6
7
Mixer Bias Current Setting (MIX1_IDD)
Mixer 1 Linearity Performance
Mixer 1 Input Power for 1dB Compression
MIX_IDD = 5, +3.0V, IF Output = 100MHz
LO Frequency = 1000MHz, IF Output = 100MHz
30.0
30.0
25.0
25.0
20.0
20.0
15.0
15.0
14.0
12.0
10.0
10.0
Pin 1dB (dBm)
Pin 1dB (dBm)
IIP3 (dBm)
10.0
8.0
-40 Deg C, +2.7V
-40 Deg C, +3.0V
6.0
-40 Deg C, +3.3V
+27 Deg C, +2.7V
4.0
+27 Deg C, +3.0V
+27 Deg C, +3.3V
2.0
5.0
5.0
Input IP3
Pin 1dB
750
1000
1250
1500
1750
2000
RF Input Frequency (MHz)
20 of 26
+85 Deg C, +3.0V
+85 Deg C, +3.3V
0.0
500
+85 Deg C, +2.7V
0.0
0.0
2250
-2.0
1
2
3
4
5
6
7
Mixer Bias Current Setting (MIX1_IDD)
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
DS140110
RFFC5071/5072
Typical Performance Characteristics: RF Mixer 2, RFFC5071 and RFFC5072
VDD = +3V and TA = +27°C unless stated. As measured on RFFC5071/5072 wideband evaluation board.
See application schematic on page 13.
Conversion Gain of Mixer 2
IF Output = 100MHz
Mixer 2 Noise Figure versus Bias Current
-40 Deg C, +3.0V
LO Frequency = 1000MHz, IF Output = 100MHz
-40 Deg C, +3.3V
0.0
16.0
+27 Deg C, +2.7V
-1.0
14.0
+27 Deg C, +3.0V
+27 Deg C, +3.3V
+85 Deg C, +2.7V
-3.0
+85 Deg C, +3.0V
+85 Deg C, +3.3V
-4.0
-5.0
-6.0
12.0
Noise Figure (dB)
-2.0
Conversion Gain (dB)
-40 Deg C, +2.7V
-7.0
10.0
-40 Deg C, +2.7V
-40 Deg C, +3.0V
8.0
-40 Deg C, +3.3V
+27 Deg C, +2.7V
6.0
+27 Deg C, +3.0V
4.0
+27 Deg C, +3.3V
2.0
+85 Deg C, +3.0V
+85 Deg C, +2.7V
-8.0
-9.0
+85 Deg C, +3.3V
0.0
-10.0
400
600
800
1000
1200
1400
1600
1800
1
2000
2
3
4
5
6
7
Mixer Bias Current Setting (MIX2_IDD)
RF Input Frequency (MHz)
Mixer 2 Noise Figure versus Frequency
Mixer 2 Input IP3 versus Bias Current
IF Output = 100MHz
LO Frequency = 1000MHz, IF Output = 100MHz
16.0
30.0
14.0
25.0
Input IP3 (dBm)
Noise Figure (dB)
12.0
10.0
MIX_IDD = 1
8.0
MIX_IDD = 2
MIX_IDD = 3
6.0
MIX_IDD = 4
20.0
-40 Deg C, +2.7V
-40 Deg C, +3.0V
15.0
-40 Deg C, +3.3V
+27 Deg C, +2.7V
+27 Deg C, +3.0V
10.0
MIX_IDD = 5
4.0
+27 Deg C, +3.3V
MIX_IDD = 6
2.0
+85 Deg C, +2.7V
5.0
MIX_IDD = 7
+85 Deg C, +3.0V
+85 Deg C, +3.3V
0.0
0.0
500
750
1000
1250
1500
1750
2000
1
LO Frequency (MHz)
2
3
4
5
6
7
Mixer Bias Current Setting (MIX2_IDD)
Mixer 2 Input Power for 1dB Compression
Mixer 2 Linearity Performance
LO Frequency = 1000MHz, IF Output = 100MHz
MIX_IDD = 5, +3.0V, IF Output = 100MHz
30.0
14.0
30.0
12.0
25.0
25.0
20.0
20.0
15.0
10.0
10.0
Pin 1dB (dBm)
15.0
Pin 1dB (dBm)
IIP3 (dBm)
10.0
8.0
-40 Deg C, +2.7V
-40 Deg C, +3.0V
6.0
-40 Deg C, +3.3V
+27 Deg C, +2.7V
4.0
+27 Deg C, +3.0V
+27 Deg C, +3.3V
2.0
+85 Deg C, +2.7V
5.0
Input IP3
5.0
+85 Deg C, +3.0V
0.0
+85 Deg C, +3.3V
Pin 1dB
0.0
500
750
1000
1250
1500
1750
2000
RF Input Frequency (MHz)
DS140110
0.0
2250
-2.0
1
2
3
4
5
6
7
Mixer Bias Current Setting (MIX2_IDD)
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
21 of 26
RFFC5071/5072
Typical Performance Characteristics: RF Mixers, RFFC5071 and RFFC5072
VDD = +3V and TA = +27°C unless stated. As measured on RFFC5071 wideband evaluation board.
See application schematic on page 13. Note: Mixer 1 plots only apply to RFFC5071.
LO & RF Leakage at Mixer 1 Output
-10.0
IF Output at 100MHz
LO Leakage (High Side)
RF Leakage
-20.0
RF Input Power 0dBm, MIX2_IDD = 4
0.0
Level at Mixer 2 Output (dBm)
Level at Mixer 1 Output (dBm)
LO & RF Leakage at Mixer 2 Output
RF Input Power 0dBm, MIX1_IDD = 4
0.0
-30.0
-40.0
-50.0
-10.0
IF Output at 100MHz
LO Leakage (High Side)
RF Leakage
-20.0
-30.0
-40.0
-50.0
-60.0
400.0
600.0
800.0
1000.0
1200.0
1400.0
-60.0
400.0
1600.0
600.0
RF Input Frequency (MHz)
1000.0
1200.0
1400.0
1600.0
RF Input Frequency (MHz)
Typical LO Leakage at Mixer Output
Mixer to Mixer Isolation in Full Duplex Mode
+3.0V Supply Voltage
LO = RF input + 100MHz
0.0
100.0
Path 1, -40 Deg C
Path 1, +27 Deg C
-10.0
Path 1, +85 Deg C
90.0
Path 2, +27 Deg C
Path 2, +85 Deg C
-30.0
-40.0
Isolation (dB)
Path 2, -40 Deg C
-20.0
LO Leakage (dBm)
800.0
80.0
70.0
-50.0
60.0
-60.0
50.0
MIX_IDD = 4
-70.0
200
400
600
800
1000 1200 1400 1600 1800 2000
LO Frequency (MHz)
22 of 26
40.0
0
500
1000
1500
2000
2500
RF Input Frequency (MHz)
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
DS140110
RFFC5071/5072
Typical Performance Characteristics: RF Mixers at 3.7GHz
VDD = +3V and TA = +27°C unless stated. As measured on 3.7GHz narrowband evaluation board, down conversion.
See application schematic on page 14
Conversion Gain of Mixer 1
0.0
RF Frequency = 4000MHz, IF Output = 200MHz
30.0
-40 Deg C, +3.3V
-1.0
+27 Deg C, +2.7V
-2.0
+27 Deg C, +3.0V
+27 Deg C, +3.3V
-3.0
+85 Deg C, +2.7V
-4.0
+85 Deg C, +3.0V
+85 Deg C, +3.3V
-5.0
-6.0
25.0
Input IP3 (dBm)
Conversion Gain (dB)
Mixer 1 Input IP3 versus Bias Current
-40 Deg C, +2.7V
-40 Deg C, +3.0V
Down Conversion with IF Output = 200MHz
20.0
-40 Deg C, +2.7V
-40 Deg C, +3.0V
15.0
-40 Deg C, +3.3V
+27 Deg C, +2.7V
+27 Deg C, +3.0V
10.0
-7.0
-8.0
+27 Deg C, +3.3V
+85 Deg C, +2.7V
5.0
+85 Deg C, +3.0V
-9.0
+85 Deg C, +3.3V
-10.0
3400 3500 3600
0.0
3700 3800 3900 4000
4100
1
4200
2
RF Input Frequency (MHz)
3
4
5
6
7
Mixer Bias Current Setting (MIX1_IDD)
Typical LO Leakage at Mixer 1 Output
Mixer 1 Noise Figure versus Frequency
+3.0V Supply Voltage
IF Output = 200MHz
0.0
18.0
16.0
-40 Deg C
+27 Deg C
+85 Deg C
-10.0
LO Leakage (dBm)
Noise Figure (dB)
14.0
12.0
10.0
MIX_IDD = 1
8.0
6.0
MIX_IDD = 2
MIX_IDD = 3
4.0
MIX_IDD = 4
MIX_IDD = 5
2.0
-20.0
-30.0
-40.0
-50.0
MIX_IDD = 6
MIX_IDD = 7
-60.0
3200
0.0
3400 3500 3600 3700 3800 3900 4000 4100 4200
RF Input Frequency (MHz)
Mixer 1 Linearity Performance
20.0
20.0
15.0
15.0
10.0
5.0
0.0
0.0
3400 3500 3600 3700 3800 3900 4000 4100 4200
DS140110
Level at Mixer 1 Output (dBm)
25.0
RF Input Frequency (MHz)
4200
4400
-10.0
Pin 1dB (dBm)
IIP3 (dBm)
25.0
Pin 1dB
4000
RF Input Power -10dBm, MIX1_IDD = 4
30.0
5.0
3800
LO & RF Leakage at Mixer 1 Output
30.0
Input IP3
3600
LO Frequency (MHz)
MIX_IDD = 5, +3.0V, IF Output = 200MHz
10.0
3400
-20.0
-30.0
-40.0
IF Output at 200MHz
-50.0
LO Leakage (Low Side)
RF Leakage
-60.0
-70.0
-80.0
3400 3500 3600 3700 3800 3900 4000 4100 4200
RF Input Frequency (MHz)
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
23 of 26
RFFC5071/5072
Typical Performance Characteristics: RF Mixers at 3.7GHz
VDD = +3V and TA = +27°C unless stated. As measured on 3.7GHz narrowband evaluation board, up conversion.
See application schematic on page 14
Resonant match on mixer output, shunt inductor L1 is 2.7nH unless stated.
Conversion Gain of Mixer 2
Mixer 2 Input IP3 versus Bias Current
Up Conversion with IF Input = 500MHz
IF Input = 500MHz, RF output = 3900MHz
0.0
25.0
-40 Deg C, +2.7V
-40 Deg C, +3.0V
Conversion Gain (dB)
-2.0
-40 Deg C, +3.3V
+27 Deg C, +2.7V
-3.0
+27 Deg C, +3.0V
+27 Deg C, +3.3V
+85 Deg C, +2.7V
-4.0
-5.0
+85 Deg C, +3.0V
+85 Deg C, +3.3V
-6.0
20.0
Input IP3 (dBm)
-1.0
15.0
-40 Deg C, +2.7V
-40 Deg C, +3.0V
-40 Deg C, +3.3V
+27 Deg C, +2.7V
+27 Deg C, +3.0V
+27 Deg C, +3.3V
+85 Deg C, +2.7V
+85 Deg C, +3.0V
+85 Deg C, +3.3V
10.0
-7.0
-8.0
5.0
-9.0
-10.0
3400
0.0
3600
3800
4000
4200
1
RF Output Frequency (MHz)
2
3
4
5
6
7
Mixer Bias Current Setting (MIX2_IDD)
Conversion Gain of Mixer 2 versus Shunt Inductor
Mixer 2 Noise Figure versus Frequency
Up Conversion with IF Input = 500MHz
Up Conversion with IF Input = 500MHz
0.0
20.0
18.0
-5.0
Conversion Gain (dB)
Noise Figure (dB)
16.0
14.0
12.0
10.0
MIX_IDD = 1
MIX_IDD = 2
MIX_IDD = 3
MIX_IDD = 4
MIX_IDD = 5
MIX_IDD = 6
MIX_IDD = 7
8.0
6.0
4.0
2.0
0.0
3400
3600
3800
4000
-10.0
-15.0
3.3nH
2.7nH
-20.0
2.2nH
-25.0
2500 2750 3000 3250 3500 3750 4000 4250 4500 4750
4200
RF Output Frequency (MHz)
RF Output Frequency (MHz)
IF and LO Leakage at Mixer 2 Output
Mixer 2 Noise Figure versus Bias Current
RF Input Power - 10dBm, MIX_IDD = 4
IF Input = 500MHz, RF Output = 3900MHz
20.0
-10.0
18.0
-20.0
Level at Mixer 2 Output (dBm)
Input IP3 (dBm)
16.0
14.0
12.0
-40 Deg C, +2.7V
-40 Deg C, +3.0V
-40 Deg C, +3.3V
+27 Deg C, +2.7V
+27 Deg C, +3.0V
+27 Deg C, +3.3V
+85 Deg C, +2.7V
+85 Deg C, +3.0V
+85 Deg C, +3.3V
10.0
8.0
6.0
4.0
2.0
0.0
1
2
3
4
5
6
Mixer Bias Current Setting (MIX2_IDD)
24 of 26
7
-30.0
-40.0
-50.0
RF Output
LO Leakage (Low Side)
-60.0
IF Leakage at 500MHz
-70.0
-80.0
2800 3000 3200 3400 3600 3800 4000 4200 4400 4600
RF Output Frequency (MHz)
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
DS140110
RFFC5071/5072
Package Drawing
QFN, 32-pin, 5mm x 5mm
DS140110
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
25 of 26
RFFC5071/5072
Ordering Information
26 of 26
RFFC5071
Part Number
Description
Devices/Container
RFFC5071SB
RFFC5071SQ
RFFC5071SR
RFFC5071TR7
RFFC5071TR13
DKFC5071
32-pin QFN
32-pin QFN
32-pin QFN
32-pin QFN
32-pin QFN
Complete Design Kit
5-Piece sample bag
25-Piece sample bag
100-Piece reel
750-Piece reel
2500-Piece reel
1 Box
Part Number
Description
Devices/Container
RFFC5072SB
RFFC5072SQ
RFFC5072SR
RFFC5072TR7
RFFC5072TR13
DKFC5072
32-pin QFN
32-pin QFN
32-pin QFN
32-pin QFN
32-pin QFN
Complete Design Kit
5-Piece sample bag
25-Piece sample bag
100-Piece reel
750-Piece reel
2500-Piece reel
1 Box
RFFC5072
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
DS140110