19-0517; Rev 0; 6/06 KIT ATION EVALU E L B AVAILA 12-Bit, 2.3Gsps, Multi-Nyquist DAC with Selectable Frequency Response Applications Radar Waveform and LO Signal Synthesis Digital IF Generation in X-Band Transmitters Arbitrary Waveform Generators Direct Digital Synthesis Automatic Test Equipment Direct Digital Generation of Wideband RF Signals Up to 2GHz ♦ Industry-Leading Dynamic Performance SFDR = 68dBc at fOUT = 1200MHz Noise Density = -162dBm/Hz at 200MHz ♦ 1GHz Signal Bandwidth ♦ Frequency Response Modes: NRZ, RZ, RF ♦ High SNR and Exceptional Gain Flatness in Nyquist Zones 1, 2, 3 ♦ 4:1 Multiplexed LVDS Inputs (Up to 575MHz Each) ♦ Internal 50Ω Differential Output Termination ♦ Low Power: 760mW (fCLK = 1000MHz) ♦ Compact 11mm x 11mm, 169 CSBGA Package ♦ Evaluation Kit Available (Order MAX19692EVKIT) Ordering Information PART TEMP RANGE MAX19692EXW-D -40°C to +85°C PACKAGE PKG CODE 169 CSBGA X16911-1 Functional Diagram RZ RF DAP[11:0] DAN[11:0] 12 x 2 DBP[11:0] DBN[11:0] 12 x 2 DCP[11:0] DCN[11:0] 12 x 2 DDP[11:0] DDN[11:0] 12 x 2 DATACLKP DATACLKN FREQUENCY RESPONSE SELECT 2 /8 /16 CLOCK DIVIDER AVDD3.3 AVCLK VDD1.8 4:1 REGISTERED MUX GND 12 DAC /4 OUTP OUTN CAL REFRES REFIO CLKDIV MAX19692 DELAY CLKP BANDGAP REFERENCE CLK FSADJ DACREF CLKN SELECTABLE FREQUENCY RESPONSE 0 OUTPUT AMPLITUDE RESPONSE (dB) The MAX19692 12-bit, 2.3Gsps digital-to-analog converter (DAC) enables direct digital synthesis of high-frequency and wideband signals in baseband and higher Nyquist zones. It has been optimized for wideband communications and radar applications. It has excellent spurious and noise performance and can be used for synthesis of wideband signals in the frequency range from DC to more than 2GHz. The 2.3Gsps update rate allows digital generation of signals with more than 1GHz bandwidth. The selectable frequency response enables signal output with high SNR and excellent gain flatness in the first three Nyquist zones, reducing the number of upconversion stages needed in a radio transmitter. With its unique ability to generate broadband signals over a wide frequency range, the MAX19692 enables ultra-high data rate wireless modems and multistandard software radio transmitters. The MAX19692 features an update rate up to 2.3Gsps, and has four 12-bit multiplexed low-voltage differential signaling (LVDS) input ports that each operate up to 575MHz. The device accepts a clock at the DAC update rate that can be either a sine wave or a square wave. The input data rate is 1/4 the DAC update rate. The MAX19692 provides an LVDS data clock output to simplify interfacing to FPGA or ASIC devices. The MAX19692 has three frequency response output modes: • Non-Return-to-Zero (NRZ) mode is the most common in the industry and provides highest dynamic range and output power in the 1st Nyquist zone. • Return-to-Zero (RZ) mode trades off SNR for improved gain flatness in the 1st, 2nd, and 3rd Nyquist zones. • Radio Frequency (RF) mode provides higher SNR and excellent dynamic performance in the 2nd and 3rd Nyquist zones. The MAX19692 is a current-steering DAC with an integrated, self-calibrated 50Ω differential output termination to ensure optimum dynamic performance. The MAX19692 operates from 3.3V and 1.8V power supplies and consumes 760mW at 1.0Gsps. Features -5 NRZ RZ RF -10 -15 -20 -25 -30 -35 -40 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Pin Configuration appears at end of data sheet. fOUT NORMALIZED TO DAC UPDATE RATE (fCLK) ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX19692 General Description MAX19692 12-Bit, 2.3Gsps, Multi-Nyquist DAC with Selectable Frequency Response ABSOLUTE MAXIMUM RATINGS AVDD3.3 to GND, DACREF ......................................-0.3V to +3.9V VDD1.8, AVCLK to GND, DACREF ..........................-0.3V to +2.1V REFIO, FSADJ to GND, DACREF ........-0.3V to (AVDD3.3 + 0.3V) OUTP, OUTN to GND, DACREF ..........-0.3V to (AVDD3.3 + 1.0V) CREF to GND, DACREF............................-0.3V to (VDD1.8 + 0.3V) DELAY, CLKDIV, RZ, RF, REFRES, CAL to GND, DACREF ......................-0.3V to (AVDD3.3 + 0.3V) CLKP, CLKN to GND, DACREF..............-0.3V to (AVCLK + 0.3V) DAP0–DAP11, DBP0–DBP11, DCP0–DCP11 to GND, DACREF........-0.3V to (VDD1.8 + 0.3V) DDP0–DDP11 to GND, DACREF............-0.3V to (VDD1.8 + 0.3V) DAN0–DAN11, DBN0–DBN11, DCN0–DCN11 to GND, DACREF.......-0.3V to (VDD1.8 + 0.3V) DDN0–DDN11 to GND, DACREF...........-0.3V to (VDD1.8 + 0.3V) DATACLKP, DATACLKN to GND, DACREF .....................................................-0.3V to (VDD1.8 + 0.3V) DATACLKP, DATACLKN Continuous Current ......................8mA Continuous Power Dissipation (TA = +70°C) 169-Pin CSBGA (derate 33.3mW/°C above +70°C)..........................................................2666.7mW Thermal Resistance θJA (Note 1)...................................+18°C/W Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-60°C to +150°C Note 1: Thermal resistance based on a 4.5in x 5.5in multilayer board. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVDD3.3 = 3.3V, VDD1.8 = AVCLK = 1.8V, RREFRES = 500Ω, RSET = 2kΩ, VREFIO = external 1.25V, CAL on, NRZ mode, transformercoupled differential output, IOUT = 20mA, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution 12 Bits Integral Nonlinearity INL Measured differentially ±1.3 LSB Differential Nonlinearity DNL Measured differentially ±0.9 LSB Offset Voltage Error OS Measured differentially, no external load resistors -0.5 Offset Drift Full-Scale Output Current Output-Current Gain Error ±0.1 +0.5 ±10 IOUT (Note 3) GE Output-Voltage Gain Drift 20 mA -4 +4 %FS Internal reference -0.003 -0.0025 POUT Differential, into 50Ω load Output Resistance ROUT Differential, CAL ≥ 0.7 x AVDD3.3 (Note 4) ppm/°C 8 External reference Maximum Output Power %FS dB/°C -2.6 44 48 dBm 52 Ω 10 MHz DYNAMIC PERFORMANCE (Note 5) Minimum Output Update Rate fCLK Maximum Output Update Rate fCLK Wideband NoiseSpectral Density 2 1.8V ≤ VDD1.8 ≤ 1.9V fCLK = 1000MHz, fOUT = 200MHz, -12dBFS 2300 MHz -162 _______________________________________________________________________________________ dBm/Hz 12-Bit, 2.3Gsps, Multi-Nyquist DAC with Selectable Frequency Response (AVDD3.3 = 3.3V, VDD1.8 = AVCLK = 1.8V, RREFRES = 500Ω, RSET = 2kΩ, VREFIO = external 1.25V, CAL on, NRZ mode, transformercoupled differential output, IOUT = 20mA, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS fCLK = 500MHz Spurious-Free Dynamic Range within Nyquist Zone of fOUT SFDR fCLK = 1000MHz fCLK = 2000MHz, NRZ mode fCLK = 2300MHz, NRZ mode fCLK = 1000MHz, NRZ mode 2-Tone IMD TTIMD fCLK = 1000MHz, RF mode Minimum Output Bandwidth BW-3dB MIN TYP fOUT = 50MHz, -6dBFS, NRZ mode 73 fOUT = 100MHz, -6dBFS, NRZ mode 74 fOUT = 200MHz, -6dBFS, NRZ mode 70 fOUT = 400MHz, -6dBFS, RF mode 71 fOUT = 600MHz, -6dBFS, RF mode 73 fOUT = 200MHz, -6dBFS, NRZ mode 75 fOUT = 409MHz, -0.1dBFS, NRZ mode, TA ≥ +25°C 60 68 fOUT = 409MHz, -0.1dBFS, NRZ mode 56 68 fOUT = 800MHz, -6dBFS, RF mode 67 fOUT = 1200MHz, -6dBFS, RF mode 65 fOUT = 100MHz, -6dBFS 71 fOUT = 200MHz, -6dBFS 68 fOUT = 400MHz, -6dBFS 70 fOUT = 800MHz, -6dBFS 58 fOUT = 92MHz, 0dBFS 60 fOUT1 = 200MHz, -7dBFS MAX UNITS dBc 71 -72 fOUT2 = 201MHz, -7dBFS dBc fOUT1 = 1300MHz, -7dBFS -66 fOUT2 = 1301MHz, -7dBFS (Note 6) 1500 MHz REFERENCE Internal Reference Voltage Range VREFIO 1.1 Reference Input Compliance Range VREFIOCR 0.50 1.2 1.3 V 1.25 V Reference Input Resistance RREFIO 10 kΩ Reference Voltage Drift TCOREF 50 ppm/°C ANALOG OUTPUT TIMING (Note 7) Output Fall Time tFALL 90% to 10% 270 ps Output Rise Time tRISE 10% to 90% 270 ps Settling to 0.1% 3.5 Settling to 0.025% 4.5 (Note 8) 0.9 Settling Time Output Propagation Delay ts tPD ns ns _______________________________________________________________________________________ 3 MAX19692 ELECTRICAL CHARACTERISTICS (continued) MAX19692 12-Bit, 2.3Gsps, Multi-Nyquist DAC with Selectable Frequency Response ELECTRICAL CHARACTERISTICS (continued) (AVDD3.3 = 3.3V, VDD1.8 = AVCLK = 1.8V, RREFRES = 500Ω, RSET = 2kΩ, VREFIO = external 1.25V, CAL on, NRZ mode, transformercoupled differential output, IOUT = 20mA, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TIMING CHARACTERISTICS Data to Clock Setup Time tSETUP Referenced to rising edge of data clock (Note 9) 1.6 ns Data to Clock Hold Time tHOLD Referenced to rising edge of data clock (Note 9) -0.8 ns Data Latency (Note 10) Clock cycles 14 LVDS LOGIC INPUTS (DAP11–DAP0, DAN11–DAN0, DBP11–DBP0, DBN11–DBN0, DCP11–DCP0, DCN11–DCN0, DDP11–DDP0, DDN11–DDN0) Differential Input Logic-High VIH Differential Input Logic-Low VIL Common-Mode Voltage Range VCOM Differential Input Resistance RIN Input Capacitance CIN 100 mV -100 mV 1.125 1.375 V 85 125 Ω 1.5 pF CMOS LOGIC INPUTS (RZ, RF, CLKDIV, DELAY) Input Logic-High VIH Input Logic-Low VIL Input Leakage Current IIN Input Capacitance CIN 0.7 x AVDD3.3 V 0.3 x AVDD3.3 -15 +15 3 V µA pF CLOCK INPUTS (CLKP, CLKN) Minimum Differential Input Voltage Swing (Note 11) VCLK Maximum Differential Voltage Swing VCLK Differential Input Slew Rate SRCLK Common-Mode Voltage Range VCOMCLK Input Resistance RCLK Input Capacitance CCLK 4 fCLK ≤ 1.5GHz 0.6 fCLK = 2.3GHz, see Figure 6 for dependence on fCLK 2.0 (Note 11) 2.5 VP-P 6000 V/µs 0.55 Differential AVCLK / 3 VP-P 0.65 V 100 Ω 2 pF _______________________________________________________________________________________ 12-Bit, 2.3Gsps, Multi-Nyquist DAC with Selectable Frequency Response (AVDD3.3 = 3.3V, VDD1.8 = AVCLK = 1.8V, RREFRES = 500Ω, RSET = 2kΩ, VREFIO = external 1.25V, CAL on, NRZ mode, transformercoupled differential output, IOUT = 20mA, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ±0.25 ±0.35 ±0.45 V DATA CLOCK OUTPUTS (DATACLKP, DATACLKN) Differential Output VDCLK With 100Ω differential termination Output Rise and Fall Time tR, tF With 100Ω differential termination Common-Mode Voltage Range VCOM Output Resistance RCLK 0.5 1.125 Differential 1.25 ns 1.375 V Ω 100 POWER SUPPLIES Analog-Supply Voltage Range AVDD3.3 1.8V Supply Voltage Range VDD1.8 Clock-Supply Voltage Range AVCLK Analog Supply Current 3.1 3.3 10MHz ≤ fCLK < 2.0GHz (Note 9) 1.7 1.8 2.0GHz ≤ fCLK ≤ 2.3GHz 1.8 10MHz ≤ fCLK < 2.0GHz (Note 9) 1.7 2.0GHz ≤ fCLK ≤ 2.3GHz 1.8 3.5 1.9 1.9 1.8 1.9 1.9 117 V V IAVDD3.3 fCLK = 1000MHz, fOUT = 10MHz, AOUT = 0dBFS Digital Supply Current IVDD1.8 fCLK = 1000MHz, fOUT = 10MHz, AOUT = 0dBFS 61 76 mA Clock Supply Current IAVCLK fCLK = 1000MHz, fOUT = 10MHz, AOUT = 0dBFS 164 191 mA Total Power Dissipation PDISS fCLK = 1000MHz, fOUT = 10MHz, AOUT = 0dBFS 760 870 mW Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: 107 V mA All specifications are 100% tested at TA ≥ +25°C. Specifications at TA < +25°C are guaranteed by design and characterization. Nominal full-scale current IOUT = 32 x IREF. ROUT can be set to 50Ω as described in the Output Resistor Calibration section. CLK input = +10dBm, AC-coupled sine wave. Excludes impulse-response dependent rolloff inherent in the DAC. Measured single-ended into 50Ω termination resistor. Measured differentially into a 50Ω termination resistor. Excludes data latency. Guaranteed by design and characterization. DA_P/DA_N to DAC output. Differential voltage swing defined as VP + VN. VCLKN VP VN VCLKP _______________________________________________________________________________________ 5 MAX19692 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (AVDD3.3 = 3.3V, AVDD1.8 = DVDD = AVCLK = 1.8V, RREFRES = 500Ω, RSET = 2kΩ, VREFIO = external 1.25V, CAL on, transformercoupled differential output, IOUT = 20mA, TA = +25°C, unless otherwise noted.) -6dBFS 50 70 50 0 50 100 150 fOUT (MHz) 200 0 250 SFDR vs. OUTPUT FREQUENCY fCLK = 2300MHz, NRZ MODE 70 -6dBFS 100 400 80 70 0dBFS 0 500 -3dBFS 40 -3dBFS 230 460 690 fOUT (MHz) 920 50 70 50 100 150 fOUT (MHz) 200 0dBFS -3dBFS -6dBFS 50 0 250 SFDR vs. OUTPUT FREQUENCY fCLK = 2300MHz, RZ MODE 80 70 100 200 300 fOUT (MHz) 400 500 SFDR vs. OUTPUT FREQUENCY fCLK = 500MHz, RZ MODE 80 MAX19692 toc08 -3dBFS 60 30 0 MAX19692 toc07 0dBFS 750 40 SFDR vs. OUTPUT FREQUENCY fCLK = 1500MHz, RZ MODE 80 625 -6dBFS 60 1150 375 500 fOUT (MHz) 70 30 0 250 80 40 30 125 SFDR vs. OUTPUT FREQUENCY fCLK = 1000MHz, RZ MODE SFDR (dBc) SFDR (dBc) 60 50 200 300 fOUT (MHz) MAX19692 toc05 0dBFS -3dBFS 50 SFDR vs. OUTPUT FREQUENCY fCLK = 500MHz, RZ MODE MAX19692 toc04 80 0dBFS 30 30 30 60 40 40 40 SFDR (dBc) -6dBFS 60 -6dBFS MAX19692 toc06 0dBFS SFDR (dBc) SFDR (dBc) 0dBFS 60 MAX19692 toc03 70 80 -3dBFS 70 MAX19692 toc09 70 -3dBFS SFDR (dBc) -3dBFS MAX19692 toc02 80 MAX19692 toc01 80 SFDR vs. OUTPUT FREQUENCY fCLK = 1500MHz, NRZ MODE SFDR vs. OUTPUT FREQUENCY fCLK = 1000MHz, NRZ MODE SFDR vs. OUTPUT FREQUENCY fCLK = 500MHz, NRZ MODE -3dBFS -6dBFS -6dBFS 50 40 60 SFDR (dBc) 60 SFDR (dBc) SFDR (dBc) MAX19692 12-Bit, 2.3Gsps, Multi-Nyquist DAC with Selectable Frequency Response 50 40 0dBFS 60 -6dBFS 50 40 0dBFS 30 0 6 125 250 375 500 fOUT (MHz) 625 750 30 30 0 230 460 690 fOUT (MHz) 920 1150 250 300 350 400 fOUT (MHz) _______________________________________________________________________________________ 450 500 12-Bit, 2.3Gsps, Multi-Nyquist DAC with Selectable Frequency Response 70 -6dBFS 40 60 0dBFS 50 900 1000 750 70 1375 -3dBFS 70 SFDR (dBc) 60 0dBFS 1125 1250 fOUT (MHz) 80 MAX19692 toc13 -3dBFS 1000 250 1500 -6dBFS 50 60 -6dBFS 0dBFS 50 300 350 400 fOUT (MHz) 450 500 SFDR vs. OUTPUT FREQUENCY fCLK = 2000MHz, RF MODE SFDR vs. OUTPUT FREQUENCY fCLK = 1500MHz, RF MODE SFDR vs. OUTPUT FREQUENCY fCLK = 1000MHz, RF MODE 80 875 80 70 SFDR (dBc) 700 800 fOUT (MHz) MAX19692 toc14 600 50 30 30 500 0dBFS 40 40 30 SFDR (dBc) -6dBFS -3dBFS 60 -3dBFS MAX19692 toc15 0dBFS -6dBFS 70 SFDR (dBc) 60 -3dBFS SFDR (dBc) SFDR (dBc) 70 80 MAX19692 toc11 -3dBFS 50 80 MAX19692 toc10 80 SFDR vs. OUTPUT FREQUENCY fCLK = 500MHz, RF MODE SFDR vs. OUTPUT FREQUENCY fCLK = 1500MHz, RZ MODE MAX19692 toc12 SFDR vs. OUTPUT FREQUENCY fCLK = 1000MHz, RZ MODE -6dBFS 60 50 0dBFS 40 40 30 30 30 700 800 fOUT (MHz) 900 750 1000 -6dBFS 60 1375 -6dBFS 0dBFS 50 -3dBFS 70 SFDR (dBc) SFDR (dBc) 70 1125 1250 fOUT (MHz) 80 MAX19692 toc16 -3dBFS 1000 60 0dBFS 50 550 600 650 fOUT (MHz) 700 750 1400 1600 fOUT (MHz) 1800 2000 80 -3dBFS 70 0dBFS 60 -6dBFS 50 40 30 30 30 1200 SFDR vs. OUTPUT FREQUENCY fCLK = 500MHz, RF MODE 40 40 500 1000 1500 SFDR vs. OUTPUT FREQUENCY fCLK = 1000MHz, RZ MODE SFDR vs. OUTPUT FREQUENCY fCLK = 500MHz, RZ MODE 80 875 SFDR (dBc) 600 MAX19692 toc17 500 MAX19692 toc18 40 1000 1100 1200 1300 fOUT (MHz) 1400 1500 500 550 600 650 fOUT (MHz) 700 _______________________________________________________________________________________ 750 7 MAX19692 Typical Operating Characteristics (continued) (AVDD3.3 = 3.3V, AVDD1.8 = DVDD = AVCLK = 1.8V, RREFRES = 500Ω, RSET = 2kΩ, VREFIO = external 1.25V, CAL on, transformer- Typical Operating Characteristics (continued) (AVDD3.3 = 3.3V, AVDD1.8 = DVDD = AVCLK = 1.8V, RREFRES = 500Ω, RSET = 2kΩ, VREFIO = external 1.25V, CAL on, transformercoupled differential output, IOUT = 20mA, TA = +25°C, unless otherwise noted.) -6dBFS 70 NRZ MODE 70 80 MAX19692 toc20 80 MAX19692 toc19 80 -3dBFS SFDR vs. OUTPUT AMPLITUDE fCLK = 1000MHz, fOUT = 800MHz SFDR vs. OUTPUT AMPLITUDE fCLK = 1000MHz, fOUT = 200MHz 60 50 SFDR (dBc) SFDR (dBc) SFDR (dBc) RZ MODE 50 RF MODE 70 60 60 MAX19692 toc21 SFDR vs. OUTPUT FREQUENCY fCLK = 1000MHz, RF MODE 40 30 50 RZ MODE 40 30 0dBFS 30 20 10 10 0 0 1200 1300 fOUT (MHz) 1400 1500 -18 -16 -14 -12 -10 -8 -6 AOUT (dBFS) SFDR vs. OUTPUT AMPLITUDE fCLK = 1000MHz, fOUT = 1200MHz -30 MAX19296 toc22 RF MODE -40 60 50 -2 -18 -16 -14 -12 -10 -8 -6 AOUT (dBFS) 0 IMD (dBc) RZ MODE 40 30 -50 -60 -4 -2 0 TWO-TONE IMD vs. OUTPUT FREQUENCY fCLK = 1000MHz, 1MHz SPACING, NRZ MODE TWO-TONE IMD vs. OUTPUT FREQUENCY fCLK = 500MHz, 1MHz SPACING, NRZ MODE 80 70 -4 -30 -40 IMD (dBc) 1100 MAX19692 toc23 1000 SFDR (dBc) 20 MAX19262 toc24 40 -50 ATONE = -12dBFS -60 ATONE = -12dBFS 20 ATONE = -6dBFS -70 -70 10 ATONE = -6dBFS -80 -80 -4 -2 0 0 200 -30 MAX19692 toc25 -40 100 150 fOUT (MHz) 0 250 -40 ATONE = -6dBFS -60 ATONE = -6dBFS -60 +85°C 500 600 700 800 fOUT (MHz) 900 1000 -60 -70 -80 +25°C -90 -80 -80 500 -40°C -70 -70 8 -50 400 -50 ACLK (dBm) IMD (dBc) ATONE = -12dBFS 200 300 fOUT (MHz) -40 ATONE = -12dBFS -50 100 CLK FEEDTHROUGH vs. CLK FREQUENCY fOUT = 200MHz, AOUT = -1dBFS, NRZ MODE TWO-TONE IMD vs. OUTPUT FREQUENCY fCLK = 1000MHz, 1MHz SPACING, RF MODE TWO-TONE IMD vs. OUTPUT FREQUENCY fCLK = 1000MHz, 1MHz SPACING, RF MODE -30 50 MAX19692 toc26 -18 -16 -14 -12 -10 -8 -6 AOUT (dBFS) MAX19692 toc27 0 IMD (dBc) MAX19692 12-Bit, 2.3Gsps, Multi-Nyquist DAC with Selectable Frequency Response 1000 1100 1200 1300 fOUT (MHz) 1400 1500 500 800 1100 1400 1700 fCLK (MHz) _______________________________________________________________________________________ 2000 2300 12-Bit, 2.3Gsps, Multi-Nyquist DAC with Selectable Frequency Response SFDR SPECTRAL PLOT fCLK = 1600MHz, fOUT = 700MHz, AOUT = -3dBFS, NRZ MODE -10 700MHz AT -11.5dBm -20 -10 MAX19692 toc29 -6dBFS -160 -40 POWER (dBm) POWER (dBm) 0dBFS -40 -50 HD2 AT -62dBc -60 HD3 AT -62dBc -50 -12dBFS -180 -70 -90 -90 -100 1000 1250 1500 fCLK (MHz) 1750 2000 1290MHz AT -17.5dBm -30 CENTER = 700MHz, SPAN = 100MHz, RBW = 3kHz SFDR vs. TEMPERATURE fCLK = 1000MHz, fOUT = 200MHz, NRZ MODE SFDR vs. TEMPERATURE (AVDD3.3, 1.8V SUPPLIES) fCLK = 2000MHz, fOUT = 400MHz, NRZ MODE 80 MAX19692 toc31 -10 -110 SPAN = 800MHz, CENTER = 400MHz, RBW = 20kHz 100 MAX19692 toc32 750 SFDR SPECTRAL PLOT, 3rd NYQUIST ZONE fCLK = 1000MHz, fOUT = 1290MHz, AOUT = -3dBFS, RF MODE -20 -80 -80 -100 500 70 AOUT = 0dBFS 90 -6dBFS 60 80 -3dBFS 0dBFS SFDR (dBc) SFDR (dBc) HD2 AT -66dBc CLK + CLK/4 AT -63dBc 50 3.5V, 1.9V 70 60 -80 3.1V, 1.9V 40 -90 50 3.1V, 1.7V -100 30 40 -40 SPAN = 500MHz, CENTER = 1250MHz, RBW = 30kHz -15 10 35 TEMPERATURE (°C) 60 SFDR vs. TEMPERATURE (AVDD3.3, 1.8V SUPPLIES) fCLK = 2000MHz, fOUT = 400MHz, NRZ MODE AOUT = -3dBFS 74 73 3.5V, 1.9V 3.1V, 1.9V 73 71 SFDR (dBc) 71 3.1V, 1.7V 68 3.5V, 1.7V 10 35 TEMPERATURE (°C) AOUT = -6dBFS 74 72 69 -15 75 72 70 -40 60 85 SFDR vs. TEMPERATURE (AVDD3.3, 1.8V SUPPLIES) fCLK = 2000MHz, fOUT = 400MHz, NRZ MODE MMAX19692 toc34 75 85 MAX19692 toc35 -110 SFDR (dBc) POWER (dBm) CLK -60 -70 3.5V, 1.7V 3.1V, 1.9V -40 -50 WORST CASE AT -60dBc IMD PRODUCTS IMD PRODUCTS -60 -70 -170 AOUT2 = -9dBFS -30 -30 -150 AOUT1 = -9dBFS -20 MAX19692 toc33 -140 NOISE DENSITY (dBm/Hz) 0 MAX19296 toc28 -130 TWO-TONE IMD SPECTRAL PLOT fCLK = 1600MHz, fOUT = 695MHz, fOUT2 = 705MHz MAX19692 toc30 OUTPUT NOISE DENSITY vs. CLK FREQUENCY fOUT = 200MHz, NRZ MODE 3.1V, 1.9V 70 3.5V, 1.7V 69 68 67 67 66 66 65 3.5V, 1.9V 3.1V, 1.7V 65 -40 -15 10 35 TEMPERATURE (°C) 60 85 -40 -15 10 35 TEMPERATURE (°C) 60 85 _______________________________________________________________________________________ 9 MAX19692 Typical Operating Characteristics (continued) (AVDD3.3 = 3.3V, AVDD1.8 = DVDD = AVCLK = 1.8V, RREFRES = 500Ω, RSET = 2kΩ, VREFIO = external 1.25V, CAL on, transformercoupled differential output, IOUT = 20mA, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (AVDD3.3 = 3.3V, AVDD1.8 = DVDD = AVCLK = 1.8V, RREFRES = 500Ω, RSET = 2kΩ, VREFIO = external 1.25V, CAL on, transformercoupled differential output, IOUT = 20mA, TA = +25°C, unless otherwise noted.) INTEGRAL NONLINEARITY vs. DIGITAL CODE INTERNAL REFERENCE (REFIO) VOLTAGE vs. TEMPERATURE 1.28 1.26 MAX19692 toc37 2.0 MAX19692 toc36 1.30 1.5 1.0 0.5 1.22 INL(LSB) VREFIO (V) 1.24 1.20 1.18 0 -0.5 1.16 -1.0 1.14 -1.5 1.12 -2.0 1.10 -15 10 35 TEMPERATURE (°C) 60 0 85 SUPPLY CURRENT vs. CLK FREQUENCY fOUT = 100MHz, AOUT = 0dBFS, NRZ MODE DIFFERENTIAL NONLINEARITY vs. DIGITAL CODE 575 MAX19692 toc38 1.0 0.8 0.6 525 1.8V NRZ AND RF MODES 475 0.4 CURRENT (mA) 425 0.2 0 -0.2 375 325 275 -0.4 225 -0.6 175 -0.8 125 -1.0 3.3V 1.8V RZ MODE 75 0 10 512 1024 1536 2048 2560 3072 3584 4096 DIGITAL CODE MAX19692 toc39 -40 DNL (LSB) MAX19692 12-Bit, 2.3Gsps, Multi-Nyquist DAC with Selectable Frequency Response 512 1024 1536 2048 2560 3072 3584 4096 DIGITAL CODE 500 800 1100 1400 1700 fCLK (MHz) 2000 ______________________________________________________________________________________ 2300 12-Bit, 2.3Gsps, Multi-Nyquist DAC with Selectable Frequency Response PIN NAME FUNCTION A1 REFIO Reference Input/Output. Output pin for the internal 1.2V-bandgap reference. REFIO has a 10kΩ series resistance and can be driven using an external reference. Connect a 1µF capacitor between REFIO and DACREF. A2 FSADJ Full-Scale Adjust Input. Sets the full-scale output current of the DAC. For a 20mA fullscale output current, connect a 2kΩ resistor between FSADJ and DACREF. A3 DACREF Current-Set Resistor Return Path. For a 20mA full-scale output current, connect a 2kΩ resistor between FSADJ and DACREF. DACREF is internally connected to AGND. DO NOT CONNECT TO EXTERNAL GROUND. A4, A5, A7, A9 AVDD3.3 Analog 3.3V Supply Voltage. Accepts a 3.1V to 3.5V supply voltage range. Connect 47nF bypass capacitors between each AVDD3.3 pin and AGND. A6 OUTP Positive Terminal of Differential DAC Output. OUTP has a calibrated internal 25Ω resistor to AVDD3.3. A8 OUTN Negative Terminal of Differential DAC Output. OUTN has a calibrated internal 25Ω resistor to AVDD3.3. A10, B10, C2, C3, C10, E1–E4, E10–E13, F13 VDD1.8 Analog 1.8V Supply Voltage. Accepts a 1.7V to 1.9V supply voltage range. Connect 47nF bypass capacitors between each VDD1.8 pin and GND. A11, A13, B5–B9, B11, C4–C9, C11, D1–D11, D13, E5–E9, G13, M13 GND A12, B12, C12, D12 AVCLK Clock 1.8V Supply Voltage. Accepts a 1.7V to 1.9V supply voltage range. Connect 47nF bypass capacitors between AVCLK and GND. B1 CREF Noise Bypass Pin. A 1µF capacitor between the CREF and DACREF band limits the phase noise of the MAX19692. B2 REFRES Calibration Reference Resistor Input. Connect a 500Ω resistor between REFRES and AVDD3.3. The internal analog output resistors are calibrated to this external resistor. Ground. Connect to ground plane with minimum inductance. RZ Return-to-Zero (RZ) Mode-Select Input. RZ = 0 (and RF = 0): Normal DAC (NRZ) operation (default). RZ = 1 (and RF = 0): Return-to-zero (RZ) DAC operation. RZ is a 3.3V CMOS logic input with an internal pulldown resistor. B4 RF Radio Frequency (RF) Mode-Select Input. RF = 0: NRZ or RZ DAC operation. RF = 1 (and RZ = 0): RF DAC operation. RF is a 3.3V CMOS logic input with internal pulldown resistor. C13 CLKP LVDS-Compatible Converter Clock Input. There is an internal 100Ω termination resistor between CLKP and CLKN. B13 CLKN LVDS-Compatible Converter Clock Input. There is an internal 100Ω termination resistor between CLKP and CLKN. B3 C1 CAL DAC Output Resistance Calibration Input. Calibration of the internal output resistors is initiated by a rising edge on CAL. CAL = 1: Output resistors are calibrated. CAL = 0: Output resistors are uncalibrated. CAL is a 3.3V CMOS input with an internal pulldown resistor. Leakage current is less than ±15µA. ______________________________________________________________________________________ 11 MAX19692 Pin Description MAX19692 12-Bit, 2.3Gsps, Multi-Nyquist DAC with Selectable Frequency Response Pin Description (continued) PIN NAME F6–F3, F1, F2, H6–H1 DAP11–DAP0 FUNCTION Positive Terminals of A-Channel LVDS Data Inputs. DAP11 is MSB. Offset binary format. Negative Terminals of A-Channel LVDS Data Inputs G6–G3, G1, G2, J6–J1 DAN11–DAN0 K1–K4, M1–M4, K5, M5, K6, M6 DBP11–DBP0 Positive Terminals of B-Channel LVDS Data Inputs. DBP11 is MSB. Offset binary format. L1–L4, N1–N4, L5, N5, L6, N6 DBN11–DBN0 Negative Terminals of B-Channel LVDS Data Inputs M7, K7, M8, K8, M9–M12, K9, K10, K11, L12 DCP11–DCP0 Positive Terminals of C-Channel LVDS Data Inputs. DCP11 is MSB. Offset binary format. N7, L7, N8, L8, N9–N12, L9, L10, L11, K12 DCN11–DCN0 Negative Terminals of C-Channel LVDS Data Inputs G7, J7, J12–J8, G12–G8 DDP11–DDP0 Positive Terminals of D-Channel LVDS Data Inputs. DDP11 is MSB. Offset binary format. F7, H7, H12–H8, F12–F8 DDN11–DDN0 Negative Terminals of D-Channel LVDS Data Inputs J13 H13 DATACLKP DATACLKN Positive Terminal of LVDS Data Output Clock Negative Terminal of LVDS Data Output Clock DELAY Data Clock Delay Mode Input. Adjusts the delay of the output data clock. DELAY = 0: No delay added. DELAY = 1: Add delay of 1/2 input data period (2 DAC clock cycles). DELAY is a 3.3V CMOS input with an internal pulldown resistor. L13 CLKDIV Data Clock Divide Mode Input. CLKDIV = 1: Data clock rate = input data rate / 2 (fCLK / 8). CLKDIV = 0: Data clock rate = input data rate / 4 (fCLK / 16). CLKDIV is a 3.3V CMOS input with an internal pulldown resistor. N13 N.C. K13 No Connection. This pin should be left unconnected. Detailed Description The MAX19692 is a high-performance, high-speed, 12-bit current-steering DAC with an integrated 50Ω differential output termination. The DAC is capable of operating with clock speeds up to 2.3GHz. The converter consists of an edge-triggered 4:1 input data multiplexer followed by a current-steering circuit. This circuit is capable of generating differential full-scale currents in the 8mA to 20mA range. Internal 25Ω resistors on each output, in combination with an external termination, convert the differential current into a voltage. The internal resistors are terminated to the 3.3V analog supply, AVDD3.3. The internal termination resistors can be calibrated to an external 500Ω precision resistor. A calibration cycle can be run every time the converter is powered up, or at any other time. An integrated 1.2V-bandgap reference, control amplifier, and user-selectable external resistor determine the data converter’s full-scale range. The converter features selectable frequency response to allow application-dependent optimization of output power and gain flatness. Three responses can be selected: non-return-to-zero (NRZ), return-to-zero (RZ), or radio frequency (RF). 12 Reference Input/Output The MAX19692 supports operation with the on-chip 1.2Vbandgap reference or an external reference voltage source. REFIO serves as the input for an external, lowimpedance reference source, and as the output if the DAC is operating with the internal reference. For stable operation with the internal reference, REFIO should be decoupled to DACREF with a 1µF capacitor. REFIO must be buffered with an external amplifier if heavier loading is required, due to its 10kΩ series resistance. The MAX19692’s reference circuit (Figure 1) employs a control amplifier, designed to regulate the full-scale current IOUT for the differential current outputs of the DAC. The output current can be calculated as follows: IOUT = 32 x IREF x 4095/4096 where I REF is the reference output current (I REF = VREFIO / RSET) and IOUT is the full-scale output current of the DAC. Located between FSADJ and DACREF, RSET is typically set to 2kΩ, which results in a full-scale current of 20mA if the internal reference is used. ______________________________________________________________________________________ 12-Bit, 2.3Gsps, Multi-Nyquist DAC with Selectable Frequency Response 1.2V REFERENCE 10kΩ 50Ω transformer. If the transformer is center tapped, it is recommended that the center tap be connected to AVDD3.3. If the transformer is not center tapped, bias tees or RF chokes can be used to pull up the outputs. Figure 2 shows an equivalent circuit of the internal output structure of the MAX19692. The termination resistors, RT, are calibrated to 23.5Ω. RM = RM1 + RM2 + RM3 is resistance associated with the DAC output traces and bond wires, and is not calibrated. The output resistance is equal to 2RT + 2RM, and is nominally 50Ω. The MAX19692 is normally used with an external differential 50Ω load, RL. For this case, the peak differential output voltage is calculated as: VOUT = IOUT × MAX19692 REFIO 1µF OUTP FSADJ CURRENTSOURCE ARRAY DAC IREF RSET DACREF OUTN RLRT RL + 2RM + 2RT where IOUT is the full-scale current, which is typically set to 20mA. With RL = 50Ω, RT = 23.5Ω, and RM = 1.5Ω, VOUT = 0.235V is found. This corresponds to an output power of -2.6dBm. As shown in Figure 2, the output circuit has some resistive, capacitive, and inductive elements. These elements limit the output bandwidth to 2GHz with a resistive differential 50Ω load. IREF = VREFIO / RSET Output Resistor Calibration The integrated termination resistors, RT, must be calibrated to have an accurately known DAC output resistance and an accurately known DAC output voltage. Figure 1. Reference Architecture, Internal Reference Configuration AVDD3.3 0.4pF RT = 23.5Ω 0.5pF RT = 23.5Ω RM1 = 0.6Ω 0.3nH 0.3nH RM2 = 0.4Ω 1.3nH RM3 = 0.5Ω OUTP 3pF 50Ω 3pF 0.75pF RM1 = 0.6Ω 0.3nH 0.3nH RM2 = 0.4Ω 1.3nH RM3 = 0.5Ω OUTN 10mA + IFS x (4095 - CODE) / 4096 10mA + IFS x CODE / 4096 0.4pF 0.5pF Figure 2. Equivalent Output Circuit ______________________________________________________________________________________ 13 MAX19692 Analog Outputs The MAX19692 is a differential current-steering DAC with built-in self-calibrated output termination resistors to optimize performance. The outputs are terminated to AVDD3.3, and are calibrated to provide a 50Ω differential output resistance. In addition to the signal current, a constant 10mA current sink is connected to each DAC output. Typically, the outputs should be used with a DAC Impulse/Frequency Response Selection The termination resistors are calibrated to the external reference resistor, RREFRES, which should be connected between REFRES (pin B2) and AVDD3.3. RREFRES is nominally 500Ω. A plot showing the typical relation between the DAC output resistance and RREFRES is shown in Figure 3. The MAX19692 has three impulse/frequency response modes. These are set with the RZ and RF input pins as described in Table 1. The impulse responses of the three operating modes are shown in Figure 4. The sample period is equal to T. The default operating mode of the MAX19692 is NRZ mode. The sinc (sine(x)/x) response has zeros at every multiple of the DAC update frequency fCLK = 1/T. Using this impulse response, the frequency response of the DAC has the familiar sinc shape: The calibration cycle is initiated with a rising edge on the CAL pin. The CAL pin must be asserted after the supply voltages and the reference voltage have reached steady state. Input data should not be switching while calibration is running. The duration of the calibration cycle is shorter than 65,536 DAC clock cycles—which is less than 65.6µs if the converter is operated with a 1GHz clock rate. The CAL pin must be held high for the output resistors to remain calibrated. If the clock is stopped, or if power is cycled, a new calibration cycle must be run. sin(πfOUT T) ANRZ = A 0 πfOUT T where fOUT is the DAC output frequency, T = 1/fCLK is the period of the DAC clock, and A0 is the peak low-frequency output amplitude. In RZ mode, the DAC output has a 50% duty cycle. The DAC output stays at midscale for the remaining 50% of the clock cycle. The resulting frequency response is: 55 54 53 52 ARZ = 51 ROUT (Ω) MAX19692 12-Bit, 2.3Gsps, Multi-Nyquist DAC with Selectable Frequency Response 50 A 0 sin(πfOUT T / 2) 2 πfOUT T / 2 49 48 Table 1. RZ and RF Input Truth Table 47 46 RZ RF FREQUENCY RESPONSE MODE 45 0 0 NRZ 450 460 470 480 490 500 510 520 530 540 550 1 0 RZ REFRES (Ω) 0 1 RF 1 1 Do not use 44 Figure 3. Output Resistance vs. REFRES Resistor T/2 -T/2 T/2 (a) -T/2 T/2 (b) -T/2 (c) Figure 4. Impulse Responses in (a) NRZ Mode, (b) RZ Mode, and (c) RF Mode 14 ______________________________________________________________________________________ 12-Bit, 2.3Gsps, Multi-Nyquist DAC with Selectable Frequency Response MAX19692 SELECTABLE FREQUENCY RESPONSE -5 NRZ RZ 2.5 RF 2.5V MAX PEAK-TO-PEAK DIFFERENTIAL SINUSOIDAL CLOCK VOLTAGE (V) OUTPUT AMPLITUDE RESPONSE (dB) 0 -10 -15 -20 -25 -30 -35 -40 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.0 VALID OPERATING REGION [2.3Gsps, 2.0V] 1.5 1.0 0.6V MIN 0.5 [1.5Gsps, 0.6V] 0.5 1.0 1.5 2.0 2.3 DAC UPDATE RATE (Gsps) fOUT NORMALIZED TO DAC UPDATE RATE (fCLK) Figure 5. Amplitude Responses for NRZ Mode (Solid Line), RZ Mode (Dash-Dot Line), and RF Mode (Dashed Line). Excludes output bandwidth limitation. Figure 6. Recommended Clock Amplitude This frequency response is flatter than the NRZ response in the three first Nyquist zones, particularly in the 2nd and 3rd Nyquist zones—making this DAC usable for outputting wideband signals in the 2nd and 3rd Nyquist zones. The MAX19692 features a flexible differential clock input (CLKP, CLKN) operating from a separate supply (AVCLK) to achieve the best possible jitter performance. The two clock inputs can be driven from a single-ended or a differential clock source. A sine wave or a square wave can be used. For single-ended operation, CLKP should be driven by a logic source, while CLKN should be bypassed to GND with a 0.1µF capacitor. Driving the clocks differentially is recommended for optimum jitter performance. Choose a clock amplitude that is as large as possible (without the clock voltage at the CLKN and CLKP pins going more than 200mV below ground or above the AVCLK supply voltage) to minimize jitter. This results in the most accurate duty cycle—and hence the most accurate gain in RZ and RF modes. For an AC-coupled, differential sine-wave clock, the clock amplitude should not be higher than 2.5V peak-to-peak (12dBm if terminated in 50Ω). The typical performance plots in this data sheet have generally been measured using a 10dBm (2VP-P) clock amplitude. The MAX19692 can be used with a sinusoidal clock amplitude as low as 0.6VP-P below 1.5Gsps. For higher update rates, the clock amplitude should stay within the operating region specified in Figure 6. The CLKP and CLKN pins are internally biased to 0.6V with resistors. This allows the user to AC-couple clock sources directly to the device without external resistors to define the DC level. Clock Inputs The third mode of operation is the RF mode. In this mode, the DAC output response is inverted in the second half of the clock cycle, resulting in a doublet pulse at the output of the DAC in every clock cycle. The resulting DAC frequency response is: sin(πfOUT T / 2) ARF = A 0 × sin(πfOUT T / 2) T / 2 π f OUT The RF mode increases the DAC output power in the second and third Nyquist zones and attenuates it in the first Nyquist zone. The frequency responses for the three modes of operation are plotted in Figure 5. NRZ mode provides the highest power in the first Nyquist zone. RZ mode provides the flattest frequency response in the first and third Nyquist zones, and RF mode provides superior output power in the second and third Nyquist zones, as well as the flattest gain in the second Nyquist zone. ______________________________________________________________________________________ 15 MAX19692 12-Bit, 2.3Gsps, Multi-Nyquist DAC with Selectable Frequency Response 100nF MINI-CIRCUITS TC1-1-13M CLKP 50Ω 5kΩ 100Ω 50Ω +0.6V 5kΩ CLKN MAX19692 100nF Figure 7. Typical Clock Application Circuit Clock Duty Cycle SINGLE-ENDED CLOCK INPUT The duty cycle of the converter clock should be close to 50%. If an AC-coupled sine-wave clock is used, the clock duty cycle is automatically close to 50%. If a squarewave clock is used, this is not necessarily the case. MINI-CIRCUITS TC1-1-13M 50Ω MINI-CIRCUITS 100pF CLKP TC1-1-13M MINI-CIRCUITS TC1-1-13M 50Ω 100pF CLKN Figure 8. Clock Application Circuit with Improved Symmetry The MAX19692 has an internal 100Ω termination resistor between CLKP and CLKN. An extra 100Ω differential termination resistor should be added if using a 50Ω clock source. See Figure 7 for a convenient and quick way to apply a differential signal created from a singleended source and a wideband transformer. The clock circuit in Figure 7 has some amplitude asymmetry at update rates above 1Gsps, due to transformer loss. This may cause performance degradation for some operating conditions. A clock interface circuit with improved symmetry using three balun transformers is shown in Figure 8. This clock interface circuit provides symmetric and balanced clock signals for frequencies up to the maximum update rate of the MAX19692. An equivalent circuit model for the clock inputs is shown in Figure 9. 16 Keeping the clock duty cycle close to 50% is particularly important when operating in RZ and RF modes. When operating in RZ mode, clock duty-cycle deviation from 50% distorts the converter’s frequency response. A clock duty cycle above 50% increases the converter’s output power at low frequencies, and lowers the frequency of the zero in the frequency response function—effectively producing a frequency response between that of NRZ and RZ modes. When operating in RF mode, a clock duty cycle higher or lower than 50% increases the output amplitude at low frequencies in the first Nyquist zone and slightly lowers the output amplitude in the second and third Nyquist zones. Data Inputs Data inputs (DAP[11:0], DAN[11:0], DBP[11:0], DBN[11:0], DCP[11:0], DCN[11:0], DDP[11:0], DDN[11:0]) have LVDS receivers followed by edgetriggered flip flops. Four 12-bit buses accept data in offset binary format. The LVDS inputs feature on-chip termination with differential 100Ω resistors. A 1.25V common-mode level with a ±400mV differential swing can be applied to these inputs. See Figure 10 for an equivalent circuit of the LVDS inputs. ______________________________________________________________________________________ 12-Bit, 2.3Gsps, Multi-Nyquist DAC with Selectable Frequency Response MAX19692 AVCLK 0.1Ω 100Ω 2.7nH CLKP 1.0pF 0.1pF 0.05pF 10kΩ 5kΩ 5kΩ 5kΩ 0.1pF 100Ω 0.1Ω 2.7nH CLKN 0.1pF 100Ω 1.0pF 0.1pF Figure 9. Clock Input Equivalent Circuit 1.2pF 0.05Ω 1.2nH 0.1Ω 1.75nH D_P K = 0.25 COUPLING FACTOR 0.03pF K = 0.47 COUPLING FACTOR 106Ω D D_N 0.05Ω 1.2nH 0.1Ω K TO 4:1 MULTIPLEXER CLK 1.75nH 1.2pF CLOCK Figure 10. LVDS Input Equivalent Circuit Data-Timing Relationships The timing of the LVDS inputs is defined with respect to the LVDS output DATACLK (DATACLKP - DATACLKN). The LVDS data inputs are latched at 1/4 the input clock frequency. The DATACLK output frequency is divided by another factor of 4 (CLKDIV = 0) or by 2 (CLKDIV = 1). Define the 0° point of DATACLK as the rising edge. For the case of CLKDIV = 1, data are latched at 0° and 180° of DATACLK, and setup and hold times must be satisfied for both these points in time. For the case of CLKDIV = 0, data are latched at 0°, 90°, 180°, and 270° of DATACLK. Setup and hold times must be satisfied for all four of these points in time. A delay set by the DELAY pin can skew DATACLK by 1/2 period of the input data period, as shown in Figure 11. This eases interfacing to an FPGA where the clock to Q delay of the LVDS outputs is not adjustable. The clock driving the data input register is not delayed with the DELAY pin. The setup and hold times are always referred to the case when DELAY = 0. Data-timing relationships are shown in Figure 12. ______________________________________________________________________________________ 17 MAX19692 12-Bit, 2.3Gsps, Multi-Nyquist DAC with Selectable Frequency Response CLKP, CLKN DATACLK (DELAY = 0) DATACLK (DELAY = 1) (a) CLKDIV = 1 DATACLK (DELAY = 0) DATACLK (DELAY = 1) (b) CLKDIV = 0 Figure 11. Effect of Setting DELAY = 1 on Data Clock Output CLKP, CLKN DATACLK (CLKDIV = 1) DAP[11:0], DAN[11:0] DBP[11:0], DBN[11:0] DCP[11:0], DCN[11:0] DDP[11:0], DDN[11:0] tH tS tH tS a) DUAL-DATA-RATE INTERFACE CLKP, CLKN DATACLK (CLKDIV = 0) DAP[11:0], DAN[11:0] DBP[11:0], DBN[11:0] DCP[11:0], DCN[11:0] DDP[11:0], DDN[11:0] tH tS tH tS tH tS tH tS b) QUAD-DATA-RATE INTERFACE Figure 12. Setup (tS) and Hold Time (tH) for Data Input Interface 18 ______________________________________________________________________________________ 12-Bit, 2.3Gsps, Multi-Nyquist DAC with Selectable Frequency Response LVDS DATA MAX19692 OUTPUT REGISTER DAC OUTP MINI-CIRCUITS TCBT-2R5G fCLK / n* SPRAGUE GOODMAN GLSW4M202 50Ω SINGLE-ENDED OUTPUT AVDD3.3 DATACLK 4:1 MUX DATA SOURCE (FPGA/ASIC) (a) MAX19692 OUTN OUT fCLK LVDS DATA (a) MAX19692 OUTPUT REGISTER MINI-CIRCUITS TCBT-2R5G DAC AVDD3.3 fCLK / n* DATA SOURCE (FPGA/ASIC) OUT DATACLK 4:1 MUX fCLK OUTP MINI-CIRCUITS TCBT-2R5G AVDD3.3 PHASE DET SYSTEM CLOCK fCLK / n* MINI CIRCUITS TC1-1-13M 50Ω SINGLE-ENDED OUTPUT VCO LOW-PHASE-NOISE PLL MAX19692 (b) (b) OUTN MINI-CIRCUITS TCBT-2R5G Figure 13. Possible Output Circuits for MAX19692 Applications Information Differential Coupling Using RF Transformers The differential voltage existing between OUTP and OUTN can be converted to a single-ended voltage using a transformer or a differential amplifier configuration. Using a differential transformer-coupled output, in which the output power is limited to -2.6dBm, can optimize the dynamic performance. It is recommended that the DAC outputs are pulled up to 3.3V. The use of bias tees, as shown in Figure 13, is recommended for optimal performance. RF chokes can be used rather than bias tees if an isolation transformer is used. Not pulling up the outputs to 3.3V is also possible, but may result in some degradation of dynamic performance in some applications. Two output circuits are shown in Figure 13. The circuit shown in Figure 13(a) has less than 3dB loss (in addition to the sinc attenuation built into the DAC) from approximately *n = 8 OR n = 16 AS SET BY CLKDIV. Figure 14. Data Source to DAC Interfacing 4MHz to 700MHz. The circuit shown in Figure 13(b)—that is used on the MAX19692 evaluation kit—has less than 3dB loss at frequencies up to approximately 1150MHz. To achieve the maximum bandwidth, it is important to minimize the inductance in the ground lead on the secondary side of the transformers. It is recommended to use a very short trace and multiple vias for the connection to the ground plane. Data Synchronization The DAC clock is running at four times the data rate of the data interface to the MAX19692. An LVDS level data clock output (DATACLKP, DATACLKN) is provided to help the user synchronize the data source and the DAC. The output data clock frequency can be set to 1/2 the input data rate or 1/4 the input data rate. When the DAC is running at full speed, this allows the data clock to be interfaced directly to FPGAs without using an external clock divider. For example, if the DAC is updating at 2.3Gsps, the input data rate is 575Mwps. If the DAC is interfaced to an FPGA, one could run the data clock at 1/4 the data input rate; hence the data output clock frequency would be 143.75MHz. ______________________________________________________________________________________ 19 MAX19692 AVDD3.3 MAX19692 12-Bit, 2.3Gsps, Multi-Nyquist DAC with Selectable Frequency Response If the system clock is running at the DAC update rate, the scheme in Figure 14(a) can be used. In this case, the system is clocked using the data clock output from the DAC. The delays of the data and the clock depend upon line lengths and loading. Hence, clock deskewing using a phase-locked loop may be necessary to make this system work properly at speed. When CLKDIV = 0, the data clock output can be phase-shifted by 45° using the DELAY pin. When CLKDIV = 1, the data clock output can be phase-shifted by 90° using the DELAY pin. An alternative solution is shown in Figure 14(b). In this case, the system clock distribution is running at the data clock rate. A low-jitter, low-phase-noise phaselocked loop is used to generate the high-speed DAC clock. Using the data clock for feedback into the PLL ensures synchronization between data and clock. If more than one MAX19692 is used in a system, and the relative phases need to be defined, the divided data clock of each DAC should be phase locked to a system clock running at data-rate / 4 or data-rate / 2, which is equal to the input clock rate divided by 8 or 16. Grounding, Bypassing, Power-Supply, and Board Layout Considerations Grounding and power-supply decoupling can strongly influence the performance of the MAX19692. Unwanted digital crosstalk may couple through the input, reference, power supply, and ground connections, affecting dynamic performance. Proper grounding and powersupply decoupling guidelines for high-speed, high-frequency applications should be closely followed. This reduces EMI and internal crosstalk that can significantly affect the dynamic performance of the MAX19692. Use of a multilayer PC board with separate ground and power-supply planes is required. It is recommended that the analog output and the clock input are run as controlled-impedance microstrip lines on the top layer of the board, directly above a ground plane, and that no vias are used for the clock input (CLKP, CLKN) and the analog output (OUTP, OUTN) signals. Depending on the length of the traces, and the operating condition, a low-loss dielectric material (such as ROGERS RO4003) as the top layer dielectric may be advisable. The data clock (DATACLKP, DATACLKN) must be routed so its coupling into the clock input and the DAC output is minimized. Digital input signals should be run as controlled-impedance strip lines between ground planes. Digital signals should be kept as far away from sensitive analog inputs, reference input sense lines, common-mode inputs, and clock inputs as practical. It is particularly important to 20 minimize coupling between digital signals and the clock to optimize dynamic performance for high output frequencies. A symmetric design of the clock input and analog output lines is critical to minimize distortion and optimize the DAC’s dynamic performance. Digital signal paths should be kept short and run lengths matched to avoid propagation delay and dataskew mismatches. The MAX19692 supports three separate power-supply inputs for analog 3.3V (AVDD3.3), switching (VDD1.8), and clock (AVCLK) circuits. Each AVDD3.3, VDD1.8, and AVCLK input should at least be decoupled with a separate 47nF capacitor as close to the pin as possible and their opposite ends with the shortest possible connection to the corresponding ground plane, to minimize loop inductance. All three power-supply voltages should also be decoupled at the point they enter the PC board with tantalum or electrolytic capacitors. Ferrite beads with additional decoupling capacitors forming a pi-network could also improve performance. The power-supply inputs V DD1.8 and AV CLK of the MAX19692 allow a 1.8V ±0.1V supply voltage range for update rates < 2.0Gsps. A range of 1.8V to 1.9V should be used for 2.0Gsps to 2.3Gsps. The analog powersupply input AVDD3.3 allows a 3.3V ±0.2V supply voltage range. To optimize the dynamic performance of the MAX19692 over temperature at the highest update rates, it is important that the difference between VDD1.8 and AV DD3.3 is at least 1.4V. If V DD1.8 is 1.9V and AVDD3.3 is 3.1V, dynamic performance at these update rates will degrade at higher temperatures, as shown in the Typical Operating Characteristics. The MAX19692 is packaged in a 169 CSBGA package with 0.8mm ball pitch (package code: X16911-1), providing design flexibility, thermal efficiency, and a small footprint for the DAC. Static Performance Parameter Definitions Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from either a best straight-line fit (closest approximation to the actual transfer curve) or end-point fit (a line drawn between the end points of the transfer function, once offset and gain errors have been nullified). For a DAC, the deviations are measured at every individual step. The MAX19692 INL is specified using the end-point method. ______________________________________________________________________________________ 12-Bit, 2.3Gsps, Multi-Nyquist DAC with Selectable Frequency Response Noise Spectral Density The DAC output noise is the sum of the quantization noise and other noise sources. Noise spectral density is the noise power in a 1Hz bandwidth. Offset Error SFDR is the ratio of the RMS amplitude of the carrier frequency (maximum signal components) to the RMS value of the largest distortion component. SFDR is usually measured in dBc with respect to the carrier frequency amplitude or in dBFS with respect to the DAC’s full-scale range. Depending on its test condition, SFDR is observed within a predefined window or to Nyquist. The offset error is the difference between the ideal and the actual offset current. For a DAC, the offset point is the average value at the output for the two midscale digital input codes with respect to the full scale of the DAC. This error affects all codes by the same amount. Gain Error A gain error is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step. Spurious-Free Dynamic Range (SFDR) Two-/Four-Tone Intermodulation Distortion (IMD) The two-/four-tone IMD is the ratio expressed in dBc (or dBFS) of the worst 3rd-order (or higher) IMD products to any output tone. Dynamic Performance Parameter Definitions Settling Time The settling time is the amount of time required from the start of a transition until the DAC output settles its new output value to within the specified accuracy. ______________________________________________________________________________________ 21 MAX19692 Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step height and the ideal value of 1 LSB. A DNL error specification greater than -1 LSB guarantees a monotonic transfer function. 12-Bit, 2.3Gsps, Multi-Nyquist DAC with Selectable Frequency Response MAX19692 Pin Configuration TOP VIEW MAX19692 A B C D E F G H J K L M N 1 2 3 4 5 6 7 8 9 10 11 12 13 REFIO FSADJ DACREF AVDD3.3 AVDD3.3 OUTP AVDD3.3 OUTN AVDD3.3 VDD1.8 GND AVCLK GND A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 CREF REFRES RZ RF GND GND GND GND GND VDD1.8 GND AVCLK CLKN B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 CAL VDD1.8 VDD1.8 GND GND GND GND GND GND VDD1.8 GND AVCLK CLKP C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 GND GND GND GND GND GND GND GND GND GND GND AVCLK GND D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 VDD1.8 VDD1.8 VDD1.8 VDD1.8 GND GND GND GND GND VDD1.8 VDD1.8 VDD1.8 VDD1.8 E6 E7 E8 E9 E10 E11 E12 E13 E1 E2 E3 E4 E5 DAP7 DAP6 DAP8 DAP9 DAP10 DAP11 DDN11 DDN0 DDN1 DDN2 DDN3 DDN4 VDD1.8 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 DAN7 DAN6 DAN8 DAN9 DAN10 DAN11 DDP11 DDP0 DDP1 DDP2 DDP3 DDP4 GND G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 DAP0 DAP1 DAP2 DAP3 DAP4 DAP5 DDN10 DDN5 DDN6 DDN7 DDN8 DDN9 DATACLKN H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 DAN0 DAN1 DAN2 DAN3 DAN4 DAN5 DDP10 DDP5 DDP6 DDP7 DDP8 DDP9 DATACLKP J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 DBP11 DBP10 DBP9 DBP8 DBP3 DBP1 DCP10 DCP8 DCP3 DCP2 DCP1 DCN0 DELAY K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 DBN11 DBN10 DBN9 DBN8 DBN3 DBN1 DCN10 DCN8 DCN3 DCN2 DCN1 DCP0 CLKDIV L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 DBP7 DBP6 DBP5 DBP4 DBP2 DBP0 DCP11 DCP9 DCP7 DCP6 DCP5 DCP4 GND M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 DBN7 DBN6 DBN5 DBN4 DBN2 DBN0 DCN11 DCN9 DCN7 DCN6 DCN5 DCN4 N.C. N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 The MAX19692 is packaged in an 11mm x 11mm, 169 CSBGA package (package code X16911-1). Ball pitch is 0.8mm. 22 ______________________________________________________________________________________ 12-Bit, 2.3Gsps, Multi-Nyquist DAC with Selectable Frequency Response 169L CSBGA.EPS PACKAGE OUTLINE 169L CSBGA, 11x11x1.4mm 21-0165 A 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23 © 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. MAX19692 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)