CD4512BMS CMOS Dual 4-Bit Latch December 1992 Features Pinout • High-Voltage Types (20-Volt Rating) CD4512BMS TOP VIEW • 3-State Outputs • Standardized, Symmetrical Output Characteristics • 100% Tested for Quiescent Current at 20V • 5V, 10V, and 15V Parametric Ratings D0 1 16 VDD D1 2 15 3-STATE DISABLE D2 3 14 SEL. OUTPUT D3 4 13 C • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and 25oC D4 5 12 B D5 6 11 A • Noise Margin (Full Package-Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V D6 7 10 INHIBIT 9 D7 VSS 8 • Meets all Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ‘B’ Series CMOS Devices" Functional Diagram 3-STATE DISABLE INHIBIT Applications • Digital Multiplexing D0-1 • Number-sequence Generation D1-2 • Signal Gating D2-3 CHANNELS INPUTS Description 15 D3-4 D4-5 14 SELECT OUTPUT D5-6 CD4512BMS is an 8-channel data selector featuring a threestate output that can interface directly with, and drive, data lines of bus-oriented systems. The CD4512BMS is supplied in these 16 lead outline packages: 10 D6-7 D7-9 A-11 SELECT CONTROL VDD = 16 VSS = 8 B-12 C-13 Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4S H1E H3X CD4512BMS CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-1180 File Number 3340 Specifications CD4512BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current Input Leakage Current Input Leakage Current SYMBOL IDD IIL IIH CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND LIMITS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 1 +25oC - 10 µA 2 +125 C - 1000 µA VDD = 18V, VIN = VDD or GND 3 -55oC - 10 µA VIN = VDD or GND 1 +25oC -100 - nA 2 +125oC -1000 - nA VDD = 18V 3 -55oC -100 - nA VDD = 20 1 +25oC - 100 nA 2 +125oC - 1000 nA 3 -55oC - 100 nA - 50 mV VIN = VDD or GND VDD = 20 VDD = 18V o Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA mA Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V VDD = 2.8V, VIN = VDD or GND 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC Functional F VOH > VOL < VDD/2 VDD/2 V Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC - 4 V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC 11 - V Tri-State Output Leakage IOZL VIN = VDD or GND VOUT = 0V 1 +25oC -0.4 - µA Tri-State Output Leakage IOZH VIN = VDD or GND VOUT = VDD VDD = 20V 2 +125oC -12 - µA VDD = 18V 3 -55oC -0.4 - µA VDD = 20V 1 +25oC - 0.4 µA 2 +125oC - 12 µA 3 -55oC - 0.4 µA VDD = 18V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 7-1181 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. Specifications CD4512BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Propagation Delay Inhibit to Output SYMBOL TPHL1 TPLH1 GROUP A SUBGROUPS TEMPERATURE CONDITIONS VDD = 5V, VIN = VDD or GND (Note 1, 2) Propagation Delay “A” Select to Output TPHL2 TPLH2 VDD = 5V, VIN = VDD or GND (Note 1, 2) Propagation Delay Data to Output TPHL3 TPLH3 VDD = 5V, VIN = VDD or GND (Note 1, 2) Propagation Delay 3-State Disable TPHZ TPZH VDD = 5V, VIN = VDD or GND (Note 2, 3) Propagation Delay 3-State Disable TPLZ TPZL VDD = 5V, VIN = VDD or GND (Note 2, 3) Transition Time TTHL TTLH VDD = 5V, VIN = VDD or GND (Note 2, 3) 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC LIMITS MIN MAX UNITS - 280 ns - 378 ns - 400 ns - 540 ns - 360 ns - 486 ns - 120 ns - 162 ns - 120 ns - 162 ns - 200 ns - 270 ns NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS NOTES VDD = 5V, VIN = VDD or GND 1, 2 TEMPERATURE -55oC, +25oC +125oC VDD = 10V, VIN = VDD or GND 1, 2 o o -55 C, +25 C Output Voltage VOL VDD = 5V, No Load 1, 2 UNITS - 5 µA - 150 µA - 10 µA - 300 µA - 10 µA +125oC - 600 µA +25oC, +125oC, - 50 mV +125 1, 2 MAX -55oC, +25oC oC VDD = 15V, VIN = VDD or GND MIN -55oC Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC 9.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA -55oC 0.64 - mA Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) IOL10 IOL15 IOH5A IOH5B VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V 1, 2 1, 2 1, 2 VDD = 5V, VOUT = 2.5V 1, 2 7-1182 +125oC 0.9 - mA -55oC 1.6 - mA +125oC 2.4 - mA -55oC 4.2 - mA +125oC - -0.36 mA -55oC - -0.64 mA +125oC - -1.15 mA -55oC - -2.0 mA Specifications CD4512BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Output Current (Source) SYMBOL IOH10 CONDITIONS VDD = 10V, VOUT = 9.5V NOTES TEMPERATURE MIN MAX UNITS 1, 2 +125oC - -0.9 mA -55 C - -1.6 mA +125oC - -2.4 mA - -4.2 mA - 3 V o Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 -55 Input Voltage Low VIL oC +25oC, +125oC, VDD = 10V, VOH > 9V, VOL < 1V 1, 2 VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC +7 - V 1, 2, 3 +25oC - 140 ns -55oC Input Voltage High VIH Propagation Delay Inhibit to Output TPHL1 TPLH1 VDD = 15V 1, 2, 3 +25 C - 100 ns Propagation Delay “A” Select ot Output TPHL2 TPLH2 VDD = 10V 1, 2, 3 +25oC - 170 ns VDD = 15V 1, 2, 3 +25oC - 120 ns Propagation Delay Data to Output TPHL3 TPLH3 VDD = 10V 1, 2, 3 +25oC - 150 ns 1, 2, 3 +25oC - 110 ns Propagation Delay 3-State Enable TPHZ TPZH VDD = 10V VDD = 15V o o VDD = 10V 1, 2, 4 +25 C - 60 ns VDD = 15V 1, 2, 4 +25oC - 40 ns 1, 2, 4 +25oC - 60 ns oC Propagation Delay 3-State Enable TPLZ TPZL VDD = 10V VDD = 15V 1, 2, 4 +25 - 40 ns Transition Time TTHL TTLH VDD = 10V 1, 2, 3 +25oC - 100 ns VDD = 15V 1, 2, 3 +25oC - 80 ns oC - 7.5 pF Input Capacitance CIN Any Input 1, 2 +25 NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. CL = 50pF, RL = 1K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 25 µA 1, 4 +25oC -2.8 -0.2 V VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V 1, 4 +25oC - ±1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns N Threshold Voltage VNTH N Threshold Voltage Delta ∆VTN P Threshold Voltage VTP P Threshold Voltage Delta ∆VTP Functional F VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 3. See Table 2 for +25oC limit. NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record 7-1183 Specifications CD4512BMS TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-2 IDD ± 1.0µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading IOH5A ± 20% x Pre-Test Reading Output Current (Source) TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas 100% 5004 1, 7, 9 100% 5004 1, 7, 9, Deltas CONFORMANCE GROUP PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group B IDD, IOL5, IOH5A 100% 5004 2, 3, 8A, 8B, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 Group A Group D READ AND RECORD Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS Group E Subgroup 2 TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD Static Burn-In 1 Note 1 14 1-13, 15 16 Static Burn-In 2 Note 1 14 8 1-7, 9-13, 15, 16 Dynamic BurnIn Note 1 - 8, 10, 15 16 9V ± -0.5V 50kHz 25kHz 14 1-7, 9, 11, 12 13 Irradiation Note 2 NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V 7-1184 CD4512BMS Logic Diagram C 13 B 12 A 11 D0 * * * * 1 INHIBIT p 10 n D1 2 * D3 4 * * 15 * p n p n D2 3 * 3-STATE DISABLE p VDD p n p n p p n 14 SELECT OUTPUT n n D4 5 D5 6 * * p n p p n VSS n D6 7 D7 9 * * p VDD n p n p p n n VSS * All inputs protected by CMOS protection network. FIGURE 1. LOGIC DIAGRAM TRUTH TABLE SELECT CONT. A B C INH 3-STATE DISABLE SELECT OUTPUT 0 0 0 0 0 D0 1 0 0 0 0 D1 0 1 0 0 0 D2 1 1 0 0 0 D3 0 0 1 0 0 D4 1 0 1 0 0 D5 0 1 1 0 0 D6 1 1 1 0 0 D7 X X X 1 0 0 X X X X 1 High Z 1 = HIGH LEVEL 0 = LOW LEVEL X = DON’T CARE 7-1185 CD4512BMS Typical Performance Characteristics OUTPUT LOW (SINK) CURRENT (IOL) (mA) 200 SUPPLY VOLTAGE (VDD) = 5V 150 100 10V 15V 50 0 0 20 30 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 40 60 80 100 LOAD CAPACITANCE (CL) (pF) 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 2. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC 0 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V 15.0 0 -5 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 -10 10.0 -15 -10V 10V 7.5 -20 -25 5.0 -15V 2.5 -30 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS AMBIENT TEMPERATURE (TA) = +25oC 105 0 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 -10V -15V 8 6 4 -10 -15 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS AMBIENT TEMPERATURE (TA) = +25oC 2 POWER DISSIPATION (PD) - µW OUTPUT LOW (SINK) CURRENT (IOL) (mA) AMBIENT TEMPERATURE (TA) = +25oC OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) TRANSITION TIME (fTHL, fTLH) (ns) AMBIENT TEMPERATURE (TA) = +25oC 104 8 6 4 103 SUPPLY VOLTAGE (VDD) = 15V 10V 10V 5V 2 8 6 4 2 102 8 6 4 CL = 50pF 2 CL = 15pF 10 2 10 4 68 2 4 6 8 2 4 6 8 101 103 102 INPUT FREQUENCY (fIN) (kHz) 2 4 6 8 104 FIGURE 7. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF FREQUENCY 7-1186 CD4512BMS PROPAGATION DELAY TIME (tPHL, tPLH) - ns Typical Performance Characteristics (Continued) AMBIENT TEMPERATURE (TA) = +25oC 300 250 SUPPLY VOLTAGE (VDD) = 5V 200 150 100 10V 50 5V 0 0 20 40 60 80 LOAD CAPACITANCE (CL) (pF) 100 FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (“A” SELECT TO OUTPUT) Chip Dimensions and Pad Layouts 0 10 20 30 40 50 60 70 78 75 70 60 50 40 72-80 (1.829-2.032) 30 20 10 0 4-10 (0.102-0.254) 75-83 (1.905-2.108) Dimensions in parentheses are in milimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch.) METALLIZATION: PASSIVATION: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches 7-1187 WWW.ALLDATASHEET.COM Copyright © Each Manufacturing Company. All Datasheets cannot be modified without permission. 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