5962-0721301QHC, 5962-0721302QHC, 5962-0721303QDC ® Data Sheet March 30, 2007 500MHz Rail-to-Rail Amplifiers Features The 5962-0721301QHC, 5962-0721302QHC, and 59620721303QDC are fully DSCC SMD compliant parts and the SMD data sheets are available on the DSCC website (http://www.dscc.dla.mil/ programs/specfind/default.asp). The 5962-0721301QHC is electrically equivalent to the EL8202, the 5962-0721302QHC is electrically equivalent to the EL8203, and the 5962-0721303QDC is electrically equivalent to the EL8403. Reference equivalent “EL” data sheet for additional information. These parts are dual and quad rail-to-rail amplifiers with a -3dB bandwidth of 500MHz and slew rate of 600V/µs. • 500MHz -3dB bandwidth Running off a low supply current of 13.5mA per channel, the 5962-0721301QHC, 5962-0721302QHC, and 59620721303QDC also feature inputs that go to 0.15V below the VS- rail. The 5962-0721301QHC and 5962-0721302QHC are dual channel amplifiers. The 5962-0721303QDC is a quad channel amplifier. The 5962-0721301QHC includes a fast-acting disable/power-down circuit with a 25ns disable and a 200ns enable, the 5962-0721301QHC is ideal for multiplexing applications. 1 FN6478.0 • 600V/µs slew rate • Supplies from 3V to 5.5V • Rail-to-rail output • Input to 0.15V below VS• Fast 25ns disable (5962-0721301QHC only) Applications • Video amplifiers • Portable/hand-held products • Communications devices Ordering Information PART NUMBER PART MARKING PACKAGE PKG. DWG. # 5962-0721301QHC 0721301QHC 10 Ld Flat Pack K10.A 5962-0721302QHC 0721302QHC 10 Ld Flat Pack K10.A 5962-0721303QDC 0721303QDC 14 Ld Flat Pack K14.A CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2007. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. 5962-0721301QHC, 5962-0721302QHC, 5962-0721302QDC Pinouts 5962-0721302QHC (10 LD FLATPACK) TOP VIEW 5962-0721301QHC (10 LD FLATPACK) TOP VIEW 1 2 3 4 5 INA+ INA- CEA OUTA VS+ VSCEB OUTB INB+ INB- 10 1 9 2 8 3 7 4 6 5 INA+ INA- NC OUTA VS- VS+ NC OUTB INB+ INB- 10 9 8 7 6 5962-0721303QDC (14 LD FLATPACK) TOP VIEW 1 2 3 4 5 6 7 2 OUTA OUTD INA- IND- INA+ IND+ VS+ VS- INB+ INC+ INB- INC- OUTB OUTC 14 13 12 11 10 9 8 FN6478.0 March 30, 2007 5962-0721301QHC, 5962-0721302QHC, 5962-0721302QDC Absolute Maximum Ratings (TA = 25°C) Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . 74.3mW / Op Amp Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Ambient Operating Temperature . . . . . . . . . . . . . . .-55°C to +125°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C Supply Voltage from VS+ to VS- . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . VS+ +0.3V to VS- -0.3V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V Continuous Output Current . . . . . . . . . . . . . . . . . . . 20mA / Op Amp CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VS+ = 5V, VS- = GND, TA = 25°C, VCM = 2.5V, RL to 2.5V, AV = 1, Unless Otherwise Specified DESCRIPTION CONDITIONS MIN TYP MAX UNIT INPUT CHARACTERISTICS RIN Input Resistance CIN Input Capacitance Common Mode 3.5 MΩ 0.5 pF 30 mΩ 65 mA OUTPUT CHARACTERISTICS ROUT Output Resistance IOUT Linear Output Current AV = +1 ENABLE (5962-0721301QHC ONLY) tEN Enable Time 200 ns tDS Disable Time 25 ns VIH-ENB ENABLE Pin Voltage for Power-up 0.8 V VIL-ENB ENABLE Pin Voltage for Shut-down 2 V AV = +1, RF = 0Ω, CL = 2.5pF 500 MHz AV = -1, RF = 1kΩ, CL = 2.5pF 140 MHz AV = +2, RF = 1kΩ, CL = 2.5pF 165 MHz AC PERFORMANCE BW -3dB Bandwidth AV = +10, RF = 1kΩ, CL = 2.5pF 18 MHz BW ±0.1dB Bandwidth AV = +1, RF = 0Ω, CL = 2.5pF 35 MHz Peak Peaking AV = +1, RL = 1kΩ, CL = 2.5pF 2 dB GBWP Gain Bandwidth Product 200 MHz PM Phase Margin RL = 1kΩ, CL = 2.5pF 55 ° SR Slew Rate AV = 2, RL = 100Ω, VOUT = 0.5V to 4.5V 600 V/µs tR Rise Time 2.5VSTEP, 20% - 80% 4 ns tF Fall Time 2.5VSTEP, 20% - 80% 2 ns OS Overshoot 200mV step 10 % tPD Propagation Delay 200mV step 1 ns tS 0.1% Settling Time 200mV step 15 ns dG Differential Gain AV = +2, RF = 1kΩ, RL = 150Ω 0.01 % dP Differential Phase AV = +2, RF = 1kΩ, RL = 150Ω 0.01 ° eN Input Noise Voltage f = 10kHz 12 nV/√Hz iN+ Positive Input Noise Current f = 10kHz 1.7 pA/√Hz iN- Negative Input Noise Current f = 10kHz 1.3 pA/√Hz eS Channel Separation f = 100kHz 95 dB 3 FN6478.0 March 30, 2007 5962-0721301QHC, 5962-0721302QHC, 5962-0721302QDC Pin Descriptions 5962-0721301QHC (10 FLATPACK) 5962-0721302QHC (10 FLATPACK) 5962-0721303QDC (14 FLATPACK) NAME 1, 5 1, 5 3, 5, 10, 12 IN+ Non-inverting input for each channel CE Enable and disable input for each channel 2, 4 FUNCTION 3 3 11 VS- Negative power supply 6, 10 6, 10 2, 6, 9, 13 IN- Inverting input for each channel 7, 9 7, 9 1, 7, 8, 14 OUT Amplifier output for each channel 8 8 4 VS+ Positive power supply NC Not Connected 2, 4 Simplified Schematic Diagram VS+ I1 I2 Q5 IN+ Q1 R8 VBIAS1 Q6 R3 R1 R7 R6 Q7 R2 Q2 DIFFERENTIAL TO SINGLE ENDED DRIVE GENERATOR IN- VBIAS2 Q3 OUT Q4 Q8 R4 R5 R9 VS- All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 4 FN6478.0 March 30, 2007 5962-0721301QHC, 5962-0721302QHC, 5962-0721302QDC Ceramic Metal Seal Flatpack Packages (Flatpack) K10.A MIL-STD-1835 CDFP3-F10 (F-4A, CONFIGURATION B) 10 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE e A INCHES A -A- D -BPIN NO. 1 ID AREA b E1 0.004 M H A-B S Q D S S1 0.036 M H A-B S D S C E -D- A -C- -HL E2 E3 SEATING AND BASE PLANE c1 L E3 (c) b1 M M (b) SECTION A-A MIN MILLIMETERS MAX MIN MAX NOTES A 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - D - 0.290 - 7.37 3 E 0.240 0.260 6.10 6.60 - E1 - 0.280 - 7.11 3 E2 0.125 - 3.18 - - E3 0.030 - 0.76 - 7 2 e LEAD FINISH BASE METAL SYMBOL 0.050 BSC 1.27 BSC - k 0.008 0.015 0.20 0.38 L 0.250 0.370 6.35 9.40 - Q 0.026 0.045 0.66 1.14 8 S1 0.005 - 0.13 - 6 M - 0.0015 - 0.04 - N 10 10 Rev. 0 3/07 NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. This dimension allows for off-center lid, meniscus, and glass overrun. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. 5 FN6478.0 March 30, 2007 5962-0721301QHC, 5962-0721302QHC, 5962-0721302QDC 14 ld FLATPACK Package Outline Drawing K14.A MIL-STD-1835 CDFP3-F14 (F-2A, CONFIGURATION B) A e 14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE A INCHES PIN NO. 1 ID AREA -A- D -B- S1 b E1 0.004 M H A-B S Q D S 0.036 M H A-B S D S C E -D- A -C- -HL E2 E3 SEATING AND BASE PLANE c1 L E3 BASE METAL (c) b1 M SYMBOL MIN MAX MIN MAX NOTES A 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - D - 0.390 - 9.91 3 E 0.235 0.260 5.97 6.60 - E1 - 0.290 - 7.11 3 E2 0.125 - 3.18 - - E3 0.030 - 0.76 - 7 e LEAD FINISH M (b) SECTION A-A MILLIMETERS 0.050 BSC 1.27 BSC - k 0.008 0.015 0.20 0.38 2 L 0.270 0.370 6.86 9.40 - Q 0.026 0.045 0.66 1.14 8 S1 0.005 - 0.13 - 6 M - 0.0015 - N 14 0.04 14 - Rev. 0 5/18/94 NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. This dimension allows for off-center lid, meniscus, and glass overrun. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. 6 FN6478.0 March 30, 2007