LTC5585 - Wideband IQ Demodulator with IIP2 and DC Offset Control

LTC5585
Wideband IQ Demodulator
with IIP2 and DC Offset
Control
DESCRIPTION
FEATURES
400MHz to 4GHz Operating Frequency
n High IIP3: 28.7dBm at 700MHz, 25.7dBm at 1.95GHz
n High IIP2: 70dBm at 700MHz, 60dBm at 1.95GHz
n User Adjustable IIP2 Up to 80dBm
n User Adjustable DC Offset Null
n High Input P1dB: 16dBm at 1950MHz
n I/Q Bandwidth of 530MHz or Higher
n Image Rejection: 43dB at 1950MHz
n Noise Figure: 13.5dB at 700MHz
12.7dB at 1.95GHz
n Conversion Gain: 2.0dB at 700MHz
2.4dB at 1.95GHz
n Single-Ended RF with On-Chip Transformer
n Shutdown Mode
n Operating Temperature Range (T ): –40°C to 105°C
C
n 24-Lead 4mm × 4mm QFN Package
The LTC®5585 is a direct conversion quadrature demodulator optimized for high linearity receiver applications in
the 400MHz to 4GHz frequency range. It is suitable for
communications receivers where an RF signal is directly
converted into I and Q baseband signals with bandwidth
of 530MHz or higher. The LTC5585 incorporates balanced
I and Q mixers, LO buffer amplifiers and a precision, high
frequency quadrature phase shifter. The integrated on-chip
broadband transformer provides a single-ended interface
at the RF input with simple off-chip L-C matching. In addition, the LTC5585 provides four analog control voltage
interface pins for IIP2 and DC offset correction, greatly
simplifying system calibration.
n
The high linearity of the LTC5585 provides excellent spurfree dynamic range for the receiver. This direct conversion
demodulator can eliminate the need for intermediate frequency (IF) signal processing, as well as the corresponding
requirements for image filtering and IF filtering. These
I/Q outputs can interface directly to channel-select filters
(LPFs) or to baseband amplifiers.
APPLICATIONS
n
n
n
n
n
LTE/W-CDMA/TD-SCDMA Base Station Receivers
Wideband DPD Receivers
Point-To-Point Broadband Radios
High Linearity Direct Conversion I/Q Receivers
Image Rejection Receivers
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
Direct Conversion Receiver with IIP2 and DC Offset Calibration
5V
LNA
BPF
RF
INPUT RF
VCC
I+
LPF
VGA
I–
IIP2 vs IP2I, IP2Q Trim Voltage
A/D
120
IP2 AND DC
OFFSET CAL
LO INPUT
LO
IP2 ADJUST
90°
D/A
100
DC OFFSET
D/A
0°
LTC5585
IP2 AND DC
OFFSET CAL
D/A
DC OFFSET
EN
Q+
Q–
LPF
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
fRF = 700MHz
90
80
70
60
IP2 ADJUST
D/A
ENABLE
I, –40°C
I, 25°C
I, 85°C
I, 105°C
110
IIP2 (dBm)
BPF
50
40
VGA
A/D
5585 TA01a
For more information www.linear.com/LTC5585
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
IP2I, IP2Q (V)
5585 G09
5585fb
1
LTC5585
PIN CONFIGURATION
VCC Supply Voltage.................................... –0.3V to 5.5V
VCAP Voltage..................................................VCC ±0.05V
I–, I+, Q+, Q –, CMI, CMQ Voltage.........2.5V to VCC + 0.3V
Voltage on Any Other Pin..................–0.3V to VCC + 0.3V
LO+, LO –, RF Input Power.....................................20dBm
RF Input DC Voltage................................................ ±0.1V
Maximum Junction Temperature (TJMAX).............. 150°C
Operating Temperature Range (TC)......... –40°C to 105°C
Storage Temperature Range................... –65°C to 150°C
CMI
Q–
Q+
I–
I+
REF
TOP VIEW
24 23 22 21 20 19
IP2Q 1
18 CMQ
DCOQ 2
17 VCAP
DCOI 3
16 LO–
25
GND
IP2I 4
15 LO+
RF 5
14 GND
GND 6
13 GND
EIP2
EDC
9 10 11 12
VCC
8
VBIAS
7
EN
(Note 1)
GND
ABSOLUTE MAXIMUM RATINGS
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
TJMAX = 150°C, θJC = 7°C/W
EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC5585IUF#PBF
LTC5585IUF#TRPBF
5585
24-Lead (4mm x 4mm) Plastic QFN
–40°C to 105°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL
CHARACTERISTICS
TC = 25°C, VCC = 5V, EN = 5V, EDC = EIP2 = 0V, REF = IP2I = IP2Q = DCOI =
DCOQ = 0.5V, PRF = –5dBm (–5dBm/tone for 2-tone IIP2 and IIP3 tests), PLO = 6dBm, unless otherwise noted. (Notes 2, 3, 5, 6, 9)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
fRF(RANGE)
RF Input Frequency Range
(Note 12)
0.4 to 4.0
MAX
UNITS
GHz
fLO(RANGE)
LO Input Frequency Range
(Note 12)
0.4 to 4.0
GHz
PLO(RANGE)
LO Input Power Range
(Note 12)
0 to 10
dBm
fRF1 = 700MHz, fRF2 = 701MHz, fLO = 690MHz, L6 = 2.7pF, C19 = 1.0pF, L5 = 12nH, C14 = 5.6pF
fRF(MATCH)
RF Input Frequency Range
Return Loss > 10dB
680 to 870
MHz
fLO(MATCH)
LO Input Frequency Range
Return Loss > 10dB
690 to 820
MHz
GV
Voltage Conversion Gain
Loaded with 100Ω Pull-Up (Note 8)
2.0
dB
NF
Noise Figure
Double-Side Band (Note 4)
13.5
dB
NFBLOCKING
Noise Figure Under Blocking Conditions
Double-Side Band, PRF = 0dBm (Note 7)
15.5
dB
IIP3
Input 3rd Order Intercept
IIP2
Input 2nd Order Intercept
Unadjusted, EIP2 = 0V
IIP2OPT
Optimized Input 2nd Order Intercept
EIP2 = 5V, IP2I, IP2Q Adjusted for Minimum IM2
P1dB
Input 1dB Compression
28.7
dBm
70
dBm
80
dBm
16
dBm
5585fb
2
For more information www.linear.com/LTC5585
LTC5585
ELECTRICAL
CHARACTERISTICS
TC = 25°C, VCC = 5V, EN = 5V, EDC = EIP2 = 0V, REF = IP2I = IP2Q = DCOI =
DCOQ = 0.5V, PRF = –5dBm (–5dBm/tone for 2-tone IIP2 and IIP3 tests), PLO = 6dBm, unless otherwise noted. (Notes 2, 3, 5, 6, 9)
SYMBOL
PARAMETER
CONDITIONS
DCOFFSET
DC Offset at I/Q Outputs
Unadjusted, EDC = 0V (Note 13)
MIN
TYP
4
MAX
UNITS
mV
∆G
I/Q Gain Mismatch
0.05
dB
∆φ
I/Q Phase Mismatch
0.3
Deg
IRR
Image Rejection Ratio
48
dB
(Note 10)
LO-RF
LO to RF Leakage
–64
dBm
RF-LO
RF to LO Isolation
60
dB
fRF1 = 1950MHz, fRF2 = 1951MHz, fLO = 1940MHz, L6 = 1.2pF, C19 = 5.1nH, L5 = 1.0pF, C13 = 5.1nH
fRF(MATCH)
RF Input Frequency Range
Return Loss > 10dB
1.6 to 2.1
GHz
fLO(MATCH)
LO Input Frequency Range
Return Loss > 10dB
1.85 to 2.05
GHz
GV
Voltage Conversion Gain
Loaded with 100Ω Pull-Up (Note 8)
2.4
dB
NF
Noise Figure
Double-Side Band (Note 4)
12.7
dB
IIP3
Input 3rd Order Intercept
25.7
dBm
IIP2
Input 2nd Order Intercept
Unadjusted, EIP2 = 0V
60
dBm
IIP2OPT
Optimized Input 2nd Order Intercept
EIP2 = 5V, IP2I, IP2Q Adjusted for Minimum IM2
80
dBm
16
dBm
7
mV
0.05
dB
0.7
Deg
43
dB
P1dB
Input 1dB Compression
DCOFFSET
DC Offset at I/Q Outputs
∆G
I/Q Gain Mismatch
∆φ
I/Q Phase Mismatch
IRR
Image Rejection Ratio
Unadjusted, EDC = 0V (Note 13)
(Note 10)
LO-RF
LO to RF Leakage
–49
dBm
RF-LO
RF to LO Isolation
58
dB
fRF1 = 2150MHz, fRF2 = 2151MHz, fLO = 2140MHz, C17 = 1.5pF, L6 = 4.7nH, C19 = 0.5pF, L5 = 5.1nH, C14 = 0.7pF
fRF(MATCH)
RF Input Frequency Range
Return Loss > 10dB
2.03 to 2.36
GHz
fLO(MATCH)
LO Input Frequency Range
Return Loss > 10dB
2.05 to 2.18
GHz
GV
Voltage Conversion Gain
Loaded with 100Ω Pull-Up (Note 8)
2.3
dB
NF
Noise Figure
Double-Side Band (Note 4)
13.0
dB
NFBLOCKING
Noise Figure Under Blocking Conditions
Double-Side Band, PRF = 0dBm (Note 7)
14.6
dB
IIP3
Input 3rd Order Intercept
25.9
dBm
IIP2
Input 2nd Order Intercept
Unadjusted, EIP2 = 0V
56
dBm
IIP2OPT
Optimized Input 2nd Order Intercept
EIP2 = 5V, IP2I, IP2Q Adjusted for Minimum IM2
80
dBm
P1dB
Input 1dB Compression
15
dBm
DCOFFSET
DC Offset at I/Q Outputs
6
mV
Unadjusted, EDC = 0V (Note 13)
∆G
I/Q Gain Mismatch
0.05
dB
∆φ
I/Q Phase Mismatch
1.0
Deg
IRR
Image Rejection Ratio
40
dB
(Note 10)
LO-RF
LO to RF Leakage
–50
dBm
RF-LO
RF to LO Isolation
60
dB
fRF1 = 2600MHz, fRF2 = 2601MHz, fLO = 2590MHz, C17 = 0.5pF, L6 = 2.7nH, L5 = 1.2nH, C14 = 1pF
fRF(MATCH)
RF Input Frequency Range
Return Loss > 10dB
2.35 to 3.1
GHz
fLO(MATCH)
LO Input Frequency Range
Return Loss > 10dB
2.47 to 2.65
GHz
GV
Voltage Conversion Gain
Loaded with 100Ω Pull-Up (Note 8)
2.3
dB
5585fb
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3
LTC5585
ELECTRICAL
CHARACTERISTICS
TC = 25°C, VCC = 5V, EN = 5V, EDC = EIP2 = 0V, REF = IP2I = IP2Q = DCOI =
DCOQ = 0.5V, PRF = –5dBm (–5dBm/tone for 2-tone IIP2 and IIP3 tests), PLO = 6dBm, unless otherwise noted. (Notes 2, 3, 5, 6, 9)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NF
Noise Figure
Double-Side Band (Note 4)
13.6
dB
NFBLOCKING
Noise Figure Under Blocking Conditions
Double-Side Band, PRF = 0dBm (Note 7)
15.2
dB
IIP3
Input 3rd Order Intercept
27.5
dBm
IIP2
Input 2nd Order Intercept
Unadjusted, EIP2 = 0V
60
dBm
IIP2OPT
Minimum Input 2nd Order Intercept
EIP2 = 5V, IP2I, IP2Q Adjusted for Minimum IM2
80
dBm
P1dB
Input 1dB Compression
15.5
dBm
DCOFFSET
DC Offset at I/Q Outputs
8
mV
Unadjusted, EDC = 0V (Note 13)
∆G
I/Q Gain Mismatch
0.05
dB
∆φ
I/Q Phase Mismatch
1.0
Deg
IRR
Image Rejection Ratio
40
dB
(Note 10)
LO-RF
LO to RF Leakage
–46
dBm
RF-LO
RF to LO Isolation
55
dB
fRF1 = 3500MHz, fRF2 = 3501MHz, fLO = 3490MHz, C17 = 0.6pF, L6 = 1.0nH, C13 = 0.7pF, L5 = Short, C14 = Open, Single-Ended LO (See Figure 14)
fRF(MATCH)
RF Input Frequency Range
Return Loss > 10dB
2.88 to 3.97
GHz
fLO(MATCH)
LO Input Frequency Range
Return Loss > 10dB
2.97 to 3.96
GHz
GV
Voltage Conversion Gain
Loaded with 100Ω Pull-Up (Note 8)
0.3
dB
NF
Noise Figure
Double-Side Band (Note 4)
17.1
dB
IIP3
Input 3rd Order Intercept
28.1
dBm
IIP2
Input 2nd Order Intercept
Unadjusted, EIP2 = 0V
52.5
dBm
IIP2OPT
Minimum Input 2nd Order Intercept
EIP2 = 5V, IP2I, IP2Q Adjusted for Minimum IM2
65.9
dBm
17.1
dBm
16.5
mV
0.04
dB
1.8
Deg
36
dB
P1dB
Input 1dB Compression
DCOFFSET
DC Offset at I/Q Outputs
∆G
I/Q Gain Mismatch
Unadjusted, EDC = 0V (Note 13)
∆φ
I/Q Phase Mismatch
IRR
Image Rejection Ratio
LO-RF
LO to RF Leakage
–34.7
dBm
RF-LO
RF to LO Isolation
44.5
dB
(Note 10)
Power Supply and Other Parameters
VCC
Supply Voltage
4.75
5.0
5.25
V
ICC
Supply Current
EDC = EIP2 = 5V
180
200
220
mA
ICC(LOW)
Supply Current
EDC = EIP2 = 0V
170
190
210
mA
900
μA
ICC(OFF)
Shutdown Current
EN < 0.3V
11
tON
Turn-On Time
EN Transition from Logic Low to High (Note 14)
0.2
µs
tOFF
Turn-Off Time
EN Transition from Logic High to Low (Note 15)
0.8
µs
VEH
EN, EDC, EIP2 Input High Voltage (On)
VEL
EN, EDC, EIP2 Input Low Voltage (Off)
IENH
EN Pin Input Current
EN = 5.0V
52
μA
IEDCH
EDC Pin Input Current
EDC = 5.0V
33
μA
2.0
V
0.3
V
5585fb
4
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LTC5585
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
IEIP2H
EIP2 Pin Input Current
EIP2 = 5.0V
MIN
VREF
REF Pin Voltage
With REF Pin Unloaded
VREF(RANGE)
REF Pin Voltage Range
When Driven with External Source
ZREF
REF Input Impedance
(Note 11)
DCOI, DCOQ, IP2I, IP2Q Pin Voltage
Unloaded
DCOI, DCOQ, IP2I, IP2Q Voltage Range
When Driven with External Source
TYP
MAX
UNITS
50
μA
0.5
V
0.4 to 0.7
V
2||1
kΩ||pF
0.5
V
0 to 2VREF
V
DCOI, DCOQ, IP2I, IP2Q Impedance
(Note 11)
8||1
kΩ||pF
DCOI, DCOQ, IP2I, IP2Q Settling Time
For Step Input, Output with 90% of Final Value
20
ns
DC Offset Adjustment Range
DCOI, DCOQ Swept from 0V to 1V, EDC = 5V
±20
mV
DC Offset Drift Over Temperature
Unadjusted, EDC = 0V
20
μV/°C
VCM
I+, I–, Q+, Q– Common Mode Voltage
ZOUT
I+, I–, Q+, Q– Output Impedance
Single Ended
BWBB
I+, I–, Q+, Q– Output Bandwidth
100Ω External Pull-Up, –3dB Corner Frequency
VCC – 1.5
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Tests are performed with the test circuit of Figure 1.
Note 3: The LTC5585 is guaranteed to be functional over the –40°C to
105°C case temperature operating range.
Note 4: DSB noise figure is measured at the baseband frequency of 15MHz
with a small-signal noise source without any filtering on the RF input and
no other RF signal applied.
Note 5: Performance at the RF frequencies listed is measured with external
RF and LO impedance matching, as shown in the table of Figure 1.
Note 6: The complementary outputs (I+, I– and Q+, Q–) are combined
using a 180° phase-shift combiner.
Note 7: Noise figure under blocking conditions (NFBLOCKING) is measured
at an output frequency of 60MHz with RF input signal at fLO + 1MHz. Both
RF and LO input signals are appropriately filtered, as well as the baseband
output. NFBLOCKING measured at 840MHz, 2140MHz and 2500MHz only.
V
100||6
Ω||pF
530
MHz
Note 8: Voltage conversion gain is calculated from the average measured
power conversion gain of the I and Q outputs using the test circuit shown
in Figure 1. Power conversion gain is measured with a 100Ω differential
load impedance on the I and Q outputs.
Note 9: Baseband outputs have a 100Ω external pull-up resistor to VCC as
shown in the test circuit shown in Figure 1.
Note 10: Image rejection is calculated from the measured gain error and
phase error using the method listed in the appendix.
Note 11: The DCOI, DCOQ, IP2I, IP2Q pins have an 8k internal resistor to
ground. The REF pin has a 2k internal resistor to ground. If unconnected,
these pins will float up to 500mV through internal current sources. A low
output resistance voltage source is recommended for driving these pins.
Note 12: This is the recommended operating range, operation outside the
listed range is possible with degraded performance to some parameters.
Note 13: DC offset measured differentially between I+ and I– and between
Q+ and Q–. The reported value is the mean of the absolute values of the
characterization data distribution.
Note 14: Baseband amplitude is within 10% of final value.
Note 15: Baseband amplitude is at least 30dB down from its on state.
5585fb
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5
LTC5585
DC PERFORMANCE CHARACTERISTICS EN = 5V, EDC = 0V and EIP2 = 0V. Test circuit shown in Figure 1
Supply Current vs Supply Voltage
260
TC = –40°C
TC = 25°C
TC = 85°C
TC = 105°C
250
240
230
540
220
210
200
190
535
530
525
520
515
180
510
170
505
160
4.75
VCC = 4.75V
VCC = 5V
VCC = 5.25V
545
REF VOLTAGE (mV)
SUPPLY CURRENT (mA)
REF Voltage vs Temperature
550
500
–40
5.25
5
SUPPLY VOLTAGE (V)
–20
40
20
0
60
TEMPERATURE (°C)
5585 G01
80
100
5585 G02
TYPICAL PERFORMANCE CHARACTERISTICS
700MHz application. VCC = 5V, EN = 5V, EDC = 0V,
EIP2 = 0V, REF = 0.5V, TC = 25°C, PLO = 6dBm, fLO = 690MHz, fRF1 = 700MHz, fRF2 = 701MHz, fBB = 10MHz, PRF1 = PRF2 = –5dBm,
DC Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement unless otherwise noted.
Test circuit with RF and LO ports impedance matched as in Figure 1.
IIP3, P1dB vs Temperature (TC)
46
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
42
38
34
IIP3
30
26
22
18
IIP3, P1dB vs Supply Voltage (VCC)
46
IIP3, P1dB (dBm)
IIP3, P1dB (dBm)
42
I, –40°C
I, 25°C
I, 85°C
I, 105°C
50
P1dB
I, 4.75V
I, 5.0V
I, 5.25V
Q, 4.75V
Q, 5.0V
Q, 5.25V
IIP3 vs LO Power
50
TC = 25°C
46
42
38
38
34
34
30
IIP3 (dBm)
50
IIP3
26
22
18
22
P1dB
18
14
14
10
600
10
600
5585 G03
TC = 25°C
26
14
1000
Q, 0dBm
Q, 6dBm
Q, 10dBm
30
10
600
800
700
900
LO FREQUENCY (MHz)
I, 0dBm
I, 6dBm
I, 10dBm
800
700
900
LO FREQUENCY (MHz)
1000
5585 G04
800
700
900
LO FREQUENCY (MHz)
1000
5585 G05
5585fb
6
For more information www.linear.com/LTC5585
LTC5585
700MHz
application. VCC = 5V, EN = 5V, EDC = 0V,
TYPICAL
PERFORMANCE CHARACTERISTICS
EIP2 = 0V, REF = 0.5V, TC = 25°C, PLO = 6dBm, fLO = 690MHz, fRF1 = 700MHz, fRF2 = 701MHz, fBB = 10MHz, PRF1 = PRF2 = –5dBm,
DC Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement unless otherwise noted.
Test circuit with RF and LO ports impedance matched as in Figure 1.
Uncalibrated IIP2 vs Temperature
(TC)
I, –40°C
I, 25°C
I, 85°C
I, 105°C
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
120
fRF1 = 700MHz
fRF2 = 701MHz
fLO = 690MHz
I, –40°C
I, 25°C
I, 85°C
I, 105°C
110
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
100
–8
–6
–2
–4
0
RF POWER (dBm)
2
80
60
60
50
600
700
800
900
LO FREQUENCY (MHz)
100
TC = 25°C
95
fRF1 = 700MHz
90 fLO = 690MHz
85
80
fRF = 700MHz
80
70
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
IP2I, IP2Q (V)
90
85
75
70
65
60
55
40
50
0
50
100 150 200 250 300 350 400
RF TONE SPACING (MHz)
GAIN, NF (dB)
NF
1000
5585 G12
0
50
100 150 200 250 300 350 400
RF TO LO TONE SPACING (MHz)
5585 G10
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
800
900
700
LO FREQUENCY (MHz)
I
70
5585 G11
Noise Figure and Conversion
Gain vs LO Power
GAIN
Q
75
45
24
22
20
18
16
14
12
10
8
6
4
2
0
–2
–4
600
I, 0dBm
I, 6dBm
I, 10dBm
Q, 0dBm
Q, 6dBm
Q, 10dBm
Noise Figure vs RF Power and
IP2I, IP2Q Trim Voltage
20
TC = 25°C
I, –20dBm
I, 0dBm
19
NF
GAIN
17
16
15
14
13
TC = 25°C
fRF = 890MHz
fLO = 900MHz
fNOISE = 3.4MHz
EIP2 = 5V
12
11
800
900
700
LO FREQUENCY (MHz)
Q, –20dBm
Q, 0dBm
18
DSB NOISE FIGURE (dB)
I, –40°C
I, 25°C
I, 85°C
I, 105°C
80
65
5585 G09
Noise Figure and Conversion
Gain vs Temperature (TC)
1000
TC = 25°C
fLO = 690MHz
95
50
50
GAIN, NF (dB)
100
I (UNCALIBRATED)
I (NULLED AT 1MHz)
Q (UNCALIBRATED)
Q (NULLED AT 1MHz)
60
24
22
20
18
16
14
12
10
8
6
4
2
0
–2
–4
600
800
900
LO FREQUENCY (MHz)
5585 G08
55
60
0
700
2x2 Half-IF IIP2
vs RF to LO Tone Spacing
IIP2 vs RF Tone Spacing
90
40
50
600
1000
5585 G07
IIP2 (dBm)
IIP2 (dBm)
100
80
70
IIP2 (dBm)
110
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
90
70
IIP2 vs IP2I, IP2Q Trim Voltage
I, –40°C
I, 25°C
I, 85°C
I, 105°C
TC = 25°C
Q, 0dBm
Q, 6dBm
Q, 10dBm
100
90
4
I, 0dBm
I, 6dBm
I, 10dBm
110
5585 G06
120
Uncalibrated IIP2 vs LO Power
120
IIP2 (dBm)
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
–10
IIP2 (dBm)
IIP3 (dBm)
2-Tone IIP3 vs RF Power
1000
5585 G13
10
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
IP2I, IP2Q TRIM VOLTAGE (V)
5585 G14
5585fb
For more information www.linear.com/LTC5585
7
LTC5585
application. VCC = 5V, EN = 5V, EDC = 0V,
700MHz
TYPICAL
PERFORMANCE CHARACTERISTICS
EIP2 = 0V, REF = 0.5V, TC = 25°C, PLO = 6dBm, fLO = 690MHz, fRF1 = 700MHz, fRF2 = 701MHz, fBB = 10MHz, PRF1 = PRF2 = –5dBm,
DC Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement unless otherwise noted.
Test circuit with RF and LO ports impedance matched as in Figure 1.
10
5585 G15
DC OFFSET (mV)
10
40
I, –40°C
f = 700MHz
35 LO
I, 25°C
I, 85°C
30
I, 105°C
25
20
15
10
5
0
–5
–10
–15
–20
–25
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
DCOI, DCOQ (V)
LO to RF Leakage and RF to LO
Isolation
5585 G18
–30
L-R, –40°C
R-L, –40°C
–35
L-R, 25°C
R-L, 25°C
–40
L-R, 85°C
R-L, 85°C
L-R, 105°C
R-L, 105°C
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
600 650 700 750 800 850 900 950 1000
LO FREQUENCY (MHz)
LEAKAGE (dBm), –ISOLATION (dB)
10
I, 0dBm
Q, 0dBm
TC = 25°C
9
I, 6dBm
Q, 6dBm
8
I, 10dBm
Q, 10dBm
7
6
5
4
3
2
1
0
–1
–2
–3
–4
–5
600 650 700 750 800 850 900 950 1000
LO FREQUENCY (MHz)
5585 G19
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
0.8 0.9 1.0
5585 G17
5585 G16
DC Offset vs LO Power
DC OFFSET (mV)
25
PLO = 0dBm
24
PLO = 6dBm
23
PLO = 10dBm
22 T = 25°C
C
21 fLO = 900MHz
20 fRF = 890MHz
19 fNOISE = 3.4MHz
18
17
16
15
14
13
12
11
10
0
–20
–5
5
–15
–10
RF INPUT POWER (dBm)
DC Offset vs DCOI, DCOQ Control
Voltage
Image Rejection vs Temperature
(Note 10)
100
90
IMAGE REJECTION (dB)
25
PLO = 0dBm
24
PLO = 6dBm
23
PLO = 10dBm
22 T = 25°C
C
21 fLO = 840MHz
20 fRF = 841MHz
19 fNOISE = 60MHz
18
17
16
15
14
13
12
11
10
0
–20
–5
5
–15
–10
RF INPUT POWER (dBm)
Noise Figure vs RF Input Power
with fNOISE = 3.4MHz
DSB NOISE FIGURE (dB)
DSB NOISE FIGURE (dB)
Noise Figure vs RF Input Power
with fNOISE = 60MHz
80
TC = –40°C
TC = 25°C
TC = 85°C
TC = 105°C
70
60
50
40
30
20
600 650 700 750 800 850 900 950 1000
LO FREQUENCY (MHz)
5585 G20
5585fb
8
For more information www.linear.com/LTC5585
LTC5585
TYPICAL PERFORMANCE CHARACTERISTICS
1950MHz application. VCC = 5V, EN = 5V, EDC = 0V,
REF = 0.5V, EIP2 = 0V, TC = 25°C, PLO = 6dBm, fLO = 1940MHz, fRF1 = 1950MHz, fRF2 = 1951MHz, fBB = 10MHz, PRF1 = PRF2 = –5dBm,
DC Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement unless otherwise noted.
Test circuit with RF and LO ports impedance matched as in Figure 1.
IIP3, P1dB vs Temperature (TC)
I, –40°C
I, 25°C
I, 85°C
I, 105°C
46
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
42
38
34
IIP3
30
26
22
18
I, 4.75V
I, 5.0V
I, 5.25V
46
IIP3, P1dB (dBm)
IIP3, P1dB (dBm)
42
IIP3, P1dB vs Supply Voltage
50
34
IIP3
26
TC = 25°C
Q, 0dBm
Q, 6dBm
Q, 10dBm
30
26
22
22
18
P1dB
14
14
14
10
1500 1600 1700 1800 1900 2000 2100 2200
LO FREQUENCY (MHz)
10
1500 1600 1700 1800 1900 2000 2100 2200
LO FREQUENCY (MHz)
10
1500 1600 1700 1800 1900 2000 2100 2200
LO FREQUENCY (MHz)
Uncalibrated IIP2 vs Temperature
(TC)
130
I, –40°C
I, 25°C
I, 85°C
I, 105°C
120
110
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
2
IIP2 (dBm)
80
70
60
60
50
50
40
1500 1600 1700 1800 1900 2000 2100 2200
LO FREQUENCY (MHz)
40
1500 1600 1700 1800 1900 2000 2100 2200
LO FREQUENCY (MHz)
75
70
65
5585 G27
40
80
75
70
I
60
Q
55
45
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
IP2I, IP2Q (V)
90
65
50
0
TC = 25°C
fLO = 1940MHz
95
85
55
50
100
I (UNCALIBRATED)
I (NULLED AT 1MHz)
Q (UNCALIBRATED)
Q (NULLED AT 1MHz)
60
60
40
2x2 Half-IF IIP2
vs RF to LO Tone Spacing
IIP2 (dBm)
IIP2 (dBm)
70
5585 G26
IIP2 vs RF Tone Spacing
100
T = 25°C
95 C
fRF1 = 1950MHz
90 fLO = 1940MHz
85
80
80
80
5585 G25
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
90
TC = 25°C
90
70
IIP2 vs IP2I, IP2Q Trim Voltage
I, –40°C
I, 25°C
110
I, 85°C
I, 105°C
100 f = 1950MHz
RF
Q, 0dBm
Q, 6dBm
Q, 10dBm
110
90
4
I, 0dBm
I, 6dBm
I, 10dBm
120
100
5585 G24
120
Uncalibrated IIP2 vs LO Power
130
100
IIP2 (dBm)
50
I, –40°C
Q, –40°C
48
I, 25°C
Q, 25°C
46
I, 85°C
Q, 85°C
44
I, 105°C
Q, 105°C
42 fRF1 = 1950MHz
40 fRF2 = 1951MHz
38 fLO = 1940MHz
36
34
32
30
28
26
24
22
20
–2
–10 –8
–4
0
–6
RF POWER (dBm)
5585 G23
5585 G22
2-Tone IIP3 vs RF Power
IIP3 (dBm)
42
38
30
I, 0dBm
I, 6dBm
I, 10dBm
46
34
5585 G21
IIP2 (dBm)
TC = 25°C
38
18
P1dB
Q, 4.75V
Q, 5.0V
Q, 5.25V
IIP3 vs LO Power
50
IIP3 (dBm)
50
0
50
100 150 200 250 300 350 400
RF TONE SPACING (MHz)
5585 G28
50
0
50
100 150 200 250 300 350 400
RF TO LO TONE SPACING (MHz)
5585 G29
5585fb
For more information www.linear.com/LTC5585
9
LTC5585
TYPICAL PERFORMANCE CHARACTERISTICS
1950MHz application. VCC = 5V, EN = 5V, EDC = 0V,
REF = 0.5V, EIP2 = 0V, TC = 25°C, PLO = 6dBm, fLO = 1940MHz, fRF1 = 1950MHz, fRF2 = 1951MHz, fBB = 10MHz, PRF1 = PRF2 = –5dBm,
DC Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement unless otherwise noted.
Test circuit with RF and LO ports impedance matched as in Figure 1.
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
NF
GAIN
1600 1700 1800 1900 2000 2100 2200
LO FREQUENCY (MHz)
24
22
20
18
16
14
12
10
8
6
4
2
0
–2
–4
1500
I, 0dBm
I, 6dBm
I, 10dBm
Q, 0dBm
Q, 6dBm
Q, 10dBm
TC = 25°C
DC OFFSET (mV)
I, –40°C
I, 25°C
I, 85°C
I, 105°C
NF
GAIN
1600 1700 1800 1900 2000 2100 2200
LO FREQUENCY (MHz)
5585 G30
2.2
3.0
2.6
2.8
CONVERSION GAIN (dB)
2.4
LEAKAGE (dBm), –ISOLATION (dB)
DC OFFSET (mV)
60
50
40
30
20
1500 1600 1700 1800 1900 2000 2100 2200
LO FREQUENCY (MHz)
5585 G35
80
70
60
50
40
30
20
3.2
5585 G36
0
TC = –40°C
TC = 25°C
TC = 85°C
TC = 105°C
90
PERCENTAGE DISTRIBUTION (%)
PERCENTAGE DISTRIBUTION (%)
PERCENTAGE DISTRIBUTION (%)
70
IIP3 Distribution, Q Side
10
2
80
100
TC = –40°C
TC = 25°C
TC = 85°C
TC = 105°C
90
10
TC = –40°C
TC = 25°C
TC = 85°C
TC = 105°C
90
IIP3 Distribution, I Side
100
20
0
100
5585 G34
Conversion Gain Distribution
30
0.8 0.9 1.0
Image Rejection vs Temperature
(Note 10)
–20
L-R, –40°C
R-L, –40°C
–25
L-R, 25°C
R-L, 25°C
–30
L-R, 85°C
R-L, 85°C
L-R, 105°C
R-L, 105°C
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
1500 1600 1700 1800 1900 2000 2100 2200
LO FREQUENCY (MHz)
5585 G33
TC = –40°C
TC = 25°C
TC = 85°C
TC = 105°C
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
5585 G32
LO to RF Leakage and RF to LO
Isolation
15
TC = 25°C
I, 0dBm
Q, 0dBm
14
I, 6dBm
Q, 6dBm
13
I, 10dBm
Q, 10dBm
12
11
10
9
8
7
6
5
4
3
2
1
0
1500 1600 1700 1800 1900 2000 2100 2200
LO FREQUENCY (MHz)
40
40
I, –40°C
f = 1950MHz
35 LO
I, 25°C
I, 85°C
30
I, 105°C
25
20
15
10
5
0
–5
–10
–15
–20
–25
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
DCOI, DCOQ (V)
5585 G31
DC Offset vs LO Power
50
DC Offset vs DCOI, DCOQ Control
Voltage
IMAGE REJECTION (dB)
24
22
20
18
16
14
12
10
8
6
4
2
0
–2
–4
1500
Noise Figure and Conversion
Gain vs LO Power
GAIN, NF (dB)
GAIN, NF (dB)
Noise Figure and Conversion
Gain vs Temperature (TC)
80
70
60
50
40
30
20
10
20
22
24
26
28
IIP3 (dBm)
30
32
5585 G37
0
20
22
24
26
28
IIP3 (dBm)
30
32
5585 G38
5585fb
10
For more information www.linear.com/LTC5585
LTC5585
TYPICAL PERFORMANCE CHARACTERISTICS
1950MHz application. VCC = 5V, EN = 5V, EDC = 0V,
REF = 0.5V, EIP2 = 0V, TC = 25°C, PLO = 6dBm, fLO = 1940MHz, fRF1 = 1950MHz, fRF2 = 1951MHz, fBB = 10MHz, PRF1 = PRF2 = –5dBm,
DC Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement unless otherwise noted.
Test circuit with RF and LO ports impedance matched as in Figure 1.
TC = –40°C
TC = 25°C
TC = 85°C
TC = 105°C
80
70
60
50
40
30
20
80
70
60
50
40
30
20
100
14
15
16
13
DSB NOISE FIGURE (dB)
17
0
12
11
14
15
16
13
DSB NOISE FIGURE (dB)
5585 G39
IIP2 Distribution, Q Side
100
80
70
60
50
40
30
20
70
75
80
85
90
IIP2 (dBm)
40
30
20
0
17
70
75
80
95
50
30
20
10
0
100
–0.1
–0.06
0.06
–0.02 0.02
GAIN ERROR (dB)
0.1
5585 G43
Image Rejection Distribution
(Note 10)
50
TC = –40°C
TC = 25°C
TC = 85°C
TC = 105°C
20
10
–1
100
40
Phase Error Distribution
0
95
TC = –40°C
TC = 25°C
TC = 85°C
TC = 105°C
60
5585 G42
30
85
90
IIP2 (dBm)
5585 G41
70
10
0
60
50
Gain Error Distribution
TC = –40°C
TC = 25°C
TC = 85°C
TC = 105°C
90
70
5585 G40
PERCENTAGE DISTRIBUTION (%)
12
80
10
PERCENTAGE DISTRIBUTION (%)
11
TC = –40°C
TC = 25°C
TC = 85°C
TC = 105°C
90
10
PERCENTAGE DISTRIBUTION (%)
0
IIP2 Distribution, I Side
TC = –40°C
TC = 25°C
TC = 85°C
TC = 105°C
90
10
PERCENTAGE DISTRIBUTION (%)
PERCENTAGE DISTRIBUTION (%)
90
100
PERCENTAGE DISTRIBUTION (%)
100
DSB Noise Figure Distribution,
Q Side
PERCENTAGE DISTRIBUTION (%)
DSB Noise Figure Distribution,
I Side
–0.4
–0.2
–0.6
–0.8
PHASE ERROR (DEGREES)
0
TC = –40°C
TC = 25°C
TC = 85°C
TC = 105°C
40
30
20
10
0
40 42.5 45 47.5 50 52.5 55 57.5 60
IMAGE REJECTION (dB)
5585 G44
5585 G45
5585fb
For more information www.linear.com/LTC5585
11
LTC5585
TYPICAL PERFORMANCE CHARACTERISTICS
2150MHz application. VCC = 5V, EN = 5V,
EDC = 0V, EIP2 = 0V, REF = 0.5V, TC = 25°C, PLO = 6dBm, fLO = 2140MHz, fRF1 = 2150MHz, fRF2 = 2151MHz, fBB = 10MHz,
PRF1 = PRF2 = –5dBm, DC Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement
unless otherwise noted. Test circuit with RF and LO ports impedance matched as in Figure 1.
IIP3, P1dB vs Supply Voltage
(VCC)
IIP3, P1dB vs Temperature (TC)
I, –40°C
I, 25°C
I, 85°C
I, 105°C
46
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
42
38
34
IIP3
30
26
22
P1dB
18
I, 4.75V
I, 5.0V
I, 5.25V
46
IIP3, P1dB (dBm)
IIP3, P1dB (dBm)
42
50
Q, 4.75V
Q, 5.0V
Q, 5.25V
I, 0dBm
I, 6dBm
I, 10dBm
46
42
TC = 25°C
Q, 0dBm
Q, 6dBm
Q, 10dBm
38
34
IIP3
30
26
34
30
26
22
22
18
P1dB
18
14
14
14
10
1750 1850 1950 2050 2150 2250 2350 2450 2550
LO FREQUENCY (MHz)
10
1750 1850 1950 2050 2150 2250 2350 2450 2550
LO FREQUENCY (MHz)
10
1750 1850 1950 2050 2150 2250 2350 2450 2550
LO FREQUENCY (MHz)
Uncalibrated IIP2 vs Temperature
(TC)
130
I, –40°C
I, 25°C
I, 85°C
I, 105°C
120
110
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
2
4
100
IIP2 (dBm)
70
70
60
50
50
40
1750 1850 1950 2050 2150 2250 2350 2450 2550
LO FREQUENCY (MHz)
40
1750 1850 1950 2050 2150 2250 2350 2450 2550
LO FREQUENCY (MHz)
40
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
IP2I, IP2Q (V)
5585 G52
TC = 25°C
fLO = 2140MHz
95
90
85
IIP2 (dBm)
75
70
65
80
Q
75
70
65
I
60
50
0
100
I (UNCALIBRATED)
I (NULLED AT 1MHz)
Q (UNCALIBRATED)
Q (NULLED AT 1MHz)
55
50
5585 G51
2x2 Half-IF IIP2
vs RF to LO Tone Spacing
60
60
80
IIP2 vs RF Tone Spacing
IIP2 (dBm)
70
90
60
100
TC = 25°C
95
fRF1 = 2150MHz
90 fLO = 2140MHz
85
80
80
TC = 25°C
5585 G50
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
90
Q, 0dBm
Q, 6dBm
Q, 10dBm
110
80
IIP2 vs IP2I, IP2Q Trim Voltage
I, –40°C
I, 25°C
110
I, 85°C
I, 105°C
100 f = 2150MHz
RF
I, 0dBm
I, 6dBm
I, 10dBm
120
90
5585 G49
120
Uncalibrated IIP2 vs LO Power
130
100
IIP2 (dBm)
50
I, –40°C
Q, –40°C
48
I, 25°C
Q, 25°C
46
I, 85°C
Q, 85°C
44
I, 105°C
Q, 105°C
42 f
RF1 = 2150MHz
40 fRF2 = 2151MHz
38 fLO = 2140MHz
36
34
32
30
28
26
24
22
20
–2
–10 –8
–4
0
–6
RF POWER (dBm)
5585 G48
5585 G47
2-Tone IIP3 vs RF Power
IIP3 (dBm)
TC = 25°C
38
5585 G46
IIP2 (dBm)
IIP3 vs LO Power
50
IIP3 (dBm)
50
45
55
40
50
0
50
100 150 200 250 300 350 400
RF TONE SPACING (MHz)
5585 G53
0
50
100 150 200 250 300 350 400
RF TO LO TONE SPACING (MHz)
5585 G54
5585fb
12
For more information www.linear.com/LTC5585
LTC5585
TYPICAL PERFORMANCE CHARACTERISTICS
2150MHz application. VCC = 5V, EN = 5V,
EDC = 0V, EIP2 = 0V, REF = 0.5V, TC = 25°C, PLO = 6dBm, fLO = 2140MHz, fRF1 = 2150MHz, fRF2 = 2151MHz, fBB = 10MHz,
PRF1 = PRF2 = –5dBm, DC Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement
unless otherwise noted. Test circuit with RF and LO ports impedance matched as in Figure 1.
Noise Figure and Conversion
Gain vs Temperature (TC)
10
24
22
20
18
16
14
12
10
8
6
4
2
0
–2
–4
1750
I, –40°C
I, 25°C
I, 85°C
I, 105°C
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
NF
GAIN
1850 1950 2050 2150 2250 2350 2450 2550
LO FREQUENCY (MHz)
5585 G55
5585 G57
DC Offset vs LO Power
15
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
I, 0dBm
I, 6dBm
I, 10dBm
13
11
DC OFFSET (mV)
DC OFFSET (mV)
24
I, 0dBm
Q, 0dBm
TC = 25°C
22
I, 6dBm
Q, 6dBm
20
I, 10dBm
Q, 10dBm
18
16
NF
14
12
10
8
6
GAIN
4
2
0
–2
–4
1750 1850 1950 2050 2150 2250 2350 2450 2550
LO FREQUENCY (MHz)
5585 G56
DC Offset vs DCOI, DCOQ Control
Voltage
40
I, –40°C
f = 2150MHz
35 LO
I, 25°C
I, 85°C
30
I, 105°C
25
20
15
10
5
0
–5
–10
–15
–20
–25
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
DCOI, DCOQ (V)
Noise Figure and Conversion
Gain vs LO Power
GAIN, NF (dB)
GAIN, NF (dB)
25
PLO = 0dBm
24
PLO = 6dBm
23
PLO = 10dBm
22 T = 25°C
C
21 fLO = 2140MHz
20 fRF = 2141MHz
19 fNOISE = 60MHz
18
17
16
15
14
13
12
11
10
0
–20
–5
5
–15
–10
RF INPUT POWER (dBm)
Q, 0dBm
Q, 6dBm
Q, 10dBm
TC = 25°C
9
7
5
3
1
–1
–3
–5
1750 1850 1950 2050 2150 2250 2350 2450 2550
LO FREQUENCY (MHz)
0.8 0.9 1.0
5585 G59
5585 G58
LO to RF Leakage and RF to LO
Isolation
–20
L-R, –40°C
R-L, –40°C
–25
L-R, 25°C
R-L, 25°C
–30
L-R, 85°C
R-L, 85°C
L-R, 105°C
R-L, 105°C
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
1750 1850 1950 2050 2150 2250 2350 2450 2550
LO FREQUENCY (MHz)
Image Rejection vs Temperature
(Note 10)
100
90
IMAGE REJECTION (dB)
LEAKAGE (dBm), –ISOLATION (dB)
DSB NOISE FIGURE (dB)
Noise Figure vs RF Input Power
80
TC = –40°C
TC = 25°C
TC = 85°C
TC = 105°C
70
60
50
40
30
20
1750 1850 1950 2050 2150 2250 2350 2450 2550
LO FREQUENCY (MHz)
5585 G60
5585 G61
5585fb
For more information www.linear.com/LTC5585
13
LTC5585
TYPICAL PERFORMANCE CHARACTERISTICS
2600MHz application. VCC = 5V, EN = 5V, EDC = 0V,
EIP2 = 0V, REF = 0.5V, TC = 25°C, PLO = 6dBm, fLO = 2590MHz, fRF1 = 2600MHz, fRF2 = 2601MHz, fBB = 10MHz, PRF1 = PRF2 = –5dBm,
DC Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement unless otherwise noted.
Test circuit with RF and LO ports impedance matched as in Figure 1.
IIP3, P1dB vs Temperature (TC)
I, –40°C
I, 25°C
I, 85°C
I, 105°C
46
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
IIP3
30
26
22
18
38
I, 0dBm
I, 6dBm
I, 10dBm
46
42
Q, 0dBm
Q, 6dBm
Q, 10dBm
TC = 25°C
38
26
22
34
30
26
22
P1dB
18
14
14
14
10
2200 2300 2400 2500 2600 2700 2800 2900 3000
LO FREQUENCY (MHz)
10
2200 2300 2400 2500 2600 2700 2800 2900 3000
LO FREQUENCY (MHz)
10
2200 2300 2400 2500 2600 2700 2800 2900 3000
LO FREQUENCY (MHz)
5585 G63
130
I, –40°C
I, 25°C
I, 85°C
I, 105°C
120
110
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
2
4
IIP2 (dBm)
80
70
60
60
50
50
40
2200 2300 2400 2500 2600 2700 2800 2900 3000
LO FREQUENCY (MHz)
40
2200 2300 2400 2500 2600 2700 2800 2900 3000
LO FREQUENCY (MHz)
40
75
70
65
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
IP2I, IP2Q (V)
5585 G68
80
75
70
60
50
0
90
65
55
50
TC = 25°C
fLO = 2590MHz
95
85
60
60
100
I (UNCALIBRATED)
I (NULLED AT 1MHz)
Q (UNCALIBRATED)
Q (NULLED AT 1MHz)
IIP2 (dBm)
70
5585 G66
2x2 Half-IF IIP2 vs RF to LO Tone
Spacing
IIP2 vs RF Tone Spacing
IIP2 (dBm)
80
80
70
100
TC = 25°C
95
fRF1 = 2600MHz
90 fLO = 2590MHz
85
80
90
TC = 25°C
90
5585 G66
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
Q, 0dBm
Q, 6dBm
Q, 10dBm
110
90
IIP2 vs IP2I, IP2Q Trim Voltage
I, –40°C
I, 25°C
110
I, 85°C
I, 105°C
100 f = 2600MHz
RF
I, 0dBm
I, 6dBm
I, 10dBm
120
100
5585 G65
120
Uncalibrated IIP2 vs LO Power
130
100
IIP2 (dBm)
50
I, –40°C
Q, –40°C
48
I, 25°C
Q, 25°C
46
I, 85°C
Q, 85°C
44
I, 105°C
Q, 105°C
42 fRF1 = 2600MHz
40 fRF2 = 2601MHz
38 fLO = 2590MHz
36
34
32
30
28
26
24
22
20
–2
–10 –8
–4
0
–6
RF POWER (dBm)
5585 G64
Uncalibrated IIP2 vs Temperature
(TC)
2-Tone IIP3 vs RF Power
IIP2 (dBm)
TC = 25°C
30
18
P1dB
Q, 4.75V
Q, 5.0V
Q, 5.25V
IIP3 vs LO Power
50
IIP3
34
5585 G62
IIP3 (dBm)
I, 4.75V
I, 5.0V
I, 5.25V
42
38
34
IIP3, P1dB vs Supply Voltage (VCC)
46
IIP3, P1dB (dBm)
IIP3, P1dB (dBm)
42
50
IIP3 (dBm)
50
45
55
40
50
0
50
100 150 200 250 300 350 400
RF TONE SPACING (MHz)
5585 G69
I
Q
0
50
100 150 200 250 300 350 400
RF TO LO TONE SPACING (MHz)
5585 G70
5585fb
14
For more information www.linear.com/LTC5585
LTC5585
TYPICAL PERFORMANCE CHARACTERISTICS
2600MHz application. VCC = 5V, EN = 5V, EDC = 0V,
EIP2 = 0V, REF = 0.5V, TC = 25°C, PLO = 6dBm, fLO = 2590MHz, fRF1 = 2600MHz, fRF2 = 2601MHz, fBB = 10MHz, PRF1 = PRF2 = –5dBm,
DC Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement unless otherwise noted.
Test circuit with RF and LO ports impedance matched as in Figure 1.
I, –40°C
I, 25°C
I, 85°C
I, 105°C
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
NF
GAIN
2300 2400 2500 2600 2700 2800 2900 3000
LO FREQUENCY (MHz)
24
22
20
18
16
14
12
10
8
6
4
2
0
–2
–4
2200
I, 0dBm
I, 6dBm
I, 10dBm
NF
GAIN
17
16
15
14
13
TC = 25°C
fRF = 2501MHz
fLO = 2500MHz
fNOISE = 60MHz
EIP2 = 5V
12
11
10
2300 2400 2500 2600 2700 2800 2900 3000
LO FREQUENCY (MHz)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
IP2I, IP2Q TRIM VOLTAGE (V)
5585 G73
DC Offset vs DCOI, DCOQ Control
Voltage
DC Offset vs LO Power
15
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
13
11
DC OFFSET (mV)
DC OFFSET (mV)
40
I, –40°C
f = 2600MHz
35 LO
I, 25°C
I, 85°C
30
I, 105°C
25
20
15
10
5
0
–5
–10
–15
–20
–25
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
DCOI, DCOQ (V)
I, 0dBm
I, 6dBm
I, 10dBm
Q, 0dBm
Q, 6dBm
Q, 10dBm
9
7
5
3
1
–3
0.8 0.9 1.0
–5
2200
2600
2400
2800
LO FREQUENCY (MHz)
5585 G75
LO to RF Leakage and RF to LO
Isolation
3000
5585 G76
Image Rejection vs Temperature
(Note 10)
100
90
IMAGE REJECTION (dB)
–10
L-R, –40°C
R-L, –40°C
–15
L-R, 25°C
R-L, 25°C
–20
L-R, 85°C
R-L, 85°C
L-R, 105°C
R-L, 105°C
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
2200 2300 2400 2500 2600 2700 2800 2900 3000
LO FREQUENCY (MHz)
TC = 25°C
–1
5585 G74
LEAKAGE (dBm), –ISOLATION (dB)
DSB NOISE FIGURE (dB)
Q, –20dBm
Q, 0dBm
5585 G72
Noise Figure vs RF Input Power
10
I, –20dBm
I, 0dBm
19
18
5585 G71
25
PLO = 0dBm
24
PLO = 6dBm
23
PLO = 10dBm
22 T = 25°C
C
21 fLO = 2500MHz
20 fRF = 2501MHz
19 fNOISE = 60MHz
18
17
16
15
14
13
12
11
10
0
–20
–5
5
–15
–10
RF INPUT POWER (dBm)
20
TC = 25°C
Q, 0dBm
Q, 6dBm
Q, 10dBm
DSB NOISE FIGURE (dB)
24
22
20
18
16
14
12
10
8
6
4
2
0
–2
–4
2200
Noise Figure vs RF Power and
IP2I, IP2Q Trim Voltage
Noise Figure and Conversion
Gain vs LO Power
GAIN, NF (dB)
GAIN, NF (dB)
Noise Figure and Conversion
Gain vs Temperature (TC)
80
TC = –40°C
TC = 25°C
TC = 85°C
TC = 105°C
70
60
50
40
30
20
2200 2300 2400 2500 2600 2700 2800 2900 3000
LO FREQUENCY (MHz)
5585 G77
5585 G78
5585fb
For more information www.linear.com/LTC5585
15
LTC5585
PIN FUNCTIONS
IP2Q, IP2I (Pin 1, Pin 4): IIP2 Adjustment Analog Control
Voltage Input for Q and I Channel. A decoupling capacitor
is recommended on this pin. A low output resistance voltage source is recommended for driving these pins. These
pins should be left floating if unused.
DCOQ, DCOI (Pin 2, Pin 3): DC Offset Analog Control
Voltage Input for Q and I Channel. A decoupling capacitor is recommended on this pin. A low output resistance
voltage source is recommended for driving these pins.
These pins should be left floating if unused.
RF (Pin 5): RF Input. External matching is used to obtain
good return loss across the RF input frequency range.
The RF pin is internally shorted to ground through internal
transformer windings. The RF pin should be DC-blocked
with a 1000pF coupling capacitor.
GND (Pins 6, 8, 13, 14, Exposed Pad Pin 25): Ground.
These pins must be soldered to the RF ground plane on
the circuit board. The backside exposed pad ground connection should have a low inductance connection and
good thermal contact to the printed circuit board ground
plane using many through-hole vias. See Figures 2 and 3.
EN (Pin 7): Enable Pin. When the voltage on the EN pin
is a logic high, the chip is completely turned on; the chip
is completely turned off for a logic low. An internal 200k
pull-down resistor ensures the chip remains disabled if
there is no connection to the pin (open-circuit condition).
VBIAS (Pin 9): This pin can be pulled to ground through
a resistor to lower the current consumption of the chip.
See Applications Information.
VCC (Pin 10): Positive Supply Pin. This pin should be
bypassed with shunt 1000pF and 1µF capacitors.
EDC (Pin 11): DC Offset Adjustment Mode Enable Pin.
When the voltage on the EDC pin is a logic high, the DC
offset control circuitry is enabled. The circuitry is disabled
for a logic low. An internal 200k pull-down resistor ensures
the circuitry remains disabled if there is no connection to
the pin (open-circuit condition).
EIP2 (Pin 12): IP2 Offset Adjustment Mode Enable Pin.
When the voltage on the EIP2 pin is a logic high, the IP2
adjustment circuitry is enabled. The circuitry is disabled
for a logic low. An internal 200k pull-down resistor ensures
the circuitry remains disabled if there is no connection to
the pin (open-circuit condition).
LO+,LO– (Pin 15, Pin 16): LO Inputs. External matching
is required to obtain good return loss across the LO input
frequency range. Can be driven single ended or differentially with an external transformer. The LO pins should be
DC-blocked with a 1000pF coupling capacitor.
VCAP, CMQ, CMI (Pin 17, Pin 18, Pin 19): Common Mode
Bypass Capacitor Pins. It is recommended that CMI and
CMQ be connected to VCAP through 0.1µF capacitors.
Nothing else should be connected to VCAP since it is connected to VCC inside the chip.
I+, I–, Q+, Q– (Pin 23, Pin 22, Pin 21, Pin 20): Differential
Baseband Output Pins for the I Channel and Q Channel.
The DC bias point is VCC – 1.5V for each pin. These pins
must have an external 100Ω or an inductor pull-up to VCC.
REF (Pin 24): Voltage Reference Input for Analog Control
Voltage Pins. A decoupling capacitor is recommended
on this pin. A low output resistance voltage source is
recommended for driving this pin. This pin should be left
floating if unused.
5585fb
16
For more information www.linear.com/LTC5585
LTC5585
BLOCK DIAGRAM
10
VCC
5
6
17
VCAP
CMI
I+
RF
I–
16
0°
LO–
7
IP2I
EIP2
90°
REF
VBIAS
EN
DCOI
EDC
LO+
IP2 AND DC
OFFSET CAL
9
23
22
GND
IP2 AND DC
OFFSET CAL
15
19
IP2Q
DCOQ
Q+
Q–
BIAS
CMQ
GND
8
GND
13
GND
14
EXPOSED
PAD
25
3
4
11
12
24
1
2
21
20
18
5585 BD
5585fb
For more information www.linear.com/LTC5585
17
LTC5585
TEST CIRCUIT
RF
GND
0.015"
0.062"
DC
GND
NELCO N4000-13
0.015"
C29
R11
R9
C21
C22
R13
C30
R14
I– OUT
Q+ OUT
I+ OUT
Q– OUT
C10
REF
C33
C35
C34
5
6
C18
RF
CMI
Q–
Q+
LO–
LTC5585IUF
IP2I
LO+
RF
GND
L6
C17
I–
REF
DCOI
C19
7
8
9
EIP2
C32
VCAP
EDC
4
IP2I
CMQ
DCOQ
VCC
3
DCOI
IP2Q
VBIAS
2
GND
IP2Q
DCOQ
EN
1
I+
24 23 22 21 20 19
C31
18
C11
C36
17
16
C37
15
14
2
6
4
5
C12
L5
3 T1 1
LO
C13 C14
GND
13
GND
25
GND
10 11 12
EIP2
EDC
EN
C15
C16
VCC
4.75V TO 5.25V
5585 F01
RF MATCH
FREQUENCY RANGE
C17
700MHz
1950MHz
REF DES
LO MATCH
L6
C19
2.7pF
1.0pF
1.2pF
5.1nH
2150MHz
1.5pF
4.7nH
0.5pF
2600MHz
0.5pF
2.7nH
VALUE
SIZE
VENDOR
C13
5.1nH
L5
C14
12nH
5.6pF
1.0pF
5.1nH
0.7pF
1.2nH
1pF
REF DES
VALUE
SIZE
VENDOR
C10, C11, C31-C35
0.1μF
0402
Murata
L5, L6
See Table
0402
Murata
C12, C15, C18, C36, C37
1000pF
0402
Murata
R9, R11, R13, R14
100Ω
0402
Vishay
C13, C14, C17, C19
See Table
0402
Murata
T1
4:1
0805
Anaren
BD0826J50200A00
C16, C21, C22, C29, C30
1μF
0402
Murata
Figure 1. Test Circuit Schematic
5585fb
18
For more information www.linear.com/LTC5585
LTC5585
TEST CIRCUIT
Figure 2. Component Side of Evaluation Board
Figure 3. Bottom Side of Evaluation Board
APPLICATIONS INFORMATION
The LTC5585 is an IQ demodulator designed for high
dynamic range receiver applications. It consists of RF
transconductance amplifiers, I/Q mixers, quadrature LO
amplifiers, IIP2 and DC offset correction circuitry, and
bias circuitry.
Operation
As shown in the Block Diagram for the LTC5585, the RF
signal is applied to the inputs of the RF transconductor
V-to-I converters and is then demodulated into I/Q
baseband signals using quadrature LO signals which are
internally generated by a precision 90° phase shifter. The
demodulated I/Q signals are lowpass filtered on-chip with
a –3dB bandwidth of 530MHz. The differential outputs of
the I-channel and Q-channel are well matched in amplitude
and their phases are 90° apart.
RF Input Port
Figure 4 shows the demodulator’s RF input which consists
of an integrated transformer and high linearity transconductance amplifiers (V-I converters). The primary side
of the transformer is connected to the RF input pin. The
secondary side of the transformer is connected to the
RF
INPUT
(MATCHED)
C18
1000pF
LTC5585
BIAS
RF
L6
C17
C19
5585 F04
GND
Figure 4: Simplified Schematic of the RF Pin Interface
5585fb
For more information www.linear.com/LTC5585
19
LTC5585
APPLICATIONS INFORMATION
differential inputs of the transconductance amplifiers.
External DC voltage should not be applied to the RF input
pin. DC current flowing into the primary side of the transformer may cause damage to the integrated transformer.
A series DC blocking capacitor should be used to couple
the RF input pin to the RF signal source.
The RF input port can be externally matched over the
operating frequency range with simple L-C matching. An
input return loss better than 10dB can be obtained over a
bandwidth of better than 16% with this method. Figure 5
shows the RF input return loss for various matching component values. Table 1 shows the impedance and input
reflection coefficient for the RF input without using any
external matching components. The input transmission
line length is de-embedded from the measurement.
5
TC = 25°C
RETURN LOSS (dB)
0
–5
–10
Table 1. RF Input Impedance
FREQUENCY
(MHz)
400
600
800
1000
1200
1400
1600
1800
2000
2200
2400
2600
2800
3000
3200
3400
3600
3800
4000
INPUT IMPEDANCE (Ω)
6.98 + j25.09
10.43 + j39.74
16.76 + j56.73
28.55 + j77.15
51.47 + j101.03
96.49 + j122.28
171.91 + j112.37
229.92 + j30.89
202.21 – j58.84
145.32 – j91.23
104.82 – j91.69
78.33 – j83.38
61.86 – j73.64
51.27 – j64.65
43.83 – j56.56
38.86 – j49.72
35.17 – j43.6
32.46 – j38.21
30.48 – j33.41
MAG
0.800
0.775
0.751
0.727
0.706
0.686
0.667
0.648
0.630
0.612
0.594
0.575
0.557
0.538
0.519
0.500
0.481
0.463
0.444
S11
ANGLE (°)
125.98
101.55
80.01
61.05
44.29
29.33
15.81
3.45
–8.00
–18.71
–28.49
–38.22
–47.49
–56.32
–65.15
–73.40
–81.68
–89.79
–97.76
–15
–20
RF INPUT
1500MHz TO
2200MHz
–25
–30
0 0.5 1
1.5 2 2.5 3 3.5 4
FREQUENCY (GHz)
C18
L7
1000pF 3.9nH
LTC5585
BIAS
RF
L6
8.2nH
C17
1.2pF
C19
0.5pF
4.5 5
5585 F05
L6 = 2.7pF, C19 = 1pF
L6 = 1.2pF, C19 = 5.1nH
C17 = 1.5pF, L6 = 4.7nH, C19 = 0.5pF
C17 = 0.5pF, L6 = 2.7nH
5585 F06
GND
Figure 6. Wide Bandwidth RF Input Match
Figure 5. RF Input Return Loss
0
Broadband Performance
–5
RETURN LOSS (dB)
Larger bandwidths can be obtained by using multiple L-C
sections. For example Figure 6 shows a 2-section L-C
match having a bandwidth of about 38% where return
loss is >10dB. Figure 7 shows the RF input return loss
for the wide bandwidth match.
–10
–15
To get an idea of the broadband performance of the
LTC5585, a 6dB pad can be put on the RF and LO ports,
and the ports can be left unmatched. The measured RF
performance for this configuration is shown in Figures 8,
9, 10 and 11 with the 6dB pad de-embedded. The RF
–20
TC = 25°C
L7 = 3.9nH, C17 = 1.2pF
L6 = 8.2nH, C19 = 0.5pF
0
0.5
1
1.5
2 2.5 3
FREQUENCY (GHz)
3.5
4
5585 F07
Figure 7. RF Input Return Loss for Wideband Match
5585fb
20
For more information www.linear.com/LTC5585
LTC5585
APPLICATIONS INFORMATION
50
46
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
38
34
GAIN, NF (dB)
IIP3, P1dB (dBm)
42
I, –40°C
I, 25°C
I, 85°C
I, 105°C
IIP3
30
26
22
18
P1dB
14
10
400
900 1400 1900 2400 2900 3400 3900
LO FREQUENCY (MHz)
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0
–2
–4
I, –40°C
I, 25°C
I, 85°C
I, 105°C
NF
GAIN
900 1400 1900 2400 2900 3400 3900
LO FREQUENCY (MHz)
5585 F08
5585 F10
Figure 8. Broadband IIP3 and IP1dB
120
110
I, –40°C
I, 25°C
I, 85°C
I, 105°C
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
IIP2 (dBm)
100
90
80
70
60
50
100
90
80
TC = –40°C
TC = 25°C
TC = 85°C
TC = 105°C
70
60
50
40
30
40
30
400
Figure 10. Broadband NF and Gain
IMAGE REJECTION (dB)
130
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
900 1400 1900 2400 2900 3400 3900
LO FREQUENCY (MHz)
20
500 1000 1500 2000 2500 3000 3500 4000
LO FREQUENCY (MHz)
5585 F11
5585 F09
Figure 9. Broadband IIP2
Figure 11. Broadband Image Rejection
tone spacing is 1MHz, and fLO is 10MHz lower than fRF.
The conversion gain is lower than under the impedance
matched condition, and correspondingly the P1dB, IIP3,
and NF are higher. As shown, the part can be used at
frequencies outside its specified operating range with
reduced conversion gain and higher NF.
The differential LO input impedance and S parameters with
the input transmission lines and balun de-embedded are
listed in Table 2.
LO Input Port
For optimum IIP2 and large-signal NF performance the LO
inputs should be driven differentially with a 4:1 balun such
as the ANAREN BD0826J50200A00 or BD2425J50200AHF.
As shown in Figure 14, the LO input can also be driven
single-ended from either the LO+ or LO– input. The unused
port should be DC-blocked and terminated with a 50Ω load.
Figure 15 compares the uncalibrated IIP2 performance of
single ended versus differential LO drive.
The demodulator’s LO input interface is shown in Figure 12. The input consists of a high precision quadrature
phase shifter which generates 0° and 90° phase shifted
LO signals for the LO buffer amplifiers to drive the I/Q
mixers. DC blocking capacitors are required on the LO+
and LO– inputs.
Figure 13 shows LO input return loss using the ANAREN
BD0826J50200A00 4:1 balun with various matching
component values.
5585fb
For more information www.linear.com/LTC5585
21
LTC5585
APPLICATIONS INFORMATION
VCC
LTC5585
LO
INPUT
(MATCHED)
L5
ANAREN
BD0826J50200A00
C14
C37
1000pF
TO IDENTICAL
Q-CHANNEL
LO+
C13
LO–
PHASE SHIFTER
C36
1000pF
5585 F12
GND
Figure 12. Simplified Schematic of LO Input Interface with External Matching Components
Table 2. LO Input Impedance (Differential)
5
S11
INPUT IMPEDANCE (Ω)
MAG
ANGLE (°)
0
400
118.18 – j120.02
0.668
–24.89
–5
600
94.18 – j99.93
0.623
–31.42
800
78.00 – j85.06
0.583
–38.17
1000
67.21 – j73.16
0.544
–44.79
1200
59.71 – j63.49
0.507
–51.25
1400
54.22 – j55.46
0.471
–57.63
1600
50.06 – j48.59
0.437
–64.02
1800
46.80 – j42.69
0.405
–70.49
2000
44.10 – j37.42
0.374
–77.28
2200
41.86 – j32.61
0.345
–84.47
2400
39.98 – j28.16
0.317
–92.21
2600
38.39 – j23.98
0.291
–100.65
2800
37.05 – j20.01
0.267
–109.95
3000
35.92 – j16.21
0.246
–120.29
3200
34.99 – j12.53
0.228
–131.76
3400
34.22 – j8.95
0.214
–144.37
3600
33.61 – j5.45
0.206
–157.88
3800
33.15 – j2.0
0.204
–171.85
4000
32.82 + j1.4
0.208
174.35
RETURN LOSS (dB)
FREQUENCY
(MHz)
–10
–15
–20
L5 = 12nH, C14 = 5.6pF
C13 = 5.1nH, L5 = 1.0pF
L5 = 5.1nH, C14 = 0.7pF
L5 = 1.2nH, C14 = 1pF
–25
–30
0 0.5 1
1.5 2 2.5 3 3.5 4
FREQUENCY (GHz)
4.5 5
5585 F13
Figure 13. LO Input Return Loss
5585fb
22
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LTC5585
APPLICATIONS INFORMATION
VCC
LTC5585
LO
INPUT
(MATCHED)
C37
1000pF
L5
C13
50Ω
C14
TO IDENTICAL
Q-CHANNEL
LO+
LO–
PHASE SHIFTER
C36
1000pF
5585 F14
GND
Figure 14. Recommended Single-Ended LO Input Configuration
100
TC = 25°C
90
IIP2 (dBm)
80
70
60
50
current sources are required. Each single-ended output
has an impedance of 100Ω in parallel with a 6pF internal
capacitor. With an external 100Ω pull-up resistor this
forms a lowpass filter with a –3dB corner frequency at
530MHz. The outputs can be DC coupled or AC coupled
to external loads. The voltage conversion gain is reduced
by the external load by:
40
30
400
900 1400 1900 2400 2900 3400 3900
5585 F15
LO FREQUENCY (MHz)
SINGLE-ENDED LO, I SIDE
DIFFERENTIAL LO, I SIDE
SINGLE-ENDED LO, Q SIDE
DIFFERENTIAL LO, Q SIDE
Figure 15. Broadband IIP2 with Differential
and Single-Ended LO Drive
I-Channel and Q-Channel Outputs
The phase relationship between the I-channel output
signal and the Q-channel output signal is fixed. When the
LO input frequency is higher (or lower) than the RF input
frequency, the Q-channel outputs (Q+, Q–) lag (or lead)
the I-channel outputs (I+, I–) by 90°.
Each of the I-channel and Q-channel outputs is internally
connected to VCC through a 100Ω resistor. In order to
maintain an output DC bias voltage of VCC – 1.5V, external 100Ω pull-up resistors or equivalent 15mA DC
1

50Ω
20Log10  +
 dB
 2 RPULL-UP ||RLOAD(SE) 
when the output port is terminated by RLOAD(SE). For instance, the gain is reduced by 6dB when each output pin is
connected to a 50Ω load (or 100Ω differentially). The output
should be taken differentially (or by using differential-tosingle-ended conversion) for best RF performance, including NF and IIP2. When no external filtering or matching
components are used, the output response is determined
by the loading capacitance and the total resistance loading
the outputs. The –3dB corner frequency, fC, is given by
the following equation:
fC = [2π(RLOAD(SE)||100Ω||RPULL-UP) (6pF)]–1
Figure 16 shows the actual measured output response
with various load resistances.
Figure 17 shows a simplified model of the I, Q outputs
with a 100Ω differential load and 100Ω pull-ups. The –1dB
bandwidth in this configuration is about 520MHz, or about
twice the –1dB bandwidth with no load.
5585fb
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23
LTC5585
CONVERSION GAIN (dB)
APPLICATIONS INFORMATION
Figure 18 shows a simplified model of the I, Q outputs
with a L-C matching network for bandwidth extension.
Capacitor CS serves to filter common mode LO switching
noise immediately at the demodulator outputs. Capacitor
CC in combination with inductor LS is used to peak the
output response to give greater bandwidth of 650MHz. In
this case, capacitor CC was chosen as a common mode
capacitor instead of a differential mode capacitor to increase
rejection of common mode LO switching noise.
5
4 TC = 25°C
3
2
1
0
–1
–2
–3
–4
–5
–6
RLOAD(DIFF) = 100Ω, BW = 850MHz
–7
RLOAD(DIFF) = 200Ω, BW = 630MHz
–8
RLOAD(DIFF) = 400Ω, BW = 530MHz
–9
RLOAD(DIFF) = 1k, BW = 460MHz
–10
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
BASEBAND FREQUENCY (GHz) 5585 G16
When AC output coupling is used, the resulting highpass
filter’s –3dB roll-off frequency, fC, is defined by the R-C
constant of the external AC coupling capacitance, CAC, and
the differential load resistance, RLOAD(DIFF):
Figure 16. Conversion Gain Baseband Output Response with
RLOAD(DIFF) = 100Ω, 200Ω, 400Ω and 1k and RPULL-UP = 100Ω
fC = [2π • RLOAD(DIFF) • CAC]–1
VCC
VCC
LTC5585
6pF
100Ω
100Ω
1k
30mA
AC CURRENT
SOURCE
PACKAGE
PARASITICS
6pF
1.5nH
I+
1.5nH
I–
0.2pF
0.2pF
RPULL-UP
100Ω
RPULL-UP
100Ω
RLOAD(DIFF)
100Ω
–1dB BW = 520MHz
30mA
5585 F17
GND
Figure 17. Simplified Model of the Baseband Output
VCC
VCC
LTC5585
6pF
100Ω
100Ω
1k
30mA DC
AC CURRENT
SOURCE
6pF
PACKAGE
PARASITICS
1.5nF
I+
1.5nF
I–
0.2pF
0.2pF
30mA DC
CS
2pF
LS
10nH
CC
4pF
LS
10nH
CS
2pF
RPULL-UP
100Ω
RPULL-UP
100Ω
RLOAD(DIFF)
100Ω
CC
4pF
LOWPASS
–1dB BW = 650MHz
5585 F18
GND
Figure 18. Simplified Model of the Baseband Output Showing Bandwidth Extension with External L, C Matching
5585fb
24
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LTC5585
APPLICATIONS INFORMATION
Care should be taken when the demodulator’s outputs
are DC coupled to the external load to make sure that the
I/Q mixers are biased properly. If the current drain from
the outputs exceeds about 6mA, there can be significant
degradation of the linearity performance. Keeping the common mode output voltage of the demodulator above 3.15V,
with a 5V supply, will ensure optimum performance. Each
output can sink no more than 30mA when the outputs are
connected to an external load with a DC voltage higher
than VCC – 1.5V.
In order to achieve the best IIP2 performance, it is important to minimize high frequency coupling among the
baseband outputs, RF port, and LO port. Although it may
increase layout complexity, routing the baseband output
traces on the backside of the PCB can improve uncalibrated
IIP2 performance. Figure 19 shows the alternate layout
having the baseband outputs on the backside of the PCB.
As shown in Figure 21, the REF pin is similar to the DCOI
pin, but the bias current source is 250µA, and the internal resistance is 2k. If this pin is left disconnected, it will
self-bias to 500mV. A low impedance voltage source with
a source resistance of less than 200Ω is recommended
to drive this pin. The control voltage range of the DCOI,
DCOQ, IP2I and IP2Q pins is set by the REF pin. This range
is equal to 0V to twice the voltage on the REF pin, whether
internally or externally applied.
It is recommended to decouple any AC noise present on
the signal lines that connect to the analog control-voltage
inputs. A shunt capacitor to ground placed close to these
pins can provide adequate filtering. For instance, a value
of 1000pF on the DCOI, DCOQ, IP2I and IP2Q pins will
provide a corner frequency of around 6 to 7MHz. A similar
corner frequency can be obtained on the REF pin with a
value of 3900pF. Using larger capacitance values such as
0.1µF is recommended on these pins unless a faster control
VCC
LTC5585
62.5µA
DCOI, DCOQ,
IP2I, IP2Q
8k
5585 F20
GND
Figure 20. Simplified Schematic of the Interface for the
DCOI, DCOQ, IP2I and IP2Q Pins
VCC
Figure 19. Alternate Layout of PCB with
Baseband Outputs on the Backside
LTC5585
Analog Control Voltage Pins
250µA
Figure 20 shows the equivalent circuit for the DCOI, DCOQ,
IP2I, and IP2Q pins. Internal temperature compensated
62.5μA current sources keep these pins biased at a nominal
500mV through 8k resistors. A low impedance voltage
source with a source resistance of less than 200Ω is
recommended to drive these pins.
REF
2k
5585 F21
GND
Figure 21. Simplified Schematic of the REF Pin Interface
5585fb
For more information www.linear.com/LTC5585
25
LTC5585
APPLICATIONS INFORMATION
response is needed. Figure 22 shows the input response
–3dB bandwidth for the pins versus shunt capacitance
when driven from a 50Ω source.
0
TC = 25°C
–1
RESPONSE (dB)
–2
–3
–4
–5
–6
–7
–8
DCOI, DCOQ; C = 470pF
DCOI, DCOQ; C = 1000pF
IP2I, IP2Q; C = 1000pF
–9
–10
0
2
4
6 8 10 12 14 16 18 20
5585 F22
FREQUENCY (MHz)
Figure 22. Input Response Bandwidth for the
DCOI, DCOQ, IP2I and IP2Q Pins
DC Offset Adjustment Circuitry
Any sources of LO leakage to the RF input of a direct
conversion receiver will contribute to the DC offsets of
its baseband outputs. The LTC5585 features DC offset
adjustment circuitry to reduce such effects. When the
EDC pin is a logic high the circuitry is enabled and the
resulting DC offset adjustment range is typically ±20mV.
In a typical direct conversion receiver application, DC
offset calibration will be done periodically at a time when
no receive data is present and when the receiver DC levels
have sufficiently settled.
DC Offset Adjustment Example
Figure 23 shows a typical direct conversion receive path
having a DSP feedback path for DC offset adjustment.
Any sources of LO leakage to the RF input of the LTC5585
demodulator will contribute to the DC offset of the receiver.
This includes both static and dynamic DC offsets. If the
coupling is static in nature due to fixed board-level leakage
paths, the resulting DC offset does not typically need to
be adjusted at a high repetition rate. Dynamic DC offsets
due to transmitter transient leakage or antenna reflection
can be much harder to correct for and will require a faster
update rate from the DSP.
LO leakage into the RF port of the demodulator causes a
DC offset at the baseband outputs which is then multiplied
by the gain in the baseband path. The usable ADC voltage
window will be reduced by the amplified DC offset, resulting in lower dynamic range. Using DSP, this DC offset
value can be averaged and sampled at a given update
rate and then a 1D minimization algorithm can be applied
before a new DCOI or DCOQ control signal is generated to
minimize the offset. The 1-D minimization algorithm can
be implemented in many ways such as golden-section
search, backtracking, or Newton’s method.
IM2 Adjustment Circuitry
The LTC5585 also contains circuitry for the independent
adjustment of IM2 levels on the I and Q channels. When
the EIP2 pin is a logic high, this circuitry is enabled and
the IP2I and IP2Q analog control voltage inputs are able
DSP
DAC
DCOI
BPF
LNA
DC
AVERAGING
LOWPASS
FILTER
ADC
1-D
MINIMIZATION
ALGORITHM
SAMPLE AND
HOLD
LTC5585
fLO = 1950MHz
5585 F23
Figure 23. Block Diagram of a Receiver with a DSP Feedback Loop for DC Offset Adjustment
5585fb
26
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LTC5585
APPLICATIONS INFORMATION
Figure 24 shows the CMI (and identical CMQ) pin interface.
These pins have an internal 40pF decoupling capacitance
to VCC, to provide a reference for the IP2 adjustment circuitry. The lower 3dB frequency limit, fC, of the circuitry
is set by the following equation:
fC = [2π • 500(40pF + CCM(EXT))]–1
Without any external capacitor on the CMI or CMQ pin the
lower limit is 8MHz. By adding a 0.1μF capacitor, CCM(EXT),
between the CMI and CMQ pins to VCAP, the lower –3dB
frequency corner can be reduced to 3kHz. Figure 25 shows
IIP2 as a function of RF frequency spacing versus common
mode decoupling capacitance values of 0.1µF and 1500pF.
There is effectively no limit on the size of this capacitor,
other than the impact it has on enable time for the IM2
circuitry to be operational. When the chip is disabled, there
is no current in the I or Q mixers, so the common mode
output voltage will be equal to VCC (if no DC common mode
current is being drawn by external baseband circuitry such
as a baseband amplifier). When the chip is enabled, the
off-chip common mode decoupling capacitor must charge
up through a 500Ω resistor. The time constant for this
is essentially 500Ω times the common mode decoupling
capacitance value. For example, with a 0.01µF capacitor
this wait time is approximately 30μs. Figure 26 shows
the pulsed enable response of the common-mode output
voltage with 0.01µF on the CMI and CMQ pins.
130
110
100
80
70
50
40
30
0.01
1
0.1
RF FREQUENCY SPACING (MHz)
10
5585 F25
Figure 25. IIP2 vs Common Mode Decoupling Capacitance
8
7
VCM (V)
10
TC = 25°C
CCMI,Q = 0.01µF
EN
PULSE
OFF
6
5
EN PULSE ON
0
5
–5
40pF
CMI, CMQ
4
CMI OR CMQ
3
ENABLE VOLTAGE (V)
VCAP
TC = 25°C
fRF1 = 2150MHz
fLO = 2100MHz
90
60
VCC
LTC5585
0.1µF (UNCALIBRATED)
0.1µF (NULLED IP2I = 0.1V)
1500pF (UNCALIBRATED)
1500pF (NULLED IP2I = 0.15V)
120
IIP2 (dBm)
to adjust the IM2 level. The IM2 level can be effectively
minimized over a large range of the baseband bandwidth.
The circuitry has an effective baseband frequency upper
limit of about 200MHz. Any IM2 component that falls in this
frequency range can be minimized. Beyond this frequency,
the gain of the IM2 correction amplifier falls off appreciably
and the circuit no longer improves IP2 performance. The
lower baseband frequency limit of the IM2 adjustment
circuitry is set by the common mode reference decoupling
capacitor at the CMI and CMQ pins. Below this frequency
the circuit can not minimize the IM2 component.
–10
0
5585 F24
GND
BASEBAND OUTPUTS
–15
10 20 30 40 50 60 70 80 90 100
TIME (µs)
5585 F26
Figure 24. Equivalent Circuit of the CMI and CMQ Pin Interfaces
Figure 26. Common Mode Output Voltage with a Pulsed Enable
5585fb
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27
LTC5585
APPLICATIONS INFORMATION
IM2 Suppression Example
IM2 adjustment circuitry can be used in a typical transceiver loop-back application as shown in Figure 27. In
this example a 2-tone SSB training source of f1 = 20MHz
and f2 = 21MHz is generated in DSP and upconverted
by the LTC5588-1 quadrature modulator to RF tones at
1970MHz and 1971MHz using an LO source at 1950MHz.
A narrowband RF filter is required to remove the IM2
component generated by the LTC5588-1. During the
loopback test these RF tones are routed through high
isolation switches and an attenuation pad to the LTC5585
demodulator input. The tones are then downconverted by
the same LO source at 1950MHz to produce two tones
at the baseband outputs of 20MHz and 21MHz plus an
IM2 impairment signal at 1MHz. After baseband channel filtering and amplification the output of the ADC is
filtered by a 1MHz bandpass filter in DSP to isolate the
IM2 tone. The power in this tone is calculated in DSP and
then a 1-D minimization algorithm is applied to calculate
the correction signal for the IP2I control voltage pin. The
1-D minimization algorithm can be implemented in many
ways such as golden-section search, backtracking or
Newton’s method.
Figures 29 and 30 show the simplified schematics for the
EDC and EIP2 pins
VCC
LTC5585
EN
100k
100k
5585 F28
GND
Figure 28. Simplified Schematic of the EN Pin Interface
VCC
LTC5585
EDC
100k
100k
EN
5585 F29
Enable Interface
GND
A simplified schematic of the EN pin is shown in Figure 28.
The enable voltage necessary to turn on the LTC5585 is 2V.
To disable or turn off the chip, this voltage should be below
0.3V. If the EN pin is not connected, the chip is disabled.
Figure 29. Simplified Schematic of the EDC Pin Interface
DSP
1-D
MINIMIZATION
ALGORITHM
DAC
1MHz BPF
IP2I
LNA
RMS
DETECTION
ADC
LTC5585
LOOPBACK
fLO = 1950MHz
f1 = 20MHz
DAC
PA
LTC5588-1
+
f2 = 21MHz
5585 F27
Figure 27. Block Diagram for a Direct Conversion Transceiver with IM2 Adjustment. Only the I-Channel Is Shown
5585fb
28
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LTC5585
APPLICATIONS INFORMATION
VCC
VCC
LTC5585
LTC5585
EIP2
VBIAS
100k
OPTIONAL R
TO REDUCE
CURRENT
10k
100Ω
EN
COPT
100k
5585 F30
GND
5585 F31
Figure 30. Simplified Schematic of the EIP2 Pin Interface
Reducing Power Consumption
Figure 31 shows the simplified schematic of the VBIAS
interface. The VBIAS pin can be used to lower the mixer
core bias current and total power consumption for the
chip. For example, adding 294Ω from the VBIAS pin to
GND will lower the DC current to 150mA, at the expense
of reduced IIP3 performance. Figure 32 shows IIP3 and
P1dB performance versus DC current and resistor value.
An optional capacitor, COPT in Figure 31, has minimal effect on improving PSRR and IIP2.
1950MHz Receiver Application
Figure 33 shows a typical receiver application consisting of
the chain of LNA, demodulator, lowpass filter, ADC driver,
and ADC. Total DC power consumption is about 2.1W.
Full-scale power at the RF input is -6dBm. The Chebychev
lowpass filter with unequal terminations is designed using the method shown in the appendix. Filter component
values are then adjusted for the best overall response
Figure 31. Simplified Schematic of the VBIAS Pin Interface
50
45
40
IIP3, P1dB (dBm)
It is important that the voltage applied to the EN, EDC and
EIP2 pins should never exceed VCC by more than 0.3V.
Otherwise, the supply current may be sourced through the
upper ESD protection diode connected at the pin. Under
no circumstances should voltage be applied to the enable
pins before the supply voltage is applied to the VCC pin. If
this occurs, damage to the IC may result.
GND
35
30
I, 190mA
I, 170mA, 487Ω
I, 150mA, 294Ω
TC = 25°C
fRF = 1950MHz
Q, 190mA
Q, 170mA, 487Ω
Q, 150mA, 294Ω
IIP3
25
20
15
P1dB
10
5
1500 1600 1700 1800 1900 2000 2100 2200
LO FREQUENCY (MHz)
5585 G21
Figure 32. IIP3 and P1dB vs DC Current
and VBIAS Resistor Value
and available component values. A positive voltage gain
slope with frequency is necessary to compensate for the
roll-off contributed by the ADC Driver and Anti-Alias Filter.
From the chain analysis shown in Figure 34, the IIP3-NF
dynamic range figure of merit (FOM) is 4.3dB at the LNA
input, 7.5dB at the demodulator input, and 14.85dB at the
ADC driver amp input.
The measured 6th order lowpass baseband response is
shown in Figure 35.
5585fb
For more information www.linear.com/LTC5585
29
30
RF INPUT
1910MHz
TO
1990MHz
C1
100pF
C5
100pF L2
8.2nH
C3
4.7µF
LNA
LO INPUT
1950MHz
6dBm
C2
100pF
For more information www.linear.com/LTC5585
C8
0.5pF
LO+
RF
C10
100pF
C13
150pF
L8 180nH
L6 470nH
C12
47pF
L7 180nH
C14
150pF
L5 470nH
C9
47pF
C17
1µF
T1
ANAREN BD2425J50200AHF
I–
LO–
VCC
+
LTC5585 I
5V
200mA
C15
150pF
C16
150pF
R4
110Ω
40MHz LOWPASS FILTER
C18
0.1µF
R7
30Ω
R6
30Ω
R5
110Ω
R8
440Ω
C20
0.4pF
+ –
R9
440Ω
VOCN LTC6409
– +
5V
52mA
C19
0.4pF
L9 180nH
R15
35Ω
R10
100Ω
R13
138Ω
R11
10Ω L10 180nH
R12
10Ω
R14
138Ω
R16
35Ω
C22
62pF R18
83Ω
L12 180nH
L11 180nH
C21
62pF
R17
83Ω
40MHz ANTI-ALIAS FILTER
Figure 33. Simplified Schematic of 1950MHz Receiver, (Only I-Channel Is Shown)
L4 4.7nH
C11
100pF
C7
0.5pF
C4
100pF
C6
4.7µF
L3 4.7nH
L2
8.2nH
R3
0Ω
5V
48mA
AVAGO
MGA-634P8
BIAS
R1
49.9Ω
R2
5.6k
5585 F33
R19
105Ω
R20
105Ω
C23
1µF
AIN–
VCM
AIN+
CONTROL
LTC2185
ADC
VDD
1.8V
206mA
D15
•
•
•
D0
LTC5585
APPLICATIONS INFORMATION
5585fb
LTC5585
APPLICATIONS INFORMATION
1950MHz Receiver Chain Analysis
G = 32.6dB
NF = 3.7dB
IIP3 = 8dBm
FOM = 4.3dB
G = 15.2dB
NF = 18.3dB
IIP3 = 25.8dBm
FOM = 7.5dB
MGA-634P8
G = 17.4dB
NF = 0.44dB
OIP3 = 36dBm
LTC5585
G = 21.5dB
NF = 10.85dB
IIP3 = 25.7dBm
FOM = 14.85dB
40MHz LPF
G = –6.3dB
NF = 13dB
IIP3 = 27dBm
G = –0.3dB
NF = 0.3dB
G = 21.8dB
NF = 10.55dB
IIP3 = 25.4dBm
FOM = 14.85dB
LTC6409
G = –1.2dB
NF = 24.3dB
IIP3 = 48.7dBm
FOM = 24.4dB
G = 0dB
NF = 23.1dB
IIP3 = 47.5dBm
FOM = 24.4dB
40MHz AAF
G = 23dB
NF = 10dB
OIP3 = 50dBm
G = –1.2dB
NF = 1.2dB
LTC2185
G = 0dB
NF = 23.1dB
IP3 = 47.5dBm
5585 F34
Figure 34. 1950MHz Receiver Chain Analysis
20
TC = 25°C
10
0
GAIN (dB)
–10
–20
–30
–40
–50
SNRIN = PIN – P0
–60
–70
–80
For this example, receiver noise floor is approximated
by a measurement at 845MHz, where adequate filtering
for RF and LO signals was possible. Using the test data
from Figure 37, the receiver noise figure for the I-channel
(Ch 1) is calculated using the –6dBm input power, 1875Hz
bin width, 40MHz bandwidth, and –116.3dBFS measured
in-band noise floor:
0
20
40
60 80 100 120 140 160
FREQUENCY (MHz)
5585 F35
Figure 35. Baseband Gain Response without LNA
The receiver spurious free dynamic range (SFDR) in terms
of FOM can be calculated using the following equations:
FOM = IIP3 – NF
SFDR = 2/3(FOM – P0)
SNRIN = – 6 – (–174 + 76) = 92dB
SNROUT = –10 Log10(BinW/BW) – Floor
SNROUT = –43.3 + 116.3 = 73dB
NF = SNRIN – SNROUT
NF = 92 – 73 = 19dB
Finally, an approximate receiver spurious free dynamic
range can be calculated using the measured data at
845MHz and 1910MHz:
SFDR = 2(IIP3 – NF – P0)/3
P0 = –174dBm + 10Log10(BW|Hz)
SFDR = 2(21.78 – 19 – (–174 + 76))/3
where P0 is the input noise power and –174dBm is the
input thermal noise power in a 1Hz bandwidth. A measured
2-tone output spectrum at 1910MHz is shown in Figure 36.
IIP3 is calculated from the 2-tone IM3 levels:
Measured IIP3 is 2.3dB higher for the Q-channel, so the
resulting SFDR is:
IIP3 = (–7.067 – (–76.63))/2 – 13
SFDR = 68.7dB (Q-channel)
SFDR = 67.2dB (I-channel)
IIP3 = 21.78dBm
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LTC5585
APPLICATIONS INFORMATION
Figure 36. fRF = 1909MHz and 1910MHz 2-Tone Receiver Test, fLO = 1930MHz.
Ch.1 Is the I-Channel and Ch.2 Is the Q-Channel. Tested without LNA
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LTC5585
APPLICATIONS INFORMATION
Figure 37. fRF = 845MHz Receiver Noise Floor Test, fLO = 846MHz.
Ch.1 Is the I-Channel and Ch.2 Is the Q-Channel. Tested without LNA
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33
LTC5585
APPENDIX
Chebychev Filter Synthesis with Unequal
Terminations
To synthesize Chebychev filters with unequal terminations,
two equally terminated filters are synthesized at the two
different impedance levels and the resulting networks are
joined using the Impedance Bisection Theorem[1]. This
method only works with symmetrical odd-order filters. The
general lowpass prototype element values are generated
by the method shown [2]:
L | 

β =Incoth Ar dB 
17.37 

π ( 2k– 1)
, k= 1,2,...,n
2n
2
2 πk
b
=
γ
+
sin
, k= 1,2,...,n
k
n
where LAr|dB is the passband ripple in dB, and n is the
filter order.
The prototype element values will be:
g1 =
2a1
γ
gn+1 = 1 for n odd
gn+1 = coth   for n even
 4
Assuming the first element is a capacitor, we can scale
the filter capacitor prototype values up to our desired
cutoff frequency fC:
34
g1 = 1.339 → C1 = 53.3pF
g2 = 1.337 → L1 = 531.98nH
g3 = 2.166 → C2 = 86.19pF
g4 = 1.337 → L2 = 531.98nH
g5 = 1.339 → C3 = 53.3pF
Filter 2: RIN = ROUT = 20Ω
g1 = 1.339 → C1 = 266.48pF
g2 = 1.337 → L1 = 106.4nH
g3 = 2.166 → C2 = 430.93pF
g4 = 1.337 → L2 = 106.4nH
g5 = 1.339 → C3 = 266.48pF
C2→
86.19pF 430.93pF
+
= 258.56pF
2
2
The final unequally-terminated filter design values are
shown in Figure 38.
RIN
100Ω
+
L1
531.98nH
C1
53.3pF
–
L2
106.4nH
C2
258.56pF
C3
266.48pF
ROUT
20Ω
5585 F38
The filter inductor values can be scaled with:
g •R
LK = k IN , k= 2,4,...,n
2π •fC
2 β 
gk
Ck =
, k= 1,3,...,n
2π •fC •RIN
For example, if LAr|dB = 0.2dB, fC = 40MHz, RIN = 100Ω,
ROUT = 20Ω and n = 5, the prototype element values and
resulting scaled filter values are listed:
The Impedance Bisection Theorem can be applied at the
plane of symmetry about C2 such that a new value of C2
can be computed with half the values of the two filters.
4a a
gk = k k–1 , k= 1,2,...,n
bk−1gk−1
The Impedance Bisection Theorem can be applied to symmetrical networks by dividing the element values along
the networks’ plane of symmetry, and then adding the
two networks together. The filter response is preserved.
Filter 1: RIN = ROUT = 100Ω
β
γ = sinh 
 2n
ak = sin
where RIN is the input impedance and the terminating
impedance ROUT is equal to RIN for the n odd case but is
scaled by the gn+1 prototype value for the n even case.
Figure 38. Final Design Schematic
[1] A.C. Bartlett, “An Extension of a Property of Artificial Lines,” Phil. Mag., vol.4, p.902,
November 1927.
[2] G. Matthaei, L. Young, and E.M.T. Jones, Microwave Filters, Impedance-Matching Networks,
and Coupling Structures, p.99, 1964.
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LTC5585
APPENDIX
Image Rejection Calculation
Image rejection can be calculated from the measured gain
and phase error responses of the demodulator. Consider
the signal diagram of Figure 39:
AERR
RF(t)
I(t)
We combine I(t) + Q–90(t) and choose terms containing
ωBB as the desired signal:
1
A
desired= sin( ω BB t) + ERR sin( ω BB t– φERR )
2
2
Similarly, we choose terms containing ωIM as the image
signal:
1
A
image= sin( ωIMt) – ERR sin( ωIMt+ φERR )
2
2
LOI(t)
LOQ(t)
The image rejection ratio (IRR) can then be written as:
Q(t)
5585 F39
Figure 39. Signal Diagram for a Demodulator
where:
RF(t) = sin(ωLO + ωBB)t + sin(ωLO – ωIM)t
LOI(t) = cos(ωLOt + φERR)
|desired|2
IRR|dB = 10log
|image|2
Written in terms of AERR and φERR as:
ωLO + ωBB is the desired sideband frequency and
ωLO – ωIM is the image frequency. The total phase error
of the I and Q channels is lumped into the I-channel LO
source as φERR. The total gain error is represented by
AERR, and is lumped into a gain multiplier in the I-channel.
After lowpass filtering the I and Q signals can be written as:
A
I(t) = ERR sin( ω BB t– φERR ) – sin( ωIMt+ φERR ) 
2
1
Q(t) = cos ( ω BB t) + cos ( ωIMt) 
2
Figure 40 shows image rejection as a function of amplitude
and phase errors for a demodulator.
70
AERR = 0dB
AERR = 0.05dB
AERR = 0.1dB
AERR = 0.2dB
AERR = 0.3dB
AERR = 0.5dB
AERR = 1dB
60
IMAGE REJECTION (dB)
LOQ(t) = sin(ωLOt)
|1+ AERR2 + 2AERR cos ( φERR ) |
IRR|dB = 10log
|1+ AERR2 − 2AERR cos ( φERR ) |
50
40
30
20
10
Shifting the Q channel by –90° can be accomplished by
replacing sine with cosine such that the shifted Q-channel
signal is:
0
1
2
3 4 5 6 7
PHASE ERROR (DEG)
8
9
10
5585 F40
Figure 40. Image Rejection as a Function of Gain and Phase Errors
1
Q–90(t) = sin( ω BB t) + sin( ωIMt) 
2
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35
LTC5585
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UF Package
UF Package
24-Lead Plastic
QFN (4mm × 4mm)
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697 Rev B)
(Reference LTC DWG # 05-08-1697 Rev B)
0.70 ±0.05
4.50 ±0.05
2.45 ±0.05
3.10 ±0.05 (4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
4.00 ±0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
R = 0.115
TYP
0.75 ±0.05
PIN 1 NOTCH
R = 0.20 TYP OR
0.35 × 45° CHAMFER
23 24
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
1
2
2.45 ±0.10
(4-SIDES)
(UF24) QFN 0105 REV B
0.200 REF
0.00 – 0.05
0.25 ±0.05
0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
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LTC5585
REVISION HISTORY
REV
DATE
DESCRIPTION
A
8/12
Changes to 1950MHz L6, C19 and L5 Matching Component Values
3
Correction to Plot 5585 G4 Vertical Axis Label
6
B
11/14
PAGE NUMBER
Changes to Plot G20
8
Changes to Plots G30 and G35
10
Corrections to Plot G44 Horizontal Axis Label
11
Changes to Plot G61
13
Changes to Plot G78
15
Changes to Figure 1, RF and LO MATCH Table 1950MHz L6, C19 and L5 Component Values
18
Changes to Figure 5, 1.9GHz L6 and C19 Component Values
20
Change to Figure 13, 1.9GHz L5 Component Value
22
Added Reduced Power Consumption Paragraph Title
29
Correction to Figure 32 Title
29
Correction to text 1875Hz
31
Changes to Features and Description
1
Change to 700MHz IRR
3
Insert 3500MHz Data and Supply Current Condition
4
Correction to Plot G19 Vertical Axis Label
8
Correction to Plot G34 Vertical Axis Label
10
Correction to Plot G45 Horizontal Axis Label
11
Correction to Plot G60 Vertical Axis Label
13
Correction to Plot G77 Vertical Axis Label
15
Change to Figure 1 RF MATCH 2150MHz Table Values
18
Change to Figure 13 C13 and L5 Component Values
22
Change to text "lag (or lead)"
23
Omission of 6mA Current Arrows
24
Change in Figure 22 C Value
26
Change in Figure 33 ADC Output D15
30
Change in Typical Application ADC Output D15
38
5585fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LTC5585
37
LTC5585
TYPICAL APPLICATION
Simplified Schematic of 1950MHz Receiver, (Only I-Channel Is Shown)
C19
0.4pF
40MHz LOWPASS FILTER
C17
1µF
5V
200mA
RF INPUT
1910MHz
TO
1990MHz
L3 4.7nH
RF
C7
C2 0.5pF
100pF
LO+
C11
100pF
LO INPUT
1950MHz
6dBm
C9
47pF
VCC
+
LTC5585 I
I–
LO–
R4
110Ω
C14
150pF
L5 470nH
L7 180nH
L6 470nH
L8 180nH
C12
47pF
C13
150pF
C16
150pF
R6
30Ω
R7
30Ω
C15
150pF
R14
138Ω
R12
10Ω
– +
VOCM LTC6409
+ –
R9
440Ω
R17
83Ω
C21
62pF
R15
35Ω
L9 180nH
AIN+
L11 180nH
R11
10Ω L10 180nH
R13
138Ω
1.8V
206mA
VCM
L12 180nH
R16
35Ω
C22
62pF R18
83Ω
R19
105Ω
R10
100Ω
C8
0.5pF
AIN–
R20
105Ω
C23
1µF
C20
0.4pF
T1
ANAREN BD2425J50200AHF
L4 4.7nH
5V
52mA
C18
0.1µF
C10
100pF
40MHz ANTI-ALIAS FILTER (AAF)
R8
440Ω
R5
110Ω
VDD
D15
•
•
•
D0
LTC2185
ADC
CONTROL
5585 TA02
RELATED PARTS
PART
NUMBER
DESCRIPTION
Infrastructure
LTC5569
300MHz to 4GHz Dual Active Downconverting Mixer
LT5527
400MHz to 3.7GHz, 5V Downconverting Mixer
LT5557
400MHz to 3.8GHz, 3.3V Downconverting Mixer
LTC6409
10GHz GBW Differential Amplifier
LTC6412
31dB Linear Analog VGA
LTC554X
600MHz to 4GHz Downconverting Mixer Family
LT5554
Ultralow Distortion IF Digital VGA
LT5578
400MHz to 2.7GHz Upconverting Mixer
LT5579
1.5GHz to 3.8GHz Upconverting Mixer
LTC5590
Dual 600MHz to 1.7GHz Downconverting Mixer
LTC5591
Dual 1.3GHz to 2.3GHz Downconverting Mixer
LTC5592
Dual 1.6GHz to 2.7GHz Downconverting Mixer
RF PLL/Synthesizer with VCO
LTC6946-1 Low Noise, Low Spurious Integer-N PLL with
Integrated VCO
LTC6946-2 Low Noise, Low Spurious Integer-N PLL with
Integrated VCO
LTC6946-3 Low Noise, Low Spurious Integer-N PLL with
Integrated VCO
ADCs
LTC2145-14 14-Bit, 125Msps 1.8V Dual ADC
LTC2185
16-Bit, 125Msps 1.8V Dual ADC
LTC2158-14 14-Bit, 310Msps 1.8V Dual ADC, 1.25GHz Full-Power
Bandwidth
COMMENTS
2dB Gain, 26.7dBm IIP3 and 11.7dB NF at 1950MHz, 3.3V/180mA Supply
2.3dB Gain, 23.5dBm IIP3 and 12.5dB NF at 1900MHz, 5V/78mA Supply
2.9dB Gain, 24.7dBm IIP3 and 11.7dB NF at 1950MHz, 3.3V/82mA Supply
DC-Coupled, 48dBm OIP3 at 140MHz, 1.1nV/√Hz Input Noise Density
35dBm OIP3 at 240MHz, Continuous Gain Range –14dB to 17dB
8dB Gain, >25dBm IIP3, 10dB NF, 3.3V/200mA Supply
48dBm OIP3 at 200MHz, 2dB to 18dB Gain Range, 0.125dB Gain Steps
27dBm OIP3 at 900MHz, 24.2dBm at 1.95GHz, Integrated RF Transformer
27.3dBm OIP3 at 2.14GHz, NF = 9.9dB, 3.3V Supply, Single-Ended LO and RF Ports
8.7dB Gain, 26dBm IIP3, 9.7dB Noise Figure
8.5dB Gain, 26.2dBm IIP3, 9.9dB Noise Figure
8.3dB Gain, 27.3dBm IIP3, 9.8dB Noise Figure
373MHz to 3.74GHz, –157dBc/Hz WB Phase Noise Floor, –100dBc/Hz Closed-Loop
Phase Noise
513MHz to 4.9GHz, –157dBc/Hz WB Phase Noise Floor, –100dBc/Hz Closed-Loop
Phase Noise
640MHz to 5.79GHz, –157dBc/Hz WB Phase Noise Floor, –100dBc/Hz Closed-Loop
Phase Noise
73.1dB SNR, 90dB SFDR, 95mW/Ch Power Consumption
76.8dB SNR, 90dB SFDR, 185mW/Channel Power Consumption
68.8dB SNR, 88dB SFDR, 362mW/Ch Power Consumption, 1.32VP-P Input Range
5585fb
38 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC5585
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTC5585
LT 1114 REV B • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2012