ISL80101-ADJ

DATASHEET
High Performance 1A LDO
ISL80101-ADJ
Features
The ISL80101-ADJ is a low voltage, high current, single output
LDO specified at 1A output current. This LDO operates from
input voltages from 2.2V to 6V, and is capable of providing
output voltages from 0.8V to 5V. The ISL80101-ADJ features
an adjustable output. For the fixed output version of the
ISL80101-ADJ, please refer to the ISL80101 datasheet.
• ±1.8% VOUT accuracy guaranteed over line, load and
TJ = -40°C to +125°C
A submicron BiCMOS process is utilized for this product family
to deliver the best in class analog performance and overall
value. This CMOS LDO will consume significantly lower
quiescent current as a function of load compared to bipolar
LDOs, which translates into higher efficiency and packages
with smaller footprints. State of the art internal compensation
achieves a very fast load transient response. An external
capacitor on the soft-start pin provides an adjustable
soft-starting ramp. The ENABLE feature allows the part to be
placed into a low quiescent current shutdown mode. A
Power-good logic output signals a fault condition.
• Power-good output
Table 1 shows the differences between the ISL80101-ADJ and
others in its family:
• Noise-sensitive instrumentation systems
• Very low 130mV dropout voltage at VOUT = 2.5V
• Very fast transient response
• Programmable soft-starting
• Excellent 65dB PSRR
• Current limit protection
• Thermal shutdown function
• Available in a 10 Ld DFN package
• Pb-Free (RoHS compliant)
Applications
• DSP, FPGA and µP core power supplies
• Post regulation of switched mode power supplies
• Industrial systems
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
PART NUMBER
PROGRAMMABLE
ILIMIT
ILIMIT
(DEFAULT)
ADJ OR FIXED
VOUT
ISL80101-ADJ
No
1.75A
ADJ
ISL80101
No
1.75A
1.8V, 2.5V,
3.3V, 5.0V
ISL80101A
Yes
1.62A
ADJ
ISL80121-5
Yes
0.75A
5.0V
• Medical equipment
• Telecommunications and networking equipment
• Servers
• Hard disk drives (HD/HDD)
Related Literature
• AN1592, “ISL80101 High Performance 1A LDO Evaluation
Board User Guide”
10
10µF
CIN
VIN
VOUT
9 V
IN
VOUT
10k
R3
ADJ
1
2
82pF
CPB
3
1.00k
R1
ISL80101-ADJ
7
6
0.01µF
CSS
ENABLE
PG
2.61k
R2
4
SS
GND
5
1.8V
140
10µF
COUT
120
100k
RPG
DROPOUT VOLTAGE (mV)
2.5V ± 10%
100
80
60
40
20
0
VOUT = 2.5V
0
0.2
0.4
0.6
0.8
1.0
OUTPUT CURRENT (A)
FIGURE 1. TYPICAL APPLICATION CIRCUIT
August 26, 2015
FN7834.3
1
FIGURE 2. DROPOUT vs LOAD CURRENT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC. 2011, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL80101-ADJ
Block Diagram
VIN
EN
CONTROL
LOGIC
EA
REFERENCE
+
SOFT-START
THERMAL
SENSOR
PG
PG
+
FET DRIVER
WITH CURRENT
LIMIT
VOUT
SS
ADJ
+
-
GND
Ordering Information
PART NUMBER
(Notes 3, 4)
PART
MARKING
ISL80101IRAJZ (Note 1)
DZAB
ISL80101EVAL2Z
Evaluation Board
VOUT VOLTAGE
(Note 2)
TEMP RANGE
(°C)
ADJ
-40 to +125
PACKAGE
(RoHS Compliant)
10 Ld 3x3 DFN
PKG DWG. #
L10.3x3
NOTES:
1. Add “-T*” for Tape and Reel. Please refer to TB347 for details on reel specifications.
2. For other output voltages, contact Intersil Marketing.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see product information page for ISL80101-ADJ. For more information on MSL please see techbrief
TB363.
Submit Document Feedback
2
FN7834.3
August 26, 2015
ISL80101-ADJ
Pin Configurations
ISL80101-ADJ
(10 LD 3x3 DFN)
TOP VIEW
VOUT 1
10 VIN
VOUT 2
ADJ 3
PG 4
GND 5
9 VIN
EPAD
8 NC
7 ENABLE
6 SS
Pin Descriptions
PIN NUMBER
PIN NAME
1, 2
VOUT
Regulated output voltage. A X5R/X7R output capacitor is required for stability. See “External Capacitor
Requirements” on page 8 for more details.
3
ADJ
This pin is connected to the feedback resistor divider and provides voltage feedback signals for the LDO to set the
output voltage. In addition, the PGOOD circuit uses this input to monitor the output voltage status.
4
PG
This is an open-drain logic output used to indicate the status of the output voltage. Logic low indicates VOUT is not
in regulation. Must be grounded if not used.
5
GND
6
SS
7
ENABLE
8
NC
No connection; Leave floating.
9, 10
VIN
Input supply; A minimum of 10µF X5R/X7R input capacitor is required for proper operation. See “External
Capacitor Requirements” on page 8 for more details.
-
EPAD
Submit Document Feedback
DESCRIPTION
Ground
External capacitor on this pin adjusts start-up ramp and controls inrush current.
VIN independent chip enable. TTL and CMOS compatible.
EPAD at ground potential. It is recommended to solder the EPAD to the ground plane.
3
FN7834.3
August 26, 2015
ISL80101-ADJ
Absolute Maximum Ratings
Thermal Information
VIN Relative to GND (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
VOUT Relative to GND (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
PG, ENABLE, ADJ, SS
Relative to GND (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
ESD Rating
Human Body Model (Tested per JESD22 A114F) . . . . . . . . . . . . . . .2.5kV
Charge Device Model (Tested per JESD22-C101C). . . . . . . . . . . . . . . 2kV
Latch-up (Tested per JESD78C, Class 2, Level A) . . . . ±100mA at +125°C
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
10 Ld DFN Package (Notes 6, 7) . . . . . . . .
48
7
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions (Notes 8, 9)
Junction Temperature Range (TJ) (Note 8) . . . . . . . . . . . .-40°C to +125°C
VIN Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.2V to 6V
VOUT Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800mV to 5V
PG, ENABLE, ADJ, SS relative to GND . . . . . . . . . . . . . . . . . . . . . . . 0V to 6V
PG Sink Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <10mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
5. ABS max voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6V of 1%.
6. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
7. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
8. Extended operation at these conditions may compromise reliability. Exceeding these limits will result in damage. Recommended operating conditions
define limits where specifications are guaranteed.
9. Electromigration specification defined as lifetime average junction temperature of +110°C where max rated DC current = lifetime average current.
Electrical Specifications
Unless otherwise noted, 2.2V < VIN < 6V, VOUT = 0.5V, TJ = +25°C. Applications must follow thermal guidelines
of the package to determine worst case junction temperature. Please refer to “Applications Information” on page 8 and Tech Brief TB379.
Boldface limits apply across the operating temperature range, -40°C to +125°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 10)
TYP
MAX
(Note 10)
UNITS
VADJ
VOUT + 0.4V < VIN < 6V, VOUT = 2.5V, 0A < ILOAD < 1A
491
500
509
mV
DC CHARACTERISTICS
Feedback Pin (ADJ Option Only)
DC Input Line Regulation
(VOUT low line - VOUT + 0.4V < VIN < 6V, VOUT = 2.5V
VOUT high
line)/VOUT low
line
-1
1
%
DC Output Load Regulation
(VOUT no load- 0A < ILOAD < 1A, VOUT = 2.5V
VOUT high
load)/ VOUT no
load
-1
1
%
VADJ = 0.5V
Feedback Input Current
Ground Pin Current
IQ
Ground Pin Current in Shutdown
ISHDN
0.01
1
µA
ILOAD = 0A, VOUT + 0.4V < VIN < 6V, VOUT = 2.5V
3
5
mA
ILOAD = 1A, VOUT + 0.4V < VIN < 6V, VOUT = 2.5V
5
7
mA
0.2
12
µA
212
mV
ENABLE Pin = 0.2V, VIN = 6V
Dropout Voltage (Note 11)
VDO
ILOAD = 1A, VOUT = 2.5V
130
Output Short Circuit Current
OCP
VOUT = 0V
1.75
A
Thermal Shutdown Temperature
TSD
160
°C
Thermal Shutdown Hysteresis
TSDn
30
°C
f = 1kHz, ILOAD = 1A; VIN = 2.2V, VOUT = 1.8V
58
dB
f = 120Hz, ILOAD = 1A; VIN = 2.2V, VOUT = 1.8V
65
dB
ILOAD = 1A, BW = 100Hz < f < 100kHz, VIN = 2.2V,
VOUT = 1.8V
53
µVRMS
AC CHARACTERISTICS
Input Supply Ripple Rejection
PSRR
Output Noise Voltage
Submit Document Feedback
4
FN7834.3
August 26, 2015
ISL80101-ADJ
Electrical Specifications
Unless otherwise noted, 2.2V < VIN < 6V, VOUT = 0.5V, TJ = +25°C. Applications must follow thermal guidelines
of the package to determine worst case junction temperature. Please refer to “Applications Information” on page 8 and Tech Brief TB379.
Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued)
MIN
(Note 10)
TYP
MAX
(Note 10)
UNITS
Turn-on Threshold
0.5
0.8
1
V
Hysteresis
10
80
200
mV
PARAMETER
SYMBOL
TEST CONDITIONS
ENABLE PIN CHARACTERISTICS
ENABLE Pin Turn-on Delay
COUT = 10µF, ILOAD = 1A
ENABLE Pin Leakage Current
VIN = 6V, ENABLE = 2.8V
100
µs
1
µA
SOFT-START CHARACTERISTICS
IPD
SS Pin Currents (Note 12)
VIN = 3.5V, ENABLE = 0V, SS = 1V
ICHG
0.5
1
1.3
mA
-3.3
-2
-0.8
µA
75
85
92
%VOUT
PG PIN CHARACTERISTICS
VOUT PG Flag Threshold
VOUT PG Flag Hysteresis
4
PG Flag Low Voltage
VIN = 3V, ISINK = 500µA
PG Flag Leakage Current
VIN = 6V, PG = 6V
%
100
mV
1
µA
NOTES:
10. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
11. Dropout is defined as the difference in supply VIN and VOUT when the supply produces a 2% drop in VOUT from its nominal voltage.
12. IPD is the internal pull down current that discharges the external SS capacitor on disable. ICHG is the current from the SS pin that charges the external
SS capacitor during start-up.
Submit Document Feedback
5
FN7834.3
August 26, 2015
ISL80101-ADJ
Typical Operating Performance
Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C, IL = 0A.
200
1.8
VOUT = 2.5V
1.2
160
140
IOUT = 1.0A
0.6
120
100
VOUT (%)
DROPOUT VOLTAGE (mV)
180
IOUT = 0.5A
80
60
0
-0.6
IOUT = 0.1A
40
-1.2
20
0
-40
-25
-10
5
20
35
50
65
80
95
-1.8
-50
110 125
-25
0
25
50
75
100
125
150
JUNCTION TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 3. DROPOUT VOLTAGE vs TEMPERATURE
FIGURE 4. VOUT vs TEMPERATURE
1.8
2.0
1.2
1.6
1.4
0.6
1.2
VOUT (%)
OUTPUT VOLTAGE (V)
1.8
+125°C
1.0
0.8
-40°C
+25°C
+25°C
0
-0.6
0.6
0.4
-40°C
+125°C
-1.2
0.2
0
0
1
3
2
5
4
-1.8
6
0
0.25
SUPPLY VOLTAGE (V)
FIGURE 5. OUTPUT VOLTAGE vs SUPPLY VOLTAGE
0.50
0.75
OUTPUT CURRENT (A)
1.00
FIGURE 6. OUTPUT VOLTAGE vs OUTPUT CURRENT
3.5
5
GROUND CURRENT (mA)
GROUND CURRENT (mA)
3.0
2.5
2.0
1.5
+25°C
+125°C
-40°C
1.0
0.5
0
0
0.2
0.4
0.6
0.8
LOAD CURRENT (A)
FIGURE 7. GROUND CURRENT vs LOAD CURRENT
Submit Document Feedback
6
1.0
4
3
2
1
0
2
3
4
5
6
INPUT VOLTAGE (V)
FIGURE 8. GROUND CURRENT vs SUPPLY VOLTAGE
FN7834.3
August 26, 2015
ISL80101-ADJ
Typical Operating Performance
Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C, IL = 0A. (Continued)
3.5
2.5
2.0
CURRENT (A)
VOLTAGE RAILS AT 50mV/DIV
VIN = 3.7V, VOUT = 3.3V, COUT = 10µF, CPB = 100pF
VIN = 6V
VIN = 2.2V
1.5
1.0
0.5
VIN = 2.9V, VOUT = 2.5V, COUT = 10µF, CPB = 82pF
0
-40
-25
-10
5
20
35
50
65
80
95 110 125
JUNCTION TEMPERATURE (°C)
FIGURE 10. CURRENT LIMIT vs TEMPERATURE (VOUT = 0V)
VIN = 2.5V, VOUT = 1.8V, COUT = 10µF, CPB = 82pF
VIN = 2.5V, VOUT = 1.5V, COUT = 22µF, CPB = 150pF
ENABLE
(2V/DIV)
VIN = 2.5V, VOUT = 1.2V, COUT = 47µF, CPB = 270pF
VOUT (1V/DIV)
VIN = 2.5V, VOUT = 1.0V, COUT = 47µF, CPB = 220pF
SS (1V/DIV)
1A
1mA
di/dt = 4A/µs
FIGURE 9. LOAD TRANSIENT RESPONSE
FIGURE 11. ENABLE START-UP (CSS = 2.2nF)
90
80
90
500mA
70
1A
80
COUT = 10µF, CPB = 82pF
70
COUT = 100µF
60
PSRR (dB)
PSRR (dB)
60
50
(500µs/DIV)
PG (1V/DIV)
TIME (20µs/DIV)
0mA
100mA
40
50
40
30
30
20
20
10
10
CPB = 82pF
0
100
1k
10k
FREQUENCY (Hz)
100k
1M
FIGURE 12. PSRR vs FREQUENCY FOR VARIOUS LOAD CURRENTS
Submit Document Feedback
7
0
100
1k
10k
FREQUENCY (Hz)
100k
1M
FIGURE 13. PSRR vs FREQUENCY FOR VARIOUS OUTPUT
CAPACITORS (IOUT = 100mA)
FN7834.3
August 26, 2015
ISL80101-ADJ
Typical Operating Performance
Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C, IL = 0A. (Continued)
10
VIN (2V/DIV)
VIN = 2.25V
NOISE (µV/√Hz)
VIN = 3.8V
1
0.1
VIN = 2.2V
VOUT = 1.8
COUT = 10µF
IOUT = 1A
VOUT (5mV/DIV)
0.01
10
100
TIME (200µs/DIV)
FIGURE 14. LINE TRANSIENT RESPONSE
Applications Information
Input Voltage Requirements
ISL80101-ADJ is capable of delivering output voltages from 0.8V
to 5.0V. Due to the nature of an LDO, VIN must be some margin
higher than VOUT plus dropout at the maximum rated current of
the application if active filtering (PSRR) is expected from VIN to
VOUT. The very low dropout specification of this family of LDOs
allows applications to design for a level of efficiency that can
accommodate profiles smaller than the TO220/263.
Enable Operation
The Enable turn-on threshold is typically 800mV with 80mV of
hysteresis. This pin must not be left floating, and should be tied
to VIN if not used. A 1kΩ to 10kΩ pull-up resistor is required for
applications that use open collector or open-drain outputs to
control the Enable pin. An internal pull-up or pull-down resistor to
change these values is available upon request. The Enable pin
may be connected directly to VIN for applications with outputs
that are always on.
Power-Good Operation
PG is a logic output that indicates the status of VOUT. The PG flag
is an open-drain NMOS that can sink up to 10mA. It requires an
external pull-up resistor typically connected to the VOUT pin. The
PG pin should not be pulled up to a voltage source greater than
VIN. PG goes low when the output voltage drops below 84% of the
nominal output voltage or if the part is disabled. The PG comparator
functions during current limit and thermal shutdown. For applications
not using this feature, connect this pin to ground.
Soft-Start Operation
The soft-start circuit controls the rate at which the output voltage
rises up to regulation at power-up or LDO enable. This start-up
ramp time can be set by adding an external capacitor from the
SS pin to ground. An internal 2µA current source charges up this
CSS and the feedback reference voltage is clamped to the
voltage across it. The start-up time is set by Equation 1.
Submit Document Feedback
8
1k
FREQUENCY (Hz)
10k
100k
FIGURE 15. OUTPUT NOISE SPECTRAL DENSITY
C SS x0.5
T start = -----------------------2A
(EQ. 1)
Equation 2 determines the CSS required for a specific start-up
in-rush current, where VOUT is the output voltage, COUT is the
total capacitance on the output and IINRUSH is the desired in-rush
current.
V OUT xC OUT x2A
C SS = ---------------------------------------------------I INRUSH x0.5V
(EQ. 2)
The external capacitor is always discharged to ground at the
beginning of start-up or enabling.
Output Voltage Selection
An external resistor divider, R1 and R2 as referenced in Figure 1
on page 1, is used to scale the output voltage relative to the
internal reference voltage. The output voltage can be
programmed to any level between 0.8V and 5V. The
recommended value for R2 is 500Ω to 5kΩ. R1 is then chosen to
satisfy Equation 3.
 R2

V OUT = 0.5V   ------- + 1
 R1

(EQ. 3)
External Capacitor Requirements
External capacitors are required for proper operation. Careful
attention must be paid to the layout guidelines and selection of
capacitor type and value to ensure optimal performance.
OUTPUT CAPACITOR
The ISL80101-ADJ applies state-of-the-art internal compensation
to keep the selection of the output capacitor simple for the
customer. Stable operation over full temperature, VIN range,
VOUT range and load extremes are guaranteed for all capacitor
types and values assuming the minimum recommended ceramic
capacitor is used for local bypass on VOUT. There is a growing
trend to use very-low ESR multilayer ceramic capacitors (MLCC)
because they can support fast load transients and also bypass
very high frequency noise from other sources. However, the
effective capacitance of MLCCs drops with applied voltage, age,
FN7834.3
August 26, 2015
ISL80101-ADJ
and temperature. X7R and X5R dielectric ceramic capacitors are
strongly recommended as they typically maintain a capacitance
range within ±20% of nominal voltage over full operating ratings
of temperature and voltage. This output capacitor must be
connected to the VOUT and GND pins of the LDO with PCB traces
no longer than 0.5cm.
Additional capacitors of any value in ceramic, POSCAP,
alum/tantalum electrolytic types may be placed in parallel to
improve PSRR at higher frequencies and/or load transient AC
output voltage tolerances. The use of CPB (see following section)
is recommended when only the minimum recommended
ceramic capacitor is used on the output. Please refer to Table 2
for these minimum conditions for various output voltages.
Phase Boost Capacitor
A small phase boost capacitor, CPB, can be placed across the top
resistor, R2, in the feedback resistor divider network in order to
place a zero at:
1
F z = ---------------------------------2xR 2 xC PB
(EQ. 4)
Power Dissipation and Thermals
The junction temperature must not exceed the range specified in
the “Recommended Operating Conditions” on page 4. The power
dissipation can be calculated by using Equation 5:
The maximum allowable junction temperature, TJ(MAX) and the
maximum expected ambient temperature, TA(MAX) determine the
maximum allowable power dissipation, as shown in Equation 6:
JA is the junction-to-ambient thermal resistance.
For safe operation, ensure that the power dissipation PD,
calculated from Equation 5, is less than the maximum allowable
power dissipation PD(MAX).
The DFN package uses the copper area on the PCB as a heatsink.
The EPAD of this package must be soldered to the copper plane
(GND plane) for effective heat dissipation. Figure 16 shows a curve
for the JA of the DFN package for different copper area sizes.
49
It is important to note that LDO stability and load transient
performance are affected by the type of output capacitor used.
For optimal result, empirical tuning of CPB is suggested for each
specific application. It is recommended to not use CPB when high
ESR capacitors such as Aluminum Electrolytic or Tantalum are
used on the output.
45
TABLE 2. RECOMMENDED CPB FOR DIFFERENT VOUT AND COUT
VOUT
(V)
R2
(kΩ)
R1
(kΩ)
COUT
(µF)
CPB
(pF)
5.0
2.61
0.287
10
100
3.3
2.61
0.464
10
100
2.5
2.61
0.649
10
82
1.8
2.61
1.0
10
82
1.5
2.61
1.3
10
68
1.5
2.61
1.3
22
150
1.2
2.61
1.87
22
120
1.2
2.61
1.87
47
270
1.0
2.61
2.61
47
220
0.8
2.61
4.32
47
220
INPUT CAPACITOR
For proper operation, a minimum capacitance of 10µF X5R/X7R
is required at the input. This ceramic input capacitor must be
connected to the VIN and GND pins of the LDO with PCB traces no
longer than 0.5cm.
Submit Document Feedback
9
(EQ. 6)
P D  MAX  =  T J  MAX  – T A    JA
This zero increases the crossover frequency of the LDO and
provides additional phase resulting in faster load transient
response.
Table 2 shows the recommended minimum ceramic COUT and
corresponding CPB, R2 and R1 for different output voltages.
(EQ. 5)
P D =  V IN – V OUT   I OUT + V IN  I GND
JA °C/W
47
43
41
39
37
2
4
6
8
10
12
14
16
18
20
22
24
EPAD-MOUNT COPPER LAND AREA ON PCB, mm2
FIGURE 16. 3mmx3mm 10-PIN DFN ON 4-LAYER PCB WITH
THERMAL VIAS JA vs EPAD-MOUNT COPPER LAND
AREA ON PCB
Thermal Fault Protection
The power level and the thermal impedance of the package
(+45°C/W for DFN) determine when the junction temperature
exceeds the thermal shutdown temperature. In the event that the
die temperature exceeds around +160°C, the output of the LDO will
shut down until the die temperature cools down to about +130°C.
Current Limit Protection
The ISL80101-ADJ LDO incorporates protection against overcurrent
due to any short or overload condition applied to the output pin. The
LDO performs as a constant current source when the output current
exceeds the current limit threshold noted in the “Electrical
Specifications” table on page 4. If the short or overload condition is
removed from VOUT, then the output returns to normal voltage
regulation mode. In the event of an overload condition, the LDO may
begin to cycle on and off due to the die temperature exceeding
thermal fault condition and subsequently cooling down after the
power device is turned off.
FN7834.3
August 26, 2015
ISL80101-ADJ
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
August 26, 2015
FN7834.3
CHANGE
Added Related Literature to page 1.
Removed 1st bullet in Features on page 1 which read ±0.2% initial VOUT accuracy.
Changed 7th bullet in Features on page 1 from Excellent 58dB PSRR at 1kHz to Excellent 65dB PSRR
Updated the EA amp in the “Block Diagram” on page 2 by switching the + and - terminals. The positive
terminal is now connected to the ADJ pin. Removed “SENSE” pin Reference in diagram
“Pin Descriptions” on page 3 - Removed “minimum 10µF” from 1st sentence in VOUT description.
“Absolute Maximum Ratings” on page 4 - Removed Machine Model and changed latch up from +85°C to
+125°C.
Removed "SENSE" from “ADJ” in "‘Recommended Operating Conditions" on page 4.
Added “VIN =” to values in Figure 10 on page 7
Changed Title of Figure 3 on page 6 from Dropout vs Temperature to Dropout Voltage vs Temperature
Changed Title in Figure 12 on page 7 from PSRR vs Frequency and Load Current to PSRR vs Frequency for
various load currents
Changed Title in Figure 13 on page 7 from PSRR vs Frequency and Output Capacitance (IOUT = 100mA) to
PSRR vs Frequency for various output capacitors (IOUT=100mA)
Electrical Spec changes:
Electrical Spec Table conditions on page 4 changed: VIN = VOUT + 0.4V, VOUT = 1.8V, CIN = COUT = 2.2µF, to:
2.2V < VIN < 6V, VOUT = 0.5V
“Feedback Pin (ADJ Option Only)” Test Conditions changed from: 2.2V VIN  6V, 0A < ILOAD < 1A to: VOUT +
0.4V < VIN < 6V, VOUT = 2.5V, 0A < ILOAD < 1A
"DC Input Line Regulation" on page 4 - changed symbol from VOUT/VIN to VOUT low line - VOUT high
line)/VOUT low line and added MIN -1. Test Conditions changed from: VOUT + 0.5V < VIN < 5V to: VOUT + 0.4V
< VIN < 6V, VOUT = 2.5V
“DC Output Load Regulation” on page 4 - changed symbol from VOUT/IOUT to VOUT no load-VOUT high load)/
VOUT no load and added MAX 1. Test Conditions changed from: 0A < ILOAD < 1A, All voltage options to: 0A <
ILOAD < 1A, VOUT = 2.5V
Ground Pin Current Test Conditions changed from:
ILOAD = 0A, 2.2V < VIN < 6V to: ILOAD = 0A, VOUT + 0.4V < VIN < 6V, VOUT = 2.5V
ILOAD = 1A, 2.2V < VIN < 6V to: ILOAD = 1A, VOUT + 0.4V < VIN < 6V, VOUT = 2.5V
Output Short Circuit Current Test Conditions changed from: VOUT = 0V, 2.2V < VIN < 6V to: VOUT = 0V
Thermal Shutdown Temperature, Thermal Shutdown Hysteresis, Turn-on Threshold and Hysteresis - Removed
Test Conditions
Removed “Rising Threshold” from ““Thermal Shutdown Hysteresis” on page 4 and from “Hysteresis” on page 5
“AC CHARACTERISTICS” on page 4 in PSRR - changed TYP from "72" to "65" for f = 120Hz. Added to Test
Conditions: VOUT = 1.8V
Output Noise Voltage in test conditions changed “10Hz” to “100Hz”, added VIN = 2.2V, VOUT = 1.8V. Changed
TYP from “63” to “53”
“PG Flag Low Voltage” on page 5 changed in test conditions - VIN = 2.5V TO VIN = 3V
“Turn-on Threshold” on page 5 changed MIN from: 0.3; to: 0.5
“Hysteresis” on page 5 changed in test conditions from: 2.2V < VOUT + 0.4V < 6V, to: 2.2V < VIN < 6V
“ENABLE Pin Leakage Current” on page 5 changed “Enable = 3V” to “Enable = 2.8V”
------------------------------------------------Updated Output Spectral Noise Density (Figure 15 on page 8) and changed IL = 1A to IOUT = 1A
Updated POD L10.3x3 to most recent revision with changes as follows:
Added missing dimension 0.415 in Typical Recommended land pattern.
Shortened the e-pad rectangle on both the recommended land pattern and the package bottom view to line
up with the centers of the corner pins.
Tiebar Note 4 updated
From: Tiebar shown (if present) is a non-functional feature.
To: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends).
Submit Document Feedback
10
FN7834.3
August 26, 2015
ISL80101-ADJ
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision. (Continued)
DATE
REVISION
CHANGE
July 31, 2014
FN7834.2
Updated the “Block Diagram” on page 2 reversed the + and - terminals on the EA amp. The inverting terminal
is now connected to the Adj/Sense pin.
Updated About Intersil verbiage to new standard.
Updated “Package Outline Drawing” on page 12 to latest revision.
August 3, 2011
FN7834.1
PAGE 1
1. Introduction, paragraph 1: Last two sentences removed, and replaced with: "The ISL80101-ADJ features
an adjustable output. For the fixed output version of the ISL80101, please refer to the ISL80101 datasheet."
2. Table 1: Replaced Table 1 with Table 1 from FN6931 to include the "ADJ or Fixed VOUT" column and
"ISL80101-ADJ" row.
3. Features: "Available in a 10 Ld DFN Package" has "TO220-5, TO263-5 and SOT223-5 to follow soon"
removed.
PAGE 5
1. Enable Pin Characteristics
a. "Enable Pin Turn-on Delay" changed to "ENABLE Pin Turn-on Delay"
b. "Enable Pin Leakage Current" changed to "ENABLE Pin Leakage Current"
PAGE 7
Figure 9: Timescale changed from "20µs/DIV" to "TIME (20µs/DIV)"
PAGE 8
2. Equation 1 - Parentheses deleted.
3. Equation 2 - Parentheses deleted.
March 31, 2011
FN7834.0
Initial Release.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
Submit Document Feedback
11
FN7834.3
August 26, 2015
ISL80101-ADJ
Package Outline Drawing
L10.3x3
10 LEAD DUAL FLAT PACKAGE (DFN)
Rev 11, 3/15
3.00
5
PIN #1 INDEX AREA
A
B
1
5
PIN 1
INDEX AREA
(4X)
3.00
2.00
8x 0.50
2
10 x 0.23
0.10
1.60
TOP VIEW
10x 0.35
BOTTOM VIEW
(4X)
0.10 M C A B
0.415
0.200
0.23
0.35
(10 x 0.55)
SEE DETAIL "X"
(10x 0.23)
1.00
MAX
0.10 C
0.20
2.00
(8x 0.50)
BASE PLANE
C
SEATING PLANE
0.08 C
SIDE VIEW
0.415
C
1.60
0.20 REF
4
0.05
2.85 TYP
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
Submit Document Feedback
12
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Tiebar shown (if present) is a non-functional feature and may be
located on any of the 4 sides (or ends).
5.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN7834.3
August 26, 2015