DATASHEET

DATASHEET
Radiation Hardened Dual 36V Precision Single-Supply,
Rail-to-Rail Output, Low-Power Operational Amplifiers
ISL70218SEH, ISL70218SRH
Features
The ISL70218SEH, ISL70218SRH are dual, low-power
precision amplifiers optimized for single-supply applications.
These op amps feature a common-mode input voltage range
extending to 0.5V below the V- rail, a rail-to-rail differential
input voltage range, and rail-to-rail output voltage swing, which
makes it ideal for single-supply applications where input
operation at ground is important.
• DLA SMD# 5962-12222 (ISL70218SEH Only)
These op amps feature low-power, low-offset voltage and
low-temperature drift, making it ideal for applications
requiring both high DC accuracy and AC performance. They are
designed to operate over a single supply range of 3V to 36V or a
split supply voltage range of +1.8V/-1.2V to ±18V. The
combination of precision and small footprint provides the user
with outstanding value and flexibility relative to similar
competitive parts.
Applications for these amplifiers include precision
instrumentation, data acquisition and precision power supply
controls.
ISL70218SEH, ISL70218SRH are available in a 10 lead
hermetic ceramic flatpack and operate across the extended
temperature range of -55°C to +125°C.
Related Literature
• AN1653, “ISL70218SRH Evaluation Board User’s Guide”
• AN1677, “Single Events Effects Testing of the
ISL70218SRH, Dual 36V Rad Hard Low Power Operational
Amplifiers”
• Wide single and dual supply range . . . . . . 3V to 42V, Abs. Max.
• Low current consumption . . . . . . . . . . . . . . . . .850µA, typical
• Low input offset voltage. . . . . . . . . . . . . . . . . . . . 40µV, typical
• Rail-to-rail output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <10mV
• Rail-to-rail input differential voltage range for comparator
applications
• Operating temperature range. . . . . . . . . . . .-55°C to +125°C
• Below-ground (V-) input capability to -0.5V
• Low noise voltage. . . . . . . . . . . . . . . . . . . . . 5.6nV/Hz, typical
• Low noise current. . . . . . . . . . . . . . . . . . . . 355fA/Hz, typical
• Offset voltage temperature drift . . . . . . . . .0.3µV/°C, typical
• No phase reversal
• Radiation tolerance
- High dose rate (50-300rad(Si)/s). . . . . . . . . . . 100krad(Si)
- Low dose rate (0.01rad(Si)/s) . . . . . . . . . . . . 100krad(Si)*
- SEB LETTH (VS = ±18V) . . . . . . . . . . . . . .86.4 MeV•cm2/mg
- SEL Immune (SOI Process)
* Product capability established by initial characterization. The
EH version is acceptance tested on a wafer-by-wafer basis to
50krad(Si) at low dose rate.
Applications
• Precision instruments
• Active filter blocks
• Data acquisition
• Power supply control
RINRSENSE
IN-
400
100kΩ
300
-
V+
ISL70218SxH
VIN+
+
10kΩ
RIN+
10kΩ
+3V
to 36V
+25°C
+125°C
200
VOUT
GAIN = 10
RREF+
100kΩ
|VOS (µV)|
LOAD
RF
100
0
-100
-40°C
-200 -55°C
-300
VREF
-400
-16
-15
-14
-13 13
14
15
16
INPUT COMMON-MODE VOLTAGE (V)
FIGURE 1. TYPICAL APPLICATION: SINGLE-SUPPLY, LOW-SIDE
CURRENT SENSE AMPLIFIER
May 19, 2016
FN7957.3
1
FIGURE 2. INPUT OFFSET VOLTAGE vs INPUT COMMON-MODE
VOLTAGE, VS = ±15V
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC. 2012, 2014, 2016. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL70218SEH, ISL70218SRH
Pin Configuration
ISL70218SEH, ISL70218SRH
(10 LD FLATPACK)
TOP VIEW
OUT_A
V+
1
10
9
OUT_B
8
-IN_B
7
+IN_B
6
NC
-IN_A
2
+IN_A
3
NC
4
V-
5
- +
+ -
Pin Descriptions
PIN NUMBER
PIN NAME
EQUIVALENT CIRCUIT
1
OUT_A
Circuit 2
Amplifier A output
2
-IN_A
Circuit 1
Amplifier A inverting input
3
+IN_A
Circuit 1
Amplifier A noninverting input
4, 6
NC
5
V-
Circuit 1, 2, 3
7
+IN_B
Circuit 1
Amplifier B noninverting input
8
-IN_B
Circuit 1
Amplifier B inverting input
9
OUT_B
Circuit 2
Amplifier B output
10
V+
Circuit 1, 2, 3
IN-
No connect
V+
V+
IN+
OUT
V-
VCIRCUIT 1
Submit Document Feedback
CIRCUIT 2
2
DESCRIPTION
Negative power supply
Positive power supply
V+
CAPACITIVELY
TRIGGERED ESD
CLAMP
VCIRCUIT 3
FN7957.3
May 19, 2016
ISL70218SEH, ISL70218SRH
Ordering Information
ORDERING
SMD NUMBER
PART NUMBER
(Note 1)
TEMP RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
5962R1222201VXC (Note 2)
ISL70218SEHVF
-55 to +125
10 Ld Flatpack
K10.A
NA
ISL70218SEHF/PROTO
-55 to +125
10 Ld Flatpack
K10.A
5962R1222201V9A (Note 2)
ISL70218SEHVX
-55 to +125
Die
NA
ISL70218SEHVX/SAMPLE
-55 to +125
Die
NA
ISL70218SRHMF
-55 to +125
10 Ld Flatpack
K10.A
NA
ISL70218SRHF/PROTO
-55 to +125
10 Ld Flatpack
K10.A
NA
ISL70218SRHMX
-55 to +125
Die
NA
ISL70218SRHX/SAMPLE
-55 to +125
Die
NA
ISL70218SRHMEVAL1Z
Evaluation Board
NOTES:
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in the
“Ordering Information” table must be used when ordering.
Submit Document Feedback
3
FN7957.3
May 19, 2016
ISL70218SEH, ISL70218SRH
Absolute Maximum Ratings
Thermal Information
Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42V
Maximum Supply Voltage (Note 5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V
Maximum Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Maximum Differential Input Voltage . . . . . . . . . . . . . . .V- - 0.5V to V+ + 0.5V
Min/Max Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . .V- - 0.5V to V+ + 0.5V
Max/Min Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA
Output Short-Circuit Duration (1 output at a time) . . . . . . . . . . . . . Indefinite
ESD Tolerance
Human Body Model (Tested per MIL-PRF-883 3015.7). . . . . . . . . . . 2kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . . 300V
Charged Device Model (Tested per CDM-22CI0ID) . . . . . . . . . . . . . . 750V
Dielectrically Isolated PR40 Process . . . . . . . . . . . . . . . . . . . . Latch-Up Free
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
10 Ld Flatpack Package (Notes 3, 4). . . . .
130
20
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Recommended Operating Conditions
Ambient Operating Temperature Range . . . . . . . . . . . . . .-55°C to +125°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . .+150°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 3V (+1.8V/-1.2V) to 30V (±15V)
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
4. For JC, the “case temp” location is the center of the package underside.
5. Tested in a heavy ion environment at LET = 86.4 MeV•cm2/mg at +125°C (TC) for SEB. Please refer to AN1677 for more information.
Electrical Specifications VS ±15V, VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply across the
operating temperature range, -55°C to +125°C.
SYMBOL
VOS
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
Offset Voltage
TYP
MAX
(Note 6)
UNIT
40
230
µV
290
µV
TCVOS
Offset Voltage Drift
0.3
1.4
µV/°C
VOS
Input Offset Voltage Match
Channel-to-Channel
44
280
µV
365
µV
50
nA
75
nA
IOS
Input Offset Current
-50
4
-75
IB
Input Bias Current
-575
-230
nA
-800
VCMIR
CMRR
PSRR
AVOL
VOH
VOL
IS
IS+
Common-Mode Input Voltage Range
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Open-Loop Gain
Output Voltage High, V+ to VOUT
Output Voltage Low, VOUT to V-
Guaranteed by CMRR Test
(V-) - 0.5
(V+) - 1.8
V
V-
(V+) - 1.8
V
VCM = V- to V+ -1.8V
100
VCM = V- to V+ -1.8V
97
VS = 3V to 40V,
VCMIR = Valid Input Voltage
105
RL = 10kΩ to ground
VO = -13V to +13V
120
Submit Document Feedback
4
118
dB
dB
124
dB
100
dB
130
dB
115
dB
RL = 10kΩ
RL = 10kΩ
Supply Current/Amplifier
Source Current Capability
nA
0.85
10
110
mV
120
mV
70
mV
80
mV
1.10
mA
1.4
mA
mA
FN7957.3
May 19, 2016
ISL70218SEH, ISL70218SRH
Electrical Specifications VS ±15V, VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply across the
operating temperature range, -55°C to +125°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
IS-
Sink Current Capability
VSUPPLY
Supply Voltage Range
Guaranteed by PSRR
GBW
Gain Bandwidth Product
ACL = 101, VOUT = 100mVP-P; RL = 2k
enp-p
MIN
(Note 6)
TYP
MAX
(Note 6)
10
UNIT
mA
3
40
V
AC SPECIFICATIONS
4
MHz
Voltage Noise
0.1Hz to 10Hz, VS = ±18V
300
nVP-P
en
Voltage Noise Density
f = 10Hz, VS = ±18V
8.5
nV/Hz
en
Voltage Noise Density
f = 100Hz, VS = ±18V
5.8
nV/Hz
en
Voltage Noise Density
f = 1kHz, VS = ±18V
5.6
nV/Hz
en
Voltage Noise Density
f = 10kHz, VS = ±18V
5.6
nV/Hz
in
Current Noise Density
f = 1kHz, VS = ±18V
355
fA/Hz
Total Harmonic Distortion + Noise
1kHz, G = 1, VO = 3.5VRMS,
RL = 10kΩ
0.0003
%
±1.2
V/µs
THD + N
TRANSIENT RESPONSE
SR
Slew Rate
AV = 1, RL = 2kΩ, VO = 10VP-P
±1.0
±0.4
tr, tf, Small Signal
Rise Time 10% to 90% of VOUT
V/µs
AV = 1, VOUT = 100mVP-P, Rf = 0Ω,
RL = 2kΩ to VCM
100
AV = 1, VOUT = 100mVP-P, Rf = 0Ω
RL = 2kΩto VCM
100
Settling Time to 0.01%
10V Step; 10% to VOUT
AV = 1, VOUT = 10VP-P, Rf = 0Ω
RL = 2kΩ to VCM
8.5
µs
OS+
Positive Overshoot
AV = 1, VOUT = 10VP-P, Rf = 0Ω
RL = 2kΩ to VCM
5
%
OS-
Negative Overshoot
AV = 1, VOUT = 10VP-P, Rf = 0Ω
RL = 2kΩ to VCM
5
Fall Time 90% to 10% of VOUT
ts
200
ns
400
ns
230
ns
400
ns
35
%
%
35
%
Electrical Specifications VS ±15V, VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply over a total
ionizing dose of 100krad(Si) with exposure at a high dose rate of 50 - 300krad(Si)/s; and over a total ionizing dose of 50krad(Si) with exposure at a low
dose rate of <10mrad(Si)/s.
SYMBOL
VOS
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
Offset Voltage
TYP
MAX
(Note 6)
UNIT
40
230
µV
290
µV
TCVOS
Offset Voltage Drift
0.3
1.4
µV/°C
VOS
Input Offset Voltage Match
Channel-to-Channel
44
280
µV
365
µV
50
nA
75
nA
IOS
Input Offset Current
-50
4
-75
IB
Input Bias Current
-575
-1500
Submit Document Feedback
5
-230
nA
nA
FN7957.3
May 19, 2016
ISL70218SEH, ISL70218SRH
Electrical Specifications VS ±15V, VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply over a total
ionizing dose of 100krad(Si) with exposure at a high dose rate of 50 - 300krad(Si)/s; and over a total ionizing dose of 50krad(Si) with exposure at a low
dose rate of <10mrad(Si)/s. (Continued)
SYMBOL
VCMIR
CMRR
PSRR
AVOL
PARAMETER
TEST CONDITIONS
Common-Mode Input Voltage Range
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Open-Loop Gain
Guaranteed by CMRR Test
VCM =
V-
VCM =
V-
MIN
(Note 6)
(V-)
TYP
MAX
(Note 6)
- 0.5
-1.8
V
V-
(V+)
- 1.8
V
to
V+
-1.8V
100
to
V+
-1.8V
97
VS = 3V to 40V, VCMIR = Valid Input
Voltage
105
RL = 10kΩ to ground VO = -13V to +13V
120
118
dB
dB
124
dB
100
dB
130
dB
115
VOH
VOL
IS
Output Voltage High,
V+
to VOUT
Output Voltage Low, VOUT to
V-
UNIT
(V+)
dB
RL = 10kΩ
RL = 10kΩ
Supply Current/Amplifier
0.85
110
mV
120
mV
70
mV
80
mV
1.1
mA
1.4
mA
IS+
Source Current Capability
10
mA
IS-
Sink Current Capability
10
mA
VSUPPLY
Supply Voltage Range
Guaranteed by PSRR
GBW
Gain Bandwidth Product
ACL = 101, VOUT = 100mVP-P;
RL = 2kΩ
enp-p
Voltage Noise
0.1Hz to 10Hz, VS = ±18V
3
40
V
AC SPECIFICATIONS
4
MHz
300
nVP-P
en
Voltage Noise Density
f = 10Hz, VS = ±18V
8.5
nV/Hz
en
Voltage Noise Density
f = 100Hz, VS = ±18V
5.8
nV/Hz
en
Voltage Noise Density
f = 1kHz, VS = ±18V
5.6
nV/Hz
en
Voltage Noise Density
f = 10kHz, VS = ±18V
5.6
nV/Hz
in
Current Noise Density
f = 1kHz, VS = ±18V
355
fA/Hz
Total Harmonic Distortion + Noise
1kHz, G = 1, VO = 3.5VRMS,
RL = 10kΩ
0.0003
%
±1.2
V/µs
THD + N
TRANSIENT RESPONSE
SR
Slew Rate
AV = 1, RL = 2kΩ, VO = 10VP-P
±1.0
±0.4
tr, tf, Small Signal
Rise Time 10% to 90% of VOUT
AV = 1, VOUT = 100mVP-P, Rf = 0Ω,
RL = 2kΩ to VCM
100
AV = 1, VOUT = 100mVP-P, Rf = 0Ω,
RL = 2kΩ to VCM
100
Settling Time to 0.01% 10V Step; 10% to
VOUT
AV = 1, VOUT = 10VP-P, Rf = 0Ω
RL = 2kΩ to VCM
8.5
Positive Overshoot
AV = 1, VOUT = 10VP-P, Rf = 0Ω
RL = 2kΩ to VCM
5
Fall Time 90% to 10% of VOUT
ts
OS+
V/µs
Submit Document Feedback
6
230
ns
400
ns
200
ns
400
ns
µs
%
35
%
FN7957.3
May 19, 2016
ISL70218SEH, ISL70218SRH
Electrical Specifications VS ±15V, VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply over a total
ionizing dose of 100krad(Si) with exposure at a high dose rate of 50 - 300krad(Si)/s; and over a total ionizing dose of 50krad(Si) with exposure at a low
dose rate of <10mrad(Si)/s. (Continued)
SYMBOL
OS-
PARAMETER
Negative Overshoot
Electrical Specifications
temperature range, -55°C to +125°C.
SYMBOL
VOS
TEST CONDITIONS
MIN
(Note 6)
AV = 1, VOUT = 10VP-P, Rf = 0Ω
RL = 2kΩto VCM
TYP
MAX
(Note 6)
5
UNIT
%
35
%
VS ±5V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply over the operating
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
Offset Voltage
40
µV
Input Offset Voltage Match Channel to
Channel
44
µV
IOS
Input Offset Current
4
nA
IB
Input Bias Current
-230
nA
VOS
VCMIR
Common-Mode Input Voltage Range
Guaranteed by CMRR Test
(V-) - 0.5
(V+) - 1.8
V
V-
(V+) - 1.8
V
CMRR
Common-Mode Rejection Ratio
VCM = V- - 0.5V to V+ - 1.8
VCM = V- to V+ - 1.8V
117
dB
PSRR
Power Supply Rejection Ratio
VS = 3V to 40V,
VCMIR = Valid Input Voltage
124
dB
AVOL
Open-Loop Gain
RL = 10kΩ to ground
VO = -3V to +3V
130
dB
VOH
Output Voltage High,
V+ to VOUT
RL = 10kΩ
65
mV
70
mV
Output Voltage Low,
VOUT to V-
RL = 10kΩ
38
mV
45
mV
VOL
IS
Supply Current/Amplifier
0.85
mA
IS+
Source Current Capability
8
mA
IS-
Sink Current Capability
8
mA
GBW
Gain Bandwidth Product
3.2
MHz
enp-p
Voltage Noise
0.1Hz to 10Hz
320
nVP-P
en
Voltage Noise Density
f = 10Hz
9
nV/Hz
en
Voltage Noise Density
f = 100Hz
5.7
nV/Hz
en
Voltage Noise Density
f = 1kHz
5.5
nV/Hz
en
Voltage Noise Density
f = 10kHz
5.5
nV/Hz
in
Current Noise Density
f = 1kHz
380
fA/Hz
Total Harmonic Distortion + Noise
1kHz, G = 1, VO = 1.25VRMS, RL = 10kΩ
0.0003
%
±1
V/µs
AC SPECIFICATIONS
THD + N
TRANSIENT RESPONSE
SR
Slew Rate
Submit Document Feedback
AV = 1, RL = 2kΩVO = 4VP-P
7
FN7957.3
May 19, 2016
ISL70218SEH, ISL70218SRH
Electrical Specifications
VS ±5V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply over the operating
temperature range, -55°C to +125°C. (Continued)
SYMBOL
tr, tf, Small Signal
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
MAX
(Note 6)
TYP
UNIT
Rise Time 10% to 90% of VOUT
AV = 1, VOUT = 100mVP-P , Rf = 0Ω,
RL = 2kΩ to VCM
100
ns
Fall Time 90% to 10% of VOUT
AV = 1, VOUT = 100mVP-P , Rf = 0Ω,
RL = 2kΩ to VCM
100
ns
Settling Time to 0.01%
4V Step; 10% to VOUT
AV = 1, VOUT = 4VP-P, Rf = 0Ω
RL = 2kΩ to VCM
4
µs
OS+
Positive Overshoot
AV = 1, VOUT = 10VP-P, Rf = 0Ω
RL = 2kΩ to VCM
5
%
OS-
Negative Overshoot
AV = 1, VOUT = 10VP-P, Rf = 0Ω
RL = 2kΩ to VCM
5
%
ts
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
High Dose Rate Post Radiation Characteristics VS ±15V, VCM = 0V, VO = 0V, RL = Open, TA= +25°C, unless otherwise
noted. This data is typical test data post radiation exposure at a rate of 50 to 300rad(Si)/s. This data is intended to show typical parameter shifts due to
high dose rate radiation. These are not limits nor are they guaranteed.
SYMBOL
PARAMETER
TEST CONDITIONS
50k RAD
75k RAD
100k RAD
UNIT
VOS
Offset Voltage
35
35
35
µV
IOS
Input Offset Current
2
3
5
nA
IB
Input Bias Current
200
400
575
nA
CMRR
Common-Mode Rejection Ration
VCM = -13V to +13V
129
128
127
dB
PSRR
Power Supply Rejection Ratio
VS = ±2.25V to ±15V
130
130
130
dB
AVOL
Open-Loop Gain
VO = -13V to +13V
RL = 10kΩ to ground
131.6
131.1
131.1
dB
VOH
Output Voltage High
V+ to VOUT
RL = 10kΩ to ground
71
74
76
mV
VOL
Output Voltage Low
VOUT to V-
RL = 10kΩ to ground
54
57
59
mV
830
830
830
µA
1.24
1.23
1.22
V/µs
IS
Supply Current/Amplifier
TRANSIENT RESPONSE
SR
Slew Rate
AV = 10, RL = 2kΩVO = 4VP-P
Low Dose Rate Post Radiation Characteristics
VS ±15V, VCM = 0V, VO = 0V, RL = Open, TA= +25°C, unless otherwise
noted. This data is typical test data post radiation exposure at a rate of 10mrad(Si)/s. This data is intended to show typical parameter shifts due to low
dose rate radiation. These are not limits nor are they guaranteed.
SYMBOL
PARAMETER
TEST CONDITIONS
10k RAD
20k RAD
50k RAD
UNIT
VOS
Offset Voltage
20
20
20
µV
IOS
Input Offset Current
6
8
10
nA
IB
Input Bias Current
300
500
1200
nA
IS
Supply Current/Amplifier
650
625
615
µA
Submit Document Feedback
8
FN7957.3
May 19, 2016
ISL70218SEH, ISL70218SRH
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, TA= +25°C, unless otherwise specified.
100
400
90
300
80
+125°C
200
60
VS = ±15V
50
40
|VOS (µV)|
70
VOS (µV)
+25°C
30
100
0
-100
-40°C
-200 -55°C
20
VS = ±5V
10
0
-60
-40
-20
0
20
-300
40
60
80
-400
-16
100 120 140 160
-15
TEMPERATURE (°C)
FIGURE 3. VOS vs TEMPERATURE
-14
-13 13
14
15
FIGURE 4. INPUT OFFSET VOLTAGE vs INPUT COMMON-MODE
VOLTAGE, VS = ±15V
-150
0
-50
VS = +40V
-200
-100
VS = +30V
-200
IBIAS (nA)
IBIAS (nA)
-150
-250
-300
-250
-300
VS = +3.0V
-350
-350
-400
VS = +4.5V
-450
-500
-400
-60
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
VS (V)
130
128
128
126
126
CHANNEL-A
120
118
CMRR (dB)
CMRR (dB)
132
130
122
40
60
80
100
120
140
CHANNEL-A
122
120
CHANNEL-B
118
114
112
112
20 40 60 80 100 120 140 160
TEMPERATURE (°C)
FIGURE 7. CMRR vs TEMPERATURE, VS = ±15V
Submit Document Feedback
20
116
CHANNEL-B
0
0
124
114
110
-60 -40 -20
-20
FIGURE 6. IBIAS vs TEMPERATURE vs SUPPLY
132
124
-40
VS = +10V
TEMPERATURE (°C)
FIGURE 5. IBIAS vs VS
116
16
INPUT COMMON-MODE VOLTAGE (V)
9
110
-60 -40 -20
0
20 40 60 80 100 120 140 160
TEMPERATURE (°C)
FIGURE 8. CMRR vs TEMPERATURE, VS = ±5V
FN7957.3
May 19, 2016
ISL70218SEH, ISL70218SRH
140
130
120
110
100
90
80
70
60
50
40
30 VS = ±15V
20 SIMULATION
10
0
1m 0.01 0.1 1
VS = ±15V, VCM = 0V, RL = Open, TA= +25°C, unless otherwise specified. (Continued)
140
135
130
PSRR (dB)
CMRR (dB)
Typical Performance Curves
125
120
115
110
105
100
-60
10 100 1k 10k 100k 1M 10M 100M 1G
FREQUENCY (Hz)
140
130
120
110
100
90
80
70
60
50
40 VS = ±15V
30 AV = 1
20 CL = 4pF
10 RL = 10k
0 VCM = 1VP-P
-10
10
100
PSRR+
PSRR-
1k
10k
100k
FREQUENCY (Hz)
1M
10M
140
130
120
110
100
90
80
70
60
50
40 VS = ±5V
30 AV = 1
20 CL = 4pF
10 RL = 10k
0 VCM = 1VP-P
-10
10
100
0
20 40 60 80 100 120 140 160
TEMPERATURE (°C)
PSRR+
PSRR-
1k
10k
100k
FREQUENCY (Hz)
70
60
PHASE
RF = 10kΩ, RG = 100Ω
40
30
20
ACL = 10
0
10 100 1k 10k 100k 1M 10M100M 1G
FREQUENCY (Hz)
FIGURE 13. OPEN-LOOP GAIN, PHASE vs FREQUENCY, VS = ±15V
Submit Document Feedback
10
VS = ±5V & ±15V
CL = 4pF
RL = 2k
VOUT = 100mVP-P
ACL = 100
10
1
10M
RF = 10kΩ, RG = 10Ω
ACL = 1000
50
GAIN
1M
FIGURE 12. PSRR vs FREQUENCY, VS = ±5V
GAIN (dB)
GAIN (dB)
FIGURE 11. PSRR vs FREQUENCY, VS = ±15V
200
180
160
140
120
100
80
60
40
20
0
-20
-40
-60 VS = ±15V
-80 RL = 1MΩ
-100
1m 0.01 0.1
-20
FIGURE 10. PSRR vs TEMPERATURE, VS = ±15V
PSRR (dB)
PSRR (dB)
FIGURE 9. CMRR vs FREQUENCY, VS = ±15V
-40
-10
100
RF = 10kΩ, RG = 1kΩ
ACL = 1
RF = 0, RG = ∞
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 14. FREQUENCY RESPONSE vs CLOSED LOOP GAIN
FN7957.3
May 19, 2016
ISL70218SEH, ISL70218SRH
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, TA= +25°C, unless otherwise specified. (Continued)
1
0
0
-1
-1
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
1
-2
-3
-4
RL = OPEN, 100k, 10k
-5
RL = 1k
RL = 499
RL = 100
VS = ±15V
CL = 4pF
-7
AV = +1
-8 VOUT = 100mVp-p
-6
-9
100
1k
RL = 49.9
10k
100k
1M
-2
-3
-4
RL = OPEN, 100k, 10k
-6
VS = ±5V
CL = 4pF
-7 A = +1
V
-8 VOUT = 100mVp-p
-9
100
10M
RL = 1k
RL = 499
RL = 100
-5
RL = 49.9
1k
10k
FIGURE 15. GAIN vs FREQUENCY vs RL, VS = ±15V
-1
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
0
-1
-2
-3
-4
VOUT = 10mVP-P
VS = ±5V
VOUT = 50mVP-P
CL = 4pF
-7 A = +1
V
-8 RL = INF
VOUT = 100mVP-P
-9
100
VOUT = 500mVP-P
VOUT = 1VP-P
1k
10k
100k
1M
-2
-3
VS = ±1.5V
-4
VS = ±5V
-5
-9
100
10M
1k
10k
40
38
VOH
VOH AND VOL (mV)
VOH AND VOL (mV)
42
70
60
50
40
-60
VOL
-40
-20
0
20 40 60 80 100 120 140 160
TEMPERATURE (°C)
FIGURE 19. OUTPUT OVERHEAD VOLTAGE vs TEMPERATURE,
VS = ±15V, RL = 10k
Submit Document Feedback
11
1M
10M
FIGURE 18. GAIN vs FREQUENCY vs SUPPLY VOLTAGE
VS = ±15V
RL = 10k
80
100k
FREQUENCY (Hz)
FIGURE 17. GAIN vs FREQUENCY vs OUTPUT VOLTAGE
90
VS = ±15V
-6 CL = 4pF
R = 10k
-7 L
AV = +1
-8 VOUT = 100mVP-P
FREQUENCY (Hz)
100
10M
1
0
-6
1M
FIGURE 16. GAIN vs FREQUENCY vs RL, VS = ±5V
1
-5
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
VS = ±5V
RL = 10k
VOH
36
34
32
30
28
26
24
VOL
22
20
-60
-40
-20
0
20 40 60 80 100 120 140 160
TEMPERATURE (°C)
FIGURE 20. OUTPUT OVERHEAD VOLTAGE vs TEMPERATURE,
VS = ±5V, RL = 10k
FN7957.3
May 19, 2016
ISL70218SEH, ISL70218SRH
Typical Performance Curves
1.0
VS = ±15V, VCM = 0V, RL = Open, TA= +25°C, unless otherwise specified. (Continued)
1.0
VS = ±5V AND ±15V
VS = ±5V AND ±15V
+125°C
0.01
0.01
-55°C
0.001
0.001
0.01
0.1
LOAD CURRENT (mA)
-55°C
1.0
10
0.001
0.001
-11
VOH
+125°C
+75°C
-40°C
-12
0°C
10
+125°C
+75°C
-55°C
-2
+25°C
-13
4 VS = ±5V
AV = 2
3 R = R = 100k
F
G
VIN = ±2.5V-DC
2
1
-1
VOL
VOH
1.0
5
14 V = ±15V
S
13 AV = 2
RF = RG = 100k
12 V = ±7.5V-DC
IN
11
-55°C
10
-10
VOL
0.1
FIGURE 22. OUTPUT OVERHEAD VOLTAGE LOW vs LOAD CURRENT, VS
= ±5V AND ±15V
15
0°C
-40°C
-3
+25°C
-4
-14
0
2
4
6
8
10 12 14 16
I-FORCE (mA)
18
20
22
-5
24
FIGURE 23. OUTPUT VOLTAGE SWING vs LOAD CURRENT, VS = ±15V
0
2
4
6
8
10 12 14 16
I-FORCE (mA)
18
20
22
24
FIGURE 24. OUTPUT VOLTAGE SWING vs LOAD CURRENT, VS = ±5V
1600
VS = ±21V
1200
1000
VS = ±15V
800
VS = ±2.25V
600
ISUPPLY PER AMPLIFIER (µA)
1100
1400
CURRENT (µA)
0.01
LOAD CURRENT (mA)
FIGURE 21. OUTPUT OVERHEAD VOLTAGE HIGH vs LOAD CURRENT,
VS = ±5V AND ±15V
-15
+25°C
0.1
VOL - V- (V)
0.1
V+ - VOH (V)
+125°C
+25°C
1000
900
800
700
600
500
400
300
200
100
400
-60
-40
-20
0
20
40
60
80
100 120 140 160
TEMPERATURE (°C)
FIGURE 25. SUPPLY CURRENT vs TEMPERATURE vs SUPPLY
VOLTAGE
Submit Document Feedback
12
0
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42
VSUPPLY (V)
FIGURE 26. SUPPLY CURRENT vs SUPPLY VOLTAGE
FN7957.3
May 19, 2016
ISL70218SEH, ISL70218SRH
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, TA= +25°C, unless otherwise specified. (Continued)
INPUT NOISE VOLTAGE
10
10
INPUT NOISE CURRENT
1
0.1
0.1
1
10
100
1k
10k
1
INPUT NOISE VOLTAGE (nV/√Hz)
INPUT NOISE CURRENT (fA/√Hz)
INPUT NOISE VOLTAGE (nV/√Hz)
100
100
VS = ±18V
0.1
100k
100
VS = ±5V
INPUT NOISE VOLTAGE
10
10
INPUT NOISE CURRENT
1
1
0.1
0.1
1
10
100
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
500
VS = ±18V
AV = 10k
400
300
INPUT NOISE VOLTAGE (nV)
INPUT NOISE VOLTAGE (nV)
500
200
100
0
-100
-200
-300
-400
VS = ±5V
AV = 10k
400
300
200
100
0
-100
-200
-300
-400
-500
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
TIME (s)
0.1
VS = ±15V
CL = 4pF
RL = 2k
VOUT = 10VP-P
-55°C
AV = 10
+25°C
+125°C
0.01 C-WEIGHTED
22Hz TO 500kHz
0.001
0.0001
10
-55°C
+25°C
+125°C
AV = 1
100
1k
FREQUENCY (Hz)
10k
100k
FIGURE 31. THD+N vs FREQUENCY vs TEMPERATURE, AV = 1, 10,
RL = 2k
Submit Document Feedback
13
5
6
7
8
9
10
FIGURE 30. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz, VS = ±5V
THD + N (%)
0.1
4
TIME (s)
FIGURE 29. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz, VS = ±18V
THD + N (%)
0.1
100k
10k
FIGURE 28. INPUT NOISE VOLTAGE (en) AND CURRENT (in) vs
FREQUENCY, VS = ±5V
FIGURE 27. INPUT NOISE VOLTAGE (en) AND CURRENT (in) vs
FREQUENCY, VS = ±18V
-500
INPUT NOISE CURRENT (fA/√Hz)
100
VS = ±15V
CL = 4pF
RL = 10k
VOUT = 10VP-P
0.01 C-WEIGHTED
22Hz TO 500kHz
-55°C
AV = 10
+25°C
+125°C
0.001
+25°C
0.0001
10
AV = 1
+125°C
100
1k
-55°C
10k
100k
FREQUENCY (Hz)
FIGURE 32. THD+N vs FREQUENCY vs TEMPERATURE, AV = 1, 10,
RL = 10k
FN7957.3
May 19, 2016
ISL70218SEH, ISL70218SRH
Typical Performance Curves
THD + N (%)
VS = ±15V
CL = 4pF
RL = 2k
0.1 f = 1kHz
1.0
VS = ±15V
CL = 4pF
RL = 10k
0.1 f = 1kHz
C-WEIGHTED
22Hz TO 22kHz
AV = 10
-55°C
0.01
+25°C
+125°C
0.001
0.0001
C-WEIGHTED
22Hz TO 22kHz
AV = 10
THD + N (%)
1.0
VS = ±15V, VCM = 0V, RL = Open, TA= +25°C, unless otherwise specified. (Continued)
-55°C
0.01
+125°C
0.001
0
+125°C
+25°C
10
5
15
AV = 1 -55°C
20
25
30
0.0001
0
+25°C
10
5
VOUT (VP-P)
FIGURE 33. THD+N vs OUTPUT VOLTAGE (VOUT) vs TEMPERATURE,
AV = 1, 10, RL = 2k
+125°C
15
20
VOUT (VP-P)
AV = 1
-55°C
25
30
FIGURE 34. THD+N vs OUTPUT VOLTAGE (VOUT) vs TEMPERATURE,
AV = 1, 10, RL = 10k
6
2.4
VS = ±15V
AV = 1
4
RL = 2k
CL = 4pF
2
VS = ±5V
AV = 1
RL = 2k
CL = 4pF
2.0
1.6
1.2
0.8
0.4
VOUT (V)
VOUT (V)
+25°C
0
0
-0.4
-2
-0.8
-1.2
-4
-6
-1.6
-2.0
-2.4
0
10
20
30
40
50
60
TIME (µs)
70
80
90
FIGURE 35. LARGE SIGNAL 10V STEP RESPONSE, VS = ±15V
100
VOUT (V)
40
20
0
-20
-40
-60
-80
-100
20
30
40
50
60
TIME (µs)
70
80
90
100
VS = ±5V
VIN = ±5.9V
5
INPUT AND OUTPUT (V)
60
10
FIGURE 36. LARGE SIGNAL 4V STEP RESPONSE, VS = ±5V
6
VS = ±15V
AND
VS = ±5V
AV = 1
RL = 2k
CL = 4pF
80
0
100
4
INPUT
3
2
1
OUTPUT
0
-1
-2
-3
-4
-5
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
TIME (µs)
FIGURE 37. SMALL SIGNAL TRANSIENT RESPONSE,
VS = ±5V, ±15V
Submit Document Feedback
14
1.8
2
-6
0
1
2
TIME (ms)
3
4
FIGURE 38. NO PHASE REVERSAL
FN7957.3
May 19, 2016
ISL70218SEH, ISL70218SRH
12
OUTPUT
-40
-4
-80
-8
-120
80
8
40
4
-160
0
40
-200
0
4
8
12
16
20
24
TIME (µs)
28
32
36
6
VS = ±5V
AV = 100
5
RL = 10k
VIN = 50mVP-P
OVERDRIVE = 1V 4
INPUT
40
OUTPUT
1
-50
0
40
-60
0
20
24
28
32
36
0
-30
-3
OUTPUT
-40
INPUT
0
4
8
12
TIME (µs)
16
20
24
-4
VS = ±5V
AV = 100
RL = 10k
-5
VIN = 50mVP-P
OVERDRIVE = 1V
-6
28
32
36
40
TIME (µs)
FIGURE 41. POSITIVE OUTPUT OVERLOAD RESPONSE TIME,
VS = ±5V
FIGURE 42. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME,
VS = ±5V
100
100
VS = ±15V
VS = ±5V
AV = 10
10
AV = 10
10
AV = 100
AV = 100
ZOUT (Ω)
ZOUT (Ω)
24
-2
10
16
20
-20
2
12
16
-1
20
8
12
-10
3
4
8
0
30
0
4
FIGURE 40. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME,
VS = ±15V
OUTPUT (V)
50
0
-12
VS = ±15V
AV = 100
-16
RL = 10k
VIN = 100mVP-P
OVERDRIVE = 1V
-20
28
32
36
40
TIME (µs)
FIGURE 39. POSITIVE OUTPUT OVERLOAD RESPONSE TIME,
VS = ±15V
60
OUTPUT
1
0.10
1
0.10
AV = 1
AV = 1
0.01
OUTPUT (V)
0
INPUT (mV)
INPUT (mV)
120
INPUT
INPUT (mV)
INPUT (mV)
160
0
0
20
VS = ±15V
AV = 100
RL = 10k
16
VIN = 100mVP-P
OVERDRIVE = 1V
INPUT
OUTPUT (V)
200
VS = ±15V, VCM = 0V, RL = Open, TA= +25°C, unless otherwise specified. (Continued)
OUTPUT (V)
Typical Performance Curves
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 43. OUTPUT IMPEDANCE vs FREQUENCY, VS = ±15V
Submit Document Feedback
15
0.01
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 44. OUTPUT IMPEDANCE vs FREQUENCY, VS = ±5V
FN7957.3
May 19, 2016
ISL70218SEH, ISL70218SRH
Typical Performance Curves
OVERSHOOT (%)
50
60
VS = ±15V
VOUT = 100mVP-P
50
AV = 1
OVERSHOOT (%)
60
VS = ±15V, VCM = 0V, RL = Open, TA= +25°C, unless otherwise specified. (Continued)
40
AV = 10
AV = -1
30
20
AV = 1
40
0.010
0.100
1
10
20
0
0.001
100
0.01
LOAD CAPACITANCE (nF)
10
100
30
VS = ±15V
28 R = 10k
L
26
VS = ±15V
AV = 1
24
ISC-SINK
22
20
18
16
14
ISC-SOURCE
12
10k
100k
FREQUENCY (Hz)
FIGURE 47. IMAX OUTPUT VOLTAGE vs FREQUENCY
Submit Document Feedback
1
FIGURE 46. OVERSHOOT vs CAPACITIVE LOAD, VS = ±5V
ISC (mA)
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0
1k
0.1
LOAD CAPACITANCE (nF)
FIGURE 45. OVERSHOOT vs CAPACITIVE LOAD, VS = ±15V
VOUT (VP-P)
AV = 10
AV = -1
30
10
10
0
0.001
VS = ±5V
VOUT = 100mVP-P
16
1M
10
-60
-40
-20
0
20 40 60 80 100 120 140 160
TEMPERATURE (°C)
FIGURE 48. SHORT-CIRCUIT CURRENT vs TEMPERATURE,
VS = ±15V
FN7957.3
May 19, 2016
ISL70218SEH, ISL70218SRH
Applications Information
V+
Functional Description
The ISL70218SEH, ISL70218SRH are dual, 3.2MHz, single or
dual supply, rail-to-rail output amplifiers with a common-mode
input voltage range extending to a range of 0.5V below the V- rail.
The input stage is optimized for precision sensing of
ground-referenced signals in single-supply applications. The input
stage is able to handle large input differential voltages without
phase inversion, making this amplifier suitable for high-voltage
comparator applications. The bipolar design features high open
loop gain and excellent DC input and output temperature
stability. This op amp features very low quiescent current of
850µA, and low temperature drift. The devices are fabricated in
a new precision 40V complementary bipolar DI process and is
immune from latch-up for up to a 36V supply range.
Operating Voltage Range
The op amps are designed to operate over a single supply range of
3V to 36V or a split supply voltage range of +1.8V/-1.2V to ±18V.
The device is fully characterized at 30V (±15V). Both DC and AC
performance remain virtually unchanged over the complete
operating voltage range. Parameter variation with operating
voltage is shown in the “Typical Performance Curves” beginning
on page 9.
The input common-mode voltage to the V+ rail (V+ - 1.8V across the
full temperature range) may limit amplifier operation when
operating from split V+ and V- supplies. Figure 4 shows the
common-mode input voltage range variation over temperature.
Input Stage Performance
The ISL70218SEH, ISL70218SRH PNP input stage has a
common-mode input range extending up to 0.5V below ground at
+25°C. Full amplifier performance is guaranteed for input voltage
down to ground (V-) across the -55°C to +125°C temperature
range. For common-mode voltages down to -0.5V below ground
(V-), the amplifiers are fully functional, but performance degrades
slightly over the full temperature range. This feature provides
excellent CMRR, AC performance, and DC accuracy when
amplifying low-level, ground-referenced signals.
The input stage has a maximum input differential voltage equal
to a diode drop greater than the supply voltage and does not
contain the back-to-back input protection diodes found on many
similar amplifiers. This feature enables the device to function as
a precision comparator by maintaining very high input
impedance for high-voltage differential input comparator
voltages. The high differential input impedance also enables the
device to operate reliably in large signal pulse applications,
without the need for anti-parallel clamp diodes required on
MOSFET and most bipolar input stage op amps. Thus, input
signal distortion caused by nonlinear clamps under high slew
rate conditions is avoided.
In applications in which one or both amplifier input terminals are
at risk of exposure to voltages beyond the supply rails,
current-limiting resistors may be needed at each input terminal
(see Figure 49, RIN+, RIN-) to limit current through the
power-supply ESD diodes to 20mA.
Submit Document Feedback
17
VINVIN+
RIN-
-
RIN+
+
RF
RL
RG
V-
FIGURE 49. INPUT ESD DIODE CURRENT LIMITING
Output Drive Capability
The bipolar rail-to-rail output stage features low saturation levels
that enable an output voltage swing to less than 15mV when the
total output load (including feedback resistance) is held below
50µA (Figures 21 and 22). With ±15V supplies, this can be
achieved by using feedback resistor values >300kΩ.
The output stage is internally current limited. Output current limit
over temperature is shown in Figures 23 and 24. The amplifiers
can withstand a short-circuit to either rail as long as the power
dissipation limits are not exceeded. This applies to only one
amplifier at a time for the dual op amp. Continuous operation
under these conditions may degrade long-term reliability.
The amplifiers perform well when driving capacitive loads
(Figures 45 and 46). The unity gain, voltage follower (buffer)
configuration provides the highest bandwidth but is also the
most sensitive to ringing produced by load capacitance found in
BNC cables. Unity gain overshoot is limited to 35% at
capacitance values to 0.33nF. At gains of 10 and higher, the
device is capable of driving more than 10nF without significant
overshoot.
Output Phase Reversal
Output phase reversal is a change of polarity in the amplifier
transfer function when the input voltage exceeds the supply
voltage. The ISL70218SEH, ISL70218SRH are immune to output
phase reversal out to 0.5V beyond the rail (VABS MAX) limit (see
Figure 38 on page 14).
Single Channel Usage
The ISL70218SEH, ISL70218SRH are dual op amps. If the
application requires only one channel, the user must configure
the unused channel to prevent it from oscillating. The unused
channel oscillates if the input and output pins are floating. This
results in higher-than-expected supply currents and possible
noise injection into the channel being used. The proper way to
prevent oscillation is to short the output to the inverting input,
and ground the positive input (Figure 50).
+
FIGURE 50. PREVENTING OSCILLATIONS IN UNUSED CHANNELS
FN7957.3
May 19, 2016
ISL70218SEH, ISL70218SRH
Power Dissipation
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power supply conditions. It
is therefore important to calculate the maximum junction
temperature (TJMAX) for all applications to determine if power
supply voltages, load conditions, or package type need to be
modified to remain in the safe operating area. These parameters
are related using Equation 1:
T JMAX = T MAX +  JA xPD MAXTOTAL
(EQ. 1)
Where
• PDMAXTOTAL is the sum of the maximum power dissipation of
each amplifier in the package (PDMAX)
• TMAX = Maximum ambient temperature
• ΘJA = Thermal resistance of the package
PDMAX for each amplifier can be calculated using Equation 2:
V OUTMAX
PD MAX = V S  I qMAX +  V S - V OUTMAX   ---------------------------R
(EQ. 2)
L
Where
• PDMAX = Maximum power dissipation of one amplifier
• VS = Total supply voltage
• IqMAX = Maximum quiescent supply current of one amplifier
• VOUTMAX = Maximum output voltage swing of the application
• RL = Load resistance
Submit Document Feedback
18
FN7957.3
May 19, 2016
ISL70218SEH, ISL70218SRH
Package Characteristics
Weight of Packaged Device
0. 4029 grams (Typical)
TOP METALLIZATION
Type: AlCu (99.5%/0.5%)
Thickness: 30kÅ
BACKSIDE FINISH
Lid Characteristics
Silicon
Finish: Gold
Case Isolation to Any Lead: 20 x 109 Ω (min)
Die Characteristics
Die Dimensions
PROCESS
Dielectrically Isolated Complementary Bipolar - PR40
ASSEMBLY RELATED INFORMATION
SUBSTRATE POTENTIAL
1565µm x 2125µm (62 mils x 84 mils)
Thickness: 355µm ±25µm (14 mils ±1 mil)
Interface Materials
Floating
ADDITIONAL INFORMATION
WORST CASE CURRENT DENSITY
GLASSIVATION
< 2 x 105 A/cm2
Type: Nitrox
Thickness: 15kÅ
Metallization Mask Layout
V+
OUT_A
OUT_B
PLACE HOLDER
-IN_A
-IN_B
+IN_A
+IN_B
V-
Submit Document Feedback
19
FN7957.3
May 19, 2016
ISL70218SEH, ISL70218SRH
TABLE 1. DIE LAYOUT X-Y COORDINATES
PAD NAME
PAD NUMBER
X
(µm)
Y
(µm)
dX
(µm)
dY
(µm)
BOND WIRES
PER PAD
OUT_A
1
16.5
1670
70
70
1
-IN_A
6
-3
1015
70
70
1
+IN_A
7
-3
771
70
70
1
V-
8
0
0
70
70
1
+IN_B
12
1287
719.5
70
70
1
-IN_B
11
1287
963.5
70
70
1
OUT_B
10
1267.5
1115.5
70
70
1
V+
9
1284
1746.5
70
70
1
NOTE:
7. Origin of coordinates is the centroid of pad 8.
Submit Document Feedback
20
FN7957.3
May 19, 2016
ISL70218SEH, ISL70218SRH
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please go to web to make sure you have the latest revision.
DATE
REVISION
CHANGE
May 19, 2016
FN7957.3
Added ISL70218SRH information to datasheet.
Removed Pb-Free Reflow Profile information from Thermal Information section as it is not applicable to
hermetic packages.
July 24, 2014
FN7957.2
Updated Features on page 1, Radiation Tolerance bullet as follows:
from
• Radiation Tolerance
- SEL/SEB LETTH (VS = ±18V). . . . . . . . . . 86.4 MeV*cm2/mg
- High Dose Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 100krad(Si)
- Low Dose Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 100krad(Si)
to
• Radiation tolerance
- High dose rate (50-300rad(Si)/s) . . . . . . . . . . . 100krad(Si)
- Low dose rate (0.01rad(Si)/s) . . . . . . . . . . . . . 100krad(Si)*
- SEB LETTH (VS = ±18V) . . . . . . . . . . . . . . 86.4 MeV•cm2/mg
- SEL Immune (SOI Process)
Updated the Ordering Information table on page 3 as follows:
- Removed MSL note.
- Added SMD ordering note.
Replaced the Products verbiage with the About Intersil Verbiage on page 21.
August 24, 2012
FN7957.1
1. Electrical Specification tables (pages 3-6), added specs on overshoot and rise/fall times.
2. Page 3 - Added Abs Max in a non radiation environment
Changed ESD HBM from 3kV to 2kV
Changed ESD CDM from 2kV to 750V
February 16, 2012
FN7957.0
Initial Release
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
Submit Document Feedback
21
FN7957.3
May 19, 2016
ISL70218SEH, ISL70218SRH
Ceramic Metal Seal Flatpack Packages (Flatpack)
K10.A MIL-STD-1835 CDFP3-F10 (F-4A, CONFIGURATION B)
10 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
e
A
INCHES
A
-A-
D
-BPIN NO. 1
ID AREA
b
E1
0.004 M
H A-B S
Q
D S
S1
0.036 M
H A-B S
D S
C
E
-D-
A
-C-
-HL
E2
E3
SEATING AND
BASE PLANE
c1
L
E3
(c)
b1
M
M
(b)
SECTION A-A
MIN
MILLIMETERS
MAX
MIN
MAX
NOTES
A
0.045
0.115
1.14
2.92
-
b
0.015
0.022
0.38
0.56
-
b1
0.015
0.019
0.38
0.48
-
c
0.004
0.009
0.10
0.23
-
c1
0.004
0.006
0.10
0.15
-
D
-
0.290
-
7.37
3
E
0.240
0.260
6.10
6.60
-
E1
-
0.280
-
7.11
3
E2
0.125
-
3.18
-
-
E3
0.030
-
0.76
-
7
2
e
LEAD FINISH
BASE
METAL
SYMBOL
0.050 BSC
1.27 BSC
-
k
0.008
0.015
0.20
0.38
L
0.250
0.370
6.35
9.40
-
Q
0.026
0.045
0.66
1.14
8
S1
0.005
-
0.13
-
6
M
-
0.0015
-
0.04
-
N
10
10
Rev. 0 3/07
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark. Alternately, a tab (dimension k)
may be used to identify pin one.
2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply.
3. This dimension allows for off-center lid, meniscus, and glass
overrun.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the
leads.
8. Dimension Q shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension Q minimum
shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
Submit Document Feedback
22
FN7957.3
May 19, 2016