40V Extended Temperature Range, Precision Single-Supply, Rail-to-Rail Output, Operational Amplifier ISL28118M Features The ISL28118M is a single, low-power precision amplifier optimized for single-supply applications over the extended temperature range of -55°C to +125°C. This device features a common mode input voltage range extending to 0.5V below the V- rail, a rail-rail differential input voltage range for use as a comparator, and rail-to-rail output voltage swing, which makes it ideal for single-supply applications where input operation at ground is important. • Rail-to-Rail Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <10mV The ISL28118M features low power, low offset voltage, and low temperature drift, making it the ideal choice for applications requiring both high DC accuracy and AC performance. The op amp is designed to operate over a single supply range of 3V to 40V or a split supply voltage range of +1.8V/-1.2V to ±20V. The combination of precision and small footprint provides the user with outstanding value and flexibility relative to similar competitive parts. • Low Noise Current . . . . . . . . . . . . . . . . . . . . . . . . . . 355fA/√Hz Applications include precision instrumentation, data acquisition, precision power supply controls, and industrial controls. • Precision Instruments • Below-Ground (V-) Input Capability to -0.5V • Rail-to-Rail Input Differential Voltage Range for Comparator Applications • Single-Supply Range . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 40V • Low Current Consumption . . . . . . . . . . . . . . . . . . . . . . . 850µA • Low Noise Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6nV/√Hz • Low Input Offset Voltage . . . . . . . . . . . . . . . . . . . . 150µV Max. • Superb Offset Voltage Temperature Drift.. . . 1.2µV/°C, Max. • Operating Temperature Range. . . . . . . . . . .-55°C to +125°C • No Phase Reversal Applications • Medical Instrumentation • Data Acquisition The ISL28118M is offered in the 8 Ld MSOP package and operate over the extended temperature range of -55°C to +125°C. • Power Supply Control • Industrial Process Control RF IN- 10kΩ RIN+ IN+ 10kΩ V+ ISL28118M V- +3V to 40V 300 200 VOUT -55°C -40°C 100 + GAIN = 10 RREF+ VOS (µV) RINRSENSE 400 100kΩ LOAD +25°C +125°C 0 -100 -200 100kΩ -300 VREF -400 -16 -15 -14 -13 13 14 15 16 INPUT COMMON MODE VOLTAGE (V) FIGURE 1. TYPICAL APPLICATION: SINGLE-SUPPLY, LOW-SIDE CURRENT SENSE AMPLIFIER May 11, 2011 FN7858.0 1 FIGURE 2. INPUT OFFSET VOLTAGE vs INPUT COMMON MODE VOLTAGE, -40°C to +125°C, VS = ±15V CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL28118M ISL28118M (8 LD MSOP) TOP VIEW NC 1 8 NC -IN 2 7 V+ +IN 3 6 VOUT V- 4 5 NC - + Pin Descriptions ISL28118M (8 LD MSOP) PIN NAME EQUIVALENT CIRCUIT 3 +IN 1 Amplifier A non-inverting input 2 -IN 1 Amplifier A inverting input 6 VOUT 2 Amplifier A output 4 V- 3 Negative power supply 7 V+ 3 Positive power supply 1, 5, 8 NC - No Connect IN- DESCRIPTION V+ V+ IN+ OUT V- VCIRCUIT 1 V+ CAPACITIVELY TRIGGERED ESD CLAMP V- CIRCUIT 2 CIRCUIT 3 Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING ISL28118MUZ 8118M TEMPERATURE RANGE (°C) -55 to +125 PACKAGE (Pb-Free) 8 Ld MSOP PKG. DWG. # M8.118 NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information pages for ISL28118M. For more information on MSL, please see Technical Brief TB363. 2 FN7858.0 May 11, 2011 ISL28118M Absolute Maximum Ratings Thermal Information Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42V Maximum Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Maximum Differential Input Voltage . . . . . . . .42V or V- - 0.5V to V+ + 0.5V Min/Max Input Voltage . . . . . . . . . . . . . . . . . . .42V or V- - 0.5V to V+ + 0.5V Max/Min Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA Output Short-Circuit Duration (1 output at a time) . . . . . . . . . . . . . . Indefinite ESD Tolerance Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 3kV Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . . 300V Charged Device Model (Tested per CDM-22CI0ID) . . . . . . . . . . . . . . . 2kV Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 8 Ld MSOP Package (Notes 4, 5) . . . . . . . . . 165 57 Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Ambient Operating Temperature Range . . . . . . . . . . . . . .-55°C to +125°C Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . .+150°C Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 3V (+1.8V/-1.2V) to 40V (±20V) CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. For θJC, the “case temp” location is taken at the package top center. Electrical Specifications VS ±15V, VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply over the operating temperature range, -55°C to +125°C. Temperature data established by characterization. MIN PARAMETER VOS DESCRIPTION CONDITIONS Input Offset Voltage (Note 6) TYP MAX (Note 6) UNIT -150 25 150 µV 270 µV 1.2 µV/°C -270 TCVOS Input Offset Voltage Temperature Coefficient -1.2 0.2 IB Input Bias Current -575 -230 nA -800 TCIB Input Bias Current Temperature Coefficient IOS Input Offset Current nA -0.8 -50 4 -75 CMRR Common-Mode Rejection Ratio VCM = V- - 0.5V to V+ - 1.8V VCM = V- to V+ -1.8V 102 nA/°C 50 nA 75 nA 118 dB 118 dB 97 VCMIR Common Mode Input Voltage Range Guaranteed by CMRR test dB V- - 0.5 V+ - 1.8 V V- V+ - 1.8 V PSRR Power Supply Rejection Ratio VS = 3V to 40V, VCMIR = Valid Input Voltage 109 AVOL Open-Loop Gain VO = -13V to +13V, RL = 10kΩ to ground 120 124 dB 136 dB 105 dB 114 VOL VOH IS ISC+ Output Voltage Low, VOUT to V- RL = 10kΩ Output Voltage High, V+ to VOUT RL = 10kΩ Supply Current/Amplifier RL = Open Output Short Circuit Source Current 3 RL = 10Ω to V- dB 0.85 16 70 mV 85 mV 110 mV 120 mV 1.2 mA 1.6 mA mA FN7858.0 May 11, 2011 ISL28118M Electrical Specifications VS ±15V, VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply over the operating temperature range, -55°C to +125°C. Temperature data established by characterization. (Continued) MIN PARAMETER DESCRIPTION (Note 6) CONDITIONS ISC- Output Short Circuit Sink Current RL = 10Ω to V+ VSUPPLY Supply Voltage Range Guaranteed by PSRR MAX (Note 6) TYP 28 UNIT mA 3 40 V AC SPECIFICATIONS GBWP Gain Bandwidth Product ACL = 101, VOUT = 100mVP-P; RL = 2k 4 MHz enp-p Voltage Noise 0.1Hz to 10Hz, VS = ±18V 300 nVP-P en Voltage Noise Density f = 10Hz, VS = ±18V 8.5 nV/√Hz en Voltage Noise Density f = 100Hz, VS = ±18V 5.8 nV/√Hz en Voltage Noise Density f = 1kHz, VS = ±18V 5.6 nV/√Hz en Voltage Noise Density f = 10kHz, VS = ±18V 5.6 nV/√Hz in Current Noise Density f = 1kHz, VS = ±18V 355 fA/√Hz THD + N Total Harmonic Distortion + Noise 1kHz, G = 1, VO = 3.5VRMS, RL = 10kΩ 0.0003 % TRANSIENT RESPONSE SR Slew Rate AV = 1, RL = 2kΩ, VO = 10VP-P ±1.2 V/µs tr, tf, Small Signal Rise Time 10% to 90% of VOUT AV = 1, VOUT = 100mVP-P, Rf = 0Ω, RL = 2kΩ to VCM 100 ns Fall Time 90% to 10% of VOUT AV = 1, VOUT = 100mVP-P, Rf = 0Ω, RL = 2kΩ to VCM 100 ns Settling Time to 0.01% 10V Step; 10% to VOUT AV = 1, VOUT = 10VP-P, Rf = 0Ω RL = 2kΩ to VCM 8.5 µs ts Electrical Specifications VS ±5V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply over the operating temperature range, -55°C to +125°C. Temperature data established by characterization. (Note 6) TYP MAX (Note 6) UNIT -150 25 150 µV 270 µV 1.2 µV/°C MIN PARAMETER VOS DESCRIPTION CONDITIONS Input Offset Voltage -270 TCVOS Input Offset Voltage Temperature Coefficient -1.2 0.2 IB Input Bias Current -575 -230 nA -800 TCIB Input Bias Current Temperature Coefficient IOS Input Offset Current nA -0.8 -50 4 -75 CMRR Common-Mode Rejection Ratio VCM = V- - 0.5V to V+ - 1.8V VCM = V- to V+ -1.8V 101 nA/°C 50 nA 75 nA 119 dB 117 dB 96 VCMIR PSRR Common Mode Input Voltage Range Guaranteed by CMRR test Power Supply Rejection Ratio VS = 3V to 10V, VCMIR = Valid Input Voltage V- - 0.5 V+ - 1.8 V V- V+ - 1.8 V 108 103 4 dB 124 dB dB FN7858.0 May 11, 2011 ISL28118M Electrical Specifications VS ±5V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply over the operating temperature range, -55°C to +125°C. Temperature data established by characterization. (Continued) MIN PARAMETER AVOL DESCRIPTION Open-Loop Gain CONDITIONS VO = -3V to +3V, RL = 10kΩ to ground (Note 6) TYP 120 132 MAX (Note 6) dB 110 VOL UNIT dB Output Voltage Low, VOUT to V- RL = 10kΩ Output Voltage High, V+ to VOUT RL = 10kΩ IS Supply Current/Amplifier RL = Open ISC+ Output Short Circuit Source Current RL = 10Ω to V- 13 mA ISC- Output Short Circuit Sink Current RL = 10Ω to V+ 20 mA VOH 0.85 38 mV 45 mV 65 mV 70 mV 1.1 mA 1.4 mA AC SPECIFICATIONS GBWP Gain Bandwidth Product ACL = 101, VOUT = 100mVP-P; RL = 2k 3.2 MHz enp-p Voltage Noise 0.1Hz to 10Hz 320 nVP-P en Voltage Noise Density f = 10Hz 9 nV/√Hz en Voltage Noise Density f = 100Hz 5.7 nV/√Hz en Voltage Noise Density f = 1kHz 5.5 nV/√Hz en Voltage Noise Density f = 10kHz 5.5 nV/√Hz in Current Noise Density f = 1kHz 380 fA/√Hz THD + N Total Harmonic Distortion + Noise 1kHz, G = 1, VO = 1.25VRMS, RL = 10kΩ 0.0003 % TRANSIENT RESPONSE SR Slew Rate AV = 1, RL = 2kΩ, VO = 4VP-P ±1 V/µs tr, tf, Small Signal Rise Time 10% to 90% of VOUT AV = 1, VOUT = 100mVP-P , Rf = 0Ω, RL = 2kΩ to VCM 100 ns Fall Time 90% to 10% of VOUT AV = 1, VOUT = 100mVP-P , Rf = 0Ω, RL = 2kΩ to VCM 100 ns Settling Time to 0.01% 4V Step; 10% to VOUT AV = 1, VOUT = 4VP-P, Rf = 0Ω RL = 2kΩ to VCM 4 µs ts NOTE: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 5 FN7858.0 May 11, 2011 ISL28118M Typical Performance Curves 70 FIGURE 3. ISL28118M INPUT OFFSET VOLTAGE DISTRIBUTION, VS = ±15V 100 400 90 300 200 70 VOS (µV) VS = ±15V 50 40 120 80 100 60 40 -55°C -40°C 100 60 30 +25°C +125°C 0 -100 -200 20 VS = ±5V -300 10 0 -60 VOS (µV) FIGURE 4. ISL28118M INPUT OFFSET VOLTAGE DISTRIBUTION, VS = ±5V 80 VOS (µV) 10 0 120 80 VOS (µV) 100 40 60 0 20 -20 -40 -60 -80 -120 0 -100 10 20 0 20 30 20 30 40 -40 40 50 -20 50 60 -60 60 -80 70 VS = ±5V -100 NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS 80 VS = ±15V 80 -120 90 VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. -40 -20 0 20 40 60 80 100 -400 -16 120 -15 TEMPERATURE (°C) FIGURE 5. VOS vs TEMPERATURE -14 -13 13 14 15 16 INPUT COMMON MODE VOLTAGE (V) FIGURE 6. INPUT OFFSET VOLTAGE vs INPUT COMMON MODE VOLTAGE, -55°C to +125°C, VS = ±15V 0 -150 -50 VS = ±20V -200 -100 VS = ± 15V -200 IBIAS (nA) IBIAS (nA) -150 -250 -300 -250 -300 VS = +2V/-1V -350 VS = ±2.25V -350 -400 VS = ±5V -450 -500 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 VS (V) FIGURE 7. IBIAS vs VS 6 -400 -60 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 8. IBIAS vs TEMPERATURE vs SUPPLY FN7858.0 May 11, 2011 ISL28118M VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) 124 124 122 122 120 120 CMRR (dB) CMRR (dB) Typical Performance Curves 118 116 118 116 114 114 112 112 110 -60 -40 -20 0 20 40 60 80 100 110 -60 120 -40 -20 0 TEMPERATURE (°C) 80 100 120 135 130 125 120 115 110 105 100 -60 10 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) PSRR- 1M FIGURE 13. PSRR vs FREQUENCY, VS = ±15V 7 -20 0 20 40 60 80 100 120 FIGURE 12. PSRR vs TEMPERATURE, VS = ±15V PSRR+ 1k 10k 100k FREQUENCY (Hz) -40 TEMPERATURE (°C) PSRR (dB) PSRR (dB) 60 140 FIGURE 11. CMRR vs FREQUENCY, VS = ±15V 140 130 120 110 100 90 80 70 60 50 40 VS = ±15V 30 AV = 1 20 CL = 4pF 10 RL = 10k 0 VCM = 1VP-P -10 10 100 40 FIGURE 10. ISL28118M CMRR vs TEMPERATURE, VS = ±5V PSRR (dB) CMRR (dB) FIGURE 9. ISL28118M CMRR vs TEMPERATURE, V S = ±15V 140 130 120 110 100 90 80 70 60 50 40 30 VS = ±15V 20 SIMULATION 10 0 1m 0.01 0.1 1 20 TEMPERATURE (°C) 10M 140 130 120 110 100 90 80 70 60 50 40 VS = ±5V 30 AV = 1 20 CL = 4pF 10 RL = 10k 0 VCM = 1VP-P -10 10 100 PSRR+ PSRR- 1k 10k 100k FREQUENCY (Hz) 1M 10M FIGURE 14. PSRR vs FREQUENCY, VS = ±5V FN7858.0 May 11, 2011 ISL28118M 200 180 160 140 120 100 80 60 40 20 0 -20 -40 -60 VS = ±15V -80 RL = 1MΩ -100 1m 0.01 0.1 VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) 70 60 PHASE RF = 10kΩ, RG = 10Ω ACL = 1000 RF = 10kΩ, RG = 100Ω 50 GAIN (dB) GAIN (dB) Typical Performance Curves GAIN 40 30 20 ACL = 10 RF = 10kΩ, RG = 1kΩ 10 ACL = 1 0 1 -10 100 10 100 1k 10k 100k 1M 10M100M 1G VS = ±5V & ±15V CL = 4pF RL = 2k VOUT = 100mVP-P ACL = 100 RF = 0, RG = ∞ 1k 10k FIGURE 15. OPEN-LOOP GAIN, PHASE vs FREQUENCY, V S = ±15V -1 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 0 -1 -2 -3 -4 RL = OPEN, 100k, 10k -5 RL = 1k RL = 499 RL = 100 VS = ±15V CL = 4pF -7 A = +1 V -8 VOUT = 100mVp-p -9 100 1k RL = 49.9 10k 100k 1M -2 -3 -4 RL = OPEN, 100k, 10k -5 -6 CL = 4pF -7 A = +1 V -8 VOUT = 100mVp-p -9 100 10M 1k RL = 49.9 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 17. GAIN vs FREQUENCY vs R L, VS = ±15V FIGURE 18. GAIN vs FREQUENCY vs RL, VS = ±5V 1 1 0 0 -1 -1 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) RL = 1k RL = 499 RL = 100 VS = ±5V FREQUENCY (Hz) -2 -3 -4 VOUT = 10mVP-P VS = ±5V VOUT = 50mVP-P CL = 4pF -7 A = +1 V -8 RL = INF VOUT = 100mVP-P -6 10M 1 0 -5 1M FIGURE 16. FREQUENCY RESPONSE vs CLOSED LOOP GAIN 1 -6 100k FREQUENCY (Hz) FREQUENCY (Hz) -9100 VOUT = 500mVP-P VOUT = 1VP-P 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 19. GAIN vs FREQUENCY vs OUTPUT VOLTAGE 8 10M -2 -3 VS = ±1.5V -4 VS = ±5V -5 -6 CL = 4pF R = 10k -7 L AV = +1 -8 VOUT = 100mVP-P -9 100 1k VS = ±15V 10k 100k FREQUENCY (Hz) 1M 10M FIGURE 20. GAIN vs FREQUENCY vs SUPPLY VOLTAGE FN7858.0 May 11, 2011 ISL28118M Typical Performance Curves VOH AND VOL (mV) 90 40 VS = ±15V RL = 10k VS = ±5V 38 R = 10k L 36 VOH VOH AND VOL (mV) 100 VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) 80 70 60 VOH 34 32 30 28 26 24 50 40 -60 -40 -20 0 20 40 VOL 22 60 20 -60 80 100 120 VOL -40 -20 TEMPERATURE (°C) 20 40 1 -40°C 0.01 0.1 1 LOAD CURRENT (mA) 10 FIGURE 23. OUTPUT OVERHEAD VOLTAGE HIGH vs LOAD CURRENT, -40°C to +125°C, VS = ±5V AND ±15V +25°C 0.1 VOL - V- (V) V+ - VOH (V) 120 +125°C +25°C 0.01 100 VS = ±5V and ±15V +125°C 0.001 0.001 80 FIGURE 22. OUTPUT OVERHEAD VOLTAGE vs TEMPERATURE, VS = ±5V, RL = 10k VS = ±5V and ±15V 0.1 60 TEMPERATURE (°C) FIGURE 21. OUTPUT OVERHEAD VOLTAGE vs TEMPERATURE, VS = ±15V, RL = 10k 1 0 -40°C 0.01 0.001 0.001 0.01 0.1 1 LOAD CURRENT (mA) 10 FIGURE 24. OUTPUT OVERHEAD VOLTAGE LOW vs LOAD CURRENT, -40°C to +125°C, VS = ±5V AND ±15V 1100 1600 CURRENT (µA) 1200 VS = ±21V 1000 800 VS = ±15V 600 400 -60 VS = ±2.25V -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 25. ISL28118M SUPPLY CURRENT vs TEMPERATURE vs SUPPLY VOLTAGE 9 ISUPPLY PER AMPLIFIER (µA) 1000 1400 900 800 700 600 500 400 300 200 100 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 VSUPPLY (V) FIGURE 26. SUPPLY CURRENT vs SUPPLY VOLTAGE FN7858.0 May 11, 2011 ISL28118M Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) 10 10 INPUT NOISE CURRENT 1 0.1 0.1 1 10 100 1k FREQUENCY (Hz) 1 0.1 100k 10k INPUT NOISE CURRENT 1 1 1 10 100 1k FREQUENCY (Hz) 0.1 100k 10k 500 300 INPUT NOISE VOLTAGE (nV) VS = ±18V AV = 10k 400 200 100 0 -100 -200 -300 -400 0 1 2 3 4 5 6 7 8 9 VS = ±5V AV = 10k 400 300 200 100 0 -100 -200 -300 -400 -500 10 0 1 2 3 4 5 6 7 8 9 10 TIME (s) TIME (s) FIGURE 29. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz, VS = ±18V FIGURE 30. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz, VS = ±5V 0.1 0.1 VS = ±15V CL = 4pF RL = 2k VOUT = 10VP-P -40°C AV = 10 +125°C +25°C 0.01 C-WEIGHTED 22Hz TO 500kHz THD + N (%) INPUT NOISE VOLTAGE (nV) 10 10 FIGURE 28. INPUT NOISE VOLTAGE (en) AND CURRENT (in) vs FREQUENCY, VS = ±5V 500 THD + N (%) INPUT NOISE VOLTAGE 0.1 0.1 FIGURE 27. INPUT NOISE VOLTAGE (en) AND CURRENT (in) vs FREQUENCY, VS = ±18V -500 VS = ±5V INPUT NOISE CURRENT (fA/√Hz) INPUT NOISE VOLTAGE 100 100 INPUT NOISE VOLTAGE (nV/√Hz) INPUT NOISE VOLTAGE (nV/√Hz) VS = ±18V INPUT NOISE CURRENT (fA/√Hz) 100 100 0.001 VS = ±15V CL = 4pF RL = 10k VOUT = 10VP-P -40°C +125°C 0.01 C-WEIGHTED 22Hz TO 500kHz +25°C AV = 10 0.001 AV = 1 -40°C -40°C 0.0001 10 +25°C AV = 1 +125°C 100 1k FREQUENCY (Hz) 10k 100k FIGURE 31. THD+N vs FREQUENCY vs TEMPERATURE, AV = 1, 10, RL = 2k 10 0.0001 10 +25°C 100 +125°C 1k 10k 100k FREQUENCY (Hz) FIGURE 32. THD+N vs FREQUENCY vs TEMPERATURE, AV = 1, 10, RL = 10k FN7858.0 May 11, 2011 ISL28118M Typical Performance Curves 1 VS = ±15V CL = 4pF RL = 2k 0.1 f = 1kHz 1 VS = ±15V CL = 4pF RL = 10k 0.1 f = 1kHz C-WEIGHTED 22Hz TO 22kHz THD + N (%) +125°C -40°C THD + N (%) VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) +25°C 0.01 AV = 10 AV = 1 0.001 0.0001 0 5 15 20 +25°C 0.01 AV = 10 AV = 1 -40°C 25 30 0.0001 0 +25°C 10 5 VOUT (VP-P) FIGURE 33. THD+N vs OUTPUT VOLTAGE (VOUT) vs TEMPERATURE, AV = 1, 10, RL = 2k 25 30 1.2 0.8 0 0.4 0 -0.4 -2 -0.8 -4 -1.2 -1.6 -6 -2.0 -2.4 0 10 20 VS = ±5V AV = 1 RL = 2k CL = 4pF 2.0 1.6 VOUT (V) VOUT (V) 20 2.4 VS = ±15V AV = 1 4 RL = 2k CL = 4pF 2 30 40 50 60 TIME (µs) 70 80 90 100 40 20 0 -20 -40 -60 -80 20 30 40 50 60 TIME (µs) 70 80 90 100 VS = ±5V VIN = ±5.9V 5 INPUT AND OUTPUT (V) 60 10 FIGURE 36. LARGE SIGNAL 4V STEP RESPONSE, VS = ±5V 6 VS = ±15V AND VS = ±5V AV = 1 RL = 2k CL = 4pF 80 0 100 FIGURE 35. LARGE SIGNAL 10V STEP RESPONSE, VS = ±15V VOUT (V) -40°C +125°C 15 VOUT (VP-P) FIGURE 34. THD+N vs OUTPUT VOLTAGE (VOUT) vs TEMPERATURE, AV = 1, 10, RL = 10k 6 -100 +125°C -40°C 0.001 +125°C +25°C 10 C-WEIGHTED 22Hz TO 22kHz 4 INPUT 3 2 1 OUTPUT 0 -1 -2 -3 -4 -5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 TIME (µs) FIGURE 37. SMALL SIGNAL TRANSIENT RESPONSE, VS = ±5V, ±15V 11 1.8 2 -6 0 1 2 TIME (ms) 3 4 FIGURE 38. NO PHASE REVERSAL FN7858.0 May 11, 2011 ISL28118M Typical Performance Curves 20 VS = ±15V AV = 100 RL = 10k 16 VIN = 100mVP-P OVERDRIVE = 1V -80 -8 -120 80 8 40 4 -160 0 40 -200 0 0 4 8 12 16 20 24 TIME (µs) 28 32 36 50 INPUT 40 OUTPUT -50 0 40 -60 0 24 28 32 36 -40 INPUT 0 4 8 12 16 20 24 -4 VS = ±5V AV = 100 RL = 10k -5 VIN = 50mVP-P OVERDRIVE = 1V -6 28 32 36 40 TIME (µs) FIGURE 41. POSITIVE OUTPUT OVERLOAD RESPONSE TIME, VS = ±5V FIGURE 42. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME, VS = ±5V 100 100 VS = ±15V VS = ±5V AV = 10 10 AV = 10 10 AV = 100 ZOUT (Ω) AV = 100 1 0.10 1 0.10 AV = 1 AV = 1 0.01 -3 OUTPUT TIME (µs) ZOUT (Ω) 24 0 -30 1 20 20 -2 10 16 16 -20 2 12 12 -1 20 8 8 -10 3 4 4 0 30 0 0 -12 VS = ±15V AV = 100 -16 RL = 10k VIN = 100mVP-P OVERDRIVE = 1V -20 28 32 36 40 FIGURE 40. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME, VS = ±15V OUTPUT (V) 6 VS = ±5V AV = 100 5 RL = 10k VIN = 50mVP-P OVERDRIVE = 1V 4 60 OUTPUT TIME (µs) FIGURE 39. POSITIVE OUTPUT OVERLOAD RESPONSE TIME, VS = ±15V INPUT (mV) -4 OUTPUT (V) 12 OUTPUT -40 OUTPUT (V) 120 INPUT INPUT (mV) INPUT (mV) 160 0 0 INPUT (mV) INPUT OUTPUT (V) 200 VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 43. OUTPUT IMPEDANCE vs FREQUENCY, VS = ±15V 12 0.01 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 44. OUTPUT IMPEDANCE vs FREQUENCY, V S = ±5V FN7858.0 May 11, 2011 ISL28118M Typical Performance Curves OVERSHOOT (%) 50 VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) 60 VS = ±15V VOUT = 100mVP-P 50 AV = 1 OVERSHOOT (%) 60 40 AV = 10 AV = -1 30 20 10 VS = ±5V VOUT = 100mVP-P 40 20 0.010 0.100 1 10 0 0.001 100 LOAD CAPACITANCE (nF) VS = ±15V 28 R = 10k L 26 VOUT (VP-P) 24 ISC-SINK 20 18 16 ISC-SOURCE 14 12 -40 -20 0 20 40 60 80 100 TEMPERATURE (°C) FIGURE 47. ISL28118M SHORT CIRCUIT CURRENT vs TEMPERATURE, VS = ±15V 13 0.1 1 10 100 FIGURE 46. OVERSHOOT vs CAPACITIVE LOAD, VS = ±5V 30 22 0.01 LOAD CAPACITANCE (nF) FIGURE 45. OVERSHOOT vs CAPACITIVE LOAD, VS = ±15V ISC (mA) AV = 10 AV = -1 30 10 0 0.001 10 -60 AV = 1 120 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 1k VS = ±15V AV = 1 10k 100k FREQUENCY (Hz) 1M FIGURE 48. MAX OUTPUT VOLTAGE vs FREQUENCY FN7858.0 May 11, 2011 ISL28118M Applications Information Functional Description The ISL28118M is a 3.2MHz, single-supply, rail-to-rail output amplifier with a common mode input voltage range extending to a range of 0.5V below the V- rail. The input stage is optimized for precision sensing of ground-referenced signals in single-supply applications. The input stage is able to handle large input differential voltages without phase inversion, making this amplifier suitable for high-voltage comparator applications. The bipolar design features high open loop gain, excellent DC input/output temperature stability with a low quiescent current of 850µV, and low temperature drift. The op amp is fabricated in a new precision 40V complementary bipolar DI process and is immune from latch-up. Operating Voltage Range The op amp is designed to operate over a single supply range of 3V to 40V or a split supply voltage range of +1.8V, -1.2V to +/-20V. The device is fully characterized at 10V (±5V) and 30V (±15V). Both DC and AC performance remain virtually unchanged over the complete operating voltage range. Parameter variation with operating voltage is shown in the “Typical Performance Curves” beginning on page 6. The input common mode voltage to the V+ rail (V+ -1.8V over the full temperature range) may limit amplifier operation when operating from split V+ and V- supplies. Figure 6 shows the common mode input voltage range variation over temperature. Input Stage Performance The ISL28118M PNP input stage has a common mode input range extending up to 0.5V below ground at +25°C (Figure 6). Full amplifier performance is guaranteed with input voltage down to ground (V-) over the -55°C to +125°C temperature range. For common mode voltages down to -0.5V below ground (V-), the amplifiers are fully functional, but performance degrades slightly over the full temperature range. This feature provides excellent CMRR, AC performance, and DC accuracy when amplifying low-level, ground-referenced signals. The input stage has a maximum input differential voltage equal to a diode drop greater than the supply voltage (max 42V) and does not contain the back-to-back input protection diodes found on many similar amplifiers. This feature enables the device to function as a precision comparator by maintaining very high input impedance for high-voltage differential input comparator voltages. The high differential input impedance also enables the device to operate reliably in large signal pulse applications, without the need for anti-parallel clamp diodes required on MOSFET and most bipolar input stage op amps. Thus, input signal distortion caused by nonlinear clamps under high slew rate conditions is avoided. In applications where one or both amplifier input terminals are at risk of exposure to voltages beyond the supply rails, current-limiting resistors may be needed at each input terminal (see Figure 52, RIN+, RIN-) to limit current through the power-supply ESD diodes to 20mA. 14 V+ VINVIN+ RIN- - RIN+ + RG RF RL V- FIGURE 49. INPUT ESD DIODE CURRENT LIMITING Output Drive Capability The bipolar rail-to-rail output stage features low saturation levels that enable an output voltage swing to less than 15mV when the total output load (including feedback resistance) is held below 50µA. With ±15V supplies, this can be achieved by using feedback resistor values >300kΩ. The output stage is internally current limited. The amplifiers can withstand a short circuit to either rail as long as the power dissipation limits are not exceeded. Continuous operation under these conditions may degrade long-term reliability. The amplifiers perform well when driving capacitive loads (Figures 45 and 46). The unity gain, voltage follower (buffer) configuration provides the highest bandwidth but is also the most sensitive to ringing produced by load capacitance found in BNC cables. Unity gain overshoot is limited to 35% at capacitance values to 0.33nF. At gains of 10 and higher, the device is capable of driving more than 10nF without significant overshoot. Output Phase Reversal Output phase reversal is a change of polarity in the amplifier transfer function when the input voltage exceeds the supply voltage. The ISL28118M is immune to output phase reversal for input voltage to 0.5V beyond the rail (VABS MAX) limit (Figure 38). Power Dissipation It is possible to exceed the +150°C maximum junction temperatures under certain load and power supply conditions. It is therefore important to calculate the maximum junction temperature (TJMAX) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related using Equation 1: T JMAX = T MAX + θ JA xPD MAXTOTAL (EQ. 1) where • PDMAXTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PDMAX) • TMAX = Maximum ambient temperature • ΘJA = Thermal resistance of the package FN7858.0 May 11, 2011 ISL28118M PDMAX for each amplifier can be calculated using Equation 2: LICENSE STATEMENT V OUTMAX PD MAX = V S × I qMAX + ( V S - V OUTMAX ) × -----------------------R The information in the SPICE model is protected under United States copyright laws. Intersil Corporation hereby grants users of this macro-model, hereto referred to as “Licensee”, a nonexclusive, nontransferable licence to use this model, as long as the Licensee abides by the terms of this agreement. Before using this macro-model, the Licensee should read this license. If the Licensee does not accept these terms, permission to use the model is not granted. (EQ. 2) L where: • PDMAX = Maximum power dissipation of 1 amplifier • VS = Total supply voltage • IqMAX = Maximum quiescent supply current of one amplifier • VOUTMAX = Maximum output voltage swing of the application • RL = Load resistance ISL28118M SPICE Model Figure 50 shows the SPICE model schematic and Figure 51 shows the net list for the SPICE model. The model is a simplified version of the actual device and simulates important AC and DC parameters. AC parameters incorporated into the model are: 1/f and flatband noise voltage, slew rate, CMRR, and gain and phase. The DC parameters are IOS, total supply current, and output voltage swing. The model uses typical parameters given in the “Electrical Specifications” table beginning on page 3. The AVOL is adjusted for 136dB with the dominant pole at 0.6Hz. The CMRR is set at 120dB, f = 50kHz. The input stage models the actual device to present an accurate AC representation. The model is configured for an ambient temperature of +25°C. The Licensee may not sell, loan, rent, or license the macro-model, in whole, in part, or in modified form, to anyone outside the Licensee’s company. The Licensee may modify the macro-model to suit his/her specific applications, and the Licensee may make copies of this macro-model for use within their company only. This macro-model is provided “AS IS, WHERE IS, AND WITH NO WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.” In no event will Intersil be liable for special, collateral, incidental, or consequential damages in connection with or arising out of the use of this macro-model. Intersil reserves the right to make changes to the product and the macro-model without prior notice. Figures 52 through 66 show the characterization vs. simulation results for the noise voltage, open loop gain phase, closed loop gain vs. frequency, gain vs. frequency vs. RL, CMRR, large signal 10V step response, small signal 0.1V step, and output voltage swing ±15V supplies. 15 FN7858.0 May 11, 2011 DX I1 80e-6 D3 G1 + - I2 54E-6 I3 9 750 2 R17 + ++ - - 0 D14 5 0 3 750 En Q8 CinDif 1.33E-12 R1 5e11 GAIN = 0.3 Cin2 4.02e-12 DX + - C1 R7 6.6667E-11 3.7304227e9 GAIN = 1.69138e-3 -0.91 V3 Input Stage V+ 1st Gain Stage V++ L3 3.18319E-09 V++ G9 + - R13 795.7981 D10 GAIN = 1.2566e-3 D7 D11 V5 DX 24 C3 10e-12 Vc Vg 1 V++ G5 + + 18 21 GAIN = 1 R9 GAIN = 1 R11 1e-3 1e-3 19 R6 GAIN = 0.65897 D4 DX 16 G2 V-- DX 3.18319E-09 15 V-- GAIN = 1 L1 V2 -0.96 G13 GAIN = 12.5e-3 -0.4 23 26 R15 80 Vout VOUT 27 Vmid ISY D8 DX D6 22 L4 3.18319E-09 GAIN = 1.2566e-3 R14 795.7981 V-- FN7858.0 May 11, 2011 Mid Supply ref V D9 G11 G12 D12 + + GAIN = 12.5e-3 GAIN = 12.5e-3 V-V- 2nd Gain Stage -0.4 C4 10e-12 DY G8 L2 3.18319E-09 GAIN = 1 GAIN = 1 G10 DY + - GAIN = 1.69138e-3 3.7304227e9 20 G6 + - C2 6.6667E-11 17 R12 1e-3 + - G4 R10 1e-3 + - ++ - GAIN = 0.5 -0.96 V6 25 DX V4 Common Mode Gain Stage with Zero E3 + -+ GAIN = 1 V-- 0 FIGURE 50. SPICE SCHEMATIC Output Stage Correction Current Sources R16 + - 2.5E-3 G14 GAIN = 12.5e-3 80 ISL28118M D5 GAIN = 1 R4 1k 6 Cin1 4.02e-12 E2 ++ - 0 Q9 14 EOS + + - - 12 11 R3 1k Vin+ PNP_LATERAL 10 PNP_input PNP_input D2 DBREAK 8 IOS 4e-9 Vcm R18 Q6 DX D13 DN 16 DN R2 5e11 4 V8 Q7 7 +- V7 PNP_LATERAL - 1 -0.91 D1 DBREAK 0.1 0.1 1 GAIN = 0.65897 V1 54E-6 Vin- R5 13 ISL28118M *ISL28118_218 Macromodel - covers following *products *ISL28118 *ISL28218 * *Revision History: * Revision A, LaFontaine February 8th 2011 * Model for Noise, supply currents, CMRR *120dB f = 40kHz, AVOL 136dB f = 0.5Hz * SR = 1.2V/us, GBWP 4MHz. *Copyright 2011 by Intersil Corporation *Refer to data sheet “LICENSE STATEMENT” *Use of this model indicates your acceptance *with the terms and provisions in the License *Statement. * *Intended use: *This Pspice Macromodel is intended to give *typical DC and AC performance characteristics *under a wide range of external circuit *configurations using compatible simulation *platforms – such as iSim PE. * *Device performance features supported by this *model: *Typical, room temp., nominal power supply *voltages used to produce the following *characteristics: *Open and closed loop I/O impedances, *Open loop gain and phase, *Closed loop bandwidth and frequency *response, *Loading effects on closed loop frequency *response, *Input noise terms including 1/f effects, *Slew rate, *Input and Output Headroom limits to I/O *voltage swing, *Supply current at nominal specified supply *voltages, * *Device performance features NOT supported *by this model: *Harmonic distortion effects, *Output current limiting (current will limit at *40mA), *Disable operation (if any), *Thermal effects and/or over temperature *parameter variation, *Limited performance variation vs. supply *voltage is modeled, *Part to part performance variation due to *normal process parameter spread, *Any performance difference arising from *different packaging, *Load current reflected into the power supply *current. * source ISL28118_218 SPICEmodel * * Connections: +input * | -input * | | +Vsupply * | | | -Vsupply * | | | | output .subckt ISL28118_218 Vin+ Vin-V+ V- VOUT * source ISL28118_218_presubckt_0 * *Voltage Noise E_En VIN+ 6 2 0 0.3 D_D13 1 2 DN D_D14 1 2 DN V_V7 1 0 0.1 V_V8 4 0 0.1 R_R17 2 0 750 *R_R18 3 0 750 * *Input Stage Q_Q6 11 10 9 PNP_input Q_Q7 8 7 9 PNP_input Q_Q8 V-- VIN- 7 PNP_LATERAL Q_Q9 V-- 12 10 PNP_LATERAL I_I1 V++ 9 DC 80e-6 I_I2 V++ 7 DC 54E-6 I_I3 V++ 10 DC 54E-6 I_IOS 6 VIN- DC 4e-9 *D_D1 7 10 DBREAK *D_D2 10 7 DBREAK R_R1 5 6 5e11 R_R2 VIN- 5 5e11 R_R3 V-- 8 1000 R_R4 V-- 11 1000 C_Cin1 V-- VIN- 4.02e-12 C_Cin2 V-- 6 4.02e-12 C_CinDif 6 VIN- 1.33E-12 * *1st Gain Stage G_G1 V++ 14 8 11 0.65897 G_G2 V-- 14 8 11 0.65897 V_V1 13 14 -0.91 V_V2 14 15 -0.96 D_D3 13 V++ DX D_D4 V-- 15 DX R_R5 14 V++ 1 R_R6 V-- 14 1 * *2nd Gain Stage G_G3 V++ VG 14 VMID 1.69138e-3 G_G4 V-- VG 14 VMID 1.69138e-3 V_V3 16 VG -0.91 V_V4 VG 17 -0.96 D_D5 16 V++ DX D_D6 V-- 17 DX R_R7 VG V++ 3.7304227e9 R_R8 V-- VG 3.7304227e9 C_C1 VG V++ 6.6667E-11 C_C2 V-- VG 6.6667E-11 * *Mid supply Ref E_E2 V++ 0 V+ 0 1 E_E3 V-- 0 V- 0 1 E_E4 VMID V-- V++ V-- 0.5 I_ISY V+ V- DC 0.85E-3 * *Common Mode Gain Stage with Zero G_G5 V++ 19 5 VMID 1 G_G6 V-- 19 5 VMID 1 G_G7 V++ VC 19 VMID 1 G_G8 V-- VC 19 VMID 1 E_EOS 12 6 VC VMID 1 L_L1 18 V++ 3.18319E-09 L_L2 20 V-- 3.18319E-09 L_L3 21 V++ 3.18319E-09 L_L4 22 V-- 3.18319E-09 R_R9 19 18 1e-3 R_R10 20 19 1e-3 R_R11 VC 21 1e-3 R_R12 22 VC 1e-3 * *Pole Stage G_G9 V++ 23 VG VMID 1.2566e-3 G_G10 V-- 23 VG VMID 1.2566e-3 R_R13 23 V++ 795.7981 R_R14 V-- 23 795.7981 C_C3 23 V++ 10e-12 C_C4 V-- 23 10e-12 * *Output Stage with Correction Current Sources G_G11 26 V-- VOUT 23 12.5e-3 G_G12 27 V-- 23 VOUT 12.5e-3 G_G13 VOUT V++ V++ 23 12.5e-3 G_G14 V-- VOUT 23 V-- 12.5e-3 D_D7 23 24 DX D_D8 25 23 DX D_D9 V-- 26 DY D_D10 V++ 26 DX D_D11 V++ 27 DX D_D12 V-- 27 DY V_V5 24 VOUT -0.4 V_V6 VOUT 25 -0.4 R_R15 VOUT V++ 80 R_R16 V-- VOUT 80 .model PNP_LATERAL pnp(is=1e-016 bf=250 va=80 + ik=0.138 rb=0.01 re=0.101 rc=180 kf=0 af=1) .model PNP_input pnp(is=1e-016 bf=100 va=80 + ik=0.138 rb=0.01 re=0.101 rc=180 kf=0 af=1) .model DBREAK D(bv=43 rs=1) .model DN D(KF=6.69e-9 AF=1) .MODEL DX D(IS=1E-12 Rs=0.1) .MODEL DY D(IS=1E-15 BV=50 Rs=1) .ends ISL28118_218 FIGURE 51. SPICE NET LIST 17 FN7858.0 May 11, 2011 ISL28118M Characterization vs Simulation Results 100 INPUT NOISE VOLTAGE 10 10 INPUT NOISE CURRENT 1 0.1 0.1 1 10 100 1k FREQUENCY (Hz) 10k 1 100 INPUT NOISE VOLTAGE (nV/√Hz) VS = ±18V INPUT NOISE CURRENT (fA/√Hz) INPUT NOISE VOLTAGE (nV/√Hz) 100 0.1 100k 10 1 0.1 0.1 200 180 160 140 120 100 80 60 40 20 0 -20 -40 -60 VS = ±15V -80 RL = 1MΩ -100 1m 0.01 0.1 PHASE GAIN 1 10 100 1k 10k 100k 1M 10M100M 1G 10 200 180 160 140 120 100 80 60 40 20 0 -20 -40 -60 VS = ±15V -80 RL = 1MΩ -100 1m 0.01 0.1 FIGURE 54. CHARACTERIZED OPEN-LOOP GAIN, PHASE vs FREQUENCY GAIN (dB) 40 VS = ±5V & ±15V CL = 4pF RL = 2k VOUT = 100mVP-P ACL = 100 30 20 60 RF = 10kΩ, RG = 100Ω 50 ACL = 10 10 0 -10 100 RF = 10kΩ, RG = 1kΩ 100k 1M 10M FREQUENCY (Hz) FIGURE 56. CHARACTERIZED CLOSED-LOOP GAIN vs FREQUENCY 18 1 10 100 1k 10k 100k 1M 10M100M 1G RF = 10kΩ, RG = 10Ω RF = 10kΩ, RG = 100Ω 50 40 VS = ±5V & ±15V CL = 4pF RL = 2k VOUT = 100mVP-P ACL = 100 30 20 ACL = 10 0 RF = 0, RG = ∞ 10k GAIN ACL = 1000 10 ACL = 1 1k PHASE 70 GAIN (dB) 60 100k FIGURE 55. SIMULATED OPEN-LOOP GAIN, PHASE vs FREQUENCY RF = 10kΩ, RG = 10Ω ACL = 1000 10k FREQUENCY (Hz) FREQUENCY (Hz) 70 100 1k FREQUENCY (Hz) FIGURE 53. SIMULATED INPUT NOISE VOLTAGE GAIN (dB) GAIN (dB) FIGURE 52. CHARACTERIZED INPUT NOISE VOLTAGE 1 -10 100 RF = 10kΩ, RG = 1kΩ ACL = 1 RF = 0, RG = ∞ 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 57. SIMULATED CLOSED-LOOP GAIN vs FREQUENCY FN7858.0 May 11, 2011 ISL28118M Characterization vs Simulation Results (Continued) 1 0 0 -1 -1 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 1 -2 -3 -4 RL = OPEN, 100k, 10k -5 -6 RL = 1k RL = 499k RL = 100k VS = ±15V CL = 4pF -7 A = +1 V -8 VOUT = 100mVp-p -9 100 RL = 49.9k 1k 10k 100k 1M -2 -3 -4 RL = OPEN, 100k, 10k -5 RL = 1k RL = 499k RL = 100k VS = ±15V -6 CL = 4pF -7 A = +1 V -8 VOUT = 100mVp-p -9 100 10M RL = 49.9k 1k 10k FREQUENCY (Hz) 10 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) 140 130 120 110 100 90 80 70 60 50 40 30 VS = ±15V 20 SIMULATION 10 0 1m 0.01 0.1 1 FIGURE 60. CHARACTERIZED CMRR vs FREQUENCY 6 2 0 0 -2 -2 -4 -4 10 20 30 40 50 60 TIME (µs) 70 80 90 100 FIGURE 62. CHARACTERIZED LARGE-SIGNAL 10V STEP RESPONSE 19 10 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) VS = ±15V AV = 1 RL = 2k CL = 4pF 4 VOUT (V) VOUT (V) VS = ±15V AV = 1 4 RL = 2k CL = 4pF 2 0 10M FIGURE 61. SIMULATED CMRR vs FREQUENCY 6 -6 1M FIGURE 59. SIMULATED GAIN vs FREQUENCY vs RL CMRR (dB) CMRR (dB) FIGURE 58. CHARACTERIZED GAIN vs FREQUENCY vs RL 140 130 120 110 100 90 80 70 60 50 40 30 VS = ±15V 20 SIMULATION 10 0 1m 0.01 0.1 1 100k FREQUENCY (Hz) -6 0 10 20 30 40 50 60 TIME (µs) 70 80 90 100 FIGURE 63. SIMULATED LARGE-SIGNAL 10V STEP RESPONSE FN7858.0 May 11, 2011 ISL28118M Characterization vs Simulation Results (Continued) 100 40 20 60 40 0 -20 20 0 -20 -40 -40 -60 -60 -80 -80 -100 -100 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VS = ±15V AND VS = ±5V AV = 1 RL = 2k CL = 4pF 80 VOUT (V) 60 VOUT (V) 100 VS = ±15V AND VS = ±5V AV = 1 RL = 2k CL = 4pF 80 2.0 0 0.2 0.4 0.6 TIME (µs) 0.8 1.0 1.2 1.4 1.6 1.8 2.0 TIME (µs) FIGURE 64. CHARACTERIZED SMALL-SIGNAL TRANSIENT RESPONSE FIGURE 65. SIMULATED SMALL-SIGNAL TRANSIENT RESPONSE OUTPUT VOLTAGE SWING (V) 20V VOH = 14.88V 10V 0V RL = 10kΩ -10V VS = ±15V VOL = -14.93V -20V 0 0.5 1.0 TIME (ms) 1.5 2.0 FIGURE 66. SIMULATED OUTPUT VOLTAGE SWING 20 FN7858.0 May 11, 2011 ISL28118M Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION 5/11/11 FN7858.0 CHANGE Initial Release Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL28118M. To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff FITs are available from our website at: http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 21 FN7858.0 May 11, 2011 ISL28118M Package Outline Drawing M8.118 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 3, 3/10 5 3.0±0.05 A DETAIL "X" D 8 1.10 MAX SIDE VIEW 2 0.09 - 0.20 4.9±0.15 3.0±0.05 5 0.95 REF PIN# 1 ID 1 2 B 0.65 BSC GAUGE PLANE TOP VIEW 0.55 ± 0.15 0.25 3°±3° 0.85±010 H DETAIL "X" C SEATING PLANE 0.25 - 0.036 0.08 M C A-B D 0.10 ± 0.05 0.10 C SIDE VIEW 1 (5.80) NOTES: (4.40) (3.00) 1. Dimensions are in millimeters. (0.65) (0.40) (1.40) TYPICAL RECOMMENDED LAND PATTERN 22 2. Dimensioning and tolerancing conform to JEDEC MO-187-AA and AMSEY14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. 4. Plastic interlead protrusions of 0.15mm max per side are not included. 5. Dimensions are measured at Datum Plane "H". 6. Dimensions in ( ) are for reference only. FN7858.0 May 11, 2011