isl70219asehev1z user guide

User Guide 007
ISL70219ASEH Evaluation Board User’s Guide
Introduction
Key Features
The ISL70219ASEHEV1Z evaluation platform is designed to
evaluate the ISL70219ASEH. The ISL70219ASEH contains two
very high precision amplifiers featuring the perfect combination
of low noise vs power consumption. Low offset voltage, low IBIAS
current and low temperature drift making them the ideal choice
for applications requiring both high DC accuracy and AC
performance. The combination of high precision, low noise, low
power and small footprint provides the user with outstanding
value and flexibility relative to similar competitive parts.
• Wide VIN range single supply or dual supply
- ±2.25V to ±18V
- +4.5V to +36V
Applications for these amplifiers include precision active
filters, medical and analytical instrumentation, precision
power supply controls, and industrial controls.
The ordering number for this board is ISL70219ASEHEV1Z.
Please go to ordering tab on the landing page for the
ISL70219ASEH.
Reference Documents
• ISL70219ASEH Datasheet
• ISL70219ASEH SMD 5962-14226
• Singled-ended or differential input operation
• External VREF input
• Banana Jack connectors for power supply and VREF inputs
• BNC connectors for op amp input and output terminals
• Convenient PCB pads for op amp input/output impedance
loading.
Specifications
• V+ range: +2.25V to 18V
• V- range: -2.25V to -18V
• Common mode input range: 2V within V+ and V- rails.
Ordering Information
PART NUMBER
• ISL70219ASEH Radiation Test Report
ISL70219ASEHEV1Z
DESCRIPTION
Evaluation Board
• TR002 Single Event Effects (SEE) Testing of the
ISL70219ASEH Dual Operational Amplifier
FIGURE 1. ISL70219ASEHEV1Z EVALUATION BOARD
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2014. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
User Guide 007
RF
ISL70219 (1/2)
100kΩ
INRIN+
+
+
-
VP
IN-
IN-
-
RIN+
IN+
IN+
VREF
VREF
IN+
VOUT
V+
10kΩ
VCM
0Ω
V+
10kΩ
VN
RREF+
RL
100kΩ
DNP
GND
FIGURE 2. BASIC AMPLIFIER CONFIGURATION
Power Supplies
PCB Layout Considerations
External power connections are made through the +V, -V, VREF
and Ground connections on the evaluation board. For single
supply operation, the -V and Ground pins are tied together to the
power supply negative terminal. For split supplies, +V and -V
terminals connect to their respective power supply terminals.
Decoupling capacitors C2, C3, C4 and C6 connect to their
respective supplies through R11 and R15 resistors. These
resistors are 100Ω but can be changed by the user to provide
additional power supply filtering, or to reduce the voltage rate of
rise to less than ±1V/µs. Two additional capacitors, C5 and C7,
are connected close to the part to filter out high frequency noise.
Anti-reverse diode D1 protects the circuit in the momentary case
of accidentally reversing the power supplies to the evaluation
board. The VREF pin can be connected to ground to establish a
ground referenced input for split supply operation, or can be
externally set to any reference level for single supply operation.
There a few layout constraints to consider when using the
ISL70219ASEH, but this will generally apply to any generic
operational amplifier. Analog circuits can conduct noise
through paths that connect it to the “outside world”. These
paths include the V+, V-, IN+, IN- and OUT terminals. It’s
important to make sure these paths are kept away from
known noise sources to ensure optimal performance of the
part. If the ISL70219ASEH resides on the same boards as
digital circuitry it is necessary to decouple the power pins on
the analog as well as the digital circuitry. This is done on the
evaluation board with C2 through C7, with the lower value
capacitors, C5 and C7, placed near the V- and V+ pins
respectively to minimize high frequency noise.
V OUT =  V IN+ – V IN-    R F  R IN  + V REF
(EQ. 1)
C4
1µF
1µF
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2
J9
VREF
J10
100
C2
D1
C3
0.1µF
For single-ended input with an inverting gain G = -10V/V, the
IN+ input is grounded and the signal is supplied to the INinput. The VREF can be connected to a reference voltage
between the V+ and V- supply rails. For non-inverting operation
with G = 11V/V, the IN- input is grounded and the signal is
supplied to the IN+ input. The non-inverting gain is strongly
dependent on any resistance from IN- to GND. For good gain
accuracy, a 0Ω resistor should be installed on the empty R5
pad. The VREF pin must be connected to ground to establish a
ground referenced input for dual supply operation, or can be
externally set to any reference level for single supply
operation. The VREF should not be left floating.
V+ J8
J6
R15
R11
A simplified schematic of the evaluation board is shown in
Figure 3. The input stage with the components supplied is
shown in Figure 4, with a closed loop gain of 10V/V. The
differential amplifier gain is expressed in Equation 1:
V-
100
Amplifier Configuration
J7
J5
C5
0.01µF
C6
0.1µF
C7
0.01µF
FIGURE 3. POWER SUPPLY CIRCUIT
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DNP
J2
R4
R9
10k
100k
C1
R10
R2
OPEN
VREF
10k
DNP
R6
R12
DNP
100k
FROM OUTPUT
OUTPUT
IN-
C6
OPEN
R26
IN+
0
FIGURE 4. INPUT STAGE (1/2)
DNP
R5
0
DNP
R3
R1
OPEN
R28
J1
FIGURE 5. OUTPUT STAGE (1/2)
User-selectable Options
Component pads are included to enable a variety of
user-selectable circuits to be added to the amplifier VREF, inputs,
outputs, and the amplifier feedback loops.
A voltage divider (Figure 4, R6 and R12) can be added to
establish a power supply-tracking common mode reference
using the VREF input. The input stages (see Figure 4) have
additional resistor and/or capacitor pads that may be used to
add voltage divider networks or feedback networks for adding
input attenuation, or to establish input DC offsets through the
VREF pin. The output stages (see Figure 5) have additional
resistor and capacitor placements for loading.
NOTE: Operational amplifiers are sensitive to output capacitance
and may oscillate. In the event of oscillation, reduce output
capacitance by using shorter cables, or add a resistor in series
with the output.
Bill of Materials
DEVICE #
DESCRIPTION
COMMENTS
C2, C4
CAP, SMD, 1210, 1µF, 50V, 10%, X7R, ROHS
Power Supply Decoupling
C3, C6
CAP, SMD, 0805, 0.1µF, 50V, 10%, X7R, ROHS
Power Supply Decoupling
C5, C7
CAP, SMD, 0603, 0.01µF, 50V, 10%, X7R, ROHS
Power Supply Decoupling
C1, C8-C12
CAP, SMD, 0603, DNP-PLACE HOLDER, ROHS
User selectable capacitors - not populated
D1
DIODE-RECTIFIER, SMD, SOD-123, 2P, 40V, 0.5A, ROHS
Reverse Power Protection
U1
ISL70219ASEH, DUAL OP AMP, 10Ld. FLATPACK
R1, R2, R5-R8, R14, R20, R23, R24,
RESISTOR, SMD, 0603, 0.1%, MF, DNP PLACEHOLDER
User selectable resistors - not populated
R3, R20-R22
RES, SMD, 0603, 0Ω, 1/10W,TF, ROHS
0Ω user selectable resistors
R4, R10, R17, R18
RES, SMD, 0603, 10k, 1/10W, 1%, TF, ROHS
Gain resistors
R10, R12, R13, R16
RES, SMD, 0603, 100k, 1/10W, 1%, TF, ROHS
Gain resistors
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J9
100
R14
2
1
100
R11
J8
VREF
J6
V+
J10
J7
J5
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V-
D1
C4
4
3
C2
1UF
1UF
C3
C6
0.1UF
0.1UF
C5
C7
0.01UF
0.01UF
C3 AND C5 CLOSE TO PART
User Guide 007
R21
J11
OUT A
10K
100K
R15
R18
C1
100K
10K
R2
3
10K
4
DNP
5
V+
OUTA
-INA
+INA
-INB
NC
+INB
J12
R20
R16
7
6
OUT B
0
8
LID
V-
DNP
R22
9
OUTB
C9
R23
2
R6
OPEN
DNP
J2
IN+ A
C10
10
C12
1
0
U1
OPEN
C8
OPEN
R19
R5
DNP
DNP
R1
R24
0
IN- A
DNP
R10
C11
R4
OPEN
0
R3
OPEN
J1
10K
OPEN
JP1
ISL70219ASEHVF
J3
IN- B
R7
VREF
DNP
J4
IN+ B
R8
DRAWN BY:
R9
R12
R13
R17
DNP
DNP
100K
100K
DNP
TIM KLEMANN
DATE:
ENGINEER:
DATE:
UPDATED BY:
DATE:
D
Kiran Bernard
10/14/2014
RELEASED BY:
TITLE:
ISL70219ASEH
FIGURE 6. ISL70219ASEHEV1Z SCHEMATIC DIAGRAM
EVALUATION BOAR
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ISL70219ASEH Board Layout
FIGURE 7. TOP VIEW
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Typical Performance Curves
80
80
ACL1000
ACL1000
60
60
ACL100
GAIN (dB)
GAIN (dB)
ACL100
40
40
20
0
ACL10
-20
20
0
ACL10
-20
ACL1
ACL1
-40
-40
-60
100
1k
10k
100k
1M
-60
100
10M
1k
4
GAIN (dB)
GAIN (dB)
RL = 1kΩ
RL = 10kΩ
0
RL = 500Ω
-4
RL=100Ω
-6
-2
RL = 500Ω
-4
RL = 100Ω
-6
-8
-8
10k
100k
1M
-10
1k
10M
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 11. FREQUENCY RESPONSE vs RL (±18.0V)
FIGURE 10. FREQUENCY RESPONSE vs RL (±5.0V)
10
10
CL = 1000pF
8
CL = 43pF
CL = 470pF
6
4
CL = 220pF
8
CL = 1000pF
6
CL = 470pF
CL = 43pF
4
2
0
CL = 4pF
-2
-4
GAIN (dB)
GAIN (dB)
10M
RL = 5kΩ
2
RL = 1kΩ
-2
CL = 220pF
2
0
CL = 4pF
-2
-4
-6
-6
CL = 150pF
-8
-10
1M
4
RL = 5kΩ
RL = 10kΩ
0
-10
1k
100k
FIGURE 9. FREQUENCY RESPONSE vs ACL (±18.0V)
FIGURE 8. FREQUENCY RESPONSE vs ACL (±5.0V)
2
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
CL = 150pF
-8
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 12. FREQUENCY RESPONSE vs CL (±5.0V)
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-10
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 13. FREQUENCY RESPONSE vs CL (±18.0V)
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2
VS = ±2.25V
SMALL SIGNAL TRANSIENT RESPONSE (mV)
Typical Performance Curves (Continued)
VS = ±5V
0
VS = ±19.8V
GAIN (dB)
-2
VS = ±16.2V
VS = ±18V
VS = ±4.5V
VS = ±5.5V
-4
-6
VS = ±2.5V
-8
-10
VS = ±2.75V
1k
10k
100k
100M
FREQUENCY (Hz)
10M
2.4
40
VS =±5, ±18V
30
RL = 10k
CL = 4pF
AV = +1
VOUT = 50mVP-P
20
10
0
-10
0
VS = ±18V, RL = 2k, 10k
1.2
15
20
25
TIME (µs)
30
35
40
0.4
0
VS = ±5V, RL = 2k, 10k
-0.4
-0.8
CL = 4pF
AV = +1
VOUT = 4VP-P
-1.2
-1.6
-2.0
0
10
20
30
40
50
60
TIME (µs)
0.5
0.4
0.2
0.1
70
80
90
0.0
-75
100
-50
-25
INPUT VOLTAGE LEVEL (V)
0.04
POSITIVE SLEW RATE
NEGATIVE SLEW RATE
0.4
0.3
0.2
0.1
-25
0
25
50
75
TEMPERATURE (°C)
100
125
FIGURE 18. SLEW RATE vs TEMPERATURE VS = ±18V
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50
75
100
125
150
INPUT
0
-0.04
-55°C
-0.08
-0.12
+25°C
-0.16
-0.20
-50
25
FIGURE 17. SLEW RATE vs TEMPERATURE VS = ±5V
0.7
-75
0
TEMPERATURE (°C)
0.08
0.5
NEGATIVE SLEW RATE
0.3
0.8
0.6
POSITIVE SLEW RATE
0.6
0.8
FIGURE 16. LARGE SIGNAL TRANSIENT RESPONSE (+25°C)
SLEW RATE (V/µs)
10
0.7
1.6
0
5
0.8
2.0
SLEW RATE (V/µs)
LARGE SIGNAL TRANSIENT RESPONSE (V)
50
FIGURE 15. SMALL SIGNAL TRANSIENT RESPONSE (+25°C)
FIGURE 14. FREQUENCY RESPONSE vs SUPPLY VOLTAGE (+25°C)
-2.4
60
150
-0.24
+125°C
0
10
20
30
40
50
60
70
80
90
TIME (µs)
FIGURE 19. ±18V POSITIVE SATURATION RECOVERY TIME (+25°C)
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Typical Performance Curves (Continued)
0.04
0.24
INPUT VOLTAGE LEVEL (V)
INPUT VOLTAGE LEVEL (V)
+25°C
0.16
0.12
0.08
-55°C
INPUT
0.04
0
-0.04
INPUT
-0.08
-55°C
-0.12
-0.16
+25°C
-0.20
-0.24
-0.04
-0.08
+125°C
0
+125°C
0.20
0
10
20
30
40
50
60
70
80
90
-0.28
0
10
20
30
TIME (µs)
FIGURE 20. ±18V NEGATIVE SATURATION RECOVERY TIME (+25°C)
40
50
TIME (µs)
60
70
80
90
FIGURE 21. ±5V POSITIVE SATURATION RECOVERY TIME (+25°C)
0.28
INPUT VOLTAGE LEVEL (V)
0.24
INPUT
0.20
-55°C
0.16
0.12
0.08 +25°C
+125°C
0.04
0
-0.04
0
10
20
30
40
50
TIME (µs)
60
70
80
90
FIGURE 22. ±5V NEGATIVE SATURATION RECOVERY TIME (+25°C)
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is
cautioned to verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
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