5962-14226

REVISIONS
LTR
DESCRIPTION
A
DATE (YR-MO-DA)
APPROVED
15-01-26
C. SAFFLE
Add device type 02, case outline Y, and figure A-2. - ro
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OF SHEETS
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PMIC N/A
PREPARED BY
RICK OFFICER
STANDARD
MICROCIRCUIT
DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil
CHECKED BY
RAJESH PITHADIA
APPROVED BY
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
CHARLES F. SAFFLE
DRAWING APPROVAL DATE
14-09-02
REVISION LEVEL
A
MICROCIRCUIT, LINEAR, PRECISION LOW
POWER OPERATIONAL AMPLIFIERS,
MONOLITHIC SILICON
SIZE
CAGE CODE
A
67268
SHEET
DSCC FORM 2233
APR 97
5962-14226
1 OF 27
5962-E065-15
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q) and
space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or
Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
F
14226
Federal
stock class
designator
\
RHA
designator
(see 1.2.1)
01
V
X
C
Device
type
(see 1.2.2)
Device
class
designator
(see 1.2.3)
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
/
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
01
02
Generic number
Circuit function
ISL70419SEH
ISL70219ASEH
Quad, precision low power operational amplifier
Dual, precision low power operational amplifier
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class
Device requirements documentation
Q or V
Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
X
Y
Descriptive designator
Terminals
See figure 1
CDFP3-F10
14
10
Package style
Flat pack
Flat pack
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-14226
A
REVISION LEVEL
A
SHEET
2
1.3 Absolute maximum ratings. 1/
Supply voltage (VS) ....................................................................................................... 42 V
2
Supply voltage (LET = 86.4 MeV/cm /mg) ....................................................................
Different input current ...................................................................................................
Differential input voltage ...............................................................................................
Input voltage (VIN) ........................................................................................................
36 V
20 mA
20 V
-VS - 0.5 V to +VS + 0.5 V
Input current for input voltage (  +VS or  -VS ) .......................................................... 20 mA
Output short circuit duration ( 1 output at a time) .......................................................... Indefinite
Power dissipation (PD) :
Case outline X:
TA = +125C .......................................................................................................... 714 mW
TA = +25C ............................................................................................................ 3.571 W
Case outline Y:
TA = +125C .......................................................................................................... 625 mW
TA = +25C ............................................................................................................ 3.125 W
Maximum junction temperature (TJ) ..............................................................................
Lead temperature (soldering, 10 seconds) ....................................................................
Storage temperature range ...........................................................................................
Thermal resistance, junction-to-case (JC) :
Case outlines X and Y ...............................................................................................
Thermal resistance, junction-to-ambient (JA) :
Case outline X ...........................................................................................................
Case outline Y ...........................................................................................................
Electrostatic discharge (ESD) rating:
Human body model (HBM) ........................................................................................
Machine model (MM) .................................................................................................
Charge device model (CDM) .....................................................................................
+150C
+300C
-65C to +150C
8C/W 2/
35C/W 3/
40C/W 3/
2 kV
200 V
750 V
1.4 Recommended operating conditions.
Supply voltage (VS) :
Device type 01 ........................................................................................................... 10 V (5 V) to 30 V (15 V)
Device type 02 ........................................................................................................... 4.5 V (2.25 V) to 36 V (18 V)
Ambient operating temperature range (TA) ................................................................... -55C to +125C
______
1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
2/ For JC, the “case temperature” location is the center of the package underside.
3/
JA is measured in free air with the component mounted on a high effective thermal conductivity test board with
“direct attach” features.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-14226
A
REVISION LEVEL
A
SHEET
3
1.5 Radiation features.
Maximum total dose available (dose rate = 50 – 300 rads(Si)/s) .................................. 300 krads(Si) 4/
Maximum total dose available (dose rate  0.010 rad(Si)/s) ......................................... 50 krads(Si) 4/
Single event phenomenon (SEP):
2
No Single event latchup (SEL) occurs at effective LET (see 4.4.4.2) ......................... ≤ 86 MeV/mg/cm 5/
2
No Single event burnout (SEB) occurs at effective LET (see 4.4.4.2) ........................ ≤ 86 MeV/mg/cm 5/
Single event transient (SET) observed that resulted in a recovery
time not exceeding 10 s (device type 01) and 15 s (device type 02) at
-3
2
2
saturated cross section = 1.22 x 10 cm with effective LET (see 4.4.4.2) .......... 60 MeV/mg/cm
5/
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 MIL-STD-1835 -
Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 MIL-HDBK-780 -
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Copies of these documents are available online at http://quicksearch.dla.mil or from the Standardization Document Order
Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.
Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract.
ASTM INTERNATIONAL (ASTM)
ASTM F1192
-
Standard Guide for the Measurement of Single Event Phenomena (SEP) from Heavy Ion
Irradiation of semiconductor Devices.
(Copies of these documents are available online at http://www.astm.org or from ASTM International, 100 Barr Harbor Drive,
P.O. Box C700, West Conshohocken, PA, 19428-2959).
2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
_______
4/ Device radiation end point limits for the noted parameters are guaranteed only for the conditions as specified in
MIL-STD-883, method 1019, condition A to a maximum total dose of 300 krads(Si), and condition D to a maximum total
dose of 50 krads(Si).
5/ Limits are characterized at initial qualification and after any design or process changes which may affect the SEP
characteristics but are not production tested unless specified by the customer through the purchase order or contract.
See manufacturer’s SEE test report for more information.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-14226
A
REVISION LEVEL
A
SHEET
4
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 as specified herein, or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein.
3.1.1 Microcircuit die. For the requirements of microcircuit die, see appendix A to this document.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and herein for device classes Q and V.
3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.3 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document
revision level control and shall be made available to the preparing and acquiring activity upon request.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the
full ambient operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical
tests for each subgroup are defined in table IA.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance
submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the
manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall
be provided with each lot of microcircuits delivered to this drawing.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-14226
A
REVISION LEVEL
A
SHEET
5
TABLE IA. Electrical performance characteristics.
Test
Symbol
Group A
subgroups
Conditions 1/ 2/
-55C  TA +125C
Device
type
Limits
device type 01, VS = 15 V,
Min
Unit
Max
device type 02, VS = 18 V
unless otherwise specified
Offset voltage
1
VOS
M,D,P,L,R,F
Input bias current
M,D,P,L,R,F
Input offset current
M,D,P,L,R,F
Input voltage range
VCM
110
1
110
-2.5
2.5
2,3
-5
5
1
-15
15
-2.5
2.5
2,3
-3
3
1
-10
10
01
-13
13
02
-16
16
1
IOS
Guaranteed by CMRR test
85
2,3
1
IIB
01, 02
1,2,3
01, 02
01, 02
V
nA
nA
V
Common mode rejection ratio
CMRR
VCM = -13 V to +13 V
1,2,3
01, 02
120
dB
Power supply rejection ratio
PSRR
VS = 2.25 V to 20 V
1,2,3
01, 02
120
dB
Open loop gain
AVOL
VO = -13 V to +13 V,
4,5,6
01, 02
3,000
1
01, 02
VS - 1.5
V/mV
RL = 10 k to ground
Output voltage high
VOH
RL = 10 k to ground
M,D,P,L,R,F
RL = 2 k to ground
M,D,P,L,R,F
Output voltage low
VOL
2, 3
VS - 1.8
1
VS - 1.8
1
VS - 1.7
2, 3
VS – 2.0
1
VS – 2.0
1
RL = 10 k to ground
M,D,P,L,R,F
RL = 2 k to ground
M,D,P,L,R,F
01, 02
V
-VS + 1.5 V
2, 3
-VS + 1.8
1
-VS + 1.8
1
-VS + 1.7
2, 3
-VS + 2.0
1
-VS + 2.0
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-14226
A
REVISION LEVEL
A
SHEET
6
TABLE IA. Electrical performance characteristics - Continued.
Test
Symbol
Group A
subgroups
Conditions 1/ 2/
-55C  TA +125C
Device
type
device type 01, VS = 15 V,
Limits
Min
Unit
Max
device type 02, VS = 18 V
unless otherwise specified
Supply current / amplifier
1
IS
M,D,P,L,R,F
Supply voltage range
VS
Guaranteed by PSRR
SR
AV = 1, RL = 2 k,
0.53
2, 3
0.68
1
0.68
1
M,D,P,L,R,F
01
02
mA
0.725
2, 3
0.85
1
0.85
1,2,3
01, 02
2.25
4
01, 02
0.3
20
V
Transient response
Slew rate, VOUT 20% to 80%
VO = 4 VPP
M,D,P,L,R,F
Rise time,
tr
10% to 90% of VOUT
RL = 10 k to VCM
tf
90% to 10% of VOUT
RL = 10 k to VCM
+OS
1
0.2
AV = 1, VOUT = 10 VP-P,
01, 02
450
5,6
625
4
625
4
AV = 1, VOUT = 50 mVP-P,
M,D,P,L,R,F
Positive overshoot
0.2
4
AV = 1, VOUT = 50 mVP-P,
M,D,P,L,R,F
Fall time,
5,6
V/s
01, 02
600
5,6
700
4
700
ns
ns
4,5,6
01, 02
33
%
4,5,6
01, 02
33
%
Rf = 0 , RL = 2 k to VCM
Negative overshoot
-OS
AV = 1, VOUT = 10 VP-P,
Rf = 0 , RL = 2 k to VCM
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-14226
A
REVISION LEVEL
A
SHEET
7
TABLE IA. Electrical performance characteristics - Continued.
Test
Symbol
Group A
subgroups
Conditions 1/ 2/
-55C  TA +125C
Device
type
VS = 5 V,
unless otherwise specified
Offset voltage
M,D,P,L,R,F
Input bias current
M,D,P,L,R,F
Max
150
250
1
250
-2.5
2.5
2,3
-5
5
1
-15
15
-2.5
2.5
2,3
-3
3
1
-10
10
3
1
IOS
01, 02
Unit
2,3
1
IIB
M,D,P,L,R,F
Input offset current
Min
1
VOS
Limits
01, 02
01, 02
V
nA
nA
Input voltage range
VCM
Guaranteed by CMRR test
1,2,3
01, 02
-3
V
Common mode rejection ratio
CMRR
VCM = -3 V to +3 V
1,2,3
01, 02
120
dB
Power supply rejection ratio
PSRR
VS = 2.25 V to 5 V
1,2,3
01, 02
120
dB
Open loop gain
AVOL
VO = -3 V to +3 V,
4,5,6
01, 02
3,000
1
01, 02
3.5
V/mV
RL = 10 k to ground
Output voltage high
VOH
RL = 10 k to ground
M,D,P,L,R,F
RL = 2 k to ground
M,D,P,L,R,F
Output voltage low
VOL
2, 3
3.2
1
3.2
1
3.3
2, 3
3.0
1
3.0
1
RL = 10 k to ground
M,D,P,L,R,F
RL = 2 k to ground
M,D,P,L,R,F
01, 02
V
-3.5
2, 3
-3.2
1
-3.2
1
-3.3
2, 3
-3.0
1
-3.0
V
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-14226
A
REVISION LEVEL
A
SHEET
8
TABLE IA. Electrical performance characteristics - Continued.
Test
Symbol
Group A
subgroups
Conditions 1/ 2/
-55C  TA +125C
Device
type
VS = 5 V,
unless otherwise specified
Supply current / amplifier
Min
1
IS
M,D,P,L,R,F
01
Unit
Max
0.625
2, 3
0.75
1
0.75
1
M,D,P,L,R,F
Limits
02
mA
0.675
2, 3
0.8
1
0.8
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-14226
A
REVISION LEVEL
A
SHEET
9
TABLE IA. Electrical performance characteristics - Continued.
Test
Symbol
Group A
subgroups
Conditions 1/ 2/
-55C  TA +125C
Device
type
VS = 2.25 V
unless otherwise specified
Offset voltage
M,D,P,L,R,F
Input bias current
M,D,P,L,R,F
Max
150
250
1
250
-2.5
2.5
2,3
-5
5
1
-15
15
-2.5
2.5
2,3
-3
3
1
-10
10
0.25
1
IOS
02
Unit
2,3
1
IIB
M,D,P,L,R,F
Input offset current
Min
1
VOS
Limits
02
02
V
nA
nA
Input voltage range
VCM
Guaranteed by CMRR test
1,2,3
02
-0.25
Common mode rejection ratio
CMRR
VCM = -3 V to +3 V
1,2,3
02
90
dB
Output voltage high
VOH
RL = 10 k to ground
1
02
0.8
V
M,D,P,L,R,F
RL = 2 k to ground
M,D,P,L,R,F
Output voltage low
VOL
0.5
1
0.5
1
0.75
2, 3
0.45
1
0.45
1
RL = 10 k to ground
M,D,P,L,R,F
RL = 2 k to ground
M,D,P,L,R,F
Supply current / amplifier
2, 3
M,D,P,L,R,F
-0.8
2, 3
-0.5
1
-0.5
1
-0.75
2, 3
-0.45
1
-0.45
1
IS
02
02
0.675
2, 3
0.8
1
0.8
V
V
mA
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-14226
A
REVISION LEVEL
A
SHEET
10
TABLE IA. Electrical performance characteristics - Continued.
1/
Unless otherwise specified, VCM = 0 V and VO = 0 V.
2/
RHA device types supplied to this drawing will meet all levels M, D, P, L, R, and F of irradiation for condition A and
levels M, D, P, and L for condition D. However, this device type is only tested at the F level in accordance with
MIL-STD-883, method 1019, condition A and tested at the L level in accordance with MIL-STD-883, method 1019,
condition D (see 1.5 herein).
Pre and Post irradiation values are identical unless otherwise specified in Table IA. When performing post irradiation
electrical measurements for any RHA level, TA = +25C.
TABLE IB. SEP test limits. 1/ 2/ 3/
Device
types
SEP
Temperature (TA)
Effective linear energy transfer (LET)
01, 02
No SEL
125C
LET ≤ 86 MeV/mg/cm
No SEB
125C
LET ≤ 86 MeV/mg/cm
SET observed 4/
+25C
LET = 60 MeV/mg/cm
2
2
2
1/ For single event phenomena (SEP) test conditions, see 4.4.4.2 herein.
2/ Technology characterization and model verification supplemented by in-line data
may be used in lieu of end of line testing. Test plan must be approved by the technical
review board and qualifying activity.
3/ Limits are characterized at initial qualification and after any design or process changes
which may affect the SEP characteristics but are not production tested unless specified
by the customer through the purchase order or contract. See manufacturer’s SEE test
report for more information.
4/ Single event transients (SET) observed that resulted in a recovery time not exceeding
-3
2
10 s (device type 01) and 15 s (device type 02) at saturated cross section = 1.22 x 10 cm with
2
effective LET = 60 MeV/mg/cm . See manufacturer’s SEE test report for more information
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-14226
A
REVISION LEVEL
A
SHEET
11
Case X
FIGURE 1. Case outline.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-14226
A
REVISION LEVEL
A
SHEET
12
Case X – continued.
Dimensions
Symbol
Inches
Millimeters
Notes
Min
Max
Min
Max
A
0.085
0.115
2.16
2.92
b
0.015
0.022
0.38
0.56
c
0.004
0.009
0.10
0.23
D
0.376
0.390
9.55
9.91
e
0.050 BSC
1.27 BSC
E
0.248
0.260
6.30
6.60
E2
0.167
0.183
4.24
4.65
E3
0.03
---
0.76
---
L
0.270
0.370
6.86
9.40
Q
0.026
0.045
0.66
1.14
5
S1
0.005
---
0.13
---
3
6
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located
within the shaded area shown.
2. The maximum limits of lead dimensions (section A-A) shall be measured at the centroid of the finished lead
surfaces, when solder dip or tin plate lead finish is applied.
3. Measure dimension at all four corners.
4. For bottom brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package
to cover the leads.
5. Dimension shall be measured at the point of exit (beyond the meniscus) of the lead from the body.
Dimension minimum shall be reduced by 0.0015 inch (0.038 mm) maximum when solder dip lead finish is applied.
6. The bottom of the package is solderable metal surface.
7. Controlling dimensions are inch, millimeter dimensions are given for reference only.
FIGURE 1. Case outline - continued.
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REVISION LEVEL
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13
Device type
01
Case outline
X
Terminal
number
Terminal
symbol
1
OUTPUT A
2
-INPUT A
Amplifier A inverting input.
3
+INPUT A
Amplifier A non-inverting input.
4
+VS
5
+INPUT B
Amplifier B non-inverting input.
6
-INPUT B
Amplifier B inverting input.
7
OUTPUT B
Amplifier B output.
8
OUTPUT C
Amplifier C output.
9
-INPUT C
Amplifier C inverting input.
10
+INPUT C
Amplifier C non-inverting input.
11
-VS
12
+INPUT D
Amplifier D non-inverting input.
13
-INPUT D
Amplifier D inverting input.
14
OUTPUT D
Description
Amplifier A output.
Positive power supply.
Negative power supply.
Amplifier D output.
EPAD
None
Unbiased, tied to package lid. The bottom of the
package is a solderable metal surface.
Lid
None
Unbiased, tied to package EPAD.
FIGURE 2. Terminal connections.
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REVISION LEVEL
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14
Device type
02
Case outline
Y
Terminal
number
Terminal
symbol
1
OUTPUT A
2
-INPUT A
Amplifier A inverting input.
3
+INPUT A
Amplifier A non-inverting input.
4
NC
No internal connection.
5
-VS
Negative power supply.
6
LID
Pin connected to lid.
7
+INPUT B
Amplifier B non-inverting input.
8
-INPUT B
Amplifier B inverting input.
9
OUTPUT B
10
+VS
Description
Amplifier A output.
Amplifier B output.
Positive power supply.
FIGURE 2. Terminal connections – continued.
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REVISION LEVEL
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4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection.
4.2.1 Additional criteria for device classes Q and V.
a.
The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
b.
Interim and final electrical test parameters shall be as specified in table IIA herein.
c.
Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections, and as specified herein.
4.4.1 Group A inspection.
a.
Tests shall be as specified in table IIA herein.
b.
Subgroups 7, 8, 9, 10, and 11 in table I, method 5005 of MIL-STD-883 shall be omitted.
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.2.1 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of
MIL-STD-883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
STANDARD
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REVISION LEVEL
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TABLE IIA. Electrical test requirements.
Test requirements
Interim electrical
parameters (see 4.2)
Final electrical
parameters (see 4.2)
Group A test
requirements (see 4.4)
Group C end-point electrical
parameters (see 4.4)
Group D end-point electrical
parameters (see 4.4)
Group E end-point electrical
parameters (see 4.4)
Subgroups
(in accordance with
MIL-PRF-38535, table III)
Device
Device
class Q
class V
1, 4
1, 4
1, 2, 3, 1/
4, 5, 6
1, 2, 3, 4, 5, 6
1, 2, 3, 1/ 2/
4, 5, 6
1, 2, 3, 4, 5, 6
1, 2, 3, 4, 5, 6
1, 4
1, 2, 3, 2/
4, 5, 6
1, 4
1, 4
1, 4
1/ PDA applies to subgroup 1.
2/ Delta limits as specified in table IIB shall be required where specified,
and the delta limits shall be completed with reference to the previous
electrical parameters.
TABLE IIB. Burn-in and operating life test delta parameters. TA = +25C. 1/
Parameters
Symbol
Conditions
VOS
Input bias current
Supply current
Offset voltage
VOS
Offset voltage
Input bias current
Supply current
Min
Max
Units
15 V
Device
types
01
-40
40
V
IIB
15 V
01
-1
1
nA
IS
15 V
01
-500
500
A
18 V
02
-40
40
V
IIB
18 V
02
-1
1
nA
IS
18 V
02
-250
250
A
1/ Deltas are performed at room temperature.
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4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured
(see 3.5 herein).
a.
End-point electrical parameters shall be as specified in table IIA herein.
b.
For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. All device classes must meet the postirradiation end-point
electrical parameter limits as defined in table IA at TA = +25C 5C, after exposure, to the subgroups specified in
table IIA herein.
4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883
method 1019, condition A and as specified herein. In addition, a low dose rate test shall be performed in accordance with
MIL-STD-883 method 1019, condition D and as specified herein.
4.4.4.2 Single event phenomena (SEP). When specified in the purchase order or contract, SEP testing shall be performed on
class V devices. SEP testing shall be performed on the Standard Evaluation Circuit (SEC) or alternate SEP test vehicle as
approved by the qualifying activity at initial qualification and after any design or process changes which may affect the upset or
latchup characteristics. Test four devices with zero failures. ASTM F1192 may be used as a guideline when performing SEP
testing. The recommended test conditions for SEP are as follows:
a.
The ion beam angle of incidence shall be between normal to the die surface and 60 to the normal, inclusive
(i.e. 0  angle  60). No shadowing of the ion beam due to fixturing or package related affects is allowed.
b.
The fluence shall be  100 errors or  10 ions/cm .
c.
The flux shall be between 10 and 10 ions/cm /s.
d.
The particle range shall be  20 micron in silicon.
e.
The test temperature shall be +125C 10% for SEB and SEL.
f.
For SEB test limits, see table IB herein.
7
2
5
2
2
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q and V.
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18
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor
prepared specification or drawing.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform DLA Land and Maritime when a system application requires
configuration control and which SMD's are applicable to that system. DLA Land and Maritime will maintain a record of users and
this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic
devices (FSC 5962) should contact DLA Land and Maritime-VA, telephone (614) 692-8108.
6.4 Comments. Comments on this drawing should be directed to DLA Land and Maritime-VA, Columbus, Ohio 43218-3990,
or telephone (614) 692-0540.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in
MIL-HDBK-103 and QML-38535. The vendors listed in MIL-HDBK-103 and QML-38535 have submitted a certificate of
compliance (see 3.6 herein) to DLA Land and Maritime-VA and have agreed to this drawing.
6.7 Additional information. When applicable, a copy of the following additional data shall be maintained and available from
the device manufacturer:
a. RHA test conditions (SEP).
b. Number of burnouts (SEB).
c. Number of latch-up (SEL).
d. Number of transients (SET).
STANDARD
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-14226
A.1 SCOPE
A.1.1 Scope. This appendix establishes minimum requirements for microcircuit die to be supplied under the Qualified
Manufacturers List (QML) Program. QML microcircuit die meeting the requirements of MIL-PRF-38535 and the manufacturers
approved QM plan for use in monolithic microcircuits, multi-chip modules (MCMs), hybrids, electronic modules, or devices using
chip and wire designs in accordance with MIL-PRF-38534 are specified herein. Two product assurance classes consisting of
military high reliability (device class Q) and space application (device class V) are reflected in the Part or Identification Number
(PIN). When available, a choice of Radiation Hardiness Assurance (RHA) levels are reflected in the PIN.
A.1.2 PIN. The PIN is as shown in the following example:
5962
F
Federal
stock class
designator
\
RHA
designator
(see A.1.2.1)
01
V
9
A
Device
type
(see A.1.2.2)
Device
class
designator
(see A.1.2.3)
Die
code
Die
details
(see A.1.2.4)
14226
/
\/
Drawing number
A.1.2.1 RHA designator. Device classes Q and V RHA identified die meet the MIL-PRF-38535 specified RHA levels. A dash
(-) indicates a non-RHA die.
A.1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
01
02
Generic number
Circuit function
ISL70419SEH
ISL70219ASEH
Quad, precision low power operational amplifier
Dual, precision low power operational amplifier
A.1.2.3 Device class designator.
Device class
Q or V
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SIZE
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REVISION LEVEL
A
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-14226
A.1.2.4 Die details. The die details designation is a unique letter which designates the die's physical dimensions, bonding
pad location(s) and related electrical function(s), interface materials, and other assembly related information, for each product
and variant supplied to this appendix.
A.1.2.4.1 Die physical dimensions.
Die type
Figure number
01
02
A-1
A-2
A.1.2.4.2 Die bonding pad locations and electrical functions.
Die type
Figure number
01
02
A-1
A-2
A.1.2.4.3 Interface materials.
Die type
Figure number
01
02
A-1
A-2
A.1.2.4.4 Assembly related information.
Die type
Figure number
01
02
A-1
A-2
A.1.3 Absolute maximum ratings. See paragraph 1.3 herein for details.
A.1.4 Recommended operating conditions. See paragraph 1.4 herein for details.
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-14226
A.2 APPLICABLE DOCUMENTS.
A.2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a
part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in
the solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARD
MIL-STD-883 - Test Method Standard Microcircuits.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Copies of these documents are available online at http://quicksearch.dla.mil or from the Standardization Document Order
Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
A.2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the
text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
A.3 REQUIREMENTS
A.3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer’s Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein.
A.3.2 Design, construction and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and herein and the manufacturer’s QM plan for device classes Q and V.
A.3.2.1 Die physical dimensions. The die physical dimensions shall be as specified in A.1.2.4.1 and on figure A-1.
A.3.2.2 Die bonding pad locations and electrical functions. The die bonding pad locations and electrical functions shall be as
specified in A.1.2.4.2 and on figure A-1.
A.3.2.3 Interface materials. The interface materials for the die shall be as specified in A.1.2.4.3 and on figure A-1.
A.3.2.4 Assembly related information. The assembly related information shall be as specified in A.1.2.4.4 and on figure A-1.
A.3.2.5 Radiation exposure circuit. The radiation exposure circuit shall be as defined in paragraph 3.2.3 herein.
A.3.3 Electrical performance characteristics and post-irradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and post-irradiation parameter limits are as specified in table IA of the body of this
document.
A.3.4 Electrical test requirements. The wafer probe test requirements shall include functional and parametric testing
sufficient to make the packaged die capable of meeting the electrical performance requirements in table IA.
A.3.5 Marking. As a minimum, each unique lot of die, loaded in single or multiple stack of carriers, for shipment to a
customer, shall be identified with the wafer lot number, the certification mark, the manufacturer’s identification and the PIN listed
in A.1.2 herein. The certification mark shall be a “QML” or “Q” as required by MIL-PRF-38535.
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-14226
A.3.6 Certification of compliance. For device classes Q and V, a certificate of compliance shall be required from a
QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see A.6.4 herein). The certificate of
compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply for this appendix shall
affirm that the manufacturer’s product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and the
requirements herein.
A.3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535
shall be provided with each lot of microcircuit die delivered to this drawing.
A.4 VERIFICATION
A.4.1 Sampling and inspection. For device classes Q and V, die sampling and inspection procedures shall be in accordance
with MIL-PRF-38535 or as modified in the device manufacturer’s Quality Management (QM) plan. The modifications in the QM
plan shall not affect the form, fit, or function as described herein.
A.4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and as defined in the
manufacturer’s QM plan. As a minimum, it shall consist of:
a.
Wafer lot acceptance for class V product using the criteria defined in MIL-STD-883, method 5007.
b.
100% wafer probe (see paragraph A.3.4 herein).
c.
100% internal visual inspection to the applicable class Q or V criteria defined in MIL-STD-883, method 2010 or the
alternate procedures allowed in MIL-STD-883, method 5004.
A.4.3 Conformance inspection.
A.4.3.1 Group E inspection. Group E inspection is required only for parts intended to be identified as radiation assured (see
A.3.5 herein). RHA levels for device classes Q and V shall be as specified in MIL-PRF-38535. End point electrical testing of
packaged die shall be as specified in table IIA herein. Group E tests and conditions are as specified in paragraphs 4.4.4,
4.4.4.1, and 4.4.4.2 herein.
A.5 DIE CARRIER
A.5.1 Die carrier requirements. The requirements for the die carrier shall be accordance with the manufacturer’s QM plan or
as specified in the purchase order by the acquiring activity. The die carrier shall provide adequate physical, mechanical and
electrostatic protection.
A.6 NOTES
A.6.1 Intended use. Microcircuit die conforming to this drawing are intended for use in microcircuits built in accordance with
MIL-PRF-38535 or MIL-PRF-38534 for government microcircuit applications (original equipment), design applications, and
logistics purposes.
A.6.2 Comments. Comments on this appendix should be directed to DLA Land and Maritime -VA, Columbus, Ohio,
43218-3990 or telephone (614)-692-0540.
A.6.3 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
A.6.4 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed within MIL-HDBK-103 and QML-38535 have submitted a certificate of compliance (see A.3.6 herein) to
DLA Land and Maritime -VA and have agreed to this drawing.
STANDARD
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REVISION LEVEL
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-14226
-INPUT A
OUTPUT A
OUTPUT D
-INPUT D
+INPUT A
+INPUT D
+VS
+VS
+INPUT B
+INPUT C
-INPUT B
OUTPUT B
OUTPUT C
-INPUT C
FIGURE A-1. Die bonding pad locations and electrical functions.
STANDARD
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A
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-14226
Pad name
Pad number
Y
(m)
1308.5
dX
(m)
70
dY
(m)
70
Bond wires per
pad
3
X
(m)
-445.5
OUTPUT A
-INPUT A
4
-815
1308.5
70
70
1
+INPUT A
5
-1040.5
1092
70
70
1
+VS
9
-1044
0
70
70
1
+INPUT B
13
-1040.5
-1092
70
70
1
-INPUT B
14
-815
-1308.5
70
70
1
1
OUTPUT B
15
-445.5
-1308.5
70
70
1
OUTPUT C
16
445.5
-1308.5
70
70
1
-INPUT C
17
815
-1308.5
70
70
1
+INPUT C
18
1040.5
-1092
70
70
1
-VS
22
1044
0
70
70
1
+INPUT D
26
1040.5
1092
70
70
1
-INPUT D
1
815
1308.5
70
70
1
OUTPUT D
2
445.5
1308.5
70
70
1
Note: Origin of coordinates is the center of the die.
Die bonding pad locations and electrical functions
Die physical dimensions.
Die size: 2406 μm x 2935 μm (95 mils x 116 mils)
Die thickness: 483 μm ± 25 μm (19 mils ± 1 mil)
Interface materials.
Top metallization: AlCu (99.5%/0.5%)
Thickness: 30 kÅ
Backside metallization: Bare Silicon
Glassivation.
Type: Nitrox
Thickness: 15 kÅ
Substrate: PR40 process: Bonded wafer dielectrically isolated complementary bipolar.
Assembly related information.
Substrate potential: Floating
Special assembly instructions: None
FIGURE A-1. Die bonding pad locations and electrical functions - continued.
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-14226
-INPUT A
OUTPUT A
+INPUT A
+VS
OUTPUT B
-VS
+INPUT B
-INPUT B
FIGURE A-2. Die bonding pad locations and electrical functions.
STANDARD
MICROCIRCUIT DRAWING
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-14226
Pad name
Pad number
Y
(m)
1418.0
dX
(m)
70
dY
(m)
70
Bond wires per
pad
1
X
(m)
2195.0
OUTPUT B
+VS
2
2195.0
2510.0
70
70
1
OUTPUT A
3
709.0
2727.0
70
70
1
-INPUT A
4
339.0
2727.0
70
70
1
+INPUT A
5
114.0
2510.0
70
70
1
-VS
6
114.0
336.0
70
70
1
+INPUT B
7
2195.0
336.0
70
70
1
-INPUT B
8
1970.0
110.0
70
70
1
1
Note: Origin of coordinates is the bottom left corner of the die
Die physical dimensions.
Die size: 2406 μm x 2935 μm (95 mils x 116 mils)
Die thickness: 483 μm ± 25 μm (19 mils ± 1 mil)
Interface materials.
Top metallization: AlCu (99.5%/0.5%)
Thickness: 30 kÅ
Backside metallization: Bare silicon
Glassivation.
Type: Nitrox
Thickness: 15 kÅ
Substrate: PR40 process: Bonded wafer dielectrically isolated complementary bipolar.
Assembly related information.
Substrate potential: Floating
Special assembly instructions: None
FIGURE A-2. Die bonding pad locations and electrical functions - continued.
STANDARD
MICROCIRCUIT DRAWING
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DSCC FORM 2234
APR 97
SIZE
5962-14226
A
REVISION LEVEL
A
SHEET
27
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 15-01-26
Approved sources of supply for SMD 5962-14226 are listed below for immediate acquisition information only and
shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be
revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a
certificate of compliance has been submitted to and accepted by DLA Land and Maritime-VA. This information
bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DLA Land and Maritime
maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962F1422601VXC
34371
ISL70419SEHVF
5962F1422601V9A
34371
ISL70419SEHVX
5962F1422602VYC
34371
ISL70219ASEHVF
5962F1422602V9A
34371
ISL70219ASEHVX
1/ The lead finish shown for each PIN representing
a hermetic package is the most readily available
from the manufacturer listed for that part. If the
desired lead finish is not listed contact the vendor
to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number may not
satisfy the performance requirements of this drawing.
Vendor CAGE
number
34371
Vendor name
and address
Intersil Corporation
1001 Murphy Ranch Road
Milpitas, CA 95035-6803
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.